ClabureDB: Classified Bug-Reports Database

     /* Generated by CIL v. 1.3.7 */
     /* print_CIL_Input is true */
     
     #line 19 "include/asm-generic/int-ll64.h"
     typedef signed char __s8;
     #line 20 "include/asm-generic/int-ll64.h"
     typedef unsigned char __u8;
     #line 22 "include/asm-generic/int-ll64.h"
     typedef short __s16;
    #line 23 "include/asm-generic/int-ll64.h"
    typedef unsigned short __u16;
    #line 25 "include/asm-generic/int-ll64.h"
    typedef int __s32;
    #line 26 "include/asm-generic/int-ll64.h"
    typedef unsigned int __u32;
    #line 29 "include/asm-generic/int-ll64.h"
    typedef long long __s64;
    #line 30 "include/asm-generic/int-ll64.h"
    typedef unsigned long long __u64;
    #line 43 "include/asm-generic/int-ll64.h"
    typedef unsigned char u8;
    #line 46 "include/asm-generic/int-ll64.h"
    typedef unsigned short u16;
    #line 48 "include/asm-generic/int-ll64.h"
    typedef int s32;
    #line 49 "include/asm-generic/int-ll64.h"
    typedef unsigned int u32;
    #line 51 "include/asm-generic/int-ll64.h"
    typedef long long s64;
    #line 52 "include/asm-generic/int-ll64.h"
    typedef unsigned long long u64;
    #line 11 "include/asm-generic/types.h"
    typedef unsigned short umode_t;
    #line 11 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef unsigned int __kernel_mode_t;
    #line 12 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef unsigned long __kernel_nlink_t;
    #line 13 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef long __kernel_off_t;
    #line 14 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef int __kernel_pid_t;
    #line 16 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef unsigned int __kernel_uid_t;
    #line 17 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef unsigned int __kernel_gid_t;
    #line 18 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef unsigned long __kernel_size_t;
    #line 19 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef long __kernel_ssize_t;
    #line 21 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef long __kernel_time_t;
    #line 22 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef long __kernel_suseconds_t;
    #line 23 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef long __kernel_clock_t;
    #line 24 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef int __kernel_timer_t;
    #line 25 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef int __kernel_clockid_t;
    #line 32 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef long long __kernel_loff_t;
    #line 41 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef __kernel_uid_t __kernel_uid32_t;
    #line 42 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/posix_types_64.h"
    typedef __kernel_gid_t __kernel_gid32_t;
    #line 21 "include/linux/types.h"
    typedef __u32 __kernel_dev_t;
    #line 24 "include/linux/types.h"
    typedef __kernel_dev_t dev_t;
    #line 26 "include/linux/types.h"
    typedef __kernel_mode_t mode_t;
    #line 27 "include/linux/types.h"
    typedef __kernel_nlink_t nlink_t;
    #line 28 "include/linux/types.h"
    typedef __kernel_off_t off_t;
    #line 29 "include/linux/types.h"
    typedef __kernel_pid_t pid_t;
    #line 34 "include/linux/types.h"
    typedef __kernel_clockid_t clockid_t;
    #line 37 "include/linux/types.h"
    typedef _Bool bool;
    #line 39 "include/linux/types.h"
    typedef __kernel_uid32_t uid_t;
    #line 40 "include/linux/types.h"
    typedef __kernel_gid32_t gid_t;
    #line 53 "include/linux/types.h"
    typedef __kernel_loff_t loff_t;
    #line 62 "include/linux/types.h"
    typedef __kernel_size_t size_t;
    #line 67 "include/linux/types.h"
    typedef __kernel_ssize_t ssize_t;
    #line 77 "include/linux/types.h"
    typedef __kernel_time_t time_t;
    #line 110 "include/linux/types.h"
    typedef __s32 int32_t;
    #line 114 "include/linux/types.h"
    typedef __u8 uint8_t;
    #line 115 "include/linux/types.h"
    typedef __u16 uint16_t;
   #line 116 "include/linux/types.h"
   typedef __u32 uint32_t;
   #line 119 "include/linux/types.h"
   typedef __u64 uint64_t;
   #line 141 "include/linux/types.h"
   typedef unsigned long sector_t;
   #line 142 "include/linux/types.h"
   typedef unsigned long blkcnt_t;
   #line 154 "include/linux/types.h"
   typedef u64 dma_addr_t;
   #line 201 "include/linux/types.h"
   typedef unsigned int gfp_t;
   #line 202 "include/linux/types.h"
   typedef unsigned int fmode_t;
   #line 205 "include/linux/types.h"
   typedef u64 phys_addr_t;
   #line 210 "include/linux/types.h"
   typedef phys_addr_t resource_size_t;
   #line 214 "include/linux/types.h"
   struct __anonstruct_atomic_t_6 {
      int counter ;
   };
   #line 214 "include/linux/types.h"
   typedef struct __anonstruct_atomic_t_6 atomic_t;
   #line 219 "include/linux/types.h"
   struct __anonstruct_atomic64_t_7 {
      long counter ;
   };
   #line 219 "include/linux/types.h"
   typedef struct __anonstruct_atomic64_t_7 atomic64_t;
   #line 220 "include/linux/types.h"
   struct list_head {
      struct list_head *next ;
      struct list_head *prev ;
   };
   #line 225
   struct hlist_node;
   #line 225
   struct hlist_node;
   #line 225 "include/linux/types.h"
   struct hlist_head {
      struct hlist_node *first ;
   };
   #line 229 "include/linux/types.h"
   struct hlist_node {
      struct hlist_node *next ;
      struct hlist_node **pprev ;
   };
   #line 58 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/alternative.h"
   struct module;
   #line 58
   struct module;
   #line 145 "include/linux/init.h"
   typedef void (*ctor_fn_t)(void);
   #line 48 "include/linux/dynamic_debug.h"
   struct bug_entry {
      int bug_addr_disp ;
      int file_disp ;
      unsigned short line ;
      unsigned short flags ;
   };
   #line 70 "include/asm-generic/bug.h"
   struct completion;
   #line 70
   struct completion;
   #line 71
   struct pt_regs;
   #line 71
   struct pt_regs;
   #line 321 "include/linux/kernel.h"
   struct pid;
   #line 321
   struct pid;
   #line 671
   struct timespec;
   #line 671
   struct timespec;
   #line 672
   struct compat_timespec;
   #line 672
   struct compat_timespec;
   #line 673 "include/linux/kernel.h"
   struct __anonstruct_futex_9 {
      u32 *uaddr ;
      u32 val ;
      u32 flags ;
      u32 bitset ;
      u64 time ;
      u32 *uaddr2 ;
   };
   #line 673 "include/linux/kernel.h"
   struct __anonstruct_nanosleep_10 {
      clockid_t clockid ;
      struct timespec *rmtp ;
      struct compat_timespec *compat_rmtp ;
      u64 expires ;
   };
   #line 673
   struct pollfd;
   #line 673
   struct pollfd;
   #line 673 "include/linux/kernel.h"
   struct __anonstruct_poll_11 {
      struct pollfd *ufds ;
      int nfds ;
      int has_timeout ;
      unsigned long tv_sec ;
      unsigned long tv_nsec ;
   };
   #line 673 "include/linux/kernel.h"
   union __anonunion_ldv_2052_8 {
      struct __anonstruct_futex_9 futex ;
      struct __anonstruct_nanosleep_10 nanosleep ;
      struct __anonstruct_poll_11 poll ;
   };
   #line 673 "include/linux/kernel.h"
   struct restart_block {
      long (*fn)(struct restart_block * ) ;
      union __anonunion_ldv_2052_8 ldv_2052 ;
   };
   #line 59 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/page_types.h"
   struct page;
   #line 59
   struct page;
   #line 21 "include/asm-generic/getorder.h"
   struct task_struct;
   #line 21
   struct task_struct;
   #line 22
   struct exec_domain;
   #line 22
   struct exec_domain;
   #line 23
   struct mm_struct;
   #line 23
   struct mm_struct;
   #line 215 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/segment.h"
   struct pt_regs {
      unsigned long r15 ;
      unsigned long r14 ;
      unsigned long r13 ;
      unsigned long r12 ;
      unsigned long bp ;
      unsigned long bx ;
      unsigned long r11 ;
      unsigned long r10 ;
      unsigned long r9 ;
      unsigned long r8 ;
      unsigned long ax ;
      unsigned long cx ;
      unsigned long dx ;
      unsigned long si ;
      unsigned long di ;
      unsigned long orig_ax ;
      unsigned long ip ;
      unsigned long cs ;
      unsigned long flags ;
      unsigned long sp ;
      unsigned long ss ;
   };
   #line 282 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/ptrace.h"
   struct kernel_vm86_regs {
      struct pt_regs pt ;
      unsigned short es ;
      unsigned short __esh ;
      unsigned short ds ;
      unsigned short __dsh ;
      unsigned short fs ;
      unsigned short __fsh ;
      unsigned short gs ;
      unsigned short __gsh ;
   };
   #line 203 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/vm86.h"
   union __anonunion_ldv_2292_12 {
      struct pt_regs *regs ;
      struct kernel_vm86_regs *vm86 ;
   };
   #line 203 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/vm86.h"
   struct math_emu_info {
      long ___orig_eip ;
      union __anonunion_ldv_2292_12 ldv_2292 ;
   };
   #line 13 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_64_types.h"
   typedef unsigned long pgdval_t;
   #line 14 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_64_types.h"
   typedef unsigned long pgprotval_t;
   #line 18 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_64_types.h"
   struct pgprot {
      pgprotval_t pgprot ;
   };
   #line 190 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   typedef struct pgprot pgprot_t;
   #line 192 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   struct __anonstruct_pgd_t_15 {
      pgdval_t pgd ;
   };
   #line 192 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   typedef struct __anonstruct_pgd_t_15 pgd_t;
   #line 280 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   typedef struct page *pgtable_t;
   #line 288
   struct file;
   #line 288
   struct file;
   #line 303
   struct seq_file;
   #line 303
   struct seq_file;
   #line 335 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   struct __anonstruct_ldv_2526_19 {
      unsigned int a ;
      unsigned int b ;
   };
   #line 335 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   struct __anonstruct_ldv_2541_20 {
      u16 limit0 ;
      u16 base0 ;
      unsigned char base1 ;
      unsigned char type : 4 ;
      unsigned char s : 1 ;
      unsigned char dpl : 2 ;
      unsigned char p : 1 ;
      unsigned char limit : 4 ;
      unsigned char avl : 1 ;
      unsigned char l : 1 ;
      unsigned char d : 1 ;
      unsigned char g : 1 ;
      unsigned char base2 ;
   };
   #line 335 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   union __anonunion_ldv_2542_18 {
      struct __anonstruct_ldv_2526_19 ldv_2526 ;
      struct __anonstruct_ldv_2541_20 ldv_2541 ;
   };
   #line 335 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/pgtable_types.h"
   struct desc_struct {
      union __anonunion_ldv_2542_18 ldv_2542 ;
   };
   #line 122 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/desc_defs.h"
   struct thread_struct;
   #line 122
   struct thread_struct;
   #line 124
   struct cpumask;
   #line 124
   struct cpumask;
   #line 320 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt_types.h"
   struct arch_spinlock;
   #line 320
   struct arch_spinlock;
   #line 304 "include/linux/bitmap.h"
   struct cpumask {
      unsigned long bits[64U] ;
   };
   #line 13 "include/linux/cpumask.h"
   typedef struct cpumask cpumask_t;
   #line 622 "include/linux/cpumask.h"
   typedef struct cpumask *cpumask_var_t;
   #line 90 "include/linux/personality.h"
   struct map_segment;
   #line 90
   struct map_segment;
   #line 90 "include/linux/personality.h"
   struct exec_domain {
      char const   *name ;
      void (*handler)(int  , struct pt_regs * ) ;
      unsigned char pers_low ;
      unsigned char pers_high ;
      unsigned long *signal_map ;
      unsigned long *signal_invmap ;
      struct map_segment *err_map ;
      struct map_segment *socktype_map ;
      struct map_segment *sockopt_map ;
      struct map_segment *af_map ;
      struct module *module ;
      struct exec_domain *next ;
   };
   #line 145 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct seq_operations;
   #line 145
   struct seq_operations;
   #line 277 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct i387_fsave_struct {
      u32 cwd ;
      u32 swd ;
      u32 twd ;
      u32 fip ;
      u32 fcs ;
      u32 foo ;
      u32 fos ;
      u32 st_space[20U] ;
      u32 status ;
   };
   #line 295 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct __anonstruct_ldv_5171_24 {
      u64 rip ;
      u64 rdp ;
   };
   #line 295 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct __anonstruct_ldv_5177_25 {
      u32 fip ;
      u32 fcs ;
      u32 foo ;
      u32 fos ;
   };
   #line 295 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   union __anonunion_ldv_5178_23 {
      struct __anonstruct_ldv_5171_24 ldv_5171 ;
      struct __anonstruct_ldv_5177_25 ldv_5177 ;
   };
   #line 295 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   union __anonunion_ldv_5187_26 {
      u32 padding1[12U] ;
      u32 sw_reserved[12U] ;
   };
   #line 295 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct i387_fxsave_struct {
      u16 cwd ;
      u16 swd ;
      u16 twd ;
      u16 fop ;
      union __anonunion_ldv_5178_23 ldv_5178 ;
      u32 mxcsr ;
      u32 mxcsr_mask ;
      u32 st_space[32U] ;
      u32 xmm_space[64U] ;
      u32 padding[12U] ;
      union __anonunion_ldv_5187_26 ldv_5187 ;
   };
   #line 329 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct i387_soft_struct {
      u32 cwd ;
      u32 swd ;
      u32 twd ;
      u32 fip ;
      u32 fcs ;
      u32 foo ;
      u32 fos ;
      u32 st_space[20U] ;
      u8 ftop ;
      u8 changed ;
      u8 lookahead ;
      u8 no_update ;
      u8 rm ;
      u8 alimit ;
      struct math_emu_info *info ;
      u32 entry_eip ;
   };
   #line 350 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct ymmh_struct {
      u32 ymmh_space[64U] ;
   };
   #line 355 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct xsave_hdr_struct {
      u64 xstate_bv ;
      u64 reserved1[2U] ;
      u64 reserved2[5U] ;
   };
   #line 361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct xsave_struct {
      struct i387_fxsave_struct i387 ;
      struct xsave_hdr_struct xsave_hdr ;
      struct ymmh_struct ymmh ;
   };
   #line 367 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   union thread_xstate {
      struct i387_fsave_struct fsave ;
      struct i387_fxsave_struct fxsave ;
      struct i387_soft_struct soft ;
      struct xsave_struct xsave ;
   };
   #line 375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct fpu {
      union thread_xstate *state ;
   };
   #line 421
   struct kmem_cache;
   #line 421
   struct kmem_cache;
   #line 422
   struct perf_event;
   #line 422
   struct perf_event;
   #line 423 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct thread_struct {
      struct desc_struct tls_array[3U] ;
      unsigned long sp0 ;
      unsigned long sp ;
      unsigned long usersp ;
      unsigned short es ;
      unsigned short ds ;
      unsigned short fsindex ;
      unsigned short gsindex ;
      unsigned long fs ;
      unsigned long gs ;
      struct perf_event *ptrace_bps[4U] ;
      unsigned long debugreg6 ;
      unsigned long ptrace_dr7 ;
      unsigned long cr2 ;
      unsigned long trap_no ;
      unsigned long error_code ;
      struct fpu fpu ;
      unsigned long *io_bitmap_ptr ;
      unsigned long iopl ;
      unsigned int io_bitmap_max ;
   };
   #line 622 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   struct __anonstruct_mm_segment_t_28 {
      unsigned long seg ;
   };
   #line 622 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/processor.h"
   typedef struct __anonstruct_mm_segment_t_28 mm_segment_t;
   #line 23 "include/asm-generic/atomic-long.h"
   typedef atomic64_t atomic_long_t;
   #line 131 "include/asm-generic/atomic-long.h"
   struct thread_info {
      struct task_struct *task ;
      struct exec_domain *exec_domain ;
      __u32 flags ;
      __u32 status ;
      __u32 cpu ;
      int preempt_count ;
      mm_segment_t addr_limit ;
      struct restart_block restart_block ;
      void *sysenter_return ;
      int uaccess_err ;
   };
   #line 8 "include/linux/bottom_half.h"
   struct arch_spinlock {
      unsigned int slock ;
   };
   #line 10 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/spinlock_types.h"
   typedef struct arch_spinlock arch_spinlock_t;
   #line 16 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/spinlock_types.h"
   struct __anonstruct_arch_rwlock_t_29 {
      unsigned int lock ;
   };
   #line 16 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/spinlock_types.h"
   typedef struct __anonstruct_arch_rwlock_t_29 arch_rwlock_t;
   #line 17
   struct lockdep_map;
   #line 17
   struct lockdep_map;
   #line 55 "include/linux/debug_locks.h"
   struct stack_trace {
      unsigned int nr_entries ;
      unsigned int max_entries ;
      unsigned long *entries ;
      int skip ;
   };
   #line 26 "include/linux/stacktrace.h"
   struct lockdep_subclass_key {
      char __one_byte ;
   };
   #line 53 "include/linux/lockdep.h"
   struct lock_class_key {
      struct lockdep_subclass_key subkeys[8U] ;
   };
   #line 59 "include/linux/lockdep.h"
   struct lock_class {
      struct list_head hash_entry ;
      struct list_head lock_entry ;
      struct lockdep_subclass_key *key ;
      unsigned int subclass ;
      unsigned int dep_gen_id ;
      unsigned long usage_mask ;
      struct stack_trace usage_traces[13U] ;
      struct list_head locks_after ;
      struct list_head locks_before ;
      unsigned int version ;
      unsigned long ops ;
      char const   *name ;
      int name_version ;
      unsigned long contention_point[4U] ;
      unsigned long contending_point[4U] ;
   };
   #line 144 "include/linux/lockdep.h"
   struct lockdep_map {
      struct lock_class_key *key ;
      struct lock_class *class_cache[2U] ;
      char const   *name ;
      int cpu ;
      unsigned long ip ;
   };
   #line 187 "include/linux/lockdep.h"
   struct held_lock {
      u64 prev_chain_key ;
      unsigned long acquire_ip ;
      struct lockdep_map *instance ;
      struct lockdep_map *nest_lock ;
      u64 waittime_stamp ;
      u64 holdtime_stamp ;
      unsigned short class_idx : 13 ;
      unsigned char irq_context : 2 ;
      unsigned char trylock : 1 ;
      unsigned char read : 2 ;
      unsigned char check : 2 ;
      unsigned char hardirqs_off : 1 ;
      unsigned short references : 11 ;
   };
   #line 552 "include/linux/lockdep.h"
   struct raw_spinlock {
      arch_spinlock_t raw_lock ;
      unsigned int magic ;
      unsigned int owner_cpu ;
      void *owner ;
      struct lockdep_map dep_map ;
   };
   #line 32 "include/linux/spinlock_types.h"
   typedef struct raw_spinlock raw_spinlock_t;
   #line 33 "include/linux/spinlock_types.h"
   struct __anonstruct_ldv_6059_31 {
      u8 __padding[24U] ;
      struct lockdep_map dep_map ;
   };
   #line 33 "include/linux/spinlock_types.h"
   union __anonunion_ldv_6060_30 {
      struct raw_spinlock rlock ;
      struct __anonstruct_ldv_6059_31 ldv_6059 ;
   };
   #line 33 "include/linux/spinlock_types.h"
   struct spinlock {
      union __anonunion_ldv_6060_30 ldv_6060 ;
   };
   #line 76 "include/linux/spinlock_types.h"
   typedef struct spinlock spinlock_t;
   #line 23 "include/linux/rwlock_types.h"
   struct __anonstruct_rwlock_t_32 {
      arch_rwlock_t raw_lock ;
      unsigned int magic ;
      unsigned int owner_cpu ;
      void *owner ;
      struct lockdep_map dep_map ;
   };
   #line 23 "include/linux/rwlock_types.h"
   typedef struct __anonstruct_rwlock_t_32 rwlock_t;
   #line 110 "include/linux/seqlock.h"
   struct seqcount {
      unsigned int sequence ;
   };
   #line 121 "include/linux/seqlock.h"
   typedef struct seqcount seqcount_t;
   #line 233 "include/linux/seqlock.h"
   struct timespec {
      __kernel_time_t tv_sec ;
      long tv_nsec ;
   };
   #line 18 "include/linux/time.h"
   struct timeval {
      __kernel_time_t tv_sec ;
      __kernel_suseconds_t tv_usec ;
   };
   #line 286 "include/linux/time.h"
   struct kstat {
      u64 ino ;
      dev_t dev ;
      umode_t mode ;
      unsigned int nlink ;
      uid_t uid ;
      gid_t gid ;
      dev_t rdev ;
      loff_t size ;
      struct timespec atime ;
      struct timespec mtime ;
      struct timespec ctime ;
      unsigned long blksize ;
      unsigned long long blocks ;
   };
   #line 49 "include/linux/wait.h"
   struct __wait_queue_head {
      spinlock_t lock ;
      struct list_head task_list ;
   };
   #line 54 "include/linux/wait.h"
   typedef struct __wait_queue_head wait_queue_head_t;
   #line 96 "include/linux/nodemask.h"
   struct __anonstruct_nodemask_t_34 {
      unsigned long bits[16U] ;
   };
   #line 96 "include/linux/nodemask.h"
   typedef struct __anonstruct_nodemask_t_34 nodemask_t;
   #line 640 "include/linux/mmzone.h"
   struct mutex {
      atomic_t count ;
      spinlock_t wait_lock ;
      struct list_head wait_list ;
      struct task_struct *owner ;
      char const   *name ;
      void *magic ;
      struct lockdep_map dep_map ;
   };
   #line 63 "include/linux/mutex.h"
   struct mutex_waiter {
      struct list_head list ;
      struct task_struct *task ;
      void *magic ;
   };
   #line 171
   struct rw_semaphore;
   #line 171
   struct rw_semaphore;
   #line 172 "include/linux/mutex.h"
   struct rw_semaphore {
      long count ;
      spinlock_t wait_lock ;
      struct list_head wait_list ;
      struct lockdep_map dep_map ;
   };
   #line 170 "include/linux/srcu.h"
   struct notifier_block {
      int (*notifier_call)(struct notifier_block * , unsigned long  , void * ) ;
      struct notifier_block *next ;
      int priority ;
   };
   #line 139 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/e820.h"
   struct resource {
      resource_size_t start ;
      resource_size_t end ;
      char const   *name ;
      unsigned long flags ;
      struct resource *parent ;
      struct resource *sibling ;
      struct resource *child ;
   };
   #line 25 "include/linux/ioport.h"
   struct pci_dev;
   #line 25
   struct pci_dev;
   #line 175
   struct device;
   #line 175
   struct device;
   #line 15 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/tsc.h"
   typedef unsigned long long cycles_t;
   #line 312 "include/linux/jiffies.h"
   union ktime {
      s64 tv64 ;
   };
   #line 59 "include/linux/ktime.h"
   typedef union ktime ktime_t;
   #line 99 "include/linux/debugobjects.h"
   struct tvec_base;
   #line 99
   struct tvec_base;
   #line 100 "include/linux/debugobjects.h"
   struct timer_list {
      struct list_head entry ;
      unsigned long expires ;
      struct tvec_base *base ;
      void (*function)(unsigned long  ) ;
      unsigned long data ;
      int slack ;
      int start_pid ;
      void *start_site ;
      char start_comm[16U] ;
      struct lockdep_map lockdep_map ;
   };
   #line 289 "include/linux/timer.h"
   struct hrtimer;
   #line 289
   struct hrtimer;
   #line 290
   enum hrtimer_restart;
   #line 290
   enum hrtimer_restart;
   #line 290
   enum hrtimer_restart;
   #line 301
   struct workqueue_struct;
   #line 301
   struct workqueue_struct;
   #line 302
   struct work_struct;
   #line 302
   struct work_struct;
   #line 45 "include/linux/workqueue.h"
   struct work_struct {
      atomic_long_t data ;
      struct list_head entry ;
      void (*func)(struct work_struct * ) ;
      struct lockdep_map lockdep_map ;
   };
   #line 86 "include/linux/workqueue.h"
   struct delayed_work {
      struct work_struct work ;
      struct timer_list timer ;
   };
   #line 443 "include/linux/workqueue.h"
   struct completion {
      unsigned int done ;
      wait_queue_head_t wait ;
   };
   #line 46 "include/linux/pm.h"
   struct pm_message {
      int event ;
   };
   #line 52 "include/linux/pm.h"
   typedef struct pm_message pm_message_t;
   #line 53 "include/linux/pm.h"
   struct dev_pm_ops {
      int (*prepare)(struct device * ) ;
      void (*complete)(struct device * ) ;
      int (*suspend)(struct device * ) ;
      int (*resume)(struct device * ) ;
      int (*freeze)(struct device * ) ;
      int (*thaw)(struct device * ) ;
      int (*poweroff)(struct device * ) ;
      int (*restore)(struct device * ) ;
      int (*suspend_noirq)(struct device * ) ;
      int (*resume_noirq)(struct device * ) ;
      int (*freeze_noirq)(struct device * ) ;
      int (*thaw_noirq)(struct device * ) ;
      int (*poweroff_noirq)(struct device * ) ;
      int (*restore_noirq)(struct device * ) ;
      int (*runtime_suspend)(struct device * ) ;
      int (*runtime_resume)(struct device * ) ;
      int (*runtime_idle)(struct device * ) ;
   };
   #line 272
   enum rpm_status {
       RPM_ACTIVE = 0,
       RPM_RESUMING = 1,
       RPM_SUSPENDED = 2,
       RPM_SUSPENDING = 3
   } ;
   #line 279
   enum rpm_request {
       RPM_REQ_NONE = 0,
       RPM_REQ_IDLE = 1,
       RPM_REQ_SUSPEND = 2,
       RPM_REQ_AUTOSUSPEND = 3,
       RPM_REQ_RESUME = 4
   } ;
   #line 287
   struct wakeup_source;
   #line 287
   struct wakeup_source;
   #line 288 "include/linux/pm.h"
   struct dev_pm_info {
      pm_message_t power_state ;
      unsigned char can_wakeup : 1 ;
      unsigned char async_suspend : 1 ;
      bool is_prepared ;
      bool is_suspended ;
      spinlock_t lock ;
      struct list_head entry ;
      struct completion completion ;
      struct wakeup_source *wakeup ;
      struct timer_list suspend_timer ;
      unsigned long timer_expires ;
      struct work_struct work ;
      wait_queue_head_t wait_queue ;
      atomic_t usage_count ;
      atomic_t child_count ;
      unsigned char disable_depth : 3 ;
      unsigned char ignore_children : 1 ;
      unsigned char idle_notification : 1 ;
      unsigned char request_pending : 1 ;
      unsigned char deferred_resume : 1 ;
      unsigned char run_wake : 1 ;
      unsigned char runtime_auto : 1 ;
      unsigned char no_callbacks : 1 ;
      unsigned char irq_safe : 1 ;
      unsigned char use_autosuspend : 1 ;
      unsigned char timer_autosuspends : 1 ;
      enum rpm_request request ;
      enum rpm_status runtime_status ;
      int runtime_error ;
      int autosuspend_delay ;
      unsigned long last_busy ;
      unsigned long active_jiffies ;
      unsigned long suspended_jiffies ;
      unsigned long accounting_timestamp ;
      void *subsys_data ;
   };
   #line 469 "include/linux/pm.h"
   struct dev_power_domain {
      struct dev_pm_ops ops ;
   };
   #line 175 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/topology.h"
   struct pci_bus;
   #line 175
   struct pci_bus;
   #line 22 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/mmu.h"
   struct __anonstruct_mm_context_t_99 {
      void *ldt ;
      int size ;
      unsigned short ia32_compat ;
      struct mutex lock ;
      void *vdso ;
   };
   #line 22 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/mmu.h"
   typedef struct __anonstruct_mm_context_t_99 mm_context_t;
   #line 71 "include/asm-generic/iomap.h"
   struct vm_area_struct;
   #line 71
   struct vm_area_struct;
   #line 53 "include/linux/rcupdate.h"
   struct rcu_head {
      struct rcu_head *next ;
      void (*func)(struct rcu_head * ) ;
   };
   #line 841
   struct nsproxy;
   #line 841
   struct nsproxy;
   #line 36 "include/linux/kmod.h"
   struct cred;
   #line 36
   struct cred;
   #line 27 "include/linux/elf.h"
   typedef __u64 Elf64_Addr;
   #line 28 "include/linux/elf.h"
   typedef __u16 Elf64_Half;
   #line 32 "include/linux/elf.h"
   typedef __u32 Elf64_Word;
   #line 33 "include/linux/elf.h"
   typedef __u64 Elf64_Xword;
   #line 202 "include/linux/elf.h"
   struct elf64_sym {
      Elf64_Word st_name ;
      unsigned char st_info ;
      unsigned char st_other ;
      Elf64_Half st_shndx ;
      Elf64_Addr st_value ;
      Elf64_Xword st_size ;
   };
   #line 210 "include/linux/elf.h"
   typedef struct elf64_sym Elf64_Sym;
   #line 444
   struct sock;
   #line 444
   struct sock;
   #line 445
   struct kobject;
   #line 445
   struct kobject;
   #line 446
   enum kobj_ns_type {
       KOBJ_NS_TYPE_NONE = 0,
       KOBJ_NS_TYPE_NET = 1,
       KOBJ_NS_TYPES = 2
   } ;
   #line 452 "include/linux/elf.h"
   struct kobj_ns_type_operations {
      enum kobj_ns_type type ;
      void *(*grab_current_ns)(void) ;
      void const   *(*netlink_ns)(struct sock * ) ;
      void const   *(*initial_ns)(void) ;
      void (*drop_ns)(void * ) ;
   };
   #line 57 "include/linux/kobject_ns.h"
   struct attribute {
      char const   *name ;
      mode_t mode ;
      struct lock_class_key *key ;
      struct lock_class_key skey ;
   };
   #line 33 "include/linux/sysfs.h"
   struct attribute_group {
      char const   *name ;
      mode_t (*is_visible)(struct kobject * , struct attribute * , int  ) ;
      struct attribute **attrs ;
   };
   #line 62 "include/linux/sysfs.h"
   struct bin_attribute {
      struct attribute attr ;
      size_t size ;
      void *private ;
      ssize_t (*read)(struct file * , struct kobject * , struct bin_attribute * , char * ,
                      loff_t  , size_t  ) ;
      ssize_t (*write)(struct file * , struct kobject * , struct bin_attribute * , char * ,
                       loff_t  , size_t  ) ;
      int (*mmap)(struct file * , struct kobject * , struct bin_attribute * , struct vm_area_struct * ) ;
   };
   #line 98 "include/linux/sysfs.h"
   struct sysfs_ops {
      ssize_t (*show)(struct kobject * , struct attribute * , char * ) ;
      ssize_t (*store)(struct kobject * , struct attribute * , char const   * , size_t  ) ;
   };
   #line 116
   struct sysfs_dirent;
   #line 116
   struct sysfs_dirent;
   #line 181 "include/linux/sysfs.h"
   struct kref {
      atomic_t refcount ;
   };
   #line 49 "include/linux/kobject.h"
   struct kset;
   #line 49
   struct kset;
   #line 49
   struct kobj_type;
   #line 49
   struct kobj_type;
   #line 49 "include/linux/kobject.h"
   struct kobject {
      char const   *name ;
      struct list_head entry ;
     struct kobject *parent ;
     struct kset *kset ;
     struct kobj_type *ktype ;
     struct sysfs_dirent *sd ;
     struct kref kref ;
     unsigned char state_initialized : 1 ;
     unsigned char state_in_sysfs : 1 ;
     unsigned char state_add_uevent_sent : 1 ;
     unsigned char state_remove_uevent_sent : 1 ;
     unsigned char uevent_suppress : 1 ;
  };
  #line 109 "include/linux/kobject.h"
  struct kobj_type {
     void (*release)(struct kobject * ) ;
     struct sysfs_ops  const  *sysfs_ops ;
     struct attribute **default_attrs ;
     struct kobj_ns_type_operations  const  *(*child_ns_type)(struct kobject * ) ;
     void const   *(*namespace)(struct kobject * ) ;
  };
  #line 117 "include/linux/kobject.h"
  struct kobj_uevent_env {
     char *envp[32U] ;
     int envp_idx ;
     char buf[2048U] ;
     int buflen ;
  };
  #line 124 "include/linux/kobject.h"
  struct kset_uevent_ops {
     int (* const  filter)(struct kset * , struct kobject * ) ;
     char const   *(* const  name)(struct kset * , struct kobject * ) ;
     int (* const  uevent)(struct kset * , struct kobject * , struct kobj_uevent_env * ) ;
  };
  #line 141 "include/linux/kobject.h"
  struct kset {
     struct list_head list ;
     spinlock_t list_lock ;
     struct kobject kobj ;
     struct kset_uevent_ops  const  *uevent_ops ;
  };
  #line 219
  struct kernel_param;
  #line 219
  struct kernel_param;
  #line 220 "include/linux/kobject.h"
  struct kernel_param_ops {
     int (*set)(char const   * , struct kernel_param  const  * ) ;
     int (*get)(char * , struct kernel_param  const  * ) ;
     void (*free)(void * ) ;
  };
  #line 44 "include/linux/moduleparam.h"
  struct kparam_string;
  #line 44
  struct kparam_string;
  #line 44
  struct kparam_array;
  #line 44
  struct kparam_array;
  #line 44 "include/linux/moduleparam.h"
  union __anonunion_ldv_12924_129 {
     void *arg ;
     struct kparam_string  const  *str ;
     struct kparam_array  const  *arr ;
  };
  #line 44 "include/linux/moduleparam.h"
  struct kernel_param {
     char const   *name ;
     struct kernel_param_ops  const  *ops ;
     u16 perm ;
     u16 flags ;
     union __anonunion_ldv_12924_129 ldv_12924 ;
  };
  #line 59 "include/linux/moduleparam.h"
  struct kparam_string {
     unsigned int maxlen ;
     char *string ;
  };
  #line 65 "include/linux/moduleparam.h"
  struct kparam_array {
     unsigned int max ;
     unsigned int elemsize ;
     unsigned int *num ;
     struct kernel_param_ops  const  *ops ;
     void *elem ;
  };
  #line 404 "include/linux/moduleparam.h"
  struct jump_label_key {
     atomic_t enabled ;
  };
  #line 99 "include/linux/jump_label.h"
  struct tracepoint;
  #line 99
  struct tracepoint;
  #line 100 "include/linux/jump_label.h"
  struct tracepoint_func {
     void *func ;
     void *data ;
  };
  #line 29 "include/linux/tracepoint.h"
  struct tracepoint {
     char const   *name ;
     struct jump_label_key key ;
     void (*regfunc)(void) ;
     void (*unregfunc)(void) ;
     struct tracepoint_func *funcs ;
  };
  #line 84 "include/linux/tracepoint.h"
  struct mod_arch_specific {
  
  };
  #line 127 "include/trace/events/module.h"
  struct kernel_symbol {
     unsigned long value ;
     char const   *name ;
  };
  #line 48 "include/linux/module.h"
  struct module_attribute {
     struct attribute attr ;
     ssize_t (*show)(struct module_attribute * , struct module * , char * ) ;
     ssize_t (*store)(struct module_attribute * , struct module * , char const   * ,
                      size_t  ) ;
     void (*setup)(struct module * , char const   * ) ;
     int (*test)(struct module * ) ;
     void (*free)(struct module * ) ;
  };
  #line 68
  struct module_param_attrs;
  #line 68
  struct module_param_attrs;
  #line 68 "include/linux/module.h"
  struct module_kobject {
     struct kobject kobj ;
     struct module *mod ;
     struct kobject *drivers_dir ;
     struct module_param_attrs *mp ;
  };
  #line 81
  struct exception_table_entry;
  #line 81
  struct exception_table_entry;
  #line 218
  enum module_state {
      MODULE_STATE_LIVE = 0,
      MODULE_STATE_COMING = 1,
      MODULE_STATE_GOING = 2
  } ;
  #line 224 "include/linux/module.h"
  struct module_ref {
     unsigned int incs ;
     unsigned int decs ;
  };
  #line 418
  struct module_sect_attrs;
  #line 418
  struct module_sect_attrs;
  #line 418
  struct module_notes_attrs;
  #line 418
  struct module_notes_attrs;
  #line 418
  struct ftrace_event_call;
  #line 418
  struct ftrace_event_call;
  #line 418 "include/linux/module.h"
  struct module {
     enum module_state state ;
     struct list_head list ;
     char name[56U] ;
     struct module_kobject mkobj ;
     struct module_attribute *modinfo_attrs ;
     char const   *version ;
     char const   *srcversion ;
     struct kobject *holders_dir ;
     struct kernel_symbol  const  *syms ;
     unsigned long const   *crcs ;
     unsigned int num_syms ;
     struct kernel_param *kp ;
     unsigned int num_kp ;
     unsigned int num_gpl_syms ;
     struct kernel_symbol  const  *gpl_syms ;
     unsigned long const   *gpl_crcs ;
     struct kernel_symbol  const  *unused_syms ;
     unsigned long const   *unused_crcs ;
     unsigned int num_unused_syms ;
     unsigned int num_unused_gpl_syms ;
     struct kernel_symbol  const  *unused_gpl_syms ;
     unsigned long const   *unused_gpl_crcs ;
     struct kernel_symbol  const  *gpl_future_syms ;
     unsigned long const   *gpl_future_crcs ;
     unsigned int num_gpl_future_syms ;
     unsigned int num_exentries ;
     struct exception_table_entry *extable ;
     int (*init)(void) ;
     void *module_init ;
     void *module_core ;
     unsigned int init_size ;
     unsigned int core_size ;
     unsigned int init_text_size ;
     unsigned int core_text_size ;
     unsigned int init_ro_size ;
     unsigned int core_ro_size ;
     struct mod_arch_specific arch ;
     unsigned int taints ;
     unsigned int num_bugs ;
     struct list_head bug_list ;
     struct bug_entry *bug_table ;
     Elf64_Sym *symtab ;
     Elf64_Sym *core_symtab ;
     unsigned int num_symtab ;
     unsigned int core_num_syms ;
     char *strtab ;
     char *core_strtab ;
     struct module_sect_attrs *sect_attrs ;
     struct module_notes_attrs *notes_attrs ;
     char *args ;
     void *percpu ;
     unsigned int percpu_size ;
     unsigned int num_tracepoints ;
     struct tracepoint * const  *tracepoints_ptrs ;
     unsigned int num_trace_bprintk_fmt ;
     char const   **trace_bprintk_fmt_start ;
     struct ftrace_event_call **trace_events ;
     unsigned int num_trace_events ;
     unsigned int num_ftrace_callsites ;
     unsigned long *ftrace_callsites ;
     struct list_head source_list ;
     struct list_head target_list ;
     struct task_struct *waiter ;
     void (*exit)(void) ;
     struct module_ref *refptr ;
     ctor_fn_t (**ctors)(void) ;
     unsigned int num_ctors ;
  };
  #line 8 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  struct klist_node;
  #line 8
  struct klist_node;
  #line 37 "include/linux/klist.h"
  struct klist_node {
     void *n_klist ;
     struct list_head n_node ;
     struct kref n_ref ;
  };
  #line 67
  struct dma_map_ops;
  #line 67
  struct dma_map_ops;
  #line 67 "include/linux/klist.h"
  struct dev_archdata {
     void *acpi_handle ;
     struct dma_map_ops *dma_ops ;
     void *iommu ;
  };
  #line 14 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/device.h"
  struct pdev_archdata {
  
  };
  #line 17
  struct device_private;
  #line 17
  struct device_private;
  #line 18
  struct device_driver;
  #line 18
  struct device_driver;
  #line 19
  struct driver_private;
  #line 19
  struct driver_private;
  #line 20
  struct class;
  #line 20
  struct class;
  #line 21
  struct subsys_private;
  #line 21
  struct subsys_private;
  #line 22
  struct bus_type;
  #line 22
  struct bus_type;
  #line 23
  struct device_node;
  #line 23
  struct device_node;
  #line 24 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/device.h"
  struct bus_attribute {
     struct attribute attr ;
     ssize_t (*show)(struct bus_type * , char * ) ;
     ssize_t (*store)(struct bus_type * , char const   * , size_t  ) ;
  };
  #line 49 "include/linux/device.h"
  struct device_attribute;
  #line 49
  struct device_attribute;
  #line 49
  struct driver_attribute;
  #line 49
  struct driver_attribute;
  #line 49 "include/linux/device.h"
  struct bus_type {
     char const   *name ;
     struct bus_attribute *bus_attrs ;
     struct device_attribute *dev_attrs ;
     struct driver_attribute *drv_attrs ;
     int (*match)(struct device * , struct device_driver * ) ;
     int (*uevent)(struct device * , struct kobj_uevent_env * ) ;
     int (*probe)(struct device * ) ;
     int (*remove)(struct device * ) ;
     void (*shutdown)(struct device * ) ;
     int (*suspend)(struct device * , pm_message_t  ) ;
     int (*resume)(struct device * ) ;
     struct dev_pm_ops  const  *pm ;
     struct subsys_private *p ;
  };
  #line 153
  struct of_device_id;
  #line 153
  struct of_device_id;
  #line 153 "include/linux/device.h"
  struct device_driver {
     char const   *name ;
     struct bus_type *bus ;
     struct module *owner ;
     char const   *mod_name ;
     bool suppress_bind_attrs ;
     struct of_device_id  const  *of_match_table ;
     int (*probe)(struct device * ) ;
     int (*remove)(struct device * ) ;
     void (*shutdown)(struct device * ) ;
     int (*suspend)(struct device * , pm_message_t  ) ;
     int (*resume)(struct device * ) ;
     struct attribute_group  const  **groups ;
     struct dev_pm_ops  const  *pm ;
     struct driver_private *p ;
  };
  #line 218 "include/linux/device.h"
  struct driver_attribute {
     struct attribute attr ;
     ssize_t (*show)(struct device_driver * , char * ) ;
     ssize_t (*store)(struct device_driver * , char const   * , size_t  ) ;
  };
  #line 248
  struct class_attribute;
  #line 248
  struct class_attribute;
  #line 248 "include/linux/device.h"
  struct class {
     char const   *name ;
     struct module *owner ;
     struct class_attribute *class_attrs ;
     struct device_attribute *dev_attrs ;
     struct bin_attribute *dev_bin_attrs ;
     struct kobject *dev_kobj ;
     int (*dev_uevent)(struct device * , struct kobj_uevent_env * ) ;
     char *(*devnode)(struct device * , mode_t * ) ;
     void (*class_release)(struct class * ) ;
     void (*dev_release)(struct device * ) ;
     int (*suspend)(struct device * , pm_message_t  ) ;
     int (*resume)(struct device * ) ;
     struct kobj_ns_type_operations  const  *ns_type ;
     void const   *(*namespace)(struct device * ) ;
     struct dev_pm_ops  const  *pm ;
     struct subsys_private *p ;
  };
  #line 305
  struct device_type;
  #line 305
  struct device_type;
  #line 344 "include/linux/device.h"
  struct class_attribute {
     struct attribute attr ;
     ssize_t (*show)(struct class * , struct class_attribute * , char * ) ;
     ssize_t (*store)(struct class * , struct class_attribute * , char const   * , size_t  ) ;
  };
  #line 395 "include/linux/device.h"
  struct device_type {
     char const   *name ;
     struct attribute_group  const  **groups ;
     int (*uevent)(struct device * , struct kobj_uevent_env * ) ;
     char *(*devnode)(struct device * , mode_t * ) ;
     void (*release)(struct device * ) ;
     struct dev_pm_ops  const  *pm ;
  };
  #line 422 "include/linux/device.h"
  struct device_attribute {
     struct attribute attr ;
     ssize_t (*show)(struct device * , struct device_attribute * , char * ) ;
     ssize_t (*store)(struct device * , struct device_attribute * , char const   * ,
                      size_t  ) ;
  };
  #line 483 "include/linux/device.h"
  struct device_dma_parameters {
     unsigned int max_segment_size ;
     unsigned long segment_boundary_mask ;
  };
  #line 492
  struct dma_coherent_mem;
  #line 492
  struct dma_coherent_mem;
  #line 492 "include/linux/device.h"
  struct device {
     struct device *parent ;
     struct device_private *p ;
     struct kobject kobj ;
     char const   *init_name ;
     struct device_type  const  *type ;
     struct mutex mutex ;
     struct bus_type *bus ;
     struct device_driver *driver ;
     void *platform_data ;
     struct dev_pm_info power ;
     struct dev_power_domain *pwr_domain ;
     int numa_node ;
     u64 *dma_mask ;
     u64 coherent_dma_mask ;
     struct device_dma_parameters *dma_parms ;
     struct list_head dma_pools ;
     struct dma_coherent_mem *dma_mem ;
     struct dev_archdata archdata ;
     struct device_node *of_node ;
     dev_t devt ;
     spinlock_t devres_lock ;
     struct list_head devres_head ;
     struct klist_node knode_class ;
     struct class *class ;
     struct attribute_group  const  **groups ;
     void (*release)(struct device * ) ;
  };
  #line 604 "include/linux/device.h"
  struct wakeup_source {
     char *name ;
     struct list_head entry ;
     spinlock_t lock ;
     struct timer_list timer ;
     unsigned long timer_expires ;
     ktime_t total_time ;
     ktime_t max_time ;
     ktime_t last_time ;
     unsigned long event_count ;
     unsigned long active_count ;
     unsigned long relax_count ;
     unsigned long hit_count ;
     unsigned char active : 1 ;
  };
  #line 903
  struct file_operations;
  #line 903
  struct file_operations;
  #line 63 "include/linux/miscdevice.h"
  struct block_device;
  #line 63
  struct block_device;
  #line 92 "include/linux/bit_spinlock.h"
  struct hlist_bl_node;
  #line 92
  struct hlist_bl_node;
  #line 92 "include/linux/bit_spinlock.h"
  struct hlist_bl_head {
     struct hlist_bl_node *first ;
  };
  #line 36 "include/linux/list_bl.h"
  struct hlist_bl_node {
     struct hlist_bl_node *next ;
     struct hlist_bl_node **pprev ;
  };
  #line 114 "include/linux/rculist_bl.h"
  struct nameidata;
  #line 114
  struct nameidata;
  #line 115
  struct path;
  #line 115
  struct path;
  #line 116
  struct vfsmount;
  #line 116
  struct vfsmount;
  #line 117 "include/linux/rculist_bl.h"
  struct qstr {
     unsigned int hash ;
     unsigned int len ;
     unsigned char const   *name ;
  };
  #line 100 "include/linux/dcache.h"
  struct inode;
  #line 100
  struct inode;
  #line 100
  struct dentry_operations;
  #line 100
  struct dentry_operations;
  #line 100
  struct super_block;
  #line 100
  struct super_block;
  #line 100 "include/linux/dcache.h"
  union __anonunion_d_u_130 {
     struct list_head d_child ;
     struct rcu_head d_rcu ;
  };
  #line 100 "include/linux/dcache.h"
  struct dentry {
     unsigned int d_flags ;
     seqcount_t d_seq ;
     struct hlist_bl_node d_hash ;
     struct dentry *d_parent ;
     struct qstr d_name ;
     struct inode *d_inode ;
     unsigned char d_iname[32U] ;
     unsigned int d_count ;
     spinlock_t d_lock ;
     struct dentry_operations  const  *d_op ;
     struct super_block *d_sb ;
     unsigned long d_time ;
     void *d_fsdata ;
     struct list_head d_lru ;
     union __anonunion_d_u_130 d_u ;
     struct list_head d_subdirs ;
     struct list_head d_alias ;
  };
  #line 151 "include/linux/dcache.h"
  struct dentry_operations {
     int (*d_revalidate)(struct dentry * , struct nameidata * ) ;
     int (*d_hash)(struct dentry  const  * , struct inode  const  * , struct qstr * ) ;
     int (*d_compare)(struct dentry  const  * , struct inode  const  * , struct dentry  const  * ,
                      struct inode  const  * , unsigned int  , char const   * , struct qstr  const  * ) ;
     int (*d_delete)(struct dentry  const  * ) ;
     void (*d_release)(struct dentry * ) ;
     void (*d_iput)(struct dentry * , struct inode * ) ;
     char *(*d_dname)(struct dentry * , char * , int  ) ;
     struct vfsmount *(*d_automount)(struct path * ) ;
     int (*d_manage)(struct dentry * , bool  ) ;
  };
  #line 422 "include/linux/dcache.h"
  struct path {
     struct vfsmount *mnt ;
     struct dentry *dentry ;
  };
  #line 51 "include/linux/radix-tree.h"
  struct radix_tree_node;
  #line 51
  struct radix_tree_node;
  #line 51 "include/linux/radix-tree.h"
  struct radix_tree_root {
     unsigned int height ;
     gfp_t gfp_mask ;
     struct radix_tree_node *rnode ;
  };
  #line 229
  struct prio_tree_node;
  #line 229
  struct prio_tree_node;
  #line 229 "include/linux/radix-tree.h"
  struct raw_prio_tree_node {
     struct prio_tree_node *left ;
     struct prio_tree_node *right ;
     struct prio_tree_node *parent ;
  };
  #line 19 "include/linux/prio_tree.h"
  struct prio_tree_node {
     struct prio_tree_node *left ;
     struct prio_tree_node *right ;
     struct prio_tree_node *parent ;
     unsigned long start ;
     unsigned long last ;
  };
  #line 27 "include/linux/prio_tree.h"
  struct prio_tree_root {
     struct prio_tree_node *prio_tree_node ;
     unsigned short index_bits ;
     unsigned short raw ;
  };
  #line 111
  enum pid_type {
      PIDTYPE_PID = 0,
      PIDTYPE_PGID = 1,
      PIDTYPE_SID = 2,
      PIDTYPE_MAX = 3
  } ;
  #line 118
  struct pid_namespace;
  #line 118
  struct pid_namespace;
  #line 118 "include/linux/prio_tree.h"
  struct upid {
     int nr ;
     struct pid_namespace *ns ;
     struct hlist_node pid_chain ;
  };
  #line 56 "include/linux/pid.h"
  struct pid {
     atomic_t count ;
     unsigned int level ;
     struct hlist_head tasks[3U] ;
     struct rcu_head rcu ;
     struct upid numbers[1U] ;
  };
  #line 68 "include/linux/pid.h"
  struct pid_link {
     struct hlist_node node ;
     struct pid *pid ;
  };
  #line 93 "include/linux/capability.h"
  struct kernel_cap_struct {
     __u32 cap[2U] ;
  };
  #line 96 "include/linux/capability.h"
  typedef struct kernel_cap_struct kernel_cap_t;
  #line 104
  struct user_namespace;
  #line 104
  struct user_namespace;
  #line 45 "include/linux/semaphore.h"
  struct fiemap_extent {
     __u64 fe_logical ;
     __u64 fe_physical ;
     __u64 fe_length ;
     __u64 fe_reserved64[2U] ;
     __u32 fe_flags ;
     __u32 fe_reserved[3U] ;
  };
  #line 38 "include/linux/fiemap.h"
  struct export_operations;
  #line 38
  struct export_operations;
  #line 40
  struct iovec;
  #line 40
  struct iovec;
  #line 41
  struct kiocb;
  #line 41
  struct kiocb;
  #line 42
  struct pipe_inode_info;
  #line 42
  struct pipe_inode_info;
  #line 43
  struct poll_table_struct;
  #line 43
  struct poll_table_struct;
  #line 44
  struct kstatfs;
  #line 44
  struct kstatfs;
  #line 426 "include/linux/fs.h"
  struct iattr {
     unsigned int ia_valid ;
     umode_t ia_mode ;
     uid_t ia_uid ;
     gid_t ia_gid ;
     loff_t ia_size ;
     struct timespec ia_atime ;
     struct timespec ia_mtime ;
     struct timespec ia_ctime ;
     struct file *ia_file ;
  };
  #line 119 "include/linux/quota.h"
  struct if_dqinfo {
     __u64 dqi_bgrace ;
     __u64 dqi_igrace ;
     __u32 dqi_flags ;
     __u32 dqi_valid ;
  };
  #line 176 "include/linux/percpu_counter.h"
  struct fs_disk_quota {
     __s8 d_version ;
     __s8 d_flags ;
     __u16 d_fieldmask ;
     __u32 d_id ;
     __u64 d_blk_hardlimit ;
     __u64 d_blk_softlimit ;
     __u64 d_ino_hardlimit ;
     __u64 d_ino_softlimit ;
     __u64 d_bcount ;
     __u64 d_icount ;
     __s32 d_itimer ;
     __s32 d_btimer ;
     __u16 d_iwarns ;
     __u16 d_bwarns ;
     __s32 d_padding2 ;
     __u64 d_rtb_hardlimit ;
     __u64 d_rtb_softlimit ;
     __u64 d_rtbcount ;
     __s32 d_rtbtimer ;
     __u16 d_rtbwarns ;
     __s16 d_padding3 ;
     char d_padding4[8U] ;
  };
  #line 75 "include/linux/dqblk_xfs.h"
  struct fs_qfilestat {
     __u64 qfs_ino ;
     __u64 qfs_nblks ;
     __u32 qfs_nextents ;
  };
  #line 150 "include/linux/dqblk_xfs.h"
  typedef struct fs_qfilestat fs_qfilestat_t;
  #line 151 "include/linux/dqblk_xfs.h"
  struct fs_quota_stat {
     __s8 qs_version ;
     __u16 qs_flags ;
     __s8 qs_pad ;
     fs_qfilestat_t qs_uquota ;
     fs_qfilestat_t qs_gquota ;
     __u32 qs_incoredqs ;
     __s32 qs_btimelimit ;
     __s32 qs_itimelimit ;
     __s32 qs_rtbtimelimit ;
     __u16 qs_bwarnlimit ;
     __u16 qs_iwarnlimit ;
  };
  #line 165
  struct dquot;
  #line 165
  struct dquot;
  #line 185 "include/linux/quota.h"
  typedef __kernel_uid32_t qid_t;
  #line 186 "include/linux/quota.h"
  typedef long long qsize_t;
  #line 189 "include/linux/quota.h"
  struct mem_dqblk {
     qsize_t dqb_bhardlimit ;
     qsize_t dqb_bsoftlimit ;
     qsize_t dqb_curspace ;
     qsize_t dqb_rsvspace ;
     qsize_t dqb_ihardlimit ;
     qsize_t dqb_isoftlimit ;
     qsize_t dqb_curinodes ;
     time_t dqb_btime ;
     time_t dqb_itime ;
  };
  #line 211
  struct quota_format_type;
  #line 211
  struct quota_format_type;
  #line 212 "include/linux/quota.h"
  struct mem_dqinfo {
     struct quota_format_type *dqi_format ;
     int dqi_fmt_id ;
     struct list_head dqi_dirty_list ;
     unsigned long dqi_flags ;
     unsigned int dqi_bgrace ;
     unsigned int dqi_igrace ;
     qsize_t dqi_maxblimit ;
     qsize_t dqi_maxilimit ;
     void *dqi_priv ;
  };
  #line 271 "include/linux/quota.h"
  struct dquot {
     struct hlist_node dq_hash ;
     struct list_head dq_inuse ;
     struct list_head dq_free ;
     struct list_head dq_dirty ;
     struct mutex dq_lock ;
     atomic_t dq_count ;
     wait_queue_head_t dq_wait_unused ;
     struct super_block *dq_sb ;
     unsigned int dq_id ;
     loff_t dq_off ;
     unsigned long dq_flags ;
     short dq_type ;
     struct mem_dqblk dq_dqb ;
  };
  #line 299 "include/linux/quota.h"
  struct quota_format_ops {
     int (*check_quota_file)(struct super_block * , int  ) ;
     int (*read_file_info)(struct super_block * , int  ) ;
     int (*write_file_info)(struct super_block * , int  ) ;
     int (*free_file_info)(struct super_block * , int  ) ;
     int (*read_dqblk)(struct dquot * ) ;
     int (*commit_dqblk)(struct dquot * ) ;
     int (*release_dqblk)(struct dquot * ) ;
  };
  #line 310 "include/linux/quota.h"
  struct dquot_operations {
     int (*write_dquot)(struct dquot * ) ;
     struct dquot *(*alloc_dquot)(struct super_block * , int  ) ;
     void (*destroy_dquot)(struct dquot * ) ;
     int (*acquire_dquot)(struct dquot * ) ;
     int (*release_dquot)(struct dquot * ) ;
     int (*mark_dirty)(struct dquot * ) ;
     int (*write_info)(struct super_block * , int  ) ;
     qsize_t *(*get_reserved_space)(struct inode * ) ;
  };
  #line 324 "include/linux/quota.h"
  struct quotactl_ops {
     int (*quota_on)(struct super_block * , int  , int  , struct path * ) ;
     int (*quota_on_meta)(struct super_block * , int  , int  ) ;
     int (*quota_off)(struct super_block * , int  ) ;
     int (*quota_sync)(struct super_block * , int  , int  ) ;
     int (*get_info)(struct super_block * , int  , struct if_dqinfo * ) ;
     int (*set_info)(struct super_block * , int  , struct if_dqinfo * ) ;
     int (*get_dqblk)(struct super_block * , int  , qid_t  , struct fs_disk_quota * ) ;
     int (*set_dqblk)(struct super_block * , int  , qid_t  , struct fs_disk_quota * ) ;
     int (*get_xstate)(struct super_block * , struct fs_quota_stat * ) ;
     int (*set_xstate)(struct super_block * , unsigned int  , int  ) ;
  };
  #line 340 "include/linux/quota.h"
  struct quota_format_type {
     int qf_fmt_id ;
     struct quota_format_ops  const  *qf_ops ;
     struct module *qf_owner ;
     struct quota_format_type *qf_next ;
  };
  #line 386 "include/linux/quota.h"
  struct quota_info {
     unsigned int flags ;
     struct mutex dqio_mutex ;
     struct mutex dqonoff_mutex ;
     struct rw_semaphore dqptr_sem ;
     struct inode *files[2U] ;
     struct mem_dqinfo info[2U] ;
     struct quota_format_ops  const  *ops[2U] ;
  };
  #line 417
  struct address_space;
  #line 417
  struct address_space;
  #line 418
  struct writeback_control;
  #line 418
  struct writeback_control;
  #line 576 "include/linux/fs.h"
  union __anonunion_arg_133 {
     char *buf ;
     void *data ;
  };
  #line 576 "include/linux/fs.h"
  struct __anonstruct_read_descriptor_t_132 {
     size_t written ;
     size_t count ;
     union __anonunion_arg_133 arg ;
     int error ;
  };
  #line 576 "include/linux/fs.h"
  typedef struct __anonstruct_read_descriptor_t_132 read_descriptor_t;
  #line 579 "include/linux/fs.h"
  struct address_space_operations {
     int (*writepage)(struct page * , struct writeback_control * ) ;
     int (*readpage)(struct file * , struct page * ) ;
     int (*writepages)(struct address_space * , struct writeback_control * ) ;
     int (*set_page_dirty)(struct page * ) ;
     int (*readpages)(struct file * , struct address_space * , struct list_head * ,
                      unsigned int  ) ;
     int (*write_begin)(struct file * , struct address_space * , loff_t  , unsigned int  ,
                        unsigned int  , struct page ** , void ** ) ;
     int (*write_end)(struct file * , struct address_space * , loff_t  , unsigned int  ,
                      unsigned int  , struct page * , void * ) ;
     sector_t (*bmap)(struct address_space * , sector_t  ) ;
     void (*invalidatepage)(struct page * , unsigned long  ) ;
     int (*releasepage)(struct page * , gfp_t  ) ;
     void (*freepage)(struct page * ) ;
     ssize_t (*direct_IO)(int  , struct kiocb * , struct iovec  const  * , loff_t  ,
                          unsigned long  ) ;
     int (*get_xip_mem)(struct address_space * , unsigned long  , int  , void ** , unsigned long * ) ;
     int (*migratepage)(struct address_space * , struct page * , struct page * ) ;
     int (*launder_page)(struct page * ) ;
     int (*is_partially_uptodate)(struct page * , read_descriptor_t * , unsigned long  ) ;
     int (*error_remove_page)(struct address_space * , struct page * ) ;
  };
  #line 630
  struct backing_dev_info;
  #line 630
  struct backing_dev_info;
  #line 631 "include/linux/fs.h"
  struct address_space {
     struct inode *host ;
     struct radix_tree_root page_tree ;
     spinlock_t tree_lock ;
     unsigned int i_mmap_writable ;
     struct prio_tree_root i_mmap ;
     struct list_head i_mmap_nonlinear ;
     struct mutex i_mmap_mutex ;
     unsigned long nrpages ;
     unsigned long writeback_index ;
     struct address_space_operations  const  *a_ops ;
     unsigned long flags ;
     struct backing_dev_info *backing_dev_info ;
     spinlock_t private_lock ;
     struct list_head private_list ;
     struct address_space *assoc_mapping ;
  };
  #line 652
  struct hd_struct;
  #line 652
  struct hd_struct;
  #line 652
  struct gendisk;
  #line 652
  struct gendisk;
  #line 652 "include/linux/fs.h"
  struct block_device {
     dev_t bd_dev ;
     int bd_openers ;
     struct inode *bd_inode ;
     struct super_block *bd_super ;
     struct mutex bd_mutex ;
     struct list_head bd_inodes ;
     void *bd_claiming ;
     void *bd_holder ;
     int bd_holders ;
     bool bd_write_holder ;
     struct list_head bd_holder_disks ;
     struct block_device *bd_contains ;
     unsigned int bd_block_size ;
     struct hd_struct *bd_part ;
     unsigned int bd_part_count ;
     int bd_invalidated ;
     struct gendisk *bd_disk ;
     struct list_head bd_list ;
     unsigned long bd_private ;
     int bd_fsfreeze_count ;
     struct mutex bd_fsfreeze_mutex ;
  };
  #line 723
  struct posix_acl;
  #line 723
  struct posix_acl;
  #line 724
  struct inode_operations;
  #line 724
  struct inode_operations;
  #line 724 "include/linux/fs.h"
  union __anonunion_ldv_15897_134 {
     struct list_head i_dentry ;
     struct rcu_head i_rcu ;
  };
  #line 724
  struct file_lock;
  #line 724
  struct file_lock;
  #line 724
  struct cdev;
  #line 724
  struct cdev;
  #line 724 "include/linux/fs.h"
  union __anonunion_ldv_15923_135 {
     struct pipe_inode_info *i_pipe ;
     struct block_device *i_bdev ;
     struct cdev *i_cdev ;
  };
  #line 724 "include/linux/fs.h"
  struct inode {
     umode_t i_mode ;
     uid_t i_uid ;
     gid_t i_gid ;
     struct inode_operations  const  *i_op ;
     struct super_block *i_sb ;
     spinlock_t i_lock ;
     unsigned int i_flags ;
     unsigned long i_state ;
     void *i_security ;
     struct mutex i_mutex ;
     unsigned long dirtied_when ;
     struct hlist_node i_hash ;
     struct list_head i_wb_list ;
     struct list_head i_lru ;
     struct list_head i_sb_list ;
     union __anonunion_ldv_15897_134 ldv_15897 ;
     unsigned long i_ino ;
     atomic_t i_count ;
     unsigned int i_nlink ;
     dev_t i_rdev ;
     unsigned int i_blkbits ;
     u64 i_version ;
     loff_t i_size ;
     struct timespec i_atime ;
     struct timespec i_mtime ;
     struct timespec i_ctime ;
     blkcnt_t i_blocks ;
     unsigned short i_bytes ;
     struct rw_semaphore i_alloc_sem ;
     struct file_operations  const  *i_fop ;
     struct file_lock *i_flock ;
     struct address_space *i_mapping ;
     struct address_space i_data ;
     struct dquot *i_dquot[2U] ;
     struct list_head i_devices ;
     union __anonunion_ldv_15923_135 ldv_15923 ;
     __u32 i_generation ;
     __u32 i_fsnotify_mask ;
     struct hlist_head i_fsnotify_marks ;
     atomic_t i_readcount ;
     atomic_t i_writecount ;
     struct posix_acl *i_acl ;
     struct posix_acl *i_default_acl ;
     void *i_private ;
  };
  #line 902 "include/linux/fs.h"
  struct fown_struct {
     rwlock_t lock ;
     struct pid *pid ;
     enum pid_type pid_type ;
     uid_t uid ;
     uid_t euid ;
     int signum ;
  };
  #line 910 "include/linux/fs.h"
  struct file_ra_state {
     unsigned long start ;
     unsigned int size ;
     unsigned int async_size ;
     unsigned int ra_pages ;
     unsigned int mmap_miss ;
     loff_t prev_pos ;
  };
  #line 933 "include/linux/fs.h"
  union __anonunion_f_u_136 {
     struct list_head fu_list ;
     struct rcu_head fu_rcuhead ;
  };
  #line 933 "include/linux/fs.h"
  struct file {
     union __anonunion_f_u_136 f_u ;
     struct path f_path ;
     struct file_operations  const  *f_op ;
     spinlock_t f_lock ;
     int f_sb_list_cpu ;
     atomic_long_t f_count ;
     unsigned int f_flags ;
     fmode_t f_mode ;
     loff_t f_pos ;
     struct fown_struct f_owner ;
     struct cred  const  *f_cred ;
     struct file_ra_state f_ra ;
     u64 f_version ;
     void *f_security ;
     void *private_data ;
     struct list_head f_ep_links ;
     struct address_space *f_mapping ;
     unsigned long f_mnt_write_state ;
  };
  #line 1064
  struct files_struct;
  #line 1064
  struct files_struct;
  #line 1064 "include/linux/fs.h"
  typedef struct files_struct *fl_owner_t;
  #line 1065 "include/linux/fs.h"
  struct file_lock_operations {
     void (*fl_copy_lock)(struct file_lock * , struct file_lock * ) ;
     void (*fl_release_private)(struct file_lock * ) ;
  };
  #line 1070 "include/linux/fs.h"
  struct lock_manager_operations {
     int (*fl_compare_owner)(struct file_lock * , struct file_lock * ) ;
     void (*fl_notify)(struct file_lock * ) ;
     int (*fl_grant)(struct file_lock * , struct file_lock * , int  ) ;
     void (*fl_release_private)(struct file_lock * ) ;
     void (*fl_break)(struct file_lock * ) ;
     int (*fl_change)(struct file_lock ** , int  ) ;
  };
  #line 163 "include/linux/nfs.h"
  struct nlm_lockowner;
  #line 163
  struct nlm_lockowner;
  #line 164 "include/linux/nfs.h"
  struct nfs_lock_info {
     u32 state ;
     struct nlm_lockowner *owner ;
     struct list_head list ;
  };
  #line 18 "include/linux/nfs_fs_i.h"
  struct nfs4_lock_state;
  #line 18
  struct nfs4_lock_state;
  #line 19 "include/linux/nfs_fs_i.h"
  struct nfs4_lock_info {
     struct nfs4_lock_state *owner ;
  };
  #line 23
  struct fasync_struct;
  #line 23
  struct fasync_struct;
  #line 23 "include/linux/nfs_fs_i.h"
  struct __anonstruct_afs_138 {
     struct list_head link ;
     int state ;
  };
  #line 23 "include/linux/nfs_fs_i.h"
  union __anonunion_fl_u_137 {
     struct nfs_lock_info nfs_fl ;
     struct nfs4_lock_info nfs4_fl ;
     struct __anonstruct_afs_138 afs ;
  };
  #line 23 "include/linux/nfs_fs_i.h"
  struct file_lock {
     struct file_lock *fl_next ;
     struct list_head fl_link ;
     struct list_head fl_block ;
     fl_owner_t fl_owner ;
     unsigned char fl_flags ;
     unsigned char fl_type ;
     unsigned int fl_pid ;
     struct pid *fl_nspid ;
     wait_queue_head_t fl_wait ;
     struct file *fl_file ;
     loff_t fl_start ;
     loff_t fl_end ;
     struct fasync_struct *fl_fasync ;
     unsigned long fl_break_time ;
     struct file_lock_operations  const  *fl_ops ;
     struct lock_manager_operations  const  *fl_lmops ;
     union __anonunion_fl_u_137 fl_u ;
  };
  #line 1171 "include/linux/fs.h"
  struct fasync_struct {
     spinlock_t fa_lock ;
     int magic ;
     int fa_fd ;
     struct fasync_struct *fa_next ;
     struct file *fa_file ;
     struct rcu_head fa_rcu ;
  };
  #line 1363
  struct file_system_type;
  #line 1363
  struct file_system_type;
  #line 1363
  struct super_operations;
  #line 1363
  struct super_operations;
  #line 1363
  struct xattr_handler;
  #line 1363
  struct xattr_handler;
  #line 1363
  struct mtd_info;
  #line 1363
  struct mtd_info;
  #line 1363 "include/linux/fs.h"
  struct super_block {
     struct list_head s_list ;
     dev_t s_dev ;
     unsigned char s_dirt ;
     unsigned char s_blocksize_bits ;
     unsigned long s_blocksize ;
     loff_t s_maxbytes ;
     struct file_system_type *s_type ;
     struct super_operations  const  *s_op ;
     struct dquot_operations  const  *dq_op ;
     struct quotactl_ops  const  *s_qcop ;
     struct export_operations  const  *s_export_op ;
     unsigned long s_flags ;
     unsigned long s_magic ;
     struct dentry *s_root ;
     struct rw_semaphore s_umount ;
     struct mutex s_lock ;
     int s_count ;
     atomic_t s_active ;
     void *s_security ;
     struct xattr_handler  const  **s_xattr ;
     struct list_head s_inodes ;
     struct hlist_bl_head s_anon ;
     struct list_head *s_files ;
     struct list_head s_dentry_lru ;
     int s_nr_dentry_unused ;
     struct block_device *s_bdev ;
     struct backing_dev_info *s_bdi ;
     struct mtd_info *s_mtd ;
     struct list_head s_instances ;
     struct quota_info s_dquot ;
     int s_frozen ;
     wait_queue_head_t s_wait_unfrozen ;
     char s_id[32U] ;
     u8 s_uuid[16U] ;
     void *s_fs_info ;
     fmode_t s_mode ;
     u32 s_time_gran ;
     struct mutex s_vfs_rename_mutex ;
     char *s_subtype ;
     char *s_options ;
     struct dentry_operations  const  *s_d_op ;
     int cleancache_poolid ;
  };
  #line 1495 "include/linux/fs.h"
  struct fiemap_extent_info {
     unsigned int fi_flags ;
     unsigned int fi_extents_mapped ;
     unsigned int fi_extents_max ;
     struct fiemap_extent *fi_extents_start ;
  };
  #line 1534 "include/linux/fs.h"
  struct file_operations {
     struct module *owner ;
     loff_t (*llseek)(struct file * , loff_t  , int  ) ;
     ssize_t (*read)(struct file * , char * , size_t  , loff_t * ) ;
     ssize_t (*write)(struct file * , char const   * , size_t  , loff_t * ) ;
     ssize_t (*aio_read)(struct kiocb * , struct iovec  const  * , unsigned long  ,
                         loff_t  ) ;
     ssize_t (*aio_write)(struct kiocb * , struct iovec  const  * , unsigned long  ,
                          loff_t  ) ;
     int (*readdir)(struct file * , void * , int (*)(void * , char const   * , int  ,
                                                     loff_t  , u64  , unsigned int  ) ) ;
     unsigned int (*poll)(struct file * , struct poll_table_struct * ) ;
     long (*unlocked_ioctl)(struct file * , unsigned int  , unsigned long  ) ;
     long (*compat_ioctl)(struct file * , unsigned int  , unsigned long  ) ;
     int (*mmap)(struct file * , struct vm_area_struct * ) ;
     int (*open)(struct inode * , struct file * ) ;
     int (*flush)(struct file * , fl_owner_t  ) ;
     int (*release)(struct inode * , struct file * ) ;
     int (*fsync)(struct file * , int  ) ;
     int (*aio_fsync)(struct kiocb * , int  ) ;
     int (*fasync)(int  , struct file * , int  ) ;
     int (*lock)(struct file * , int  , struct file_lock * ) ;
     ssize_t (*sendpage)(struct file * , struct page * , int  , size_t  , loff_t * ,
                         int  ) ;
     unsigned long (*get_unmapped_area)(struct file * , unsigned long  , unsigned long  ,
                                        unsigned long  , unsigned long  ) ;
     int (*check_flags)(int  ) ;
     int (*flock)(struct file * , int  , struct file_lock * ) ;
     ssize_t (*splice_write)(struct pipe_inode_info * , struct file * , loff_t * , size_t  ,
                             unsigned int  ) ;
     ssize_t (*splice_read)(struct file * , loff_t * , struct pipe_inode_info * , size_t  ,
                            unsigned int  ) ;
     int (*setlease)(struct file * , long  , struct file_lock ** ) ;
     long (*fallocate)(struct file * , int  , loff_t  , loff_t  ) ;
  };
  #line 1574 "include/linux/fs.h"
  struct inode_operations {
     struct dentry *(*lookup)(struct inode * , struct dentry * , struct nameidata * ) ;
     void *(*follow_link)(struct dentry * , struct nameidata * ) ;
     int (*permission)(struct inode * , int  , unsigned int  ) ;
     int (*check_acl)(struct inode * , int  , unsigned int  ) ;
     int (*readlink)(struct dentry * , char * , int  ) ;
     void (*put_link)(struct dentry * , struct nameidata * , void * ) ;
     int (*create)(struct inode * , struct dentry * , int  , struct nameidata * ) ;
     int (*link)(struct dentry * , struct inode * , struct dentry * ) ;
     int (*unlink)(struct inode * , struct dentry * ) ;
     int (*symlink)(struct inode * , struct dentry * , char const   * ) ;
     int (*mkdir)(struct inode * , struct dentry * , int  ) ;
     int (*rmdir)(struct inode * , struct dentry * ) ;
     int (*mknod)(struct inode * , struct dentry * , int  , dev_t  ) ;
     int (*rename)(struct inode * , struct dentry * , struct inode * , struct dentry * ) ;
     void (*truncate)(struct inode * ) ;
     int (*setattr)(struct dentry * , struct iattr * ) ;
     int (*getattr)(struct vfsmount * , struct dentry * , struct kstat * ) ;
     int (*setxattr)(struct dentry * , char const   * , void const   * , size_t  , int  ) ;
     ssize_t (*getxattr)(struct dentry * , char const   * , void * , size_t  ) ;
     ssize_t (*listxattr)(struct dentry * , char * , size_t  ) ;
     int (*removexattr)(struct dentry * , char const   * ) ;
     void (*truncate_range)(struct inode * , loff_t  , loff_t  ) ;
     int (*fiemap)(struct inode * , struct fiemap_extent_info * , u64  , u64  ) ;
  };
  #line 1620 "include/linux/fs.h"
  struct super_operations {
     struct inode *(*alloc_inode)(struct super_block * ) ;
     void (*destroy_inode)(struct inode * ) ;
     void (*dirty_inode)(struct inode * , int  ) ;
     int (*write_inode)(struct inode * , struct writeback_control * ) ;
     int (*drop_inode)(struct inode * ) ;
     void (*evict_inode)(struct inode * ) ;
     void (*put_super)(struct super_block * ) ;
     void (*write_super)(struct super_block * ) ;
     int (*sync_fs)(struct super_block * , int  ) ;
     int (*freeze_fs)(struct super_block * ) ;
     int (*unfreeze_fs)(struct super_block * ) ;
     int (*statfs)(struct dentry * , struct kstatfs * ) ;
     int (*remount_fs)(struct super_block * , int * , char * ) ;
     void (*umount_begin)(struct super_block * ) ;
     int (*show_options)(struct seq_file * , struct vfsmount * ) ;
     int (*show_devname)(struct seq_file * , struct vfsmount * ) ;
     int (*show_path)(struct seq_file * , struct vfsmount * ) ;
     int (*show_stats)(struct seq_file * , struct vfsmount * ) ;
     ssize_t (*quota_read)(struct super_block * , int  , char * , size_t  , loff_t  ) ;
     ssize_t (*quota_write)(struct super_block * , int  , char const   * , size_t  ,
                            loff_t  ) ;
     int (*bdev_try_to_free_page)(struct super_block * , struct page * , gfp_t  ) ;
  };
  #line 1801 "include/linux/fs.h"
  struct file_system_type {
     char const   *name ;
     int fs_flags ;
     struct dentry *(*mount)(struct file_system_type * , int  , char const   * , void * ) ;
     void (*kill_sb)(struct super_block * ) ;
     struct module *owner ;
     struct file_system_type *next ;
     struct list_head fs_supers ;
     struct lock_class_key s_lock_key ;
     struct lock_class_key s_umount_key ;
     struct lock_class_key s_vfs_rename_key ;
     struct lock_class_key i_lock_key ;
     struct lock_class_key i_mutex_key ;
     struct lock_class_key i_mutex_dir_key ;
     struct lock_class_key i_alloc_sem_key ;
  };
  #line 118 "include/linux/kmemleak.h"
  struct kmem_cache_cpu {
     void **freelist ;
     unsigned long tid ;
     struct page *page ;
     int node ;
     unsigned int stat[19U] ;
  };
  #line 46 "include/linux/slub_def.h"
  struct kmem_cache_node {
     spinlock_t list_lock ;
     unsigned long nr_partial ;
     struct list_head partial ;
     atomic_long_t nr_slabs ;
     atomic_long_t total_objects ;
     struct list_head full ;
  };
  #line 57 "include/linux/slub_def.h"
  struct kmem_cache_order_objects {
     unsigned long x ;
  };
  #line 67 "include/linux/slub_def.h"
  struct kmem_cache {
     struct kmem_cache_cpu *cpu_slab ;
     unsigned long flags ;
     unsigned long min_partial ;
     int size ;
     int objsize ;
     int offset ;
     struct kmem_cache_order_objects oo ;
     struct kmem_cache_order_objects max ;
     struct kmem_cache_order_objects min ;
     gfp_t allocflags ;
     int refcount ;
     void (*ctor)(void * ) ;
     int inuse ;
     int align ;
     int reserved ;
     char const   *name ;
     struct list_head list ;
     struct kobject kobj ;
     int remote_node_defrag_ratio ;
     struct kmem_cache_node *node[1024U] ;
  };
  #line 46 "include/linux/proc_fs.h"
  typedef int read_proc_t(char * , char ** , off_t  , int  , int * , void * );
  #line 48 "include/linux/proc_fs.h"
  typedef int write_proc_t(struct file * , char const   * , unsigned long  , void * );
  #line 49 "include/linux/proc_fs.h"
  struct proc_dir_entry {
     unsigned int low_ino ;
     unsigned int namelen ;
     char const   *name ;
     mode_t mode ;
     nlink_t nlink ;
     uid_t uid ;
     gid_t gid ;
     loff_t size ;
     struct inode_operations  const  *proc_iops ;
     struct file_operations  const  *proc_fops ;
     struct proc_dir_entry *next ;
     struct proc_dir_entry *parent ;
     struct proc_dir_entry *subdir ;
     void *data ;
     read_proc_t *read_proc ;
     write_proc_t *write_proc ;
     atomic_t count ;
     int pde_users ;
     spinlock_t pde_unload_lock ;
     struct completion *pde_unload_completion ;
     struct list_head pde_openers ;
  };
  #line 121
  struct tty_driver;
  #line 121
  struct tty_driver;
  #line 12 "include/linux/mod_devicetable.h"
  typedef unsigned long kernel_ulong_t;
  #line 13 "include/linux/mod_devicetable.h"
  struct pci_device_id {
     __u32 vendor ;
     __u32 device ;
     __u32 subvendor ;
     __u32 subdevice ;
     __u32 class ;
     __u32 class_mask ;
     kernel_ulong_t driver_data ;
  };
  #line 215 "include/linux/mod_devicetable.h"
  struct of_device_id {
     char name[32U] ;
     char type[32U] ;
     char compatible[128U] ;
     void *data ;
  };
  #line 474 "include/linux/mod_devicetable.h"
  struct platform_device_id {
     char name[20U] ;
     kernel_ulong_t driver_data ;
  };
  #line 535
  struct mfd_cell;
  #line 535
  struct mfd_cell;
  #line 536 "include/linux/mod_devicetable.h"
  struct platform_device {
     char const   *name ;
     int id ;
     struct device dev ;
     u32 num_resources ;
     struct resource *resource ;
     struct platform_device_id  const  *id_entry ;
     struct mfd_cell *mfd_cell ;
     struct pdev_archdata archdata ;
  };
  #line 69 "include/linux/io.h"
  enum irqreturn {
      IRQ_NONE = 0,
      IRQ_HANDLED = 1,
      IRQ_WAKE_THREAD = 2
  } ;
  #line 16 "include/linux/irqreturn.h"
  typedef enum irqreturn irqreturn_t;
  #line 17
  struct hotplug_slot;
  #line 17
  struct hotplug_slot;
  #line 17 "include/linux/irqreturn.h"
  struct pci_slot {
     struct pci_bus *bus ;
     struct list_head list ;
     struct hotplug_slot *hotplug ;
     unsigned char number ;
     struct kobject kobj ;
  };
  #line 117 "include/linux/pci.h"
  typedef int pci_power_t;
  #line 143 "include/linux/pci.h"
  typedef unsigned int pci_channel_state_t;
  #line 144
  enum pci_channel_state {
      pci_channel_io_normal = 1,
      pci_channel_io_frozen = 2,
      pci_channel_io_perm_failure = 3
  } ;
  #line 169 "include/linux/pci.h"
  typedef unsigned short pci_dev_flags_t;
  #line 184 "include/linux/pci.h"
  typedef unsigned short pci_bus_flags_t;
  #line 227
  struct pcie_link_state;
  #line 227
  struct pcie_link_state;
  #line 228
  struct pci_vpd;
  #line 228
  struct pci_vpd;
  #line 229
  struct pci_sriov;
  #line 229
  struct pci_sriov;
  #line 230
  struct pci_ats;
  #line 230
  struct pci_ats;
  #line 231
  struct pci_driver;
  #line 231
  struct pci_driver;
  #line 231 "include/linux/pci.h"
  union __anonunion_ldv_18895_140 {
     struct pci_sriov *sriov ;
     struct pci_dev *physfn ;
  };
  #line 231 "include/linux/pci.h"
  struct pci_dev {
     struct list_head bus_list ;
     struct pci_bus *bus ;
     struct pci_bus *subordinate ;
     void *sysdata ;
     struct proc_dir_entry *procent ;
     struct pci_slot *slot ;
     unsigned int devfn ;
     unsigned short vendor ;
     unsigned short device ;
     unsigned short subsystem_vendor ;
     unsigned short subsystem_device ;
     unsigned int class ;
     u8 revision ;
     u8 hdr_type ;
     u8 pcie_cap ;
     u8 pcie_type ;
     u8 rom_base_reg ;
     u8 pin ;
     struct pci_driver *driver ;
     u64 dma_mask ;
     struct device_dma_parameters dma_parms ;
     pci_power_t current_state ;
     int pm_cap ;
     unsigned char pme_support : 5 ;
     unsigned char pme_interrupt : 1 ;
     unsigned char d1_support : 1 ;
     unsigned char d2_support : 1 ;
     unsigned char no_d1d2 : 1 ;
     unsigned char mmio_always_on : 1 ;
     unsigned char wakeup_prepared : 1 ;
     unsigned int d3_delay ;
     struct pcie_link_state *link_state ;
     pci_channel_state_t error_state ;
     struct device dev ;
     int cfg_size ;
     unsigned int irq ;
     struct resource resource[18U] ;
     resource_size_t fw_addr[18U] ;
     unsigned char transparent : 1 ;
     unsigned char multifunction : 1 ;
     unsigned char is_added : 1 ;
     unsigned char is_busmaster : 1 ;
     unsigned char no_msi : 1 ;
     unsigned char block_ucfg_access : 1 ;
     unsigned char broken_parity_status : 1 ;
     unsigned char irq_reroute_variant : 2 ;
     unsigned char msi_enabled : 1 ;
     unsigned char msix_enabled : 1 ;
     unsigned char ari_enabled : 1 ;
     unsigned char is_managed : 1 ;
     unsigned char is_pcie : 1 ;
     unsigned char needs_freset : 1 ;
     unsigned char state_saved : 1 ;
     unsigned char is_physfn : 1 ;
     unsigned char is_virtfn : 1 ;
     unsigned char reset_fn : 1 ;
     unsigned char is_hotplug_bridge : 1 ;
     unsigned char __aer_firmware_first_valid : 1 ;
     unsigned char __aer_firmware_first : 1 ;
     pci_dev_flags_t dev_flags ;
     atomic_t enable_cnt ;
     u32 saved_config_space[16U] ;
     struct hlist_head saved_cap_space ;
     struct bin_attribute *rom_attr ;
     int rom_attr_enabled ;
     struct bin_attribute *res_attr[18U] ;
     struct bin_attribute *res_attr_wc[18U] ;
     struct list_head msi_list ;
     struct pci_vpd *vpd ;
     union __anonunion_ldv_18895_140 ldv_18895 ;
     struct pci_ats *ats ;
  };
  #line 406
  struct pci_ops;
  #line 406
  struct pci_ops;
  #line 406 "include/linux/pci.h"
  struct pci_bus {
     struct list_head node ;
     struct pci_bus *parent ;
     struct list_head children ;
     struct list_head devices ;
     struct pci_dev *self ;
     struct list_head slots ;
     struct resource *resource[4U] ;
     struct list_head resources ;
     struct pci_ops *ops ;
     void *sysdata ;
     struct proc_dir_entry *procdir ;
     unsigned char number ;
     unsigned char primary ;
     unsigned char secondary ;
     unsigned char subordinate ;
     unsigned char max_bus_speed ;
     unsigned char cur_bus_speed ;
     char name[48U] ;
     unsigned short bridge_ctl ;
     pci_bus_flags_t bus_flags ;
     struct device *bridge ;
     struct device dev ;
     struct bin_attribute *legacy_io ;
     struct bin_attribute *legacy_mem ;
     unsigned char is_added : 1 ;
  };
  #line 458 "include/linux/pci.h"
  struct pci_ops {
     int (*read)(struct pci_bus * , unsigned int  , int  , int  , u32 * ) ;
     int (*write)(struct pci_bus * , unsigned int  , int  , int  , u32  ) ;
  };
  #line 493 "include/linux/pci.h"
  struct pci_dynids {
     spinlock_t lock ;
     struct list_head list ;
  };
  #line 506 "include/linux/pci.h"
  typedef unsigned int pci_ers_result_t;
  #line 515 "include/linux/pci.h"
  struct pci_error_handlers {
     pci_ers_result_t (*error_detected)(struct pci_dev * , enum pci_channel_state  ) ;
     pci_ers_result_t (*mmio_enabled)(struct pci_dev * ) ;
     pci_ers_result_t (*link_reset)(struct pci_dev * ) ;
     pci_ers_result_t (*slot_reset)(struct pci_dev * ) ;
     void (*resume)(struct pci_dev * ) ;
  };
  #line 543 "include/linux/pci.h"
  struct pci_driver {
     struct list_head node ;
     char const   *name ;
     struct pci_device_id  const  *id_table ;
     int (*probe)(struct pci_dev * , struct pci_device_id  const  * ) ;
     void (*remove)(struct pci_dev * ) ;
     int (*suspend)(struct pci_dev * , pm_message_t  ) ;
     int (*suspend_late)(struct pci_dev * , pm_message_t  ) ;
     int (*resume_early)(struct pci_dev * ) ;
     int (*resume)(struct pci_dev * ) ;
     void (*shutdown)(struct pci_dev * ) ;
     struct pci_error_handlers *err_handler ;
     struct device_driver driver ;
     struct pci_dynids dynids ;
  };
  #line 948 "include/linux/pci.h"
  struct scatterlist {
     unsigned long sg_magic ;
     unsigned long page_link ;
     unsigned int offset ;
     unsigned int length ;
     dma_addr_t dma_address ;
     unsigned int dma_length ;
  };
  #line 1095 "include/linux/pci.h"
  struct rb_node {
     unsigned long rb_parent_color ;
     struct rb_node *rb_right ;
     struct rb_node *rb_left ;
  };
  #line 108 "include/linux/rbtree.h"
  struct rb_root {
     struct rb_node *rb_node ;
  };
  #line 180 "include/linux/rbtree.h"
  struct __anonstruct_ldv_19717_142 {
     u16 inuse ;
     u16 objects ;
  };
  #line 180 "include/linux/rbtree.h"
  union __anonunion_ldv_19718_141 {
     atomic_t _mapcount ;
     struct __anonstruct_ldv_19717_142 ldv_19717 ;
  };
  #line 180 "include/linux/rbtree.h"
  struct __anonstruct_ldv_19723_144 {
     unsigned long private ;
     struct address_space *mapping ;
  };
  #line 180 "include/linux/rbtree.h"
  union __anonunion_ldv_19726_143 {
     struct __anonstruct_ldv_19723_144 ldv_19723 ;
     struct kmem_cache *slab ;
     struct page *first_page ;
  };
  #line 180 "include/linux/rbtree.h"
  union __anonunion_ldv_19730_145 {
     unsigned long index ;
     void *freelist ;
  };
  #line 180 "include/linux/rbtree.h"
  struct page {
     unsigned long flags ;
     atomic_t _count ;
     union __anonunion_ldv_19718_141 ldv_19718 ;
     union __anonunion_ldv_19726_143 ldv_19726 ;
     union __anonunion_ldv_19730_145 ldv_19730 ;
     struct list_head lru ;
  };
  #line 124 "include/linux/mm_types.h"
  struct __anonstruct_vm_set_147 {
     struct list_head list ;
     void *parent ;
     struct vm_area_struct *head ;
  };
  #line 124 "include/linux/mm_types.h"
  union __anonunion_shared_146 {
     struct __anonstruct_vm_set_147 vm_set ;
     struct raw_prio_tree_node prio_tree_node ;
  };
  #line 124
  struct anon_vma;
  #line 124
  struct anon_vma;
  #line 124
  struct vm_operations_struct;
  #line 124
  struct vm_operations_struct;
  #line 124
  struct mempolicy;
  #line 124
  struct mempolicy;
  #line 124 "include/linux/mm_types.h"
  struct vm_area_struct {
     struct mm_struct *vm_mm ;
     unsigned long vm_start ;
     unsigned long vm_end ;
     struct vm_area_struct *vm_next ;
     struct vm_area_struct *vm_prev ;
     pgprot_t vm_page_prot ;
     unsigned long vm_flags ;
     struct rb_node vm_rb ;
     union __anonunion_shared_146 shared ;
     struct list_head anon_vma_chain ;
     struct anon_vma *anon_vma ;
     struct vm_operations_struct  const  *vm_ops ;
     unsigned long vm_pgoff ;
     struct file *vm_file ;
     void *vm_private_data ;
     struct mempolicy *vm_policy ;
  };
  #line 187 "include/linux/mm_types.h"
  struct core_thread {
     struct task_struct *task ;
     struct core_thread *next ;
  };
  #line 193 "include/linux/mm_types.h"
  struct core_state {
     atomic_t nr_threads ;
     struct core_thread dumper ;
     struct completion startup ;
  };
  #line 206 "include/linux/mm_types.h"
  struct mm_rss_stat {
     atomic_long_t count[3U] ;
  };
  #line 219
  struct linux_binfmt;
  #line 219
  struct linux_binfmt;
  #line 219
  struct mmu_notifier_mm;
  #line 219
  struct mmu_notifier_mm;
  #line 219 "include/linux/mm_types.h"
  struct mm_struct {
     struct vm_area_struct *mmap ;
     struct rb_root mm_rb ;
     struct vm_area_struct *mmap_cache ;
     unsigned long (*get_unmapped_area)(struct file * , unsigned long  , unsigned long  ,
                                        unsigned long  , unsigned long  ) ;
     void (*unmap_area)(struct mm_struct * , unsigned long  ) ;
     unsigned long mmap_base ;
     unsigned long task_size ;
     unsigned long cached_hole_size ;
     unsigned long free_area_cache ;
     pgd_t *pgd ;
     atomic_t mm_users ;
     atomic_t mm_count ;
     int map_count ;
     spinlock_t page_table_lock ;
     struct rw_semaphore mmap_sem ;
     struct list_head mmlist ;
     unsigned long hiwater_rss ;
     unsigned long hiwater_vm ;
     unsigned long total_vm ;
     unsigned long locked_vm ;
     unsigned long shared_vm ;
     unsigned long exec_vm ;
     unsigned long stack_vm ;
     unsigned long reserved_vm ;
     unsigned long def_flags ;
     unsigned long nr_ptes ;
     unsigned long start_code ;
     unsigned long end_code ;
     unsigned long start_data ;
     unsigned long end_data ;
     unsigned long start_brk ;
     unsigned long brk ;
     unsigned long start_stack ;
     unsigned long arg_start ;
     unsigned long arg_end ;
     unsigned long env_start ;
     unsigned long env_end ;
     unsigned long saved_auxv[44U] ;
     struct mm_rss_stat rss_stat ;
     struct linux_binfmt *binfmt ;
     cpumask_var_t cpu_vm_mask_var ;
     mm_context_t context ;
     unsigned int faultstamp ;
     unsigned int token_priority ;
     unsigned int last_interval ;
     atomic_t oom_disable_count ;
     unsigned long flags ;
     struct core_state *core_state ;
     spinlock_t ioctx_lock ;
     struct hlist_head ioctx_list ;
     struct task_struct *owner ;
     struct file *exe_file ;
     unsigned long num_exe_file_vmas ;
     struct mmu_notifier_mm *mmu_notifier_mm ;
     pgtable_t pmd_huge_pte ;
     struct cpumask cpumask_allocation ;
  };
  #line 30 "include/linux/range.h"
  struct user_struct;
  #line 30
  struct user_struct;
  #line 175 "include/linux/mm.h"
  struct vm_fault {
     unsigned int flags ;
     unsigned long pgoff ;
     void *virtual_address ;
     struct page *page ;
  };
  #line 192 "include/linux/mm.h"
  struct vm_operations_struct {
     void (*open)(struct vm_area_struct * ) ;
     void (*close)(struct vm_area_struct * ) ;
     int (*fault)(struct vm_area_struct * , struct vm_fault * ) ;
     int (*page_mkwrite)(struct vm_area_struct * , struct vm_fault * ) ;
     int (*access)(struct vm_area_struct * , unsigned long  , void * , int  , int  ) ;
     int (*set_policy)(struct vm_area_struct * , struct mempolicy * ) ;
     struct mempolicy *(*get_policy)(struct vm_area_struct * , unsigned long  ) ;
     int (*migrate)(struct vm_area_struct * , nodemask_t const   * , nodemask_t const   * ,
                    unsigned long  ) ;
  };
  #line 1124 "include/linux/mm.h"
  struct shrink_control {
     gfp_t gfp_mask ;
     unsigned long nr_to_scan ;
  };
  #line 1136 "include/linux/mm.h"
  struct shrinker {
     int (*shrink)(struct shrinker * , struct shrink_control * ) ;
     int seeks ;
     struct list_head list ;
     long nr ;
  };
  #line 34 "include/linux/bug.h"
  struct dma_attrs {
     unsigned long flags[1U] ;
  };
  #line 266 "include/linux/scatterlist.h"
  enum dma_data_direction {
      DMA_BIDIRECTIONAL = 0,
      DMA_TO_DEVICE = 1,
      DMA_FROM_DEVICE = 2,
      DMA_NONE = 3
  } ;
  #line 273 "include/linux/scatterlist.h"
  struct dma_map_ops {
     void *(*alloc_coherent)(struct device * , size_t  , dma_addr_t * , gfp_t  ) ;
     void (*free_coherent)(struct device * , size_t  , void * , dma_addr_t  ) ;
     dma_addr_t (*map_page)(struct device * , struct page * , unsigned long  , size_t  ,
                            enum dma_data_direction  , struct dma_attrs * ) ;
     void (*unmap_page)(struct device * , dma_addr_t  , size_t  , enum dma_data_direction  ,
                        struct dma_attrs * ) ;
     int (*map_sg)(struct device * , struct scatterlist * , int  , enum dma_data_direction  ,
                   struct dma_attrs * ) ;
     void (*unmap_sg)(struct device * , struct scatterlist * , int  , enum dma_data_direction  ,
                      struct dma_attrs * ) ;
     void (*sync_single_for_cpu)(struct device * , dma_addr_t  , size_t  , enum dma_data_direction  ) ;
     void (*sync_single_for_device)(struct device * , dma_addr_t  , size_t  , enum dma_data_direction  ) ;
     void (*sync_sg_for_cpu)(struct device * , struct scatterlist * , int  , enum dma_data_direction  ) ;
     void (*sync_sg_for_device)(struct device * , struct scatterlist * , int  , enum dma_data_direction  ) ;
     int (*mapping_error)(struct device * , dma_addr_t  ) ;
     int (*dma_supported)(struct device * , u64  ) ;
     int (*set_dma_mask)(struct device * , u64  ) ;
     int is_phys ;
  };
  #line 1590 "include/linux/pci.h"
  struct cdev {
     struct kobject kobj ;
     struct module *owner ;
     struct file_operations  const  *ops ;
     struct list_head list ;
     dev_t dev ;
     unsigned int count ;
  };
  #line 34 "include/linux/cdev.h"
  struct exception_table_entry {
     unsigned long insn ;
     unsigned long fixup ;
  };
  #line 118 "include/linux/sem.h"
  struct sem_undo_list;
  #line 118
  struct sem_undo_list;
  #line 131 "include/linux/sem.h"
  struct sem_undo_list {
     atomic_t refcnt ;
     spinlock_t lock ;
     struct list_head list_proc ;
  };
  #line 140 "include/linux/sem.h"
  struct sysv_sem {
     struct sem_undo_list *undo_list ;
  };
  #line 16 "include/linux/socket.h"
  struct iovec {
     void *iov_base ;
     __kernel_size_t iov_len ;
  };
  #line 44 "include/linux/aio_abi.h"
  struct io_event {
     __u64 data ;
     __u64 obj ;
     __s64 res ;
     __s64 res2 ;
  };
  #line 7 "include/asm-generic/cputime.h"
  typedef unsigned long cputime_t;
  #line 26
  struct siginfo;
  #line 26
  struct siginfo;
  #line 32 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/signal.h"
  struct __anonstruct_sigset_t_159 {
     unsigned long sig[1U] ;
  };
  #line 32 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/signal.h"
  typedef struct __anonstruct_sigset_t_159 sigset_t;
  #line 17 "include/asm-generic/signal-defs.h"
  typedef void __signalfn_t(int  );
  #line 18 "include/asm-generic/signal-defs.h"
  typedef __signalfn_t *__sighandler_t;
  #line 20 "include/asm-generic/signal-defs.h"
  typedef void __restorefn_t(void);
  #line 21 "include/asm-generic/signal-defs.h"
  typedef __restorefn_t *__sigrestore_t;
  #line 126 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/signal.h"
  struct sigaction {
     __sighandler_t sa_handler ;
     unsigned long sa_flags ;
     __sigrestore_t sa_restorer ;
     sigset_t sa_mask ;
  };
  #line 173 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/signal.h"
  struct k_sigaction {
     struct sigaction sa ;
  };
  #line 185 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/signal.h"
  union sigval {
     int sival_int ;
     void *sival_ptr ;
  };
  #line 10 "include/asm-generic/siginfo.h"
  typedef union sigval sigval_t;
  #line 11 "include/asm-generic/siginfo.h"
  struct __anonstruct__kill_161 {
     __kernel_pid_t _pid ;
     __kernel_uid32_t _uid ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  struct __anonstruct__timer_162 {
     __kernel_timer_t _tid ;
     int _overrun ;
     char _pad[0U] ;
     sigval_t _sigval ;
     int _sys_private ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  struct __anonstruct__rt_163 {
     __kernel_pid_t _pid ;
     __kernel_uid32_t _uid ;
     sigval_t _sigval ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  struct __anonstruct__sigchld_164 {
     __kernel_pid_t _pid ;
     __kernel_uid32_t _uid ;
     int _status ;
     __kernel_clock_t _utime ;
     __kernel_clock_t _stime ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  struct __anonstruct__sigfault_165 {
     void *_addr ;
     short _addr_lsb ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  struct __anonstruct__sigpoll_166 {
     long _band ;
     int _fd ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  union __anonunion__sifields_160 {
     int _pad[28U] ;
     struct __anonstruct__kill_161 _kill ;
     struct __anonstruct__timer_162 _timer ;
     struct __anonstruct__rt_163 _rt ;
     struct __anonstruct__sigchld_164 _sigchld ;
     struct __anonstruct__sigfault_165 _sigfault ;
     struct __anonstruct__sigpoll_166 _sigpoll ;
  };
  #line 11 "include/asm-generic/siginfo.h"
  struct siginfo {
     int si_signo ;
     int si_errno ;
     int si_code ;
     union __anonunion__sifields_160 _sifields ;
  };
  #line 94 "include/asm-generic/siginfo.h"
  typedef struct siginfo siginfo_t;
  #line 24 "include/linux/signal.h"
  struct sigpending {
     struct list_head list ;
     sigset_t signal ;
  };
  #line 90 "include/linux/proportions.h"
  struct prop_local_single {
     unsigned long events ;
     unsigned long period ;
     int shift ;
     spinlock_t lock ;
  };
  #line 10 "include/linux/seccomp.h"
  struct __anonstruct_seccomp_t_169 {
     int mode ;
  };
  #line 10 "include/linux/seccomp.h"
  typedef struct __anonstruct_seccomp_t_169 seccomp_t;
  #line 21 "include/linux/seccomp.h"
  struct plist_head {
     struct list_head node_list ;
     raw_spinlock_t *rawlock ;
     spinlock_t *spinlock ;
  };
  #line 88 "include/linux/plist.h"
  struct plist_node {
     int prio ;
     struct list_head prio_list ;
     struct list_head node_list ;
  };
  #line 20 "include/linux/rtmutex.h"
  struct rt_mutex {
     raw_spinlock_t wait_lock ;
     struct plist_head wait_list ;
     struct task_struct *owner ;
     int save_state ;
     char const   *name ;
     char const   *file ;
     int line ;
     void *magic ;
  };
  #line 38
  struct rt_mutex_waiter;
  #line 38
  struct rt_mutex_waiter;
  #line 41 "include/linux/resource.h"
  struct rlimit {
     unsigned long rlim_cur ;
     unsigned long rlim_max ;
  };
  #line 85 "include/linux/resource.h"
  struct timerqueue_node {
     struct rb_node node ;
     ktime_t expires ;
  };
  #line 12 "include/linux/timerqueue.h"
  struct timerqueue_head {
     struct rb_root head ;
     struct timerqueue_node *next ;
  };
  #line 50
  struct hrtimer_clock_base;
  #line 50
  struct hrtimer_clock_base;
  #line 51
  struct hrtimer_cpu_base;
  #line 51
  struct hrtimer_cpu_base;
  #line 60
  enum hrtimer_restart {
      HRTIMER_NORESTART = 0,
      HRTIMER_RESTART = 1
  } ;
  #line 65 "include/linux/timerqueue.h"
  struct hrtimer {
     struct timerqueue_node node ;
     ktime_t _softexpires ;
     enum hrtimer_restart (*function)(struct hrtimer * ) ;
     struct hrtimer_clock_base *base ;
     unsigned long state ;
     int start_pid ;
     void *start_site ;
     char start_comm[16U] ;
  };
  #line 132 "include/linux/hrtimer.h"
  struct hrtimer_clock_base {
     struct hrtimer_cpu_base *cpu_base ;
     int index ;
     clockid_t clockid ;
     struct timerqueue_head active ;
     ktime_t resolution ;
     ktime_t (*get_time)(void) ;
     ktime_t softirq_time ;
     ktime_t offset ;
  };
  #line 162 "include/linux/hrtimer.h"
  struct hrtimer_cpu_base {
     raw_spinlock_t lock ;
     unsigned long active_bases ;
     ktime_t expires_next ;
     int hres_active ;
     int hang_detected ;
     unsigned long nr_events ;
     unsigned long nr_retries ;
     unsigned long nr_hangs ;
     ktime_t max_hang_time ;
     struct hrtimer_clock_base clock_base[3U] ;
  };
  #line 452 "include/linux/hrtimer.h"
  struct task_io_accounting {
     u64 rchar ;
     u64 wchar ;
     u64 syscr ;
     u64 syscw ;
     u64 read_bytes ;
     u64 write_bytes ;
     u64 cancelled_write_bytes ;
  };
  #line 45 "include/linux/task_io_accounting.h"
  struct latency_record {
     unsigned long backtrace[12U] ;
     unsigned int count ;
     unsigned long time ;
     unsigned long max ;
  };
  #line 29 "include/linux/key.h"
  typedef int32_t key_serial_t;
  #line 32 "include/linux/key.h"
  typedef uint32_t key_perm_t;
  #line 33
  struct key;
  #line 33
  struct key;
  #line 34
  struct signal_struct;
  #line 34
  struct signal_struct;
  #line 35
  struct key_type;
  #line 35
  struct key_type;
  #line 37
  struct keyring_list;
  #line 37
  struct keyring_list;
  #line 115
  struct key_user;
  #line 115
  struct key_user;
  #line 115 "include/linux/key.h"
  union __anonunion_ldv_24696_170 {
     time_t expiry ;
     time_t revoked_at ;
  };
  #line 115 "include/linux/key.h"
  union __anonunion_type_data_171 {
     struct list_head link ;
     unsigned long x[2U] ;
     void *p[2U] ;
     int reject_error ;
  };
  #line 115 "include/linux/key.h"
  union __anonunion_payload_172 {
     unsigned long value ;
     void *rcudata ;
     void *data ;
     struct keyring_list *subscriptions ;
  };
  #line 115 "include/linux/key.h"
  struct key {
     atomic_t usage ;
     key_serial_t serial ;
     struct rb_node serial_node ;
     struct key_type *type ;
     struct rw_semaphore sem ;
     struct key_user *user ;
     void *security ;
     union __anonunion_ldv_24696_170 ldv_24696 ;
     uid_t uid ;
     gid_t gid ;
     key_perm_t perm ;
     unsigned short quotalen ;
     unsigned short datalen ;
     unsigned long flags ;
     char *description ;
     union __anonunion_type_data_171 type_data ;
     union __anonunion_payload_172 payload ;
  };
  #line 310
  struct audit_context;
  #line 310
  struct audit_context;
  #line 27 "include/linux/selinux.h"
  struct group_info {
     atomic_t usage ;
     int ngroups ;
     int nblocks ;
     gid_t small_block[32U] ;
     gid_t *blocks[0U] ;
  };
  #line 77 "include/linux/cred.h"
  struct thread_group_cred {
     atomic_t usage ;
     pid_t tgid ;
     spinlock_t lock ;
     struct key *session_keyring ;
     struct key *process_keyring ;
     struct rcu_head rcu ;
  };
  #line 91 "include/linux/cred.h"
  struct cred {
     atomic_t usage ;
     atomic_t subscribers ;
     void *put_addr ;
     unsigned int magic ;
     uid_t uid ;
     gid_t gid ;
     uid_t suid ;
     gid_t sgid ;
     uid_t euid ;
     gid_t egid ;
     uid_t fsuid ;
     gid_t fsgid ;
     unsigned int securebits ;
     kernel_cap_t cap_inheritable ;
     kernel_cap_t cap_permitted ;
     kernel_cap_t cap_effective ;
     kernel_cap_t cap_bset ;
     unsigned char jit_keyring ;
     struct key *thread_keyring ;
     struct key *request_key_auth ;
     struct thread_group_cred *tgcred ;
     void *security ;
     struct user_struct *user ;
     struct user_namespace *user_ns ;
     struct group_info *group_info ;
     struct rcu_head rcu ;
  };
  #line 264
  struct futex_pi_state;
  #line 264
  struct futex_pi_state;
  #line 265
  struct robust_list_head;
  #line 265
  struct robust_list_head;
  #line 266
  struct bio_list;
  #line 266
  struct bio_list;
  #line 267
  struct fs_struct;
  #line 267
  struct fs_struct;
  #line 268
  struct perf_event_context;
  #line 268
  struct perf_event_context;
  #line 269
  struct blk_plug;
  #line 269
  struct blk_plug;
  #line 149 "include/linux/sched.h"
  struct cfs_rq;
  #line 149
  struct cfs_rq;
  #line 383
  struct kioctx;
  #line 383
  struct kioctx;
  #line 384 "include/linux/sched.h"
  union __anonunion_ki_obj_173 {
     void *user ;
     struct task_struct *tsk ;
  };
  #line 384
  struct eventfd_ctx;
  #line 384
  struct eventfd_ctx;
  #line 384 "include/linux/sched.h"
  struct kiocb {
     struct list_head ki_run_list ;
     unsigned long ki_flags ;
     int ki_users ;
     unsigned int ki_key ;
     struct file *ki_filp ;
     struct kioctx *ki_ctx ;
     int (*ki_cancel)(struct kiocb * , struct io_event * ) ;
     ssize_t (*ki_retry)(struct kiocb * ) ;
     void (*ki_dtor)(struct kiocb * ) ;
     union __anonunion_ki_obj_173 ki_obj ;
     __u64 ki_user_data ;
     loff_t ki_pos ;
     void *private ;
     unsigned short ki_opcode ;
     size_t ki_nbytes ;
     char *ki_buf ;
     size_t ki_left ;
     struct iovec ki_inline_vec ;
     struct iovec *ki_iovec ;
     unsigned long ki_nr_segs ;
     unsigned long ki_cur_seg ;
     struct list_head ki_list ;
     struct eventfd_ctx *ki_eventfd ;
  };
  #line 161 "include/linux/aio.h"
  struct aio_ring_info {
     unsigned long mmap_base ;
     unsigned long mmap_size ;
     struct page **ring_pages ;
     spinlock_t ring_lock ;
     long nr_pages ;
     unsigned int nr ;
     unsigned int tail ;
     struct page *internal_pages[8U] ;
  };
  #line 177 "include/linux/aio.h"
  struct kioctx {
     atomic_t users ;
     int dead ;
     struct mm_struct *mm ;
     unsigned long user_id ;
     struct hlist_node list ;
     wait_queue_head_t wait ;
     spinlock_t ctx_lock ;
     int reqs_active ;
     struct list_head active_reqs ;
     struct list_head run_list ;
     unsigned int max_reqs ;
     struct aio_ring_info ring_info ;
     struct delayed_work wq ;
     struct rcu_head rcu_head ;
  };
  #line 404 "include/linux/sched.h"
  struct sighand_struct {
     atomic_t count ;
     struct k_sigaction action[64U] ;
     spinlock_t siglock ;
     wait_queue_head_t signalfd_wqh ;
  };
  #line 447 "include/linux/sched.h"
  struct pacct_struct {
     int ac_flag ;
     long ac_exitcode ;
     unsigned long ac_mem ;
     cputime_t ac_utime ;
     cputime_t ac_stime ;
     unsigned long ac_minflt ;
     unsigned long ac_majflt ;
  };
  #line 455 "include/linux/sched.h"
  struct cpu_itimer {
     cputime_t expires ;
     cputime_t incr ;
     u32 error ;
     u32 incr_error ;
  };
  #line 462 "include/linux/sched.h"
  struct task_cputime {
     cputime_t utime ;
     cputime_t stime ;
     unsigned long long sum_exec_runtime ;
  };
  #line 479 "include/linux/sched.h"
  struct thread_group_cputimer {
     struct task_cputime cputime ;
     int running ;
     spinlock_t lock ;
  };
  #line 515
  struct autogroup;
  #line 515
  struct autogroup;
  #line 516
  struct tty_struct;
  #line 516
  struct tty_struct;
  #line 516
  struct taskstats;
  #line 516
  struct taskstats;
  #line 516
  struct tty_audit_buf;
  #line 516
  struct tty_audit_buf;
  #line 516 "include/linux/sched.h"
  struct signal_struct {
     atomic_t sigcnt ;
     atomic_t live ;
     int nr_threads ;
     wait_queue_head_t wait_chldexit ;
     struct task_struct *curr_target ;
     struct sigpending shared_pending ;
     int group_exit_code ;
     int notify_count ;
     struct task_struct *group_exit_task ;
     int group_stop_count ;
     unsigned int flags ;
     struct list_head posix_timers ;
     struct hrtimer real_timer ;
     struct pid *leader_pid ;
     ktime_t it_real_incr ;
     struct cpu_itimer it[2U] ;
     struct thread_group_cputimer cputimer ;
     struct task_cputime cputime_expires ;
     struct list_head cpu_timers[3U] ;
     struct pid *tty_old_pgrp ;
     int leader ;
     struct tty_struct *tty ;
     struct autogroup *autogroup ;
     cputime_t utime ;
     cputime_t stime ;
     cputime_t cutime ;
     cputime_t cstime ;
     cputime_t gtime ;
     cputime_t cgtime ;
     cputime_t prev_utime ;
     cputime_t prev_stime ;
     unsigned long nvcsw ;
     unsigned long nivcsw ;
     unsigned long cnvcsw ;
     unsigned long cnivcsw ;
     unsigned long min_flt ;
     unsigned long maj_flt ;
     unsigned long cmin_flt ;
     unsigned long cmaj_flt ;
     unsigned long inblock ;
     unsigned long oublock ;
     unsigned long cinblock ;
     unsigned long coublock ;
     unsigned long maxrss ;
     unsigned long cmaxrss ;
     struct task_io_accounting ioac ;
     unsigned long long sum_sched_runtime ;
     struct rlimit rlim[16U] ;
     struct pacct_struct pacct ;
     struct taskstats *stats ;
     unsigned int audit_tty ;
     struct tty_audit_buf *tty_audit_buf ;
     struct rw_semaphore threadgroup_fork_lock ;
     int oom_adj ;
     int oom_score_adj ;
     int oom_score_adj_min ;
     struct mutex cred_guard_mutex ;
  };
  #line 683 "include/linux/sched.h"
  struct user_struct {
     atomic_t __count ;
     atomic_t processes ;
     atomic_t files ;
     atomic_t sigpending ;
     atomic_t inotify_watches ;
     atomic_t inotify_devs ;
     atomic_t fanotify_listeners ;
     atomic_long_t epoll_watches ;
     unsigned long mq_bytes ;
     unsigned long locked_shm ;
     struct key *uid_keyring ;
     struct key *session_keyring ;
     struct hlist_node uidhash_node ;
     uid_t uid ;
     struct user_namespace *user_ns ;
     atomic_long_t locked_vm ;
  };
  #line 728
  struct reclaim_state;
  #line 728
  struct reclaim_state;
  #line 729 "include/linux/sched.h"
  struct sched_info {
     unsigned long pcount ;
     unsigned long long run_delay ;
     unsigned long long last_arrival ;
     unsigned long long last_queued ;
  };
  #line 744 "include/linux/sched.h"
  struct task_delay_info {
     spinlock_t lock ;
     unsigned int flags ;
     struct timespec blkio_start ;
     struct timespec blkio_end ;
     u64 blkio_delay ;
     u64 swapin_delay ;
     u32 blkio_count ;
     u32 swapin_count ;
     struct timespec freepages_start ;
     struct timespec freepages_end ;
     u64 freepages_delay ;
     u32 freepages_count ;
  };
  #line 1037
  struct io_context;
  #line 1037
  struct io_context;
  #line 1060
  struct rq;
  #line 1060
  struct rq;
  #line 1061 "include/linux/sched.h"
  struct sched_class {
     struct sched_class  const  *next ;
     void (*enqueue_task)(struct rq * , struct task_struct * , int  ) ;
     void (*dequeue_task)(struct rq * , struct task_struct * , int  ) ;
     void (*yield_task)(struct rq * ) ;
     bool (*yield_to_task)(struct rq * , struct task_struct * , bool  ) ;
     void (*check_preempt_curr)(struct rq * , struct task_struct * , int  ) ;
     struct task_struct *(*pick_next_task)(struct rq * ) ;
     void (*put_prev_task)(struct rq * , struct task_struct * ) ;
     int (*select_task_rq)(struct task_struct * , int  , int  ) ;
     void (*pre_schedule)(struct rq * , struct task_struct * ) ;
     void (*post_schedule)(struct rq * ) ;
     void (*task_waking)(struct task_struct * ) ;
     void (*task_woken)(struct rq * , struct task_struct * ) ;
     void (*set_cpus_allowed)(struct task_struct * , struct cpumask  const  * ) ;
     void (*rq_online)(struct rq * ) ;
     void (*rq_offline)(struct rq * ) ;
     void (*set_curr_task)(struct rq * ) ;
     void (*task_tick)(struct rq * , struct task_struct * , int  ) ;
     void (*task_fork)(struct task_struct * ) ;
     void (*switched_from)(struct rq * , struct task_struct * ) ;
     void (*switched_to)(struct rq * , struct task_struct * ) ;
     void (*prio_changed)(struct rq * , struct task_struct * , int  ) ;
     unsigned int (*get_rr_interval)(struct rq * , struct task_struct * ) ;
     void (*task_move_group)(struct task_struct * , int  ) ;
  };
  #line 1127 "include/linux/sched.h"
  struct load_weight {
     unsigned long weight ;
     unsigned long inv_weight ;
  };
  #line 1132 "include/linux/sched.h"
  struct sched_statistics {
     u64 wait_start ;
     u64 wait_max ;
     u64 wait_count ;
     u64 wait_sum ;
     u64 iowait_count ;
     u64 iowait_sum ;
     u64 sleep_start ;
     u64 sleep_max ;
     s64 sum_sleep_runtime ;
     u64 block_start ;
     u64 block_max ;
     u64 exec_max ;
     u64 slice_max ;
     u64 nr_migrations_cold ;
     u64 nr_failed_migrations_affine ;
     u64 nr_failed_migrations_running ;
     u64 nr_failed_migrations_hot ;
     u64 nr_forced_migrations ;
     u64 nr_wakeups ;
     u64 nr_wakeups_sync ;
     u64 nr_wakeups_migrate ;
     u64 nr_wakeups_local ;
     u64 nr_wakeups_remote ;
     u64 nr_wakeups_affine ;
     u64 nr_wakeups_affine_attempts ;
     u64 nr_wakeups_passive ;
     u64 nr_wakeups_idle ;
  };
  #line 1167 "include/linux/sched.h"
  struct sched_entity {
     struct load_weight load ;
     struct rb_node run_node ;
     struct list_head group_node ;
     unsigned int on_rq ;
     u64 exec_start ;
     u64 sum_exec_runtime ;
     u64 vruntime ;
     u64 prev_sum_exec_runtime ;
     u64 nr_migrations ;
     struct sched_statistics statistics ;
     struct sched_entity *parent ;
     struct cfs_rq *cfs_rq ;
     struct cfs_rq *my_q ;
  };
  #line 1193
  struct rt_rq;
  #line 1193
  struct rt_rq;
  #line 1193 "include/linux/sched.h"
  struct sched_rt_entity {
     struct list_head run_list ;
     unsigned long timeout ;
     unsigned int time_slice ;
     int nr_cpus_allowed ;
     struct sched_rt_entity *back ;
     struct sched_rt_entity *parent ;
     struct rt_rq *rt_rq ;
     struct rt_rq *my_q ;
  };
  #line 1217
  struct mem_cgroup;
  #line 1217
  struct mem_cgroup;
  #line 1217 "include/linux/sched.h"
  struct memcg_batch_info {
     int do_batch ;
     struct mem_cgroup *memcg ;
     unsigned long nr_pages ;
     unsigned long memsw_nr_pages ;
  };
  #line 1569
  struct irqaction;
  #line 1569
  struct irqaction;
  #line 1569
  struct css_set;
  #line 1569
  struct css_set;
  #line 1569
  struct compat_robust_list_head;
  #line 1569
  struct compat_robust_list_head;
  #line 1569
  struct ftrace_ret_stack;
  #line 1569
  struct ftrace_ret_stack;
  #line 1569 "include/linux/sched.h"
  struct task_struct {
     long volatile   state ;
     void *stack ;
     atomic_t usage ;
     unsigned int flags ;
     unsigned int ptrace ;
     struct task_struct *wake_entry ;
     int on_cpu ;
     int on_rq ;
     int prio ;
     int static_prio ;
     int normal_prio ;
     unsigned int rt_priority ;
     struct sched_class  const  *sched_class ;
     struct sched_entity se ;
     struct sched_rt_entity rt ;
     struct hlist_head preempt_notifiers ;
     unsigned char fpu_counter ;
     unsigned int btrace_seq ;
     unsigned int policy ;
     cpumask_t cpus_allowed ;
     struct sched_info sched_info ;
     struct list_head tasks ;
     struct plist_node pushable_tasks ;
     struct mm_struct *mm ;
     struct mm_struct *active_mm ;
     unsigned char brk_randomized : 1 ;
     int exit_state ;
     int exit_code ;
     int exit_signal ;
     int pdeath_signal ;
     unsigned int group_stop ;
     unsigned int personality ;
     unsigned char did_exec : 1 ;
     unsigned char in_execve : 1 ;
     unsigned char in_iowait : 1 ;
     unsigned char sched_reset_on_fork : 1 ;
     unsigned char sched_contributes_to_load : 1 ;
     pid_t pid ;
     pid_t tgid ;
     unsigned long stack_canary ;
     struct task_struct *real_parent ;
     struct task_struct *parent ;
     struct list_head children ;
     struct list_head sibling ;
     struct task_struct *group_leader ;
     struct list_head ptraced ;
     struct list_head ptrace_entry ;
     struct pid_link pids[3U] ;
     struct list_head thread_group ;
     struct completion *vfork_done ;
     int *set_child_tid ;
     int *clear_child_tid ;
     cputime_t utime ;
     cputime_t stime ;
     cputime_t utimescaled ;
     cputime_t stimescaled ;
     cputime_t gtime ;
     cputime_t prev_utime ;
     cputime_t prev_stime ;
     unsigned long nvcsw ;
     unsigned long nivcsw ;
     struct timespec start_time ;
     struct timespec real_start_time ;
     unsigned long min_flt ;
     unsigned long maj_flt ;
     struct task_cputime cputime_expires ;
     struct list_head cpu_timers[3U] ;
     struct cred  const  *real_cred ;
     struct cred  const  *cred ;
     struct cred *replacement_session_keyring ;
     char comm[16U] ;
     int link_count ;
     int total_link_count ;
     struct sysv_sem sysvsem ;
     unsigned long last_switch_count ;
     struct thread_struct thread ;
     struct fs_struct *fs ;
     struct files_struct *files ;
     struct nsproxy *nsproxy ;
     struct signal_struct *signal ;
     struct sighand_struct *sighand ;
     sigset_t blocked ;
     sigset_t real_blocked ;
     sigset_t saved_sigmask ;
     struct sigpending pending ;
     unsigned long sas_ss_sp ;
     size_t sas_ss_size ;
     int (*notifier)(void * ) ;
     void *notifier_data ;
     sigset_t *notifier_mask ;
     struct audit_context *audit_context ;
     uid_t loginuid ;
     unsigned int sessionid ;
     seccomp_t seccomp ;
     u32 parent_exec_id ;
     u32 self_exec_id ;
     spinlock_t alloc_lock ;
     struct irqaction *irqaction ;
     raw_spinlock_t pi_lock ;
     struct plist_head pi_waiters ;
     struct rt_mutex_waiter *pi_blocked_on ;
     struct mutex_waiter *blocked_on ;
     unsigned int irq_events ;
     unsigned long hardirq_enable_ip ;
     unsigned long hardirq_disable_ip ;
     unsigned int hardirq_enable_event ;
     unsigned int hardirq_disable_event ;
     int hardirqs_enabled ;
     int hardirq_context ;
     unsigned long softirq_disable_ip ;
     unsigned long softirq_enable_ip ;
     unsigned int softirq_disable_event ;
     unsigned int softirq_enable_event ;
     int softirqs_enabled ;
     int softirq_context ;
     u64 curr_chain_key ;
     int lockdep_depth ;
     unsigned int lockdep_recursion ;
     struct held_lock held_locks[48U] ;
     gfp_t lockdep_reclaim_gfp ;
     void *journal_info ;
     struct bio_list *bio_list ;
     struct blk_plug *plug ;
     struct reclaim_state *reclaim_state ;
     struct backing_dev_info *backing_dev_info ;
     struct io_context *io_context ;
     unsigned long ptrace_message ;
     siginfo_t *last_siginfo ;
     struct task_io_accounting ioac ;
     u64 acct_rss_mem1 ;
     u64 acct_vm_mem1 ;
     cputime_t acct_timexpd ;
     nodemask_t mems_allowed ;
     int mems_allowed_change_disable ;
     int cpuset_mem_spread_rotor ;
     int cpuset_slab_spread_rotor ;
     struct css_set *cgroups ;
     struct list_head cg_list ;
     struct robust_list_head *robust_list ;
     struct compat_robust_list_head *compat_robust_list ;
     struct list_head pi_state_list ;
     struct futex_pi_state *pi_state_cache ;
     struct perf_event_context *perf_event_ctxp[2U] ;
     struct mutex perf_event_mutex ;
     struct list_head perf_event_list ;
     struct mempolicy *mempolicy ;
     short il_next ;
     short pref_node_fork ;
     atomic_t fs_excl ;
     struct rcu_head rcu ;
     struct pipe_inode_info *splice_pipe ;
     struct task_delay_info *delays ;
     int make_it_fail ;
     struct prop_local_single dirties ;
     int latency_record_count ;
     struct latency_record latency_record[32U] ;
     unsigned long timer_slack_ns ;
     unsigned long default_timer_slack_ns ;
     struct list_head *scm_work_list ;
     int curr_ret_stack ;
     struct ftrace_ret_stack *ret_stack ;
     unsigned long long ftrace_timestamp ;
     atomic_t trace_overrun ;
     atomic_t tracing_graph_pause ;
     unsigned long trace ;
     unsigned long trace_recursion ;
     struct memcg_batch_info memcg_batch ;
     atomic_t ptrace_bp_refcnt ;
  };
  #line 16 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/compat.h"
  typedef s32 compat_time_t;
  #line 37 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/compat.h"
  typedef s32 compat_long_t;
  #line 42 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/compat.h"
  struct compat_timespec {
     compat_time_t tv_sec ;
     s32 tv_nsec ;
  };
  #line 196 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/compat.h"
  typedef u32 compat_uptr_t;
  #line 205 "include/linux/compat.h"
  struct compat_robust_list {
     compat_uptr_t next ;
  };
  #line 209 "include/linux/compat.h"
  struct compat_robust_list_head {
     struct compat_robust_list list ;
     compat_long_t futex_offset ;
     compat_uptr_t list_op_pending ;
  };
  #line 187 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/mtrr.h"
  enum chipset_type {
      NOT_SUPPORTED = 0,
      SUPPORTED = 1
  } ;
  #line 192 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/mtrr.h"
  struct agp_version {
     u16 major ;
     u16 minor ;
  };
  #line 44 "include/linux/agp_backend.h"
  struct agp_kern_info {
     struct agp_version version ;
     struct pci_dev *device ;
     enum chipset_type chipset ;
     unsigned long mode ;
     unsigned long aper_base ;
     size_t aper_size ;
     int max_memory ;
     int current_memory ;
     bool cant_use_aperture ;
     unsigned long page_mask ;
     struct vm_operations_struct  const  *vm_ops ;
  };
  #line 58
  struct agp_bridge_data;
  #line 58
  struct agp_bridge_data;
  #line 108 "include/linux/agp_backend.h"
  struct pollfd {
     int fd ;
     short events ;
     short revents ;
  };
  #line 34 "include/linux/poll.h"
  struct poll_table_struct {
     void (*qproc)(struct file * , wait_queue_head_t * , struct poll_table_struct * ) ;
     unsigned long key ;
  };
  #line 74 "include/drm/drm.h"
  typedef unsigned int drm_magic_t;
  #line 75 "include/drm/drm.h"
  struct drm_clip_rect {
     unsigned short x1 ;
     unsigned short y1 ;
     unsigned short x2 ;
     unsigned short y2 ;
  };
  #line 110 "include/drm/drm.h"
  struct drm_hw_lock {
     unsigned int volatile   lock ;
     char padding[60U] ;
  };
  #line 139 "include/drm/drm.h"
  struct drm_unique {
     size_t unique_len ;
     char *unique ;
  };
  #line 173
  enum drm_map_type {
      _DRM_FRAME_BUFFER = 0,
      _DRM_REGISTERS = 1,
      _DRM_SHM = 2,
      _DRM_AGP = 3,
      _DRM_SCATTER_GATHER = 4,
      _DRM_CONSISTENT = 5,
      _DRM_GEM = 6
  } ;
  #line 183
  enum drm_map_flags {
      _DRM_RESTRICTED = 1,
      _DRM_READ_ONLY = 2,
      _DRM_LOCKED = 4,
      _DRM_KERNEL = 8,
      _DRM_WRITE_COMBINING = 16,
      _DRM_CONTAINS_LOCK = 32,
      _DRM_REMOVABLE = 64,
      _DRM_DRIVER = 128
  } ;
  #line 234
  enum drm_stat_type {
      _DRM_STAT_LOCK = 0,
      _DRM_STAT_OPENS = 1,
      _DRM_STAT_CLOSES = 2,
      _DRM_STAT_IOCTLS = 3,
      _DRM_STAT_LOCKS = 4,
      _DRM_STAT_UNLOCKS = 5,
      _DRM_STAT_VALUE = 6,
      _DRM_STAT_BYTE = 7,
      _DRM_STAT_COUNT = 8,
      _DRM_STAT_IRQ = 9,
      _DRM_STAT_PRIMARY = 10,
      _DRM_STAT_SECONDARY = 11,
      _DRM_STAT_DMA = 12,
      _DRM_STAT_SPECIAL = 13,
      _DRM_STAT_MISSED = 14
  } ;
  #line 399
  enum drm_ctx_flags {
      _DRM_CONTEXT_PRESERVED = 1,
      _DRM_CONTEXT_2DONLY = 2
  } ;
  #line 450 "include/drm/drm.h"
  struct drm_irq_busid {
     int irq ;
     int busnum ;
     int devnum ;
     int funcnum ;
  };
  #line 575 "include/drm/drm.h"
  struct drm_set_version {
     int drm_di_major ;
     int drm_di_minor ;
     int drm_dd_major ;
     int drm_dd_minor ;
  };
  #line 221 "include/drm/drm_mode.h"
  struct drm_mode_fb_cmd {
     __u32 fb_id ;
     __u32 width ;
     __u32 height ;
     __u32 pitch ;
     __u32 bpp ;
     __u32 depth ;
     __u32 handle ;
  };
  #line 346 "include/drm/drm_mode.h"
  struct drm_mode_create_dumb {
     uint32_t height ;
     uint32_t width ;
     uint32_t bpp ;
     uint32_t flags ;
     uint32_t handle ;
     uint32_t pitch ;
     uint64_t size ;
  };
  #line 375 "include/drm/drm_mode.h"
  struct drm_event {
     __u32 type ;
     __u32 length ;
  };
  #line 745 "include/drm/drm.h"
  struct drm_event_vblank {
     struct drm_event base ;
     __u64 user_data ;
     __u32 tv_sec ;
     __u32 tv_usec ;
     __u32 sequence ;
     __u32 reserved ;
  };
  #line 757 "include/drm/drm.h"
  struct idr_layer {
     unsigned long bitmap ;
     struct idr_layer *ary[64U] ;
     int count ;
     int layer ;
     struct rcu_head rcu_head ;
  };
  #line 58 "include/linux/idr.h"
  struct idr {
     struct idr_layer *top ;
     struct idr_layer *id_free ;
     int layers ;
     int id_free_cnt ;
     spinlock_t lock ;
  };
  #line 150
  struct drm_file;
  #line 150
  struct drm_file;
  #line 151
  struct drm_device;
  #line 151
  struct drm_device;
  #line 91 "include/linux/interrupt.h"
  struct irqaction {
     irqreturn_t (*handler)(int  , void * ) ;
     unsigned long flags ;
     void *dev_id ;
     struct irqaction *next ;
     int irq ;
     irqreturn_t (*thread_fn)(int  , void * ) ;
     struct task_struct *thread ;
     unsigned long thread_flags ;
     unsigned long thread_mask ;
     char const   *name ;
     struct proc_dir_entry *dir ;
  };
  #line 54 "include/linux/delay.h"
  struct drm_hash_item {
     struct hlist_node head ;
     unsigned long key ;
  };
  #line 46 "include/drm/drm_hashtab.h"
  struct drm_open_hash {
     struct hlist_head *table ;
     u8 order ;
  };
  #line 63 "include/drm/drm_hashtab.h"
  struct seq_file {
     char *buf ;
     size_t size ;
     size_t from ;
     size_t count ;
     loff_t index ;
     loff_t read_pos ;
     u64 version ;
     struct mutex lock ;
     struct seq_operations  const  *op ;
     void *private ;
  };
  #line 28 "include/linux/seq_file.h"
  struct seq_operations {
     void *(*start)(struct seq_file * , loff_t * ) ;
     void (*stop)(struct seq_file * , void * ) ;
     void *(*next)(struct seq_file * , void * , loff_t * ) ;
     int (*show)(struct seq_file * , void * ) ;
  };
  #line 154
  struct drm_mm;
  #line 154
  struct drm_mm;
  #line 154 "include/linux/seq_file.h"
  struct drm_mm_node {
     struct list_head node_list ;
     struct list_head hole_stack ;
     unsigned char hole_follows : 1 ;
     unsigned char scanned_block : 1 ;
     unsigned char scanned_prev_free : 1 ;
     unsigned char scanned_next_free : 1 ;
     unsigned char scanned_preceeds_hole : 1 ;
     unsigned char allocated : 1 ;
     unsigned long start ;
     unsigned long size ;
     struct drm_mm *mm ;
  };
  #line 57 "include/drm/drm_mm.h"
  struct drm_mm {
     struct list_head hole_stack ;
     struct drm_mm_node head_node ;
     struct list_head unused_nodes ;
     int num_unused ;
     spinlock_t unused_lock ;
     unsigned char scan_check_range : 1 ;
     unsigned int scan_alignment ;
     unsigned long scan_size ;
     unsigned long scan_hit_start ;
     unsigned int scan_hit_size ;
     unsigned int scanned_blocks ;
     unsigned long scan_start ;
     unsigned long scan_end ;
     struct drm_mm_node *prev_scanned_node ;
  };
  #line 286 "include/drm/drmP.h"
  typedef int drm_ioctl_t(struct drm_device * , void * , struct drm_file * );
  #line 290 "include/drm/drmP.h"
  struct drm_ioctl_desc {
     unsigned int cmd ;
     int flags ;
     drm_ioctl_t *func ;
     unsigned int cmd_drv ;
  };
  #line 327
  enum ldv_22760 {
      DRM_LIST_NONE = 0,
      DRM_LIST_FREE = 1,
      DRM_LIST_WAIT = 2,
      DRM_LIST_PEND = 3,
      DRM_LIST_PRIO = 4,
      DRM_LIST_RECLAIM = 5
  } ;
  #line 336 "include/drm/drmP.h"
  struct drm_buf {
     int idx ;
     int total ;
     int order ;
     int used ;
     unsigned long offset ;
     void *address ;
     unsigned long bus_address ;
     struct drm_buf *next ;
     int volatile   waiting ;
     int volatile   pending ;
     wait_queue_head_t dma_wait ;
     struct drm_file *file_priv ;
     int context ;
     int while_locked ;
     enum ldv_22760 list ;
     int dev_priv_size ;
     void *dev_private ;
  };
  #line 358 "include/drm/drmP.h"
  struct drm_waitlist {
     int count ;
     struct drm_buf **bufs ;
     struct drm_buf **rp ;
     struct drm_buf **wp ;
     struct drm_buf **end ;
     spinlock_t read_lock ;
     spinlock_t write_lock ;
  };
  #line 369 "include/drm/drmP.h"
  struct drm_freelist {
     int initialized ;
     atomic_t count ;
     struct drm_buf *next ;
     wait_queue_head_t waiting ;
     int low_mark ;
     int high_mark ;
     atomic_t wfh ;
     spinlock_t lock ;
  };
  #line 381 "include/drm/drmP.h"
  struct drm_dma_handle {
     dma_addr_t busaddr ;
     void *vaddr ;
     size_t size ;
  };
  #line 386 "include/drm/drmP.h"
  typedef struct drm_dma_handle drm_dma_handle_t;
  #line 387 "include/drm/drmP.h"
  struct drm_buf_entry {
     int buf_size ;
     int buf_count ;
     struct drm_buf *buflist ;
     int seg_count ;
     int page_order ;
     struct drm_dma_handle **seglist ;
     struct drm_freelist freelist ;
  };
  #line 401 "include/drm/drmP.h"
  struct drm_pending_event {
     struct drm_event *event ;
     struct list_head link ;
     struct drm_file *file_priv ;
     pid_t pid ;
     void (*destroy)(struct drm_pending_event * ) ;
  };
  #line 411
  struct drm_minor;
  #line 411
  struct drm_minor;
  #line 411
  struct drm_master;
  #line 411
  struct drm_master;
  #line 411 "include/drm/drmP.h"
  struct drm_file {
     int authenticated ;
     pid_t pid ;
     uid_t uid ;
     drm_magic_t magic ;
     unsigned long ioctl_count ;
     struct list_head lhead ;
     struct drm_minor *minor ;
     unsigned long lock_count ;
     struct idr object_idr ;
     spinlock_t table_lock ;
     struct file *filp ;
     void *driver_priv ;
     int is_master ;
     struct drm_master *master ;
     struct list_head fbs ;
     wait_queue_head_t event_wait ;
     struct list_head event_list ;
     int event_space ;
  };
  #line 440 "include/drm/drmP.h"
  struct drm_queue {
     atomic_t use_count ;
     atomic_t finalization ;
     atomic_t block_count ;
     atomic_t block_read ;
     wait_queue_head_t read_queue ;
     atomic_t block_write ;
     wait_queue_head_t write_queue ;
     atomic_t total_queued ;
     atomic_t total_flushed ;
     atomic_t total_locks ;
     enum drm_ctx_flags flags ;
     struct drm_waitlist waitlist ;
     wait_queue_head_t flush_queue ;
  };
  #line 457 "include/drm/drmP.h"
  struct drm_lock_data {
     struct drm_hw_lock *hw_lock ;
     struct drm_file *file_priv ;
     wait_queue_head_t lock_queue ;
     unsigned long lock_time ;
     spinlock_t spinlock ;
     uint32_t kernel_waiters ;
     uint32_t user_waiters ;
     int idle_has_lock ;
  };
  #line 472
  enum ldv_22785 {
      _DRM_DMA_USE_AGP = 1,
      _DRM_DMA_USE_SG = 2,
      _DRM_DMA_USE_FB = 4,
      _DRM_DMA_USE_PCI_RO = 8
  } ;
  #line 479 "include/drm/drmP.h"
  struct drm_device_dma {
     struct drm_buf_entry bufs[23U] ;
     int buf_count ;
     struct drm_buf **buflist ;
     int seg_count ;
     int page_count ;
     unsigned long *pagelist ;
     unsigned long byte_count ;
     enum ldv_22785 flags ;
  };
  #line 504 "include/drm/drmP.h"
  struct drm_agp_head {
     struct agp_kern_info agp_info ;
     struct list_head memory ;
     unsigned long mode ;
     struct agp_bridge_data *bridge ;
     int enabled ;
     int acquired ;
     unsigned long base ;
     int agp_mtrr ;
     int cant_use_aperture ;
     unsigned long page_mask ;
  };
  #line 522 "include/drm/drmP.h"
  struct drm_sg_mem {
     unsigned long handle ;
     void *virtual ;
     int pages ;
     struct page **pagelist ;
     dma_addr_t *busaddr ;
  };
  #line 533 "include/drm/drmP.h"
  struct drm_sigdata {
     int context ;
     struct drm_hw_lock *lock ;
  };
  #line 538 "include/drm/drmP.h"
  struct drm_local_map {
     resource_size_t offset ;
     unsigned long size ;
     enum drm_map_type type ;
     enum drm_map_flags flags ;
     void *handle ;
     int mtrr ;
  };
  #line 553 "include/drm/drmP.h"
  typedef struct drm_local_map drm_local_map_t;
  #line 554 "include/drm/drmP.h"
  struct drm_map_list {
     struct list_head head ;
     struct drm_hash_item hash ;
     struct drm_local_map *map ;
     uint64_t user_token ;
     struct drm_master *master ;
     struct drm_mm_node *file_offset_node ;
  };
  #line 602 "include/drm/drmP.h"
  struct drm_gem_object {
     struct kref refcount ;
     atomic_t handle_count ;
     struct drm_device *dev ;
     struct file *filp ;
     struct drm_map_list map_list ;
     size_t size ;
     int name ;
     uint32_t read_domains ;
     uint32_t write_domain ;
     uint32_t pending_read_domains ;
     uint32_t pending_write_domain ;
     void *driver_private ;
  };
  #line 26 "include/linux/of.h"
  typedef u32 phandle;
  #line 28 "include/linux/of.h"
  struct property {
     char *name ;
     int length ;
     void *value ;
     struct property *next ;
     unsigned long _flags ;
     unsigned int unique_id ;
  };
  #line 37 "include/linux/of.h"
  struct device_node {
     char const   *name ;
     char const   *type ;
     phandle phandle ;
     char *full_name ;
     struct property *properties ;
     struct property *deadprops ;
     struct device_node *parent ;
     struct device_node *child ;
     struct device_node *sibling ;
     struct device_node *next ;
     struct device_node *allnext ;
     struct proc_dir_entry *pde ;
     struct kref kref ;
     unsigned long _flags ;
     void *data ;
  };
  #line 40 "include/linux/i2c.h"
  struct i2c_msg;
  #line 40
  struct i2c_msg;
  #line 41
  struct i2c_algorithm;
  #line 41
  struct i2c_algorithm;
  #line 42
  struct i2c_adapter;
  #line 42
  struct i2c_adapter;
  #line 45
  union i2c_smbus_data;
  #line 45
  union i2c_smbus_data;
  #line 317 "include/linux/i2c.h"
  struct i2c_algorithm {
     int (*master_xfer)(struct i2c_adapter * , struct i2c_msg * , int  ) ;
     int (*smbus_xfer)(struct i2c_adapter * , u16  , unsigned short  , char  , u8  ,
                       int  , union i2c_smbus_data * ) ;
     u32 (*functionality)(struct i2c_adapter * ) ;
  };
  #line 349 "include/linux/i2c.h"
  struct i2c_adapter {
     struct module *owner ;
     unsigned int class ;
     struct i2c_algorithm  const  *algo ;
     void *algo_data ;
     struct rt_mutex bus_lock ;
     int timeout ;
     int retries ;
     struct device dev ;
     int nr ;
     char name[48U] ;
     struct completion dev_released ;
     struct mutex userspace_clients_lock ;
     struct list_head userspace_clients ;
  };
  #line 471 "include/linux/i2c.h"
  struct i2c_msg {
     __u16 addr ;
     __u16 flags ;
     __u16 len ;
     __u8 *buf ;
  };
  #line 523 "include/linux/i2c.h"
  union i2c_smbus_data {
     __u8 byte ;
     __u16 word ;
     __u8 block[34U] ;
  };
  #line 188 "include/linux/serial.h"
  struct serial_icounter_struct {
     int cts ;
     int dsr ;
     int rng ;
     int dcd ;
     int rx ;
     int tx ;
     int frame ;
     int overrun ;
     int parity ;
     int brk ;
     int buf_overrun ;
     int reserved[9U] ;
  };
  #line 6 "include/asm-generic/termbits.h"
  typedef unsigned char cc_t;
  #line 7 "include/asm-generic/termbits.h"
  typedef unsigned int speed_t;
  #line 8 "include/asm-generic/termbits.h"
  typedef unsigned int tcflag_t;
  #line 30 "include/asm-generic/termbits.h"
  struct ktermios {
     tcflag_t c_iflag ;
     tcflag_t c_oflag ;
     tcflag_t c_cflag ;
     tcflag_t c_lflag ;
     cc_t c_line ;
     cc_t c_cc[19U] ;
     speed_t c_ispeed ;
     speed_t c_ospeed ;
  };
  #line 41 "include/asm-generic/termbits.h"
  struct winsize {
     unsigned short ws_row ;
     unsigned short ws_col ;
     unsigned short ws_xpixel ;
     unsigned short ws_ypixel ;
  };
  #line 138 "include/asm-generic/termios.h"
  struct termiox {
     __u16 x_hflag ;
     __u16 x_cflag ;
     __u16 x_rflag[5U] ;
     __u16 x_sflag ;
  };
  #line 16 "include/linux/termios.h"
  struct tty_operations {
     struct tty_struct *(*lookup)(struct tty_driver * , struct inode * , int  ) ;
     int (*install)(struct tty_driver * , struct tty_struct * ) ;
     void (*remove)(struct tty_driver * , struct tty_struct * ) ;
     int (*open)(struct tty_struct * , struct file * ) ;
     void (*close)(struct tty_struct * , struct file * ) ;
     void (*shutdown)(struct tty_struct * ) ;
     void (*cleanup)(struct tty_struct * ) ;
     int (*write)(struct tty_struct * , unsigned char const   * , int  ) ;
     int (*put_char)(struct tty_struct * , unsigned char  ) ;
     void (*flush_chars)(struct tty_struct * ) ;
     int (*write_room)(struct tty_struct * ) ;
     int (*chars_in_buffer)(struct tty_struct * ) ;
     int (*ioctl)(struct tty_struct * , unsigned int  , unsigned long  ) ;
     long (*compat_ioctl)(struct tty_struct * , unsigned int  , unsigned long  ) ;
     void (*set_termios)(struct tty_struct * , struct ktermios * ) ;
     void (*throttle)(struct tty_struct * ) ;
     void (*unthrottle)(struct tty_struct * ) ;
     void (*stop)(struct tty_struct * ) ;
     void (*start)(struct tty_struct * ) ;
     void (*hangup)(struct tty_struct * ) ;
     int (*break_ctl)(struct tty_struct * , int  ) ;
     void (*flush_buffer)(struct tty_struct * ) ;
     void (*set_ldisc)(struct tty_struct * ) ;
     void (*wait_until_sent)(struct tty_struct * , int  ) ;
     void (*send_xchar)(struct tty_struct * , char  ) ;
     int (*tiocmget)(struct tty_struct * ) ;
     int (*tiocmset)(struct tty_struct * , unsigned int  , unsigned int  ) ;
     int (*resize)(struct tty_struct * , struct winsize * ) ;
     int (*set_termiox)(struct tty_struct * , struct termiox * ) ;
     int (*get_icount)(struct tty_struct * , struct serial_icounter_struct * ) ;
     int (*poll_init)(struct tty_driver * , int  , char * ) ;
     int (*poll_get_char)(struct tty_driver * , int  ) ;
     void (*poll_put_char)(struct tty_driver * , int  , char  ) ;
     struct file_operations  const  *proc_fops ;
  };
  #line 287 "include/linux/tty_driver.h"
  struct tty_driver {
     int magic ;
     struct kref kref ;
     struct cdev cdev ;
     struct module *owner ;
     char const   *driver_name ;
     char const   *name ;
     int name_base ;
     int major ;
     int minor_start ;
     int minor_num ;
     int num ;
     short type ;
     short subtype ;
     struct ktermios init_termios ;
     int flags ;
     struct proc_dir_entry *proc_entry ;
     struct tty_driver *other ;
     struct tty_struct **ttys ;
     struct ktermios **termios ;
     struct ktermios **termios_locked ;
     void *driver_state ;
     struct tty_operations  const  *ops ;
     struct list_head tty_drivers ;
  };
  #line 48 "include/linux/pps_kernel.h"
  struct pps_event_time {
     struct timespec ts_real ;
  };
  #line 116 "include/linux/pps_kernel.h"
  struct tty_ldisc_ops {
     int magic ;
     char *name ;
     int num ;
     int flags ;
     int (*open)(struct tty_struct * ) ;
     void (*close)(struct tty_struct * ) ;
     void (*flush_buffer)(struct tty_struct * ) ;
     ssize_t (*chars_in_buffer)(struct tty_struct * ) ;
     ssize_t (*read)(struct tty_struct * , struct file * , unsigned char * , size_t  ) ;
     ssize_t (*write)(struct tty_struct * , struct file * , unsigned char const   * ,
                      size_t  ) ;
     int (*ioctl)(struct tty_struct * , struct file * , unsigned int  , unsigned long  ) ;
     long (*compat_ioctl)(struct tty_struct * , struct file * , unsigned int  , unsigned long  ) ;
     void (*set_termios)(struct tty_struct * , struct ktermios * ) ;
     unsigned int (*poll)(struct tty_struct * , struct file * , struct poll_table_struct * ) ;
     int (*hangup)(struct tty_struct * ) ;
     void (*receive_buf)(struct tty_struct * , unsigned char const   * , char * , int  ) ;
     void (*write_wakeup)(struct tty_struct * ) ;
     void (*dcd_change)(struct tty_struct * , unsigned int  , struct pps_event_time * ) ;
     struct module *owner ;
     int refcount ;
  };
  #line 153 "include/linux/tty_ldisc.h"
  struct tty_ldisc {
     struct tty_ldisc_ops *ops ;
     atomic_t users ;
  };
  #line 158 "include/linux/tty_ldisc.h"
  struct tty_buffer {
     struct tty_buffer *next ;
     char *char_buf_ptr ;
     unsigned char *flag_buf_ptr ;
     int used ;
     int size ;
     int commit ;
     int read ;
     unsigned long data[0U] ;
  };
  #line 74 "include/linux/tty.h"
  struct tty_bufhead {
     struct work_struct work ;
     spinlock_t lock ;
     struct tty_buffer *head ;
     struct tty_buffer *tail ;
     struct tty_buffer *free ;
     int memory_used ;
  };
  #line 94
  struct tty_port;
  #line 94
  struct tty_port;
  #line 95 "include/linux/tty.h"
  struct tty_port_operations {
     int (*carrier_raised)(struct tty_port * ) ;
     void (*dtr_rts)(struct tty_port * , int  ) ;
     void (*shutdown)(struct tty_port * ) ;
     void (*drop)(struct tty_port * ) ;
     int (*activate)(struct tty_port * , struct tty_struct * ) ;
     void (*destruct)(struct tty_port * ) ;
  };
  #line 221 "include/linux/tty.h"
  struct tty_port {
     struct tty_struct *tty ;
     struct tty_port_operations  const  *ops ;
     spinlock_t lock ;
     int blocked_open ;
     int count ;
     wait_queue_head_t open_wait ;
     wait_queue_head_t close_wait ;
     wait_queue_head_t delta_msr_wait ;
     unsigned long flags ;
     unsigned char console : 1 ;
     struct mutex mutex ;
     struct mutex buf_mutex ;
     unsigned char *xmit_buf ;
     unsigned int close_delay ;
     unsigned int closing_wait ;
     int drain_delay ;
     struct kref kref ;
  };
  #line 243 "include/linux/tty.h"
  struct tty_struct {
     int magic ;
     struct kref kref ;
     struct device *dev ;
     struct tty_driver *driver ;
     struct tty_operations  const  *ops ;
     int index ;
     struct mutex ldisc_mutex ;
     struct tty_ldisc *ldisc ;
     struct mutex termios_mutex ;
     spinlock_t ctrl_lock ;
     struct ktermios *termios ;
     struct ktermios *termios_locked ;
     struct termiox *termiox ;
     char name[64U] ;
     struct pid *pgrp ;
     struct pid *session ;
     unsigned long flags ;
     int count ;
     struct winsize winsize ;
     unsigned char stopped : 1 ;
     unsigned char hw_stopped : 1 ;
     unsigned char flow_stopped : 1 ;
     unsigned char packet : 1 ;
     unsigned char low_latency : 1 ;
     unsigned char warned : 1 ;
     unsigned char ctrl_status ;
     unsigned int receive_room ;
     struct tty_struct *link ;
     struct fasync_struct *fasync ;
     struct tty_bufhead buf ;
     int alt_speed ;
     wait_queue_head_t write_wait ;
     wait_queue_head_t read_wait ;
     struct work_struct hangup_work ;
     void *disc_data ;
     void *driver_data ;
     struct list_head tty_files ;
     unsigned int column ;
     unsigned char lnext : 1 ;
     unsigned char erasing : 1 ;
     unsigned char raw : 1 ;
     unsigned char real_raw : 1 ;
     unsigned char icanon : 1 ;
     unsigned char closing : 1 ;
     unsigned char echo_overrun : 1 ;
     unsigned short minimum_to_wake ;
     unsigned long overrun_time ;
     int num_overrun ;
     unsigned long process_char_map[4U] ;
     char *read_buf ;
     int read_head ;
     int read_tail ;
     int read_cnt ;
     unsigned long read_flags[64U] ;
     unsigned char *echo_buf ;
     unsigned int echo_pos ;
     unsigned int echo_cnt ;
     int canon_data ;
     unsigned long canon_head ;
     unsigned int canon_column ;
     struct mutex atomic_read_lock ;
     struct mutex atomic_write_lock ;
     struct mutex output_lock ;
     struct mutex echo_lock ;
     unsigned char *write_buf ;
     int write_cnt ;
     spinlock_t read_lock ;
     struct work_struct SAK_work ;
     struct tty_port *port ;
  };
  #line 308 "include/linux/kgdb.h"
  struct fb_fix_screeninfo {
     char id[16U] ;
     unsigned long smem_start ;
     __u32 smem_len ;
     __u32 type ;
     __u32 type_aux ;
     __u32 visual ;
     __u16 xpanstep ;
     __u16 ypanstep ;
     __u16 ywrapstep ;
     __u32 line_length ;
     unsigned long mmio_start ;
     __u32 mmio_len ;
     __u32 accel ;
     __u16 reserved[3U] ;
  };
  #line 176 "include/linux/fb.h"
  struct fb_bitfield {
     __u32 offset ;
     __u32 length ;
     __u32 msb_right ;
  };
  #line 192 "include/linux/fb.h"
  struct fb_var_screeninfo {
     __u32 xres ;
     __u32 yres ;
     __u32 xres_virtual ;
     __u32 yres_virtual ;
     __u32 xoffset ;
     __u32 yoffset ;
     __u32 bits_per_pixel ;
     __u32 grayscale ;
     struct fb_bitfield red ;
     struct fb_bitfield green ;
     struct fb_bitfield blue ;
     struct fb_bitfield transp ;
     __u32 nonstd ;
     __u32 activate ;
     __u32 height ;
     __u32 width ;
     __u32 accel_flags ;
     __u32 pixclock ;
     __u32 left_margin ;
     __u32 right_margin ;
     __u32 upper_margin ;
     __u32 lower_margin ;
     __u32 hsync_len ;
     __u32 vsync_len ;
     __u32 sync ;
     __u32 vmode ;
     __u32 rotate ;
     __u32 reserved[5U] ;
  };
  #line 278 "include/linux/fb.h"
  struct fb_cmap {
     __u32 start ;
     __u32 len ;
     __u16 *red ;
     __u16 *green ;
     __u16 *blue ;
     __u16 *transp ;
  };
  #line 334 "include/linux/fb.h"
  struct fb_copyarea {
     __u32 dx ;
     __u32 dy ;
     __u32 width ;
     __u32 height ;
     __u32 sx ;
     __u32 sy ;
  };
  #line 347 "include/linux/fb.h"
  struct fb_fillrect {
     __u32 dx ;
     __u32 dy ;
     __u32 width ;
     __u32 height ;
     __u32 color ;
     __u32 rop ;
  };
  #line 356 "include/linux/fb.h"
  struct fb_image {
     __u32 dx ;
     __u32 dy ;
     __u32 width ;
     __u32 height ;
     __u32 fg_color ;
     __u32 bg_color ;
     __u8 depth ;
     char const   *data ;
     struct fb_cmap cmap ;
  };
  #line 368 "include/linux/fb.h"
  struct fbcurpos {
     __u16 x ;
     __u16 y ;
  };
  #line 384 "include/linux/fb.h"
  struct fb_cursor {
     __u16 set ;
     __u16 enable ;
     __u16 rop ;
     char const   *mask ;
     struct fbcurpos hot ;
     struct fb_image image ;
  };
  #line 398
  enum backlight_type {
      BACKLIGHT_RAW = 1,
      BACKLIGHT_PLATFORM = 2,
      BACKLIGHT_FIRMWARE = 3,
      BACKLIGHT_TYPE_MAX = 4
  } ;
  #line 405
  struct backlight_device;
  #line 405
  struct backlight_device;
  #line 406
  struct fb_info;
  #line 406
  struct fb_info;
  #line 407 "include/linux/fb.h"
  struct backlight_ops {
     unsigned int options ;
     int (*update_status)(struct backlight_device * ) ;
     int (*get_brightness)(struct backlight_device * ) ;
     int (*check_fb)(struct backlight_device * , struct fb_info * ) ;
  };
  #line 59 "include/linux/backlight.h"
  struct backlight_properties {
     int brightness ;
     int max_brightness ;
     int power ;
     int fb_blank ;
     enum backlight_type type ;
     unsigned int state ;
  };
  #line 78 "include/linux/backlight.h"
  struct backlight_device {
     struct backlight_properties props ;
     struct mutex update_lock ;
     struct mutex ops_lock ;
     struct backlight_ops  const  *ops ;
     struct notifier_block fb_notif ;
     struct device dev ;
  };
  #line 136 "include/linux/backlight.h"
  struct fb_chroma {
     __u32 redx ;
     __u32 greenx ;
     __u32 bluex ;
     __u32 whitex ;
     __u32 redy ;
     __u32 greeny ;
     __u32 bluey ;
     __u32 whitey ;
  };
  #line 452 "include/linux/fb.h"
  struct fb_videomode;
  #line 452
  struct fb_videomode;
  #line 452 "include/linux/fb.h"
  struct fb_monspecs {
     struct fb_chroma chroma ;
     struct fb_videomode *modedb ;
     __u8 manufacturer[4U] ;
     __u8 monitor[14U] ;
     __u8 serial_no[14U] ;
     __u8 ascii[14U] ;
     __u32 modedb_len ;
     __u32 model ;
     __u32 serial ;
     __u32 year ;
     __u32 week ;
     __u32 hfmin ;
     __u32 hfmax ;
     __u32 dclkmin ;
     __u32 dclkmax ;
     __u16 input ;
     __u16 dpms ;
     __u16 signal ;
     __u16 vfmin ;
     __u16 vfmax ;
     __u16 gamma ;
     unsigned char gtf : 1 ;
     __u16 misc ;
     __u8 version ;
     __u8 revision ;
     __u8 max_x ;
     __u8 max_y ;
  };
  #line 557 "include/linux/fb.h"
  struct fb_blit_caps {
     u32 x ;
     u32 y ;
     u32 len ;
     u32 flags ;
  };
  #line 568 "include/linux/fb.h"
  struct fb_pixmap {
     u8 *addr ;
     u32 size ;
     u32 offset ;
     u32 buf_align ;
     u32 scan_align ;
     u32 access_align ;
     u32 flags ;
     u32 blit_x ;
     u32 blit_y ;
     void (*writeio)(struct fb_info * , void * , void * , unsigned int  ) ;
     void (*readio)(struct fb_info * , void * , void * , unsigned int  ) ;
  };
  #line 597 "include/linux/fb.h"
  struct fb_deferred_io {
     unsigned long delay ;
     struct mutex lock ;
     struct list_head pagelist ;
     void (*deferred_io)(struct fb_info * , struct list_head * ) ;
  };
  #line 607 "include/linux/fb.h"
  struct fb_ops {
     struct module *owner ;
     int (*fb_open)(struct fb_info * , int  ) ;
     int (*fb_release)(struct fb_info * , int  ) ;
     ssize_t (*fb_read)(struct fb_info * , char * , size_t  , loff_t * ) ;
     ssize_t (*fb_write)(struct fb_info * , char const   * , size_t  , loff_t * ) ;
     int (*fb_check_var)(struct fb_var_screeninfo * , struct fb_info * ) ;
     int (*fb_set_par)(struct fb_info * ) ;
     int (*fb_setcolreg)(unsigned int  , unsigned int  , unsigned int  , unsigned int  ,
                         unsigned int  , struct fb_info * ) ;
     int (*fb_setcmap)(struct fb_cmap * , struct fb_info * ) ;
     int (*fb_blank)(int  , struct fb_info * ) ;
     int (*fb_pan_display)(struct fb_var_screeninfo * , struct fb_info * ) ;
     void (*fb_fillrect)(struct fb_info * , struct fb_fillrect  const  * ) ;
     void (*fb_copyarea)(struct fb_info * , struct fb_copyarea  const  * ) ;
     void (*fb_imageblit)(struct fb_info * , struct fb_image  const  * ) ;
     int (*fb_cursor)(struct fb_info * , struct fb_cursor * ) ;
     void (*fb_rotate)(struct fb_info * , int  ) ;
     int (*fb_sync)(struct fb_info * ) ;
     int (*fb_ioctl)(struct fb_info * , unsigned int  , unsigned long  ) ;
     int (*fb_compat_ioctl)(struct fb_info * , unsigned int  , unsigned long  ) ;
     int (*fb_mmap)(struct fb_info * , struct vm_area_struct * ) ;
     void (*fb_get_caps)(struct fb_info * , struct fb_blit_caps * , struct fb_var_screeninfo * ) ;
     void (*fb_destroy)(struct fb_info * ) ;
     int (*fb_debug_enter)(struct fb_info * ) ;
     int (*fb_debug_leave)(struct fb_info * ) ;
  };
  #line 695 "include/linux/fb.h"
  struct fb_tilemap {
     __u32 width ;
     __u32 height ;
     __u32 depth ;
     __u32 length ;
     __u8 const   *data ;
  };
  #line 711 "include/linux/fb.h"
  struct fb_tilerect {
     __u32 sx ;
     __u32 sy ;
     __u32 width ;
     __u32 height ;
     __u32 index ;
     __u32 fg ;
     __u32 bg ;
     __u32 rop ;
  };
  #line 723 "include/linux/fb.h"
  struct fb_tilearea {
     __u32 sx ;
     __u32 sy ;
     __u32 dx ;
     __u32 dy ;
     __u32 width ;
     __u32 height ;
  };
  #line 732 "include/linux/fb.h"
  struct fb_tileblit {
     __u32 sx ;
     __u32 sy ;
     __u32 width ;
     __u32 height ;
     __u32 fg ;
     __u32 bg ;
     __u32 length ;
     __u32 *indices ;
  };
  #line 743 "include/linux/fb.h"
  struct fb_tilecursor {
     __u32 sx ;
     __u32 sy ;
     __u32 mode ;
     __u32 shape ;
     __u32 fg ;
     __u32 bg ;
  };
  #line 752 "include/linux/fb.h"
  struct fb_tile_ops {
     void (*fb_settile)(struct fb_info * , struct fb_tilemap * ) ;
     void (*fb_tilecopy)(struct fb_info * , struct fb_tilearea * ) ;
     void (*fb_tilefill)(struct fb_info * , struct fb_tilerect * ) ;
     void (*fb_tileblit)(struct fb_info * , struct fb_tileblit * ) ;
     void (*fb_tilecursor)(struct fb_info * , struct fb_tilecursor * ) ;
     int (*fb_get_tilemax)(struct fb_info * ) ;
  };
  #line 771 "include/linux/fb.h"
  struct aperture {
     resource_size_t base ;
     resource_size_t size ;
  };
  #line 890 "include/linux/fb.h"
  struct apertures_struct {
     unsigned int count ;
     struct aperture ranges[0U] ;
  };
  #line 891 "include/linux/fb.h"
  struct fb_info {
     atomic_t count ;
     int node ;
     int flags ;
     struct mutex lock ;
     struct mutex mm_lock ;
     struct fb_var_screeninfo var ;
     struct fb_fix_screeninfo fix ;
     struct fb_monspecs monspecs ;
     struct work_struct queue ;
     struct fb_pixmap pixmap ;
     struct fb_pixmap sprite ;
     struct fb_cmap cmap ;
     struct list_head modelist ;
     struct fb_videomode *mode ;
     struct backlight_device *bl_dev ;
     struct mutex bl_curve_mutex ;
     u8 bl_curve[128U] ;
     struct delayed_work deferred_work ;
     struct fb_deferred_io *fbdefio ;
     struct fb_ops *fbops ;
     struct device *device ;
     struct device *dev ;
     int class_flag ;
     struct fb_tile_ops *tileops ;
     char *screen_base ;
     unsigned long screen_size ;
     void *pseudo_palette ;
     u32 state ;
     void *fbcon_par ;
     void *par ;
     struct apertures_struct *apertures ;
  };
  #line 1138 "include/linux/fb.h"
  struct fb_videomode {
     char const   *name ;
     u32 refresh ;
     u32 xres ;
     u32 yres ;
     u32 pixclock ;
     u32 left_margin ;
     u32 right_margin ;
     u32 upper_margin ;
     u32 lower_margin ;
     u32 hsync_len ;
     u32 vsync_len ;
     u32 sync ;
     u32 vmode ;
     u32 flag ;
  };
  #line 1166
  struct drm_mode_set;
  #line 1166
  struct drm_mode_set;
  #line 1167
  struct drm_framebuffer;
  #line 1167
  struct drm_framebuffer;
  #line 1168 "include/linux/fb.h"
  struct drm_mode_object {
     uint32_t id ;
     uint32_t type ;
  };
  #line 52 "include/drm/drm_crtc.h"
  enum drm_mode_status {
      MODE_OK = 0,
      MODE_HSYNC = 1,
      MODE_VSYNC = 2,
      MODE_H_ILLEGAL = 3,
      MODE_V_ILLEGAL = 4,
      MODE_BAD_WIDTH = 5,
      MODE_NOMODE = 6,
      MODE_NO_INTERLACE = 7,
      MODE_NO_DBLESCAN = 8,
      MODE_NO_VSCAN = 9,
      MODE_MEM = 10,
      MODE_VIRTUAL_X = 11,
      MODE_VIRTUAL_Y = 12,
      MODE_MEM_VIRT = 13,
      MODE_NOCLOCK = 14,
      MODE_CLOCK_HIGH = 15,
      MODE_CLOCK_LOW = 16,
      MODE_CLOCK_RANGE = 17,
      MODE_BAD_HVALUE = 18,
      MODE_BAD_VVALUE = 19,
      MODE_BAD_VSCAN = 20,
      MODE_HSYNC_NARROW = 21,
      MODE_HSYNC_WIDE = 22,
      MODE_HBLANK_NARROW = 23,
      MODE_HBLANK_WIDE = 24,
      MODE_VSYNC_NARROW = 25,
      MODE_VSYNC_WIDE = 26,
      MODE_VBLANK_NARROW = 27,
      MODE_VBLANK_WIDE = 28,
      MODE_PANEL = 29,
      MODE_INTERLACE_WIDTH = 30,
      MODE_ONE_WIDTH = 31,
      MODE_ONE_HEIGHT = 32,
      MODE_ONE_SIZE = 33,
      MODE_NO_REDUCED = 34,
      MODE_UNVERIFIED = -3,
      MODE_BAD = -2,
      MODE_ERROR = -1
  } ;
  #line 93 "include/drm/drm_crtc.h"
  struct drm_display_mode {
     struct list_head head ;
     struct drm_mode_object base ;
     char name[32U] ;
     int connector_count ;
     enum drm_mode_status status ;
     int type ;
     int clock ;
     int hdisplay ;
     int hsync_start ;
     int hsync_end ;
     int htotal ;
     int hskew ;
     int vdisplay ;
     int vsync_start ;
     int vsync_end ;
     int vtotal ;
     int vscan ;
     unsigned int flags ;
     int width_mm ;
     int height_mm ;
     int clock_index ;
     int synth_clock ;
     int crtc_hdisplay ;
     int crtc_hblank_start ;
     int crtc_hblank_end ;
     int crtc_hsync_start ;
     int crtc_hsync_end ;
     int crtc_htotal ;
     int crtc_hskew ;
     int crtc_vdisplay ;
     int crtc_vblank_start ;
     int crtc_vblank_end ;
     int crtc_vsync_start ;
     int crtc_vsync_end ;
     int crtc_vtotal ;
     int crtc_hadjusted ;
     int crtc_vadjusted ;
     int private_size ;
     int *private ;
     int private_flags ;
     int vrefresh ;
     int hsync ;
  };
  #line 170
  enum drm_connector_status {
      connector_status_connected = 1,
      connector_status_disconnected = 2,
      connector_status_unknown = 3
  } ;
  #line 176
  enum subpixel_order {
      SubPixelUnknown = 0,
      SubPixelHorizontalRGB = 1,
      SubPixelHorizontalBGR = 2,
      SubPixelVerticalRGB = 3,
      SubPixelVerticalBGR = 4,
      SubPixelNone = 5
  } ;
  #line 185 "include/drm/drm_crtc.h"
  struct drm_display_info {
     char name[32U] ;
     unsigned int width_mm ;
     unsigned int height_mm ;
     unsigned int min_vfreq ;
     unsigned int max_vfreq ;
     unsigned int min_hfreq ;
     unsigned int max_hfreq ;
     unsigned int pixel_clock ;
     unsigned int bpc ;
     enum subpixel_order subpixel_order ;
     u32 color_formats ;
     char *raw_edid ;
  };
  #line 210 "include/drm/drm_crtc.h"
  struct drm_framebuffer_funcs {
     void (*destroy)(struct drm_framebuffer * ) ;
     int (*create_handle)(struct drm_framebuffer * , struct drm_file * , unsigned int * ) ;
     int (*dirty)(struct drm_framebuffer * , struct drm_file * , unsigned int  , unsigned int  ,
                  struct drm_clip_rect * , unsigned int  ) ;
  };
  #line 230 "include/drm/drm_crtc.h"
  struct drm_framebuffer {
     struct drm_device *dev ;
     struct list_head head ;
     struct drm_mode_object base ;
     struct drm_framebuffer_funcs  const  *funcs ;
     unsigned int pitch ;
     unsigned int width ;
     unsigned int height ;
     unsigned int depth ;
     int bits_per_pixel ;
     int flags ;
     struct list_head filp_head ;
     void *helper_private ;
  };
  #line 250 "include/drm/drm_crtc.h"
  struct drm_property_blob {
     struct drm_mode_object base ;
     struct list_head head ;
     unsigned int length ;
     void *data ;
  };
  #line 263 "include/drm/drm_crtc.h"
  struct drm_property {
     struct list_head head ;
     struct drm_mode_object base ;
     uint32_t flags ;
     char name[32U] ;
     uint32_t num_values ;
     uint64_t *values ;
     struct list_head enum_blob_list ;
  };
  #line 274
  struct drm_crtc;
  #line 274
  struct drm_crtc;
  #line 275
  struct drm_connector;
  #line 275
  struct drm_connector;
  #line 276
  struct drm_encoder;
  #line 276
  struct drm_encoder;
  #line 277
  struct drm_pending_vblank_event;
  #line 277
  struct drm_pending_vblank_event;
  #line 278 "include/drm/drm_crtc.h"
  struct drm_crtc_funcs {
     void (*save)(struct drm_crtc * ) ;
     void (*restore)(struct drm_crtc * ) ;
     void (*reset)(struct drm_crtc * ) ;
     int (*cursor_set)(struct drm_crtc * , struct drm_file * , uint32_t  , uint32_t  ,
                       uint32_t  ) ;
     int (*cursor_move)(struct drm_crtc * , int  , int  ) ;
     void (*gamma_set)(struct drm_crtc * , u16 * , u16 * , u16 * , uint32_t  , uint32_t  ) ;
     void (*destroy)(struct drm_crtc * ) ;
     int (*set_config)(struct drm_mode_set * ) ;
     int (*page_flip)(struct drm_crtc * , struct drm_framebuffer * , struct drm_pending_vblank_event * ) ;
  };
  #line 337 "include/drm/drm_crtc.h"
  struct drm_crtc {
     struct drm_device *dev ;
     struct list_head head ;
     struct drm_mode_object base ;
     struct drm_framebuffer *fb ;
     bool enabled ;
     struct drm_display_mode mode ;
     struct drm_display_mode hwmode ;
     int x ;
     int y ;
     struct drm_crtc_funcs  const  *funcs ;
     uint32_t gamma_size ;
     uint16_t *gamma_store ;
     s64 framedur_ns ;
     s64 linedur_ns ;
     s64 pixeldur_ns ;
     void *helper_private ;
  };
  #line 382 "include/drm/drm_crtc.h"
  struct drm_connector_funcs {
     void (*dpms)(struct drm_connector * , int  ) ;
     void (*save)(struct drm_connector * ) ;
     void (*restore)(struct drm_connector * ) ;
     void (*reset)(struct drm_connector * ) ;
     enum drm_connector_status (*detect)(struct drm_connector * , bool  ) ;
     int (*fill_modes)(struct drm_connector * , uint32_t  , uint32_t  ) ;
     int (*set_property)(struct drm_connector * , struct drm_property * , uint64_t  ) ;
     void (*destroy)(struct drm_connector * ) ;
     void (*force)(struct drm_connector * ) ;
  };
  #line 423 "include/drm/drm_crtc.h"
  struct drm_encoder_funcs {
     void (*reset)(struct drm_encoder * ) ;
     void (*destroy)(struct drm_encoder * ) ;
  };
  #line 428 "include/drm/drm_crtc.h"
  struct drm_encoder {
     struct drm_device *dev ;
     struct list_head head ;
     struct drm_mode_object base ;
     int encoder_type ;
     uint32_t possible_crtcs ;
     uint32_t possible_clones ;
     struct drm_crtc *crtc ;
     struct drm_encoder_funcs  const  *funcs ;
     void *helper_private ;
  };
  #line 450
  enum drm_connector_force {
      DRM_FORCE_UNSPECIFIED = 0,
      DRM_FORCE_OFF = 1,
      DRM_FORCE_ON = 2,
      DRM_FORCE_ON_DIGITAL = 3
  } ;
  #line 457 "include/drm/drm_crtc.h"
  struct drm_connector {
     struct drm_device *dev ;
     struct device kdev ;
     struct device_attribute *attr ;
     struct list_head head ;
     struct drm_mode_object base ;
     int connector_type ;
     int connector_type_id ;
     bool interlace_allowed ;
     bool doublescan_allowed ;
     struct list_head modes ;
     int initial_x ;
     int initial_y ;
     enum drm_connector_status status ;
     struct list_head probed_modes ;
     struct drm_display_info display_info ;
     struct drm_connector_funcs  const  *funcs ;
     struct list_head user_modes ;
     struct drm_property_blob *edid_blob_ptr ;
     u32 property_ids[16U] ;
     uint64_t property_values[16U] ;
     uint8_t polled ;
     int dpms ;
     void *helper_private ;
     enum drm_connector_force force ;
     uint32_t encoder_ids[2U] ;
     uint32_t force_encoder_id ;
     struct drm_encoder *encoder ;
     int null_edid_counter ;
  };
  #line 526 "include/drm/drm_crtc.h"
  struct drm_mode_set {
     struct list_head head ;
     struct drm_framebuffer *fb ;
     struct drm_crtc *crtc ;
     struct drm_display_mode *mode ;
     uint32_t x ;
     uint32_t y ;
     struct drm_connector **connectors ;
     size_t num_connectors ;
  };
  #line 548 "include/drm/drm_crtc.h"
  struct drm_mode_config_funcs {
     struct drm_framebuffer *(*fb_create)(struct drm_device * , struct drm_file * ,
                                          struct drm_mode_fb_cmd * ) ;
     void (*output_poll_changed)(struct drm_device * ) ;
  };
  #line 556 "include/drm/drm_crtc.h"
  struct drm_mode_group {
     uint32_t num_crtcs ;
     uint32_t num_encoders ;
     uint32_t num_connectors ;
     uint32_t *id_list ;
  };
  #line 565 "include/drm/drm_crtc.h"
  struct drm_mode_config {
     struct mutex mutex ;
     struct mutex idr_mutex ;
     struct idr crtc_idr ;
     int num_fb ;
     struct list_head fb_list ;
     int num_connector ;
     struct list_head connector_list ;
     int num_encoder ;
     struct list_head encoder_list ;
     int num_crtc ;
     struct list_head crtc_list ;
     struct list_head property_list ;
     int min_width ;
     int min_height ;
     int max_width ;
     int max_height ;
     struct drm_mode_config_funcs *funcs ;
     resource_size_t fb_base ;
     bool poll_enabled ;
     struct delayed_work output_poll_work ;
     struct list_head property_blob_list ;
     struct drm_property *edid_property ;
     struct drm_property *dpms_property ;
     struct drm_property *dvi_i_subconnector_property ;
     struct drm_property *dvi_i_select_subconnector_property ;
     struct drm_property *tv_subconnector_property ;
     struct drm_property *tv_select_subconnector_property ;
     struct drm_property *tv_mode_property ;
     struct drm_property *tv_left_margin_property ;
     struct drm_property *tv_right_margin_property ;
     struct drm_property *tv_top_margin_property ;
     struct drm_property *tv_bottom_margin_property ;
     struct drm_property *tv_brightness_property ;
     struct drm_property *tv_contrast_property ;
     struct drm_property *tv_flicker_reduction_property ;
     struct drm_property *tv_overscan_property ;
     struct drm_property *tv_saturation_property ;
     struct drm_property *tv_hue_property ;
     struct drm_property *scaling_mode_property ;
     struct drm_property *dithering_mode_property ;
     struct drm_property *dirty_info_property ;
  };
  #line 814 "include/drm/drm_crtc.h"
  struct drm_master {
     struct kref refcount ;
     struct list_head head ;
     struct drm_minor *minor ;
     char *unique ;
     int unique_len ;
     int unique_size ;
     int blocked ;
     struct drm_open_hash magiclist ;
     struct list_head magicfree ;
     struct drm_lock_data lock ;
     void *driver_priv ;
  };
  #line 682 "include/drm/drmP.h"
  struct drm_bus {
     int bus_type ;
     int (*get_irq)(struct drm_device * ) ;
     char const   *(*get_name)(struct drm_device * ) ;
     int (*set_busid)(struct drm_device * , struct drm_master * ) ;
     int (*set_unique)(struct drm_device * , struct drm_master * , struct drm_unique * ) ;
     int (*irq_by_busid)(struct drm_device * , struct drm_irq_busid * ) ;
     int (*agp_init)(struct drm_device * ) ;
  };
  #line 709
  struct usb_driver;
  #line 709
  struct usb_driver;
  #line 709 "include/drm/drmP.h"
  union __anonunion_kdriver_183 {
     struct pci_driver *pci ;
     struct platform_device *platform_device ;
     struct usb_driver *usb ;
  };
  #line 709 "include/drm/drmP.h"
  struct drm_driver {
     int (*load)(struct drm_device * , unsigned long  ) ;
     int (*firstopen)(struct drm_device * ) ;
     int (*open)(struct drm_device * , struct drm_file * ) ;
     void (*preclose)(struct drm_device * , struct drm_file * ) ;
     void (*postclose)(struct drm_device * , struct drm_file * ) ;
     void (*lastclose)(struct drm_device * ) ;
     int (*unload)(struct drm_device * ) ;
     int (*suspend)(struct drm_device * , pm_message_t  ) ;
     int (*resume)(struct drm_device * ) ;
     int (*dma_ioctl)(struct drm_device * , void * , struct drm_file * ) ;
     int (*dma_quiescent)(struct drm_device * ) ;
     int (*context_dtor)(struct drm_device * , int  ) ;
     u32 (*get_vblank_counter)(struct drm_device * , int  ) ;
     int (*enable_vblank)(struct drm_device * , int  ) ;
     void (*disable_vblank)(struct drm_device * , int  ) ;
     int (*device_is_agp)(struct drm_device * ) ;
     int (*get_scanout_position)(struct drm_device * , int  , int * , int * ) ;
     int (*get_vblank_timestamp)(struct drm_device * , int  , int * , struct timeval * ,
                                 unsigned int  ) ;
     irqreturn_t (*irq_handler)(int  , void * ) ;
     void (*irq_preinstall)(struct drm_device * ) ;
     int (*irq_postinstall)(struct drm_device * ) ;
     void (*irq_uninstall)(struct drm_device * ) ;
     void (*reclaim_buffers)(struct drm_device * , struct drm_file * ) ;
     void (*reclaim_buffers_locked)(struct drm_device * , struct drm_file * ) ;
     void (*reclaim_buffers_idlelocked)(struct drm_device * , struct drm_file * ) ;
     void (*set_version)(struct drm_device * , struct drm_set_version * ) ;
     int (*master_create)(struct drm_device * , struct drm_master * ) ;
     void (*master_destroy)(struct drm_device * , struct drm_master * ) ;
     int (*master_set)(struct drm_device * , struct drm_file * , bool  ) ;
     void (*master_drop)(struct drm_device * , struct drm_file * , bool  ) ;
     int (*debugfs_init)(struct drm_minor * ) ;
     void (*debugfs_cleanup)(struct drm_minor * ) ;
     int (*gem_init_object)(struct drm_gem_object * ) ;
     void (*gem_free_object)(struct drm_gem_object * ) ;
     void (*vgaarb_irq)(struct drm_device * , bool  ) ;
     int (*dumb_create)(struct drm_file * , struct drm_device * , struct drm_mode_create_dumb * ) ;
     int (*dumb_map_offset)(struct drm_file * , struct drm_device * , uint32_t  , uint64_t * ) ;
     int (*dumb_destroy)(struct drm_file * , struct drm_device * , uint32_t  ) ;
     struct vm_operations_struct *gem_vm_ops ;
     int major ;
     int minor ;
     int patchlevel ;
     char *name ;
     char *desc ;
     char *date ;
     u32 driver_features ;
     int dev_priv_size ;
     struct drm_ioctl_desc *ioctls ;
     int num_ioctls ;
     struct file_operations fops ;
     union __anonunion_kdriver_183 kdriver ;
     struct drm_bus *bus ;
     struct list_head device_list ;
  };
  #line 955 "include/drm/drmP.h"
  struct drm_info_list {
     char const   *name ;
     int (*show)(struct seq_file * , void * ) ;
     u32 driver_features ;
     void *data ;
  };
  #line 966 "include/drm/drmP.h"
  struct drm_info_node {
     struct list_head list ;
     struct drm_minor *minor ;
     struct drm_info_list *info_ent ;
     struct dentry *dent ;
  };
  #line 976 "include/drm/drmP.h"
  struct drm_minor {
     int index ;
     int type ;
     dev_t device ;
     struct device kdev ;
     struct drm_device *dev ;
     struct proc_dir_entry *proc_root ;
     struct drm_info_node proc_nodes ;
     struct dentry *debugfs_root ;
     struct drm_info_node debugfs_nodes ;
     struct drm_master *master ;
     struct list_head master_list ;
     struct drm_mode_group mode_group ;
  };
  #line 996 "include/drm/drmP.h"
  struct drm_cmdline_mode {
     bool specified ;
     bool refresh_specified ;
     bool bpp_specified ;
     int xres ;
     int yres ;
     int bpp ;
     int refresh ;
     bool rb ;
     bool interlace ;
     bool cvt ;
     bool margins ;
     enum drm_connector_force force ;
  };
  #line 1011 "include/drm/drmP.h"
  struct drm_pending_vblank_event {
     struct drm_pending_event base ;
     int pipe ;
     struct drm_event_vblank event ;
  };
  #line 1018
  struct usb_device;
  #line 1018
  struct usb_device;
  #line 1018 "include/drm/drmP.h"
  struct drm_device {
     struct list_head driver_item ;
     char *devname ;
     int if_version ;
     spinlock_t count_lock ;
     struct mutex struct_mutex ;
     int open_count ;
     atomic_t ioctl_count ;
     atomic_t vma_count ;
     int buf_use ;
     atomic_t buf_alloc ;
     unsigned long counters ;
     enum drm_stat_type types[15U] ;
     atomic_t counts[15U] ;
     struct list_head filelist ;
     struct list_head maplist ;
     int map_count ;
     struct drm_open_hash map_hash ;
     struct list_head ctxlist ;
     int ctx_count ;
     struct mutex ctxlist_mutex ;
     struct idr ctx_idr ;
     struct list_head vmalist ;
     int queue_count ;
     int queue_reserved ;
     int queue_slots ;
     struct drm_queue **queuelist ;
     struct drm_device_dma *dma ;
     int irq_enabled ;
     long volatile   context_flag ;
     long volatile   interrupt_flag ;
     long volatile   dma_flag ;
     wait_queue_head_t context_wait ;
     int last_checked ;
     int last_context ;
     unsigned long last_switch ;
     struct work_struct work ;
     int vblank_disable_allowed ;
     wait_queue_head_t *vbl_queue ;
     atomic_t *_vblank_count ;
     struct timeval *_vblank_time ;
     spinlock_t vblank_time_lock ;
     spinlock_t vbl_lock ;
     atomic_t *vblank_refcount ;
     u32 *last_vblank ;
     int *vblank_enabled ;
     int *vblank_inmodeset ;
     u32 *last_vblank_wait ;
     struct timer_list vblank_disable_timer ;
     u32 max_vblank_count ;
     struct list_head vblank_event_list ;
     spinlock_t event_lock ;
     cycles_t ctx_start ;
     cycles_t lck_start ;
     struct fasync_struct *buf_async ;
     wait_queue_head_t buf_readers ;
     wait_queue_head_t buf_writers ;
     struct drm_agp_head *agp ;
     struct device *dev ;
     struct pci_dev *pdev ;
     int pci_vendor ;
     int pci_device ;
     struct platform_device *platformdev ;
     struct usb_device *usbdev ;
     struct drm_sg_mem *sg ;
     unsigned int num_crtcs ;
     void *dev_private ;
     void *mm_private ;
     struct address_space *dev_mapping ;
     struct drm_sigdata sigdata ;
     sigset_t sigmask ;
     struct drm_driver *driver ;
     struct drm_local_map *agp_buffer_map ;
     unsigned int agp_buffer_token ;
     struct drm_minor *control ;
     struct drm_minor *primary ;
     struct drm_mode_config mode_config ;
     spinlock_t object_name_lock ;
     struct idr object_name_idr ;
     int switch_power_state ;
  };
  #line 588 "include/drm/i915_drm.h"
  struct drm_i915_gem_exec_object2 {
     __u32 handle ;
     __u32 relocation_count ;
     __u64 relocs_ptr ;
     __u64 alignment ;
     __u64 offset ;
     __u64 flags ;
     __u64 rsvd1 ;
     __u64 rsvd2 ;
  };
  #line 138 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct child_device_config {
     u16 handle ;
     u16 device_type ;
     u8 i2c_speed ;
     u8 rsvd[9U] ;
     u16 addin_offset ;
     u8 dvo_port ;
     u8 i2c_pin ;
     u8 slave_addr ;
     u8 ddc_pin ;
     u16 edid_ptr ;
     u8 dvo_cfg ;
     u8 dvo2_port ;
     u8 i2c2_pin ;
     u8 slave2_addr ;
     u8 ddc2_pin ;
     u8 capabilities ;
     u8 dvo_wiring ;
     u8 dvo2_wiring ;
     u16 extended_type ;
     u8 dvo_function ;
  };
  #line 430 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct edp_power_seq {
     u16 t3 ;
     u16 t7 ;
     u16 t9 ;
     u16 t10 ;
     u16 t12 ;
  };
  #line 479
  struct drm_i915_gem_object;
  #line 479
  struct drm_i915_gem_object;
  #line 479 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct intel_hw_status_page {
     u32 *page_addr ;
     unsigned int gfx_addr ;
     struct drm_i915_gem_object *obj ;
  };
  #line 16 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
  enum intel_ring_id {
      RING_RENDER = 1,
      RING_BSD = 2,
      RING_BLT = 4
  } ;
  #line 22 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
  struct intel_ring_buffer {
     char const   *name ;
     enum intel_ring_id id ;
     u32 mmio_base ;
     void *virtual_start ;
     struct drm_device *dev ;
     struct drm_i915_gem_object *obj ;
     u32 head ;
     u32 tail ;
     int space ;
     int size ;
     int effective_size ;
     struct intel_hw_status_page status_page ;
     spinlock_t irq_lock ;
     u32 irq_refcount ;
     u32 irq_mask ;
     u32 irq_seqno ;
     u32 trace_irq_seqno ;
     u32 waiting_seqno ;
     u32 sync_seqno[2U] ;
     bool (*irq_get)(struct intel_ring_buffer * ) ;
     void (*irq_put)(struct intel_ring_buffer * ) ;
     int (*init)(struct intel_ring_buffer * ) ;
     void (*write_tail)(struct intel_ring_buffer * , u32  ) ;
     int (*flush)(struct intel_ring_buffer * , u32  , u32  ) ;
     int (*add_request)(struct intel_ring_buffer * , u32 * ) ;
     u32 (*get_seqno)(struct intel_ring_buffer * ) ;
     int (*dispatch_execbuffer)(struct intel_ring_buffer * , u32  , u32  ) ;
     void (*cleanup)(struct intel_ring_buffer * ) ;
     struct list_head active_list ;
     struct list_head request_list ;
     struct list_head gpu_write_list ;
     u32 outstanding_lazy_request ;
     wait_queue_head_t irq_queue ;
     drm_local_map_t map ;
     void *private ;
  };
  #line 202
  struct io_mapping;
  #line 202
  struct io_mapping;
  #line 160 "include/linux/io-mapping.h"
  struct intel_gtt {
     unsigned int stolen_size ;
     unsigned int gtt_total_entries ;
     unsigned int gtt_mappable_entries ;
     unsigned char needs_dmar : 1 ;
  };
  #line 41 "include/drm/intel-gtt.h"
  struct drm_i915_gem_phys_object {
     int id ;
     struct page **page_list ;
     drm_dma_handle_t *handle ;
     struct drm_i915_gem_object *cur_obj ;
  };
  #line 96 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct mem_block {
     struct mem_block *next ;
     struct mem_block *prev ;
     int start ;
     int size ;
     struct drm_file *file_priv ;
  };
  #line 104
  struct opregion_header;
  #line 104
  struct opregion_header;
  #line 105
  struct opregion_acpi;
  #line 105
  struct opregion_acpi;
  #line 106
  struct opregion_swsci;
  #line 106
  struct opregion_swsci;
  #line 107
  struct opregion_asle;
  #line 107
  struct opregion_asle;
  #line 108 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct intel_opregion {
     struct opregion_header *header ;
     struct opregion_acpi *acpi ;
     struct opregion_swsci *swsci ;
     struct opregion_asle *asle ;
     void *vbt ;
     u32 *lid_state ;
  };
  #line 118
  struct intel_overlay;
  #line 118
  struct intel_overlay;
  #line 119
  struct intel_overlay_error_state;
  #line 119
  struct intel_overlay_error_state;
  #line 127 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_fence_reg {
     struct list_head lru_list ;
     struct drm_i915_gem_object *obj ;
     uint32_t setup_seqno ;
  };
  #line 134 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct sdvo_device_mapping {
     u8 initialized ;
     u8 dvo_port ;
     u8 slave_addr ;
     u8 dvo_wiring ;
     u8 i2c_pin ;
     u8 i2c_speed ;
     u8 ddc_pin ;
  };
  #line 144
  struct intel_display_error_state;
  #line 144
  struct intel_display_error_state;
  #line 145 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_error_object {
     int page_count ;
     u32 gtt_offset ;
     u32 *pages[0U] ;
  };
  #line 178 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_error_buffer {
     u32 size ;
     u32 name ;
     u32 seqno ;
     u32 gtt_offset ;
     u32 read_domains ;
     u32 write_domain ;
     signed char fence_reg : 5 ;
     signed char pinned : 2 ;
     unsigned char tiling : 2 ;
     unsigned char dirty : 1 ;
     unsigned char purgeable : 1 ;
     unsigned char ring : 4 ;
     unsigned char cache_level : 2 ;
  };
  #line 193 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_error_state {
     u32 eir ;
     u32 pgtbl_er ;
     u32 pipestat[3U] ;
     u32 ipeir ;
     u32 ipehr ;
     u32 instdone ;
     u32 acthd ;
     u32 error ;
     u32 bcs_acthd ;
     u32 bcs_ipehr ;
     u32 bcs_ipeir ;
     u32 bcs_instdone ;
     u32 bcs_seqno ;
     u32 vcs_acthd ;
     u32 vcs_ipehr ;
     u32 vcs_ipeir ;
     u32 vcs_instdone ;
     u32 vcs_seqno ;
     u32 instpm ;
     u32 instps ;
     u32 instdone1 ;
     u32 seqno ;
     u64 bbaddr ;
     u64 fence[16U] ;
     struct timeval time ;
     struct drm_i915_error_object *ringbuffer[3U] ;
     struct drm_i915_error_object *batchbuffer[3U] ;
     struct drm_i915_error_buffer *active_bo ;
     struct drm_i915_error_buffer *pinned_bo ;
     u32 active_bo_count ;
     u32 pinned_bo_count ;
     struct intel_overlay_error_state *overlay ;
     struct intel_display_error_state *display ;
  };
  #line 197 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_display_funcs {
     void (*dpms)(struct drm_crtc * , int  ) ;
     bool (*fbc_enabled)(struct drm_device * ) ;
     void (*enable_fbc)(struct drm_crtc * , unsigned long  ) ;
     void (*disable_fbc)(struct drm_device * ) ;
     int (*get_display_clock_speed)(struct drm_device * ) ;
     int (*get_fifo_size)(struct drm_device * , int  ) ;
     void (*update_wm)(struct drm_device * ) ;
     int (*crtc_mode_set)(struct drm_crtc * , struct drm_display_mode * , struct drm_display_mode * ,
                          int  , int  , struct drm_framebuffer * ) ;
     void (*fdi_link_train)(struct drm_crtc * ) ;
     void (*init_clock_gating)(struct drm_device * ) ;
     void (*init_pch_clock_gating)(struct drm_device * ) ;
     int (*queue_flip)(struct drm_device * , struct drm_crtc * , struct drm_framebuffer * ,
                       struct drm_i915_gem_object * ) ;
  };
  #line 216 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct intel_device_info {
     u8 gen ;
     unsigned char is_mobile : 1 ;
     unsigned char is_i85x : 1 ;
     unsigned char is_i915g : 1 ;
     unsigned char is_i945gm : 1 ;
     unsigned char is_g33 : 1 ;
     unsigned char need_gfx_hws : 1 ;
     unsigned char is_g4x : 1 ;
     unsigned char is_pineview : 1 ;
     unsigned char is_broadwater : 1 ;
     unsigned char is_crestline : 1 ;
     unsigned char is_ivybridge : 1 ;
     unsigned char has_fbc : 1 ;
     unsigned char has_pipe_cxsr : 1 ;
     unsigned char has_hotplug : 1 ;
     unsigned char cursor_needs_physical : 1 ;
     unsigned char has_overlay : 1 ;
     unsigned char overlay_needs_physical : 1 ;
     unsigned char supports_tv : 1 ;
     unsigned char has_bsd_ring : 1 ;
     unsigned char has_blt_ring : 1 ;
  };
  #line 247
  enum no_fbc_reason {
      FBC_NO_OUTPUT = 0,
      FBC_STOLEN_TOO_SMALL = 1,
      FBC_UNSUPPORTED_MODE = 2,
      FBC_MODE_TOO_LARGE = 3,
      FBC_BAD_PLANE = 4,
      FBC_NOT_TILED = 5,
      FBC_MULTIPLE_PIPES = 6,
      FBC_MODULE_PARAM = 7
  } ;
  #line 258
  enum intel_pch {
      PCH_IBX = 0,
      PCH_CPT = 1
  } ;
  #line 263
  struct intel_fbdev;
  #line 263
  struct intel_fbdev;
  #line 264 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct intel_gmbus {
     struct i2c_adapter adapter ;
     struct i2c_adapter *force_bit ;
     u32 reg0 ;
  };
  #line 284 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct __anonstruct_edp_184 {
     int rate ;
     int lanes ;
     int preemphasis ;
     int vswing ;
     bool initialized ;
     bool support ;
     int bpp ;
     struct edp_power_seq pps ;
  };
  #line 284 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct __anonstruct_mm_185 {
     struct intel_gtt  const  *gtt ;
     struct drm_mm stolen ;
     struct drm_mm gtt_space ;
     struct list_head gtt_list ;
     unsigned long gtt_start ;
     unsigned long gtt_mappable_end ;
     unsigned long gtt_end ;
     struct io_mapping *gtt_mapping ;
     int gtt_mtrr ;
     struct shrinker inactive_shrinker ;
     struct list_head active_list ;
     struct list_head flushing_list ;
     struct list_head inactive_list ;
     struct list_head pinned_list ;
     struct list_head fence_list ;
     struct list_head deferred_free_list ;
     struct delayed_work retire_work ;
     bool interruptible ;
     int suspended ;
     atomic_t wedged ;
     uint32_t bit_6_swizzle_x ;
     uint32_t bit_6_swizzle_y ;
     struct drm_i915_gem_phys_object *phys_objs[3U] ;
     size_t gtt_total ;
     size_t mappable_gtt_total ;
     size_t object_memory ;
     u32 object_count ;
  };
  #line 284 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_private {
     struct drm_device *dev ;
     struct intel_device_info  const  *info ;
     int has_gem ;
     int relative_constants_mode ;
     void *regs ;
     struct intel_gmbus *gmbus ;
     struct pci_dev *bridge_dev ;
     struct intel_ring_buffer ring[3U] ;
     uint32_t next_seqno ;
     drm_dma_handle_t *status_page_dmah ;
     uint32_t counter ;
     drm_local_map_t hws_map ;
     struct drm_i915_gem_object *pwrctx ;
     struct drm_i915_gem_object *renderctx ;
     struct resource mch_res ;
     unsigned int cpp ;
     int back_offset ;
     int front_offset ;
     int current_page ;
     int page_flipping ;
     atomic_t irq_received ;
     spinlock_t irq_lock ;
     u32 pipestat[2U] ;
     u32 irq_mask ;
     u32 gt_irq_mask ;
     u32 pch_irq_mask ;
     u32 hotplug_supported_mask ;
     struct work_struct hotplug_work ;
     int tex_lru_log_granularity ;
     int allow_batchbuffer ;
     struct mem_block *agp_heap ;
     unsigned int sr01 ;
     unsigned int adpa ;
     unsigned int ppcr ;
     unsigned int dvob ;
     unsigned int dvoc ;
     unsigned int lvds ;
     int vblank_pipe ;
     int num_pipe ;
     struct timer_list hangcheck_timer ;
     int hangcheck_count ;
     uint32_t last_acthd ;
     uint32_t last_instdone ;
     uint32_t last_instdone1 ;
     unsigned long cfb_size ;
     unsigned long cfb_pitch ;
     unsigned long cfb_offset ;
     int cfb_fence ;
     int cfb_plane ;
     int cfb_y ;
     struct intel_opregion opregion ;
     struct intel_overlay *overlay ;
     int backlight_level ;
     bool backlight_enabled ;
     struct drm_display_mode *panel_fixed_mode ;
     struct drm_display_mode *lfp_lvds_vbt_mode ;
     struct drm_display_mode *sdvo_lvds_vbt_mode ;
     unsigned char int_tv_support : 1 ;
     unsigned char lvds_dither : 1 ;
     unsigned char lvds_vbt : 1 ;
     unsigned char int_crt_support : 1 ;
     unsigned char lvds_use_ssc : 1 ;
     int lvds_ssc_freq ;
     struct __anonstruct_edp_184 edp ;
     bool no_aux_handshake ;
     struct notifier_block lid_notifier ;
     int crt_ddc_pin ;
     struct drm_i915_fence_reg fence_regs[16U] ;
     int fence_reg_start ;
     int num_fence_regs ;
     unsigned int fsb_freq ;
     unsigned int mem_freq ;
     unsigned int is_ddr3 ;
     spinlock_t error_lock ;
     struct drm_i915_error_state *first_error ;
     struct work_struct error_work ;
     struct completion error_completion ;
     struct workqueue_struct *wq ;
     struct drm_i915_display_funcs display ;
     enum intel_pch pch_type ;
     unsigned long quirks ;
     bool modeset_on_lid ;
     u8 saveLBB ;
     u32 saveDSPACNTR ;
     u32 saveDSPBCNTR ;
     u32 saveDSPARB ;
     u32 saveHWS ;
     u32 savePIPEACONF ;
     u32 savePIPEBCONF ;
     u32 savePIPEASRC ;
     u32 savePIPEBSRC ;
     u32 saveFPA0 ;
     u32 saveFPA1 ;
     u32 saveDPLL_A ;
     u32 saveDPLL_A_MD ;
     u32 saveHTOTAL_A ;
     u32 saveHBLANK_A ;
     u32 saveHSYNC_A ;
     u32 saveVTOTAL_A ;
     u32 saveVBLANK_A ;
     u32 saveVSYNC_A ;
     u32 saveBCLRPAT_A ;
     u32 saveTRANSACONF ;
     u32 saveTRANS_HTOTAL_A ;
     u32 saveTRANS_HBLANK_A ;
     u32 saveTRANS_HSYNC_A ;
     u32 saveTRANS_VTOTAL_A ;
     u32 saveTRANS_VBLANK_A ;
     u32 saveTRANS_VSYNC_A ;
     u32 savePIPEASTAT ;
     u32 saveDSPASTRIDE ;
     u32 saveDSPASIZE ;
     u32 saveDSPAPOS ;
     u32 saveDSPAADDR ;
     u32 saveDSPASURF ;
     u32 saveDSPATILEOFF ;
     u32 savePFIT_PGM_RATIOS ;
     u32 saveBLC_HIST_CTL ;
     u32 saveBLC_PWM_CTL ;
     u32 saveBLC_PWM_CTL2 ;
     u32 saveBLC_CPU_PWM_CTL ;
     u32 saveBLC_CPU_PWM_CTL2 ;
     u32 saveFPB0 ;
     u32 saveFPB1 ;
     u32 saveDPLL_B ;
     u32 saveDPLL_B_MD ;
     u32 saveHTOTAL_B ;
     u32 saveHBLANK_B ;
     u32 saveHSYNC_B ;
     u32 saveVTOTAL_B ;
     u32 saveVBLANK_B ;
     u32 saveVSYNC_B ;
     u32 saveBCLRPAT_B ;
     u32 saveTRANSBCONF ;
     u32 saveTRANS_HTOTAL_B ;
     u32 saveTRANS_HBLANK_B ;
     u32 saveTRANS_HSYNC_B ;
     u32 saveTRANS_VTOTAL_B ;
     u32 saveTRANS_VBLANK_B ;
     u32 saveTRANS_VSYNC_B ;
     u32 savePIPEBSTAT ;
     u32 saveDSPBSTRIDE ;
     u32 saveDSPBSIZE ;
     u32 saveDSPBPOS ;
     u32 saveDSPBADDR ;
     u32 saveDSPBSURF ;
     u32 saveDSPBTILEOFF ;
     u32 saveVGA0 ;
     u32 saveVGA1 ;
     u32 saveVGA_PD ;
     u32 saveVGACNTRL ;
     u32 saveADPA ;
     u32 saveLVDS ;
     u32 savePP_ON_DELAYS ;
     u32 savePP_OFF_DELAYS ;
     u32 saveDVOA ;
     u32 saveDVOB ;
     u32 saveDVOC ;
     u32 savePP_ON ;
     u32 savePP_OFF ;
     u32 savePP_CONTROL ;
     u32 savePP_DIVISOR ;
     u32 savePFIT_CONTROL ;
     u32 save_palette_a[256U] ;
     u32 save_palette_b[256U] ;
     u32 saveDPFC_CB_BASE ;
     u32 saveFBC_CFB_BASE ;
     u32 saveFBC_LL_BASE ;
     u32 saveFBC_CONTROL ;
     u32 saveFBC_CONTROL2 ;
     u32 saveIER ;
     u32 saveIIR ;
     u32 saveIMR ;
     u32 saveDEIER ;
     u32 saveDEIMR ;
     u32 saveGTIER ;
     u32 saveGTIMR ;
     u32 saveFDI_RXA_IMR ;
     u32 saveFDI_RXB_IMR ;
     u32 saveCACHE_MODE_0 ;
     u32 saveMI_ARB_STATE ;
     u32 saveSWF0[16U] ;
     u32 saveSWF1[16U] ;
     u32 saveSWF2[3U] ;
     u8 saveMSR ;
     u8 saveSR[8U] ;
     u8 saveGR[25U] ;
     u8 saveAR_INDEX ;
     u8 saveAR[21U] ;
     u8 saveDACMASK ;
     u8 saveCR[37U] ;
     uint64_t saveFENCE[16U] ;
     u32 saveCURACNTR ;
     u32 saveCURAPOS ;
     u32 saveCURABASE ;
     u32 saveCURBCNTR ;
     u32 saveCURBPOS ;
     u32 saveCURBBASE ;
     u32 saveCURSIZE ;
     u32 saveDP_B ;
     u32 saveDP_C ;
     u32 saveDP_D ;
     u32 savePIPEA_GMCH_DATA_M ;
     u32 savePIPEB_GMCH_DATA_M ;
     u32 savePIPEA_GMCH_DATA_N ;
     u32 savePIPEB_GMCH_DATA_N ;
     u32 savePIPEA_DP_LINK_M ;
     u32 savePIPEB_DP_LINK_M ;
     u32 savePIPEA_DP_LINK_N ;
     u32 savePIPEB_DP_LINK_N ;
     u32 saveFDI_RXA_CTL ;
     u32 saveFDI_TXA_CTL ;
     u32 saveFDI_RXB_CTL ;
     u32 saveFDI_TXB_CTL ;
     u32 savePFA_CTL_1 ;
     u32 savePFB_CTL_1 ;
     u32 savePFA_WIN_SZ ;
     u32 savePFB_WIN_SZ ;
     u32 savePFA_WIN_POS ;
     u32 savePFB_WIN_POS ;
     u32 savePCH_DREF_CONTROL ;
     u32 saveDISP_ARB_CTL ;
     u32 savePIPEA_DATA_M1 ;
     u32 savePIPEA_DATA_N1 ;
     u32 savePIPEA_LINK_M1 ;
     u32 savePIPEA_LINK_N1 ;
     u32 savePIPEB_DATA_M1 ;
     u32 savePIPEB_DATA_N1 ;
     u32 savePIPEB_LINK_M1 ;
     u32 savePIPEB_LINK_N1 ;
     u32 saveMCHBAR_RENDER_STANDBY ;
     struct __anonstruct_mm_185 mm ;
     struct sdvo_device_mapping sdvo_mappings[2U] ;
     unsigned int lvds_border_bits ;
     u32 pch_pf_pos ;
     u32 pch_pf_size ;
     int panel_t3 ;
     int panel_t12 ;
     struct drm_crtc *plane_to_crtc_mapping[2U] ;
     struct drm_crtc *pipe_to_crtc_mapping[2U] ;
     wait_queue_head_t pending_flip_queue ;
     bool flip_pending_is_done ;
     bool render_reclock_avail ;
     bool lvds_downclock_avail ;
     int lvds_downclock ;
     struct work_struct idle_work ;
     struct timer_list idle_timer ;
     bool busy ;
     u16 orig_clock ;
     int child_dev_num ;
     struct child_device_config *child_dev ;
     struct drm_connector *int_lvds_connector ;
     bool mchbar_need_disable ;
     struct work_struct rps_work ;
     spinlock_t rps_lock ;
     u32 pm_iir ;
     u8 cur_delay ;
     u8 min_delay ;
     u8 max_delay ;
     u8 fmax ;
     u8 fstart ;
     u64 last_count1 ;
     unsigned long last_time1 ;
     u64 last_count2 ;
     struct timespec last_time2 ;
     unsigned long gfx_power ;
     int c_m ;
     int r_t ;
     u8 corr ;
     spinlock_t *mchdev_lock ;
     enum no_fbc_reason no_fbc_reason ;
     struct drm_mm_node *compressed_fb ;
     struct drm_mm_node *compressed_llb ;
     unsigned long last_gpu_reset ;
     struct intel_fbdev *fbdev ;
     struct drm_property *broadcast_rgb_property ;
     struct drm_property *force_audio_property ;
     atomic_t forcewake_count ;
  };
  #line 726 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  typedef struct drm_i915_private drm_i915_private_t;
  #line 733 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_gem_object {
     struct drm_gem_object base ;
     struct drm_mm_node *gtt_space ;
     struct list_head gtt_list ;
     struct list_head ring_list ;
     struct list_head mm_list ;
     struct list_head gpu_write_list ;
     struct list_head exec_list ;
     unsigned char active : 1 ;
     unsigned char dirty : 1 ;
     unsigned char pending_gpu_write : 1 ;
     signed char fence_reg : 5 ;
     unsigned char madv : 2 ;
     unsigned char tiling_mode : 2 ;
     unsigned char tiling_changed : 1 ;
     unsigned char pin_count : 4 ;
     unsigned char map_and_fenceable : 1 ;
     unsigned char fault_mappable : 1 ;
     unsigned char pin_mappable : 1 ;
     unsigned char pending_fenced_gpu_access : 1 ;
     unsigned char fenced_gpu_access : 1 ;
     unsigned char cache_level : 2 ;
     struct page **pages ;
     struct scatterlist *sg_list ;
     int num_sg ;
     struct hlist_node exec_node ;
     unsigned long exec_handle ;
     struct drm_i915_gem_exec_object2 *exec_entry ;
     uint32_t gtt_offset ;
     uint32_t last_rendering_seqno ;
     struct intel_ring_buffer *ring ;
     uint32_t last_fenced_seqno ;
     struct intel_ring_buffer *last_fenced_ring ;
     uint32_t stride ;
     unsigned long *bit_17 ;
     uint8_t *page_cpu_valid ;
     uint32_t user_pin_count ;
     struct drm_file *pin_filp ;
     struct drm_i915_gem_phys_object *phys_obj ;
     atomic_t pending_flip ;
  };
  #line 147 "include/drm/drm_crtc_helper.h"
  struct drm_fb_helper;
  #line 147
  struct drm_fb_helper;
  #line 148 "include/drm/drm_crtc_helper.h"
  struct drm_fb_helper_crtc {
     uint32_t crtc_id ;
     struct drm_mode_set mode_set ;
     struct drm_display_mode *desired_mode ;
  };
  #line 42 "include/drm/drm_fb_helper.h"
  struct drm_fb_helper_surface_size {
     u32 fb_width ;
     u32 fb_height ;
     u32 surface_width ;
     u32 surface_height ;
     u32 surface_bpp ;
     u32 surface_depth ;
  };
  #line 51 "include/drm/drm_fb_helper.h"
  struct drm_fb_helper_funcs {
     void (*gamma_set)(struct drm_crtc * , u16  , u16  , u16  , int  ) ;
     void (*gamma_get)(struct drm_crtc * , u16 * , u16 * , u16 * , int  ) ;
     int (*fb_probe)(struct drm_fb_helper * , struct drm_fb_helper_surface_size * ) ;
  };
  #line 60 "include/drm/drm_fb_helper.h"
  struct drm_fb_helper_connector {
     struct drm_connector *connector ;
     struct drm_cmdline_mode cmdline_mode ;
  };
  #line 66 "include/drm/drm_fb_helper.h"
  struct drm_fb_helper {
     struct drm_framebuffer *fb ;
     struct drm_framebuffer *saved_fb ;
     struct drm_device *dev ;
     struct drm_display_mode *mode ;
     int crtc_count ;
     struct drm_fb_helper_crtc *crtc_info ;
     int connector_count ;
     struct drm_fb_helper_connector **connector_info ;
     struct drm_fb_helper_funcs *funcs ;
     int conn_limit ;
     struct fb_info *fbdev ;
     u32 pseudo_palette[17U] ;
     struct list_head kernel_fb_list ;
     bool delayed_hotplug ;
  };
  #line 127 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_framebuffer {
     struct drm_framebuffer base ;
     struct drm_i915_gem_object *obj ;
  };
  #line 132 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_fbdev {
     struct drm_fb_helper helper ;
     struct intel_framebuffer ifb ;
     struct list_head fbdev_list ;
     struct drm_display_mode *our_mode ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 43 "include/drm/drm.h"
  typedef unsigned int drm_handle_t;
  #line 99 "include/drm/drm.h"
  struct drm_tex_region {
     unsigned char next ;
     unsigned char prev ;
     unsigned char in_use ;
     unsigned char padding ;
     unsigned int age ;
  };
  #line 120 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct _drm_i915_sarea;
  #line 120
  struct _drm_i915_sarea;
  #line 120 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_master_private {
     drm_local_map_t *sarea ;
     struct _drm_i915_sarea *sarea_priv ;
  };
  #line 879
  struct drm_i915_file_private;
  #line 879
  struct drm_i915_file_private;
  #line 909 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct __anonstruct_mm_186 {
     struct spinlock lock ;
     struct list_head request_list ;
  };
  #line 909 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_file_private {
     struct __anonstruct_mm_186 mm ;
  };
  #line 43 "include/drm/i915_drm.h"
  enum ldv_26036 {
      I915_INIT_DMA = 1,
      I915_CLEANUP_DMA = 2,
      I915_RESUME_DMA = 3
  } ;
  #line 49 "include/drm/i915_drm.h"
  struct _drm_i915_init {
     enum ldv_26036 func ;
     unsigned int mmio_offset ;
     int sarea_priv_offset ;
     unsigned int ring_start ;
     unsigned int ring_end ;
     unsigned int ring_size ;
     unsigned int front_offset ;
     unsigned int back_offset ;
     unsigned int depth_offset ;
     unsigned int w ;
     unsigned int h ;
     unsigned int pitch ;
     unsigned int pitch_bits ;
     unsigned int back_pitch ;
     unsigned int depth_pitch ;
     unsigned int cpp ;
     unsigned int chipset ;
  };
  #line 73 "include/drm/i915_drm.h"
  typedef struct _drm_i915_init drm_i915_init_t;
  #line 74 "include/drm/i915_drm.h"
  struct _drm_i915_sarea {
     struct drm_tex_region texList[256U] ;
     int last_upload ;
     int last_enqueue ;
     int last_dispatch ;
     int ctxOwner ;
     int texAge ;
     int pf_enabled ;
     int pf_active ;
     int pf_current_page ;
     int perf_boxes ;
     int width ;
     int height ;
     drm_handle_t front_handle ;
     int front_offset ;
     int front_size ;
     drm_handle_t back_handle ;
     int back_offset ;
     int back_size ;
     drm_handle_t depth_handle ;
     int depth_offset ;
     int depth_size ;
     drm_handle_t tex_handle ;
     int tex_offset ;
     int tex_size ;
     int log_tex_granularity ;
     int pitch ;
     int rotation ;
     int rotated_offset ;
     int rotated_size ;
     int rotated_pitch ;
     int virtualX ;
     int virtualY ;
     unsigned int front_tiled ;
     unsigned int back_tiled ;
     unsigned int depth_tiled ;
     unsigned int rotated_tiled ;
     unsigned int rotated2_tiled ;
     int pipeA_x ;
     int pipeA_y ;
     int pipeA_w ;
     int pipeA_h ;
     int pipeB_x ;
     int pipeB_y ;
     int pipeB_w ;
     int pipeB_h ;
     drm_handle_t unused_handle ;
     __u32 unused1 ;
     __u32 unused2 ;
     __u32 unused3 ;
     __u32 front_bo_handle ;
     __u32 back_bo_handle ;
     __u32 unused_bo_handle ;
     __u32 depth_bo_handle ;
  };
  #line 138 "include/drm/i915_drm.h"
  typedef struct _drm_i915_sarea drm_i915_sarea_t;
  #line 139 "include/drm/i915_drm.h"
  struct drm_i915_batchbuffer {
     int start ;
     int used ;
     int DR1 ;
     int DR4 ;
     int num_cliprects ;
     struct drm_clip_rect *cliprects ;
  };
  #line 253 "include/drm/i915_drm.h"
  typedef struct drm_i915_batchbuffer drm_i915_batchbuffer_t;
  #line 254 "include/drm/i915_drm.h"
  struct _drm_i915_cmdbuffer {
     char *buf ;
     int sz ;
     int DR1 ;
     int DR4 ;
     int num_cliprects ;
     struct drm_clip_rect *cliprects ;
  };
  #line 265 "include/drm/i915_drm.h"
  typedef struct _drm_i915_cmdbuffer drm_i915_cmdbuffer_t;
  #line 276 "include/drm/i915_drm.h"
  struct drm_i915_getparam {
     int param ;
     int *value ;
  };
  #line 298 "include/drm/i915_drm.h"
  typedef struct drm_i915_getparam drm_i915_getparam_t;
  #line 299 "include/drm/i915_drm.h"
  struct drm_i915_setparam {
     int param ;
     int value ;
  };
  #line 310 "include/drm/i915_drm.h"
  typedef struct drm_i915_setparam drm_i915_setparam_t;
  #line 357 "include/drm/i915_drm.h"
  struct drm_i915_hws_addr {
     __u64 addr ;
  };
  #line 360 "include/drm/i915_drm.h"
  typedef struct drm_i915_hws_addr drm_i915_hws_addr_t;
  #line 471 "include/linux/pnp.h"
  enum vga_switcheroo_state {
      VGA_SWITCHEROO_OFF = 0,
      VGA_SWITCHEROO_ON = 1
  } ;
  #line 1438 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
  struct cparams {
     u16 i ;
     u16 t ;
     u16 m ;
     u16 c ;
  };
  #line 1513 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
  struct v_table {
     u16 vd ;
     u16 vm ;
  };
  #line 108 "include/linux/types.h"
  typedef __s16 int16_t;
  #line 125 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/desc_defs.h"
  struct paravirt_callee_save {
     void *func ;
  };
  #line 190 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt_types.h"
  struct pv_irq_ops {
     struct paravirt_callee_save save_fl ;
     struct paravirt_callee_save restore_fl ;
     struct paravirt_callee_save irq_disable ;
     struct paravirt_callee_save irq_enable ;
     void (*safe_halt)(void) ;
     void (*halt)(void) ;
     void (*adjust_exception_frame)(void) ;
  };
  #line 28 "include/linux/wait.h"
  struct __wait_queue;
  #line 28
  struct __wait_queue;
  #line 28 "include/linux/wait.h"
  typedef struct __wait_queue wait_queue_t;
  #line 31 "include/linux/wait.h"
  struct __wait_queue {
     unsigned int flags ;
     void *private ;
     int (*func)(wait_queue_t * , unsigned int  , int  , void * ) ;
     struct list_head task_list ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 39 "include/linux/kobject.h"
  enum kobject_action {
      KOBJ_ADD = 0,
      KOBJ_REMOVE = 1,
      KOBJ_CHANGE = 2,
      KOBJ_MOVE = 3,
      KOBJ_ONLINE = 4,
      KOBJ_OFFLINE = 5,
      KOBJ_MAX = 6
  } ;
  #line 266 "include/drm/i915_drm.h"
  struct drm_i915_irq_emit {
     int *irq_seq ;
  };
  #line 271 "include/drm/i915_drm.h"
  typedef struct drm_i915_irq_emit drm_i915_irq_emit_t;
  #line 272 "include/drm/i915_drm.h"
  struct drm_i915_irq_wait {
     int irq_seq ;
  };
  #line 275 "include/drm/i915_drm.h"
  typedef struct drm_i915_irq_wait drm_i915_irq_wait_t;
  #line 340 "include/drm/i915_drm.h"
  struct drm_i915_vblank_pipe {
     int pipe ;
  };
  #line 348 "include/drm/i915_drm.h"
  typedef struct drm_i915_vblank_pipe drm_i915_vblank_pipe_t;
  #line 28 "include/drm/intel-gtt.h"
  enum pipe {
      PIPE_A = 0,
      PIPE_B = 1,
      PIPE_C = 2,
      I915_MAX_PIPES = 3
  } ;
  #line 35
  enum plane {
      PLANE_A = 0,
      PLANE_B = 1,
      PLANE_C = 2
  } ;
  #line 879 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_i915_gem_request {
     struct intel_ring_buffer *ring ;
     uint32_t seqno ;
     unsigned long emitted_jiffies ;
     struct list_head list ;
     struct drm_i915_file_private *file_priv ;
     struct list_head client_list ;
  };
  #line 139 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_encoder {
     struct drm_encoder base ;
     int type ;
     bool needs_tv_clock ;
     void (*hot_plug)(struct intel_encoder * ) ;
     int crtc_mask ;
     int clone_mask ;
  };
  #line 153
  struct intel_unpin_work;
  #line 153
  struct intel_unpin_work;
  #line 153 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_crtc {
     struct drm_crtc base ;
     enum pipe pipe ;
     enum plane plane ;
     u8 lut_r[256U] ;
     u8 lut_g[256U] ;
     u8 lut_b[256U] ;
     int dpms_mode ;
     bool active ;
     bool busy ;
     struct timer_list idle_timer ;
     bool lowfreq_avail ;
     struct intel_overlay *overlay ;
     struct intel_unpin_work *unpin_work ;
     int fdi_lanes ;
     struct drm_i915_gem_object *cursor_bo ;
     uint32_t cursor_addr ;
     int16_t cursor_x ;
     int16_t cursor_y ;
     int16_t cursor_width ;
     int16_t cursor_height ;
     bool cursor_visible ;
  };
  #line 225 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_unpin_work {
     struct work_struct work ;
     struct drm_device *dev ;
     struct drm_i915_gem_object *old_fb_obj ;
     struct drm_i915_gem_object *pending_flip_obj ;
     struct drm_pending_vblank_event *event ;
     int pending ;
     bool enable_stall_check ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 311 "include/drm/i915_drm.h"
  struct drm_i915_mem_alloc {
     int region ;
     int alignment ;
     int size ;
     int *region_offset ;
  };
  #line 321 "include/drm/i915_drm.h"
  typedef struct drm_i915_mem_alloc drm_i915_mem_alloc_t;
  #line 322 "include/drm/i915_drm.h"
  struct drm_i915_mem_free {
     int region ;
     int region_offset ;
  };
  #line 326 "include/drm/i915_drm.h"
  typedef struct drm_i915_mem_free drm_i915_mem_free_t;
  #line 327 "include/drm/i915_drm.h"
  struct drm_i915_mem_init_heap {
     int region ;
     int size ;
     int start ;
  };
  #line 332 "include/drm/i915_drm.h"
  typedef struct drm_i915_mem_init_heap drm_i915_mem_init_heap_t;
  #line 333 "include/drm/i915_drm.h"
  struct drm_i915_mem_destroy_heap {
     int region ;
  };
  #line 339 "include/drm/i915_drm.h"
  typedef struct drm_i915_mem_destroy_heap drm_i915_mem_destroy_heap_t;
  #line 44 "include/linux/types.h"
  typedef unsigned long uintptr_t;
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 230 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess.h"
  struct __large_struct {
     unsigned long buf[100U] ;
  };
  #line 594 "include/drm/drmP.h"
  struct drm_gem_mm {
     struct drm_mm offset_manager ;
     struct drm_open_hash offset_hash ;
  };
  #line 361 "include/drm/i915_drm.h"
  struct drm_i915_gem_init {
     __u64 gtt_start ;
     __u64 gtt_end ;
  };
  #line 374 "include/drm/i915_drm.h"
  struct drm_i915_gem_create {
     __u64 size ;
     __u32 handle ;
     __u32 pad ;
  };
  #line 390 "include/drm/i915_drm.h"
  struct drm_i915_gem_pread {
     __u32 handle ;
     __u32 pad ;
     __u64 offset ;
     __u64 size ;
     __u64 data_ptr ;
  };
  #line 406 "include/drm/i915_drm.h"
  struct drm_i915_gem_pwrite {
     __u32 handle ;
     __u32 pad ;
     __u64 offset ;
     __u64 size ;
     __u64 data_ptr ;
  };
  #line 422 "include/drm/i915_drm.h"
  struct drm_i915_gem_mmap {
     __u32 handle ;
     __u32 pad ;
     __u64 offset ;
     __u64 size ;
     __u64 addr_ptr ;
  };
  #line 442 "include/drm/i915_drm.h"
  struct drm_i915_gem_mmap_gtt {
     __u32 handle ;
     __u32 pad ;
     __u64 offset ;
  };
  #line 454 "include/drm/i915_drm.h"
  struct drm_i915_gem_set_domain {
     __u32 handle ;
     __u32 read_domains ;
     __u32 write_domain ;
  };
  #line 465 "include/drm/i915_drm.h"
  struct drm_i915_gem_sw_finish {
     __u32 handle ;
  };
  #line 655 "include/drm/i915_drm.h"
  struct drm_i915_gem_pin {
     __u32 handle ;
     __u32 pad ;
     __u64 alignment ;
     __u64 offset ;
  };
  #line 673 "include/drm/i915_drm.h"
  struct drm_i915_gem_busy {
     __u32 handle ;
     __u32 busy ;
  };
  #line 744 "include/drm/i915_drm.h"
  struct drm_i915_gem_get_aperture {
     __u64 aper_size ;
     __u64 aper_available_size ;
  };
  #line 763 "include/drm/i915_drm.h"
  struct drm_i915_gem_madvise {
     __u32 handle ;
     __u32 madv ;
     __u32 retained ;
  };
  #line 350 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct taskstats {
     __u16 version ;
     __u32 ac_exitcode ;
     __u8 ac_flag ;
     __u8 ac_nice ;
     __u64 cpu_count ;
     __u64 cpu_delay_total ;
     __u64 blkio_count ;
     __u64 blkio_delay_total ;
     __u64 swapin_count ;
     __u64 swapin_delay_total ;
     __u64 cpu_run_real_total ;
     __u64 cpu_run_virtual_total ;
     char ac_comm[32U] ;
     __u8 ac_sched ;
     __u8 ac_pad[3U] ;
     __u32 ac_uid ;
     __u32 ac_gid ;
     __u32 ac_pid ;
     __u32 ac_ppid ;
     __u32 ac_btime ;
     __u64 ac_etime ;
     __u64 ac_utime ;
     __u64 ac_stime ;
     __u64 ac_minflt ;
     __u64 ac_majflt ;
     __u64 coremem ;
     __u64 virtmem ;
     __u64 hiwater_rss ;
     __u64 hiwater_vm ;
     __u64 read_char ;
     __u64 write_char ;
     __u64 read_syscalls ;
     __u64 write_syscalls ;
     __u64 read_bytes ;
     __u64 write_bytes ;
     __u64 cancelled_write_bytes ;
     __u64 nvcsw ;
     __u64 nivcsw ;
     __u64 ac_utimescaled ;
     __u64 ac_stimescaled ;
     __u64 cpu_scaled_run_real_total ;
     __u64 freepages_count ;
     __u64 freepages_delay_total ;
  };
  #line 55 "include/linux/prio_heap.h"
  struct cgroupfs_root;
  #line 55
  struct cgroupfs_root;
  #line 57
  struct cgroup;
  #line 57
  struct cgroup;
  #line 58
  struct css_id;
  #line 58
  struct css_id;
  #line 56 "include/linux/cgroup.h"
  struct cgroup_subsys_state {
     struct cgroup *cgroup ;
     atomic_t refcnt ;
     unsigned long flags ;
     struct css_id *id ;
  };
  #line 194 "include/linux/cgroup.h"
  struct cgroup {
     unsigned long flags ;
     atomic_t count ;
     struct list_head sibling ;
     struct list_head children ;
     struct cgroup *parent ;
     struct dentry *dentry ;
     struct cgroup_subsys_state *subsys[64U] ;
     struct cgroupfs_root *root ;
     struct cgroup *top_cgroup ;
     struct list_head css_sets ;
     struct list_head release_list ;
     struct list_head pidlists ;
     struct mutex pidlist_mutex ;
     struct rcu_head rcu_head ;
     struct list_head event_list ;
     spinlock_t event_list_lock ;
  };
  #line 247 "include/linux/cgroup.h"
  struct css_set {
     atomic_t refcount ;
     struct hlist_node hlist ;
     struct list_head tasks ;
     struct list_head cg_links ;
     struct cgroup_subsys_state *subsys[64U] ;
     struct rcu_head rcu_head ;
  };
  #line 105 "include/linux/swap.h"
  struct reclaim_state {
     unsigned long reclaimed_slab ;
  };
  #line 391 "include/linux/swap.h"
  union __anonunion_v_193 {
     short preferred_node ;
     nodemask_t nodes ;
  };
  #line 391 "include/linux/swap.h"
  union __anonunion_w_194 {
     nodemask_t cpuset_mems_allowed ;
     nodemask_t user_nodemask ;
  };
  #line 391 "include/linux/swap.h"
  struct mempolicy {
     atomic_t refcnt ;
     unsigned short mode ;
     unsigned short flags ;
     union __anonunion_v_193 v ;
     union __anonunion_w_194 w ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 470 "include/drm/i915_drm.h"
  struct drm_i915_gem_relocation_entry {
     __u32 target_handle ;
     __u32 delta ;
     __u64 offset ;
     __u64 presumed_offset ;
     __u32 read_domains ;
     __u32 write_domain ;
  };
  #line 515 "include/drm/i915_drm.h"
  struct drm_i915_gem_exec_object {
     __u32 handle ;
     __u32 relocation_count ;
     __u64 relocs_ptr ;
     __u64 alignment ;
     __u64 offset ;
  };
  #line 563 "include/drm/i915_drm.h"
  struct drm_i915_gem_execbuffer {
     __u64 buffers_ptr ;
     __u32 buffer_count ;
     __u32 batch_start_offset ;
     __u32 batch_len ;
     __u32 DR1 ;
     __u32 DR4 ;
     __u32 num_cliprects ;
     __u64 cliprects_ptr ;
  };
  #line 618 "include/drm/i915_drm.h"
  struct drm_i915_gem_execbuffer2 {
     __u64 buffers_ptr ;
     __u32 buffer_count ;
     __u32 batch_start_offset ;
     __u32 batch_len ;
     __u32 DR1 ;
     __u32 DR4 ;
     __u32 num_cliprects ;
     __u64 cliprects_ptr ;
     __u64 flags ;
     __u64 rsvd1 ;
     __u64 rsvd2 ;
  };
  #line 350 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct change_domains {
     uint32_t invalidate_domains ;
     uint32_t flush_domains ;
     uint32_t flush_rings ;
     uint32_t flips ;
  };
  #line 216 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
  struct eb_objects {
     int and ;
     struct hlist_head buckets[0U] ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 727 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  enum i915_cache_level {
      I915_CACHE_NONE = 0,
      I915_CACHE_LLC = 1,
      I915_CACHE_LLC_MLC = 2
  } ;
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 681 "include/drm/i915_drm.h"
  struct drm_i915_gem_set_tiling {
     __u32 handle ;
     __u32 tiling_mode ;
     __u32 stride ;
     __u32 swizzle_mode ;
  };
  #line 727 "include/drm/i915_drm.h"
  struct drm_i915_gem_get_tiling {
     __u32 handle ;
     __u32 tiling_mode ;
     __u32 swizzle_mode ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 335 "include/linux/slab.h"
  struct net;
  #line 335
  struct net;
  #line 1059 "include/linux/sched.h"
  struct uts_namespace;
  #line 1059
  struct uts_namespace;
  #line 389 "drivers/gpu/drm/i915/./i915_trace.h"
  struct ring_buffer_iter;
  #line 389
  struct ring_buffer_iter;
  #line 175 "include/linux/ring_buffer.h"
  struct trace_seq;
  #line 175
  struct trace_seq;
  #line 185 "include/linux/ring_buffer.h"
  struct trace_seq {
     unsigned char buffer[4096U] ;
     unsigned int len ;
     unsigned int readpos ;
     int full ;
  };
  #line 130 "include/linux/trace_seq.h"
  union __anonunion_ldv_37100_187 {
     __u64 sample_period ;
     __u64 sample_freq ;
  };
  #line 130 "include/linux/trace_seq.h"
  union __anonunion_ldv_37125_188 {
     __u32 wakeup_events ;
     __u32 wakeup_watermark ;
  };
  #line 130 "include/linux/trace_seq.h"
  union __anonunion_ldv_37130_189 {
     __u64 bp_addr ;
     __u64 config1 ;
  };
  #line 130 "include/linux/trace_seq.h"
  union __anonunion_ldv_37134_190 {
     __u64 bp_len ;
     __u64 config2 ;
  };
  #line 130 "include/linux/trace_seq.h"
  struct perf_event_attr {
     __u32 type ;
     __u32 size ;
     __u64 config ;
     union __anonunion_ldv_37100_187 ldv_37100 ;
     __u64 sample_type ;
     __u64 read_format ;
     unsigned char disabled : 1 ;
     unsigned char inherit : 1 ;
     unsigned char pinned : 1 ;
     unsigned char exclusive : 1 ;
     unsigned char exclude_user : 1 ;
     unsigned char exclude_kernel : 1 ;
     unsigned char exclude_hv : 1 ;
     unsigned char exclude_idle : 1 ;
     unsigned char mmap : 1 ;
     unsigned char comm : 1 ;
     unsigned char freq : 1 ;
     unsigned char inherit_stat : 1 ;
     unsigned char enable_on_exec : 1 ;
     unsigned char task : 1 ;
     unsigned char watermark : 1 ;
     unsigned char precise_ip : 2 ;
     unsigned char mmap_data : 1 ;
     unsigned char sample_id_all : 1 ;
     unsigned long __reserved_1 : 45 ;
     union __anonunion_ldv_37125_188 ldv_37125 ;
     __u32 bp_type ;
     union __anonunion_ldv_37130_189 ldv_37130 ;
     union __anonunion_ldv_37134_190 ldv_37134 ;
  };
  #line 243 "include/linux/perf_event.h"
  struct perf_event_mmap_page {
     __u32 version ;
     __u32 compat_version ;
     __u32 lock ;
     __u32 index ;
     __s64 offset ;
     __u64 time_enabled ;
     __u64 time_running ;
     __u64 __reserved[123U] ;
     __u64 data_head ;
     __u64 data_tail ;
  };
  #line 12 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/local.h"
  struct __anonstruct_local_t_194 {
     atomic_long_t a ;
  };
  #line 12 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/local.h"
  typedef struct __anonstruct_local_t_194 local_t;
  #line 25 "include/asm-generic/local64.h"
  struct __anonstruct_local64_t_195 {
     local_t a ;
  };
  #line 25 "include/asm-generic/local64.h"
  typedef struct __anonstruct_local64_t_195 local64_t;
  #line 493 "include/linux/perf_event.h"
  struct arch_hw_breakpoint {
     unsigned long address ;
     u8 len ;
     u8 type ;
  };
  #line 48 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/hw_breakpoint.h"
  struct pmu;
  #line 48
  struct pmu;
  #line 73
  struct mnt_namespace;
  #line 73
  struct mnt_namespace;
  #line 74
  struct ipc_namespace;
  #line 74
  struct ipc_namespace;
  #line 75 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/hw_breakpoint.h"
  struct nsproxy {
     atomic_t count ;
     struct uts_namespace *uts_ns ;
     struct ipc_namespace *ipc_ns ;
     struct mnt_namespace *mnt_ns ;
     struct pid_namespace *pid_ns ;
     struct net *net_ns ;
  };
  #line 83 "include/linux/nsproxy.h"
  struct pidmap {
     atomic_t nr_free ;
     void *page ;
  };
  #line 14 "include/linux/pid_namespace.h"
  struct bsd_acct_struct;
  #line 14
  struct bsd_acct_struct;
  #line 15 "include/linux/pid_namespace.h"
  struct pid_namespace {
     struct kref kref ;
     struct pidmap pidmap[128U] ;
     int last_pid ;
     struct task_struct *child_reaper ;
     struct kmem_cache *pid_cachep ;
     unsigned int level ;
     struct pid_namespace *parent ;
     struct vfsmount *proc_mnt ;
     struct bsd_acct_struct *bacct ;
  };
  #line 386 "include/linux/ftrace.h"
  struct ftrace_ret_stack {
     unsigned long ret ;
     unsigned long func ;
     unsigned long long calltime ;
     unsigned long long subtime ;
     unsigned long fp ;
  };
  #line 170 "include/linux/cpu.h"
  struct irq_work {
     struct irq_work *next ;
     void (*func)(struct irq_work * ) ;
  };
  #line 19 "include/linux/irq_work.h"
  struct perf_callchain_entry {
     __u64 nr ;
     __u64 ip[255U] ;
  };
  #line 520 "include/linux/perf_event.h"
  struct perf_raw_record {
     u32 size ;
     void *data ;
  };
  #line 536 "include/linux/perf_event.h"
  struct __anonstruct_ldv_38574_199 {
     u64 config ;
     u64 last_tag ;
     unsigned long config_base ;
     unsigned long event_base ;
     int idx ;
     int last_cpu ;
     unsigned int extra_reg ;
     u64 extra_config ;
     int extra_alloc ;
  };
  #line 536 "include/linux/perf_event.h"
  struct __anonstruct_ldv_38577_200 {
     struct hrtimer hrtimer ;
  };
  #line 536 "include/linux/perf_event.h"
  struct __anonstruct_ldv_38582_201 {
     struct arch_hw_breakpoint info ;
     struct list_head bp_list ;
     struct task_struct *bp_target ;
  };
  #line 536 "include/linux/perf_event.h"
  union __anonunion_ldv_38583_198 {
     struct __anonstruct_ldv_38574_199 ldv_38574 ;
     struct __anonstruct_ldv_38577_200 ldv_38577 ;
     struct __anonstruct_ldv_38582_201 ldv_38582 ;
  };
  #line 536 "include/linux/perf_event.h"
  struct hw_perf_event {
     union __anonunion_ldv_38583_198 ldv_38583 ;
     int state ;
     local64_t prev_count ;
     u64 sample_period ;
     u64 last_period ;
     local64_t period_left ;
     u64 interrupts ;
     u64 freq_time_stamp ;
     u64 freq_count_stamp ;
  };
  #line 582
  struct perf_cpu_context;
  #line 582
  struct perf_cpu_context;
  #line 582 "include/linux/perf_event.h"
  struct pmu {
     struct list_head entry ;
     struct device *dev ;
     char *name ;
     int type ;
     int *pmu_disable_count ;
     struct perf_cpu_context *pmu_cpu_context ;
     int task_ctx_nr ;
     void (*pmu_enable)(struct pmu * ) ;
     void (*pmu_disable)(struct pmu * ) ;
     int (*event_init)(struct perf_event * ) ;
     int (*add)(struct perf_event * , int  ) ;
     void (*del)(struct perf_event * , int  ) ;
     void (*start)(struct perf_event * , int  ) ;
     void (*stop)(struct perf_event * , int  ) ;
     void (*read)(struct perf_event * ) ;
     void (*start_txn)(struct pmu * ) ;
     int (*commit_txn)(struct pmu * ) ;
     void (*cancel_txn)(struct pmu * ) ;
  };
  #line 671
  enum perf_event_active_state {
      PERF_EVENT_STATE_ERROR = -2,
      PERF_EVENT_STATE_OFF = -1,
      PERF_EVENT_STATE_INACTIVE = 0,
      PERF_EVENT_STATE_ACTIVE = 1
  } ;
  #line 678 "include/linux/perf_event.h"
  struct perf_buffer {
     atomic_t refcount ;
     struct rcu_head rcu_head ;
     struct work_struct work ;
     int page_order ;
     int nr_pages ;
     int writable ;
     atomic_t poll ;
     local_t head ;
     local_t nest ;
     local_t events ;
     local_t wakeup ;
     local_t lost ;
     long watermark ;
     struct perf_event_mmap_page *user_page ;
     void *data_pages[0U] ;
  };
  #line 709
  struct perf_sample_data;
  #line 709
  struct perf_sample_data;
  #line 727 "include/linux/perf_event.h"
  struct perf_cgroup_info {
     u64 time ;
     u64 timestamp ;
  };
  #line 741 "include/linux/perf_event.h"
  struct perf_cgroup {
     struct cgroup_subsys_state css ;
     struct perf_cgroup_info *info ;
  };
  #line 746
  struct event_filter;
  #line 746
  struct event_filter;
  #line 746 "include/linux/perf_event.h"
  struct perf_event {
     struct list_head group_entry ;
     struct list_head event_entry ;
     struct list_head sibling_list ;
     struct hlist_node hlist_entry ;
     int nr_siblings ;
     int group_flags ;
     struct perf_event *group_leader ;
     struct pmu *pmu ;
     enum perf_event_active_state state ;
     unsigned int attach_state ;
     local64_t count ;
     atomic64_t child_count ;
     u64 total_time_enabled ;
     u64 total_time_running ;
     u64 tstamp_enabled ;
     u64 tstamp_running ;
     u64 tstamp_stopped ;
     u64 shadow_ctx_time ;
     struct perf_event_attr attr ;
     u16 header_size ;
     u16 id_header_size ;
     u16 read_size ;
     struct hw_perf_event hw ;
     struct perf_event_context *ctx ;
     struct file *filp ;
     atomic64_t child_total_time_enabled ;
     atomic64_t child_total_time_running ;
     struct mutex child_mutex ;
     struct list_head child_list ;
     struct perf_event *parent ;
     int oncpu ;
     int cpu ;
     struct list_head owner_entry ;
     struct task_struct *owner ;
     struct mutex mmap_mutex ;
     atomic_t mmap_count ;
     int mmap_locked ;
     struct user_struct *mmap_user ;
     struct perf_buffer *buffer ;
     wait_queue_head_t waitq ;
     struct fasync_struct *fasync ;
     int pending_wakeup ;
     int pending_kill ;
     int pending_disable ;
     struct irq_work pending ;
     atomic_t event_limit ;
     void (*destroy)(struct perf_event * ) ;
     struct rcu_head rcu_head ;
     struct pid_namespace *ns ;
     u64 id ;
     void (*overflow_handler)(struct perf_event * , int  , struct perf_sample_data * ,
                              struct pt_regs * ) ;
     struct ftrace_event_call *tp_event ;
     struct event_filter *filter ;
     struct perf_cgroup *cgrp ;
     int cgrp_defer_enabled ;
  };
  #line 868
  enum perf_event_context_type {
      task_context = 0,
      cpu_context = 1
  } ;
  #line 873 "include/linux/perf_event.h"
  struct perf_event_context {
     struct pmu *pmu ;
     enum perf_event_context_type type ;
     raw_spinlock_t lock ;
     struct mutex mutex ;
     struct list_head pinned_groups ;
     struct list_head flexible_groups ;
     struct list_head event_list ;
     int nr_events ;
     int nr_active ;
     int is_active ;
     int nr_stat ;
     int rotate_disable ;
     atomic_t refcount ;
     struct task_struct *task ;
     u64 time ;
     u64 timestamp ;
     struct perf_event_context *parent_ctx ;
     u64 parent_gen ;
     u64 generation ;
     int pin_count ;
     struct rcu_head rcu_head ;
     int nr_cgroups ;
  };
  #line 925 "include/linux/perf_event.h"
  struct perf_cpu_context {
     struct perf_event_context ctx ;
     struct perf_event_context *task_ctx ;
     int active_oncpu ;
     int exclusive ;
     struct list_head rotation_list ;
     int jiffies_interval ;
     struct pmu *active_pmu ;
     struct perf_cgroup *cgrp ;
  };
  #line 983 "include/linux/perf_event.h"
  struct __anonstruct_tid_entry_202 {
     u32 pid ;
     u32 tid ;
  };
  #line 983 "include/linux/perf_event.h"
  struct __anonstruct_cpu_entry_203 {
     u32 cpu ;
     u32 reserved ;
  };
  #line 983 "include/linux/perf_event.h"
  struct perf_sample_data {
     u64 type ;
     u64 ip ;
     struct __anonstruct_tid_entry_202 tid_entry ;
     u64 time ;
     u64 addr ;
     u64 id ;
     u64 stream_id ;
     struct __anonstruct_cpu_entry_203 cpu_entry ;
     u64 period ;
     struct perf_callchain_entry *callchain ;
     struct perf_raw_record *raw ;
  };
  #line 1156
  struct trace_array;
  #line 1156
  struct trace_array;
  #line 1157
  struct tracer;
  #line 1157
  struct tracer;
  #line 39 "include/linux/ftrace_event.h"
  struct trace_entry {
     unsigned short type ;
     unsigned char flags ;
     unsigned char preempt_count ;
     int pid ;
     int padding ;
  };
  #line 54 "include/linux/ftrace_event.h"
  struct trace_iterator {
     struct trace_array *tr ;
     struct tracer *trace ;
     void *private ;
     int cpu_file ;
     struct mutex mutex ;
     struct ring_buffer_iter *buffer_iter[4096U] ;
     unsigned long iter_flags ;
     struct trace_seq tmp_seq ;
     struct trace_seq seq ;
     struct trace_entry *ent ;
     unsigned long lost_events ;
     int leftover ;
     int cpu ;
     u64 ts ;
     loff_t pos ;
     long idx ;
     cpumask_var_t started ;
  };
  #line 87
  struct trace_event;
  #line 87
  struct trace_event;
  #line 91
  enum print_line_t;
  #line 91
  enum print_line_t;
  #line 91
  enum print_line_t;
  #line 92 "include/linux/ftrace_event.h"
  struct trace_event_functions {
     enum print_line_t (*trace)(struct trace_iterator * , int  , struct trace_event * ) ;
     enum print_line_t (*raw)(struct trace_iterator * , int  , struct trace_event * ) ;
     enum print_line_t (*hex)(struct trace_iterator * , int  , struct trace_event * ) ;
     enum print_line_t (*binary)(struct trace_iterator * , int  , struct trace_event * ) ;
  };
  #line 100 "include/linux/ftrace_event.h"
  struct trace_event {
     struct hlist_node node ;
     struct list_head list ;
     int type ;
     struct trace_event_functions *funcs ;
  };
  #line 110
  enum print_line_t {
      TRACE_TYPE_PARTIAL_LINE = 0,
      TRACE_TYPE_HANDLED = 1,
      TRACE_TYPE_UNHANDLED = 2,
      TRACE_TYPE_NO_CONSUME = 3
  } ;
  #line 136
  enum trace_reg {
      TRACE_REG_REGISTER = 0,
      TRACE_REG_UNREGISTER = 1,
      TRACE_REG_PERF_REGISTER = 2,
      TRACE_REG_PERF_UNREGISTER = 3
  } ;
  #line 143 "include/linux/ftrace_event.h"
  struct ftrace_event_class {
     char *system ;
     void *probe ;
     void *perf_probe ;
     int (*reg)(struct ftrace_event_call * , enum trace_reg  ) ;
     int (*define_fields)(struct ftrace_event_call * ) ;
     struct list_head *(*get_fields)(struct ftrace_event_call * ) ;
     struct list_head fields ;
     int (*raw_init)(struct ftrace_event_call * ) ;
  };
  #line 177 "include/linux/ftrace_event.h"
  struct ftrace_event_call {
     struct list_head list ;
     struct ftrace_event_class *class ;
     char *name ;
     struct dentry *dir ;
     struct trace_event event ;
     char const   *print_fmt ;
     struct event_filter *filter ;
     void *mod ;
     void *data ;
     unsigned int flags ;
     int perf_refcount ;
     struct hlist_head *perf_events ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 1378 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  enum mode_set_atomic {
      LEAVE_ATOMIC_MODE_SET = 0,
      ENTER_ATOMIC_MODE_SET = 1
  } ;
  #line 1383 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_crtc_helper_funcs {
     void (*dpms)(struct drm_crtc * , int  ) ;
     void (*prepare)(struct drm_crtc * ) ;
     void (*commit)(struct drm_crtc * ) ;
     bool (*mode_fixup)(struct drm_crtc * , struct drm_display_mode * , struct drm_display_mode * ) ;
     int (*mode_set)(struct drm_crtc * , struct drm_display_mode * , struct drm_display_mode * ,
                     int  , int  , struct drm_framebuffer * ) ;
     int (*mode_set_base)(struct drm_crtc * , int  , int  , struct drm_framebuffer * ) ;
     int (*mode_set_base_atomic)(struct drm_crtc * , struct drm_framebuffer * , int  ,
                                 int  , enum mode_set_atomic  ) ;
     void (*load_lut)(struct drm_crtc * ) ;
     void (*disable)(struct drm_crtc * ) ;
  };
  #line 78 "include/drm/drm_crtc_helper.h"
  struct drm_encoder_helper_funcs {
     void (*dpms)(struct drm_encoder * , int  ) ;
     void (*save)(struct drm_encoder * ) ;
     void (*restore)(struct drm_encoder * ) ;
     bool (*mode_fixup)(struct drm_encoder * , struct drm_display_mode * , struct drm_display_mode * ) ;
     void (*prepare)(struct drm_encoder * ) ;
     void (*commit)(struct drm_encoder * ) ;
     void (*mode_set)(struct drm_encoder * , struct drm_display_mode * , struct drm_display_mode * ) ;
     struct drm_crtc *(*get_crtc)(struct drm_encoder * ) ;
     enum drm_connector_status (*detect)(struct drm_encoder * , struct drm_connector * ) ;
     void (*disable)(struct drm_encoder * ) ;
  };
  #line 148 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_connector {
     struct drm_connector base ;
     struct intel_encoder *encoder ;
  };
  #line 294 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct intel_load_detect_pipe {
     struct drm_framebuffer *release_fb ;
     bool load_detect_temp ;
     int dpms_mode ;
  };
  #line 755 "include/drm/i915_drm.h"
  struct drm_i915_get_pipe_from_crtc_id {
     __u32 crtc_id ;
     __u32 pipe ;
  };
  #line 67 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct __anonstruct_intel_clock_t_190 {
     int n ;
     int m1 ;
     int m2 ;
     int p1 ;
     int p2 ;
     int dot ;
     int vco ;
     int m ;
     int p ;
  };
  #line 67 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  typedef struct __anonstruct_intel_clock_t_190 intel_clock_t;
  #line 71 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct __anonstruct_intel_range_t_191 {
     int min ;
     int max ;
  };
  #line 71 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  typedef struct __anonstruct_intel_range_t_191 intel_range_t;
  #line 76 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct __anonstruct_intel_p2_t_192 {
     int dot_limit ;
     int p2_slow ;
     int p2_fast ;
  };
  #line 76 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  typedef struct __anonstruct_intel_p2_t_192 intel_p2_t;
  #line 79
  struct intel_limit;
  #line 79
  struct intel_limit;
  #line 79 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  typedef struct intel_limit intel_limit_t;
  #line 80 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_limit {
     intel_range_t dot ;
     intel_range_t vco ;
     intel_range_t n ;
     intel_range_t m ;
     intel_range_t m1 ;
     intel_range_t m2 ;
     intel_range_t p ;
     intel_range_t p1 ;
     intel_p2_t p2 ;
     bool (*find_pll)(intel_limit_t const   * , struct drm_crtc * , int  , int  , intel_clock_t * ) ;
  };
  #line 3131 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct fdi_m_n {
     u32 tu ;
     u32 gmch_m ;
     u32 gmch_n ;
     u32 link_m ;
     u32 link_n ;
  };
  #line 3164 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_watermark_params {
     unsigned long fifo_size ;
     unsigned long max_wm ;
     unsigned long default_wm ;
     unsigned long guard_size ;
     unsigned long cacheline_size ;
  };
  #line 3361 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct cxsr_latency {
     int is_desktop ;
     int is_ddr3 ;
     unsigned long fsb_freq ;
     unsigned long mem_freq ;
     unsigned long display_sr ;
     unsigned long display_hpll_disable ;
     unsigned long cursor_sr ;
     unsigned long cursor_hpll_disable ;
  };
  #line 7830 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_quirk {
     int device ;
     int subsystem_vendor ;
     int subsystem_device ;
     void (*hook)(struct drm_device * ) ;
  };
  #line 8048 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_cursor_error_state {
     u32 control ;
     u32 position ;
     u32 base ;
     u32 size ;
  };
  #line 8059 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_pipe_error_state {
     u32 conf ;
     u32 source ;
     u32 htotal ;
     u32 hblank ;
     u32 hsync ;
     u32 vtotal ;
     u32 vblank ;
     u32 vsync ;
  };
  #line 8071 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_plane_error_state {
     u32 control ;
     u32 stride ;
     u32 size ;
     u32 pos ;
     u32 addr ;
     u32 surface ;
     u32 tile_offset ;
  };
  #line 8081 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
  struct intel_display_error_state {
     struct intel_cursor_error_state cursor[2U] ;
     struct intel_pipe_error_state pipe[2U] ;
     struct intel_plane_error_state plane[2U] ;
  };
  #line 177 "include/linux/types.h"
  typedef __u16 __le16;
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 662 "include/drm/drm_crtc.h"
  struct edid;
  #line 662
  struct edid;
  #line 99 "include/drm/drm_crtc_helper.h"
  struct drm_connector_helper_funcs {
     int (*get_modes)(struct drm_connector * ) ;
     int (*mode_valid)(struct drm_connector * , struct drm_display_mode * ) ;
     struct drm_encoder *(*best_encoder)(struct drm_connector * ) ;
  };
  #line 147 "include/drm/drm_crtc_helper.h"
  struct est_timings {
     u8 t1 ;
     u8 t2 ;
     u8 mfg_rsvd ;
  };
  #line 42 "include/drm/drm_edid.h"
  struct std_timing {
     u8 hsize ;
     u8 vfreq_aspect ;
  };
  #line 55 "include/drm/drm_edid.h"
  struct detailed_pixel_timing {
     u8 hactive_lo ;
     u8 hblank_lo ;
     u8 hactive_hblank_hi ;
     u8 vactive_lo ;
     u8 vblank_lo ;
     u8 vactive_vblank_hi ;
     u8 hsync_offset_lo ;
     u8 hsync_pulse_width_lo ;
     u8 vsync_offset_pulse_width_lo ;
     u8 hsync_vsync_offset_pulse_width_hi ;
     u8 width_mm_lo ;
     u8 height_mm_lo ;
     u8 width_height_mm_hi ;
     u8 hborder ;
     u8 vborder ;
     u8 misc ;
  };
  #line 81 "include/drm/drm_edid.h"
  struct detailed_data_string {
     u8 str[13U] ;
  };
  #line 86 "include/drm/drm_edid.h"
  struct detailed_data_monitor_range {
     u8 min_vfreq ;
     u8 max_vfreq ;
     u8 min_hfreq_khz ;
     u8 max_hfreq_khz ;
     u8 pixel_clock_mhz ;
     __le16 sec_gtf_toggle ;
     u8 hfreq_start_khz ;
     u8 c ;
     __le16 m ;
     u8 k ;
     u8 j ;
  };
  #line 100 "include/drm/drm_edid.h"
  struct detailed_data_wpindex {
     u8 white_yx_lo ;
     u8 white_x_hi ;
     u8 white_y_hi ;
     u8 gamma ;
  };
  #line 114 "include/drm/drm_edid.h"
  struct cvt_timing {
     u8 code[3U] ;
  };
  #line 118 "include/drm/drm_edid.h"
  union __anonunion_data_184 {
     struct detailed_data_string str ;
     struct detailed_data_monitor_range range ;
     struct detailed_data_wpindex color ;
     struct std_timing timings[6U] ;
     struct cvt_timing cvt[4U] ;
  };
  #line 118 "include/drm/drm_edid.h"
  struct detailed_non_pixel {
     u8 pad1 ;
     u8 type ;
     u8 pad2 ;
     union __anonunion_data_184 data ;
  };
  #line 133 "include/drm/drm_edid.h"
  union __anonunion_data_185 {
     struct detailed_pixel_timing pixel_data ;
     struct detailed_non_pixel other_data ;
  };
  #line 133 "include/drm/drm_edid.h"
  struct detailed_timing {
     __le16 pixel_clock ;
     union __anonunion_data_185 data ;
  };
  #line 151 "include/drm/drm_edid.h"
  struct edid {
     u8 header[8U] ;
     u8 mfg_id[2U] ;
     u8 prod_code[2U] ;
     u32 serial ;
     u8 mfg_week ;
     u8 mfg_year ;
     u8 version ;
     u8 revision ;
     u8 input ;
     u8 width_cm ;
     u8 height_cm ;
     u8 gamma ;
     u8 features ;
     u8 red_green_lo ;
     u8 black_white_lo ;
     u8 red_x ;
     u8 red_y ;
     u8 green_x ;
     u8 green_y ;
     u8 blue_x ;
     u8 blue_y ;
     u8 white_x ;
     u8 white_y ;
     struct est_timings established_timings ;
     struct std_timing standard_timings[8U] ;
     struct detailed_timing detailed_timings[4U] ;
     u8 extensions ;
     u8 checksum ;
  };
  #line 846 "include/drm/i915_drm.h"
  struct intel_crt {
     struct intel_encoder base ;
     bool force_hotplug_required ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 451 "include/linux/mod_devicetable.h"
  struct dmi_strmatch {
     unsigned char slot ;
     char substr[79U] ;
  };
  #line 458 "include/linux/mod_devicetable.h"
  struct dmi_system_id {
     int (*callback)(struct dmi_system_id  const  * ) ;
     char const   *ident ;
     struct dmi_strmatch matches[4U] ;
     void *driver_data ;
  };
  #line 354 "include/linux/acpi.h"
  struct intel_lvds {
     struct intel_encoder base ;
     struct edid *edid ;
     int fitting_mode ;
     u32 pfit_control ;
     u32 pfit_pgm_ratios ;
     bool pfit_dirty ;
     struct drm_display_mode *fixed_mode ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 846 "include/drm/i915_drm.h"
  struct vbt_header {
     u8 signature[20U] ;
     u16 version ;
     u16 header_size ;
     u16 vbt_size ;
     u8 vbt_checksum ;
     u8 reserved0 ;
     u32 bdb_offset ;
     u32 aim_offset[4U] ;
  };
  #line 43 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_header {
     u8 signature[16U] ;
     u16 version ;
     u16 header_size ;
     u16 bdb_size ;
  };
  #line 69 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_general_features {
     unsigned char panel_fitting : 2 ;
     unsigned char flexaim : 1 ;
     unsigned char msg_enable : 1 ;
     unsigned char clear_screen : 3 ;
     unsigned char color_flip : 1 ;
     unsigned char download_ext_vbt : 1 ;
     unsigned char enable_ssc : 1 ;
     unsigned char ssc_freq : 1 ;
     unsigned char enable_lfp_on_override : 1 ;
     unsigned char disable_ssc_ddt : 1 ;
     unsigned char rsvd8 : 3 ;
     unsigned char disable_smooth_vision : 1 ;
     unsigned char single_dvi : 1 ;
     unsigned char rsvd9 : 6 ;
     u8 legacy_monitor_detect ;
     unsigned char int_crt_support : 1 ;
     unsigned char int_tv_support : 1 ;
     unsigned char rsvd11 : 6 ;
  };
  #line 219 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_general_definitions {
     u8 crt_ddc_gmbus_pin ;
     unsigned char dpms_acpi : 1 ;
     unsigned char skip_boot_crt_detect : 1 ;
     unsigned char dpms_aim : 1 ;
     unsigned char rsvd1 : 5 ;
     u8 boot_display[2U] ;
     u8 child_dev_size ;
     struct child_device_config devices[0U] ;
  };
  #line 247 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_lvds_options {
     u8 panel_type ;
     u8 rsvd1 ;
     unsigned char pfit_mode : 2 ;
     unsigned char pfit_text_mode_enhanced : 1 ;
     unsigned char pfit_gfx_mode_enhanced : 1 ;
     unsigned char pfit_ratio_auto : 1 ;
     unsigned char pixel_dither : 1 ;
     unsigned char lvds_edid : 1 ;
     unsigned char rsvd2 : 1 ;
     u8 rsvd4 ;
  };
  #line 261 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_lvds_lfp_data_ptr {
     u16 fp_timing_offset ;
     u8 fp_table_size ;
     u16 dvo_timing_offset ;
     u8 dvo_table_size ;
     u16 panel_pnp_id_offset ;
     u8 pnp_table_size ;
  };
  #line 271 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_lvds_lfp_data_ptrs {
     u8 lvds_entries ;
     struct bdb_lvds_lfp_data_ptr ptr[16U] ;
  };
  #line 276 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct lvds_fp_timing {
     u16 x_res ;
     u16 y_res ;
     u32 lvds_reg ;
     u32 lvds_reg_val ;
     u32 pp_on_reg ;
     u32 pp_on_reg_val ;
     u32 pp_off_reg ;
     u32 pp_off_reg_val ;
     u32 pp_cycle_reg ;
     u32 pp_cycle_reg_val ;
     u32 pfit_reg ;
     u32 pfit_reg_val ;
     u16 terminator ;
  };
  #line 293 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct lvds_dvo_timing {
     u16 clock ;
     u8 hactive_lo ;
     u8 hblank_lo ;
     unsigned char hblank_hi : 4 ;
     unsigned char hactive_hi : 4 ;
     u8 vactive_lo ;
     u8 vblank_lo ;
     unsigned char vblank_hi : 4 ;
     unsigned char vactive_hi : 4 ;
     u8 hsync_off_lo ;
     u8 hsync_pulse_width ;
     unsigned char vsync_pulse_width : 4 ;
     unsigned char vsync_off : 4 ;
     unsigned char rsvd0 : 6 ;
     unsigned char hsync_off_hi : 2 ;
     u8 h_image ;
     u8 v_image ;
     u8 max_hv ;
     u8 h_border ;
     u8 v_border ;
     unsigned char rsvd1 : 3 ;
     unsigned char digital : 2 ;
     unsigned char vsync_positive : 1 ;
     unsigned char hsync_positive : 1 ;
     unsigned char rsvd2 : 1 ;
  };
  #line 321 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct lvds_pnp_id {
     u16 mfg_name ;
     u16 product_code ;
     u32 serial ;
     u8 mfg_week ;
     u8 mfg_year ;
  };
  #line 329 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_lvds_lfp_data_entry {
     struct lvds_fp_timing fp_timing ;
     struct lvds_dvo_timing dvo_timing ;
     struct lvds_pnp_id pnp_id ;
  };
  #line 335 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_lvds_lfp_data {
     struct bdb_lvds_lfp_data_entry data[16U] ;
  };
  #line 368 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_sdvo_lvds_options {
     u8 panel_backlight ;
     u8 h40_set_panel_type ;
     u8 panel_type ;
     u8 ssc_clk_freq ;
     u16 als_low_trip ;
     u16 als_high_trip ;
     u8 sclalarcoeff_tab_row_num ;
     u8 sclalarcoeff_tab_row_size ;
     u8 coefficient[8U] ;
     u8 panel_misc_bits_1 ;
     u8 panel_misc_bits_2 ;
     u8 panel_misc_bits_3 ;
     u8 panel_misc_bits_4 ;
  };
  #line 384 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_driver_features {
     unsigned char boot_dev_algorithm : 1 ;
     unsigned char block_display_switch : 1 ;
     unsigned char allow_display_switch : 1 ;
     unsigned char hotplug_dvo : 1 ;
     unsigned char dual_view_zoom : 1 ;
     unsigned char int15h_hook : 1 ;
     unsigned char sprite_in_clone : 1 ;
     unsigned char primary_lfp_id : 1 ;
     u16 boot_mode_x ;
     u16 boot_mode_y ;
     u8 boot_mode_bpp ;
     u8 boot_mode_refresh ;
     unsigned char enable_lfp_primary : 1 ;
     unsigned char selective_mode_pruning : 1 ;
     unsigned char dual_frequency : 1 ;
     unsigned char render_clock_freq : 1 ;
     unsigned char nt_clone_support : 1 ;
     unsigned char power_scheme_ui : 1 ;
     unsigned char sprite_display_assign : 1 ;
     unsigned char cui_aspect_scaling : 1 ;
     unsigned char preserve_aspect_ratio : 1 ;
     unsigned char sdvo_device_power_down : 1 ;
     unsigned char crt_hotplug : 1 ;
     unsigned char lvds_config : 2 ;
     unsigned char tv_hotplug : 1 ;
     unsigned char hdmi_config : 2 ;
     unsigned char static_display : 1 ;
     unsigned char reserved2 : 7 ;
     u16 legacy_crt_max_x ;
     u16 legacy_crt_max_y ;
     u8 legacy_crt_max_refresh ;
     u8 hdmi_termination ;
     u8 custom_vbt_version ;
  };
  #line 455 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct edp_link_params {
     unsigned char rate : 4 ;
     unsigned char lanes : 4 ;
     unsigned char preemphasis : 4 ;
     unsigned char vswing : 4 ;
  };
  #line 462 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
  struct bdb_edp {
     struct edp_power_seq power_seqs[16U] ;
     u32 color_depth ;
     u32 sdrrs_msa_timing_delay ;
     struct edp_link_params link_params[16U] ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 846 "include/drm/i915_drm.h"
  struct i2c_algo_dp_aux_data {
     bool running ;
     u16 address ;
     int (*aux_ch)(struct i2c_adapter * , int  , uint8_t  , uint8_t * ) ;
  };
  #line 187 "include/drm/drm_dp_helper.h"
  struct intel_dp {
     struct intel_encoder base ;
     uint32_t output_reg ;
     uint32_t DP ;
     uint8_t link_configuration[9U] ;
     bool has_audio ;
     int force_audio ;
     uint32_t color_range ;
     uint8_t link_bw ;
     uint8_t lane_count ;
     uint8_t dpcd[4U] ;
     struct i2c_adapter adapter ;
     struct i2c_algo_dp_aux_data algo ;
     bool is_pch_edp ;
     uint8_t train_set[4U] ;
     uint8_t link_status[6U] ;
  };
  #line 649 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
  struct intel_dp_m_n {
     uint32_t tu ;
     uint32_t gmch_m ;
     uint32_t gmch_n ;
     uint32_t link_m ;
     uint32_t link_n ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 174 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct __anonstruct_avi_190 {
     uint8_t Y_A_B_S ;
     uint8_t C_M_R ;
     uint8_t ITC_EC_Q_SC ;
     uint8_t VIC ;
     uint8_t PR ;
     uint16_t top_bar_end ;
     uint16_t bottom_bar_start ;
     uint16_t left_bar_end ;
     uint16_t right_bar_start ;
  };
  #line 174 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  union __anonunion_body_189 {
     struct __anonstruct_avi_190 avi ;
     uint8_t payload[27U] ;
  };
  #line 174 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct dip_infoframe {
     uint8_t type ;
     uint8_t ver ;
     uint8_t len ;
     uint8_t ecc ;
     uint8_t checksum ;
     union __anonunion_body_189 body ;
  };
  #line 846 "include/drm/i915_drm.h"
  struct intel_hdmi {
     struct intel_encoder base ;
     u32 sdvox_reg ;
     int ddc_bus ;
     uint32_t color_range ;
     bool has_hdmi_sink ;
     bool has_audio ;
     int force_audio ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 846 "include/drm/i915_drm.h"
  struct intel_sdvo_caps {
     u8 vendor_id ;
     u8 device_id ;
     u8 device_rev_id ;
     u8 sdvo_version_major ;
     u8 sdvo_version_minor ;
     unsigned char sdvo_inputs_mask : 2 ;
     unsigned char smooth_scaling : 1 ;
     unsigned char sharp_scaling : 1 ;
     unsigned char up_scaling : 1 ;
     unsigned char down_scaling : 1 ;
     unsigned char stall_support : 1 ;
     unsigned char pad : 1 ;
     u16 output_flags ;
  };
  #line 63 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct __anonstruct_part1_191 {
     u16 clock ;
     u8 h_active ;
     u8 h_blank ;
     u8 h_high ;
     u8 v_active ;
     u8 v_blank ;
     u8 v_high ;
  };
  #line 63 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct __anonstruct_part2_192 {
     u8 h_sync_off ;
     u8 h_sync_width ;
     u8 v_sync_off_width ;
     u8 sync_off_width_high ;
     u8 dtd_flags ;
     u8 sdvo_flags ;
     u8 v_sync_off_high ;
     u8 reserved ;
  };
  #line 63 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_dtd {
     struct __anonstruct_part1_191 part1 ;
     struct __anonstruct_part2_192 part2 ;
  };
  #line 93 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_pixel_clock_range {
     u16 min ;
     u16 max ;
  };
  #line 98 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_preferred_input_timing_args {
     u16 clock ;
     u16 width ;
     u16 height ;
     unsigned char interlace : 1 ;
     unsigned char scaled : 1 ;
     unsigned char pad : 6 ;
  };
  #line 107 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_get_trained_inputs_response {
     unsigned char input0_trained : 1 ;
     unsigned char input1_trained : 1 ;
     unsigned char pad : 6 ;
  };
  #line 161 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_in_out_map {
     u16 in0 ;
     u16 in1 ;
  };
  #line 218 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_set_target_input_args {
     unsigned char target_1 : 1 ;
     unsigned char pad : 7 ;
  };
  #line 231 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_tv_format {
     unsigned char ntsc_m : 1 ;
     unsigned char ntsc_j : 1 ;
     unsigned char ntsc_443 : 1 ;
     unsigned char pal_b : 1 ;
     unsigned char pal_d : 1 ;
     unsigned char pal_g : 1 ;
     unsigned char pal_h : 1 ;
     unsigned char pal_i : 1 ;
     unsigned char pal_m : 1 ;
     unsigned char pal_n : 1 ;
     unsigned char pal_nc : 1 ;
     unsigned char pal_60 : 1 ;
     unsigned char secam_b : 1 ;
     unsigned char secam_d : 1 ;
     unsigned char secam_g : 1 ;
     unsigned char secam_k : 1 ;
     unsigned char secam_k1 : 1 ;
     unsigned char secam_l : 1 ;
     unsigned char secam_60 : 1 ;
     unsigned char hdtv_std_smpte_240m_1080i_59 : 1 ;
     unsigned char hdtv_std_smpte_240m_1080i_60 : 1 ;
     unsigned char hdtv_std_smpte_260m_1080i_59 : 1 ;
     unsigned char hdtv_std_smpte_260m_1080i_60 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080i_50 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080i_59 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080i_60 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_23 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_24 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_25 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_29 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_30 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_50 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_59 : 1 ;
     unsigned char hdtv_std_smpte_274m_1080p_60 : 1 ;
     unsigned char hdtv_std_smpte_295m_1080i_50 : 1 ;
     unsigned char hdtv_std_smpte_295m_1080p_50 : 1 ;
     unsigned char hdtv_std_smpte_296m_720p_59 : 1 ;
     unsigned char hdtv_std_smpte_296m_720p_60 : 1 ;
     unsigned char hdtv_std_smpte_296m_720p_50 : 1 ;
     unsigned char hdtv_std_smpte_293m_480p_59 : 1 ;
     unsigned char hdtv_std_smpte_170m_480i_59 : 1 ;
     unsigned char hdtv_std_iturbt601_576i_50 : 1 ;
     unsigned char hdtv_std_iturbt601_576p_50 : 1 ;
     unsigned char hdtv_std_eia_7702a_480i_60 : 1 ;
     unsigned char hdtv_std_eia_7702a_480p_60 : 1 ;
     unsigned char pad : 3 ;
  };
  #line 369 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_sdtv_resolution_request {
     unsigned char ntsc_m : 1 ;
     unsigned char ntsc_j : 1 ;
     unsigned char ntsc_443 : 1 ;
     unsigned char pal_b : 1 ;
     unsigned char pal_d : 1 ;
     unsigned char pal_g : 1 ;
     unsigned char pal_h : 1 ;
     unsigned char pal_i : 1 ;
     unsigned char pal_m : 1 ;
     unsigned char pal_n : 1 ;
     unsigned char pal_nc : 1 ;
     unsigned char pal_60 : 1 ;
     unsigned char secam_b : 1 ;
     unsigned char secam_d : 1 ;
     unsigned char secam_g : 1 ;
     unsigned char secam_k : 1 ;
     unsigned char secam_k1 : 1 ;
     unsigned char secam_l : 1 ;
     unsigned char secam_60 : 1 ;
     unsigned char pad : 5 ;
  };
  #line 579 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_enhancements_reply {
     unsigned char flicker_filter : 1 ;
     unsigned char flicker_filter_adaptive : 1 ;
     unsigned char flicker_filter_2d : 1 ;
     unsigned char saturation : 1 ;
     unsigned char hue : 1 ;
     unsigned char brightness : 1 ;
     unsigned char contrast : 1 ;
     unsigned char overscan_h : 1 ;
     unsigned char overscan_v : 1 ;
     unsigned char hpos : 1 ;
     unsigned char vpos : 1 ;
     unsigned char sharpness : 1 ;
     unsigned char dot_crawl : 1 ;
     unsigned char dither : 1 ;
     unsigned char tv_chroma_filter : 1 ;
     unsigned char tv_luma_filter : 1 ;
  };
  #line 670 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_sdvo_regs.h"
  struct intel_sdvo_encode {
     u8 dvi_rev ;
     u8 hdmi_rev ;
  };
  #line 71 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
  struct intel_sdvo {
     struct intel_encoder base ;
     struct i2c_adapter *i2c ;
     u8 slave_addr ;
     struct i2c_adapter ddc ;
     int sdvo_reg ;
     uint16_t controlled_output ;
     struct intel_sdvo_caps caps ;
     int pixel_clock_min ;
     int pixel_clock_max ;
     uint16_t attached_output ;
     uint32_t color_range ;
     bool is_tv ;
     int tv_format_index ;
     bool is_hdmi ;
     bool has_hdmi_monitor ;
     bool has_hdmi_audio ;
     bool is_lvds ;
     struct drm_display_mode *sdvo_lvds_fixed_mode ;
     uint8_t ddc_bus ;
     struct intel_sdvo_dtd input_dtd ;
  };
  #line 145 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
  struct intel_sdvo_connector {
     struct intel_connector base ;
     uint16_t output_flag ;
     int force_audio ;
     u8 tv_format_supported[19U] ;
     int format_supported_num ;
     struct drm_property *tv_format ;
     struct drm_property *left ;
     struct drm_property *right ;
     struct drm_property *top ;
     struct drm_property *bottom ;
     struct drm_property *hpos ;
     struct drm_property *vpos ;
     struct drm_property *contrast ;
     struct drm_property *saturation ;
     struct drm_property *hue ;
     struct drm_property *sharpness ;
     struct drm_property *flicker_filter ;
     struct drm_property *flicker_filter_adaptive ;
     struct drm_property *flicker_filter_2d ;
     struct drm_property *tv_chroma_filter ;
     struct drm_property *tv_luma_filter ;
     struct drm_property *dot_crawl ;
     struct drm_property *brightness ;
     u32 left_margin ;
     u32 right_margin ;
     u32 top_margin ;
     u32 bottom_margin ;
     u32 max_hscan ;
     u32 max_vscan ;
     u32 max_hpos ;
     u32 cur_hpos ;
     u32 max_vpos ;
     u32 cur_vpos ;
     u32 cur_brightness ;
     u32 max_brightness ;
     u32 cur_contrast ;
     u32 max_contrast ;
     u32 cur_saturation ;
     u32 max_saturation ;
     u32 cur_hue ;
     u32 max_hue ;
     u32 cur_sharpness ;
     u32 max_sharpness ;
     u32 cur_flicker_filter ;
     u32 max_flicker_filter ;
     u32 cur_flicker_filter_adaptive ;
     u32 max_flicker_filter_adaptive ;
     u32 cur_flicker_filter_2d ;
     u32 max_flicker_filter_2d ;
     u32 cur_tv_chroma_filter ;
     u32 max_tv_chroma_filter ;
     u32 cur_tv_luma_filter ;
     u32 max_tv_luma_filter ;
     u32 cur_dot_crawl ;
     u32 max_dot_crawl ;
  };
  #line 287 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
  struct _sdvo_cmd_name {
     u8 cmd ;
     char const   *name ;
  };
  #line 2476 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
  union __anonunion_enhancements_197 {
     struct intel_sdvo_enhancements_reply reply ;
     uint16_t response ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 573 "include/linux/i2c.h"
  struct i2c_algo_bit_data {
     void *data ;
     void (*setsda)(void * , int  ) ;
     void (*setscl)(void * , int  ) ;
     int (*getsda)(void * ) ;
     int (*getscl)(void * ) ;
     int (*pre_xfer)(struct i2c_adapter * ) ;
     void (*post_xfer)(struct i2c_adapter * ) ;
     int udelay ;
     int timeout ;
  };
  #line 55 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
  struct intel_gpio {
     struct i2c_adapter adapter ;
     struct i2c_algo_bit_data algo ;
     struct drm_i915_private *dev_priv ;
     u32 reg ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 853 "include/drm/i915_drm.h"
  struct intel_tv {
     struct intel_encoder base ;
     int type ;
     char const   *tv_format ;
     int margin[4U] ;
     u32 save_TV_H_CTL_1 ;
     u32 save_TV_H_CTL_2 ;
     u32 save_TV_H_CTL_3 ;
     u32 save_TV_V_CTL_1 ;
     u32 save_TV_V_CTL_2 ;
     u32 save_TV_V_CTL_3 ;
     u32 save_TV_V_CTL_4 ;
     u32 save_TV_V_CTL_5 ;
     u32 save_TV_V_CTL_6 ;
     u32 save_TV_V_CTL_7 ;
     u32 save_TV_SC_CTL_1 ;
     u32 save_TV_SC_CTL_2 ;
     u32 save_TV_SC_CTL_3 ;
     u32 save_TV_CSC_Y ;
     u32 save_TV_CSC_Y2 ;
     u32 save_TV_CSC_U ;
     u32 save_TV_CSC_U2 ;
     u32 save_TV_CSC_V ;
     u32 save_TV_CSC_V2 ;
     u32 save_TV_CLR_KNOBS ;
     u32 save_TV_CLR_LEVEL ;
     u32 save_TV_WIN_POS ;
     u32 save_TV_WIN_SIZE ;
     u32 save_TV_FILTER_CTL_1 ;
     u32 save_TV_FILTER_CTL_2 ;
     u32 save_TV_FILTER_CTL_3 ;
     u32 save_TV_H_LUMA[60U] ;
     u32 save_TV_H_CHROMA[60U] ;
     u32 save_TV_V_LUMA[43U] ;
     u32 save_TV_V_CHROMA[43U] ;
     u32 save_TV_DAC ;
     u32 save_TV_CTL ;
  };
  #line 95 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
  struct video_levels {
     int blank ;
     int black ;
     int burst ;
  };
  #line 99 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
  struct color_conversion {
     u16 ry ;
     u16 gy ;
     u16 by ;
     u16 ay ;
     u16 ru ;
     u16 gu ;
     u16 bu ;
     u16 au ;
     u16 rv ;
     u16 gv ;
     u16 bv ;
     u16 av ;
  };
  #line 356 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
  struct tv_mode {
     char const   *name ;
     int clock ;
     int refresh ;
     u32 oversample ;
     int hsync_end ;
     int hblank_start ;
     int hblank_end ;
     int htotal ;
     bool progressive ;
     bool trilevel_sync ;
     bool component_only ;
     int vsync_start_f1 ;
     int vsync_start_f2 ;
     int vsync_len ;
     bool veq_ena ;
     int veq_start_f1 ;
     int veq_start_f2 ;
     int veq_len ;
     int vi_end_f1 ;
     int vi_end_f2 ;
     int nbr_end ;
     bool burst_ena ;
     int hburst_start ;
     int hburst_len ;
     int vburst_start_f1 ;
     int vburst_end_f1 ;
     int vburst_start_f2 ;
     int vburst_end_f2 ;
     int vburst_start_f3 ;
     int vburst_end_f3 ;
     int vburst_start_f4 ;
     int vburst_end_f4 ;
     int dda2_size ;
     int dda3_size ;
     int dda1_inc ;
     int dda2_inc ;
     int dda3_inc ;
     u32 sc_reset ;
     bool pal_burst ;
     struct video_levels  const  *composite_levels ;
     struct video_levels  const  *svideo_levels ;
     struct color_conversion  const  *composite_color ;
     struct color_conversion  const  *svideo_color ;
     u32 const   *filter_table ;
     int max_srcw ;
  };
  #line 1393 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
  struct input_res {
     char const   *name ;
     int w ;
     int h ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 846 "include/drm/i915_drm.h"
  struct intel_dvo_dev_ops;
  #line 846
  struct intel_dvo_dev_ops;
  #line 846 "include/drm/i915_drm.h"
  struct intel_dvo_device {
     char const   *name ;
     int type ;
     u32 dvo_reg ;
     u32 gpio ;
     int slave_addr ;
     struct intel_dvo_dev_ops  const  *dev_ops ;
     void *dev_priv ;
     struct i2c_adapter *i2c_bus ;
  };
  #line 45 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
  struct intel_dvo_dev_ops {
     bool (*init)(struct intel_dvo_device * , struct i2c_adapter * ) ;
     void (*create_resources)(struct intel_dvo_device * ) ;
     void (*dpms)(struct intel_dvo_device * , int  ) ;
     int (*mode_valid)(struct intel_dvo_device * , struct drm_display_mode * ) ;
     bool (*mode_fixup)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ) ;
     void (*prepare)(struct intel_dvo_device * ) ;
     void (*commit)(struct intel_dvo_device * ) ;
     void (*mode_set)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ) ;
     enum drm_connector_status (*detect)(struct intel_dvo_device * ) ;
     struct drm_display_mode *(*get_modes)(struct intel_dvo_device * ) ;
     void (*destroy)(struct intel_dvo_device * ) ;
     void (*dump_regs)(struct intel_dvo_device * ) ;
  };
  #line 85 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
  struct intel_dvo {
     struct intel_encoder base ;
     struct intel_dvo_device dev ;
     struct drm_display_mode *panel_fixed_mode ;
     bool panel_wants_dither ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 216 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
  struct pipe_control {
     struct drm_i915_gem_object *obj ;
     u32 volatile   *cpu_page ;
     u32 gtt_offset ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 780 "include/drm/i915_drm.h"
  struct drm_intel_overlay_put_image {
     __u32 flags ;
     __u32 bo_handle ;
     __u16 stride_Y ;
     __u16 stride_UV ;
     __u32 offset_Y ;
     __u32 offset_U ;
     __u32 offset_V ;
     __u16 src_width ;
     __u16 src_height ;
     __u16 src_scan_width ;
     __u16 src_scan_height ;
     __u32 crtc_id ;
     __u16 dst_x ;
     __u16 dst_y ;
     __u16 dst_width ;
     __u16 dst_height ;
  };
  #line 829 "include/drm/i915_drm.h"
  struct drm_intel_overlay_attrs {
     __u32 flags ;
     __u32 color_key ;
     __s32 brightness ;
     __u32 contrast ;
     __u32 saturation ;
     __u32 gamma0 ;
     __u32 gamma1 ;
     __u32 gamma2 ;
     __u32 gamma3 ;
     __u32 gamma4 ;
     __u32 gamma5 ;
  };
  #line 350 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct overlay_registers {
     u32 OBUF_0Y ;
     u32 OBUF_1Y ;
     u32 OBUF_0U ;
     u32 OBUF_0V ;
     u32 OBUF_1U ;
     u32 OBUF_1V ;
     u32 OSTRIDE ;
     u32 YRGB_VPH ;
     u32 UV_VPH ;
     u32 HORZ_PH ;
     u32 INIT_PHS ;
     u32 DWINPOS ;
     u32 DWINSZ ;
     u32 SWIDTH ;
     u32 SWIDTHSW ;
     u32 SHEIGHT ;
     u32 YRGBSCALE ;
     u32 UVSCALE ;
     u32 OCLRC0 ;
     u32 OCLRC1 ;
     u32 DCLRKV ;
     u32 DCLRKM ;
     u32 SCLRKVH ;
     u32 SCLRKVL ;
     u32 SCLRKEN ;
     u32 OCONFIG ;
     u32 OCMD ;
     u32 RESERVED1 ;
     u32 OSTART_0Y ;
     u32 OSTART_1Y ;
     u32 OSTART_0U ;
     u32 OSTART_0V ;
     u32 OSTART_1U ;
     u32 OSTART_1V ;
     u32 OTILEOFF_0Y ;
     u32 OTILEOFF_1Y ;
     u32 OTILEOFF_0U ;
     u32 OTILEOFF_0V ;
     u32 OTILEOFF_1U ;
     u32 OTILEOFF_1V ;
     u32 FASTHSCALE ;
     u32 UVSCALEV ;
     u32 RESERVEDC[86U] ;
     u16 Y_VCOEFS[51U] ;
     u16 RESERVEDD[77U] ;
     u16 Y_HCOEFS[85U] ;
     u16 RESERVEDE[171U] ;
     u16 UV_VCOEFS[51U] ;
     u16 RESERVEDF[77U] ;
     u16 UV_HCOEFS[51U] ;
     u16 RESERVEDG[77U] ;
  };
  #line 179 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
  struct intel_overlay {
     struct drm_device *dev ;
     struct intel_crtc *crtc ;
     struct drm_i915_gem_object *vid_bo ;
     struct drm_i915_gem_object *old_vid_bo ;
     int active ;
     int pfit_active ;
     u32 pfit_vscale_ratio ;
     u32 color_key ;
     u32 brightness ;
     u32 contrast ;
     u32 saturation ;
     u32 old_xscale ;
     u32 old_yscale ;
     u32 flip_addr ;
     struct drm_i915_gem_object *reg_bo ;
     uint32_t last_flip_req ;
     void (*flip_tail)(struct intel_overlay * ) ;
  };
  #line 512 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
  struct put_image_params {
     int format ;
     short dst_x ;
     short dst_y ;
     short dst_w ;
     short dst_h ;
     short src_w ;
     short src_scan_h ;
     short src_scan_w ;
     short src_h ;
     short stride_Y ;
     short stride_UV ;
     int offset_Y ;
     int offset_U ;
     int offset_V ;
  };
  #line 1502 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
  struct intel_overlay_error_state {
     struct overlay_registers regs ;
     unsigned long base ;
     u32 dovsta ;
     u32 isr ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 181 "include/linux/mod_devicetable.h"
  struct acpi_device_id {
     __u8 id[16U] ;
     kernel_ulong_t driver_data ;
  };
  #line 161 "include/acpi/actypes.h"
  typedef u64 acpi_size;
  #line 162 "include/acpi/actypes.h"
  typedef u64 acpi_io_address;
  #line 163 "include/acpi/actypes.h"
  typedef u64 acpi_physical_address;
  #line 371 "include/acpi/actypes.h"
  typedef u32 acpi_status;
  #line 373 "include/acpi/actypes.h"
  typedef char *acpi_string;
  #line 374 "include/acpi/actypes.h"
  typedef void *acpi_handle;
  #line 548 "include/acpi/actypes.h"
  typedef u32 acpi_object_type;
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_integer_155 {
     acpi_object_type type ;
     u64 value ;
  };
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_string_156 {
     acpi_object_type type ;
     u32 length ;
     char *pointer ;
  };
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_buffer_157 {
     acpi_object_type type ;
     u32 length ;
     u8 *pointer ;
  };
  #line 707
  union acpi_object;
  #line 707
  union acpi_object;
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_package_158 {
     acpi_object_type type ;
     u32 count ;
     union acpi_object *elements ;
  };
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_reference_159 {
     acpi_object_type type ;
     acpi_object_type actual_type ;
     acpi_handle handle ;
  };
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_processor_160 {
     acpi_object_type type ;
     u32 proc_id ;
     acpi_io_address pblk_address ;
     u32 pblk_length ;
  };
  #line 707 "include/acpi/actypes.h"
  struct __anonstruct_power_resource_161 {
     acpi_object_type type ;
     u32 system_level ;
     u32 resource_order ;
  };
  #line 707 "include/acpi/actypes.h"
  union acpi_object {
     acpi_object_type type ;
     struct __anonstruct_integer_155 integer ;
     struct __anonstruct_string_156 string ;
     struct __anonstruct_buffer_157 buffer ;
     struct __anonstruct_package_158 package ;
     struct __anonstruct_reference_159 reference ;
     struct __anonstruct_processor_160 processor ;
     struct __anonstruct_power_resource_161 power_resource ;
  };
  #line 840 "include/acpi/actypes.h"
  struct acpi_object_list {
     u32 count ;
     union acpi_object *pointer ;
  };
  #line 903 "include/linux/device.h"
  struct acpi_handle_list {
     u32 count ;
     acpi_handle handles[10U] ;
  };
  #line 60 "include/acpi/acpi_bus.h"
  enum acpi_bus_removal_type {
      ACPI_BUS_REMOVAL_NORMAL = 0,
      ACPI_BUS_REMOVAL_EJECT = 1,
      ACPI_BUS_REMOVAL_SUPRISE = 2,
      ACPI_BUS_REMOVAL_TYPE_COUNT = 3
  } ;
  #line 77
  struct acpi_driver;
  #line 77
  struct acpi_driver;
  #line 78
  struct acpi_device;
  #line 78
  struct acpi_device;
  #line 95 "include/acpi/acpi_bus.h"
  struct acpi_bus_ops {
     unsigned char acpi_op_add : 1 ;
     unsigned char acpi_op_start : 1 ;
  };
  #line 100 "include/acpi/acpi_bus.h"
  struct acpi_device_ops {
     int (*add)(struct acpi_device * ) ;
     int (*remove)(struct acpi_device * , int  ) ;
     int (*start)(struct acpi_device * ) ;
     int (*suspend)(struct acpi_device * , pm_message_t  ) ;
     int (*resume)(struct acpi_device * ) ;
     int (*bind)(struct acpi_device * ) ;
     int (*unbind)(struct acpi_device * ) ;
     void (*notify)(struct acpi_device * , u32  ) ;
  };
  #line 111 "include/acpi/acpi_bus.h"
  struct acpi_driver {
     char name[80U] ;
     char class[80U] ;
     struct acpi_device_id  const  *ids ;
     unsigned int flags ;
     struct acpi_device_ops ops ;
     struct device_driver drv ;
     struct module *owner ;
  };
  #line 123 "include/acpi/acpi_bus.h"
  struct acpi_device_status {
     unsigned char present : 1 ;
     unsigned char enabled : 1 ;
     unsigned char show_in_ui : 1 ;
     unsigned char functional : 1 ;
     unsigned char battery_present : 1 ;
     unsigned int reserved : 27 ;
  };
  #line 139 "include/acpi/acpi_bus.h"
  struct acpi_device_flags {
     unsigned char dynamic_status : 1 ;
     unsigned char bus_address : 1 ;
     unsigned char removable : 1 ;
     unsigned char ejectable : 1 ;
     unsigned char lockable : 1 ;
     unsigned char suprise_removal_ok : 1 ;
     unsigned char power_manageable : 1 ;
     unsigned char performance_manageable : 1 ;
     unsigned int reserved : 24 ;
  };
  #line 153 "include/acpi/acpi_bus.h"
  struct acpi_device_dir {
     struct proc_dir_entry *entry ;
  };
  #line 164 "include/acpi/acpi_bus.h"
  typedef char acpi_bus_id[8U];
  #line 165 "include/acpi/acpi_bus.h"
  typedef unsigned long acpi_bus_address;
  #line 166 "include/acpi/acpi_bus.h"
  typedef char acpi_device_name[40U];
  #line 167 "include/acpi/acpi_bus.h"
  typedef char acpi_device_class[20U];
  #line 173 "include/acpi/acpi_bus.h"
  struct acpi_device_pnp {
     acpi_bus_id bus_id ;
     acpi_bus_address bus_address ;
     char *unique_id ;
     struct list_head ids ;
     acpi_device_name device_name ;
     acpi_device_class device_class ;
  };
  #line 186 "include/acpi/acpi_bus.h"
  struct acpi_device_power_flags {
     unsigned char explicit_get : 1 ;
     unsigned char power_resources : 1 ;
     unsigned char inrush_current : 1 ;
     unsigned char power_removed : 1 ;
     unsigned int reserved : 28 ;
  };
  #line 198 "include/acpi/acpi_bus.h"
  struct __anonstruct_flags_170 {
     unsigned char valid : 1 ;
     unsigned char explicit_set : 1 ;
     unsigned char reserved : 6 ;
  };
  #line 198 "include/acpi/acpi_bus.h"
  struct acpi_device_power_state {
     struct __anonstruct_flags_170 flags ;
     int power ;
     int latency ;
     struct acpi_handle_list resources ;
  };
  #line 209 "include/acpi/acpi_bus.h"
  struct acpi_device_power {
     int state ;
     struct acpi_device_power_flags flags ;
     struct acpi_device_power_state states[5U] ;
  };
  #line 215 "include/acpi/acpi_bus.h"
  struct acpi_device_perf_flags {
     u8 reserved ;
  };
  #line 221 "include/acpi/acpi_bus.h"
  struct __anonstruct_flags_171 {
     unsigned char valid : 1 ;
     unsigned char reserved : 7 ;
  };
  #line 221 "include/acpi/acpi_bus.h"
  struct acpi_device_perf_state {
     struct __anonstruct_flags_171 flags ;
     u8 power ;
     u8 performance ;
     int latency ;
  };
  #line 231 "include/acpi/acpi_bus.h"
  struct acpi_device_perf {
     int state ;
     struct acpi_device_perf_flags flags ;
     int state_count ;
     struct acpi_device_perf_state *states ;
  };
  #line 238 "include/acpi/acpi_bus.h"
  struct acpi_device_wakeup_flags {
     unsigned char valid : 1 ;
     unsigned char run_wake : 1 ;
     unsigned char notifier_present : 1 ;
  };
  #line 245 "include/acpi/acpi_bus.h"
  struct acpi_device_wakeup {
     acpi_handle gpe_device ;
     u64 gpe_number ;
     u64 sleep_state ;
     struct acpi_handle_list resources ;
     struct acpi_device_wakeup_flags flags ;
     int prepare_count ;
  };
  #line 254 "include/acpi/acpi_bus.h"
  struct acpi_device {
     int device_type ;
     acpi_handle handle ;
     struct acpi_device *parent ;
     struct list_head children ;
     struct list_head node ;
     struct list_head wakeup_list ;
     struct acpi_device_status status ;
     struct acpi_device_flags flags ;
     struct acpi_device_pnp pnp ;
     struct acpi_device_power power ;
     struct acpi_device_wakeup wakeup ;
     struct acpi_device_perf performance ;
     struct acpi_device_dir dir ;
     struct acpi_device_ops ops ;
     struct acpi_driver *driver ;
     void *driver_data ;
     struct device dev ;
     struct acpi_bus_ops bus_ops ;
     enum acpi_bus_removal_type removal_type ;
  };
  #line 350 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
  struct opregion_header {
     u8 signature[16U] ;
     u32 size ;
     u32 opregion_ver ;
     u8 bios_ver[32U] ;
     u8 vbios_ver[16U] ;
     u8 driver_ver[16U] ;
     u32 mboxes ;
     u8 reserved[164U] ;
  };
  #line 71 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
  struct opregion_acpi {
     u32 drdy ;
     u32 csts ;
     u32 cevt ;
     u8 rsvd1[20U] ;
     u32 didl[8U] ;
     u32 cpdl[8U] ;
     u32 cadl[8U] ;
     u32 nadl[8U] ;
     u32 aslp ;
     u32 tidx ;
     u32 chpd ;
     u32 clid ;
     u32 cdck ;
     u32 sxsw ;
     u32 evts ;
     u32 cnot ;
     u32 nrdy ;
     u8 rsvd2[60U] ;
  };
  #line 93 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
  struct opregion_swsci {
     u32 scic ;
     u32 parm ;
     u32 dslp ;
     u8 rsvd[244U] ;
  };
  #line 101 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
  struct opregion_asle {
     u32 ardy ;
     u32 aslc ;
     u32 tche ;
     u32 alsi ;
     u32 bclp ;
     u32 pfit ;
     u32 cblv ;
     u16 bclm[20U] ;
     u32 cpfm ;
     u32 epfm ;
     u8 plut[74U] ;
     u32 pfmb ;
     u8 rsvd[102U] ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 143 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
  struct ch7xxx_id_struct {
     uint8_t vid ;
     char *name ;
  };
  #line 101 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
  struct ch7xxx_priv {
     bool quiet ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 143 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
  struct ch7017_priv {
     uint8_t dummy ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 143 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
  struct ivch_priv {
     bool quiet ;
     uint16_t width ;
     uint16_t height ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 143 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
  struct tfp410_priv {
     bool quiet ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 143 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
  struct sil164_priv {
     bool quiet ;
  };
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 289 "include/drm/drmP.h"
  typedef int drm_ioctl_compat_t(struct file * , unsigned int  , unsigned long  );
  #line 846 "include/drm/i915_drm.h"
  struct _drm_i915_batchbuffer32 {
     int start ;
     int used ;
     int DR1 ;
     int DR4 ;
     int num_cliprects ;
     u32 cliprects ;
  };
  #line 52 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  typedef struct _drm_i915_batchbuffer32 drm_i915_batchbuffer32_t;
  #line 79 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  struct _drm_i915_cmdbuffer32 {
     u32 buf ;
     int sz ;
     int DR1 ;
     int DR4 ;
     int num_cliprects ;
     u32 cliprects ;
  };
  #line 87 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  typedef struct _drm_i915_cmdbuffer32 drm_i915_cmdbuffer32_t;
  #line 114 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  struct drm_i915_irq_emit32 {
     u32 irq_seq ;
  };
  #line 117 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  typedef struct drm_i915_irq_emit32 drm_i915_irq_emit32_t;
  #line 137 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  struct drm_i915_getparam32 {
     int param ;
     u32 value ;
  };
  #line 140 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  typedef struct drm_i915_getparam32 drm_i915_getparam32_t;
  #line 161 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  struct drm_i915_mem_alloc32 {
     int region ;
     int alignment ;
     int size ;
     u32 region_offset ;
  };
  #line 167 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
  typedef struct drm_i915_mem_alloc32 drm_i915_mem_alloc32_t;
  #line 290 "include/linux/timer.h"
  enum hrtimer_restart;
  #line 290
  enum hrtimer_restart;
  #line 848 "include/acpi/actypes.h"
  struct acpi_buffer {
     acpi_size length ;
     void *pointer ;
  };
  #line 1694 "include/drm/drmP.h"
  struct intel_dsm_priv {
     acpi_handle dhandle ;
  };
  #line 1 "<compiler builtins>"
  
  #line 1
  
  #line 1
  
  #line 1
  long __builtin_expect(long  , long  ) ;
  #line 69 "include/asm-generic/bug.h"
  extern void warn_slowpath_null(char const   * , int  ) ;
  #line 88 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/percpu.h"
  extern void __bad_percpu_size(void) ;
  #line 23 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
  __inline static int atomic_read(atomic_t const   *v ) 
  { int const   *__cil_tmp2 ;
    int volatile   *__cil_tmp3 ;
    int volatile   __cil_tmp4 ;
  
    {
    {
  #line 25
    __cil_tmp2 = & v->counter;
  #line 25
    __cil_tmp3 = (int volatile   *)__cil_tmp2;
  #line 25
    __cil_tmp4 = *__cil_tmp3;
  #line 25
    return ((int )__cil_tmp4);
    }
  }
  }
  #line 119 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
  __inline static int atomic_dec_and_test(atomic_t *v ) 
  { unsigned char c ;
    unsigned int __cil_tmp3 ;
  
    {
  #line 123
    __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; decl %0; sete %1": "+m" (v->counter),
                         "=qm" (c): : "memory");
    {
  #line 126
    __cil_tmp3 = (unsigned int )c;
  #line 126
    return (__cil_tmp3 != 0U);
    }
  }
  }
  #line 173 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
  __inline static int atomic_add_return(int i , atomic_t *v ) 
  { int __i ;
  
    {
  #line 182
    __i = i;
  #line 183
    __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; xaddl %0, %1": "+r" (i),
                         "+m" (v->counter): : "memory");
  #line 186
    return (i + __i);
  }
  }
  #line 217 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/thread_info.h"
  extern unsigned long kernel_stack ;
  #line 219 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/thread_info.h"
  __inline static struct thread_info *current_thread_info(void) 
  { struct thread_info *ti ;
    unsigned long pfo_ret__ ;
    unsigned long __cil_tmp3 ;
  
    {
  #line 222
    if (1) {
  #line 222
      goto case_8;
    } else {
  #line 222
      goto switch_default;
  #line 222
      if (0) {
  #line 222
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "p" (& kernel_stack));
  #line 222
        goto ldv_5782;
  #line 222
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& kernel_stack));
  #line 222
        goto ldv_5782;
  #line 222
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& kernel_stack));
  #line 222
        goto ldv_5782;
        case_8: 
  #line 222
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& kernel_stack));
  #line 222
        goto ldv_5782;
        switch_default: 
        {
  #line 222
        __bad_percpu_size();
        }
      } else {
  
      }
    }
    ldv_5782: 
  #line 222
    __cil_tmp3 = pfo_ret__ - 8152UL;
  #line 222
    ti = (struct thread_info *)__cil_tmp3;
  #line 224
    return (ti);
  }
  }
  #line 551 "include/linux/lockdep.h"
  extern void lockdep_rcu_dereference(char const   * , int  ) ;
  #line 123 "include/linux/time.h"
  extern unsigned long get_seconds(void) ;
  #line 124 "include/linux/mutex.h"
  __inline static int mutex_is_locked(struct mutex *lock ) 
  { int tmp ;
    atomic_t *__cil_tmp3 ;
    atomic_t const   *__cil_tmp4 ;
  
    {
    {
  #line 126
    __cil_tmp3 = & lock->count;
  #line 126
    __cil_tmp4 = (atomic_t const   *)__cil_tmp3;
  #line 126
    tmp = atomic_read(__cil_tmp4);
    }
  #line 126
    return (tmp != 1);
  }
  }
  #line 134
  extern void mutex_lock_nested(struct mutex * , unsigned int  ) ;
  #line 168
  extern int mutex_trylock(struct mutex * ) ;
  #line 169
  extern void mutex_unlock(struct mutex * ) ;
  #line 82 "include/linux/jiffies.h"
  extern unsigned long volatile   jiffies ;
  #line 298
  extern unsigned long msecs_to_jiffies(unsigned int  ) ;
  #line 57 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
  __inline static unsigned int readl(void const volatile   *addr ) 
  { unsigned int ret ;
    unsigned int volatile   *__cil_tmp3 ;
  
    {
  #line 57
    __cil_tmp3 = (unsigned int volatile   *)addr;
  #line 57
    __asm__  volatile   ("movl %1,%0": "=r" (ret): "m" (*__cil_tmp3): "memory");
  #line 57
    return (ret);
  }
  }
  #line 65 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
  __inline static void writel(unsigned int val , void volatile   *addr ) 
  { unsigned int volatile   *__cil_tmp3 ;
  
    {
  #line 65
    __cil_tmp3 = (unsigned int volatile   *)addr;
  #line 65
    __asm__  volatile   ("movl %0,%1": : "r" (val), "m" (*__cil_tmp3): "memory");
  #line 66
    return;
  }
  }
  #line 39 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/smp.h"
  extern int cpu_number ;
  #line 200 "include/linux/rcupdate.h"
  extern int debug_lockdep_rcu_enabled(void) ;
  #line 254 "include/linux/rcupdate.h"
  __inline static int rcu_read_lock_sched_held(void) 
  { 
  
    {
  #line 256
    return (1);
  }
  }
  #line 666 "include/linux/rcupdate.h"
  __inline static void rcu_read_lock_sched_notrace(void) 
  { 
  
    {
  #line 670
    return;
  }
  }
  #line 65 "include/linux/jump_label.h"
  __inline static bool static_branch(struct jump_label_key *key ) 
  { int tmp ;
    long tmp___0 ;
    atomic_t *__cil_tmp4 ;
    atomic_t const   *__cil_tmp5 ;
    int __cil_tmp6 ;
    long __cil_tmp7 ;
  
    {
    {
  #line 67
    __cil_tmp4 = & key->enabled;
  #line 67
    __cil_tmp5 = (atomic_t const   *)__cil_tmp4;
  #line 67
    tmp = atomic_read(__cil_tmp5);
  #line 67
    __cil_tmp6 = tmp != 0;
  #line 67
    __cil_tmp7 = (long )__cil_tmp6;
  #line 67
    tmp___0 = __builtin_expect(__cil_tmp7, 0L);
    }
  #line 67
    if (tmp___0 != 0L) {
  #line 68
      return ((bool )1);
    } else {
  
    }
  #line 69
    return ((bool )0);
  }
  }
  #line 99 "include/linux/module.h"
  extern struct module __this_module ;
  #line 3 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  int ldv_try_module_get(struct module *module ) ;
  #line 4
  void ldv_module_get(struct module *module ) ;
  #line 5
  void ldv_module_put(struct module *module ) ;
  #line 6
  unsigned int ldv_module_refcount(void) ;
  #line 7
  void ldv_module_put_and_exit(void) ;
  #line 705 "include/linux/device.h"
  extern void *dev_get_drvdata(struct device  const  * ) ;
  #line 797
  extern int dev_err(struct device  const  * , char const   *  , ...) ;
  #line 679 "include/linux/pci.h"
  extern void pci_dev_put(struct pci_dev * ) ;
  #line 720
  extern struct pci_dev *pci_get_class(unsigned int  , struct pci_dev * ) ;
  #line 723
  extern int pci_bus_read_config_byte(struct pci_bus * , unsigned int  , int  , u8 * ) ;
  #line 729
  extern int pci_bus_write_config_byte(struct pci_bus * , unsigned int  , int  , u8  ) ;
  #line 737 "include/linux/pci.h"
  __inline static int pci_read_config_byte(struct pci_dev *dev , int where , u8 *val ) 
  { int tmp ;
    struct pci_bus *__cil_tmp5 ;
    unsigned int __cil_tmp6 ;
  
    {
    {
  #line 739
    __cil_tmp5 = dev->bus;
  #line 739
    __cil_tmp6 = dev->devfn;
  #line 739
    tmp = pci_bus_read_config_byte(__cil_tmp5, __cil_tmp6, where, val);
    }
  #line 739
    return (tmp);
  }
  }
  #line 750 "include/linux/pci.h"
  __inline static int pci_write_config_byte(struct pci_dev *dev , int where , u8 val ) 
  { int tmp ;
    struct pci_bus *__cil_tmp5 ;
    unsigned int __cil_tmp6 ;
    int __cil_tmp7 ;
    u8 __cil_tmp8 ;
  
    {
    {
  #line 752
    __cil_tmp5 = dev->bus;
  #line 752
    __cil_tmp6 = dev->devfn;
  #line 752
    __cil_tmp7 = (int )val;
  #line 752
    __cil_tmp8 = (u8 )__cil_tmp7;
  #line 752
    tmp = pci_bus_write_config_byte(__cil_tmp5, __cil_tmp6, where, __cil_tmp8);
    }
  #line 752
    return (tmp);
  }
  }
  #line 764
  extern int pci_enable_device(struct pci_dev * ) ;
  #line 781
  extern void pci_disable_device(struct pci_dev * ) ;
  #line 782
  extern void pci_set_master(struct pci_dev * ) ;
  #line 813
  extern int pci_save_state(struct pci_dev * ) ;
  #line 820
  extern int pci_set_power_state(struct pci_dev * , pci_power_t  ) ;
  #line 1316 "include/linux/pci.h"
  __inline static void *pci_get_drvdata(struct pci_dev *pdev ) 
  { void *tmp ;
    struct device *__cil_tmp3 ;
    struct device  const  *__cil_tmp4 ;
  
    {
    {
  #line 1318
    __cil_tmp3 = & pdev->dev;
  #line 1318
    __cil_tmp4 = (struct device  const  *)__cil_tmp3;
  #line 1318
    tmp = dev_get_drvdata(__cil_tmp4);
    }
  #line 1318
    return (tmp);
  }
  }
  #line 16 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/delay.h"
  extern void __const_udelay(unsigned long  ) ;
  #line 46 "include/linux/delay.h"
  extern void msleep(unsigned int  ) ;
  #line 126 "include/drm/drmP.h"
  extern void drm_ut_debug_printk(unsigned int  , char const   * , char const   * ,
                                  char const   *  , ...) ;
  #line 131
  extern int drm_err(char const   * , char const   *  , ...) ;
  #line 303 "include/linux/kgdb.h"
  extern atomic_t kgdb_active ;
  #line 671 "include/drm/drm_crtc.h"
  extern void drm_mode_config_reset(struct drm_device * ) ;
  #line 1174 "include/drm/drmP.h"
  __inline static int drm_core_check_feature(struct drm_device *dev , int feature ) 
  { u32 __cil_tmp3 ;
    struct drm_driver *__cil_tmp4 ;
    u32 __cil_tmp5 ;
    unsigned int __cil_tmp6 ;
  
    {
    {
  #line 1177
    __cil_tmp3 = (u32 )feature;
  #line 1177
    __cil_tmp4 = dev->driver;
  #line 1177
    __cil_tmp5 = __cil_tmp4->driver_features;
  #line 1177
    __cil_tmp6 = __cil_tmp5 & __cil_tmp3;
  #line 1177
    return (__cil_tmp6 != 0U);
    }
  }
  }
  #line 1238
  extern long drm_ioctl(struct file * , unsigned int  , unsigned long  ) ;
  #line 1381
  extern int drm_irq_install(struct drm_device * ) ;
  #line 1382
  extern int drm_irq_uninstall(struct drm_device * ) ;
  #line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
  struct tracepoint __tracepoint_i915_reg_rw ;
  #line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
  __inline static void trace_i915_reg_rw(bool write , u32 reg , u64 val , int len ) 
  { struct tracepoint_func *it_func_ptr ;
    void *it_func ;
    void *__data ;
    struct tracepoint_func *_________p1 ;
    bool __warned ;
    int tmp ;
    int tmp___0 ;
    bool tmp___1 ;
    struct jump_label_key *__cil_tmp13 ;
    struct tracepoint_func **__cil_tmp14 ;
    struct tracepoint_func * volatile  *__cil_tmp15 ;
    struct tracepoint_func * volatile  __cil_tmp16 ;
    int __cil_tmp17 ;
    int __cil_tmp18 ;
    struct tracepoint_func *__cil_tmp19 ;
    unsigned long __cil_tmp20 ;
    unsigned long __cil_tmp21 ;
    void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
    int __cil_tmp23 ;
    bool __cil_tmp24 ;
    void *__cil_tmp25 ;
    unsigned long __cil_tmp26 ;
    void *__cil_tmp27 ;
    unsigned long __cil_tmp28 ;
  
    {
    {
  #line 387
    __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
  #line 387
    tmp___1 = static_branch(__cil_tmp13);
    }
  #line 387
    if ((int )tmp___1) {
      {
  #line 387
      rcu_read_lock_sched_notrace();
  #line 387
      __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
  #line 387
      __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
  #line 387
      __cil_tmp16 = *__cil_tmp15;
  #line 387
      _________p1 = (struct tracepoint_func *)__cil_tmp16;
  #line 387
      tmp = debug_lockdep_rcu_enabled();
      }
  #line 387
      if (tmp != 0) {
  #line 387
        if (! __warned) {
          {
  #line 387
          tmp___0 = rcu_read_lock_sched_held();
          }
  #line 387
          if (tmp___0 == 0) {
            {
  #line 387
            __warned = (bool )1;
  #line 387
            __cil_tmp17 = (int const   )411;
  #line 387
            __cil_tmp18 = (int )__cil_tmp17;
  #line 387
            lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                    __cil_tmp18);
            }
          } else {
  
          }
        } else {
  
        }
      } else {
  
      }
  #line 387
      it_func_ptr = _________p1;
      {
  #line 387
      __cil_tmp19 = (struct tracepoint_func *)0;
  #line 387
      __cil_tmp20 = (unsigned long )__cil_tmp19;
  #line 387
      __cil_tmp21 = (unsigned long )it_func_ptr;
  #line 387
      if (__cil_tmp21 != __cil_tmp20) {
        ldv_36536: 
        {
  #line 387
        it_func = it_func_ptr->func;
  #line 387
        __data = it_func_ptr->data;
  #line 387
        __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
  #line 387
        __cil_tmp23 = (int )write;
  #line 387
        __cil_tmp24 = (bool )__cil_tmp23;
  #line 387
        (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
  #line 387
        it_func_ptr = it_func_ptr + 1;
        }
        {
  #line 387
        __cil_tmp25 = (void *)0;
  #line 387
        __cil_tmp26 = (unsigned long )__cil_tmp25;
  #line 387
        __cil_tmp27 = it_func_ptr->func;
  #line 387
        __cil_tmp28 = (unsigned long )__cil_tmp27;
  #line 387
        if (__cil_tmp28 != __cil_tmp26) {
  #line 388
          goto ldv_36536;
        } else {
  #line 390
          goto ldv_36537;
        }
        }
        ldv_36537: ;
      } else {
  
      }
      }
      {
  #line 387
      rcu_read_lock_sched_notrace();
      }
    } else {
  
    }
  #line 389
    return;
  }
  }
  #line 987 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  struct drm_ioctl_desc i915_ioctls[42U] ;
  #line 988
  int i915_max_ioctl ;
  #line 989
  unsigned int i915_fbpercrtc ;
  #line 990
  int i915_panel_ignore_lid ;
  #line 991
  unsigned int i915_powersave ;
  #line 992
  unsigned int i915_semaphores ;
  #line 993
  unsigned int i915_lvds_downclock ;
  #line 994
  unsigned int i915_panel_use_ssc ;
  #line 995
  int i915_vbt_sdvo_panel_type ;
  #line 996
  unsigned int i915_enable_rc6 ;
  #line 997
  unsigned int i915_enable_fbc ;
  #line 999
  int i915_suspend(struct drm_device *dev , pm_message_t state ) ;
  #line 1000
  int i915_resume(struct drm_device *dev ) ;
  #line 1001
  int i915_master_create(struct drm_device *dev , struct drm_master *master ) ;
  #line 1002
  void i915_master_destroy(struct drm_device *dev , struct drm_master *master ) ;
  #line 1006
  int i915_driver_load(struct drm_device *dev , unsigned long flags ) ;
  #line 1007
  int i915_driver_unload(struct drm_device *dev ) ;
  #line 1008
  int i915_driver_open(struct drm_device *dev , struct drm_file *file ) ;
  #line 1009
  void i915_driver_lastclose(struct drm_device *dev ) ;
  #line 1010
  void i915_driver_preclose(struct drm_device *dev , struct drm_file *file_priv ) ;
  #line 1012
  void i915_driver_postclose(struct drm_device *dev , struct drm_file *file ) ;
  #line 1014
  int i915_driver_device_is_agp(struct drm_device *dev ) ;
  #line 1015
  long i915_compat_ioctl(struct file *filp , unsigned int cmd , unsigned long arg ) ;
  #line 1020
  int i915_reset(struct drm_device *dev , u8 flags ) ;
  #line 1113
  int i915_gem_init_object(struct drm_gem_object *obj ) ;
  #line 1119
  void i915_gem_free_object(struct drm_gem_object *gem_obj ) ;
  #line 1134
  int i915_gem_dumb_create(struct drm_file *file , struct drm_device *dev , struct drm_mode_create_dumb *args ) ;
  #line 1137
  int i915_gem_mmap_gtt(struct drm_file *file , struct drm_device *dev , uint32_t handle ,
                        uint64_t *offset ) ;
  #line 1139
  int i915_gem_dumb_destroy(struct drm_file *file , struct drm_device *dev , uint32_t handle ) ;
  #line 1162
  void i915_gem_reset(struct drm_device *dev ) ;
  #line 1168
  int i915_gem_init_ringbuffer(struct drm_device *dev ) ;
  #line 1175
  int i915_gem_idle(struct drm_device *dev ) ;
  #line 1181
  int i915_gem_fault(struct vm_area_struct *vma , struct vm_fault *vmf ) ;
  #line 1203
  void i915_gem_restore_gtt_mappings(struct drm_device *dev ) ;
  #line 1234
  int i915_debugfs_init(struct drm_minor *minor ) ;
  #line 1235
  void i915_debugfs_cleanup(struct drm_minor *minor ) ;
  #line 1238
  int i915_save_state(struct drm_device *dev ) ;
  #line 1239
  int i915_restore_state(struct drm_device *dev ) ;
  #line 1250 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  __inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter ) 
  { struct i2c_adapter  const  *__mptr ;
    struct i2c_adapter *__cil_tmp3 ;
    unsigned long __cil_tmp4 ;
    struct intel_gmbus *__cil_tmp5 ;
    struct i2c_adapter *__cil_tmp6 ;
    unsigned long __cil_tmp7 ;
    int __cil_tmp8 ;
  
    {
  #line 1252
    __mptr = (struct i2c_adapter  const  *)adapter;
    {
  #line 1252
    __cil_tmp3 = (struct i2c_adapter *)0;
  #line 1252
    __cil_tmp4 = (unsigned long )__cil_tmp3;
  #line 1252
    __cil_tmp5 = (struct intel_gmbus *)__mptr;
  #line 1252
    __cil_tmp6 = __cil_tmp5->force_bit;
  #line 1252
    __cil_tmp7 = (unsigned long )__cil_tmp6;
  #line 1252
    __cil_tmp8 = __cil_tmp7 != __cil_tmp4;
  #line 1252
    return ((bool )__cil_tmp8);
    }
  }
  }
  #line 1257
  int intel_opregion_setup(struct drm_device *dev ) ;
  #line 1259
  void intel_opregion_init(struct drm_device *dev ) ;
  #line 1260
  void intel_opregion_fini(struct drm_device *dev ) ;
  #line 1293
  void ironlake_enable_rc6(struct drm_device *dev ) ;
  #line 1295
  void intel_detect_pch(struct drm_device *dev ) ;
  #line 1335
  void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv ) ;
  #line 1336
  void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv ) ;
  #line 1337
  void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv ) ;
  #line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  __inline static u32 i915_read32(struct drm_i915_private *dev_priv , u32 reg ) 
  { u32 val ;
    struct intel_device_info  const  *__cil_tmp4 ;
    u8 __cil_tmp5 ;
    unsigned char __cil_tmp6 ;
    unsigned int __cil_tmp7 ;
    unsigned long __cil_tmp8 ;
    void *__cil_tmp9 ;
    void const volatile   *__cil_tmp10 ;
    void const volatile   *__cil_tmp11 ;
    unsigned long __cil_tmp12 ;
    void *__cil_tmp13 ;
    void const volatile   *__cil_tmp14 ;
    void const volatile   *__cil_tmp15 ;
    unsigned long __cil_tmp16 ;
    void *__cil_tmp17 ;
    void const volatile   *__cil_tmp18 ;
    void const volatile   *__cil_tmp19 ;
    unsigned long __cil_tmp20 ;
    void *__cil_tmp21 ;
    void const volatile   *__cil_tmp22 ;
    void const volatile   *__cil_tmp23 ;
    bool __cil_tmp24 ;
    u64 __cil_tmp25 ;
  
    {
  #line 1361
    val = 0U;
    {
  #line 1361
    __cil_tmp4 = dev_priv->info;
  #line 1361
    __cil_tmp5 = __cil_tmp4->gen;
  #line 1361
    __cil_tmp6 = (unsigned char )__cil_tmp5;
  #line 1361
    __cil_tmp7 = (unsigned int )__cil_tmp6;
  #line 1361
    if (__cil_tmp7 > 5U) {
  #line 1361
      if (reg <= 262143U) {
  #line 1361
        if (reg != 41356U) {
          {
  #line 1361
          gen6_gt_force_wake_get(dev_priv);
  #line 1361
          __cil_tmp8 = (unsigned long )reg;
  #line 1361
          __cil_tmp9 = dev_priv->regs;
  #line 1361
          __cil_tmp10 = (void const volatile   *)__cil_tmp9;
  #line 1361
          __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
  #line 1361
          val = readl(__cil_tmp11);
  #line 1361
          gen6_gt_force_wake_put(dev_priv);
          }
        } else {
          {
  #line 1361
          __cil_tmp12 = (unsigned long )reg;
  #line 1361
          __cil_tmp13 = dev_priv->regs;
  #line 1361
          __cil_tmp14 = (void const volatile   *)__cil_tmp13;
  #line 1361
          __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
  #line 1361
          val = readl(__cil_tmp15);
          }
        }
      } else {
        {
  #line 1361
        __cil_tmp16 = (unsigned long )reg;
  #line 1361
        __cil_tmp17 = dev_priv->regs;
  #line 1361
        __cil_tmp18 = (void const volatile   *)__cil_tmp17;
  #line 1361
        __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
  #line 1361
        val = readl(__cil_tmp19);
        }
      }
    } else {
      {
  #line 1361
      __cil_tmp20 = (unsigned long )reg;
  #line 1361
      __cil_tmp21 = dev_priv->regs;
  #line 1361
      __cil_tmp22 = (void const volatile   *)__cil_tmp21;
  #line 1361
      __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
  #line 1361
      val = readl(__cil_tmp23);
      }
    }
    }
    {
  #line 1361
    __cil_tmp24 = (bool )0;
  #line 1361
    __cil_tmp25 = (u64 )val;
  #line 1361
    trace_i915_reg_rw(__cil_tmp24, reg, __cil_tmp25, 4);
    }
  #line 1361
    return (val);
  }
  }
  #line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
  __inline static void i915_write32(struct drm_i915_private *dev_priv , u32 reg , u32 val ) 
  { bool __cil_tmp4 ;
    u64 __cil_tmp5 ;
    struct intel_device_info  const  *__cil_tmp6 ;
    u8 __cil_tmp7 ;
    unsigned char __cil_tmp8 ;
    unsigned int __cil_tmp9 ;
    unsigned long __cil_tmp10 ;
    void *__cil_tmp11 ;
    void volatile   *__cil_tmp12 ;
    void volatile   *__cil_tmp13 ;
  
    {
    {
  #line 1375
    __cil_tmp4 = (bool )1;
  #line 1375
    __cil_tmp5 = (u64 )val;
  #line 1375
    trace_i915_reg_rw(__cil_tmp4, reg, __cil_tmp5, 4);
    }
    {
  #line 1375
    __cil_tmp6 = dev_priv->info;
  #line 1375
    __cil_tmp7 = __cil_tmp6->gen;
  #line 1375
    __cil_tmp8 = (unsigned char )__cil_tmp7;
  #line 1375
    __cil_tmp9 = (unsigned int )__cil_tmp8;
  #line 1375
    if (__cil_tmp9 > 5U) {
  #line 1375
      if (reg <= 262143U) {
  #line 1375
        if (reg != 41356U) {
          {
  #line 1375
          __gen6_gt_wait_for_fifo(dev_priv);
          }
        } else {
  
        }
      } else {
  
      }
    } else {
  
    }
    }
    {
  #line 1375
    __cil_tmp10 = (unsigned long )reg;
  #line 1375
    __cil_tmp11 = dev_priv->regs;
  #line 1375
    __cil_tmp12 = (void volatile   *)__cil_tmp11;
  #line 1375
    __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
  #line 1375
    writel(val, __cil_tmp13);
    }
  #line 1376
    return;
  }
  }
  #line 140 "include/drm/drm_crtc_helper.h"
  extern int drm_helper_resume_force_mode(struct drm_device * ) ;
  #line 145
  extern void drm_kms_helper_poll_disable(struct drm_device * ) ;
  #line 146
  extern void drm_kms_helper_poll_enable(struct drm_device * ) ;
  #line 51 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_fbpercrtc  =    0U;
  #line 54 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  int i915_panel_ignore_lid  =    0;
  #line 57 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_powersave  =    1U;
  #line 60 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_semaphores  =    0U;
  #line 63 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_enable_rc6  =    0U;
  #line 66 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_enable_fbc  =    0U;
  #line 69 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_lvds_downclock  =    0U;
  #line 72 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  unsigned int i915_panel_use_ssc  =    1U;
  #line 75 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  int i915_vbt_sdvo_panel_type  =    -1;
  #line 78 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  static bool i915_try_reset  =    (bool )1;
  #line 265 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  struct pci_device_id  const  __mod_pci_device_table  ;
  #line 273 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
  void intel_detect_pch(struct drm_device *dev ) 
  { struct drm_i915_private *dev_priv ;
    struct pci_dev *pch ;
    int id ;
    void *__cil_tmp5 ;
    struct pci_dev *__cil_tmp6 ;
    struct pci_dev *__cil_tmp7 ;
    unsigned long __cil_tmp8 ;
    unsigned long __cil_tmp9 ;
    unsigned short __cil_tmp10 ;
    unsigned int __cil_tmp11 ;
    unsigned short __cil_tmp12 ;
    int __cil_tmp13 ;
  
    {
    {
  #line 275
    __cil_tmp5 = dev->dev_private;
  #line 275
    dev_priv = (struct drm_i915_private *)__cil_tmp5;
  #line 284
    __cil_tmp6 = (struct pci_dev *)0;
  #line 284
    pch = pci_get_class(393472U, __cil_tmp6);
    }
    {
  #line 285
    __cil_tmp7 = (struct pci_dev *)0;
  #line 285
    __cil_tmp8 = (unsigned long )__cil_tmp7;
  #line 285
    __cil_tmp9 = (unsigned long )pch;
  #line 285
    if (__cil_tmp9 != __cil_tmp8) {
      {
  #line 286
      __cil_tmp10 = pch->vendor;
  #line 286
      __cil_tmp11 = (unsigned int )__cil_tmp10;
  #line 286
      if (__cil_tmp11 == 32902U) {
  #line 288
        __cil_tmp12 = pch->device;
  #line 288
        __cil_tmp13 = (int )__cil_tmp12;
  #line 288
        id = __cil_tmp13 & 65280;
  #line 290
        if (id == 15104) {
          {
  #line 291
          dev_priv->pch_type = (enum intel_pch )0;
  #line 292
          drm_ut_debug_printk(4U, "drm", "intel_detect_pch", "Found Ibex Peak PCH\n");
          }
        } else
  #line 293
        if (id == 7168) {
          {
  #line 294
          dev_priv->pch_type = (enum intel_pch )1;
  #line 295
          drm_ut_debug_printk(4U, "drm", "intel_detect_pch", "Found CougarPoint PCH\n");
          }
        } else
  #line 296
        if (id == 7680) {
          {
  #line 298
          dev_priv->pch_type = (enum intel_pch )1;
 #line 299
         drm_ut_debug_printk(4U, "drm", "intel_detect_pch", "Found PatherPoint PCH\n");
         }
       } else {
 
       }
     } else {
 
     }
     }
     {
 #line 302
     pci_dev_put(pch);
     }
   } else {
 
   }
   }
 #line 304
   return;
 }
 }
 #line 306 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv ) 
 { int count ;
   int tmp ;
   unsigned int tmp___0 ;
   int tmp___1 ;
   unsigned int tmp___2 ;
   void *__cil_tmp7 ;
   void const volatile   *__cil_tmp8 ;
   void const volatile   *__cil_tmp9 ;
   int __cil_tmp10 ;
   void *__cil_tmp11 ;
   void volatile   *__cil_tmp12 ;
   void volatile   *__cil_tmp13 ;
   void *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   void const volatile   *__cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned int __cil_tmp20 ;
 
   {
 #line 310
   count = 0;
 #line 311
   goto ldv_37927;
   ldv_37926: 
   {
 #line 312
   __const_udelay(42950UL);
   }
   ldv_37927: 
 #line 311
   tmp = count;
 #line 311
   count = count + 1;
 #line 311
   if (tmp <= 49) {
     {
 #line 311
     __cil_tmp7 = dev_priv->regs;
 #line 311
     __cil_tmp8 = (void const volatile   *)__cil_tmp7;
 #line 311
     __cil_tmp9 = __cil_tmp8 + 1245328U;
 #line 311
     tmp___0 = readl(__cil_tmp9);
     }
     {
 #line 311
     __cil_tmp10 = (int )tmp___0;
 #line 311
     if (__cil_tmp10 & 1) {
 #line 312
       goto ldv_37926;
     } else {
 #line 314
       goto ldv_37928;
     }
     }
   } else {
 #line 314
     goto ldv_37928;
   }
   ldv_37928: 
   {
 #line 314
   __cil_tmp11 = dev_priv->regs;
 #line 314
   __cil_tmp12 = (void volatile   *)__cil_tmp11;
 #line 314
   __cil_tmp13 = __cil_tmp12 + 41356U;
 #line 314
   writel(1U, __cil_tmp13);
 #line 315
   __cil_tmp14 = dev_priv->regs;
 #line 315
   __cil_tmp15 = (void const volatile   *)__cil_tmp14;
 #line 315
   __cil_tmp16 = __cil_tmp15 + 41356U;
 #line 315
   readl(__cil_tmp16);
 #line 317
   count = 0;
   }
 #line 318
   goto ldv_37930;
   ldv_37929: 
   {
 #line 319
   __const_udelay(42950UL);
   }
   ldv_37930: 
 #line 318
   tmp___1 = count;
 #line 318
   count = count + 1;
 #line 318
   if (tmp___1 <= 49) {
     {
 #line 318
     __cil_tmp17 = dev_priv->regs;
 #line 318
     __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 318
     __cil_tmp19 = __cil_tmp18 + 1245328U;
 #line 318
     tmp___2 = readl(__cil_tmp19);
     }
     {
 #line 318
     __cil_tmp20 = tmp___2 & 1U;
 #line 318
     if (__cil_tmp20 == 0U) {
 #line 319
       goto ldv_37929;
     } else {
 #line 321
       goto ldv_37931;
     }
     }
   } else {
 #line 321
     goto ldv_37931;
   }
   ldv_37931: ;
 #line 323
   return;
 }
 }
 #line 328 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv ) 
 { int __ret_warn_on ;
   int tmp ;
   long tmp___0 ;
   int tmp___1 ;
   struct drm_device *__cil_tmp6 ;
   struct mutex *__cil_tmp7 ;
   int __cil_tmp8 ;
   long __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   long __cil_tmp13 ;
   atomic_t *__cil_tmp14 ;
 
   {
   {
 #line 330
   __cil_tmp6 = dev_priv->dev;
 #line 330
   __cil_tmp7 = & __cil_tmp6->struct_mutex;
 #line 330
   tmp = mutex_is_locked(__cil_tmp7);
 #line 330
   __ret_warn_on = tmp == 0;
 #line 330
   __cil_tmp8 = __ret_warn_on != 0;
 #line 330
   __cil_tmp9 = (long )__cil_tmp8;
 #line 330
   tmp___0 = __builtin_expect(__cil_tmp9, 0L);
   }
 #line 330
   if (tmp___0 != 0L) {
     {
 #line 330
     __cil_tmp10 = (int const   )330;
 #line 330
     __cil_tmp11 = (int )__cil_tmp10;
 #line 330
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p",
                        __cil_tmp11);
     }
   } else {
 
   }
   {
 #line 330
   __cil_tmp12 = __ret_warn_on != 0;
 #line 330
   __cil_tmp13 = (long )__cil_tmp12;
 #line 330
   __builtin_expect(__cil_tmp13, 0L);
 #line 333
   __cil_tmp14 = & dev_priv->forcewake_count;
 #line 333
   tmp___1 = atomic_add_return(1, __cil_tmp14);
   }
 #line 333
   if (tmp___1 == 1) {
     {
 #line 334
     __gen6_gt_force_wake_get(dev_priv);
     }
   } else {
 
   }
 #line 335
   return;
 }
 }
 #line 337 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv ) 
 { void *__cil_tmp2 ;
   void volatile   *__cil_tmp3 ;
   void volatile   *__cil_tmp4 ;
   void *__cil_tmp5 ;
   void const volatile   *__cil_tmp6 ;
   void const volatile   *__cil_tmp7 ;
 
   {
   {
 #line 339
   __cil_tmp2 = dev_priv->regs;
 #line 339
   __cil_tmp3 = (void volatile   *)__cil_tmp2;
 #line 339
   __cil_tmp4 = __cil_tmp3 + 41356U;
 #line 339
   writel(0U, __cil_tmp4);
 #line 340
   __cil_tmp5 = dev_priv->regs;
 #line 340
   __cil_tmp6 = (void const volatile   *)__cil_tmp5;
 #line 340
   __cil_tmp7 = __cil_tmp6 + 41356U;
 #line 340
   readl(__cil_tmp7);
   }
 #line 341
   return;
 }
 }
 #line 346 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv ) 
 { int __ret_warn_on ;
   int tmp ;
   long tmp___0 ;
   int tmp___1 ;
   struct drm_device *__cil_tmp6 ;
   struct mutex *__cil_tmp7 ;
   int __cil_tmp8 ;
   long __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   long __cil_tmp13 ;
   atomic_t *__cil_tmp14 ;
 
   {
   {
 #line 348
   __cil_tmp6 = dev_priv->dev;
 #line 348
   __cil_tmp7 = & __cil_tmp6->struct_mutex;
 #line 348
   tmp = mutex_is_locked(__cil_tmp7);
 #line 348
   __ret_warn_on = tmp == 0;
 #line 348
   __cil_tmp8 = __ret_warn_on != 0;
 #line 348
   __cil_tmp9 = (long )__cil_tmp8;
 #line 348
   tmp___0 = __builtin_expect(__cil_tmp9, 0L);
   }
 #line 348
   if (tmp___0 != 0L) {
     {
 #line 348
     __cil_tmp10 = (int const   )348;
 #line 348
     __cil_tmp11 = (int )__cil_tmp10;
 #line 348
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p",
                        __cil_tmp11);
     }
   } else {
 
   }
   {
 #line 348
   __cil_tmp12 = __ret_warn_on != 0;
 #line 348
   __cil_tmp13 = (long )__cil_tmp12;
 #line 348
   __builtin_expect(__cil_tmp13, 0L);
 #line 350
   __cil_tmp14 = & dev_priv->forcewake_count;
 #line 350
   tmp___1 = atomic_dec_and_test(__cil_tmp14);
   }
 #line 350
   if (tmp___1 != 0) {
     {
 #line 351
     __gen6_gt_force_wake_put(dev_priv);
     }
   } else {
 
   }
 #line 352
   return;
 }
 }
 #line 354 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv ) 
 { int loop ;
   u32 fifo ;
   unsigned int tmp ;
   int tmp___0 ;
   void *__cil_tmp6 ;
   void const volatile   *__cil_tmp7 ;
   void const volatile   *__cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
 
   {
   {
 #line 356
   loop = 500;
 #line 357
   __cil_tmp6 = dev_priv->regs;
 #line 357
   __cil_tmp7 = (void const volatile   *)__cil_tmp6;
 #line 357
   __cil_tmp8 = __cil_tmp7 + 1179656U;
 #line 357
   tmp = readl(__cil_tmp8);
 #line 357
   fifo = tmp;
   }
 #line 358
   goto ldv_37951;
   ldv_37950: 
   {
 #line 359
   __const_udelay(42950UL);
 #line 360
   __cil_tmp9 = dev_priv->regs;
 #line 360
   __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 360
   __cil_tmp11 = __cil_tmp10 + 1179656U;
 #line 360
   fifo = readl(__cil_tmp11);
   }
   ldv_37951: ;
 #line 358
   if (fifo <= 19U) {
 #line 358
     tmp___0 = loop;
 #line 358
     loop = loop - 1;
 #line 358
     if (tmp___0 != 0) {
 #line 359
       goto ldv_37950;
     } else {
 #line 361
       goto ldv_37952;
     }
   } else {
 #line 361
     goto ldv_37952;
   }
   ldv_37952: ;
 #line 363
   return;
 }
 }
 #line 364 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int i915_drm_freeze(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int error ;
   int tmp ;
   int tmp___0 ;
   void *__cil_tmp6 ;
   struct pci_dev *__cil_tmp7 ;
   struct pci_dev *__cil_tmp8 ;
   struct device *__cil_tmp9 ;
   struct device  const  *__cil_tmp10 ;
 
   {
   {
 #line 366
   __cil_tmp6 = dev->dev_private;
 #line 366
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
 #line 368
   drm_kms_helper_poll_disable(dev);
 #line 370
   __cil_tmp7 = dev->pdev;
 #line 370
   pci_save_state(__cil_tmp7);
 #line 373
   tmp___0 = drm_core_check_feature(dev, 8192);
   }
 #line 373
   if (tmp___0 != 0) {
     {
 #line 374
     tmp = i915_gem_idle(dev);
 #line 374
     error = tmp;
     }
 #line 375
     if (error != 0) {
       {
 #line 376
       __cil_tmp8 = dev->pdev;
 #line 376
       __cil_tmp9 = & __cil_tmp8->dev;
 #line 376
       __cil_tmp10 = (struct device  const  *)__cil_tmp9;
 #line 376
       dev_err(__cil_tmp10, "GEM idle failed, resume might fail\n");
       }
 #line 378
       return (error);
     } else {
 
     }
     {
 #line 380
     drm_irq_uninstall(dev);
     }
   } else {
 
   }
   {
 #line 383
   i915_save_state(dev);
 #line 385
   intel_opregion_fini(dev);
 #line 388
   dev_priv->modeset_on_lid = (bool )0;
   }
 #line 390
   return (0);
 }
 }
 #line 393 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 int i915_suspend(struct drm_device *dev , pm_message_t state ) 
 { int error ;
   struct drm_device *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   void *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   int __cil_tmp11 ;
   struct pci_dev *__cil_tmp12 ;
   struct pci_dev *__cil_tmp13 ;
 
   {
   {
 #line 397
   __cil_tmp4 = (struct drm_device *)0;
 #line 397
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 397
   __cil_tmp6 = (unsigned long )dev;
 #line 397
   if (__cil_tmp6 == __cil_tmp5) {
     {
 #line 398
     drm_err("i915_suspend", "dev: %p\n", dev);
 #line 399
     drm_err("i915_suspend", "DRM not initialized, aborting suspend.\n");
     }
 #line 400
     return (-19);
   } else {
     {
 #line 397
     __cil_tmp7 = (void *)0;
 #line 397
     __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 397
     __cil_tmp9 = dev->dev_private;
 #line 397
     __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 397
     if (__cil_tmp10 == __cil_tmp8) {
       {
 #line 398
       drm_err("i915_suspend", "dev: %p\n", dev);
 #line 399
       drm_err("i915_suspend", "DRM not initialized, aborting suspend.\n");
       }
 #line 400
       return (-19);
     } else {
 
     }
     }
   }
   }
 #line 403
   if (state.event == 8) {
 #line 404
     return (0);
   } else {
 
   }
   {
 #line 407
   __cil_tmp11 = dev->switch_power_state;
 #line 407
   if (__cil_tmp11 == 1) {
 #line 408
     return (0);
   } else {
 
   }
   }
   {
 #line 410
   error = i915_drm_freeze(dev);
   }
 #line 411
   if (error != 0) {
 #line 412
     return (error);
   } else {
 
   }
 #line 414
   if (state.event == 2) {
     {
 #line 416
     __cil_tmp12 = dev->pdev;
 #line 416
     pci_disable_device(__cil_tmp12);
 #line 417
     __cil_tmp13 = dev->pdev;
 #line 417
     pci_set_power_state(__cil_tmp13, 3);
     }
   } else {
 
   }
 #line 420
   return (0);
 }
 }
 #line 423 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int i915_drm_thaw(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int error ;
   int tmp ;
   int tmp___0 ;
   void *__cil_tmp6 ;
   struct mutex *__cil_tmp7 ;
   struct mutex *__cil_tmp8 ;
   struct mutex *__cil_tmp9 ;
   struct mutex *__cil_tmp10 ;
   int __cil_tmp11 ;
 
   {
   {
 #line 425
   __cil_tmp6 = dev->dev_private;
 #line 425
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
 #line 426
   error = 0;
 #line 428
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 428
   if (tmp != 0) {
     {
 #line 429
     __cil_tmp7 = & dev->struct_mutex;
 #line 429
     mutex_lock_nested(__cil_tmp7, 0U);
 #line 430
     i915_gem_restore_gtt_mappings(dev);
 #line 431
     __cil_tmp8 = & dev->struct_mutex;
 #line 431
     mutex_unlock(__cil_tmp8);
     }
   } else {
 
   }
   {
 #line 434
   i915_restore_state(dev);
 #line 435
   intel_opregion_setup(dev);
 #line 438
   tmp___0 = drm_core_check_feature(dev, 8192);
   }
 #line 438
   if (tmp___0 != 0) {
     {
 #line 439
     __cil_tmp9 = & dev->struct_mutex;
 #line 439
     mutex_lock_nested(__cil_tmp9, 0U);
 #line 440
     dev_priv->mm.suspended = 0;
 #line 442
     error = i915_gem_init_ringbuffer(dev);
 #line 443
     __cil_tmp10 = & dev->struct_mutex;
 #line 443
     mutex_unlock(__cil_tmp10);
 #line 445
     drm_mode_config_reset(dev);
 #line 446
     drm_irq_install(dev);
 #line 449
     drm_helper_resume_force_mode(dev);
     }
     {
 #line 451
     __cil_tmp11 = dev->pci_device;
 #line 451
     if (__cil_tmp11 == 70) {
       {
 #line 452
       ironlake_enable_rc6(dev);
       }
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 455
   intel_opregion_init(dev);
 #line 457
   dev_priv->modeset_on_lid = (bool )0;
   }
 #line 459
   return (error);
 }
 }
 #line 462 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 int i915_resume(struct drm_device *dev ) 
 { int ret ;
   int tmp ;
   int __cil_tmp4 ;
   struct pci_dev *__cil_tmp5 ;
   struct pci_dev *__cil_tmp6 ;
 
   {
   {
 #line 466
   __cil_tmp4 = dev->switch_power_state;
 #line 466
   if (__cil_tmp4 == 1) {
 #line 467
     return (0);
   } else {
 
   }
   }
   {
 #line 469
   __cil_tmp5 = dev->pdev;
 #line 469
   tmp = pci_enable_device(__cil_tmp5);
   }
 #line 469
   if (tmp != 0) {
 #line 470
     return (-5);
   } else {
 
   }
   {
 #line 472
   __cil_tmp6 = dev->pdev;
 #line 472
   pci_set_master(__cil_tmp6);
 #line 474
   ret = i915_drm_thaw(dev);
   }
 #line 475
   if (ret != 0) {
 #line 476
     return (ret);
   } else {
 
   }
   {
 #line 478
   drm_kms_helper_poll_enable(dev);
   }
 #line 479
   return (0);
 }
 }
 #line 482 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int i8xx_do_reset(struct drm_device *dev , u8 flags ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   u32 tmp___0 ;
   void *__cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   unsigned char *__cil_tmp10 ;
   unsigned char *__cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   void *__cil_tmp15 ;
   void const volatile   *__cil_tmp16 ;
   void const volatile   *__cil_tmp17 ;
   int __cil_tmp18 ;
   void *__cil_tmp19 ;
   void const volatile   *__cil_tmp20 ;
   void const volatile   *__cil_tmp21 ;
   void *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   void const volatile   *__cil_tmp24 ;
   int __cil_tmp25 ;
   void *__cil_tmp26 ;
   void const volatile   *__cil_tmp27 ;
   void const volatile   *__cil_tmp28 ;
   void *__cil_tmp29 ;
   void const volatile   *__cil_tmp30 ;
   void const volatile   *__cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   void *__cil_tmp33 ;
   void const volatile   *__cil_tmp34 ;
   void const volatile   *__cil_tmp35 ;
 
   {
 #line 484
   __cil_tmp6 = dev->dev_private;
 #line 484
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
   {
 #line 486
   __cil_tmp7 = dev->dev_private;
 #line 486
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 486
   __cil_tmp9 = __cil_tmp8->info;
 #line 486
   __cil_tmp10 = (unsigned char *)__cil_tmp9;
 #line 486
   __cil_tmp11 = __cil_tmp10 + 1UL;
 #line 486
   __cil_tmp12 = *__cil_tmp11;
 #line 486
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 486
   if (__cil_tmp13 != 0U) {
 #line 487
     return (-19);
   } else {
 
   }
   }
   {
 #line 489
   tmp = i915_read32(dev_priv, 24836U);
 #line 489
   __cil_tmp14 = tmp | 64U;
 #line 489
   i915_write32(dev_priv, 24836U, __cil_tmp14);
 #line 490
   __cil_tmp15 = dev_priv->regs;
 #line 490
   __cil_tmp16 = (void const volatile   *)__cil_tmp15;
 #line 490
   __cil_tmp17 = __cil_tmp16 + 24836U;
 #line 490
   readl(__cil_tmp17);
   }
   {
 #line 492
   __cil_tmp18 = dev->pci_device;
 #line 492
   if (__cil_tmp18 == 13687) {
     {
 #line 493
     i915_write32(dev_priv, 24688U, 896U);
 #line 497
     __cil_tmp19 = dev_priv->regs;
 #line 497
     __cil_tmp20 = (void const volatile   *)__cil_tmp19;
 #line 497
     __cil_tmp21 = __cil_tmp20 + 24688U;
 #line 497
     readl(__cil_tmp21);
 #line 498
     msleep(1U);
 #line 500
     i915_write32(dev_priv, 24688U, 0U);
 #line 501
     __cil_tmp22 = dev_priv->regs;
 #line 501
     __cil_tmp23 = (void const volatile   *)__cil_tmp22;
 #line 501
     __cil_tmp24 = __cil_tmp23 + 24688U;
 #line 501
     readl(__cil_tmp24);
     }
   } else {
     {
 #line 492
     __cil_tmp25 = dev->pci_device;
 #line 492
     if (__cil_tmp25 == 9570) {
       {
 #line 493
       i915_write32(dev_priv, 24688U, 896U);
 #line 497
       __cil_tmp26 = dev_priv->regs;
 #line 497
       __cil_tmp27 = (void const volatile   *)__cil_tmp26;
 #line 497
       __cil_tmp28 = __cil_tmp27 + 24688U;
 #line 497
       readl(__cil_tmp28);
 #line 498
       msleep(1U);
 #line 500
       i915_write32(dev_priv, 24688U, 0U);
 #line 501
       __cil_tmp29 = dev_priv->regs;
 #line 501
       __cil_tmp30 = (void const volatile   *)__cil_tmp29;
 #line 501
       __cil_tmp31 = __cil_tmp30 + 24688U;
 #line 501
       readl(__cil_tmp31);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 504
   msleep(1U);
 #line 506
   tmp___0 = i915_read32(dev_priv, 24836U);
 #line 506
   __cil_tmp32 = tmp___0 & 4294967231U;
 #line 506
   i915_write32(dev_priv, 24836U, __cil_tmp32);
 #line 507
   __cil_tmp33 = dev_priv->regs;
 #line 507
   __cil_tmp34 = (void const volatile   *)__cil_tmp33;
 #line 507
   __cil_tmp35 = __cil_tmp34 + 24836U;
 #line 507
   readl(__cil_tmp35);
   }
 #line 509
   return (0);
 }
 }
 #line 512 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int i965_reset_complete(struct drm_device *dev ) 
 { u8 gdrst ;
   struct pci_dev *__cil_tmp3 ;
   int __cil_tmp4 ;
 
   {
   {
 #line 515
   __cil_tmp3 = dev->pdev;
 #line 515
   pci_read_config_byte(__cil_tmp3, 192, & gdrst);
   }
   {
 #line 516
   __cil_tmp4 = (int )gdrst;
 #line 516
   return (__cil_tmp4 & 1);
   }
 }
 }
 #line 519 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int i965_do_reset(struct drm_device *dev , u8 flags ) 
 { u8 gdrst ;
   unsigned long timeout__ ;
   unsigned long tmp ;
   int ret__ ;
   struct thread_info *tmp___0 ;
   int pfo_ret__ ;
   int tmp___1 ;
   int tmp___2 ;
   struct pci_dev *__cil_tmp11 ;
   struct pci_dev *__cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   u8 __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   long __cil_tmp23 ;
   long __cil_tmp24 ;
   long __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   atomic_t const   *__cil_tmp28 ;
 
   {
   {
 #line 528
   __cil_tmp11 = dev->pdev;
 #line 528
   pci_read_config_byte(__cil_tmp11, 192, & gdrst);
 #line 529
   __cil_tmp12 = dev->pdev;
 #line 529
   __cil_tmp13 = (int )flags;
 #line 529
   __cil_tmp14 = (int )gdrst;
 #line 529
   __cil_tmp15 = __cil_tmp14 | __cil_tmp13;
 #line 529
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 529
   __cil_tmp17 = __cil_tmp16 | 1U;
 #line 529
   __cil_tmp18 = (int )__cil_tmp17;
 #line 529
   __cil_tmp19 = (u8 )__cil_tmp18;
 #line 529
   pci_write_config_byte(__cil_tmp12, 192, __cil_tmp19);
 #line 531
   __cil_tmp20 = (unsigned int const   )500U;
 #line 531
   __cil_tmp21 = (unsigned int )__cil_tmp20;
 #line 531
   tmp = msecs_to_jiffies(__cil_tmp21);
 #line 531
   __cil_tmp22 = (unsigned long )jiffies;
 #line 531
   timeout__ = tmp + __cil_tmp22;
 #line 531
   ret__ = 0;
   }
 #line 531
   goto ldv_38005;
   ldv_38004: ;
   {
 #line 531
   __cil_tmp23 = (long )jiffies;
 #line 531
   __cil_tmp24 = (long )timeout__;
 #line 531
   __cil_tmp25 = __cil_tmp24 - __cil_tmp23;
 #line 531
   if (__cil_tmp25 < 0L) {
 #line 531
     ret__ = -110;
 #line 531
     goto ldv_37995;
   } else {
 
   }
   }
   {
 #line 531
   tmp___0 = current_thread_info();
   }
   {
 #line 531
   __cil_tmp26 = tmp___0->preempt_count;
 #line 531
   __cil_tmp27 = __cil_tmp26 & -268435457;
 #line 531
   if (__cil_tmp27 == 0) {
 #line 531
     if (1) {
 #line 531
       goto case_4;
     } else {
 #line 531
       goto switch_default;
 #line 531
       if (0) {
 #line 531
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 531
         goto ldv_37998;
 #line 531
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 531
         goto ldv_37998;
         case_4: 
 #line 531
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 531
         goto ldv_37998;
 #line 531
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 531
         goto ldv_37998;
         switch_default: 
         {
 #line 531
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_37998: 
     {
 #line 531
     __cil_tmp28 = (atomic_t const   *)(& kgdb_active);
 #line 531
     tmp___1 = atomic_read(__cil_tmp28);
     }
 #line 531
     if (pfo_ret__ != tmp___1) {
       {
 #line 531
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38005: 
   {
 #line 531
   tmp___2 = i965_reset_complete(dev);
   }
 #line 531
   if (tmp___2 == 0) {
 #line 532
     goto ldv_38004;
   } else {
 #line 534
     goto ldv_37995;
   }
   ldv_37995: ;
 #line 531
   return (ret__);
 }
 }
 #line 534 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int ironlake_do_reset(struct drm_device *dev , u8 flags ) 
 { struct drm_i915_private *dev_priv ;
   u32 gdrst ;
   u32 tmp ;
   unsigned long timeout__ ;
   unsigned long tmp___0 ;
   int ret__ ;
   struct thread_info *tmp___1 ;
   int pfo_ret__ ;
   int tmp___2 ;
   u32 tmp___3 ;
   void *__cil_tmp13 ;
   u32 __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   long __cil_tmp20 ;
   long __cil_tmp21 ;
   long __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   atomic_t const   *__cil_tmp25 ;
   unsigned int __cil_tmp26 ;
 
   {
   {
 #line 536
   __cil_tmp13 = dev->dev_private;
 #line 536
   dev_priv = (struct drm_i915_private *)__cil_tmp13;
 #line 537
   tmp = i915_read32(dev_priv, 76964U);
 #line 537
   gdrst = tmp;
 #line 538
   __cil_tmp14 = (u32 )flags;
 #line 538
   __cil_tmp15 = __cil_tmp14 | gdrst;
 #line 538
   __cil_tmp16 = __cil_tmp15 | 1U;
 #line 538
   i915_write32(dev_priv, 76964U, __cil_tmp16);
 #line 539
   __cil_tmp17 = (unsigned int const   )500U;
 #line 539
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 539
   tmp___0 = msecs_to_jiffies(__cil_tmp18);
 #line 539
   __cil_tmp19 = (unsigned long )jiffies;
 #line 539
   timeout__ = tmp___0 + __cil_tmp19;
 #line 539
   ret__ = 0;
   }
 #line 539
   goto ldv_38031;
   ldv_38030: ;
   {
 #line 539
   __cil_tmp20 = (long )jiffies;
 #line 539
   __cil_tmp21 = (long )timeout__;
 #line 539
   __cil_tmp22 = __cil_tmp21 - __cil_tmp20;
 #line 539
   if (__cil_tmp22 < 0L) {
 #line 539
     ret__ = -110;
 #line 539
     goto ldv_38021;
   } else {
 
   }
   }
   {
 #line 539
   tmp___1 = current_thread_info();
   }
   {
 #line 539
   __cil_tmp23 = tmp___1->preempt_count;
 #line 539
   __cil_tmp24 = __cil_tmp23 & -268435457;
 #line 539
   if (__cil_tmp24 == 0) {
 #line 539
     if (1) {
 #line 539
       goto case_4;
     } else {
 #line 539
       goto switch_default;
 #line 539
       if (0) {
 #line 539
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 539
         goto ldv_38024;
 #line 539
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 539
         goto ldv_38024;
         case_4: 
 #line 539
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 539
         goto ldv_38024;
 #line 539
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 539
         goto ldv_38024;
         switch_default: 
         {
 #line 539
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_38024: 
     {
 #line 539
     __cil_tmp25 = (atomic_t const   *)(& kgdb_active);
 #line 539
     tmp___2 = atomic_read(__cil_tmp25);
     }
 #line 539
     if (pfo_ret__ != tmp___2) {
       {
 #line 539
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38031: 
   {
 #line 539
   tmp___3 = i915_read32(dev_priv, 76964U);
   }
   {
 #line 539
   __cil_tmp26 = tmp___3 & 1U;
 #line 539
   if (__cil_tmp26 == 0U) {
 #line 540
     goto ldv_38030;
   } else {
 #line 542
     goto ldv_38021;
   }
   }
   ldv_38021: ;
 #line 539
   return (ret__);
 }
 }
 #line 542 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 static int gen6_do_reset(struct drm_device *dev , u8 flags ) 
 { struct drm_i915_private *dev_priv ;
   unsigned long timeout__ ;
   unsigned long tmp ;
   int ret__ ;
   struct thread_info *tmp___0 ;
   int pfo_ret__ ;
   int tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   long __cil_tmp15 ;
   long __cil_tmp16 ;
   long __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   atomic_t const   *__cil_tmp20 ;
   int __cil_tmp21 ;
 
   {
   {
 #line 544
   __cil_tmp11 = dev->dev_private;
 #line 544
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 546
   i915_write32(dev_priv, 37916U, 1U);
 #line 547
   __cil_tmp12 = (unsigned int const   )500U;
 #line 547
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 547
   tmp = msecs_to_jiffies(__cil_tmp13);
 #line 547
   __cil_tmp14 = (unsigned long )jiffies;
 #line 547
   timeout__ = tmp + __cil_tmp14;
 #line 547
   ret__ = 0;
   }
 #line 547
   goto ldv_38056;
   ldv_38055: ;
   {
 #line 547
   __cil_tmp15 = (long )jiffies;
 #line 547
   __cil_tmp16 = (long )timeout__;
 #line 547
   __cil_tmp17 = __cil_tmp16 - __cil_tmp15;
 #line 547
   if (__cil_tmp17 < 0L) {
 #line 547
     ret__ = -110;
 #line 547
     goto ldv_38046;
   } else {
 
   }
   }
   {
 #line 547
   tmp___0 = current_thread_info();
   }
   {
 #line 547
   __cil_tmp18 = tmp___0->preempt_count;
 #line 547
   __cil_tmp19 = __cil_tmp18 & -268435457;
 #line 547
   if (__cil_tmp19 == 0) {
 #line 547
     if (1) {
 #line 547
       goto case_4;
     } else {
 #line 547
       goto switch_default;
 #line 547
       if (0) {
 #line 547
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 547
         goto ldv_38049;
 #line 547
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 547
         goto ldv_38049;
         case_4: 
 #line 547
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 547
         goto ldv_38049;
 #line 547
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 547
         goto ldv_38049;
         switch_default: 
         {
 #line 547
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_38049: 
     {
 #line 547
     __cil_tmp20 = (atomic_t const   *)(& kgdb_active);
 #line 547
     tmp___1 = atomic_read(__cil_tmp20);
     }
 #line 547
     if (pfo_ret__ != tmp___1) {
       {
 #line 547
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38056: 
   {
 #line 547
   tmp___2 = i915_read32(dev_priv, 37916U);
   }
   {
 #line 547
   __cil_tmp21 = (int )tmp___2;
 #line 547
   if (__cil_tmp21 & 1) {
 #line 548
     goto ldv_38055;
   } else {
 #line 550
     goto ldv_38046;
   }
   }
   ldv_38046: ;
 #line 547
   return (ret__);
 }
 }
 #line 566 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 int i915_reset(struct drm_device *dev , u8 flags ) 
 { drm_i915_private_t *dev_priv ;
   bool need_display ;
   int ret ;
   int tmp ;
   int tmp___0 ;
   unsigned long tmp___1 ;
   int tmp___2 ;
   void *__cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   u8 __cil_tmp17 ;
   int __cil_tmp18 ;
   void *__cil_tmp19 ;
   struct drm_i915_private *__cil_tmp20 ;
   struct intel_device_info  const  *__cil_tmp21 ;
   u8 __cil_tmp22 ;
   int __cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_device_info  const  *__cil_tmp26 ;
   u8 __cil_tmp27 ;
   int __cil_tmp28 ;
   void *__cil_tmp29 ;
   struct drm_i915_private *__cil_tmp30 ;
   struct intel_device_info  const  *__cil_tmp31 ;
   u8 __cil_tmp32 ;
   int __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   u8 __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   u8 __cil_tmp40 ;
   atomic_t *__cil_tmp41 ;
   atomic_t const   *__cil_tmp42 ;
   int __cil_tmp43 ;
   u8 __cil_tmp44 ;
   int __cil_tmp45 ;
   u8 __cil_tmp46 ;
   int __cil_tmp47 ;
   u8 __cil_tmp48 ;
   struct mutex *__cil_tmp49 ;
   int __cil_tmp50 ;
   int (*__cil_tmp51)(struct intel_ring_buffer * ) ;
   struct intel_ring_buffer (*__cil_tmp52)[3U] ;
   struct intel_ring_buffer *__cil_tmp53 ;
   void *__cil_tmp54 ;
   struct drm_i915_private *__cil_tmp55 ;
   struct intel_device_info  const  *__cil_tmp56 ;
   unsigned char *__cil_tmp57 ;
   unsigned char *__cil_tmp58 ;
   unsigned char __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   int (*__cil_tmp61)(struct intel_ring_buffer * ) ;
   struct intel_ring_buffer (*__cil_tmp62)[3U] ;
   struct intel_ring_buffer *__cil_tmp63 ;
   struct intel_ring_buffer *__cil_tmp64 ;
   void *__cil_tmp65 ;
   struct drm_i915_private *__cil_tmp66 ;
   struct intel_device_info  const  *__cil_tmp67 ;
   unsigned char *__cil_tmp68 ;
   unsigned char *__cil_tmp69 ;
   unsigned char __cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   int (*__cil_tmp72)(struct intel_ring_buffer * ) ;
   struct intel_ring_buffer (*__cil_tmp73)[3U] ;
   struct intel_ring_buffer *__cil_tmp74 ;
   struct intel_ring_buffer *__cil_tmp75 ;
   struct mutex *__cil_tmp76 ;
   struct mutex *__cil_tmp77 ;
   struct mutex *__cil_tmp78 ;
   struct mutex *__cil_tmp79 ;
   struct mutex *__cil_tmp80 ;
 
   {
 #line 568
   __cil_tmp10 = dev->dev_private;
 #line 568
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 573
   need_display = (bool )1;
 #line 576
   if (! i915_try_reset) {
 #line 577
     return (0);
   } else {
 
   }
   {
 #line 579
   __cil_tmp11 = & dev->struct_mutex;
 #line 579
   tmp = mutex_trylock(__cil_tmp11);
   }
 #line 579
   if (tmp == 0) {
 #line 580
     return (-16);
   } else {
 
   }
   {
 #line 582
   i915_gem_reset(dev);
 #line 584
   ret = -19;
 #line 585
   tmp___1 = get_seconds();
   }
   {
 #line 585
   __cil_tmp12 = dev_priv->last_gpu_reset;
 #line 585
   __cil_tmp13 = tmp___1 - __cil_tmp12;
 #line 585
   if (__cil_tmp13 <= 4UL) {
     {
 #line 586
     drm_err("i915_reset", "GPU hanging too fast, declaring wedged!\n");
     }
   } else {
     {
 #line 588
     __cil_tmp14 = dev->dev_private;
 #line 588
     __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 588
     __cil_tmp16 = __cil_tmp15->info;
 #line 588
     __cil_tmp17 = __cil_tmp16->gen;
 #line 588
     __cil_tmp18 = (int )__cil_tmp17;
 #line 588
     if (__cil_tmp18 == 7) {
 #line 588
       goto case_7;
     } else {
       {
 #line 589
       __cil_tmp19 = dev->dev_private;
 #line 589
       __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
 #line 589
       __cil_tmp21 = __cil_tmp20->info;
 #line 589
       __cil_tmp22 = __cil_tmp21->gen;
 #line 589
       __cil_tmp23 = (int )__cil_tmp22;
 #line 589
       if (__cil_tmp23 == 6) {
 #line 589
         goto case_6;
       } else {
         {
 #line 595
         __cil_tmp24 = dev->dev_private;
 #line 595
         __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 595
         __cil_tmp26 = __cil_tmp25->info;
 #line 595
         __cil_tmp27 = __cil_tmp26->gen;
 #line 595
         __cil_tmp28 = (int )__cil_tmp27;
 #line 595
         if (__cil_tmp28 == 5) {
 #line 595
           goto case_5;
         } else {
           {
 #line 598
           __cil_tmp29 = dev->dev_private;
 #line 598
           __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
 #line 598
           __cil_tmp31 = __cil_tmp30->info;
 #line 598
           __cil_tmp32 = __cil_tmp31->gen;
 #line 598
           __cil_tmp33 = (int )__cil_tmp32;
 #line 598
           if (__cil_tmp33 == 4) {
 #line 598
             goto case_4;
           } else {
             {
 #line 601
             __cil_tmp34 = dev->dev_private;
 #line 601
             __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 601
             __cil_tmp36 = __cil_tmp35->info;
 #line 601
             __cil_tmp37 = __cil_tmp36->gen;
 #line 601
             __cil_tmp38 = (int )__cil_tmp37;
 #line 601
             if (__cil_tmp38 == 2) {
 #line 601
               goto case_2;
             } else
 #line 587
             if (0) {
               case_7: ;
               case_6: 
               {
 #line 590
               __cil_tmp39 = (int )flags;
 #line 590
               __cil_tmp40 = (u8 )__cil_tmp39;
 #line 590
               ret = gen6_do_reset(dev, __cil_tmp40);
 #line 592
               __cil_tmp41 = & dev_priv->forcewake_count;
 #line 592
               __cil_tmp42 = (atomic_t const   *)__cil_tmp41;
 #line 592
               tmp___0 = atomic_read(__cil_tmp42);
               }
 #line 592
               if (tmp___0 != 0) {
                 {
 #line 593
                 __gen6_gt_force_wake_get(dev_priv);
                 }
               } else {
 
               }
 #line 594
               goto ldv_38068;
               case_5: 
               {
 #line 596
               __cil_tmp43 = (int )flags;
 #line 596
               __cil_tmp44 = (u8 )__cil_tmp43;
 #line 596
               ret = ironlake_do_reset(dev, __cil_tmp44);
               }
 #line 597
               goto ldv_38068;
               case_4: 
               {
 #line 599
               __cil_tmp45 = (int )flags;
 #line 599
               __cil_tmp46 = (u8 )__cil_tmp45;
 #line 599
               ret = i965_do_reset(dev, __cil_tmp46);
               }
 #line 600
               goto ldv_38068;
               case_2: 
               {
 #line 602
               __cil_tmp47 = (int )flags;
 #line 602
               __cil_tmp48 = (u8 )__cil_tmp47;
 #line 602
               ret = i8xx_do_reset(dev, __cil_tmp48);
               }
 #line 603
               goto ldv_38068;
             } else {
 
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
     ldv_38068: ;
   }
   }
   {
 #line 605
   dev_priv->last_gpu_reset = get_seconds();
   }
 #line 606
   if (ret != 0) {
     {
 #line 607
     drm_err("i915_reset", "Failed to reset chip.\n");
 #line 608
     __cil_tmp49 = & dev->struct_mutex;
 #line 608
     mutex_unlock(__cil_tmp49);
     }
 #line 609
     return (ret);
   } else {
 
   }
   {
 #line 626
   tmp___2 = drm_core_check_feature(dev, 8192);
   }
 #line 626
   if (tmp___2 != 0) {
 #line 626
     goto _L;
   } else {
     {
 #line 626
     __cil_tmp50 = dev_priv->mm.suspended;
 #line 626
     if (__cil_tmp50 == 0) {
       _L: 
       {
 #line 628
       dev_priv->mm.suspended = 0;
 #line 630
       __cil_tmp51 = dev_priv->ring[0].init;
 #line 630
       __cil_tmp52 = & dev_priv->ring;
 #line 630
       __cil_tmp53 = (struct intel_ring_buffer *)__cil_tmp52;
 #line 630
       (*__cil_tmp51)(__cil_tmp53);
       }
       {
 #line 631
       __cil_tmp54 = dev->dev_private;
 #line 631
       __cil_tmp55 = (struct drm_i915_private *)__cil_tmp54;
 #line 631
       __cil_tmp56 = __cil_tmp55->info;
 #line 631
       __cil_tmp57 = (unsigned char *)__cil_tmp56;
 #line 631
       __cil_tmp58 = __cil_tmp57 + 3UL;
 #line 631
       __cil_tmp59 = *__cil_tmp58;
 #line 631
       __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 631
       if (__cil_tmp60 != 0U) {
         {
 #line 632
         __cil_tmp61 = dev_priv->ring[1].init;
 #line 632
         __cil_tmp62 = & dev_priv->ring;
 #line 632
         __cil_tmp63 = (struct intel_ring_buffer *)__cil_tmp62;
 #line 632
         __cil_tmp64 = __cil_tmp63 + 1UL;
 #line 632
         (*__cil_tmp61)(__cil_tmp64);
         }
       } else {
 
       }
       }
       {
 #line 633
       __cil_tmp65 = dev->dev_private;
 #line 633
       __cil_tmp66 = (struct drm_i915_private *)__cil_tmp65;
 #line 633
       __cil_tmp67 = __cil_tmp66->info;
 #line 633
       __cil_tmp68 = (unsigned char *)__cil_tmp67;
 #line 633
       __cil_tmp69 = __cil_tmp68 + 3UL;
 #line 633
       __cil_tmp70 = *__cil_tmp69;
 #line 633
       __cil_tmp71 = (unsigned int )__cil_tmp70;
 #line 633
       if (__cil_tmp71 != 0U) {
         {
 #line 634
         __cil_tmp72 = dev_priv->ring[2].init;
 #line 634
         __cil_tmp73 = & dev_priv->ring;
 #line 634
         __cil_tmp74 = (struct intel_ring_buffer *)__cil_tmp73;
 #line 634
         __cil_tmp75 = __cil_tmp74 + 2UL;
 #line 634
         (*__cil_tmp72)(__cil_tmp75);
         }
       } else {
 
       }
       }
       {
 #line 636
       __cil_tmp76 = & dev->struct_mutex;
 #line 636
       mutex_unlock(__cil_tmp76);
 #line 637
       drm_irq_uninstall(dev);
 #line 638
       drm_mode_config_reset(dev);
 #line 639
       drm_irq_install(dev);
 #line 640
       __cil_tmp77 = & dev->struct_mutex;
 #line 640
       mutex_lock_nested(__cil_tmp77, 0U);
       }
     } else {
 
     }
     }
   }
   {
 #line 643
   __cil_tmp78 = & dev->struct_mutex;
 #line 643
   mutex_unlock(__cil_tmp78);
   }
 #line 650
   if ((int )need_display) {
     {
 #line 651
     __cil_tmp79 = & dev->mode_config.mutex;
 #line 651
     mutex_lock_nested(__cil_tmp79, 0U);
 #line 652
     drm_helper_resume_force_mode(dev);
 #line 653
     __cil_tmp80 = & dev->mode_config.mutex;
 #line 653
     mutex_unlock(__cil_tmp80);
     }
   } else {
 
   }
 #line 656
   return (0);
 }
 }
 #line 886
 void ldv_check_final_state(void) ;
 #line 892
 extern void ldv_initialize(void) ;
 #line 895
 extern int nondet_int(void) ;
 #line 898 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 int LDV_IN_INTERRUPT  ;
 #line 5 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/kernel-rules/files/engine-blast-assert.h"
 void ldv_blast_assert(void) 
 { 
 
   {
   ERROR: ;
 #line 6
   goto ERROR;
 }
 }
 #line 6 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/kernel-rules/files/engine-blast.h"
 extern int ldv_undefined_int(void) ;
 #line 1654 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 int ldv_module_refcounter  =    1;
 #line 1657 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void ldv_module_get(struct module *module ) 
 { struct module *__cil_tmp2 ;
   unsigned long __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
 
   {
   {
 #line 1660
   __cil_tmp2 = (struct module *)0;
 #line 1660
   __cil_tmp3 = (unsigned long )__cil_tmp2;
 #line 1660
   __cil_tmp4 = (unsigned long )module;
 #line 1660
   if (__cil_tmp4 != __cil_tmp3) {
 #line 1662
     ldv_module_refcounter = ldv_module_refcounter + 1;
   } else {
 
   }
   }
 #line 1663
   return;
 }
 }
 #line 1667 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 int ldv_try_module_get(struct module *module ) 
 { int module_get_succeeded ;
   struct module *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
 
   {
   {
 #line 1672
   __cil_tmp3 = (struct module *)0;
 #line 1672
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1672
   __cil_tmp5 = (unsigned long )module;
 #line 1672
   if (__cil_tmp5 != __cil_tmp4) {
     {
 #line 1675
     module_get_succeeded = ldv_undefined_int();
     }
 #line 1677
     if (module_get_succeeded == 1) {
 #line 1679
       ldv_module_refcounter = ldv_module_refcounter + 1;
 #line 1681
       return (1);
     } else {
 #line 1686
       return (0);
     }
   } else {
 
   }
   }
 #line 1688
   return (0);
 }
 }
 #line 1692 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void ldv_module_put(struct module *module ) 
 { struct module *__cil_tmp2 ;
   unsigned long __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
 
   {
   {
 #line 1695
   __cil_tmp2 = (struct module *)0;
 #line 1695
   __cil_tmp3 = (unsigned long )__cil_tmp2;
 #line 1695
   __cil_tmp4 = (unsigned long )module;
 #line 1695
   if (__cil_tmp4 != __cil_tmp3) {
 #line 1697
     if (ldv_module_refcounter <= 1) {
       {
 #line 1697
       ldv_blast_assert();
       }
     } else {
 
     }
 #line 1699
     ldv_module_refcounter = ldv_module_refcounter - 1;
   } else {
 
   }
   }
 #line 1701
   return;
 }
 }
 #line 1704 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void ldv_module_put_and_exit(void) 
 { struct module *__cil_tmp1 ;
 
   {
   {
 #line 1706
   __cil_tmp1 = (struct module *)1;
 #line 1706
   ldv_module_put(__cil_tmp1);
   }
   LDV_STOP: ;
 #line 1708
   goto LDV_STOP;
 }
 }
 #line 1712 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 unsigned int ldv_module_refcount(void) 
 { int __cil_tmp1 ;
 
   {
   {
 #line 1715
   __cil_tmp1 = ldv_module_refcounter + -1;
 #line 1715
   return ((unsigned int )__cil_tmp1);
   }
 }
 }
 #line 1719 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_drv.c.p"
 void ldv_check_final_state(void) 
 { 
 
   {
 #line 1722
   if (ldv_module_refcounter != 1) {
     {
 #line 1722
     ldv_blast_assert();
     }
   } else {
 
   }
 #line 1725
   return;
 }
 }
 #line 24 "include/linux/list.h"
 __inline static void INIT_LIST_HEAD(struct list_head *list ) 
 { 
 
   {
 #line 26
   list->next = list;
 #line 27
   list->prev = list;
 #line 28
   return;
 }
 }
 #line 101 "include/linux/printk.h"
 extern int printk(char const   *  , ...) ;
 #line 64 "include/asm-generic/bug.h"
 extern void warn_slowpath_fmt(char const   * , int  , char const   *  , ...) ;
 #line 170 "include/linux/kernel.h"
 extern void might_fault(void) ;
 #line 55 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/string_64.h"
 extern void *memset(void * , int  , size_t  ) ;
 #line 15 "include/linux/math64.h"
 __inline static u64 div_u64_rem(u64 dividend , u32 divisor , u32 *remainder ) 
 { u64 __cil_tmp4 ;
   unsigned long long __cil_tmp5 ;
   u64 __cil_tmp6 ;
 
   {
 #line 17
   __cil_tmp4 = (u64 )divisor;
 #line 17
   __cil_tmp5 = dividend % __cil_tmp4;
 #line 17
   *remainder = (u32 )__cil_tmp5;
   {
 #line 18
   __cil_tmp6 = (u64 )divisor;
 #line 18
   return (dividend / __cil_tmp6);
   }
 }
 }
 #line 78 "include/linux/math64.h"
 __inline static u64 div_u64(u64 dividend , u32 divisor ) 
 { u32 remainder ;
   u64 tmp ;
 
   {
   {
 #line 81
   tmp = div_u64_rem(dividend, divisor, & remainder);
   }
 #line 81
   return (tmp);
 }
 }
 #line 93 "include/linux/spinlock.h"
 extern void __raw_spin_lock_init(raw_spinlock_t * , char const   * , struct lock_class_key * ) ;
 #line 22 "include/linux/spinlock_api_smp.h"
 extern void _raw_spin_lock(raw_spinlock_t * ) ;
 #line 39
 extern void _raw_spin_unlock(raw_spinlock_t * ) ;
 #line 272 "include/linux/spinlock.h"
 __inline static raw_spinlock_t *spinlock_check(spinlock_t *lock ) 
 { 
 
   {
 #line 274
   return (& lock->ldv_6060.rlock);
 }
 }
 #line 283 "include/linux/spinlock.h"
 __inline static void spin_lock(spinlock_t *lock ) 
 { struct raw_spinlock *__cil_tmp2 ;
 
   {
   {
 #line 285
   __cil_tmp2 = & lock->ldv_6060.rlock;
 #line 285
   _raw_spin_lock(__cil_tmp2);
   }
 #line 286
   return;
 }
 }
 #line 323 "include/linux/spinlock.h"
 __inline static void spin_unlock(spinlock_t *lock ) 
 { struct raw_spinlock *__cil_tmp2 ;
 
   {
   {
 #line 325
   __cil_tmp2 = & lock->ldv_6060.rlock;
 #line 325
   _raw_spin_unlock(__cil_tmp2);
   }
 #line 326
   return;
 }
 }
 #line 78 "include/linux/time.h"
 extern void set_normalized_timespec(struct timespec * , time_t  , s64  ) ;
 #line 101 "include/linux/time.h"
 __inline static struct timespec timespec_sub(struct timespec lhs , struct timespec rhs ) 
 { struct timespec ts_delta ;
   __kernel_time_t __cil_tmp4 ;
   long __cil_tmp5 ;
   s64 __cil_tmp6 ;
 
   {
   {
 #line 105
   __cil_tmp4 = lhs.tv_sec - rhs.tv_sec;
 #line 105
   __cil_tmp5 = lhs.tv_nsec - rhs.tv_nsec;
 #line 105
   __cil_tmp6 = (s64 )__cil_tmp5;
 #line 105
   set_normalized_timespec(& ts_delta, __cil_tmp4, __cil_tmp6);
   }
 #line 107
   return (ts_delta);
 }
 }
 #line 161
 extern void getrawmonotonic(struct timespec * ) ;
 #line 83 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/e820.h"
 extern unsigned long pci_mem_start ;
 #line 118 "include/linux/ioport.h"
 extern int release_resource(struct resource * ) ;
 #line 296 "include/linux/jiffies.h"
 extern unsigned int jiffies_to_msecs(unsigned long  ) ;
 #line 91 "include/linux/timer.h"
 extern void init_timer_key(struct timer_list * , char const   * , struct lock_class_key * ) ;
 #line 166 "include/linux/timer.h"
 __inline static void setup_timer_key(struct timer_list *timer , char const   *name ,
                                      struct lock_class_key *key , void (*function)(unsigned long  ) ,
                                      unsigned long data ) 
 { 
 
   {
   {
 #line 172
   timer->function = function;
 #line 173
   timer->data = data;
 #line 174
   init_timer_key(timer, name, key);
   }
 #line 175
   return;
 }
 }
 #line 280
 extern int del_timer_sync(struct timer_list * ) ;
 #line 300 "include/linux/workqueue.h"
 extern struct workqueue_struct *__alloc_workqueue_key(char const   * , unsigned int  ,
                                                       int  , struct lock_class_key * ,
                                                       char const   * ) ;
 #line 347
 extern void destroy_workqueue(struct workqueue_struct * ) ;
 #line 357
 extern void flush_workqueue(struct workqueue_struct * ) ;
 #line 372
 extern bool cancel_work_sync(struct work_struct * ) ;
 #line 376
 extern bool cancel_delayed_work_sync(struct delayed_work * ) ;
 #line 55 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static unsigned char readb(void const volatile   *addr ) 
 { unsigned char ret ;
   unsigned char volatile   *__cil_tmp3 ;
 
   {
 #line 55
   __cil_tmp3 = (unsigned char volatile   *)addr;
 #line 55
   __asm__  volatile   ("movb %1,%0": "=q" (ret): "m" (*__cil_tmp3): "memory");
 #line 55
   return (ret);
 }
 }
 #line 56 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static unsigned short readw(void const volatile   *addr ) 
 { unsigned short ret ;
   unsigned short volatile   *__cil_tmp3 ;
 
   {
 #line 56
   __cil_tmp3 = (unsigned short volatile   *)addr;
 #line 56
   __asm__  volatile   ("movw %1,%0": "=r" (ret): "m" (*__cil_tmp3): "memory");
 #line 56
   return (ret);
 }
 }
 #line 189
 extern void iounmap(void volatile   * ) ;
 #line 31 "include/asm-generic/iomap.h"
 extern unsigned int ioread32(void * ) ;
 #line 37
 extern void iowrite32(u32  , void * ) ;
 #line 69
 extern void *pci_iomap(struct pci_dev * , int  , unsigned long  ) ;
 #line 70
 extern void pci_iounmap(struct pci_dev * , void * ) ;
 #line 205 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void memset_io(void volatile   *addr , unsigned char val , size_t count ) 
 { void *__cil_tmp4 ;
   int __cil_tmp5 ;
 
   {
   {
 #line 207
   __cil_tmp4 = (void *)addr;
 #line 207
   __cil_tmp5 = (int )val;
 #line 207
   memset(__cil_tmp4, __cil_tmp5, count);
   }
 #line 208
   return;
 }
 }
 #line 319
 extern void *ioremap_wc(resource_size_t  , unsigned long  ) ;
 #line 830 "include/linux/rcupdate.h"
 extern void kfree(void const   * ) ;
 #line 208 "include/linux/module.h"
 extern void *__symbol_get(char const   * ) ;
 #line 502
 extern void __symbol_put(char const   * ) ;
 #line 221 "include/linux/slub_def.h"
 extern void *__kmalloc(size_t  , gfp_t  ) ;
 #line 255 "include/linux/slub_def.h"
 __inline static void *kmalloc(size_t size , gfp_t flags ) 
 { void *tmp___2 ;
 
   {
   {
 #line 270
   tmp___2 = __kmalloc(size, flags);
   }
 #line 270
   return (tmp___2);
 }
 }
 #line 223 "include/linux/slab.h"
 __inline static void *kcalloc(size_t n , size_t size , gfp_t flags ) 
 { void *tmp ;
   unsigned long __cil_tmp5 ;
   size_t __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
 
   {
 #line 225
   if (size != 0UL) {
     {
 #line 225
     __cil_tmp5 = 1152921504606846975UL / size;
 #line 225
     if (__cil_tmp5 < n) {
 #line 226
       return ((void *)0);
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 227
   __cil_tmp6 = n * size;
 #line 227
   __cil_tmp7 = flags | 32768U;
 #line 227
   tmp = __kmalloc(__cil_tmp6, __cil_tmp7);
   }
 #line 227
   return (tmp);
 }
 }
 #line 318 "include/linux/slab.h"
 __inline static void *kzalloc(size_t size , gfp_t flags ) 
 { void *tmp ;
   unsigned int __cil_tmp4 ;
 
   {
   {
 #line 320
   __cil_tmp4 = flags | 32768U;
 #line 320
   tmp = kmalloc(size, __cil_tmp4);
   }
 #line 320
   return (tmp);
 }
 }
 #line 633 "include/linux/pci.h"
 extern resource_size_t pcibios_align_resource(void * , struct resource  const  * ,
                                               resource_size_t  , resource_size_t  ) ;
 #line 713
 extern struct pci_dev *pci_get_domain_bus_and_slot(int  , unsigned int  , unsigned int  ) ;
 #line 715 "include/linux/pci.h"
 __inline static struct pci_dev *pci_get_bus_and_slot(unsigned int bus , unsigned int devfn ) 
 { struct pci_dev *tmp ;
 
   {
   {
 #line 718
   tmp = pci_get_domain_bus_and_slot(0, bus, devfn);
   }
 #line 718
   return (tmp);
 }
 }
 #line 725
 extern int pci_bus_read_config_word(struct pci_bus * , unsigned int  , int  , u16 * ) ;
 #line 727
 extern int pci_bus_read_config_dword(struct pci_bus * , unsigned int  , int  , u32 * ) ;
 #line 733
 extern int pci_bus_write_config_dword(struct pci_bus * , unsigned int  , int  , u32  ) ;
 #line 741 "include/linux/pci.h"
 __inline static int pci_read_config_word(struct pci_dev *dev , int where , u16 *val ) 
 { int tmp ;
   struct pci_bus *__cil_tmp5 ;
   unsigned int __cil_tmp6 ;
 
   {
   {
 #line 743
   __cil_tmp5 = dev->bus;
 #line 743
   __cil_tmp6 = dev->devfn;
 #line 743
   tmp = pci_bus_read_config_word(__cil_tmp5, __cil_tmp6, where, val);
   }
 #line 743
   return (tmp);
 }
 }
 #line 745 "include/linux/pci.h"
 __inline static int pci_read_config_dword(struct pci_dev *dev , int where , u32 *val ) 
 { int tmp ;
   struct pci_bus *__cil_tmp5 ;
   unsigned int __cil_tmp6 ;
 
   {
   {
 #line 748
   __cil_tmp5 = dev->bus;
 #line 748
   __cil_tmp6 = dev->devfn;
 #line 748
   tmp = pci_bus_read_config_dword(__cil_tmp5, __cil_tmp6, where, val);
   }
 #line 748
   return (tmp);
 }
 }
 #line 758 "include/linux/pci.h"
 __inline static int pci_write_config_dword(struct pci_dev *dev , int where , u32 val ) 
 { int tmp ;
   struct pci_bus *__cil_tmp5 ;
   unsigned int __cil_tmp6 ;
 
   {
   {
 #line 761
   __cil_tmp5 = dev->bus;
 #line 761
   __cil_tmp6 = dev->devfn;
 #line 761
   tmp = pci_bus_write_config_dword(__cil_tmp5, __cil_tmp6, where, val);
   }
 #line 761
   return (tmp);
 }
 }
 #line 904
 extern int pci_bus_alloc_resource(struct pci_bus * , struct resource * , resource_size_t  ,
                                   resource_size_t  , resource_size_t  , unsigned int  ,
                                   resource_size_t (*)(void * , struct resource  const  * ,
                                                       resource_size_t  , resource_size_t  ) ,
                                   void * ) ;
 #line 1012
 extern int pci_enable_msi_block(struct pci_dev * , unsigned int  ) ;
 #line 1014
 extern void pci_disable_msi(struct pci_dev * ) ;
 #line 1162 "include/linux/mm.h"
 extern void unregister_shrinker(struct shrinker * ) ;
 #line 58 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/dma-mapping.h"
 extern int dma_supported(struct device * , u64  ) ;
 #line 108 "include/linux/dma-mapping.h"
 __inline static int dma_set_coherent_mask(struct device *dev , u64 mask ) 
 { int tmp ;
 
   {
   {
 #line 110
   tmp = dma_supported(dev, mask);
   }
 #line 110
   if (tmp == 0) {
 #line 111
     return (-5);
   } else {
 
   }
 #line 112
   dev->coherent_dma_mask = mask;
 #line 113
   return (0);
 }
 }
 #line 40 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 extern unsigned long _copy_to_user(void * , void const   * , unsigned int  ) ;
 #line 42
 extern unsigned long _copy_from_user(void * , void const   * , unsigned int  ) ;
 #line 46 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 __inline static unsigned long copy_from_user(void *to , void const   *from , unsigned long n ) 
 { int sz ;
   unsigned long tmp ;
   int __ret_warn_on ;
   long tmp___0 ;
   long tmp___1 ;
   long tmp___2 ;
   void const   *__cil_tmp10 ;
   void *__cil_tmp11 ;
   int __cil_tmp12 ;
   long __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   int __cil_tmp16 ;
   long __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   long __cil_tmp24 ;
 
   {
   {
 #line 50
   __cil_tmp10 = (void const   *)to;
 #line 50
   __cil_tmp11 = (void *)__cil_tmp10;
 #line 50
   tmp = __builtin_object_size(__cil_tmp11, 0);
 #line 50
   sz = (int )tmp;
 #line 52
   might_fault();
 #line 53
   __cil_tmp12 = sz == -1;
 #line 53
   __cil_tmp13 = (long )__cil_tmp12;
 #line 53
   tmp___1 = __builtin_expect(__cil_tmp13, 1L);
   }
 #line 53
   if (tmp___1 != 0L) {
     {
 #line 54
     __cil_tmp14 = (unsigned int )n;
 #line 54
     n = _copy_from_user(to, from, __cil_tmp14);
     }
   } else {
     {
 #line 53
     __cil_tmp15 = (unsigned long )sz;
 #line 53
     __cil_tmp16 = __cil_tmp15 >= n;
 #line 53
     __cil_tmp17 = (long )__cil_tmp16;
 #line 53
     tmp___2 = __builtin_expect(__cil_tmp17, 1L);
     }
 #line 53
     if (tmp___2 != 0L) {
       {
 #line 54
       __cil_tmp18 = (unsigned int )n;
 #line 54
       n = _copy_from_user(to, from, __cil_tmp18);
       }
     } else {
       {
 #line 57
       __ret_warn_on = 1;
 #line 57
       __cil_tmp19 = __ret_warn_on != 0;
 #line 57
       __cil_tmp20 = (long )__cil_tmp19;
 #line 57
       tmp___0 = __builtin_expect(__cil_tmp20, 0L);
       }
 #line 57
       if (tmp___0 != 0L) {
         {
 #line 57
         __cil_tmp21 = (int const   )57;
 #line 57
         __cil_tmp22 = (int )__cil_tmp21;
 #line 57
         warn_slowpath_fmt("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h",
                           __cil_tmp22, "Buffer overflow detected!\n");
         }
       } else {
 
       }
       {
 #line 57
       __cil_tmp23 = __ret_warn_on != 0;
 #line 57
       __cil_tmp24 = (long )__cil_tmp23;
 #line 57
       __builtin_expect(__cil_tmp24, 0L);
       }
     }
   }
 #line 59
   return (n);
 }
 }
 #line 63 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 __inline static int copy_to_user(void *dst , void const   *src , unsigned int size ) 
 { unsigned long tmp ;
 
   {
   {
 #line 65
   might_fault();
 #line 67
   tmp = _copy_to_user(dst, src, size);
   }
 #line 67
   return ((int )tmp);
 }
 }
 #line 115 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/mtrr.h"
 extern int mtrr_add(unsigned long  , unsigned long  , unsigned int  , bool  ) ;
 #line 119
 extern int mtrr_del(int  , unsigned long  , unsigned long  ) ;
 #line 100 "include/drm/drm_mm.h"
 extern struct drm_mm_node *drm_mm_get_block_generic(struct drm_mm_node * , unsigned long  ,
                                                     unsigned int  , int  ) ;
 #line 111 "include/drm/drm_mm.h"
 __inline static struct drm_mm_node *drm_mm_get_block(struct drm_mm_node *parent ,
                                                      unsigned long size , unsigned int alignment ) 
 { struct drm_mm_node *tmp ;
 
   {
   {
 #line 115
   tmp = drm_mm_get_block_generic(parent, size, alignment, 0);
   }
 #line 115
   return (tmp);
 }
 }
 #line 149
 extern void drm_mm_put_block(struct drm_mm_node * ) ;
 #line 152
 extern struct drm_mm_node *drm_mm_search_free(struct drm_mm  const  * , unsigned long  ,
                                               unsigned int  , int  ) ;
 #line 163
 extern int drm_mm_init(struct drm_mm * , unsigned long  , unsigned long  ) ;
 #line 165
 extern void drm_mm_takedown(struct drm_mm * ) ;
 #line 1387 "include/drm/drmP.h"
 extern int drm_vblank_init(struct drm_device * , int  ) ;
 #line 1472
 extern struct drm_local_map *drm_getsarea(struct drm_device * ) ;
 #line 1517
 extern drm_dma_handle_t *drm_pci_alloc(struct drm_device * , size_t  , size_t  ) ;
 #line 1520
 extern void drm_pci_free(struct drm_device * , drm_dma_handle_t * ) ;
 #line 1636
 extern void drm_core_ioremap_wc(struct drm_local_map * , struct drm_device * ) ;
 #line 1637
 extern void drm_core_ioremapfree(struct drm_local_map * , struct drm_device * ) ;
 #line 141 "include/drm/drm_crtc_helper.h"
 extern void drm_kms_helper_poll_init(struct drm_device * ) ;
 #line 470 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_bios.h"
 void intel_setup_bios(struct drm_device *dev ) ;
 #line 471
 bool intel_parse_bios(struct drm_device *dev ) ;
 #line 137 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
 __inline static u32 intel_read_status_page(struct intel_ring_buffer *ring , int reg ) 
 { unsigned int tmp ;
   unsigned long __cil_tmp4 ;
   u32 *__cil_tmp5 ;
   void *__cil_tmp6 ;
   void *__cil_tmp7 ;
 
   {
   {
 #line 140
   __cil_tmp4 = (unsigned long )reg;
 #line 140
   __cil_tmp5 = ring->status_page.page_addr;
 #line 140
   __cil_tmp6 = (void *)__cil_tmp5;
 #line 140
   __cil_tmp7 = __cil_tmp6 + __cil_tmp4;
 #line 140
   tmp = ioread32(__cil_tmp7);
   }
 #line 140
   return (tmp);
 }
 }
 #line 163
 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring ) ;
 #line 165
 int intel_wait_ring_buffer(struct intel_ring_buffer *ring , int n ) ;
 #line 166 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
 __inline static int intel_wait_ring_idle(struct intel_ring_buffer *ring ) 
 { int tmp ;
   int __cil_tmp3 ;
   int __cil_tmp4 ;
 
   {
   {
 #line 168
   __cil_tmp3 = ring->size;
 #line 168
   __cil_tmp4 = __cil_tmp3 + -8;
 #line 168
   tmp = intel_wait_ring_buffer(ring, __cil_tmp4);
   }
 #line 168
   return (tmp);
 }
 }
 #line 171
 int intel_ring_begin(struct intel_ring_buffer *ring , int num_dwords ) ;
 #line 173 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
 __inline static void intel_ring_emit(struct intel_ring_buffer *ring , u32 data ) 
 { u32 __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   void *__cil_tmp5 ;
   void *__cil_tmp6 ;
   u32 __cil_tmp7 ;
 
   {
   {
 #line 176
   __cil_tmp3 = ring->tail;
 #line 176
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 176
   __cil_tmp5 = ring->virtual_start;
 #line 176
   __cil_tmp6 = __cil_tmp5 + __cil_tmp4;
 #line 176
   iowrite32(data, __cil_tmp6);
 #line 177
   __cil_tmp7 = ring->tail;
 #line 177
   ring->tail = __cil_tmp7 + 4U;
   }
 #line 178
   return;
 }
 }
 #line 180
 void intel_ring_advance(struct intel_ring_buffer *ring ) ;
 #line 192
 void intel_ring_setup_status_page(struct intel_ring_buffer *ring ) ;
 #line 201
 int intel_render_ring_init_dri(struct drm_device *dev , u64 start , u32 size ) ;
 #line 125 "include/linux/io-mapping.h"
 __inline static struct io_mapping *io_mapping_create_wc(resource_size_t base , unsigned long size ) 
 { void *tmp ;
 
   {
   {
 #line 127
   tmp = ioremap_wc(base, size);
   }
 #line 127
   return ((struct io_mapping *)tmp);
 }
 }
 #line 131 "include/linux/io-mapping.h"
 __inline static void io_mapping_free(struct io_mapping *mapping ) 
 { void volatile   *__cil_tmp2 ;
 
   {
   {
 #line 133
   __cil_tmp2 = (void volatile   *)mapping;
 #line 133
   iounmap(__cil_tmp2);
   }
 #line 134
   return;
 }
 }
 #line 16 "include/drm/intel-gtt.h"
 extern struct intel_gtt  const  *intel_gtt_get(void) ;
 #line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_reg_rw___0(bool write , u32 reg , u64 val , int len ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp13 ;
   struct tracepoint_func **__cil_tmp14 ;
   struct tracepoint_func * volatile  *__cil_tmp15 ;
   struct tracepoint_func * volatile  __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct tracepoint_func *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   void *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   void *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
 
   {
   {
 #line 387
   __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
 #line 387
   tmp___1 = static_branch(__cil_tmp13);
   }
 #line 387
   if ((int )tmp___1) {
     {
 #line 387
     rcu_read_lock_sched_notrace();
 #line 387
     __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
 #line 387
     __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
 #line 387
     __cil_tmp16 = *__cil_tmp15;
 #line 387
     _________p1 = (struct tracepoint_func *)__cil_tmp16;
 #line 387
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 387
     if (tmp != 0) {
 #line 387
       if (! __warned) {
         {
 #line 387
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 387
         if (tmp___0 == 0) {
           {
 #line 387
           __warned = (bool )1;
 #line 387
           __cil_tmp17 = (int const   )411;
 #line 387
           __cil_tmp18 = (int )__cil_tmp17;
 #line 387
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp18);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 387
     it_func_ptr = _________p1;
     {
 #line 387
     __cil_tmp19 = (struct tracepoint_func *)0;
 #line 387
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 387
     __cil_tmp21 = (unsigned long )it_func_ptr;
 #line 387
     if (__cil_tmp21 != __cil_tmp20) {
       ldv_36474: 
       {
 #line 387
       it_func = it_func_ptr->func;
 #line 387
       __data = it_func_ptr->data;
 #line 387
       __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
 #line 387
       __cil_tmp23 = (int )write;
 #line 387
       __cil_tmp24 = (bool )__cil_tmp23;
 #line 387
       (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
 #line 387
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 387
       __cil_tmp25 = (void *)0;
 #line 387
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 387
       __cil_tmp27 = it_func_ptr->func;
 #line 387
       __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 387
       if (__cil_tmp28 != __cil_tmp26) {
 #line 388
         goto ldv_36474;
       } else {
 #line 390
         goto ldv_36475;
       }
       }
       ldv_36475: ;
     } else {
 
     }
     }
     {
 #line 387
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 389
   return;
 }
 }
 #line 1005 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 void i915_kernel_lost_context(struct drm_device *dev ) ;
 #line 1017
 int i915_emit_box(struct drm_device *dev , struct drm_clip_rect *box , int DR1 , int DR4 ) ;
 #line 1021
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv ) ;
 #line 1022
 unsigned long i915_mch_val(struct drm_i915_private *dev_priv ) ;
 #line 1023
 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv ) ;
 #line 1024
 void i915_update_gfx_val(struct drm_i915_private *dev_priv ) ;
 #line 1028
 void i915_hangcheck_elapsed(unsigned long data ) ;
 #line 1030
 int i915_irq_emit(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1032
 int i915_irq_wait(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1035
 void intel_irq_init(struct drm_device *dev ) ;
 #line 1037
 int i915_vblank_pipe_set(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1039
 int i915_vblank_pipe_get(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1041
 int i915_vblank_swap(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1053
 void i915_destroy_error_state(struct drm_device *dev ) ;
 #line 1060
 int i915_mem_alloc(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1062
 int i915_mem_free(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1064
 int i915_mem_init_heap(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1066
 int i915_mem_destroy_heap(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1068
 void i915_mem_takedown(struct mem_block **heap ) ;
 #line 1069
 void i915_mem_release(struct drm_device *dev , struct drm_file *file_priv , struct mem_block *heap ) ;
 #line 1072
 int i915_gem_init_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1074
 int i915_gem_create_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1076
 int i915_gem_pread_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1078
 int i915_gem_pwrite_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1080
 int i915_gem_mmap_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1082
 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1084
 int i915_gem_set_domain_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1086
 int i915_gem_sw_finish_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1088
 int i915_gem_execbuffer(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1090
 int i915_gem_execbuffer2(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1092
 int i915_gem_pin_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1094
 int i915_gem_unpin_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1096
 int i915_gem_busy_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1098
 int i915_gem_throttle_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1100
 int i915_gem_madvise_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1102
 int i915_gem_entervt_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1104
 int i915_gem_leavevt_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 1106
 int i915_gem_set_tiling(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1108
 int i915_gem_get_tiling(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1110
 int i915_gem_get_aperture_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 1112
 void i915_gem_load(struct drm_device *dev ) ;
 #line 1126
 void i915_gem_lastclose(struct drm_device *dev ) ;
 #line 1169
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev ) ;
 #line 1170
 void i915_gem_do_init(struct drm_device *dev , unsigned long start , unsigned long mappable_end ,
                       unsigned long end ) ;
 #line 1174
 int i915_gpu_idle(struct drm_device *dev ) ;
 #line 1194
 void i915_gem_free_all_phys_object(struct drm_device *dev ) ;
 #line 1195
 void i915_gem_release(struct drm_device *dev , struct drm_file *file ) ;
 #line 1246
 int intel_setup_gmbus(struct drm_device *dev ) ;
 #line 1247
 void intel_teardown_gmbus(struct drm_device *dev ) ;
 #line 1274
 void intel_register_dsm_handler(void) ;
 #line 1282
 void intel_modeset_init(struct drm_device *dev ) ;
 #line 1283
 void intel_modeset_gem_init(struct drm_device *dev ) ;
 #line 1284
 void intel_modeset_cleanup(struct drm_device *dev ) ;
 #line 1285
 int intel_modeset_vga_set_state(struct drm_device *dev , bool state ) ;
 #line 1289
 void intel_disable_fbc(struct drm_device *dev ) ;
 #line 1292
 bool ironlake_set_drps(struct drm_device *dev , u8 val ) ;
 #line 1359 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u8 i915_read8(struct drm_i915_private *dev_priv , u32 reg ) 
 { u8 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1359
   val = (u8 )0U;
   {
 #line 1359
   __cil_tmp4 = dev_priv->info;
 #line 1359
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1359
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1359
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1359
   if (__cil_tmp7 > 5U) {
 #line 1359
     if (reg <= 262143U) {
 #line 1359
       if (reg != 41356U) {
         {
 #line 1359
         gen6_gt_force_wake_get(dev_priv);
 #line 1359
         __cil_tmp8 = (unsigned long )reg;
 #line 1359
         __cil_tmp9 = dev_priv->regs;
 #line 1359
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1359
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1359
         val = readb(__cil_tmp11);
 #line 1359
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1359
         __cil_tmp12 = (unsigned long )reg;
 #line 1359
         __cil_tmp13 = dev_priv->regs;
 #line 1359
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1359
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1359
         val = readb(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1359
       __cil_tmp16 = (unsigned long )reg;
 #line 1359
       __cil_tmp17 = dev_priv->regs;
 #line 1359
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1359
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1359
       val = readb(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1359
     __cil_tmp20 = (unsigned long )reg;
 #line 1359
     __cil_tmp21 = dev_priv->regs;
 #line 1359
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1359
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1359
     val = readb(__cil_tmp23);
     }
   }
   }
   {
 #line 1359
   __cil_tmp24 = (bool )0;
 #line 1359
   __cil_tmp25 = (u64 )val;
 #line 1359
   trace_i915_reg_rw___0(__cil_tmp24, reg, __cil_tmp25, 1);
   }
 #line 1359
   return (val);
 }
 }
 #line 1360 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u16 i915_read16(struct drm_i915_private *dev_priv , u32 reg ) 
 { u16 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1360
   val = (u16 )0U;
   {
 #line 1360
   __cil_tmp4 = dev_priv->info;
 #line 1360
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1360
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1360
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1360
   if (__cil_tmp7 > 5U) {
 #line 1360
     if (reg <= 262143U) {
 #line 1360
       if (reg != 41356U) {
         {
 #line 1360
         gen6_gt_force_wake_get(dev_priv);
 #line 1360
         __cil_tmp8 = (unsigned long )reg;
 #line 1360
         __cil_tmp9 = dev_priv->regs;
 #line 1360
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1360
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1360
         val = readw(__cil_tmp11);
 #line 1360
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1360
         __cil_tmp12 = (unsigned long )reg;
 #line 1360
         __cil_tmp13 = dev_priv->regs;
 #line 1360
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1360
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1360
         val = readw(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1360
       __cil_tmp16 = (unsigned long )reg;
 #line 1360
       __cil_tmp17 = dev_priv->regs;
 #line 1360
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1360
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1360
       val = readw(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1360
     __cil_tmp20 = (unsigned long )reg;
 #line 1360
     __cil_tmp21 = dev_priv->regs;
 #line 1360
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1360
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1360
     val = readw(__cil_tmp23);
     }
   }
   }
   {
 #line 1360
   __cil_tmp24 = (bool )0;
 #line 1360
   __cil_tmp25 = (u64 )val;
 #line 1360
   trace_i915_reg_rw___0(__cil_tmp24, reg, __cil_tmp25, 2);
   }
 #line 1360
   return (val);
 }
 }
 #line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u32 i915_read32___0(struct drm_i915_private *dev_priv , u32 reg ) 
 { u32 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1361
   val = 0U;
   {
 #line 1361
   __cil_tmp4 = dev_priv->info;
 #line 1361
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1361
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1361
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1361
   if (__cil_tmp7 > 5U) {
 #line 1361
     if (reg <= 262143U) {
 #line 1361
       if (reg != 41356U) {
         {
 #line 1361
         gen6_gt_force_wake_get(dev_priv);
 #line 1361
         __cil_tmp8 = (unsigned long )reg;
 #line 1361
         __cil_tmp9 = dev_priv->regs;
 #line 1361
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1361
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1361
         val = readl(__cil_tmp11);
 #line 1361
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1361
         __cil_tmp12 = (unsigned long )reg;
 #line 1361
         __cil_tmp13 = dev_priv->regs;
 #line 1361
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1361
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1361
         val = readl(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1361
       __cil_tmp16 = (unsigned long )reg;
 #line 1361
       __cil_tmp17 = dev_priv->regs;
 #line 1361
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1361
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1361
       val = readl(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1361
     __cil_tmp20 = (unsigned long )reg;
 #line 1361
     __cil_tmp21 = dev_priv->regs;
 #line 1361
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1361
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1361
     val = readl(__cil_tmp23);
     }
   }
   }
   {
 #line 1361
   __cil_tmp24 = (bool )0;
 #line 1361
   __cil_tmp25 = (u64 )val;
 #line 1361
   trace_i915_reg_rw___0(__cil_tmp24, reg, __cil_tmp25, 4);
   }
 #line 1361
   return (val);
 }
 }
 #line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static void i915_write32___0(struct drm_i915_private *dev_priv , u32 reg ,
                                       u32 val ) 
 { bool __cil_tmp4 ;
   u64 __cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   void *__cil_tmp11 ;
   void volatile   *__cil_tmp12 ;
   void volatile   *__cil_tmp13 ;
 
   {
   {
 #line 1375
   __cil_tmp4 = (bool )1;
 #line 1375
   __cil_tmp5 = (u64 )val;
 #line 1375
   trace_i915_reg_rw___0(__cil_tmp4, reg, __cil_tmp5, 4);
   }
   {
 #line 1375
   __cil_tmp6 = dev_priv->info;
 #line 1375
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1375
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1375
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1375
   if (__cil_tmp9 > 5U) {
 #line 1375
     if (reg <= 262143U) {
 #line 1375
       if (reg != 41356U) {
         {
 #line 1375
         __gen6_gt_wait_for_fifo(dev_priv);
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1375
   __cil_tmp10 = (unsigned long )reg;
 #line 1375
   __cil_tmp11 = dev_priv->regs;
 #line 1375
   __cil_tmp12 = (void volatile   *)__cil_tmp11;
 #line 1375
   __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
 #line 1375
   writel(val, __cil_tmp13);
   }
 #line 1376
   return;
 }
 }
 #line 290 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 int intel_get_pipe_from_crtc_id(struct drm_device *dev , void *data , struct drm_file *file ) ;
 #line 331
 int intel_fbdev_init(struct drm_device *dev ) ;
 #line 332
 void intel_fbdev_fini(struct drm_device *dev ) ;
 #line 339
 void intel_cleanup_overlay(struct drm_device *dev ) ;
 #line 341
 int intel_overlay_put_image(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 343
 int intel_overlay_attrs(struct drm_device *dev , void *data , struct drm_file *file_priv ) ;
 #line 347
 void intel_fb_restore_mode(struct drm_device *dev ) ;
 #line 38 "include/drm/i915_drm.h"
 unsigned long i915_read_mch_val(void) ;
 #line 39
 bool i915_gpu_raise(void) ;
 #line 40
 bool i915_gpu_lower(void) ;
 #line 41
 bool i915_gpu_busy(void) ;
 #line 42
 bool i915_gpu_turbo_disable(void) ;
 #line 230 "include/linux/vgaarb.h"
 extern int vga_client_register(struct pci_dev * , void * , void (*)(void * , bool  ) ,
                                unsigned int (*)(void * , bool  ) ) ;
 #line 464 "include/linux/pnp.h"
 extern int pnp_range_reserved(resource_size_t  , resource_size_t  ) ;
 #line 33 "include/linux/vga_switcheroo.h"
 extern void vga_switcheroo_unregister_client(struct pci_dev * ) ;
 #line 34
 extern int vga_switcheroo_register_client(struct pci_dev * , void (*)(struct pci_dev * ,
                                                                       enum vga_switcheroo_state  ) ,
                                           void (*)(struct pci_dev * ) , bool (*)(struct pci_dev * ) ) ;
 #line 45
 extern int vga_switcheroo_process_delayed_switch(void) ;
 #line 18 "include/acpi/video.h"
 extern int acpi_video_register(void) ;
 #line 19
 extern void acpi_video_unregister(void) ;
 #line 53 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_write_hws_pga(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 addr ;
   void *__cil_tmp4 ;
   drm_dma_handle_t *__cil_tmp5 ;
   dma_addr_t __cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   u8 __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   drm_dma_handle_t *__cil_tmp13 ;
   dma_addr_t __cil_tmp14 ;
   dma_addr_t __cil_tmp15 ;
   u32 __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
 
   {
 #line 55
   __cil_tmp4 = dev->dev_private;
 #line 55
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 58
   __cil_tmp5 = dev_priv->status_page_dmah;
 #line 58
   __cil_tmp6 = __cil_tmp5->busaddr;
 #line 58
   addr = (u32 )__cil_tmp6;
   {
 #line 59
   __cil_tmp7 = dev->dev_private;
 #line 59
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 59
   __cil_tmp9 = __cil_tmp8->info;
 #line 59
   __cil_tmp10 = __cil_tmp9->gen;
 #line 59
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 59
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 59
   if (__cil_tmp12 > 3U) {
 #line 60
     __cil_tmp13 = dev_priv->status_page_dmah;
 #line 60
     __cil_tmp14 = __cil_tmp13->busaddr;
 #line 60
     __cil_tmp15 = __cil_tmp14 >> 28;
 #line 60
     __cil_tmp16 = (u32 )__cil_tmp15;
 #line 60
     __cil_tmp17 = __cil_tmp16 & 240U;
 #line 60
     addr = __cil_tmp17 | addr;
   } else {
 
   }
   }
   {
 #line 61
   i915_write32___0(dev_priv, 8320U, addr);
   }
 #line 62
   return;
 }
 }
 #line 68 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_init_phys_hws(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct intel_ring_buffer *ring ;
   void *__cil_tmp4 ;
   struct intel_ring_buffer (*__cil_tmp5)[3U] ;
   drm_dma_handle_t *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   drm_dma_handle_t *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   drm_dma_handle_t *__cil_tmp10 ;
   void *__cil_tmp11 ;
   u32 *__cil_tmp12 ;
   void volatile   *__cil_tmp13 ;
 
   {
   {
 #line 70
   __cil_tmp4 = dev->dev_private;
 #line 70
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 71
   __cil_tmp5 = & dev_priv->ring;
 #line 71
   ring = (struct intel_ring_buffer *)__cil_tmp5;
 #line 74
   dev_priv->status_page_dmah = drm_pci_alloc(dev, 4096UL, 4096UL);
   }
   {
 #line 77
   __cil_tmp6 = (drm_dma_handle_t *)0;
 #line 77
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 77
   __cil_tmp8 = dev_priv->status_page_dmah;
 #line 77
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 77
   if (__cil_tmp9 == __cil_tmp7) {
     {
 #line 78
     drm_err("i915_init_phys_hws", "Can not allocate hardware status page\n");
     }
 #line 79
     return (-12);
   } else {
 
   }
   }
   {
 #line 81
   __cil_tmp10 = dev_priv->status_page_dmah;
 #line 81
   __cil_tmp11 = __cil_tmp10->vaddr;
 #line 81
   ring->status_page.page_addr = (u32 *)__cil_tmp11;
 #line 84
   __cil_tmp12 = ring->status_page.page_addr;
 #line 84
   __cil_tmp13 = (void volatile   *)__cil_tmp12;
 #line 84
   memset_io(__cil_tmp13, (unsigned char)0, 4096UL);
 #line 86
   i915_write_hws_pga(dev);
 #line 88
   drm_ut_debug_printk(2U, "drm", "i915_init_phys_hws", "Enabled hardware status page\n");
   }
 #line 89
   return (0);
 }
 }
 #line 96 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_free_hws(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct intel_ring_buffer *ring ;
   void *__cil_tmp4 ;
   struct intel_ring_buffer (*__cil_tmp5)[3U] ;
   drm_dma_handle_t *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   drm_dma_handle_t *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   drm_dma_handle_t *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   drm_local_map_t *__cil_tmp12 ;
 
   {
 #line 98
   __cil_tmp4 = dev->dev_private;
 #line 98
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 99
   __cil_tmp5 = & dev_priv->ring;
 #line 99
   ring = (struct intel_ring_buffer *)__cil_tmp5;
   {
 #line 101
   __cil_tmp6 = (drm_dma_handle_t *)0;
 #line 101
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 101
   __cil_tmp8 = dev_priv->status_page_dmah;
 #line 101
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 101
   if (__cil_tmp9 != __cil_tmp7) {
     {
 #line 102
     __cil_tmp10 = dev_priv->status_page_dmah;
 #line 102
     drm_pci_free(dev, __cil_tmp10);
 #line 103
     dev_priv->status_page_dmah = (drm_dma_handle_t *)0;
     }
   } else {
 
   }
   }
   {
 #line 106
   __cil_tmp11 = ring->status_page.gfx_addr;
 #line 106
   if (__cil_tmp11 != 0U) {
     {
 #line 107
     ring->status_page.gfx_addr = 0U;
 #line 108
     __cil_tmp12 = & dev_priv->hws_map;
 #line 108
     drm_core_ioremapfree(__cil_tmp12, dev);
     }
   } else {
 
   }
   }
   {
 #line 112
   i915_write32___0(dev_priv, 8320U, 536866816U);
   }
 #line 113
   return;
 }
 }
 #line 115 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 void i915_kernel_lost_context(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   struct intel_ring_buffer *ring ;
   int tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp8 ;
   struct intel_ring_buffer (*__cil_tmp9)[3U] ;
   u32 __cil_tmp10 ;
   u32 __cil_tmp11 ;
   u32 __cil_tmp12 ;
   u32 __cil_tmp13 ;
   u32 __cil_tmp14 ;
   u32 __cil_tmp15 ;
   u32 __cil_tmp16 ;
   u32 __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   struct drm_master *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   struct drm_minor *__cil_tmp23 ;
   struct drm_master *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_minor *__cil_tmp26 ;
   struct drm_master *__cil_tmp27 ;
   void *__cil_tmp28 ;
   u32 __cil_tmp29 ;
   u32 __cil_tmp30 ;
   struct _drm_i915_sarea *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   struct _drm_i915_sarea *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   struct _drm_i915_sarea *__cil_tmp35 ;
   struct _drm_i915_sarea *__cil_tmp36 ;
   int __cil_tmp37 ;
 
   {
   {
 #line 117
   __cil_tmp8 = dev->dev_private;
 #line 117
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 119
   __cil_tmp9 = & dev_priv->ring;
 #line 119
   ring = (struct intel_ring_buffer *)__cil_tmp9;
 #line 125
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 125
   if (tmp != 0) {
 #line 126
     return;
   } else {
 
   }
   {
 #line 128
   __cil_tmp10 = ring->mmio_base;
 #line 128
   __cil_tmp11 = __cil_tmp10 + 52U;
 #line 128
   tmp___0 = i915_read32___0(dev_priv, __cil_tmp11);
 #line 128
   ring->head = tmp___0 & 2097148U;
 #line 129
   __cil_tmp12 = ring->mmio_base;
 #line 129
   __cil_tmp13 = __cil_tmp12 + 48U;
 #line 129
   tmp___1 = i915_read32___0(dev_priv, __cil_tmp13);
 #line 129
   ring->tail = tmp___1 & 2097144U;
 #line 130
   __cil_tmp14 = ring->tail;
 #line 130
   __cil_tmp15 = ring->head;
 #line 130
   __cil_tmp16 = __cil_tmp15 - __cil_tmp14;
 #line 130
   __cil_tmp17 = __cil_tmp16 - 8U;
 #line 130
   ring->space = (int )__cil_tmp17;
   }
   {
 #line 131
   __cil_tmp18 = ring->space;
 #line 131
   if (__cil_tmp18 < 0) {
 #line 132
     __cil_tmp19 = ring->size;
 #line 132
     __cil_tmp20 = ring->space;
 #line 132
     ring->space = __cil_tmp20 + __cil_tmp19;
   } else {
 
   }
   }
   {
 #line 134
   __cil_tmp21 = (struct drm_master *)0;
 #line 134
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 134
   __cil_tmp23 = dev->primary;
 #line 134
   __cil_tmp24 = __cil_tmp23->master;
 #line 134
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 134
   if (__cil_tmp25 == __cil_tmp22) {
 #line 135
     return;
   } else {
 
   }
   }
 #line 137
   __cil_tmp26 = dev->primary;
 #line 137
   __cil_tmp27 = __cil_tmp26->master;
 #line 137
   __cil_tmp28 = __cil_tmp27->driver_priv;
 #line 137
   master_priv = (struct drm_i915_master_private *)__cil_tmp28;
   {
 #line 138
   __cil_tmp29 = ring->tail;
 #line 138
   __cil_tmp30 = ring->head;
 #line 138
   if (__cil_tmp30 == __cil_tmp29) {
     {
 #line 138
     __cil_tmp31 = (struct _drm_i915_sarea *)0;
 #line 138
     __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 138
     __cil_tmp33 = master_priv->sarea_priv;
 #line 138
     __cil_tmp34 = (unsigned long )__cil_tmp33;
 #line 138
     if (__cil_tmp34 != __cil_tmp32) {
 #line 139
       __cil_tmp35 = master_priv->sarea_priv;
 #line 139
       __cil_tmp36 = master_priv->sarea_priv;
 #line 139
       __cil_tmp37 = __cil_tmp36->perf_boxes;
 #line 139
       __cil_tmp35->perf_boxes = __cil_tmp37 | 1;
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 140
   return;
 }
 }
 #line 142 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_dma_cleanup(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int i ;
   void *__cil_tmp4 ;
   int __cil_tmp5 ;
   struct mutex *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct intel_ring_buffer (*__cil_tmp8)[3U] ;
   struct intel_ring_buffer *__cil_tmp9 ;
   struct intel_ring_buffer *__cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
 
   {
 #line 144
   __cil_tmp4 = dev->dev_private;
 #line 144
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
   {
 #line 151
   __cil_tmp5 = dev->irq_enabled;
 #line 151
   if (__cil_tmp5 != 0) {
     {
 #line 152
     drm_irq_uninstall(dev);
     }
   } else {
 
   }
   }
   {
 #line 154
   __cil_tmp6 = & dev->struct_mutex;
 #line 154
   mutex_lock_nested(__cil_tmp6, 0U);
 #line 155
   i = 0;
   }
 #line 155
   goto ldv_40292;
   ldv_40291: 
   {
 #line 156
   __cil_tmp7 = (unsigned long )i;
 #line 156
   __cil_tmp8 = & dev_priv->ring;
 #line 156
   __cil_tmp9 = (struct intel_ring_buffer *)__cil_tmp8;
 #line 156
   __cil_tmp10 = __cil_tmp9 + __cil_tmp7;
 #line 156
   intel_cleanup_ring_buffer(__cil_tmp10);
 #line 155
   i = i + 1;
   }
   ldv_40292: ;
 #line 155
   if (i <= 2) {
 #line 156
     goto ldv_40291;
   } else {
 #line 158
     goto ldv_40293;
   }
   ldv_40293: 
   {
 #line 157
   __cil_tmp11 = & dev->struct_mutex;
 #line 157
   mutex_unlock(__cil_tmp11);
   }
   {
 #line 160
   __cil_tmp12 = dev->dev_private;
 #line 160
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 160
   __cil_tmp14 = __cil_tmp13->info;
 #line 160
   __cil_tmp15 = (unsigned char *)__cil_tmp14;
 #line 160
   __cil_tmp16 = __cil_tmp15 + 1UL;
 #line 160
   __cil_tmp17 = *__cil_tmp16;
 #line 160
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 160
   if (__cil_tmp18 != 0U) {
     {
 #line 161
     i915_free_hws(dev);
     }
   } else {
 
   }
   }
 #line 163
   return (0);
 }
 }
 #line 166 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_initialize(struct drm_device *dev , drm_i915_init_t *init ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   int ret ;
   struct drm_local_map *tmp ;
   void *__cil_tmp7 ;
   struct drm_minor *__cil_tmp8 ;
   struct drm_master *__cil_tmp9 ;
   void *__cil_tmp10 ;
   drm_local_map_t *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   drm_local_map_t *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   drm_local_map_t *__cil_tmp17 ;
   void *__cil_tmp18 ;
   struct _drm_i915_sarea *__cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   struct drm_i915_gem_object *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   struct intel_ring_buffer (*__cil_tmp23)[3U] ;
   struct intel_ring_buffer *__cil_tmp24 ;
   struct drm_i915_gem_object *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   u64 __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   struct _drm_i915_sarea *__cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   struct _drm_i915_sarea *__cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   struct _drm_i915_sarea *__cil_tmp36 ;
 
   {
   {
 #line 168
   __cil_tmp7 = dev->dev_private;
 #line 168
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 169
   __cil_tmp8 = dev->primary;
 #line 169
   __cil_tmp9 = __cil_tmp8->master;
 #line 169
   __cil_tmp10 = __cil_tmp9->driver_priv;
 #line 169
   master_priv = (struct drm_i915_master_private *)__cil_tmp10;
 #line 172
   tmp = drm_getsarea(dev);
 #line 172
   master_priv->sarea = tmp;
   }
   {
 #line 173
   __cil_tmp11 = (drm_local_map_t *)0;
 #line 173
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 173
   __cil_tmp13 = master_priv->sarea;
 #line 173
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 173
   if (__cil_tmp14 != __cil_tmp12) {
 #line 174
     __cil_tmp15 = init->sarea_priv_offset;
 #line 174
     __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 174
     __cil_tmp17 = master_priv->sarea;
 #line 174
     __cil_tmp18 = __cil_tmp17->handle;
 #line 174
     __cil_tmp19 = (struct _drm_i915_sarea *)__cil_tmp18;
 #line 174
     master_priv->sarea_priv = __cil_tmp19 + __cil_tmp16;
   } else {
     {
 #line 177
     drm_ut_debug_printk(2U, "drm", "i915_initialize", "sarea not found assuming DRI2 userspace\n");
     }
   }
   }
   {
 #line 180
   __cil_tmp20 = init->ring_size;
 #line 180
   if (__cil_tmp20 != 0U) {
     {
 #line 181
     __cil_tmp21 = (struct drm_i915_gem_object *)0;
 #line 181
     __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 181
     __cil_tmp23 = & dev_priv->ring;
 #line 181
     __cil_tmp24 = (struct intel_ring_buffer *)__cil_tmp23;
 #line 181
     __cil_tmp25 = __cil_tmp24->obj;
 #line 181
     __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 181
     if (__cil_tmp26 != __cil_tmp22) {
       {
 #line 182
       i915_dma_cleanup(dev);
 #line 183
       drm_err("i915_initialize", "Client tried to initialize ringbuffer in GEM mode\n");
       }
 #line 185
       return (-22);
     } else {
 
     }
     }
     {
 #line 188
     __cil_tmp27 = init->ring_start;
 #line 188
     __cil_tmp28 = (u64 )__cil_tmp27;
 #line 188
     __cil_tmp29 = init->ring_size;
 #line 188
     ret = intel_render_ring_init_dri(dev, __cil_tmp28, __cil_tmp29);
     }
 #line 191
     if (ret != 0) {
       {
 #line 192
       i915_dma_cleanup(dev);
       }
 #line 193
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
 #line 197
   dev_priv->cpp = init->cpp;
 #line 198
   __cil_tmp30 = init->back_offset;
 #line 198
   dev_priv->back_offset = (int )__cil_tmp30;
 #line 199
   __cil_tmp31 = init->front_offset;
 #line 199
   dev_priv->front_offset = (int )__cil_tmp31;
 #line 200
   dev_priv->current_page = 0;
   {
 #line 201
   __cil_tmp32 = (struct _drm_i915_sarea *)0;
 #line 201
   __cil_tmp33 = (unsigned long )__cil_tmp32;
 #line 201
   __cil_tmp34 = master_priv->sarea_priv;
 #line 201
   __cil_tmp35 = (unsigned long )__cil_tmp34;
 #line 201
   if (__cil_tmp35 != __cil_tmp33) {
 #line 202
     __cil_tmp36 = master_priv->sarea_priv;
 #line 202
     __cil_tmp36->pf_current_page = 0;
   } else {
 
   }
   }
 #line 206
   dev_priv->allow_batchbuffer = 1;
 #line 208
   return (0);
 }
 }
 #line 211 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_dma_resume(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct intel_ring_buffer *ring ;
   void *__cil_tmp4 ;
   struct intel_ring_buffer (*__cil_tmp5)[3U] ;
   void *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   void *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   u32 *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   u32 *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   u32 *__cil_tmp14 ;
   unsigned int __cil_tmp15 ;
 
   {
   {
 #line 213
   __cil_tmp4 = dev->dev_private;
 #line 213
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 214
   __cil_tmp5 = & dev_priv->ring;
 #line 214
   ring = (struct intel_ring_buffer *)__cil_tmp5;
 #line 216
   drm_ut_debug_printk(2U, "drm", "i915_dma_resume", "%s\n", "i915_dma_resume");
   }
   {
 #line 218
   __cil_tmp6 = (void *)0;
 #line 218
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 218
   __cil_tmp8 = ring->map.handle;
 #line 218
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 218
   if (__cil_tmp9 == __cil_tmp7) {
     {
 #line 219
     drm_err("i915_dma_resume", "can not ioremap virtual address for ring buffer\n");
     }
 #line 221
     return (-12);
   } else {
 
   }
   }
   {
 #line 225
   __cil_tmp10 = (u32 *)0;
 #line 225
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 225
   __cil_tmp12 = ring->status_page.page_addr;
 #line 225
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 225
   if (__cil_tmp13 == __cil_tmp11) {
     {
 #line 226
     drm_err("i915_dma_resume", "Can not find hardware status page\n");
     }
 #line 227
     return (-22);
   } else {
 
   }
   }
   {
 #line 229
   __cil_tmp14 = ring->status_page.page_addr;
 #line 229
   drm_ut_debug_printk(2U, "drm", "i915_dma_resume", "hw status page @ %p\n", __cil_tmp14);
   }
   {
 #line 231
   __cil_tmp15 = ring->status_page.gfx_addr;
 #line 231
   if (__cil_tmp15 != 0U) {
     {
 #line 232
     intel_ring_setup_status_page(ring);
     }
   } else {
     {
 #line 234
     i915_write_hws_pga(dev);
     }
   }
   }
   {
 #line 236
   drm_ut_debug_printk(2U, "drm", "i915_dma_resume", "Enabled hardware status page\n");
   }
 #line 238
   return (0);
 }
 }
 #line 241 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_dma_init(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_init_t *init ;
   int retcode ;
   enum ldv_26036 __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   int __cil_tmp8 ;
   enum ldv_26036 __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   int __cil_tmp11 ;
   enum ldv_26036 __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   int __cil_tmp14 ;
 
   {
 #line 244
   init = (drm_i915_init_t *)data;
 #line 245
   retcode = 0;
   {
 #line 248
   __cil_tmp6 = init->func;
 #line 248
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 248
   __cil_tmp8 = (int )__cil_tmp7;
 #line 248
   if (__cil_tmp8 == 1) {
 #line 248
     goto case_1;
   } else {
     {
 #line 251
     __cil_tmp9 = init->func;
 #line 251
     __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 251
     __cil_tmp11 = (int )__cil_tmp10;
 #line 251
     if (__cil_tmp11 == 2) {
 #line 251
       goto case_2;
     } else {
       {
 #line 254
       __cil_tmp12 = init->func;
 #line 254
       __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 254
       __cil_tmp14 = (int )__cil_tmp13;
 #line 254
       if (__cil_tmp14 == 3) {
 #line 254
         goto case_3;
       } else {
 #line 257
         goto switch_default;
 #line 247
         if (0) {
           case_1: 
           {
 #line 249
           retcode = i915_initialize(dev, init);
           }
 #line 250
           goto ldv_40316;
           case_2: 
           {
 #line 252
           retcode = i915_dma_cleanup(dev);
           }
 #line 253
           goto ldv_40316;
           case_3: 
           {
 #line 255
           retcode = i915_dma_resume(dev);
           }
 #line 256
           goto ldv_40316;
           switch_default: 
 #line 258
           retcode = -22;
 #line 259
           goto ldv_40316;
         } else {
 
         }
       }
       }
     }
     }
   }
   }
   ldv_40316: ;
 #line 262
   return (retcode);
 }
 }
 #line 274 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int validate_cmd(int cmd ) 
 { unsigned int __cil_tmp2 ;
   unsigned int __cil_tmp3 ;
   int __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   int __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
 
   {
   {
 #line 277
   __cil_tmp2 = (unsigned int )cmd;
 #line 277
   __cil_tmp3 = __cil_tmp2 >> 29;
 #line 277
   __cil_tmp4 = (int )__cil_tmp3;
 #line 277
   if (__cil_tmp4 == 0) {
 #line 277
     goto case_0;
   } else {
     {
 #line 287
     __cil_tmp5 = (unsigned int )cmd;
 #line 287
     __cil_tmp6 = __cil_tmp5 >> 29;
 #line 287
     __cil_tmp7 = (int )__cil_tmp6;
 #line 287
     if (__cil_tmp7 == 1) {
 #line 287
       goto case_1;
     } else {
       {
 #line 289
       __cil_tmp8 = (unsigned int )cmd;
 #line 289
       __cil_tmp9 = __cil_tmp8 >> 29;
 #line 289
       __cil_tmp10 = (int )__cil_tmp9;
 #line 289
       if (__cil_tmp10 == 2) {
 #line 289
         goto case_2;
       } else {
         {
 #line 291
         __cil_tmp11 = (unsigned int )cmd;
 #line 291
         __cil_tmp12 = __cil_tmp11 >> 29;
 #line 291
         __cil_tmp13 = (int )__cil_tmp12;
 #line 291
         if (__cil_tmp13 == 3) {
 #line 291
           goto case_3;
         } else {
 #line 325
           goto switch_default___2;
 #line 276
           if (0) {
             case_0: ;
             {
 #line 279
             __cil_tmp14 = cmd >> 23;
 #line 279
             __cil_tmp15 = __cil_tmp14 & 63;
 #line 279
             if (__cil_tmp15 == 0) {
 #line 279
               goto case_0___0;
             } else {
               {
 #line 281
               __cil_tmp16 = cmd >> 23;
 #line 281
               __cil_tmp17 = __cil_tmp16 & 63;
 #line 281
               if (__cil_tmp17 == 4) {
 #line 281
                 goto case_4;
               } else {
 #line 283
                 goto switch_default;
 #line 278
                 if (0) {
                   case_0___0: ;
 #line 280
                   return (1);
                   case_4: ;
 #line 282
                   return (1);
                   switch_default: ;
 #line 284
                   return (0);
                 } else {
 
                 }
               }
               }
             }
             }
 #line 286
             goto ldv_40327;
             case_1: ;
 #line 288
             return (0);
             case_2: ;
             {
 #line 290
             __cil_tmp18 = cmd & 255;
 #line 290
             return (__cil_tmp18 + 2);
             }
             case_3: ;
             {
 #line 292
             __cil_tmp19 = cmd >> 24;
 #line 292
             __cil_tmp20 = __cil_tmp19 & 31;
 #line 292
             if (__cil_tmp20 <= 24) {
 #line 293
               return (1);
             } else {
 
             }
             }
             {
 #line 296
             __cil_tmp21 = cmd >> 24;
 #line 296
             __cil_tmp22 = __cil_tmp21 & 31;
 #line 296
             if (__cil_tmp22 == 28) {
 #line 296
               goto case_28;
             } else {
               {
 #line 298
               __cil_tmp23 = cmd >> 24;
 #line 298
               __cil_tmp24 = __cil_tmp23 & 31;
 #line 298
               if (__cil_tmp24 == 29) {
 #line 298
                 goto case_29;
               } else {
                 {
 #line 307
                 __cil_tmp25 = cmd >> 24;
 #line 307
                 __cil_tmp26 = __cil_tmp25 & 31;
 #line 307
                 if (__cil_tmp26 == 30) {
 #line 307
                   goto case_30;
                 } else {
                   {
 #line 312
                   __cil_tmp27 = cmd >> 24;
 #line 312
                   __cil_tmp28 = __cil_tmp27 & 31;
 #line 312
                   if (__cil_tmp28 == 31) {
 #line 312
                     goto case_31;
                   } else {
 #line 322
                     goto switch_default___1;
 #line 295
                     if (0) {
                       case_28: ;
 #line 297
                       return (1);
                       case_29: ;
                       {
 #line 300
                       __cil_tmp29 = cmd >> 16;
 #line 300
                       __cil_tmp30 = __cil_tmp29 & 255;
 #line 300
                       if (__cil_tmp30 == 3) {
 #line 300
                         goto case_3___0;
                       } else {
                         {
 #line 302
                         __cil_tmp31 = cmd >> 16;
 #line 302
                         __cil_tmp32 = __cil_tmp31 & 255;
 #line 302
                         if (__cil_tmp32 == 4) {
 #line 302
                           goto case_4___0;
                         } else {
 #line 304
                           goto switch_default___0;
 #line 299
                           if (0) {
                             case_3___0: ;
                             {
 #line 301
                             __cil_tmp33 = cmd & 31;
 #line 301
                             return (__cil_tmp33 + 2);
                             }
                             case_4___0: ;
                             {
 #line 303
                             __cil_tmp34 = cmd & 15;
 #line 303
                             return (__cil_tmp34 + 2);
                             }
                             switch_default___0: ;
                             {
 #line 305
                             __cil_tmp35 = cmd & 65535;
 #line 305
                             return (__cil_tmp35 + 2);
                             }
                           } else {
 
                           }
                         }
                         }
                       }
                       }
                       case_30: ;
                       {
 #line 308
                       __cil_tmp36 = cmd & 8388608;
 #line 308
                       if (__cil_tmp36 != 0) {
                         {
 #line 309
                         __cil_tmp37 = cmd & 65535;
 #line 309
                         return (__cil_tmp37 + 1);
                         }
                       } else {
 #line 311
                         return (1);
                       }
                       }
                       case_31: ;
                       {
 #line 313
                       __cil_tmp38 = cmd & 8388608;
 #line 313
                       if (__cil_tmp38 == 0) {
                         {
 #line 314
                         __cil_tmp39 = cmd & 131071;
 #line 314
                         return (__cil_tmp39 + 2);
                         }
                       } else {
                         {
 #line 315
                         __cil_tmp40 = cmd & 131072;
 #line 315
                         if (__cil_tmp40 != 0) {
                           {
 #line 316
                           __cil_tmp41 = cmd & 65535;
 #line 316
                           if (__cil_tmp41 == 0) {
 #line 317
                             return (0);
                           } else {
                             {
 #line 319
                             __cil_tmp42 = cmd & 65535;
 #line 319
                             __cil_tmp43 = __cil_tmp42 + 1;
 #line 319
                             __cil_tmp44 = __cil_tmp43 / 2;
 #line 319
                             return (__cil_tmp44 + 1);
                             }
                           }
                           }
                         } else {
 #line 321
                           return (2);
                         }
                         }
                       }
                       }
                       switch_default___1: ;
 #line 323
                       return (0);
                     } else {
 
                     }
                   }
                   }
                 }
                 }
               }
               }
             }
             }
             switch_default___2: ;
 #line 326
             return (0);
           } else {
 
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_40327: ;
 #line 329
   return (0);
 }
 }
 #line 332 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_emit_cmds(struct drm_device *dev , int *buffer , int dwords ) 
 { drm_i915_private_t *dev_priv ;
   int i ;
   int ret ;
   int sz ;
   int tmp ;
   void *__cil_tmp9 ;
   struct intel_ring_buffer (*__cil_tmp10)[3U] ;
   struct intel_ring_buffer *__cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   int *__cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   struct intel_ring_buffer (*__cil_tmp26)[3U] ;
   struct intel_ring_buffer *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   int *__cil_tmp29 ;
   int __cil_tmp30 ;
   u32 __cil_tmp31 ;
   struct intel_ring_buffer (*__cil_tmp32)[3U] ;
   struct intel_ring_buffer *__cil_tmp33 ;
   struct intel_ring_buffer (*__cil_tmp34)[3U] ;
   struct intel_ring_buffer *__cil_tmp35 ;
 
   {
 #line 334
   __cil_tmp9 = dev->dev_private;
 #line 334
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
   {
 #line 337
   __cil_tmp10 = & dev_priv->ring;
 #line 337
   __cil_tmp11 = (struct intel_ring_buffer *)__cil_tmp10;
 #line 337
   __cil_tmp12 = __cil_tmp11->size;
 #line 337
   __cil_tmp13 = __cil_tmp12 + -8;
 #line 337
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 337
   __cil_tmp15 = dwords + 1;
 #line 337
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 337
   __cil_tmp17 = __cil_tmp16 * 4UL;
 #line 337
   if (__cil_tmp17 >= __cil_tmp14) {
 #line 338
     return (-22);
   } else {
 
   }
   }
 #line 340
   i = 0;
 #line 340
   goto ldv_40350;
   ldv_40349: 
   {
 #line 341
   __cil_tmp18 = (unsigned long )i;
 #line 341
   __cil_tmp19 = buffer + __cil_tmp18;
 #line 341
   __cil_tmp20 = *__cil_tmp19;
 #line 341
   tmp = validate_cmd(__cil_tmp20);
 #line 341
   sz = tmp;
   }
 #line 342
   if (sz == 0) {
 #line 343
     return (-22);
   } else {
     {
 #line 342
     __cil_tmp21 = i + sz;
 #line 342
     if (__cil_tmp21 > dwords) {
 #line 343
       return (-22);
     } else {
 
     }
     }
   }
 #line 344
   i = i + sz;
   ldv_40350: ;
 #line 340
   if (i < dwords) {
 #line 341
     goto ldv_40349;
   } else {
 #line 343
     goto ldv_40351;
   }
   ldv_40351: 
   {
 #line 347
   __cil_tmp22 = & dev_priv->ring;
 #line 347
   __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 347
   __cil_tmp24 = dwords + 1;
 #line 347
   __cil_tmp25 = __cil_tmp24 & -2;
 #line 347
   ret = intel_ring_begin(__cil_tmp23, __cil_tmp25);
   }
 #line 348
   if (ret != 0) {
 #line 349
     return (ret);
   } else {
 
   }
 #line 351
   i = 0;
 #line 351
   goto ldv_40353;
   ldv_40352: 
   {
 #line 352
   __cil_tmp26 = & dev_priv->ring;
 #line 352
   __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
 #line 352
   __cil_tmp28 = (unsigned long )i;
 #line 352
   __cil_tmp29 = buffer + __cil_tmp28;
 #line 352
   __cil_tmp30 = *__cil_tmp29;
 #line 352
   __cil_tmp31 = (u32 )__cil_tmp30;
 #line 352
   intel_ring_emit(__cil_tmp27, __cil_tmp31);
 #line 351
   i = i + 1;
   }
   ldv_40353: ;
 #line 351
   if (i < dwords) {
 #line 352
     goto ldv_40352;
   } else {
 #line 354
     goto ldv_40354;
   }
   ldv_40354: ;
 #line 353
   if (dwords & 1) {
     {
 #line 354
     __cil_tmp32 = & dev_priv->ring;
 #line 354
     __cil_tmp33 = (struct intel_ring_buffer *)__cil_tmp32;
 #line 354
     intel_ring_emit(__cil_tmp33, 0U);
     }
   } else {
 
   }
   {
 #line 356
   __cil_tmp34 = & dev_priv->ring;
 #line 356
   __cil_tmp35 = (struct intel_ring_buffer *)__cil_tmp34;
 #line 356
   intel_ring_advance(__cil_tmp35);
   }
 #line 358
   return (0);
 }
 }
 #line 362 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_emit_box(struct drm_device *dev , struct drm_clip_rect *box , int DR1 , int DR4 ) 
 { struct drm_i915_private *dev_priv ;
   int ret ;
   void *__cil_tmp7 ;
   unsigned short __cil_tmp8 ;
   int __cil_tmp9 ;
   unsigned short __cil_tmp10 ;
   int __cil_tmp11 ;
   unsigned short __cil_tmp12 ;
   int __cil_tmp13 ;
   unsigned short __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned short __cil_tmp16 ;
   int __cil_tmp17 ;
   unsigned short __cil_tmp18 ;
   int __cil_tmp19 ;
   unsigned short __cil_tmp20 ;
   int __cil_tmp21 ;
   unsigned short __cil_tmp22 ;
   int __cil_tmp23 ;
   unsigned short __cil_tmp24 ;
   int __cil_tmp25 ;
   unsigned short __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned short __cil_tmp28 ;
   int __cil_tmp29 ;
   unsigned short __cil_tmp30 ;
   int __cil_tmp31 ;
   unsigned short __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned short __cil_tmp34 ;
   int __cil_tmp35 ;
   unsigned short __cil_tmp36 ;
   int __cil_tmp37 ;
   unsigned short __cil_tmp38 ;
   int __cil_tmp39 ;
   unsigned short __cil_tmp40 ;
   int __cil_tmp41 ;
   unsigned short __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned short __cil_tmp44 ;
   int __cil_tmp45 ;
   unsigned short __cil_tmp46 ;
   int __cil_tmp47 ;
   unsigned short __cil_tmp48 ;
   int __cil_tmp49 ;
   unsigned short __cil_tmp50 ;
   int __cil_tmp51 ;
   void *__cil_tmp52 ;
   struct drm_i915_private *__cil_tmp53 ;
   struct intel_device_info  const  *__cil_tmp54 ;
   u8 __cil_tmp55 ;
   unsigned char __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   struct intel_ring_buffer (*__cil_tmp58)[3U] ;
   struct intel_ring_buffer *__cil_tmp59 ;
   struct intel_ring_buffer (*__cil_tmp60)[3U] ;
   struct intel_ring_buffer *__cil_tmp61 ;
   struct intel_ring_buffer (*__cil_tmp62)[3U] ;
   struct intel_ring_buffer *__cil_tmp63 ;
   unsigned short __cil_tmp64 ;
   int __cil_tmp65 ;
   int __cil_tmp66 ;
   unsigned short __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   u32 __cil_tmp70 ;
   struct intel_ring_buffer (*__cil_tmp71)[3U] ;
   struct intel_ring_buffer *__cil_tmp72 ;
   unsigned short __cil_tmp73 ;
   int __cil_tmp74 ;
   int __cil_tmp75 ;
   int __cil_tmp76 ;
   unsigned short __cil_tmp77 ;
   int __cil_tmp78 ;
   int __cil_tmp79 ;
   int __cil_tmp80 ;
   int __cil_tmp81 ;
   u32 __cil_tmp82 ;
   struct intel_ring_buffer (*__cil_tmp83)[3U] ;
   struct intel_ring_buffer *__cil_tmp84 ;
   u32 __cil_tmp85 ;
   struct intel_ring_buffer (*__cil_tmp86)[3U] ;
   struct intel_ring_buffer *__cil_tmp87 ;
   struct intel_ring_buffer (*__cil_tmp88)[3U] ;
   struct intel_ring_buffer *__cil_tmp89 ;
   struct intel_ring_buffer (*__cil_tmp90)[3U] ;
   struct intel_ring_buffer *__cil_tmp91 ;
   u32 __cil_tmp92 ;
   struct intel_ring_buffer (*__cil_tmp93)[3U] ;
   struct intel_ring_buffer *__cil_tmp94 ;
   unsigned short __cil_tmp95 ;
   int __cil_tmp96 ;
   int __cil_tmp97 ;
   unsigned short __cil_tmp98 ;
   int __cil_tmp99 ;
   int __cil_tmp100 ;
   u32 __cil_tmp101 ;
   struct intel_ring_buffer (*__cil_tmp102)[3U] ;
   struct intel_ring_buffer *__cil_tmp103 ;
   unsigned short __cil_tmp104 ;
   int __cil_tmp105 ;
   int __cil_tmp106 ;
   int __cil_tmp107 ;
   unsigned short __cil_tmp108 ;
   int __cil_tmp109 ;
   int __cil_tmp110 ;
   int __cil_tmp111 ;
   int __cil_tmp112 ;
   u32 __cil_tmp113 ;
   struct intel_ring_buffer (*__cil_tmp114)[3U] ;
   struct intel_ring_buffer *__cil_tmp115 ;
   u32 __cil_tmp116 ;
   struct intel_ring_buffer (*__cil_tmp117)[3U] ;
   struct intel_ring_buffer *__cil_tmp118 ;
   struct intel_ring_buffer (*__cil_tmp119)[3U] ;
   struct intel_ring_buffer *__cil_tmp120 ;
 
   {
 #line 366
   __cil_tmp7 = dev->dev_private;
 #line 366
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
   {
 #line 369
   __cil_tmp8 = box->y1;
 #line 369
   __cil_tmp9 = (int )__cil_tmp8;
 #line 369
   __cil_tmp10 = box->y2;
 #line 369
   __cil_tmp11 = (int )__cil_tmp10;
 #line 369
   if (__cil_tmp11 <= __cil_tmp9) {
     {
 #line 371
     __cil_tmp12 = box->x1;
 #line 371
     __cil_tmp13 = (int )__cil_tmp12;
 #line 371
     __cil_tmp14 = box->y1;
 #line 371
     __cil_tmp15 = (int )__cil_tmp14;
 #line 371
     __cil_tmp16 = box->x2;
 #line 371
     __cil_tmp17 = (int )__cil_tmp16;
 #line 371
     __cil_tmp18 = box->y2;
 #line 371
     __cil_tmp19 = (int )__cil_tmp18;
 #line 371
     drm_err("i915_emit_box", "Bad box %d,%d..%d,%d\n", __cil_tmp13, __cil_tmp15, __cil_tmp17,
             __cil_tmp19);
     }
 #line 373
     return (-22);
   } else {
     {
 #line 369
     __cil_tmp20 = box->x1;
 #line 369
     __cil_tmp21 = (int )__cil_tmp20;
 #line 369
     __cil_tmp22 = box->x2;
 #line 369
     __cil_tmp23 = (int )__cil_tmp22;
 #line 369
     if (__cil_tmp23 <= __cil_tmp21) {
       {
 #line 371
       __cil_tmp24 = box->x1;
 #line 371
       __cil_tmp25 = (int )__cil_tmp24;
 #line 371
       __cil_tmp26 = box->y1;
 #line 371
       __cil_tmp27 = (int )__cil_tmp26;
 #line 371
       __cil_tmp28 = box->x2;
 #line 371
       __cil_tmp29 = (int )__cil_tmp28;
 #line 371
       __cil_tmp30 = box->y2;
 #line 371
       __cil_tmp31 = (int )__cil_tmp30;
 #line 371
       drm_err("i915_emit_box", "Bad box %d,%d..%d,%d\n", __cil_tmp25, __cil_tmp27,
               __cil_tmp29, __cil_tmp31);
       }
 #line 373
       return (-22);
     } else {
       {
 #line 369
       __cil_tmp32 = box->y2;
 #line 369
       __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 369
       if (__cil_tmp33 == 0U) {
         {
 #line 371
         __cil_tmp34 = box->x1;
 #line 371
         __cil_tmp35 = (int )__cil_tmp34;
 #line 371
         __cil_tmp36 = box->y1;
 #line 371
         __cil_tmp37 = (int )__cil_tmp36;
 #line 371
         __cil_tmp38 = box->x2;
 #line 371
         __cil_tmp39 = (int )__cil_tmp38;
 #line 371
         __cil_tmp40 = box->y2;
 #line 371
         __cil_tmp41 = (int )__cil_tmp40;
 #line 371
         drm_err("i915_emit_box", "Bad box %d,%d..%d,%d\n", __cil_tmp35, __cil_tmp37,
                 __cil_tmp39, __cil_tmp41);
         }
 #line 373
         return (-22);
       } else {
         {
 #line 369
         __cil_tmp42 = box->x2;
 #line 369
         __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 369
         if (__cil_tmp43 == 0U) {
           {
 #line 371
           __cil_tmp44 = box->x1;
 #line 371
           __cil_tmp45 = (int )__cil_tmp44;
 #line 371
           __cil_tmp46 = box->y1;
 #line 371
           __cil_tmp47 = (int )__cil_tmp46;
 #line 371
           __cil_tmp48 = box->x2;
 #line 371
           __cil_tmp49 = (int )__cil_tmp48;
 #line 371
           __cil_tmp50 = box->y2;
 #line 371
           __cil_tmp51 = (int )__cil_tmp50;
 #line 371
           drm_err("i915_emit_box", "Bad box %d,%d..%d,%d\n", __cil_tmp45, __cil_tmp47,
                   __cil_tmp49, __cil_tmp51);
           }
 #line 373
           return (-22);
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
   {
 #line 376
   __cil_tmp52 = dev->dev_private;
 #line 376
   __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
 #line 376
   __cil_tmp54 = __cil_tmp53->info;
 #line 376
   __cil_tmp55 = __cil_tmp54->gen;
 #line 376
   __cil_tmp56 = (unsigned char )__cil_tmp55;
 #line 376
   __cil_tmp57 = (unsigned int )__cil_tmp56;
 #line 376
   if (__cil_tmp57 > 3U) {
     {
 #line 377
     __cil_tmp58 = & dev_priv->ring;
 #line 377
     __cil_tmp59 = (struct intel_ring_buffer *)__cil_tmp58;
 #line 377
     ret = intel_ring_begin(__cil_tmp59, 4);
     }
 #line 378
     if (ret != 0) {
 #line 379
       return (ret);
     } else {
 
     }
     {
 #line 381
     __cil_tmp60 = & dev_priv->ring;
 #line 381
     __cil_tmp61 = (struct intel_ring_buffer *)__cil_tmp60;
 #line 381
     intel_ring_emit(__cil_tmp61, 2030043138U);
 #line 382
     __cil_tmp62 = & dev_priv->ring;
 #line 382
     __cil_tmp63 = (struct intel_ring_buffer *)__cil_tmp62;
 #line 382
     __cil_tmp64 = box->y1;
 #line 382
     __cil_tmp65 = (int )__cil_tmp64;
 #line 382
     __cil_tmp66 = __cil_tmp65 << 16;
 #line 382
     __cil_tmp67 = box->x1;
 #line 382
     __cil_tmp68 = (int )__cil_tmp67;
 #line 382
     __cil_tmp69 = __cil_tmp68 | __cil_tmp66;
 #line 382
     __cil_tmp70 = (u32 )__cil_tmp69;
 #line 382
     intel_ring_emit(__cil_tmp63, __cil_tmp70);
 #line 383
     __cil_tmp71 = & dev_priv->ring;
 #line 383
     __cil_tmp72 = (struct intel_ring_buffer *)__cil_tmp71;
 #line 383
     __cil_tmp73 = box->y2;
 #line 383
     __cil_tmp74 = (int )__cil_tmp73;
 #line 383
     __cil_tmp75 = __cil_tmp74 + -1;
 #line 383
     __cil_tmp76 = __cil_tmp75 << 16;
 #line 383
     __cil_tmp77 = box->x2;
 #line 383
     __cil_tmp78 = (int )__cil_tmp77;
 #line 383
     __cil_tmp79 = __cil_tmp78 + -1;
 #line 383
     __cil_tmp80 = __cil_tmp79 & 65535;
 #line 383
     __cil_tmp81 = __cil_tmp80 | __cil_tmp76;
 #line 383
     __cil_tmp82 = (u32 )__cil_tmp81;
 #line 383
     intel_ring_emit(__cil_tmp72, __cil_tmp82);
 #line 384
     __cil_tmp83 = & dev_priv->ring;
 #line 384
     __cil_tmp84 = (struct intel_ring_buffer *)__cil_tmp83;
 #line 384
     __cil_tmp85 = (u32 )DR4;
 #line 384
     intel_ring_emit(__cil_tmp84, __cil_tmp85);
     }
   } else {
     {
 #line 386
     __cil_tmp86 = & dev_priv->ring;
 #line 386
     __cil_tmp87 = (struct intel_ring_buffer *)__cil_tmp86;
 #line 386
     ret = intel_ring_begin(__cil_tmp87, 6);
     }
 #line 387
     if (ret != 0) {
 #line 388
       return (ret);
     } else {
 
     }
     {
 #line 390
     __cil_tmp88 = & dev_priv->ring;
 #line 390
     __cil_tmp89 = (struct intel_ring_buffer *)__cil_tmp88;
 #line 390
     intel_ring_emit(__cil_tmp89, 2105540611U);
 #line 391
     __cil_tmp90 = & dev_priv->ring;
 #line 391
     __cil_tmp91 = (struct intel_ring_buffer *)__cil_tmp90;
 #line 391
     __cil_tmp92 = (u32 )DR1;
 #line 391
     intel_ring_emit(__cil_tmp91, __cil_tmp92);
 #line 392
     __cil_tmp93 = & dev_priv->ring;
 #line 392
     __cil_tmp94 = (struct intel_ring_buffer *)__cil_tmp93;
 #line 392
     __cil_tmp95 = box->y1;
 #line 392
     __cil_tmp96 = (int )__cil_tmp95;
 #line 392
     __cil_tmp97 = __cil_tmp96 << 16;
 #line 392
     __cil_tmp98 = box->x1;
 #line 392
     __cil_tmp99 = (int )__cil_tmp98;
 #line 392
     __cil_tmp100 = __cil_tmp99 | __cil_tmp97;
 #line 392
     __cil_tmp101 = (u32 )__cil_tmp100;
 #line 392
     intel_ring_emit(__cil_tmp94, __cil_tmp101);
 #line 393
     __cil_tmp102 = & dev_priv->ring;
 #line 393
     __cil_tmp103 = (struct intel_ring_buffer *)__cil_tmp102;
 #line 393
     __cil_tmp104 = box->y2;
 #line 393
     __cil_tmp105 = (int )__cil_tmp104;
 #line 393
     __cil_tmp106 = __cil_tmp105 + -1;
 #line 393
     __cil_tmp107 = __cil_tmp106 << 16;
 #line 393
     __cil_tmp108 = box->x2;
 #line 393
     __cil_tmp109 = (int )__cil_tmp108;
 #line 393
     __cil_tmp110 = __cil_tmp109 + -1;
 #line 393
     __cil_tmp111 = __cil_tmp110 & 65535;
 #line 393
     __cil_tmp112 = __cil_tmp111 | __cil_tmp107;
 #line 393
     __cil_tmp113 = (u32 )__cil_tmp112;
 #line 393
     intel_ring_emit(__cil_tmp103, __cil_tmp113);
 #line 394
     __cil_tmp114 = & dev_priv->ring;
 #line 394
     __cil_tmp115 = (struct intel_ring_buffer *)__cil_tmp114;
 #line 394
     __cil_tmp116 = (u32 )DR4;
 #line 394
     intel_ring_emit(__cil_tmp115, __cil_tmp116);
 #line 395
     __cil_tmp117 = & dev_priv->ring;
 #line 395
     __cil_tmp118 = (struct intel_ring_buffer *)__cil_tmp117;
 #line 395
     intel_ring_emit(__cil_tmp118, 0U);
     }
   }
   }
   {
 #line 397
   __cil_tmp119 = & dev_priv->ring;
 #line 397
   __cil_tmp120 = (struct intel_ring_buffer *)__cil_tmp119;
 #line 397
   intel_ring_advance(__cil_tmp120);
   }
 #line 399
   return (0);
 }
 }
 #line 406 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_emit_breadcrumb(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   int tmp ;
   void *__cil_tmp5 ;
   struct drm_minor *__cil_tmp6 ;
   struct drm_master *__cil_tmp7 ;
   void *__cil_tmp8 ;
   uint32_t __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   int __cil_tmp11 ;
   struct _drm_i915_sarea *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct _drm_i915_sarea *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct _drm_i915_sarea *__cil_tmp16 ;
   uint32_t __cil_tmp17 ;
   struct intel_ring_buffer (*__cil_tmp18)[3U] ;
   struct intel_ring_buffer *__cil_tmp19 ;
   struct intel_ring_buffer (*__cil_tmp20)[3U] ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
   struct intel_ring_buffer (*__cil_tmp24)[3U] ;
   struct intel_ring_buffer *__cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   struct intel_ring_buffer (*__cil_tmp27)[3U] ;
   struct intel_ring_buffer *__cil_tmp28 ;
   struct intel_ring_buffer (*__cil_tmp29)[3U] ;
   struct intel_ring_buffer *__cil_tmp30 ;
 
   {
 #line 408
   __cil_tmp5 = dev->dev_private;
 #line 408
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 409
   __cil_tmp6 = dev->primary;
 #line 409
   __cil_tmp7 = __cil_tmp6->master;
 #line 409
   __cil_tmp8 = __cil_tmp7->driver_priv;
 #line 409
   master_priv = (struct drm_i915_master_private *)__cil_tmp8;
 #line 411
   __cil_tmp9 = dev_priv->counter;
 #line 411
   dev_priv->counter = __cil_tmp9 + 1U;
   {
 #line 412
   __cil_tmp10 = dev_priv->counter;
 #line 412
   __cil_tmp11 = (int )__cil_tmp10;
 #line 412
   if (__cil_tmp11 < 0) {
 #line 413
     dev_priv->counter = 0U;
   } else {
 
   }
   }
   {
 #line 414
   __cil_tmp12 = (struct _drm_i915_sarea *)0;
 #line 414
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 414
   __cil_tmp14 = master_priv->sarea_priv;
 #line 414
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 414
   if (__cil_tmp15 != __cil_tmp13) {
 #line 415
     __cil_tmp16 = master_priv->sarea_priv;
 #line 415
     __cil_tmp17 = dev_priv->counter;
 #line 415
     __cil_tmp16->last_enqueue = (int )__cil_tmp17;
   } else {
 
   }
   }
   {
 #line 417
   __cil_tmp18 = & dev_priv->ring;
 #line 417
   __cil_tmp19 = (struct intel_ring_buffer *)__cil_tmp18;
 #line 417
   tmp = intel_ring_begin(__cil_tmp19, 4);
   }
 #line 417
   if (tmp == 0) {
     {
 #line 418
     __cil_tmp20 = & dev_priv->ring;
 #line 418
     __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
 #line 418
     intel_ring_emit(__cil_tmp21, 276824065U);
 #line 419
     __cil_tmp22 = & dev_priv->ring;
 #line 419
     __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 419
     intel_ring_emit(__cil_tmp23, 132U);
 #line 420
     __cil_tmp24 = & dev_priv->ring;
 #line 420
     __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
 #line 420
     __cil_tmp26 = dev_priv->counter;
 #line 420
     intel_ring_emit(__cil_tmp25, __cil_tmp26);
 #line 421
     __cil_tmp27 = & dev_priv->ring;
 #line 421
     __cil_tmp28 = (struct intel_ring_buffer *)__cil_tmp27;
 #line 421
     intel_ring_emit(__cil_tmp28, 0U);
 #line 422
     __cil_tmp29 = & dev_priv->ring;
 #line 422
     __cil_tmp30 = (struct intel_ring_buffer *)__cil_tmp29;
 #line 422
     intel_ring_advance(__cil_tmp30);
     }
   } else {
 
   }
 #line 424
   return;
 }
 }
 #line 426 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_dispatch_cmdbuffer(struct drm_device *dev , drm_i915_cmdbuffer_t *cmd ,
                                    struct drm_clip_rect *cliprects , void *cmdbuf ) 
 { int nbox ;
   int i ;
   int count ;
   int ret ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_clip_rect *__cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int *__cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
 
   {
 #line 431
   nbox = cmd->num_cliprects;
 #line 432
   i = 0;
   {
 #line 434
   __cil_tmp9 = cmd->sz;
 #line 434
   __cil_tmp10 = __cil_tmp9 & 3;
 #line 434
   if (__cil_tmp10 != 0) {
     {
 #line 435
     drm_err("i915_dispatch_cmdbuffer", "alignment");
     }
 #line 436
     return (-22);
   } else {
 
   }
   }
   {
 #line 439
   i915_kernel_lost_context(dev);
   }
 #line 441
   if (nbox != 0) {
 #line 441
     count = nbox;
   } else {
 #line 441
     count = 1;
   }
 #line 443
   i = 0;
 #line 443
   goto ldv_40381;
   ldv_40380: ;
 #line 444
   if (i < nbox) {
     {
 #line 445
     __cil_tmp11 = (unsigned long )i;
 #line 445
     __cil_tmp12 = cliprects + __cil_tmp11;
 #line 445
     __cil_tmp13 = cmd->DR1;
 #line 445
     __cil_tmp14 = cmd->DR4;
 #line 445
     ret = i915_emit_box(dev, __cil_tmp12, __cil_tmp13, __cil_tmp14);
     }
 #line 447
     if (ret != 0) {
 #line 448
       return (ret);
     } else {
 
     }
   } else {
 
   }
   {
 #line 451
   __cil_tmp15 = (int *)cmdbuf;
 #line 451
   __cil_tmp16 = cmd->sz;
 #line 451
   __cil_tmp17 = __cil_tmp16 / 4;
 #line 451
   ret = i915_emit_cmds(dev, __cil_tmp15, __cil_tmp17);
   }
 #line 452
   if (ret != 0) {
 #line 453
     return (ret);
   } else {
 
   }
 #line 443
   i = i + 1;
   ldv_40381: ;
 #line 443
   if (i < count) {
 #line 444
     goto ldv_40380;
   } else {
 #line 446
     goto ldv_40382;
   }
   ldv_40382: 
   {
 #line 456
   i915_emit_breadcrumb(dev);
   }
 #line 457
   return (0);
 }
 }
 #line 460 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_dispatch_batchbuffer(struct drm_device *dev , drm_i915_batchbuffer_t *batch ,
                                      struct drm_clip_rect *cliprects ) 
 { struct drm_i915_private *dev_priv ;
   int nbox ;
   int i ;
   int count ;
   int ret ;
   int tmp ;
   void *__cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct drm_clip_rect *__cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   struct intel_ring_buffer (*__cil_tmp21)[3U] ;
   struct intel_ring_buffer *__cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   u8 __cil_tmp26 ;
   unsigned char __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   struct intel_ring_buffer (*__cil_tmp29)[3U] ;
   struct intel_ring_buffer *__cil_tmp30 ;
   struct intel_ring_buffer (*__cil_tmp31)[3U] ;
   struct intel_ring_buffer *__cil_tmp32 ;
   int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   struct intel_ring_buffer (*__cil_tmp35)[3U] ;
   struct intel_ring_buffer *__cil_tmp36 ;
   struct intel_ring_buffer (*__cil_tmp37)[3U] ;
   struct intel_ring_buffer *__cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   u32 __cil_tmp41 ;
   struct intel_ring_buffer (*__cil_tmp42)[3U] ;
   struct intel_ring_buffer *__cil_tmp43 ;
   struct intel_ring_buffer (*__cil_tmp44)[3U] ;
   struct intel_ring_buffer *__cil_tmp45 ;
   struct intel_ring_buffer (*__cil_tmp46)[3U] ;
   struct intel_ring_buffer *__cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   u32 __cil_tmp50 ;
   struct intel_ring_buffer (*__cil_tmp51)[3U] ;
   struct intel_ring_buffer *__cil_tmp52 ;
   int __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   u32 __cil_tmp57 ;
   struct intel_ring_buffer (*__cil_tmp58)[3U] ;
   struct intel_ring_buffer *__cil_tmp59 ;
   struct intel_ring_buffer (*__cil_tmp60)[3U] ;
   struct intel_ring_buffer *__cil_tmp61 ;
   void *__cil_tmp62 ;
   struct drm_i915_private *__cil_tmp63 ;
   struct intel_device_info  const  *__cil_tmp64 ;
   unsigned char *__cil_tmp65 ;
   unsigned char *__cil_tmp66 ;
   unsigned char __cil_tmp67 ;
   unsigned int __cil_tmp68 ;
   void *__cil_tmp69 ;
   struct drm_i915_private *__cil_tmp70 ;
   struct intel_device_info  const  *__cil_tmp71 ;
   u8 __cil_tmp72 ;
   unsigned char __cil_tmp73 ;
   unsigned int __cil_tmp74 ;
   struct intel_ring_buffer (*__cil_tmp75)[3U] ;
   struct intel_ring_buffer *__cil_tmp76 ;
   struct intel_ring_buffer (*__cil_tmp77)[3U] ;
   struct intel_ring_buffer *__cil_tmp78 ;
   struct intel_ring_buffer (*__cil_tmp79)[3U] ;
   struct intel_ring_buffer *__cil_tmp80 ;
   struct intel_ring_buffer (*__cil_tmp81)[3U] ;
   struct intel_ring_buffer *__cil_tmp82 ;
 
   {
 #line 464
   __cil_tmp10 = dev->dev_private;
 #line 464
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 465
   nbox = batch->num_cliprects;
   {
 #line 468
   __cil_tmp11 = batch->used;
 #line 468
   __cil_tmp12 = batch->start;
 #line 468
   __cil_tmp13 = __cil_tmp12 | __cil_tmp11;
 #line 468
   __cil_tmp14 = __cil_tmp13 & 7;
 #line 468
   if (__cil_tmp14 != 0) {
     {
 #line 469
     drm_err("i915_dispatch_batchbuffer", "alignment");
     }
 #line 470
     return (-22);
   } else {
 
   }
   }
   {
 #line 473
   i915_kernel_lost_context(dev);
   }
 #line 475
   if (nbox != 0) {
 #line 475
     count = nbox;
   } else {
 #line 475
     count = 1;
   }
 #line 476
   i = 0;
 #line 476
   goto ldv_40395;
   ldv_40394: ;
 #line 477
   if (i < nbox) {
     {
 #line 478
     __cil_tmp15 = (unsigned long )i;
 #line 478
     __cil_tmp16 = cliprects + __cil_tmp15;
 #line 478
     __cil_tmp17 = batch->DR1;
 #line 478
     __cil_tmp18 = batch->DR4;
 #line 478
     ret = i915_emit_box(dev, __cil_tmp16, __cil_tmp17, __cil_tmp18);
     }
 #line 480
     if (ret != 0) {
 #line 481
       return (ret);
     } else {
 
     }
   } else {
 
   }
   {
 #line 484
   __cil_tmp19 = dev->pci_device;
 #line 484
   if (__cil_tmp19 != 13687) {
     {
 #line 484
     __cil_tmp20 = dev->pci_device;
 #line 484
     if (__cil_tmp20 != 9570) {
       {
 #line 485
       __cil_tmp21 = & dev_priv->ring;
 #line 485
       __cil_tmp22 = (struct intel_ring_buffer *)__cil_tmp21;
 #line 485
       ret = intel_ring_begin(__cil_tmp22, 2);
       }
 #line 486
       if (ret != 0) {
 #line 487
         return (ret);
       } else {
 
       }
       {
 #line 489
       __cil_tmp23 = dev->dev_private;
 #line 489
       __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 489
       __cil_tmp25 = __cil_tmp24->info;
 #line 489
       __cil_tmp26 = __cil_tmp25->gen;
 #line 489
       __cil_tmp27 = (unsigned char )__cil_tmp26;
 #line 489
       __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 489
       if (__cil_tmp28 > 3U) {
         {
 #line 490
         __cil_tmp29 = & dev_priv->ring;
 #line 490
         __cil_tmp30 = (struct intel_ring_buffer *)__cil_tmp29;
 #line 490
         intel_ring_emit(__cil_tmp30, 411042176U);
 #line 491
         __cil_tmp31 = & dev_priv->ring;
 #line 491
         __cil_tmp32 = (struct intel_ring_buffer *)__cil_tmp31;
 #line 491
         __cil_tmp33 = batch->start;
 #line 491
         __cil_tmp34 = (u32 )__cil_tmp33;
 #line 491
         intel_ring_emit(__cil_tmp32, __cil_tmp34);
         }
       } else {
         {
 #line 493
         __cil_tmp35 = & dev_priv->ring;
 #line 493
         __cil_tmp36 = (struct intel_ring_buffer *)__cil_tmp35;
 #line 493
         intel_ring_emit(__cil_tmp36, 411041920U);
 #line 494
         __cil_tmp37 = & dev_priv->ring;
 #line 494
         __cil_tmp38 = (struct intel_ring_buffer *)__cil_tmp37;
 #line 494
         __cil_tmp39 = batch->start;
 #line 494
         __cil_tmp40 = __cil_tmp39 | 1;
 #line 494
         __cil_tmp41 = (u32 )__cil_tmp40;
 #line 494
         intel_ring_emit(__cil_tmp38, __cil_tmp41);
         }
       }
       }
     } else {
 #line 484
       goto _L;
     }
     }
   } else {
     _L: 
     {
 #line 497
     __cil_tmp42 = & dev_priv->ring;
 #line 497
     __cil_tmp43 = (struct intel_ring_buffer *)__cil_tmp42;
 #line 497
     ret = intel_ring_begin(__cil_tmp43, 4);
     }
 #line 498
     if (ret != 0) {
 #line 499
       return (ret);
     } else {
 
     }
     {
 #line 501
     __cil_tmp44 = & dev_priv->ring;
 #line 501
     __cil_tmp45 = (struct intel_ring_buffer *)__cil_tmp44;
 #line 501
     intel_ring_emit(__cil_tmp45, 402653185U);
 #line 502
     __cil_tmp46 = & dev_priv->ring;
 #line 502
     __cil_tmp47 = (struct intel_ring_buffer *)__cil_tmp46;
 #line 502
     __cil_tmp48 = batch->start;
 #line 502
     __cil_tmp49 = __cil_tmp48 | 1;
 #line 502
     __cil_tmp50 = (u32 )__cil_tmp49;
 #line 502
     intel_ring_emit(__cil_tmp47, __cil_tmp50);
 #line 503
     __cil_tmp51 = & dev_priv->ring;
 #line 503
     __cil_tmp52 = (struct intel_ring_buffer *)__cil_tmp51;
 #line 503
     __cil_tmp53 = batch->used;
 #line 503
     __cil_tmp54 = batch->start;
 #line 503
     __cil_tmp55 = __cil_tmp54 + __cil_tmp53;
 #line 503
     __cil_tmp56 = __cil_tmp55 + -4;
 #line 503
     __cil_tmp57 = (u32 )__cil_tmp56;
 #line 503
     intel_ring_emit(__cil_tmp52, __cil_tmp57);
 #line 504
     __cil_tmp58 = & dev_priv->ring;
 #line 504
     __cil_tmp59 = (struct intel_ring_buffer *)__cil_tmp58;
 #line 504
     intel_ring_emit(__cil_tmp59, 0U);
     }
   }
   }
   {
 #line 506
   __cil_tmp60 = & dev_priv->ring;
 #line 506
   __cil_tmp61 = (struct intel_ring_buffer *)__cil_tmp60;
 #line 506
   intel_ring_advance(__cil_tmp61);
 #line 476
   i = i + 1;
   }
   ldv_40395: ;
 #line 476
   if (i < count) {
 #line 477
     goto ldv_40394;
   } else {
 #line 479
     goto ldv_40396;
   }
   ldv_40396: ;
   {
 #line 510
   __cil_tmp62 = dev->dev_private;
 #line 510
   __cil_tmp63 = (struct drm_i915_private *)__cil_tmp62;
 #line 510
   __cil_tmp64 = __cil_tmp63->info;
 #line 510
   __cil_tmp65 = (unsigned char *)__cil_tmp64;
 #line 510
   __cil_tmp66 = __cil_tmp65 + 1UL;
 #line 510
   __cil_tmp67 = *__cil_tmp66;
 #line 510
   __cil_tmp68 = (unsigned int )__cil_tmp67;
 #line 510
   if (__cil_tmp68 != 0U) {
 #line 510
     goto _L___0;
   } else {
     {
 #line 510
     __cil_tmp69 = dev->dev_private;
 #line 510
     __cil_tmp70 = (struct drm_i915_private *)__cil_tmp69;
 #line 510
     __cil_tmp71 = __cil_tmp70->info;
 #line 510
     __cil_tmp72 = __cil_tmp71->gen;
 #line 510
     __cil_tmp73 = (unsigned char )__cil_tmp72;
 #line 510
     __cil_tmp74 = (unsigned int )__cil_tmp73;
 #line 510
     if (__cil_tmp74 == 5U) {
       _L___0: 
       {
 #line 511
       __cil_tmp75 = & dev_priv->ring;
 #line 511
       __cil_tmp76 = (struct intel_ring_buffer *)__cil_tmp75;
 #line 511
       tmp = intel_ring_begin(__cil_tmp76, 2);
       }
 #line 511
       if (tmp == 0) {
         {
 #line 512
         __cil_tmp77 = & dev_priv->ring;
 #line 512
         __cil_tmp78 = (struct intel_ring_buffer *)__cil_tmp77;
 #line 512
         intel_ring_emit(__cil_tmp78, 33554468U);
 #line 513
         __cil_tmp79 = & dev_priv->ring;
 #line 513
         __cil_tmp80 = (struct intel_ring_buffer *)__cil_tmp79;
 #line 513
         intel_ring_emit(__cil_tmp80, 0U);
 #line 514
         __cil_tmp81 = & dev_priv->ring;
 #line 514
         __cil_tmp82 = (struct intel_ring_buffer *)__cil_tmp81;
 #line 514
         intel_ring_advance(__cil_tmp82);
         }
       } else {
 
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 518
   i915_emit_breadcrumb(dev);
   }
 #line 519
   return (0);
 }
 }
 #line 522 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_dispatch_flip(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   int ret ;
   uint32_t tmp ;
   int tmp___0 ;
   void *__cil_tmp7 ;
   struct drm_minor *__cil_tmp8 ;
   struct drm_master *__cil_tmp9 ;
   void *__cil_tmp10 ;
   struct _drm_i915_sarea *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct _drm_i915_sarea *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   int __cil_tmp15 ;
   struct _drm_i915_sarea *__cil_tmp16 ;
   int __cil_tmp17 ;
   struct intel_ring_buffer (*__cil_tmp18)[3U] ;
   struct intel_ring_buffer *__cil_tmp19 ;
   struct intel_ring_buffer (*__cil_tmp20)[3U] ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
   struct intel_ring_buffer (*__cil_tmp24)[3U] ;
   struct intel_ring_buffer *__cil_tmp25 ;
   struct intel_ring_buffer (*__cil_tmp26)[3U] ;
   struct intel_ring_buffer *__cil_tmp27 ;
   int __cil_tmp28 ;
   struct intel_ring_buffer (*__cil_tmp29)[3U] ;
   struct intel_ring_buffer *__cil_tmp30 ;
   int __cil_tmp31 ;
   u32 __cil_tmp32 ;
   struct intel_ring_buffer (*__cil_tmp33)[3U] ;
   struct intel_ring_buffer *__cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   struct intel_ring_buffer (*__cil_tmp37)[3U] ;
   struct intel_ring_buffer *__cil_tmp38 ;
   struct intel_ring_buffer (*__cil_tmp39)[3U] ;
   struct intel_ring_buffer *__cil_tmp40 ;
   struct intel_ring_buffer (*__cil_tmp41)[3U] ;
   struct intel_ring_buffer *__cil_tmp42 ;
   struct intel_ring_buffer (*__cil_tmp43)[3U] ;
   struct intel_ring_buffer *__cil_tmp44 ;
   uint32_t __cil_tmp45 ;
   struct _drm_i915_sarea *__cil_tmp46 ;
   struct intel_ring_buffer (*__cil_tmp47)[3U] ;
   struct intel_ring_buffer *__cil_tmp48 ;
   struct intel_ring_buffer (*__cil_tmp49)[3U] ;
   struct intel_ring_buffer *__cil_tmp50 ;
   struct intel_ring_buffer (*__cil_tmp51)[3U] ;
   struct intel_ring_buffer *__cil_tmp52 ;
   struct intel_ring_buffer (*__cil_tmp53)[3U] ;
   struct intel_ring_buffer *__cil_tmp54 ;
   uint32_t __cil_tmp55 ;
   struct intel_ring_buffer (*__cil_tmp56)[3U] ;
   struct intel_ring_buffer *__cil_tmp57 ;
   struct intel_ring_buffer (*__cil_tmp58)[3U] ;
   struct intel_ring_buffer *__cil_tmp59 ;
   struct _drm_i915_sarea *__cil_tmp60 ;
 
   {
 #line 524
   __cil_tmp7 = dev->dev_private;
 #line 524
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 525
   __cil_tmp8 = dev->primary;
 #line 525
   __cil_tmp9 = __cil_tmp8->master;
 #line 525
   __cil_tmp10 = __cil_tmp9->driver_priv;
 #line 525
   master_priv = (struct drm_i915_master_private *)__cil_tmp10;
   {
 #line 529
   __cil_tmp11 = (struct _drm_i915_sarea *)0;
 #line 529
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 529
   __cil_tmp13 = master_priv->sarea_priv;
 #line 529
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 529
   if (__cil_tmp14 == __cil_tmp12) {
 #line 530
     return (-22);
   } else {
 
   }
   }
   {
 #line 532
   __cil_tmp15 = dev_priv->current_page;
 #line 532
   __cil_tmp16 = master_priv->sarea_priv;
 #line 532
   __cil_tmp17 = __cil_tmp16->pf_current_page;
 #line 532
   drm_ut_debug_printk(2U, "drm", "i915_dispatch_flip", "%s: page=%d pfCurrentPage=%d\n",
                       "i915_dispatch_flip", __cil_tmp15, __cil_tmp17);
 #line 537
   i915_kernel_lost_context(dev);
 #line 539
   __cil_tmp18 = & dev_priv->ring;
 #line 539
   __cil_tmp19 = (struct intel_ring_buffer *)__cil_tmp18;
 #line 539
   ret = intel_ring_begin(__cil_tmp19, 10);
   }
 #line 540
   if (ret != 0) {
 #line 541
     return (ret);
   } else {
 
   }
   {
 #line 543
   __cil_tmp20 = & dev_priv->ring;
 #line 543
   __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
 #line 543
   intel_ring_emit(__cil_tmp21, 33554433U);
 #line 544
   __cil_tmp22 = & dev_priv->ring;
 #line 544
   __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 544
   intel_ring_emit(__cil_tmp23, 0U);
 #line 546
   __cil_tmp24 = & dev_priv->ring;
 #line 546
   __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
 #line 546
   intel_ring_emit(__cil_tmp25, 171966466U);
 #line 547
   __cil_tmp26 = & dev_priv->ring;
 #line 547
   __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
 #line 547
   intel_ring_emit(__cil_tmp27, 0U);
   }
   {
 #line 548
   __cil_tmp28 = dev_priv->current_page;
 #line 548
   if (__cil_tmp28 == 0) {
     {
 #line 549
     __cil_tmp29 = & dev_priv->ring;
 #line 549
     __cil_tmp30 = (struct intel_ring_buffer *)__cil_tmp29;
 #line 549
     __cil_tmp31 = dev_priv->back_offset;
 #line 549
     __cil_tmp32 = (u32 )__cil_tmp31;
 #line 549
     intel_ring_emit(__cil_tmp30, __cil_tmp32);
 #line 550
     dev_priv->current_page = 1;
     }
   } else {
     {
 #line 552
     __cil_tmp33 = & dev_priv->ring;
 #line 552
     __cil_tmp34 = (struct intel_ring_buffer *)__cil_tmp33;
 #line 552
     __cil_tmp35 = dev_priv->front_offset;
 #line 552
     __cil_tmp36 = (u32 )__cil_tmp35;
 #line 552
     intel_ring_emit(__cil_tmp34, __cil_tmp36);
 #line 553
     dev_priv->current_page = 0;
     }
   }
   }
   {
 #line 555
   __cil_tmp37 = & dev_priv->ring;
 #line 555
   __cil_tmp38 = (struct intel_ring_buffer *)__cil_tmp37;
 #line 555
   intel_ring_emit(__cil_tmp38, 0U);
 #line 557
   __cil_tmp39 = & dev_priv->ring;
 #line 557
   __cil_tmp40 = (struct intel_ring_buffer *)__cil_tmp39;
 #line 557
   intel_ring_emit(__cil_tmp40, 25165828U);
 #line 558
   __cil_tmp41 = & dev_priv->ring;
 #line 558
   __cil_tmp42 = (struct intel_ring_buffer *)__cil_tmp41;
 #line 558
   intel_ring_emit(__cil_tmp42, 0U);
 #line 560
   __cil_tmp43 = & dev_priv->ring;
 #line 560
   __cil_tmp44 = (struct intel_ring_buffer *)__cil_tmp43;
 #line 560
   intel_ring_advance(__cil_tmp44);
 #line 562
   tmp = dev_priv->counter;
 #line 562
   __cil_tmp45 = dev_priv->counter;
 #line 562
   dev_priv->counter = __cil_tmp45 + 1U;
 #line 562
   __cil_tmp46 = master_priv->sarea_priv;
 #line 562
   __cil_tmp46->last_enqueue = (int )tmp;
 #line 564
   __cil_tmp47 = & dev_priv->ring;
 #line 564
   __cil_tmp48 = (struct intel_ring_buffer *)__cil_tmp47;
 #line 564
   tmp___0 = intel_ring_begin(__cil_tmp48, 4);
   }
 #line 564
   if (tmp___0 == 0) {
     {
 #line 565
     __cil_tmp49 = & dev_priv->ring;
 #line 565
     __cil_tmp50 = (struct intel_ring_buffer *)__cil_tmp49;
 #line 565
     intel_ring_emit(__cil_tmp50, 276824065U);
 #line 566
     __cil_tmp51 = & dev_priv->ring;
 #line 566
     __cil_tmp52 = (struct intel_ring_buffer *)__cil_tmp51;
 #line 566
     intel_ring_emit(__cil_tmp52, 132U);
 #line 567
     __cil_tmp53 = & dev_priv->ring;
 #line 567
     __cil_tmp54 = (struct intel_ring_buffer *)__cil_tmp53;
 #line 567
     __cil_tmp55 = dev_priv->counter;
 #line 567
     intel_ring_emit(__cil_tmp54, __cil_tmp55);
 #line 568
     __cil_tmp56 = & dev_priv->ring;
 #line 568
     __cil_tmp57 = (struct intel_ring_buffer *)__cil_tmp56;
 #line 568
     intel_ring_emit(__cil_tmp57, 0U);
 #line 569
     __cil_tmp58 = & dev_priv->ring;
 #line 569
     __cil_tmp59 = (struct intel_ring_buffer *)__cil_tmp58;
 #line 569
     intel_ring_advance(__cil_tmp59);
     }
   } else {
 
   }
 #line 572
   __cil_tmp60 = master_priv->sarea_priv;
 #line 572
   __cil_tmp60->pf_current_page = dev_priv->current_page;
 #line 573
   return (0);
 }
 }
 #line 576 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_quiescent(struct drm_device *dev ) 
 { struct intel_ring_buffer *ring ;
   int tmp ;
   void *__cil_tmp4 ;
   struct drm_i915_private *__cil_tmp5 ;
   struct intel_ring_buffer (*__cil_tmp6)[3U] ;
 
   {
   {
 #line 578
   __cil_tmp4 = dev->dev_private;
 #line 578
   __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
 #line 578
   __cil_tmp6 = & __cil_tmp5->ring;
 #line 578
   ring = (struct intel_ring_buffer *)__cil_tmp6;
 #line 580
   i915_kernel_lost_context(dev);
 #line 581
   tmp = intel_wait_ring_idle(ring);
   }
 #line 581
   return (tmp);
 }
 }
 #line 584 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_flush_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { int ret ;
   struct drm_i915_gem_object *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_ring_buffer (*__cil_tmp9)[3U] ;
   struct intel_ring_buffer *__cil_tmp10 ;
   struct drm_i915_gem_object *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_master *__cil_tmp13 ;
   struct drm_hw_lock *__cil_tmp14 ;
   unsigned int volatile   __cil_tmp15 ;
   int __cil_tmp16 ;
   struct drm_master *__cil_tmp17 ;
   struct drm_hw_lock *__cil_tmp18 ;
   unsigned int volatile   __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   struct drm_master *__cil_tmp22 ;
   struct drm_file *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct drm_master *__cil_tmp25 ;
   struct drm_file *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct drm_master *__cil_tmp28 ;
   struct drm_hw_lock *__cil_tmp29 ;
   unsigned int volatile   __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   struct drm_master *__cil_tmp33 ;
   struct drm_file *__cil_tmp34 ;
   struct mutex *__cil_tmp35 ;
   struct mutex *__cil_tmp36 ;
 
   {
   {
 #line 589
   __cil_tmp5 = (struct drm_i915_gem_object *)0;
 #line 589
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 589
   __cil_tmp7 = dev->dev_private;
 #line 589
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 589
   __cil_tmp9 = & __cil_tmp8->ring;
 #line 589
   __cil_tmp10 = (struct intel_ring_buffer *)__cil_tmp9;
 #line 589
   __cil_tmp11 = __cil_tmp10->obj;
 #line 589
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 589
   if (__cil_tmp12 == __cil_tmp6) {
     {
 #line 589
     __cil_tmp13 = file_priv->master;
 #line 589
     __cil_tmp14 = __cil_tmp13->lock.hw_lock;
 #line 589
     __cil_tmp15 = __cil_tmp14->lock;
 #line 589
     __cil_tmp16 = (int )__cil_tmp15;
 #line 589
     if (__cil_tmp16 >= 0) {
       {
 #line 589
       __cil_tmp17 = file_priv->master;
 #line 589
       __cil_tmp18 = __cil_tmp17->lock.hw_lock;
 #line 589
       __cil_tmp19 = __cil_tmp18->lock;
 #line 589
       __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 589
       __cil_tmp21 = __cil_tmp20 & 2147483648U;
 #line 589
       __cil_tmp22 = file_priv->master;
 #line 589
       __cil_tmp23 = __cil_tmp22->lock.file_priv;
 #line 589
       drm_err("i915_flush_ioctl", "%s called without lock held, held  %d owner %p %p\n",
               "i915_flush_ioctl", __cil_tmp21, __cil_tmp23, file_priv);
       }
 #line 589
       return (-22);
     } else {
       {
 #line 589
       __cil_tmp24 = (unsigned long )file_priv;
 #line 589
       __cil_tmp25 = file_priv->master;
 #line 589
       __cil_tmp26 = __cil_tmp25->lock.file_priv;
 #line 589
       __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 589
       if (__cil_tmp27 != __cil_tmp24) {
         {
 #line 589
         __cil_tmp28 = file_priv->master;
 #line 589
         __cil_tmp29 = __cil_tmp28->lock.hw_lock;
 #line 589
         __cil_tmp30 = __cil_tmp29->lock;
 #line 589
         __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 589
         __cil_tmp32 = __cil_tmp31 & 2147483648U;
 #line 589
         __cil_tmp33 = file_priv->master;
 #line 589
         __cil_tmp34 = __cil_tmp33->lock.file_priv;
 #line 589
         drm_err("i915_flush_ioctl", "%s called without lock held, held  %d owner %p %p\n",
                 "i915_flush_ioctl", __cil_tmp32, __cil_tmp34, file_priv);
         }
 #line 589
         return (-22);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 591
   __cil_tmp35 = & dev->struct_mutex;
 #line 591
   mutex_lock_nested(__cil_tmp35, 0U);
 #line 592
   ret = i915_quiescent(dev);
 #line 593
   __cil_tmp36 = & dev->struct_mutex;
 #line 593
   mutex_unlock(__cil_tmp36);
   }
 #line 595
   return (ret);
 }
 }
 #line 598 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_batchbuffer(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   drm_i915_sarea_t *sarea_priv ;
   drm_i915_batchbuffer_t *batch ;
   int ret ;
   struct drm_clip_rect *cliprects ;
   void *tmp ;
   unsigned long tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp13 ;
   struct drm_minor *__cil_tmp14 ;
   struct drm_master *__cil_tmp15 ;
   void *__cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   struct drm_i915_gem_object *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_ring_buffer (*__cil_tmp25)[3U] ;
   struct intel_ring_buffer *__cil_tmp26 ;
   struct drm_i915_gem_object *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_master *__cil_tmp29 ;
   struct drm_hw_lock *__cil_tmp30 ;
   unsigned int volatile   __cil_tmp31 ;
   int __cil_tmp32 ;
   struct drm_master *__cil_tmp33 ;
   struct drm_hw_lock *__cil_tmp34 ;
   unsigned int volatile   __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   struct drm_master *__cil_tmp38 ;
   struct drm_file *__cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   struct drm_master *__cil_tmp41 ;
   struct drm_file *__cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   struct drm_master *__cil_tmp44 ;
   struct drm_hw_lock *__cil_tmp45 ;
   unsigned int volatile   __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   struct drm_master *__cil_tmp49 ;
   struct drm_file *__cil_tmp50 ;
   int __cil_tmp51 ;
   int __cil_tmp52 ;
   int __cil_tmp53 ;
   size_t __cil_tmp54 ;
   struct drm_clip_rect *__cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   void *__cil_tmp58 ;
   struct drm_clip_rect *__cil_tmp59 ;
   void const   *__cil_tmp60 ;
   int __cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   unsigned long __cil_tmp63 ;
   struct mutex *__cil_tmp64 ;
   struct mutex *__cil_tmp65 ;
   drm_i915_sarea_t *__cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   struct intel_ring_buffer (*__cil_tmp69)[3U] ;
   struct intel_ring_buffer *__cil_tmp70 ;
   void const   *__cil_tmp71 ;
 
   {
 #line 601
   __cil_tmp13 = dev->dev_private;
 #line 601
   dev_priv = (drm_i915_private_t *)__cil_tmp13;
 #line 602
   __cil_tmp14 = dev->primary;
 #line 602
   __cil_tmp15 = __cil_tmp14->master;
 #line 602
   __cil_tmp16 = __cil_tmp15->driver_priv;
 #line 602
   master_priv = (struct drm_i915_master_private *)__cil_tmp16;
 #line 603
   sarea_priv = master_priv->sarea_priv;
 #line 605
   batch = (drm_i915_batchbuffer_t *)data;
 #line 607
   cliprects = (struct drm_clip_rect *)0;
   {
 #line 609
   __cil_tmp17 = dev_priv->allow_batchbuffer;
 #line 609
   if (__cil_tmp17 == 0) {
     {
 #line 610
     drm_err("i915_batchbuffer", "Batchbuffer ioctl disabled\n");
     }
 #line 611
     return (-22);
   } else {
 
   }
   }
   {
 #line 614
   __cil_tmp18 = batch->start;
 #line 614
   __cil_tmp19 = batch->used;
 #line 614
   __cil_tmp20 = batch->num_cliprects;
 #line 614
   drm_ut_debug_printk(2U, "drm", "i915_batchbuffer", "i915 batchbuffer, start %x used %d cliprects %d\n",
                       __cil_tmp18, __cil_tmp19, __cil_tmp20);
   }
   {
 #line 617
   __cil_tmp21 = (struct drm_i915_gem_object *)0;
 #line 617
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 617
   __cil_tmp23 = dev->dev_private;
 #line 617
   __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 617
   __cil_tmp25 = & __cil_tmp24->ring;
 #line 617
   __cil_tmp26 = (struct intel_ring_buffer *)__cil_tmp25;
 #line 617
   __cil_tmp27 = __cil_tmp26->obj;
 #line 617
   __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 617
   if (__cil_tmp28 == __cil_tmp22) {
     {
 #line 617
     __cil_tmp29 = file_priv->master;
 #line 617
     __cil_tmp30 = __cil_tmp29->lock.hw_lock;
 #line 617
     __cil_tmp31 = __cil_tmp30->lock;
 #line 617
     __cil_tmp32 = (int )__cil_tmp31;
 #line 617
     if (__cil_tmp32 >= 0) {
       {
 #line 617
       __cil_tmp33 = file_priv->master;
 #line 617
       __cil_tmp34 = __cil_tmp33->lock.hw_lock;
 #line 617
       __cil_tmp35 = __cil_tmp34->lock;
 #line 617
       __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 617
       __cil_tmp37 = __cil_tmp36 & 2147483648U;
 #line 617
       __cil_tmp38 = file_priv->master;
 #line 617
       __cil_tmp39 = __cil_tmp38->lock.file_priv;
 #line 617
       drm_err("i915_batchbuffer", "%s called without lock held, held  %d owner %p %p\n",
               "i915_batchbuffer", __cil_tmp37, __cil_tmp39, file_priv);
       }
 #line 617
       return (-22);
     } else {
       {
 #line 617
       __cil_tmp40 = (unsigned long )file_priv;
 #line 617
       __cil_tmp41 = file_priv->master;
 #line 617
       __cil_tmp42 = __cil_tmp41->lock.file_priv;
 #line 617
       __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 617
       if (__cil_tmp43 != __cil_tmp40) {
         {
 #line 617
         __cil_tmp44 = file_priv->master;
 #line 617
         __cil_tmp45 = __cil_tmp44->lock.hw_lock;
 #line 617
         __cil_tmp46 = __cil_tmp45->lock;
 #line 617
         __cil_tmp47 = (unsigned int )__cil_tmp46;
 #line 617
         __cil_tmp48 = __cil_tmp47 & 2147483648U;
 #line 617
         __cil_tmp49 = file_priv->master;
 #line 617
         __cil_tmp50 = __cil_tmp49->lock.file_priv;
 #line 617
         drm_err("i915_batchbuffer", "%s called without lock held, held  %d owner %p %p\n",
                 "i915_batchbuffer", __cil_tmp48, __cil_tmp50, file_priv);
         }
 #line 617
         return (-22);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 619
   __cil_tmp51 = batch->num_cliprects;
 #line 619
   if (__cil_tmp51 < 0) {
 #line 620
     return (-22);
   } else {
 
   }
   }
   {
 #line 622
   __cil_tmp52 = batch->num_cliprects;
 #line 622
   if (__cil_tmp52 != 0) {
     {
 #line 623
     __cil_tmp53 = batch->num_cliprects;
 #line 623
     __cil_tmp54 = (size_t )__cil_tmp53;
 #line 623
     tmp = kcalloc(__cil_tmp54, 8UL, 208U);
 #line 623
     cliprects = (struct drm_clip_rect *)tmp;
     }
     {
 #line 626
     __cil_tmp55 = (struct drm_clip_rect *)0;
 #line 626
     __cil_tmp56 = (unsigned long )__cil_tmp55;
 #line 626
     __cil_tmp57 = (unsigned long )cliprects;
 #line 626
     if (__cil_tmp57 == __cil_tmp56) {
 #line 627
       return (-12);
     } else {
 
     }
     }
     {
 #line 629
     __cil_tmp58 = (void *)cliprects;
 #line 629
     __cil_tmp59 = batch->cliprects;
 #line 629
     __cil_tmp60 = (void const   *)__cil_tmp59;
 #line 629
     __cil_tmp61 = batch->num_cliprects;
 #line 629
     __cil_tmp62 = (unsigned long )__cil_tmp61;
 #line 629
     __cil_tmp63 = __cil_tmp62 * 8UL;
 #line 629
     tmp___0 = copy_from_user(__cil_tmp58, __cil_tmp60, __cil_tmp63);
 #line 629
     ret = (int )tmp___0;
     }
 #line 632
     if (ret != 0) {
 #line 633
       ret = -14;
 #line 634
       goto fail_free;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 638
   __cil_tmp64 = & dev->struct_mutex;
 #line 638
   mutex_lock_nested(__cil_tmp64, 0U);
 #line 639
   ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 #line 640
   __cil_tmp65 = & dev->struct_mutex;
 #line 640
   mutex_unlock(__cil_tmp65);
   }
   {
 #line 642
   __cil_tmp66 = (drm_i915_sarea_t *)0;
 #line 642
   __cil_tmp67 = (unsigned long )__cil_tmp66;
 #line 642
   __cil_tmp68 = (unsigned long )sarea_priv;
 #line 642
   if (__cil_tmp68 != __cil_tmp67) {
     {
 #line 643
     __cil_tmp69 = & dev_priv->ring;
 #line 643
     __cil_tmp70 = (struct intel_ring_buffer *)__cil_tmp69;
 #line 643
     tmp___1 = intel_read_status_page(__cil_tmp70, 33);
 #line 643
     sarea_priv->last_dispatch = (int )tmp___1;
     }
   } else {
 
   }
   }
   fail_free: 
   {
 #line 646
   __cil_tmp71 = (void const   *)cliprects;
 #line 646
   kfree(__cil_tmp71);
   }
 #line 648
   return (ret);
 }
 }
 #line 651 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_cmdbuffer(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   drm_i915_sarea_t *sarea_priv ;
   drm_i915_cmdbuffer_t *cmdbuf ;
   struct drm_clip_rect *cliprects ;
   void *batch_data ;
   int ret ;
   unsigned long tmp ;
   void *tmp___0 ;
   unsigned long tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp15 ;
   struct drm_minor *__cil_tmp16 ;
   struct drm_master *__cil_tmp17 ;
   void *__cil_tmp18 ;
   char *__cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   struct drm_i915_gem_object *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_ring_buffer (*__cil_tmp26)[3U] ;
   struct intel_ring_buffer *__cil_tmp27 ;
   struct drm_i915_gem_object *__cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   struct drm_master *__cil_tmp30 ;
   struct drm_hw_lock *__cil_tmp31 ;
   unsigned int volatile   __cil_tmp32 ;
   int __cil_tmp33 ;
   struct drm_master *__cil_tmp34 ;
   struct drm_hw_lock *__cil_tmp35 ;
   unsigned int volatile   __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   struct drm_master *__cil_tmp39 ;
   struct drm_file *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   struct drm_master *__cil_tmp42 ;
   struct drm_file *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   struct drm_master *__cil_tmp45 ;
   struct drm_hw_lock *__cil_tmp46 ;
   unsigned int volatile   __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   struct drm_master *__cil_tmp50 ;
   struct drm_file *__cil_tmp51 ;
   int __cil_tmp52 ;
   int __cil_tmp53 ;
   size_t __cil_tmp54 ;
   void *__cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   char *__cil_tmp58 ;
   void const   *__cil_tmp59 ;
   int __cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   int __cil_tmp62 ;
   int __cil_tmp63 ;
   size_t __cil_tmp64 ;
   struct drm_clip_rect *__cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   void *__cil_tmp68 ;
   struct drm_clip_rect *__cil_tmp69 ;
   void const   *__cil_tmp70 ;
   int __cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   unsigned long __cil_tmp73 ;
   struct mutex *__cil_tmp74 ;
   struct mutex *__cil_tmp75 ;
   drm_i915_sarea_t *__cil_tmp76 ;
   unsigned long __cil_tmp77 ;
   unsigned long __cil_tmp78 ;
   struct intel_ring_buffer (*__cil_tmp79)[3U] ;
   struct intel_ring_buffer *__cil_tmp80 ;
   void const   *__cil_tmp81 ;
   void const   *__cil_tmp82 ;
 
   {
   {
 #line 654
   __cil_tmp15 = dev->dev_private;
 #line 654
   dev_priv = (drm_i915_private_t *)__cil_tmp15;
 #line 655
   __cil_tmp16 = dev->primary;
 #line 655
   __cil_tmp17 = __cil_tmp16->master;
 #line 655
   __cil_tmp18 = __cil_tmp17->driver_priv;
 #line 655
   master_priv = (struct drm_i915_master_private *)__cil_tmp18;
 #line 656
   sarea_priv = master_priv->sarea_priv;
 #line 658
   cmdbuf = (drm_i915_cmdbuffer_t *)data;
 #line 659
   cliprects = (struct drm_clip_rect *)0;
 #line 663
   __cil_tmp19 = cmdbuf->buf;
 #line 663
   __cil_tmp20 = cmdbuf->sz;
 #line 663
   __cil_tmp21 = cmdbuf->num_cliprects;
 #line 663
   drm_ut_debug_printk(2U, "drm", "i915_cmdbuffer", "i915 cmdbuffer, buf %p sz %d cliprects %d\n",
                       __cil_tmp19, __cil_tmp20, __cil_tmp21);
   }
   {
 #line 666
   __cil_tmp22 = (struct drm_i915_gem_object *)0;
 #line 666
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 666
   __cil_tmp24 = dev->dev_private;
 #line 666
   __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 666
   __cil_tmp26 = & __cil_tmp25->ring;
 #line 666
   __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
 #line 666
   __cil_tmp28 = __cil_tmp27->obj;
 #line 666
   __cil_tmp29 = (unsigned long )__cil_tmp28;
 #line 666
   if (__cil_tmp29 == __cil_tmp23) {
     {
 #line 666
     __cil_tmp30 = file_priv->master;
 #line 666
     __cil_tmp31 = __cil_tmp30->lock.hw_lock;
 #line 666
     __cil_tmp32 = __cil_tmp31->lock;
 #line 666
     __cil_tmp33 = (int )__cil_tmp32;
 #line 666
     if (__cil_tmp33 >= 0) {
       {
 #line 666
       __cil_tmp34 = file_priv->master;
 #line 666
       __cil_tmp35 = __cil_tmp34->lock.hw_lock;
 #line 666
       __cil_tmp36 = __cil_tmp35->lock;
 #line 666
       __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 666
       __cil_tmp38 = __cil_tmp37 & 2147483648U;
 #line 666
       __cil_tmp39 = file_priv->master;
 #line 666
       __cil_tmp40 = __cil_tmp39->lock.file_priv;
 #line 666
       drm_err("i915_cmdbuffer", "%s called without lock held, held  %d owner %p %p\n",
               "i915_cmdbuffer", __cil_tmp38, __cil_tmp40, file_priv);
       }
 #line 666
       return (-22);
     } else {
       {
 #line 666
       __cil_tmp41 = (unsigned long )file_priv;
 #line 666
       __cil_tmp42 = file_priv->master;
 #line 666
       __cil_tmp43 = __cil_tmp42->lock.file_priv;
 #line 666
       __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 666
       if (__cil_tmp44 != __cil_tmp41) {
         {
 #line 666
         __cil_tmp45 = file_priv->master;
 #line 666
         __cil_tmp46 = __cil_tmp45->lock.hw_lock;
 #line 666
         __cil_tmp47 = __cil_tmp46->lock;
 #line 666
         __cil_tmp48 = (unsigned int )__cil_tmp47;
 #line 666
         __cil_tmp49 = __cil_tmp48 & 2147483648U;
 #line 666
         __cil_tmp50 = file_priv->master;
 #line 666
         __cil_tmp51 = __cil_tmp50->lock.file_priv;
 #line 666
         drm_err("i915_cmdbuffer", "%s called without lock held, held  %d owner %p %p\n",
                 "i915_cmdbuffer", __cil_tmp49, __cil_tmp51, file_priv);
         }
 #line 666
         return (-22);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 668
   __cil_tmp52 = cmdbuf->num_cliprects;
 #line 668
   if (__cil_tmp52 < 0) {
 #line 669
     return (-22);
   } else {
 
   }
   }
   {
 #line 671
   __cil_tmp53 = cmdbuf->sz;
 #line 671
   __cil_tmp54 = (size_t )__cil_tmp53;
 #line 671
   batch_data = kmalloc(__cil_tmp54, 208U);
   }
   {
 #line 672
   __cil_tmp55 = (void *)0;
 #line 672
   __cil_tmp56 = (unsigned long )__cil_tmp55;
 #line 672
   __cil_tmp57 = (unsigned long )batch_data;
 #line 672
   if (__cil_tmp57 == __cil_tmp56) {
 #line 673
     return (-12);
   } else {
 
   }
   }
   {
 #line 675
   __cil_tmp58 = cmdbuf->buf;
 #line 675
   __cil_tmp59 = (void const   *)__cil_tmp58;
 #line 675
   __cil_tmp60 = cmdbuf->sz;
 #line 675
   __cil_tmp61 = (unsigned long )__cil_tmp60;
 #line 675
   tmp = copy_from_user(batch_data, __cil_tmp59, __cil_tmp61);
 #line 675
   ret = (int )tmp;
   }
 #line 676
   if (ret != 0) {
 #line 677
     ret = -14;
 #line 678
     goto fail_batch_free;
   } else {
 
   }
   {
 #line 681
   __cil_tmp62 = cmdbuf->num_cliprects;
 #line 681
   if (__cil_tmp62 != 0) {
     {
 #line 682
     __cil_tmp63 = cmdbuf->num_cliprects;
 #line 682
     __cil_tmp64 = (size_t )__cil_tmp63;
 #line 682
     tmp___0 = kcalloc(__cil_tmp64, 8UL, 208U);
 #line 682
     cliprects = (struct drm_clip_rect *)tmp___0;
     }
     {
 #line 684
     __cil_tmp65 = (struct drm_clip_rect *)0;
 #line 684
     __cil_tmp66 = (unsigned long )__cil_tmp65;
 #line 684
     __cil_tmp67 = (unsigned long )cliprects;
 #line 684
     if (__cil_tmp67 == __cil_tmp66) {
 #line 685
       ret = -12;
 #line 686
       goto fail_batch_free;
     } else {
 
     }
     }
     {
 #line 689
     __cil_tmp68 = (void *)cliprects;
 #line 689
     __cil_tmp69 = cmdbuf->cliprects;
 #line 689
     __cil_tmp70 = (void const   *)__cil_tmp69;
 #line 689
     __cil_tmp71 = cmdbuf->num_cliprects;
 #line 689
     __cil_tmp72 = (unsigned long )__cil_tmp71;
 #line 689
     __cil_tmp73 = __cil_tmp72 * 8UL;
 #line 689
     tmp___1 = copy_from_user(__cil_tmp68, __cil_tmp70, __cil_tmp73);
 #line 689
     ret = (int )tmp___1;
     }
 #line 692
     if (ret != 0) {
 #line 693
       ret = -14;
 #line 694
       goto fail_clip_free;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 698
   __cil_tmp74 = & dev->struct_mutex;
 #line 698
   mutex_lock_nested(__cil_tmp74, 0U);
 #line 699
   ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 #line 700
   __cil_tmp75 = & dev->struct_mutex;
 #line 700
   mutex_unlock(__cil_tmp75);
   }
 #line 701
   if (ret != 0) {
     {
 #line 702
     drm_err("i915_cmdbuffer", "i915_dispatch_cmdbuffer failed\n");
     }
 #line 703
     goto fail_clip_free;
   } else {
 
   }
   {
 #line 706
   __cil_tmp76 = (drm_i915_sarea_t *)0;
 #line 706
   __cil_tmp77 = (unsigned long )__cil_tmp76;
 #line 706
   __cil_tmp78 = (unsigned long )sarea_priv;
 #line 706
   if (__cil_tmp78 != __cil_tmp77) {
     {
 #line 707
     __cil_tmp79 = & dev_priv->ring;
 #line 707
     __cil_tmp80 = (struct intel_ring_buffer *)__cil_tmp79;
 #line 707
     tmp___2 = intel_read_status_page(__cil_tmp80, 33);
 #line 707
     sarea_priv->last_dispatch = (int )tmp___2;
     }
   } else {
 
   }
   }
   fail_clip_free: 
   {
 #line 710
   __cil_tmp81 = (void const   *)cliprects;
 #line 710
   kfree(__cil_tmp81);
   }
   fail_batch_free: 
   {
 #line 712
   __cil_tmp82 = (void const   *)batch_data;
 #line 712
   kfree(__cil_tmp82);
   }
 #line 714
   return (ret);
 }
 }
 #line 717 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_flip_bufs(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { int ret ;
   struct drm_i915_gem_object *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_ring_buffer (*__cil_tmp9)[3U] ;
   struct intel_ring_buffer *__cil_tmp10 ;
   struct drm_i915_gem_object *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_master *__cil_tmp13 ;
   struct drm_hw_lock *__cil_tmp14 ;
   unsigned int volatile   __cil_tmp15 ;
   int __cil_tmp16 ;
   struct drm_master *__cil_tmp17 ;
   struct drm_hw_lock *__cil_tmp18 ;
   unsigned int volatile   __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   struct drm_master *__cil_tmp22 ;
   struct drm_file *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct drm_master *__cil_tmp25 ;
   struct drm_file *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct drm_master *__cil_tmp28 ;
   struct drm_hw_lock *__cil_tmp29 ;
   unsigned int volatile   __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   struct drm_master *__cil_tmp33 ;
   struct drm_file *__cil_tmp34 ;
   struct mutex *__cil_tmp35 ;
   struct mutex *__cil_tmp36 ;
 
   {
   {
 #line 722
   drm_ut_debug_printk(2U, "drm", "i915_flip_bufs", "%s\n", "i915_flip_bufs");
   }
   {
 #line 724
   __cil_tmp5 = (struct drm_i915_gem_object *)0;
 #line 724
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 724
   __cil_tmp7 = dev->dev_private;
 #line 724
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 724
   __cil_tmp9 = & __cil_tmp8->ring;
 #line 724
   __cil_tmp10 = (struct intel_ring_buffer *)__cil_tmp9;
 #line 724
   __cil_tmp11 = __cil_tmp10->obj;
 #line 724
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 724
   if (__cil_tmp12 == __cil_tmp6) {
     {
 #line 724
     __cil_tmp13 = file_priv->master;
 #line 724
     __cil_tmp14 = __cil_tmp13->lock.hw_lock;
 #line 724
     __cil_tmp15 = __cil_tmp14->lock;
 #line 724
     __cil_tmp16 = (int )__cil_tmp15;
 #line 724
     if (__cil_tmp16 >= 0) {
       {
 #line 724
       __cil_tmp17 = file_priv->master;
 #line 724
       __cil_tmp18 = __cil_tmp17->lock.hw_lock;
 #line 724
       __cil_tmp19 = __cil_tmp18->lock;
 #line 724
       __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 724
       __cil_tmp21 = __cil_tmp20 & 2147483648U;
 #line 724
       __cil_tmp22 = file_priv->master;
 #line 724
       __cil_tmp23 = __cil_tmp22->lock.file_priv;
 #line 724
       drm_err("i915_flip_bufs", "%s called without lock held, held  %d owner %p %p\n",
               "i915_flip_bufs", __cil_tmp21, __cil_tmp23, file_priv);
       }
 #line 724
       return (-22);
     } else {
       {
 #line 724
       __cil_tmp24 = (unsigned long )file_priv;
 #line 724
       __cil_tmp25 = file_priv->master;
 #line 724
       __cil_tmp26 = __cil_tmp25->lock.file_priv;
 #line 724
       __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 724
       if (__cil_tmp27 != __cil_tmp24) {
         {
 #line 724
         __cil_tmp28 = file_priv->master;
 #line 724
         __cil_tmp29 = __cil_tmp28->lock.hw_lock;
 #line 724
         __cil_tmp30 = __cil_tmp29->lock;
 #line 724
         __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 724
         __cil_tmp32 = __cil_tmp31 & 2147483648U;
 #line 724
         __cil_tmp33 = file_priv->master;
 #line 724
         __cil_tmp34 = __cil_tmp33->lock.file_priv;
 #line 724
         drm_err("i915_flip_bufs", "%s called without lock held, held  %d owner %p %p\n",
                 "i915_flip_bufs", __cil_tmp32, __cil_tmp34, file_priv);
         }
 #line 724
         return (-22);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 726
   __cil_tmp35 = & dev->struct_mutex;
 #line 726
   mutex_lock_nested(__cil_tmp35, 0U);
 #line 727
   ret = i915_dispatch_flip(dev);
 #line 728
   __cil_tmp36 = & dev->struct_mutex;
 #line 728
   mutex_unlock(__cil_tmp36);
   }
 #line 730
   return (ret);
 }
 }
 #line 733 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_getparam(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_getparam_t *param ;
   int value ;
   u32 tmp ;
   int tmp___0 ;
   void *__cil_tmp9 ;
   drm_i915_private_t *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   struct pci_dev *__cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   int __cil_tmp30 ;
   struct intel_ring_buffer (*__cil_tmp31)[3U] ;
   struct intel_ring_buffer *__cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   struct intel_overlay *__cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   struct intel_overlay *__cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   void *__cil_tmp39 ;
   struct drm_i915_private *__cil_tmp40 ;
   struct intel_device_info  const  *__cil_tmp41 ;
   unsigned char __cil_tmp42 ;
   void *__cil_tmp43 ;
   struct drm_i915_private *__cil_tmp44 ;
   struct intel_device_info  const  *__cil_tmp45 ;
   unsigned char __cil_tmp46 ;
   void *__cil_tmp47 ;
   struct drm_i915_private *__cil_tmp48 ;
   struct intel_device_info  const  *__cil_tmp49 ;
   u8 __cil_tmp50 ;
   unsigned char __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   int __cil_tmp53 ;
   int *__cil_tmp54 ;
   void *__cil_tmp55 ;
   void const   *__cil_tmp56 ;
 
   {
 #line 736
   __cil_tmp9 = dev->dev_private;
 #line 736
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 737
   param = (drm_i915_getparam_t *)data;
   {
 #line 740
   __cil_tmp10 = (drm_i915_private_t *)0;
 #line 740
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 740
   __cil_tmp12 = (unsigned long )dev_priv;
 #line 740
   if (__cil_tmp12 == __cil_tmp11) {
     {
 #line 741
     drm_err("i915_getparam", "called with no initialization\n");
     }
 #line 742
     return (-22);
   } else {
 
   }
   }
   {
 #line 746
   __cil_tmp13 = param->param;
 #line 746
   if (__cil_tmp13 == 1) {
 #line 746
     goto case_1;
   } else {
     {
 #line 749
     __cil_tmp14 = param->param;
 #line 749
     if (__cil_tmp14 == 2) {
 #line 749
       goto case_2;
     } else {
       {
 #line 752
       __cil_tmp15 = param->param;
 #line 752
       if (__cil_tmp15 == 3) {
 #line 752
         goto case_3;
       } else {
         {
 #line 755
         __cil_tmp16 = param->param;
 #line 755
         if (__cil_tmp16 == 4) {
 #line 755
           goto case_4;
         } else {
           {
 #line 758
           __cil_tmp17 = param->param;
 #line 758
           if (__cil_tmp17 == 5) {
 #line 758
             goto case_5;
           } else {
             {
 #line 761
             __cil_tmp18 = param->param;
 #line 761
             if (__cil_tmp18 == 6) {
 #line 761
               goto case_6;
             } else {
               {
 #line 764
               __cil_tmp19 = param->param;
 #line 764
               if (__cil_tmp19 == 7) {
 #line 764
                 goto case_7;
               } else {
                 {
 #line 767
                 __cil_tmp20 = param->param;
 #line 767
                 if (__cil_tmp20 == 8) {
 #line 767
                   goto case_8;
                 } else {
                   {
 #line 770
                   __cil_tmp21 = param->param;
 #line 770
                   if (__cil_tmp21 == 9) {
 #line 770
                     goto case_9;
                   } else {
                     {
 #line 774
                     __cil_tmp22 = param->param;
 #line 774
                     if (__cil_tmp22 == 10) {
 #line 774
                       goto case_10;
                     } else {
                       {
 #line 777
                       __cil_tmp23 = param->param;
 #line 777
                       if (__cil_tmp23 == 11) {
 #line 777
                         goto case_11;
                       } else {
                         {
 #line 780
                         __cil_tmp24 = param->param;
 #line 780
                         if (__cil_tmp24 == 12) {
 #line 780
                           goto case_12;
                         } else {
                           {
 #line 783
                           __cil_tmp25 = param->param;
 #line 783
                           if (__cil_tmp25 == 13) {
 #line 783
                             goto case_13;
                           } else {
                             {
 #line 786
                             __cil_tmp26 = param->param;
 #line 786
                             if (__cil_tmp26 == 14) {
 #line 786
                               goto case_14;
                             } else {
                               {
 #line 789
                               __cil_tmp27 = param->param;
 #line 789
                               if (__cil_tmp27 == 15) {
 #line 789
                                 goto case_15;
                               } else {
 #line 792
                                 goto switch_default;
 #line 745
                                 if (0) {
                                   case_1: 
 #line 747
                                   __cil_tmp28 = dev->pdev;
 #line 747
                                   __cil_tmp29 = __cil_tmp28->irq;
 #line 747
                                   value = __cil_tmp29 != 0U;
 #line 748
                                   goto ldv_40460;
                                   case_2: 
 #line 750
                                   __cil_tmp30 = dev_priv->allow_batchbuffer;
 #line 750
                                   value = __cil_tmp30 != 0;
 #line 751
                                   goto ldv_40460;
                                   case_3: 
                                   {
 #line 753
                                   __cil_tmp31 = & dev_priv->ring;
 #line 753
                                   __cil_tmp32 = (struct intel_ring_buffer *)__cil_tmp31;
 #line 753
                                   tmp = intel_read_status_page(__cil_tmp32, 33);
 #line 753
                                   value = (int )tmp;
                                   }
 #line 754
                                   goto ldv_40460;
                                   case_4: 
 #line 756
                                   value = dev->pci_device;
 #line 757
                                   goto ldv_40460;
                                   case_5: 
 #line 759
                                   value = dev_priv->has_gem;
 #line 760
                                   goto ldv_40460;
                                   case_6: 
 #line 762
                                   __cil_tmp33 = dev_priv->fence_reg_start;
 #line 762
                                   __cil_tmp34 = dev_priv->num_fence_regs;
 #line 762
                                   value = __cil_tmp34 - __cil_tmp33;
 #line 763
                                   goto ldv_40460;
                                   case_7: 
 #line 765
                                   __cil_tmp35 = (struct intel_overlay *)0;
 #line 765
                                   __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 765
                                   __cil_tmp37 = dev_priv->overlay;
 #line 765
                                   __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 765
                                   value = __cil_tmp38 != __cil_tmp36;
 #line 766
                                   goto ldv_40460;
                                   case_8: 
 #line 768
                                   value = 1;
 #line 769
                                   goto ldv_40460;
                                   case_9: 
 #line 772
                                   value = dev_priv->has_gem;
 #line 773
                                   goto ldv_40460;
                                   case_10: 
 #line 775
                                   __cil_tmp39 = dev->dev_private;
 #line 775
                                   __cil_tmp40 = (struct drm_i915_private *)__cil_tmp39;
 #line 775
                                   __cil_tmp41 = __cil_tmp40->info;
 #line 775
                                   __cil_tmp42 = __cil_tmp41->has_bsd_ring;
 #line 775
                                   value = (int )__cil_tmp42;
 #line 776
                                   goto ldv_40460;
                                   case_11: 
 #line 778
                                   __cil_tmp43 = dev->dev_private;
 #line 778
                                   __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
 #line 778
                                   __cil_tmp45 = __cil_tmp44->info;
 #line 778
                                   __cil_tmp46 = __cil_tmp45->has_blt_ring;
 #line 778
                                   value = (int )__cil_tmp46;
 #line 779
                                   goto ldv_40460;
                                   case_12: 
 #line 781
                                   value = 1;
 #line 782
                                   goto ldv_40460;
                                   case_13: 
 #line 784
                                   value = 1;
 #line 785
                                   goto ldv_40460;
                                   case_14: 
 #line 787
                                   __cil_tmp47 = dev->dev_private;
 #line 787
                                   __cil_tmp48 = (struct drm_i915_private *)__cil_tmp47;
 #line 787
                                   __cil_tmp49 = __cil_tmp48->info;
 #line 787
                                   __cil_tmp50 = __cil_tmp49->gen;
 #line 787
                                   __cil_tmp51 = (unsigned char )__cil_tmp50;
 #line 787
                                   __cil_tmp52 = (unsigned int )__cil_tmp51;
 #line 787
                                   value = __cil_tmp52 > 3U;
 #line 788
                                   goto ldv_40460;
                                   case_15: 
 #line 790
                                   value = 1;
 #line 791
                                   goto ldv_40460;
                                   switch_default: 
                                   {
 #line 793
                                   __cil_tmp53 = param->param;
 #line 793
                                   drm_ut_debug_printk(2U, "drm", "i915_getparam",
                                                       "Unknown parameter %d\n", __cil_tmp53);
                                   }
 #line 795
                                   return (-22);
                                 } else {
 
                                 }
                               }
                               }
                             }
                             }
                           }
                           }
                         }
                         }
                       }
                       }
                     }
                     }
                   }
                   }
                 }
                 }
               }
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_40460: 
   {
 #line 798
   __cil_tmp54 = param->value;
 #line 798
   __cil_tmp55 = (void *)__cil_tmp54;
 #line 798
   __cil_tmp56 = (void const   *)(& value);
 #line 798
   tmp___0 = copy_to_user(__cil_tmp55, __cil_tmp56, 4U);
   }
 #line 798
   if (tmp___0 != 0) {
     {
 #line 799
     drm_err("i915_getparam", "DRM_COPY_TO_USER failed\n");
     }
 #line 800
     return (-14);
   } else {
 
   }
 #line 803
   return (0);
 }
 }
 #line 806 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_setparam(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_setparam_t *param ;
   void *__cil_tmp6 ;
   drm_i915_private_t *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
 
   {
 #line 809
   __cil_tmp6 = dev->dev_private;
 #line 809
   dev_priv = (drm_i915_private_t *)__cil_tmp6;
 #line 810
   param = (drm_i915_setparam_t *)data;
   {
 #line 812
   __cil_tmp7 = (drm_i915_private_t *)0;
 #line 812
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 812
   __cil_tmp9 = (unsigned long )dev_priv;
 #line 812
   if (__cil_tmp9 == __cil_tmp8) {
     {
 #line 813
     drm_err("i915_setparam", "called with no initialization\n");
     }
 #line 814
     return (-22);
   } else {
 
   }
   }
   {
 #line 818
   __cil_tmp10 = param->param;
 #line 818
   if (__cil_tmp10 == 1) {
 #line 818
     goto case_1;
   } else {
     {
 #line 820
     __cil_tmp11 = param->param;
 #line 820
     if (__cil_tmp11 == 2) {
 #line 820
       goto case_2;
     } else {
       {
 #line 823
       __cil_tmp12 = param->param;
 #line 823
       if (__cil_tmp12 == 3) {
 #line 823
         goto case_3;
       } else {
         {
 #line 826
         __cil_tmp13 = param->param;
 #line 826
         if (__cil_tmp13 == 4) {
 #line 826
           goto case_4;
         } else {
 #line 833
           goto switch_default;
 #line 817
           if (0) {
             case_1: ;
 #line 819
             goto ldv_40485;
             case_2: 
 #line 821
             dev_priv->tex_lru_log_granularity = param->value;
 #line 822
             goto ldv_40485;
             case_3: 
 #line 824
             dev_priv->allow_batchbuffer = param->value;
 #line 825
             goto ldv_40485;
             case_4: ;
             {
 #line 827
             __cil_tmp14 = dev_priv->num_fence_regs;
 #line 827
             __cil_tmp15 = param->value;
 #line 827
             if (__cil_tmp15 > __cil_tmp14) {
 #line 829
               return (-22);
             } else {
               {
 #line 827
               __cil_tmp16 = param->value;
 #line 827
               if (__cil_tmp16 < 0) {
 #line 829
                 return (-22);
               } else {
 
               }
               }
             }
             }
 #line 831
             dev_priv->fence_reg_start = param->value;
 #line 832
             goto ldv_40485;
             switch_default: 
             {
 #line 834
             __cil_tmp17 = param->param;
 #line 834
             drm_ut_debug_printk(2U, "drm", "i915_setparam", "unknown parameter %d\n",
                                 __cil_tmp17);
             }
 #line 836
             return (-22);
           } else {
 
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_40485: ;
 #line 839
   return (0);
 }
 }
 #line 842 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_set_status_page(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_hws_addr_t *hws ;
   struct intel_ring_buffer *ring ;
   int __ret_warn_on ;
   long tmp ;
   int tmp___0 ;
   void *__cil_tmp10 ;
   struct intel_ring_buffer (*__cil_tmp11)[3U] ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   drm_i915_private_t *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   int __cil_tmp22 ;
   long __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   long __cil_tmp27 ;
   __u64 __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   __u64 __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   __u64 __cil_tmp32 ;
   struct drm_agp_head *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   unsigned long long __cil_tmp35 ;
   drm_local_map_t *__cil_tmp36 ;
   void *__cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   void *__cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   void *__cil_tmp41 ;
   u32 *__cil_tmp42 ;
   void volatile   *__cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   u32 *__cil_tmp46 ;
 
   {
 #line 845
   __cil_tmp10 = dev->dev_private;
 #line 845
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 846
   hws = (drm_i915_hws_addr_t *)data;
 #line 847
   __cil_tmp11 = & dev_priv->ring;
 #line 847
   ring = (struct intel_ring_buffer *)__cil_tmp11;
   {
 #line 849
   __cil_tmp12 = dev->dev_private;
 #line 849
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 849
   __cil_tmp14 = __cil_tmp13->info;
 #line 849
   __cil_tmp15 = (unsigned char *)__cil_tmp14;
 #line 849
   __cil_tmp16 = __cil_tmp15 + 1UL;
 #line 849
   __cil_tmp17 = *__cil_tmp16;
 #line 849
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 849
   if (__cil_tmp18 == 0U) {
 #line 850
     return (-22);
   } else {
 
   }
   }
   {
 #line 852
   __cil_tmp19 = (drm_i915_private_t *)0;
 #line 852
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 852
   __cil_tmp21 = (unsigned long )dev_priv;
 #line 852
   if (__cil_tmp21 == __cil_tmp20) {
     {
 #line 853
     drm_err("i915_set_status_page", "called with no initialization\n");
     }
 #line 854
     return (-22);
   } else {
 
   }
   }
   {
 #line 857
   tmp___0 = drm_core_check_feature(dev, 8192);
   }
 #line 857
   if (tmp___0 != 0) {
     {
 #line 858
     __ret_warn_on = 1;
 #line 858
     __cil_tmp22 = __ret_warn_on != 0;
 #line 858
     __cil_tmp23 = (long )__cil_tmp22;
 #line 858
     tmp = __builtin_expect(__cil_tmp23, 0L);
     }
 #line 858
     if (tmp != 0L) {
       {
 #line 858
       __cil_tmp24 = (int const   )858;
 #line 858
       __cil_tmp25 = (int )__cil_tmp24;
 #line 858
       warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p",
                         __cil_tmp25, "tried to set status page when mode setting active\n");
       }
     } else {
 
     }
     {
 #line 858
     __cil_tmp26 = __ret_warn_on != 0;
 #line 858
     __cil_tmp27 = (long )__cil_tmp26;
 #line 858
     __builtin_expect(__cil_tmp27, 0L);
     }
 #line 859
     return (0);
   } else {
 
   }
   {
 #line 862
   __cil_tmp28 = hws->addr;
 #line 862
   __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 862
   drm_ut_debug_printk(2U, "drm", "i915_set_status_page", "set status page addr 0x%08x\n",
                       __cil_tmp29);
 #line 864
   __cil_tmp30 = hws->addr;
 #line 864
   __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 864
   ring->status_page.gfx_addr = __cil_tmp31 & 536866816U;
 #line 866
   __cil_tmp32 = hws->addr;
 #line 866
   __cil_tmp33 = dev->agp;
 #line 866
   __cil_tmp34 = __cil_tmp33->base;
 #line 866
   __cil_tmp35 = (unsigned long long )__cil_tmp34;
 #line 866
   dev_priv->hws_map.offset = __cil_tmp35 + __cil_tmp32;
 #line 867
   dev_priv->hws_map.size = 4096UL;
 #line 868
   dev_priv->hws_map.type = (enum drm_map_type )0;
 #line 869
   dev_priv->hws_map.flags = (enum drm_map_flags )0;
 #line 870
   dev_priv->hws_map.mtrr = 0;
 #line 872
   __cil_tmp36 = & dev_priv->hws_map;
 #line 872
   drm_core_ioremap_wc(__cil_tmp36, dev);
   }
   {
 #line 873
   __cil_tmp37 = (void *)0;
 #line 873
   __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 873
   __cil_tmp39 = dev_priv->hws_map.handle;
 #line 873
   __cil_tmp40 = (unsigned long )__cil_tmp39;
 #line 873
   if (__cil_tmp40 == __cil_tmp38) {
     {
 #line 874
     i915_dma_cleanup(dev);
 #line 875
     ring->status_page.gfx_addr = 0U;
 #line 876
     drm_err("i915_set_status_page", "can not ioremap virtual address for G33 hw status page\n");
     }
 #line 878
     return (-12);
   } else {
 
   }
   }
   {
 #line 880
   __cil_tmp41 = dev_priv->hws_map.handle;
 #line 880
   ring->status_page.page_addr = (u32 *)__cil_tmp41;
 #line 882
   __cil_tmp42 = ring->status_page.page_addr;
 #line 882
   __cil_tmp43 = (void volatile   *)__cil_tmp42;
 #line 882
   memset_io(__cil_tmp43, (unsigned char)0, 4096UL);
 #line 883
   __cil_tmp44 = ring->status_page.gfx_addr;
 #line 883
   i915_write32___0(dev_priv, 8320U, __cil_tmp44);
 #line 885
   __cil_tmp45 = ring->status_page.gfx_addr;
 #line 885
   drm_ut_debug_printk(2U, "drm", "i915_set_status_page", "load hws HWS_PGA with gfx mem 0x%x\n",
                       __cil_tmp45);
 #line 887
   __cil_tmp46 = ring->status_page.page_addr;
 #line 887
   drm_ut_debug_printk(2U, "drm", "i915_set_status_page", "load hws at %p\n", __cil_tmp46);
   }
 #line 889
   return (0);
 }
 }
 #line 892 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_get_bridge_dev(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp3 ;
   struct pci_dev *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   struct pci_dev *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
 
   {
   {
 #line 894
   __cil_tmp3 = dev->dev_private;
 #line 894
   dev_priv = (struct drm_i915_private *)__cil_tmp3;
 #line 896
   dev_priv->bridge_dev = pci_get_bus_and_slot(0U, 0U);
   }
   {
 #line 897
   __cil_tmp4 = (struct pci_dev *)0;
 #line 897
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 897
   __cil_tmp6 = dev_priv->bridge_dev;
 #line 897
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 897
   if (__cil_tmp7 == __cil_tmp5) {
     {
 #line 898
     drm_err("i915_get_bridge_dev", "bridge device not found\n");
     }
 #line 899
     return (-1);
   } else {
 
   }
   }
 #line 901
   return (0);
 }
 }
 #line 913 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int intel_alloc_mchbar_resource(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int reg ;
   int tmp ;
   u32 temp_lo ;
   u32 temp_hi ;
   u64 mchbar_addr ;
   int ret ;
   int tmp___0 ;
   void *__cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   u8 __cil_tmp20 ;
   unsigned char __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   struct pci_dev *__cil_tmp23 ;
   int __cil_tmp24 ;
   struct pci_dev *__cil_tmp25 ;
   unsigned long long __cil_tmp26 ;
   unsigned long long __cil_tmp27 ;
   unsigned long long __cil_tmp28 ;
   u64 __cil_tmp29 ;
   struct pci_dev *__cil_tmp30 ;
   struct pci_bus *__cil_tmp31 ;
   struct resource *__cil_tmp32 ;
   resource_size_t __cil_tmp33 ;
   struct pci_dev *__cil_tmp34 ;
   void *__cil_tmp35 ;
   void *__cil_tmp36 ;
   struct drm_i915_private *__cil_tmp37 ;
   struct intel_device_info  const  *__cil_tmp38 ;
   u8 __cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct pci_dev *__cil_tmp42 ;
   int __cil_tmp43 ;
   resource_size_t __cil_tmp44 ;
   resource_size_t __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   struct pci_dev *__cil_tmp47 ;
   resource_size_t __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
 
   {
 #line 915
   __cil_tmp10 = dev->dev_private;
 #line 915
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
   {
 #line 916
   __cil_tmp11 = dev->dev_private;
 #line 916
   __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 916
   __cil_tmp13 = __cil_tmp12->info;
 #line 916
   __cil_tmp14 = __cil_tmp13->gen;
 #line 916
   __cil_tmp15 = (unsigned char )__cil_tmp14;
 #line 916
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 916
   if (__cil_tmp16 > 3U) {
 #line 916
     tmp = 72;
   } else {
 #line 916
     tmp = 68;
   }
   }
 #line 916
   reg = tmp;
 #line 917
   temp_hi = 0U;
   {
 #line 921
   __cil_tmp17 = dev->dev_private;
 #line 921
   __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 921
   __cil_tmp19 = __cil_tmp18->info;
 #line 921
   __cil_tmp20 = __cil_tmp19->gen;
 #line 921
   __cil_tmp21 = (unsigned char )__cil_tmp20;
 #line 921
   __cil_tmp22 = (unsigned int )__cil_tmp21;
 #line 921
   if (__cil_tmp22 > 3U) {
     {
 #line 922
     __cil_tmp23 = dev_priv->bridge_dev;
 #line 922
     __cil_tmp24 = reg + 4;
 #line 922
     pci_read_config_dword(__cil_tmp23, __cil_tmp24, & temp_hi);
     }
   } else {
 
   }
   }
   {
 #line 923
   __cil_tmp25 = dev_priv->bridge_dev;
 #line 923
   pci_read_config_dword(__cil_tmp25, reg, & temp_lo);
 #line 924
   __cil_tmp26 = (unsigned long long )temp_lo;
 #line 924
   __cil_tmp27 = (unsigned long long )temp_hi;
 #line 924
   __cil_tmp28 = __cil_tmp27 << 32;
 #line 924
   mchbar_addr = __cil_tmp28 | __cil_tmp26;
   }
 #line 928
   if (mchbar_addr != 0ULL) {
     {
 #line 928
     __cil_tmp29 = mchbar_addr + 16384ULL;
 #line 928
     tmp___0 = pnp_range_reserved(mchbar_addr, __cil_tmp29);
     }
 #line 928
     if (tmp___0 != 0) {
 #line 930
       return (0);
     } else {
 
     }
   } else {
 
   }
   {
 #line 934
   dev_priv->mch_res.name = "i915 MCHBAR";
 #line 935
   dev_priv->mch_res.flags = 512UL;
 #line 936
   __cil_tmp30 = dev_priv->bridge_dev;
 #line 936
   __cil_tmp31 = __cil_tmp30->bus;
 #line 936
   __cil_tmp32 = & dev_priv->mch_res;
 #line 936
   __cil_tmp33 = (resource_size_t )pci_mem_start;
 #line 936
   __cil_tmp34 = dev_priv->bridge_dev;
 #line 936
   __cil_tmp35 = (void *)__cil_tmp34;
 #line 936
   ret = pci_bus_alloc_resource(__cil_tmp31, __cil_tmp32, 16384ULL, 16384ULL, __cil_tmp33,
                                0U, & pcibios_align_resource, __cil_tmp35);
   }
 #line 942
   if (ret != 0) {
     {
 #line 943
     drm_ut_debug_printk(2U, "drm", "intel_alloc_mchbar_resource", "failed bus alloc: %d\n",
                         ret);
 #line 944
     dev_priv->mch_res.start = 0ULL;
     }
 #line 945
     return (ret);
   } else {
 
   }
   {
 #line 948
   __cil_tmp36 = dev->dev_private;
 #line 948
   __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
 #line 948
   __cil_tmp38 = __cil_tmp37->info;
 #line 948
   __cil_tmp39 = __cil_tmp38->gen;
 #line 948
   __cil_tmp40 = (unsigned char )__cil_tmp39;
 #line 948
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 948
   if (__cil_tmp41 > 3U) {
     {
 #line 949
     __cil_tmp42 = dev_priv->bridge_dev;
 #line 949
     __cil_tmp43 = reg + 4;
 #line 949
     __cil_tmp44 = dev_priv->mch_res.start;
 #line 949
     __cil_tmp45 = __cil_tmp44 >> 32ULL;
 #line 949
     __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 949
     pci_write_config_dword(__cil_tmp42, __cil_tmp43, __cil_tmp46);
     }
   } else {
 
   }
   }
   {
 #line 952
   __cil_tmp47 = dev_priv->bridge_dev;
 #line 952
   __cil_tmp48 = dev_priv->mch_res.start;
 #line 952
   __cil_tmp49 = (unsigned int )__cil_tmp48;
 #line 952
   pci_write_config_dword(__cil_tmp47, reg, __cil_tmp49);
   }
 #line 954
   return (0);
 }
 }
 #line 959 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void intel_setup_mchbar(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int mchbar_reg ;
   int tmp ;
   u32 temp ;
   bool enabled ;
   int tmp___0 ;
   void *__cil_tmp8 ;
   void *__cil_tmp9 ;
   struct drm_i915_private *__cil_tmp10 ;
   struct intel_device_info  const  *__cil_tmp11 ;
   u8 __cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   void *__cil_tmp15 ;
   struct drm_i915_private *__cil_tmp16 ;
   struct intel_device_info  const  *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char *__cil_tmp19 ;
   unsigned char __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   struct pci_dev *__cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   struct pci_dev *__cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   struct pci_dev *__cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   void *__cil_tmp32 ;
   struct drm_i915_private *__cil_tmp33 ;
   struct intel_device_info  const  *__cil_tmp34 ;
   unsigned char *__cil_tmp35 ;
   unsigned char *__cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   struct pci_dev *__cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   int __cil_tmp41 ;
   struct pci_dev *__cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   struct pci_dev *__cil_tmp44 ;
   struct pci_dev *__cil_tmp45 ;
   unsigned int __cil_tmp46 ;
 
   {
 #line 961
   __cil_tmp8 = dev->dev_private;
 #line 961
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
   {
 #line 962
   __cil_tmp9 = dev->dev_private;
 #line 962
   __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
 #line 962
   __cil_tmp11 = __cil_tmp10->info;
 #line 962
   __cil_tmp12 = __cil_tmp11->gen;
 #line 962
   __cil_tmp13 = (unsigned char )__cil_tmp12;
 #line 962
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 962
   if (__cil_tmp14 > 3U) {
 #line 962
     tmp = 72;
   } else {
 #line 962
     tmp = 68;
   }
   }
 #line 962
   mchbar_reg = tmp;
 #line 966
   dev_priv->mchbar_need_disable = (bool )0;
   {
 #line 968
   __cil_tmp15 = dev->dev_private;
 #line 968
   __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
 #line 968
   __cil_tmp17 = __cil_tmp16->info;
 #line 968
   __cil_tmp18 = (unsigned char *)__cil_tmp17;
 #line 968
   __cil_tmp19 = __cil_tmp18 + 1UL;
 #line 968
   __cil_tmp20 = *__cil_tmp19;
 #line 968
   __cil_tmp21 = (unsigned int )__cil_tmp20;
 #line 968
   if (__cil_tmp21 != 0U) {
     {
 #line 969
     __cil_tmp22 = dev_priv->bridge_dev;
 #line 969
     pci_read_config_dword(__cil_tmp22, 84, & temp);
 #line 970
     __cil_tmp23 = temp & 268435456U;
 #line 970
     __cil_tmp24 = __cil_tmp23 != 0U;
 #line 970
     enabled = (bool )__cil_tmp24;
     }
   } else {
     {
 #line 968
     __cil_tmp25 = dev->pci_device;
 #line 968
     if (__cil_tmp25 == 9618) {
       {
 #line 969
       __cil_tmp26 = dev_priv->bridge_dev;
 #line 969
       pci_read_config_dword(__cil_tmp26, 84, & temp);
 #line 970
       __cil_tmp27 = temp & 268435456U;
 #line 970
       __cil_tmp28 = __cil_tmp27 != 0U;
 #line 970
       enabled = (bool )__cil_tmp28;
       }
     } else {
       {
 #line 972
       __cil_tmp29 = dev_priv->bridge_dev;
 #line 972
       pci_read_config_dword(__cil_tmp29, mchbar_reg, & temp);
 #line 973
       __cil_tmp30 = temp & 1U;
 #line 973
       __cil_tmp31 = __cil_tmp30 != 0U;
 #line 973
       enabled = (bool )__cil_tmp31;
       }
     }
     }
   }
   }
 #line 977
   if ((int )enabled) {
 #line 978
     return;
   } else {
 
   }
   {
 #line 980
   tmp___0 = intel_alloc_mchbar_resource(dev);
   }
 #line 980
   if (tmp___0 != 0) {
 #line 981
     return;
   } else {
 
   }
 #line 983
   dev_priv->mchbar_need_disable = (bool )1;
   {
 #line 986
   __cil_tmp32 = dev->dev_private;
 #line 986
   __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
 #line 986
   __cil_tmp34 = __cil_tmp33->info;
 #line 986
   __cil_tmp35 = (unsigned char *)__cil_tmp34;
 #line 986
   __cil_tmp36 = __cil_tmp35 + 1UL;
 #line 986
   __cil_tmp37 = *__cil_tmp36;
 #line 986
   __cil_tmp38 = (unsigned int )__cil_tmp37;
 #line 986
   if (__cil_tmp38 != 0U) {
     {
 #line 987
     __cil_tmp39 = dev_priv->bridge_dev;
 #line 987
     __cil_tmp40 = temp | 268435456U;
 #line 987
     pci_write_config_dword(__cil_tmp39, 84, __cil_tmp40);
     }
   } else {
     {
 #line 986
     __cil_tmp41 = dev->pci_device;
 #line 986
     if (__cil_tmp41 == 9618) {
       {
 #line 987
       __cil_tmp42 = dev_priv->bridge_dev;
 #line 987
       __cil_tmp43 = temp | 268435456U;
 #line 987
       pci_write_config_dword(__cil_tmp42, 84, __cil_tmp43);
       }
     } else {
       {
 #line 990
       __cil_tmp44 = dev_priv->bridge_dev;
 #line 990
       pci_read_config_dword(__cil_tmp44, mchbar_reg, & temp);
 #line 991
       __cil_tmp45 = dev_priv->bridge_dev;
 #line 991
       __cil_tmp46 = temp | 1U;
 #line 991
       pci_write_config_dword(__cil_tmp45, mchbar_reg, __cil_tmp46);
       }
     }
     }
   }
   }
 #line 993
   return;
 }
 }
 #line 996 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void intel_teardown_mchbar(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int mchbar_reg ;
   int tmp ;
   u32 temp ;
   void *__cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   u8 __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   bool __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   struct pci_dev *__cil_tmp21 ;
   struct pci_dev *__cil_tmp22 ;
   int __cil_tmp23 ;
   struct pci_dev *__cil_tmp24 ;
   struct pci_dev *__cil_tmp25 ;
   struct pci_dev *__cil_tmp26 ;
   struct pci_dev *__cil_tmp27 ;
   resource_size_t __cil_tmp28 ;
   struct resource *__cil_tmp29 ;
 
   {
 #line 998
   __cil_tmp6 = dev->dev_private;
 #line 998
   dev_priv = (drm_i915_private_t *)__cil_tmp6;
   {
 #line 999
   __cil_tmp7 = dev->dev_private;
 #line 999
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 999
   __cil_tmp9 = __cil_tmp8->info;
 #line 999
   __cil_tmp10 = __cil_tmp9->gen;
 #line 999
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 999
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 999
   if (__cil_tmp12 > 3U) {
 #line 999
     tmp = 72;
   } else {
 #line 999
     tmp = 68;
   }
   }
 #line 999
   mchbar_reg = tmp;
   {
 #line 1002
   __cil_tmp13 = dev_priv->mchbar_need_disable;
 #line 1002
   if ((int )__cil_tmp13) {
     {
 #line 1003
     __cil_tmp14 = dev->dev_private;
 #line 1003
     __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 1003
     __cil_tmp16 = __cil_tmp15->info;
 #line 1003
     __cil_tmp17 = (unsigned char *)__cil_tmp16;
 #line 1003
     __cil_tmp18 = __cil_tmp17 + 1UL;
 #line 1003
     __cil_tmp19 = *__cil_tmp18;
 #line 1003
     __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 1003
     if (__cil_tmp20 != 0U) {
       {
 #line 1004
       __cil_tmp21 = dev_priv->bridge_dev;
 #line 1004
       pci_read_config_dword(__cil_tmp21, 84, & temp);
 #line 1005
       temp = temp & 4026531839U;
 #line 1006
       __cil_tmp22 = dev_priv->bridge_dev;
 #line 1006
       pci_write_config_dword(__cil_tmp22, 84, temp);
       }
     } else {
       {
 #line 1003
       __cil_tmp23 = dev->pci_device;
 #line 1003
       if (__cil_tmp23 == 9618) {
         {
 #line 1004
         __cil_tmp24 = dev_priv->bridge_dev;
 #line 1004
         pci_read_config_dword(__cil_tmp24, 84, & temp);
 #line 1005
         temp = temp & 4026531839U;
 #line 1006
         __cil_tmp25 = dev_priv->bridge_dev;
 #line 1006
         pci_write_config_dword(__cil_tmp25, 84, temp);
         }
       } else {
         {
 #line 1008
         __cil_tmp26 = dev_priv->bridge_dev;
 #line 1008
         pci_read_config_dword(__cil_tmp26, mchbar_reg, & temp);
 #line 1009
         temp = temp & 4294967294U;
 #line 1010
         __cil_tmp27 = dev_priv->bridge_dev;
 #line 1010
         pci_write_config_dword(__cil_tmp27, mchbar_reg, temp);
         }
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 1014
   __cil_tmp28 = dev_priv->mch_res.start;
 #line 1014
   if (__cil_tmp28 != 0ULL) {
     {
 #line 1015
     __cil_tmp29 = & dev_priv->mch_res;
 #line 1015
     release_resource(__cil_tmp29);
     }
   } else {
 
   }
   }
 #line 1016
   return;
 }
 }
 #line 1035 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static unsigned long i915_stolen_to_phys(struct drm_device *dev , u32 offset ) 
 { struct drm_i915_private *dev_priv ;
   struct pci_dev *pdev ;
   u32 base ;
   u16 val ;
   u8 val___0 ;
   void *__cil_tmp8 ;
   void *__cil_tmp9 ;
   struct drm_i915_private *__cil_tmp10 ;
   struct intel_device_info  const  *__cil_tmp11 ;
   u8 __cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   struct intel_gtt  const  *__cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   u32 __cil_tmp33 ;
   u32 __cil_tmp34 ;
 
   {
 #line 1037
   __cil_tmp8 = dev->dev_private;
 #line 1037
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 1038
   pdev = dev_priv->bridge_dev;
   {
 #line 1055
   __cil_tmp9 = dev->dev_private;
 #line 1055
   __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
 #line 1055
   __cil_tmp11 = __cil_tmp10->info;
 #line 1055
   __cil_tmp12 = __cil_tmp11->gen;
 #line 1055
   __cil_tmp13 = (unsigned char )__cil_tmp12;
 #line 1055
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 1055
   if (__cil_tmp14 > 3U) {
     {
 #line 1057
     pci_read_config_word(pdev, 176, & val);
 #line 1058
     __cil_tmp15 = (int )val;
 #line 1058
     __cil_tmp16 = __cil_tmp15 >> 4;
 #line 1058
     __cil_tmp17 = __cil_tmp16 << 20;
 #line 1058
     base = (u32 )__cil_tmp17;
     }
   } else {
     {
 #line 1055
     __cil_tmp18 = dev->dev_private;
 #line 1055
     __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 1055
     __cil_tmp20 = __cil_tmp19->info;
 #line 1055
     __cil_tmp21 = (unsigned char *)__cil_tmp20;
 #line 1055
     __cil_tmp22 = __cil_tmp21 + 1UL;
 #line 1055
     __cil_tmp23 = *__cil_tmp22;
 #line 1055
     __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 1055
     if (__cil_tmp24 != 0U) {
       {
 #line 1057
       pci_read_config_word(pdev, 176, & val);
 #line 1058
       __cil_tmp25 = (int )val;
 #line 1058
       __cil_tmp26 = __cil_tmp25 >> 4;
 #line 1058
       __cil_tmp27 = __cil_tmp26 << 20;
 #line 1058
       base = (u32 )__cil_tmp27;
       }
     } else {
       {
 #line 1061
       pci_read_config_byte(pdev, 156, & val___0);
 #line 1062
       __cil_tmp28 = (int )val___0;
 #line 1062
       __cil_tmp29 = __cil_tmp28 >> 3;
 #line 1062
       __cil_tmp30 = __cil_tmp29 << 27;
 #line 1062
       base = (u32 )__cil_tmp30;
       }
     }
     }
   }
   }
 #line 1064
   __cil_tmp31 = dev_priv->mm.gtt;
 #line 1064
   __cil_tmp32 = __cil_tmp31->stolen_size;
 #line 1064
   __cil_tmp33 = (u32 )__cil_tmp32;
 #line 1064
   base = base - __cil_tmp33;
   {
 #line 1067
   __cil_tmp34 = base + offset;
 #line 1067
   return ((unsigned long )__cil_tmp34);
   }
 }
 }
 #line 1070 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_warn_stolen(struct drm_device *dev ) 
 { 
 
   {
   {
 #line 1072
   drm_err("i915_warn_stolen", "not enough stolen space for compressed buffer, disabling\n");
 #line 1073
   drm_err("i915_warn_stolen", "hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
   }
 #line 1074
   return;
 }
 }
 #line 1076 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_setup_compression(struct drm_device *dev , int size ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_mm_node *compressed_fb ;
   struct drm_mm_node *compressed_llb ;
   unsigned long cfb_base ;
   unsigned long ll_base ;
   void *__cil_tmp8 ;
   struct drm_mm *__cil_tmp9 ;
   struct drm_mm  const  *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_mm_node *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct drm_mm_node *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   u32 __cil_tmp20 ;
   int __cil_tmp21 ;
   void *__cil_tmp22 ;
   struct drm_i915_private *__cil_tmp23 ;
   struct intel_device_info  const  *__cil_tmp24 ;
   u8 __cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   unsigned char *__cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   struct drm_mm *__cil_tmp41 ;
   struct drm_mm  const  *__cil_tmp42 ;
   struct drm_mm_node *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct drm_mm_node *__cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   u32 __cil_tmp50 ;
   void *__cil_tmp51 ;
   struct drm_i915_private *__cil_tmp52 ;
   struct intel_device_info  const  *__cil_tmp53 ;
   u8 __cil_tmp54 ;
   unsigned char __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   u32 __cil_tmp58 ;
   void *__cil_tmp59 ;
   struct drm_i915_private *__cil_tmp60 ;
   struct intel_device_info  const  *__cil_tmp61 ;
   u8 __cil_tmp62 ;
   unsigned char __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   unsigned long __cil_tmp65 ;
   u32 __cil_tmp66 ;
   void *__cil_tmp67 ;
   struct drm_i915_private *__cil_tmp68 ;
   struct intel_device_info  const  *__cil_tmp69 ;
   unsigned char *__cil_tmp70 ;
   unsigned char *__cil_tmp71 ;
   unsigned char __cil_tmp72 ;
   unsigned int __cil_tmp73 ;
   unsigned long __cil_tmp74 ;
   u32 __cil_tmp75 ;
   int __cil_tmp76 ;
   unsigned long __cil_tmp77 ;
   u32 __cil_tmp78 ;
   u32 __cil_tmp79 ;
   u32 __cil_tmp80 ;
   int __cil_tmp81 ;
 
   {
   {
 #line 1078
   __cil_tmp8 = dev->dev_private;
 #line 1078
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 1079
   compressed_llb = compressed_llb;
 #line 1081
   ll_base = 0UL;
 #line 1083
   __cil_tmp9 = & dev_priv->mm.stolen;
 #line 1083
   __cil_tmp10 = (struct drm_mm  const  *)__cil_tmp9;
 #line 1083
   __cil_tmp11 = (unsigned long )size;
 #line 1083
   compressed_fb = drm_mm_search_free(__cil_tmp10, __cil_tmp11, 4096U, 0);
   }
   {
 #line 1084
   __cil_tmp12 = (struct drm_mm_node *)0;
 #line 1084
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 1084
   __cil_tmp14 = (unsigned long )compressed_fb;
 #line 1084
   if (__cil_tmp14 != __cil_tmp13) {
     {
 #line 1085
     __cil_tmp15 = (unsigned long )size;
 #line 1085
     compressed_fb = drm_mm_get_block(compressed_fb, __cil_tmp15, 4096U);
     }
   } else {
 
   }
   }
   {
 #line 1086
   __cil_tmp16 = (struct drm_mm_node *)0;
 #line 1086
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 1086
   __cil_tmp18 = (unsigned long )compressed_fb;
 #line 1086
   if (__cil_tmp18 == __cil_tmp17) {
 #line 1087
     goto err;
   } else {
 
   }
   }
   {
 #line 1089
   __cil_tmp19 = compressed_fb->start;
 #line 1089
   __cil_tmp20 = (u32 )__cil_tmp19;
 #line 1089
   cfb_base = i915_stolen_to_phys(dev, __cil_tmp20);
   }
 #line 1090
   if (cfb_base == 0UL) {
 #line 1091
     goto err_fb;
   } else {
 
   }
   {
 #line 1093
   __cil_tmp21 = dev->pci_device;
 #line 1093
   if (__cil_tmp21 != 10818) {
     {
 #line 1093
     __cil_tmp22 = dev->dev_private;
 #line 1093
     __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
 #line 1093
     __cil_tmp24 = __cil_tmp23->info;
 #line 1093
     __cil_tmp25 = __cil_tmp24->gen;
 #line 1093
     __cil_tmp26 = (unsigned char )__cil_tmp25;
 #line 1093
     __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1093
     if (__cil_tmp27 != 5U) {
       {
 #line 1093
       __cil_tmp28 = dev->dev_private;
 #line 1093
       __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 1093
       __cil_tmp30 = __cil_tmp29->info;
 #line 1093
       __cil_tmp31 = __cil_tmp30->gen;
 #line 1093
       __cil_tmp32 = (unsigned char )__cil_tmp31;
 #line 1093
       __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 1093
       if (__cil_tmp33 != 6U) {
         {
 #line 1093
         __cil_tmp34 = dev->dev_private;
 #line 1093
         __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 1093
         __cil_tmp36 = __cil_tmp35->info;
 #line 1093
         __cil_tmp37 = (unsigned char *)__cil_tmp36;
 #line 1093
         __cil_tmp38 = __cil_tmp37 + 2UL;
 #line 1093
         __cil_tmp39 = *__cil_tmp38;
 #line 1093
         __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 1093
         if (__cil_tmp40 == 0U) {
           {
 #line 1094
           __cil_tmp41 = & dev_priv->mm.stolen;
 #line 1094
           __cil_tmp42 = (struct drm_mm  const  *)__cil_tmp41;
 #line 1094
           compressed_llb = drm_mm_search_free(__cil_tmp42, 4096UL, 4096U, 0);
           }
           {
 #line 1096
           __cil_tmp43 = (struct drm_mm_node *)0;
 #line 1096
           __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 1096
           __cil_tmp45 = (unsigned long )compressed_llb;
 #line 1096
           if (__cil_tmp45 != __cil_tmp44) {
             {
 #line 1097
             compressed_llb = drm_mm_get_block(compressed_llb, 4096UL, 4096U);
             }
           } else {
 
           }
           }
           {
 #line 1099
           __cil_tmp46 = (struct drm_mm_node *)0;
 #line 1099
           __cil_tmp47 = (unsigned long )__cil_tmp46;
 #line 1099
           __cil_tmp48 = (unsigned long )compressed_llb;
 #line 1099
           if (__cil_tmp48 == __cil_tmp47) {
 #line 1100
             goto err_fb;
           } else {
 
           }
           }
           {
 #line 1102
           __cil_tmp49 = compressed_llb->start;
 #line 1102
           __cil_tmp50 = (u32 )__cil_tmp49;
 #line 1102
           ll_base = i915_stolen_to_phys(dev, __cil_tmp50);
           }
 #line 1103
           if (ll_base == 0UL) {
 #line 1104
             goto err_llb;
           } else {
 
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1107
   dev_priv->cfb_size = (unsigned long )size;
 #line 1109
   intel_disable_fbc(dev);
 #line 1110
   dev_priv->compressed_fb = compressed_fb;
   }
   {
 #line 1111
   __cil_tmp51 = dev->dev_private;
 #line 1111
   __cil_tmp52 = (struct drm_i915_private *)__cil_tmp51;
 #line 1111
   __cil_tmp53 = __cil_tmp52->info;
 #line 1111
   __cil_tmp54 = __cil_tmp53->gen;
 #line 1111
   __cil_tmp55 = (unsigned char )__cil_tmp54;
 #line 1111
   __cil_tmp56 = (unsigned int )__cil_tmp55;
 #line 1111
   if (__cil_tmp56 == 5U) {
     {
 #line 1112
     __cil_tmp57 = compressed_fb->start;
 #line 1112
     __cil_tmp58 = (u32 )__cil_tmp57;
 #line 1112
     i915_write32___0(dev_priv, 274944U, __cil_tmp58);
     }
   } else {
     {
 #line 1111
     __cil_tmp59 = dev->dev_private;
 #line 1111
     __cil_tmp60 = (struct drm_i915_private *)__cil_tmp59;
 #line 1111
     __cil_tmp61 = __cil_tmp60->info;
 #line 1111
     __cil_tmp62 = __cil_tmp61->gen;
 #line 1111
     __cil_tmp63 = (unsigned char )__cil_tmp62;
 #line 1111
     __cil_tmp64 = (unsigned int )__cil_tmp63;
 #line 1111
     if (__cil_tmp64 == 6U) {
       {
 #line 1112
       __cil_tmp65 = compressed_fb->start;
 #line 1112
       __cil_tmp66 = (u32 )__cil_tmp65;
 #line 1112
       i915_write32___0(dev_priv, 274944U, __cil_tmp66);
       }
     } else {
       {
 #line 1111
       __cil_tmp67 = dev->dev_private;
 #line 1111
       __cil_tmp68 = (struct drm_i915_private *)__cil_tmp67;
 #line 1111
       __cil_tmp69 = __cil_tmp68->info;
 #line 1111
       __cil_tmp70 = (unsigned char *)__cil_tmp69;
 #line 1111
       __cil_tmp71 = __cil_tmp70 + 2UL;
 #line 1111
       __cil_tmp72 = *__cil_tmp71;
 #line 1111
       __cil_tmp73 = (unsigned int )__cil_tmp72;
 #line 1111
       if (__cil_tmp73 != 0U) {
         {
 #line 1112
         __cil_tmp74 = compressed_fb->start;
 #line 1112
         __cil_tmp75 = (u32 )__cil_tmp74;
 #line 1112
         i915_write32___0(dev_priv, 274944U, __cil_tmp75);
         }
       } else {
         {
 #line 1113
         __cil_tmp76 = dev->pci_device;
 #line 1113
         if (__cil_tmp76 == 10818) {
           {
 #line 1114
           __cil_tmp77 = compressed_fb->start;
 #line 1114
           __cil_tmp78 = (u32 )__cil_tmp77;
 #line 1114
           i915_write32___0(dev_priv, 12800U, __cil_tmp78);
           }
         } else {
           {
 #line 1116
           __cil_tmp79 = (u32 )cfb_base;
 #line 1116
           i915_write32___0(dev_priv, 12800U, __cil_tmp79);
 #line 1117
           __cil_tmp80 = (u32 )ll_base;
 #line 1117
           i915_write32___0(dev_priv, 12804U, __cil_tmp80);
 #line 1118
           dev_priv->compressed_llb = compressed_llb;
           }
         }
         }
       }
       }
     }
     }
   }
   }
   {
 #line 1121
   __cil_tmp81 = size >> 20;
 #line 1121
   drm_ut_debug_printk(4U, "drm", "i915_setup_compression", "FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
                       cfb_base, ll_base, __cil_tmp81);
   }
 #line 1123
   return;
   err_llb: 
   {
 #line 1126
   drm_mm_put_block(compressed_llb);
   }
   err_fb: 
   {
 #line 1128
   drm_mm_put_block(compressed_fb);
   }
   err: 
   {
 #line 1130
   dev_priv->no_fbc_reason = (enum no_fbc_reason )1;
 #line 1131
   i915_warn_stolen(dev);
   }
 #line 1132
   return;
 }
 }
 #line 1134 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_cleanup_compression(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp3 ;
   struct drm_mm_node *__cil_tmp4 ;
   struct drm_mm_node *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   struct drm_mm_node *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_mm_node *__cil_tmp9 ;
 
   {
   {
 #line 1136
   __cil_tmp3 = dev->dev_private;
 #line 1136
   dev_priv = (struct drm_i915_private *)__cil_tmp3;
 #line 1138
   __cil_tmp4 = dev_priv->compressed_fb;
 #line 1138
   drm_mm_put_block(__cil_tmp4);
   }
   {
 #line 1139
   __cil_tmp5 = (struct drm_mm_node *)0;
 #line 1139
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 1139
   __cil_tmp7 = dev_priv->compressed_llb;
 #line 1139
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 1139
   if (__cil_tmp8 != __cil_tmp6) {
     {
 #line 1140
     __cil_tmp9 = dev_priv->compressed_llb;
 #line 1140
     drm_mm_put_block(__cil_tmp9);
     }
   } else {
 
   }
   }
 #line 1141
   return;
 }
 }
 #line 1144 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static unsigned int i915_vga_set_decode(void *cookie , bool state ) 
 { struct drm_device *dev ;
   int __cil_tmp4 ;
   bool __cil_tmp5 ;
 
   {
   {
 #line 1146
   dev = (struct drm_device *)cookie;
 #line 1148
   __cil_tmp4 = (int )state;
 #line 1148
   __cil_tmp5 = (bool )__cil_tmp4;
 #line 1148
   intel_modeset_vga_set_state(dev, __cil_tmp5);
   }
 #line 1149
   if ((int )state) {
 #line 1150
     return (15U);
   } else {
 #line 1153
     return (12U);
   }
 }
 }
 #line 1156 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_switcheroo_set_state(struct pci_dev *pdev , enum vga_switcheroo_state state ) 
 { struct drm_device *dev ;
   void *tmp ;
   pm_message_t pmm ;
   unsigned int __cil_tmp6 ;
   struct pci_dev *__cil_tmp7 ;
 
   {
   {
 #line 1158
   tmp = pci_get_drvdata(pdev);
 #line 1158
   dev = (struct drm_device *)tmp;
 #line 1159
   pmm.event = 2;
   }
   {
 #line 1160
   __cil_tmp6 = (unsigned int )state;
 #line 1160
   if (__cil_tmp6 == 1U) {
     {
 #line 1161
     printk("<6>i915: switched on\n");
 #line 1162
     dev->switch_power_state = 2;
 #line 1164
     __cil_tmp7 = dev->pdev;
 #line 1164
     pci_set_power_state(__cil_tmp7, 0);
 #line 1165
     i915_resume(dev);
 #line 1166
     dev->switch_power_state = 0;
     }
   } else {
     {
 #line 1168
     printk("<3>i915: switched off\n");
 #line 1169
     dev->switch_power_state = 2;
 #line 1170
     i915_suspend(dev, pmm);
 #line 1171
     dev->switch_power_state = 1;
     }
   }
   }
 #line 1173
   return;
 }
 }
 #line 1175 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static bool i915_switcheroo_can_switch(struct pci_dev *pdev ) 
 { struct drm_device *dev ;
   void *tmp ;
   bool can_switch ;
   spinlock_t *__cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   spinlock_t *__cil_tmp8 ;
 
   {
   {
 #line 1177
   tmp = pci_get_drvdata(pdev);
 #line 1177
   dev = (struct drm_device *)tmp;
 #line 1180
   __cil_tmp5 = & dev->count_lock;
 #line 1180
   spin_lock(__cil_tmp5);
 #line 1181
   __cil_tmp6 = dev->open_count;
 #line 1181
   __cil_tmp7 = __cil_tmp6 == 0;
 #line 1181
   can_switch = (bool )__cil_tmp7;
 #line 1182
   __cil_tmp8 = & dev->count_lock;
 #line 1182
   spin_unlock(__cil_tmp8);
   }
 #line 1183
   return (can_switch);
 }
 }
 #line 1186 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_load_gem_init(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   unsigned long prealloc_size ;
   unsigned long gtt_size ;
   unsigned long mappable_size ;
   int ret ;
   int cfb_size ;
   void *__cil_tmp8 ;
   struct intel_gtt  const  *__cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   struct intel_gtt  const  *__cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   struct intel_gtt  const  *__cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   struct drm_mm *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct mutex *__cil_tmp19 ;
   struct mutex *__cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char *__cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
 
   {
   {
 #line 1188
   __cil_tmp8 = dev->dev_private;
 #line 1188
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 1192
   __cil_tmp9 = dev_priv->mm.gtt;
 #line 1192
   __cil_tmp10 = __cil_tmp9->stolen_size;
 #line 1192
   prealloc_size = (unsigned long )__cil_tmp10;
 #line 1193
   __cil_tmp11 = dev_priv->mm.gtt;
 #line 1193
   __cil_tmp12 = __cil_tmp11->gtt_total_entries;
 #line 1193
   __cil_tmp13 = __cil_tmp12 << 12;
 #line 1193
   gtt_size = (unsigned long )__cil_tmp13;
 #line 1194
   __cil_tmp14 = dev_priv->mm.gtt;
 #line 1194
   __cil_tmp15 = __cil_tmp14->gtt_mappable_entries;
 #line 1194
   __cil_tmp16 = __cil_tmp15 << 12;
 #line 1194
   mappable_size = (unsigned long )__cil_tmp16;
 #line 1197
   __cil_tmp17 = & dev_priv->mm.stolen;
 #line 1197
   drm_mm_init(__cil_tmp17, 0UL, prealloc_size);
 #line 1208
   __cil_tmp18 = gtt_size - 4096UL;
 #line 1208
   i915_gem_do_init(dev, 0UL, mappable_size, __cil_tmp18);
 #line 1210
   __cil_tmp19 = & dev->struct_mutex;
 #line 1210
   mutex_lock_nested(__cil_tmp19, 0U);
 #line 1211
   ret = i915_gem_init_ringbuffer(dev);
 #line 1212
   __cil_tmp20 = & dev->struct_mutex;
 #line 1212
   mutex_unlock(__cil_tmp20);
   }
 #line 1213
   if (ret != 0) {
 #line 1214
     return (ret);
   } else {
 
   }
   {
 #line 1217
   __cil_tmp21 = dev->dev_private;
 #line 1217
   __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 1217
   __cil_tmp23 = __cil_tmp22->info;
 #line 1217
   __cil_tmp24 = (unsigned char *)__cil_tmp23;
 #line 1217
   __cil_tmp25 = __cil_tmp24 + 2UL;
 #line 1217
   __cil_tmp26 = *__cil_tmp25;
 #line 1217
   __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1217
   if (__cil_tmp27 != 0U) {
 #line 1217
     if (i915_powersave != 0U) {
 #line 1223
       if (prealloc_size > 37748736UL) {
 #line 1224
         cfb_size = 33554432;
       } else {
 #line 1226
         __cil_tmp28 = prealloc_size * 7UL;
 #line 1226
         __cil_tmp29 = __cil_tmp28 / 8UL;
 #line 1226
         cfb_size = (int )__cil_tmp29;
       }
       {
 #line 1227
       i915_setup_compression(dev, cfb_size);
       }
     } else {
 
     }
   } else {
 
   }
   }
 #line 1231
   dev_priv->allow_batchbuffer = 1;
 #line 1232
   return (0);
 }
 }
 #line 1235 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static int i915_load_modeset_init(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int ret ;
   bool tmp ;
   u32 tmp___0 ;
   void *__cil_tmp6 ;
   struct pci_dev *__cil_tmp7 ;
   void *__cil_tmp8 ;
   void (*__cil_tmp9)(void * , bool  ) ;
   struct pci_dev *__cil_tmp10 ;
   void (*__cil_tmp11)(struct pci_dev * ) ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct mutex *__cil_tmp19 ;
   struct mutex *__cil_tmp20 ;
   struct pci_dev *__cil_tmp21 ;
   struct pci_dev *__cil_tmp22 ;
   void *__cil_tmp23 ;
   void (*__cil_tmp24)(void * , bool  ) ;
   unsigned int (*__cil_tmp25)(void * , bool  ) ;
 
   {
   {
 #line 1237
   __cil_tmp6 = dev->dev_private;
 #line 1237
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
 #line 1240
   tmp = intel_parse_bios(dev);
 #line 1240
   ret = (int )tmp;
   }
 #line 1241
   if (ret != 0) {
     {
 #line 1242
     printk("<6>[drm] failed to find VBIOS tables\n");
     }
   } else {
 
   }
   {
 #line 1251
   __cil_tmp7 = dev->pdev;
 #line 1251
   __cil_tmp8 = (void *)dev;
 #line 1251
   __cil_tmp9 = (void (*)(void * , bool  ))0;
 #line 1251
   ret = vga_client_register(__cil_tmp7, __cil_tmp8, __cil_tmp9, & i915_vga_set_decode);
   }
 #line 1252
   if (ret != 0) {
 #line 1252
     if (ret != -19) {
 #line 1253
       goto out;
     } else {
 
     }
   } else {
 
   }
   {
 #line 1255
   intel_register_dsm_handler();
 #line 1257
   __cil_tmp10 = dev->pdev;
 #line 1257
   __cil_tmp11 = (void (*)(struct pci_dev * ))0;
 #line 1257
   ret = vga_switcheroo_register_client(__cil_tmp10, & i915_switcheroo_set_state, __cil_tmp11,
                                        & i915_switcheroo_can_switch);
   }
 #line 1261
   if (ret != 0) {
 #line 1262
     goto cleanup_vga_client;
   } else {
 
   }
   {
 #line 1265
   __cil_tmp12 = dev->dev_private;
 #line 1265
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 1265
   __cil_tmp14 = __cil_tmp13->info;
 #line 1265
   __cil_tmp15 = __cil_tmp14->gen;
 #line 1265
   __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 1265
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 1265
   if (__cil_tmp17 == 3U) {
     {
 #line 1265
     tmp___0 = i915_read32___0(dev_priv, 8656U);
     }
     {
 #line 1265
     __cil_tmp18 = (int )tmp___0;
 #line 1265
     if (__cil_tmp18 & 1) {
 #line 1266
       dev_priv->flip_pending_is_done = (bool )1;
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1268
   intel_modeset_init(dev);
 #line 1270
   ret = i915_load_gem_init(dev);
   }
 #line 1271
   if (ret != 0) {
 #line 1272
     goto cleanup_vga_switcheroo;
   } else {
 
   }
   {
 #line 1274
   intel_modeset_gem_init(dev);
 #line 1276
   ret = drm_irq_install(dev);
   }
 #line 1277
   if (ret != 0) {
 #line 1278
     goto cleanup_gem;
   } else {
 
   }
   {
 #line 1282
   dev->vblank_disable_allowed = 1;
 #line 1284
   ret = intel_fbdev_init(dev);
   }
 #line 1285
   if (ret != 0) {
 #line 1286
     goto cleanup_irq;
   } else {
 
   }
   {
 #line 1288
   drm_kms_helper_poll_init(dev);
 #line 1291
   dev_priv->mm.suspended = 0;
   }
 #line 1293
   return (0);
   cleanup_irq: 
   {
 #line 1296
   drm_irq_uninstall(dev);
   }
   cleanup_gem: 
   {
 #line 1298
   __cil_tmp19 = & dev->struct_mutex;
 #line 1298
   mutex_lock_nested(__cil_tmp19, 0U);
 #line 1299
   i915_gem_cleanup_ringbuffer(dev);
 #line 1300
   __cil_tmp20 = & dev->struct_mutex;
 #line 1300
   mutex_unlock(__cil_tmp20);
   }
   cleanup_vga_switcheroo: 
   {
 #line 1302
   __cil_tmp21 = dev->pdev;
 #line 1302
   vga_switcheroo_unregister_client(__cil_tmp21);
   }
   cleanup_vga_client: 
   {
 #line 1304
   __cil_tmp22 = dev->pdev;
 #line 1304
   __cil_tmp23 = (void *)0;
 #line 1304
   __cil_tmp24 = (void (*)(void * , bool  ))0;
 #line 1304
   __cil_tmp25 = (unsigned int (*)(void * , bool  ))0;
 #line 1304
   vga_client_register(__cil_tmp22, __cil_tmp23, __cil_tmp24, __cil_tmp25);
   }
   out: ;
 #line 1306
   return (ret);
 }
 }
 #line 1309 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_master_create(struct drm_device *dev , struct drm_master *master ) 
 { struct drm_i915_master_private *master_priv ;
   void *tmp ;
   struct drm_i915_master_private *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
 
   {
   {
 #line 1313
   tmp = kzalloc(16UL, 208U);
 #line 1313
   master_priv = (struct drm_i915_master_private *)tmp;
   }
   {
 #line 1314
   __cil_tmp5 = (struct drm_i915_master_private *)0;
 #line 1314
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 1314
   __cil_tmp7 = (unsigned long )master_priv;
 #line 1314
   if (__cil_tmp7 == __cil_tmp6) {
 #line 1315
     return (-12);
   } else {
 
   }
   }
 #line 1317
   master->driver_priv = (void *)master_priv;
 #line 1318
   return (0);
 }
 }
 #line 1321 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 void i915_master_destroy(struct drm_device *dev , struct drm_master *master ) 
 { struct drm_i915_master_private *master_priv ;
   void *__cil_tmp4 ;
   struct drm_i915_master_private *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   void const   *__cil_tmp8 ;
 
   {
 #line 1323
   __cil_tmp4 = master->driver_priv;
 #line 1323
   master_priv = (struct drm_i915_master_private *)__cil_tmp4;
   {
 #line 1325
   __cil_tmp5 = (struct drm_i915_master_private *)0;
 #line 1325
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 1325
   __cil_tmp7 = (unsigned long )master_priv;
 #line 1325
   if (__cil_tmp7 == __cil_tmp6) {
 #line 1326
     return;
   } else {
 
   }
   }
   {
 #line 1328
   __cil_tmp8 = (void const   *)master_priv;
 #line 1328
   kfree(__cil_tmp8);
 #line 1330
   master->driver_priv = (void *)0;
   }
 #line 1331
   return;
 }
 }
 #line 1333 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_pineview_get_mem_freq(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 tmp ;
   void *__cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   int __cil_tmp20 ;
 
   {
   {
 #line 1335
   __cil_tmp4 = dev->dev_private;
 #line 1335
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 1338
   tmp = i915_read32___0(dev_priv, 68608U);
   }
   {
 #line 1341
   __cil_tmp5 = tmp & 7U;
 #line 1341
   __cil_tmp6 = (int )__cil_tmp5;
 #line 1341
   if (__cil_tmp6 == 1) {
 #line 1341
     goto case_1;
   } else {
     {
 #line 1344
     __cil_tmp7 = tmp & 7U;
 #line 1344
     __cil_tmp8 = (int )__cil_tmp7;
 #line 1344
     if (__cil_tmp8 == 2) {
 #line 1344
       goto case_2;
     } else {
       {
 #line 1347
       __cil_tmp9 = tmp & 7U;
 #line 1347
       __cil_tmp10 = (int )__cil_tmp9;
 #line 1347
       if (__cil_tmp10 == 3) {
 #line 1347
         goto case_3;
       } else {
         {
 #line 1350
         __cil_tmp11 = tmp & 7U;
 #line 1350
         __cil_tmp12 = (int )__cil_tmp11;
 #line 1350
         if (__cil_tmp12 == 5) {
 #line 1350
           goto case_5;
         } else
 #line 1340
         if (0) {
           case_1: 
 #line 1342
           dev_priv->fsb_freq = 533U;
 #line 1343
           goto ldv_40610;
           case_2: 
 #line 1345
           dev_priv->fsb_freq = 800U;
 #line 1346
           goto ldv_40610;
           case_3: 
 #line 1348
           dev_priv->fsb_freq = 667U;
 #line 1349
           goto ldv_40610;
           case_5: 
 #line 1351
           dev_priv->fsb_freq = 400U;
 #line 1352
           goto ldv_40610;
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_40610: ;
   {
 #line 1356
   __cil_tmp13 = tmp & 112U;
 #line 1356
   __cil_tmp14 = (int )__cil_tmp13;
 #line 1356
   if (__cil_tmp14 == 16) {
 #line 1356
     goto case_16;
   } else {
     {
 #line 1359
     __cil_tmp15 = tmp & 112U;
 #line 1359
     __cil_tmp16 = (int )__cil_tmp15;
 #line 1359
     if (__cil_tmp16 == 32) {
 #line 1359
       goto case_32;
     } else {
       {
 #line 1362
       __cil_tmp17 = tmp & 112U;
 #line 1362
       __cil_tmp18 = (int )__cil_tmp17;
 #line 1362
       if (__cil_tmp18 == 48) {
 #line 1362
         goto case_48;
       } else
 #line 1355
       if (0) {
         case_16: 
 #line 1357
         dev_priv->mem_freq = 533U;
 #line 1358
         goto ldv_40615;
         case_32: 
 #line 1360
         dev_priv->mem_freq = 667U;
 #line 1361
         goto ldv_40615;
         case_48: 
 #line 1363
         dev_priv->mem_freq = 800U;
 #line 1364
         goto ldv_40615;
       } else {
 
       }
       }
     }
     }
   }
   }
   ldv_40615: 
   {
 #line 1368
   tmp = i915_read32___0(dev_priv, 65960U);
 #line 1369
   __cil_tmp19 = tmp & 4U;
 #line 1369
   __cil_tmp20 = __cil_tmp19 != 0U;
 #line 1369
   dev_priv->is_ddr3 = (unsigned int )__cil_tmp20;
   }
 #line 1370
   return;
 }
 }
 #line 1372 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void i915_ironlake_get_mem_freq(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u16 ddrpll ;
   u16 csipll ;
   void *__cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
 
   {
   {
 #line 1374
   __cil_tmp5 = dev->dev_private;
 #line 1374
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 1377
   ddrpll = i915_read16(dev_priv, 76832U);
 #line 1378
   csipll = i915_read16(dev_priv, 76816U);
   }
   {
 #line 1381
   __cil_tmp6 = (int )ddrpll;
 #line 1381
   __cil_tmp7 = __cil_tmp6 & 255;
 #line 1381
   if (__cil_tmp7 == 12) {
 #line 1381
     goto case_12;
   } else {
     {
 #line 1384
     __cil_tmp8 = (int )ddrpll;
 #line 1384
     __cil_tmp9 = __cil_tmp8 & 255;
 #line 1384
     if (__cil_tmp9 == 16) {
 #line 1384
       goto case_16;
     } else {
       {
 #line 1387
       __cil_tmp10 = (int )ddrpll;
 #line 1387
       __cil_tmp11 = __cil_tmp10 & 255;
 #line 1387
       if (__cil_tmp11 == 20) {
 #line 1387
         goto case_20;
       } else {
         {
 #line 1390
         __cil_tmp12 = (int )ddrpll;
 #line 1390
         __cil_tmp13 = __cil_tmp12 & 255;
 #line 1390
         if (__cil_tmp13 == 24) {
 #line 1390
           goto case_24;
         } else {
 #line 1393
           goto switch_default;
 #line 1380
           if (0) {
             case_12: 
 #line 1382
             dev_priv->mem_freq = 800U;
 #line 1383
             goto ldv_40625;
             case_16: 
 #line 1385
             dev_priv->mem_freq = 1066U;
 #line 1386
             goto ldv_40625;
             case_20: 
 #line 1388
             dev_priv->mem_freq = 1333U;
 #line 1389
             goto ldv_40625;
             case_24: 
 #line 1391
             dev_priv->mem_freq = 1600U;
 #line 1392
             goto ldv_40625;
             switch_default: 
             {
 #line 1394
             __cil_tmp14 = (int )ddrpll;
 #line 1394
             __cil_tmp15 = __cil_tmp14 & 255;
 #line 1394
             drm_ut_debug_printk(2U, "drm", "i915_ironlake_get_mem_freq", "unknown memory frequency 0x%02x\n",
                                 __cil_tmp15);
 #line 1396
             dev_priv->mem_freq = 0U;
             }
 #line 1397
             goto ldv_40625;
           } else {
 
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_40625: 
 #line 1400
   __cil_tmp16 = dev_priv->mem_freq;
 #line 1400
   dev_priv->r_t = (int )__cil_tmp16;
   {
 #line 1403
   __cil_tmp17 = (int )csipll;
 #line 1403
   __cil_tmp18 = __cil_tmp17 & 1023;
 #line 1403
   if (__cil_tmp18 == 12) {
 #line 1403
     goto case_12___0;
   } else {
     {
 #line 1406
     __cil_tmp19 = (int )csipll;
 #line 1406
     __cil_tmp20 = __cil_tmp19 & 1023;
 #line 1406
     if (__cil_tmp20 == 14) {
 #line 1406
       goto case_14;
     } else {
       {
 #line 1409
       __cil_tmp21 = (int )csipll;
 #line 1409
       __cil_tmp22 = __cil_tmp21 & 1023;
 #line 1409
       if (__cil_tmp22 == 16) {
 #line 1409
         goto case_16___0;
       } else {
         {
 #line 1412
         __cil_tmp23 = (int )csipll;
 #line 1412
         __cil_tmp24 = __cil_tmp23 & 1023;
 #line 1412
         if (__cil_tmp24 == 18) {
 #line 1412
           goto case_18;
         } else {
           {
 #line 1415
           __cil_tmp25 = (int )csipll;
 #line 1415
           __cil_tmp26 = __cil_tmp25 & 1023;
 #line 1415
           if (__cil_tmp26 == 20) {
 #line 1415
             goto case_20___0;
           } else {
             {
 #line 1418
             __cil_tmp27 = (int )csipll;
 #line 1418
             __cil_tmp28 = __cil_tmp27 & 1023;
 #line 1418
             if (__cil_tmp28 == 22) {
 #line 1418
               goto case_22;
             } else {
               {
 #line 1421
               __cil_tmp29 = (int )csipll;
 #line 1421
               __cil_tmp30 = __cil_tmp29 & 1023;
 #line 1421
               if (__cil_tmp30 == 24) {
 #line 1421
                 goto case_24___0;
               } else {
 #line 1424
                 goto switch_default___0;
 #line 1402
                 if (0) {
                   case_12___0: 
 #line 1404
                   dev_priv->fsb_freq = 3200U;
 #line 1405
                   goto ldv_40632;
                   case_14: 
 #line 1407
                   dev_priv->fsb_freq = 3733U;
 #line 1408
                   goto ldv_40632;
                   case_16___0: 
 #line 1410
                   dev_priv->fsb_freq = 4266U;
 #line 1411
                   goto ldv_40632;
                   case_18: 
 #line 1413
                   dev_priv->fsb_freq = 4800U;
 #line 1414
                   goto ldv_40632;
                   case_20___0: 
 #line 1416
                   dev_priv->fsb_freq = 5333U;
 #line 1417
                   goto ldv_40632;
                   case_22: 
 #line 1419
                   dev_priv->fsb_freq = 5866U;
 #line 1420
                   goto ldv_40632;
                   case_24___0: 
 #line 1422
                   dev_priv->fsb_freq = 6400U;
 #line 1423
                   goto ldv_40632;
                   switch_default___0: 
                   {
 #line 1425
                   __cil_tmp31 = (int )csipll;
 #line 1425
                   __cil_tmp32 = __cil_tmp31 & 1023;
 #line 1425
                   drm_ut_debug_printk(2U, "drm", "i915_ironlake_get_mem_freq", "unknown fsb frequency 0x%04x\n",
                                       __cil_tmp32);
 #line 1427
                   dev_priv->fsb_freq = 0U;
                   }
 #line 1428
                   goto ldv_40632;
                 } else {
 
                 }
               }
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_40632: ;
   {
 #line 1431
   __cil_tmp33 = dev_priv->fsb_freq;
 #line 1431
   if (__cil_tmp33 == 3200U) {
 #line 1432
     dev_priv->c_m = 0;
   } else {
     {
 #line 1433
     __cil_tmp34 = dev_priv->fsb_freq;
 #line 1433
     if (__cil_tmp34 > 3200U) {
       {
 #line 1433
       __cil_tmp35 = dev_priv->fsb_freq;
 #line 1433
       if (__cil_tmp35 <= 4800U) {
 #line 1434
         dev_priv->c_m = 1;
       } else {
 #line 1436
         dev_priv->c_m = 2;
       }
       }
     } else {
 #line 1436
       dev_priv->c_m = 2;
     }
     }
   }
   }
 #line 1437
   return;
 }
 }
 #line 1445 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static struct cparams  const  cparams[6U]  = {      {(u16 )1U, (u16 )1333U, (u16 )301U, (u16 )28664U}, 
         {(u16 )1U, (u16 )1066U, (u16 )294U, (u16 )24460U}, 
         {(u16 )1U, (u16 )800U, (u16 )294U, (u16 )25192U}, 
         {(u16 )0U, (u16 )1333U, (u16 )276U, (u16 )27605U}, 
         {(u16 )0U, (u16 )1066U, (u16 )276U, (u16 )27605U}, 
         {(u16 )0U, (u16 )800U, (u16 )231U, (u16 )23784U}};
 #line 1454 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv ) 
 { u64 total_count ;
   u64 diff ;
   u64 ret ;
   u32 count1 ;
   u32 count2 ;
   u32 count3 ;
   u32 m ;
   u32 c ;
   unsigned long now ;
   unsigned int tmp ;
   unsigned long diff1 ;
   int i ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   u32 __cil_tmp17 ;
   u32 __cil_tmp18 ;
   u64 __cil_tmp19 ;
   u64 __cil_tmp20 ;
   u64 __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   u32 __cil_tmp27 ;
   u64 __cil_tmp28 ;
   u64 __cil_tmp29 ;
   u64 __cil_tmp30 ;
 
   {
   {
 #line 1457
   m = 0U;
 #line 1457
   c = 0U;
 #line 1458
   __cil_tmp14 = (unsigned long const   )jiffies;
 #line 1458
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 1458
   tmp = jiffies_to_msecs(__cil_tmp15);
 #line 1458
   now = (unsigned long )tmp;
 #line 1461
   __cil_tmp16 = dev_priv->last_time1;
 #line 1461
   diff1 = now - __cil_tmp16;
 #line 1463
   count1 = i915_read32___0(dev_priv, 70372U);
 #line 1464
   count2 = i915_read32___0(dev_priv, 70376U);
 #line 1465
   count3 = i915_read32___0(dev_priv, 70368U);
 #line 1467
   __cil_tmp17 = count1 + count2;
 #line 1467
   __cil_tmp18 = __cil_tmp17 + count3;
 #line 1467
   total_count = (u64 )__cil_tmp18;
   }
   {
 #line 1470
   __cil_tmp19 = dev_priv->last_count1;
 #line 1470
   if (__cil_tmp19 > total_count) {
 #line 1471
     __cil_tmp20 = dev_priv->last_count1;
 #line 1471
     diff = ~ __cil_tmp20;
 #line 1472
     diff = diff + total_count;
   } else {
 #line 1474
     __cil_tmp21 = dev_priv->last_count1;
 #line 1474
     diff = total_count - __cil_tmp21;
   }
   }
 #line 1477
   i = 0;
 #line 1477
   goto ldv_40664;
   ldv_40663: ;
   {
 #line 1478
   __cil_tmp22 = dev_priv->c_m;
 #line 1478
   __cil_tmp23 = (int )cparams[i].i;
 #line 1478
   if (__cil_tmp23 == __cil_tmp22) {
     {
 #line 1478
     __cil_tmp24 = dev_priv->r_t;
 #line 1478
     __cil_tmp25 = (int )cparams[i].t;
 #line 1478
     if (__cil_tmp25 == __cil_tmp24) {
 #line 1480
       m = (u32 )cparams[i].m;
 #line 1481
       c = (u32 )cparams[i].c;
 #line 1482
       goto ldv_40662;
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 1477
   i = i + 1;
   ldv_40664: ;
   {
 #line 1477
   __cil_tmp26 = (unsigned int )i;
 #line 1477
   if (__cil_tmp26 <= 5U) {
 #line 1478
     goto ldv_40663;
   } else {
 #line 1480
     goto ldv_40662;
   }
   }
   ldv_40662: 
   {
 #line 1486
   __cil_tmp27 = (u32 )diff1;
 #line 1486
   diff = div_u64(diff, __cil_tmp27);
 #line 1487
   __cil_tmp28 = (u64 )c;
 #line 1487
   __cil_tmp29 = (u64 )m;
 #line 1487
   __cil_tmp30 = __cil_tmp29 * diff;
 #line 1487
   ret = __cil_tmp30 + __cil_tmp28;
 #line 1488
   ret = div_u64(ret, 10U);
 #line 1490
   dev_priv->last_count1 = total_count;
 #line 1491
   dev_priv->last_time1 = now;
   }
 #line 1493
   return ((unsigned long )ret);
 }
 }
 #line 1496 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 unsigned long i915_mch_val(struct drm_i915_private *dev_priv ) 
 { unsigned long m ;
   unsigned long x ;
   unsigned long b ;
   u32 tsfs ;
   u8 tmp ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
 
   {
   {
 #line 1501
   tsfs = i915_read32___0(dev_priv, 69664U);
 #line 1503
   __cil_tmp7 = tsfs & 65280U;
 #line 1503
   __cil_tmp8 = __cil_tmp7 >> 8;
 #line 1503
   m = (unsigned long )__cil_tmp8;
 #line 1504
   tmp = i915_read8(dev_priv, 69638U);
 #line 1504
   x = (unsigned long )tmp;
 #line 1506
   __cil_tmp9 = (unsigned long )tsfs;
 #line 1506
   b = __cil_tmp9 & 255UL;
   }
   {
 #line 1508
   __cil_tmp10 = m * x;
 #line 1508
   __cil_tmp11 = __cil_tmp10 / 127UL;
 #line 1508
   return (__cil_tmp11 - b);
   }
 }
 }
 #line 1511 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv , u8 pxvid ) 
 { struct v_table v_table[128U] ;
   struct intel_device_info  const  *__cil_tmp4 ;
   unsigned char *__cil_tmp5 ;
   unsigned char *__cil_tmp6 ;
   unsigned char __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
 
   {
 #line 1516
   v_table[0].vd = (u16 )0U;
 #line 1516
   v_table[0].vm = (u16 )0U;
 #line 1516
   v_table[1].vd = (u16 )375U;
 #line 1516
   v_table[1].vm = (u16 )0U;
 #line 1516
   v_table[2].vd = (u16 )500U;
 #line 1516
   v_table[2].vm = (u16 )0U;
 #line 1516
   v_table[3].vd = (u16 )625U;
 #line 1516
   v_table[3].vm = (u16 )0U;
 #line 1516
   v_table[4].vd = (u16 )750U;
 #line 1516
   v_table[4].vm = (u16 )0U;
 #line 1516
   v_table[5].vd = (u16 )875U;
 #line 1516
   v_table[5].vm = (u16 )0U;
 #line 1516
   v_table[6].vd = (u16 )1000U;
 #line 1516
   v_table[6].vm = (u16 )0U;
 #line 1516
   v_table[7].vd = (u16 )1125U;
 #line 1516
   v_table[7].vm = (u16 )0U;
 #line 1516
   v_table[8].vd = (u16 )4125U;
 #line 1516
   v_table[8].vm = (u16 )3000U;
 #line 1516
   v_table[9].vd = (u16 )4125U;
 #line 1516
   v_table[9].vm = (u16 )3000U;
 #line 1516
   v_table[10].vd = (u16 )4125U;
 #line 1516
   v_table[10].vm = (u16 )3000U;
 #line 1516
   v_table[11].vd = (u16 )4125U;
 #line 1516
   v_table[11].vm = (u16 )3000U;
 #line 1516
   v_table[12].vd = (u16 )4125U;
 #line 1516
   v_table[12].vm = (u16 )3000U;
 #line 1516
   v_table[13].vd = (u16 )4125U;
 #line 1516
   v_table[13].vm = (u16 )3000U;
 #line 1516
   v_table[14].vd = (u16 )4125U;
 #line 1516
   v_table[14].vm = (u16 )3000U;
 #line 1516
   v_table[15].vd = (u16 )4125U;
 #line 1516
   v_table[15].vm = (u16 )3000U;
 #line 1516
   v_table[16].vd = (u16 )4125U;
 #line 1516
   v_table[16].vm = (u16 )3000U;
 #line 1516
   v_table[17].vd = (u16 )4125U;
 #line 1516
   v_table[17].vm = (u16 )3000U;
 #line 1516
   v_table[18].vd = (u16 )4125U;
 #line 1516
   v_table[18].vm = (u16 )3000U;
 #line 1516
   v_table[19].vd = (u16 )4125U;
 #line 1516
   v_table[19].vm = (u16 )3000U;
 #line 1516
   v_table[20].vd = (u16 )4125U;
 #line 1516
   v_table[20].vm = (u16 )3000U;
 #line 1516
   v_table[21].vd = (u16 )4125U;
 #line 1516
   v_table[21].vm = (u16 )3000U;
 #line 1516
   v_table[22].vd = (u16 )4125U;
 #line 1516
   v_table[22].vm = (u16 )3000U;
 #line 1516
   v_table[23].vd = (u16 )4125U;
 #line 1516
   v_table[23].vm = (u16 )3000U;
 #line 1516
   v_table[24].vd = (u16 )4125U;
 #line 1516
   v_table[24].vm = (u16 )3000U;
 #line 1516
   v_table[25].vd = (u16 )4125U;
 #line 1516
   v_table[25].vm = (u16 )3000U;
 #line 1516
   v_table[26].vd = (u16 )4125U;
 #line 1516
   v_table[26].vm = (u16 )3000U;
 #line 1516
   v_table[27].vd = (u16 )4125U;
 #line 1516
   v_table[27].vm = (u16 )3000U;
 #line 1516
   v_table[28].vd = (u16 )4125U;
 #line 1516
   v_table[28].vm = (u16 )3000U;
 #line 1516
   v_table[29].vd = (u16 )4125U;
 #line 1516
   v_table[29].vm = (u16 )3000U;
 #line 1516
   v_table[30].vd = (u16 )4125U;
 #line 1516
   v_table[30].vm = (u16 )3000U;
 #line 1516
   v_table[31].vd = (u16 )4125U;
 #line 1516
   v_table[31].vm = (u16 )3000U;
 #line 1516
   v_table[32].vd = (u16 )4250U;
 #line 1516
   v_table[32].vm = (u16 )3125U;
 #line 1516
   v_table[33].vd = (u16 )4375U;
 #line 1516
   v_table[33].vm = (u16 )3250U;
 #line 1516
   v_table[34].vd = (u16 )4500U;
 #line 1516
   v_table[34].vm = (u16 )3375U;
 #line 1516
   v_table[35].vd = (u16 )4625U;
 #line 1516
   v_table[35].vm = (u16 )3500U;
 #line 1516
   v_table[36].vd = (u16 )4750U;
 #line 1516
   v_table[36].vm = (u16 )3625U;
 #line 1516
   v_table[37].vd = (u16 )4875U;
 #line 1516
   v_table[37].vm = (u16 )3750U;
 #line 1516
   v_table[38].vd = (u16 )5000U;
 #line 1516
   v_table[38].vm = (u16 )3875U;
 #line 1516
   v_table[39].vd = (u16 )5125U;
 #line 1516
   v_table[39].vm = (u16 )4000U;
 #line 1516
   v_table[40].vd = (u16 )5250U;
 #line 1516
   v_table[40].vm = (u16 )4125U;
 #line 1516
   v_table[41].vd = (u16 )5375U;
 #line 1516
   v_table[41].vm = (u16 )4250U;
 #line 1516
   v_table[42].vd = (u16 )5500U;
 #line 1516
   v_table[42].vm = (u16 )4375U;
 #line 1516
   v_table[43].vd = (u16 )5625U;
 #line 1516
   v_table[43].vm = (u16 )4500U;
 #line 1516
   v_table[44].vd = (u16 )5750U;
 #line 1516
   v_table[44].vm = (u16 )4625U;
 #line 1516
   v_table[45].vd = (u16 )5875U;
 #line 1516
   v_table[45].vm = (u16 )4750U;
 #line 1516
   v_table[46].vd = (u16 )6000U;
 #line 1516
   v_table[46].vm = (u16 )4875U;
 #line 1516
   v_table[47].vd = (u16 )6125U;
 #line 1516
   v_table[47].vm = (u16 )5000U;
 #line 1516
   v_table[48].vd = (u16 )6250U;
 #line 1516
   v_table[48].vm = (u16 )5125U;
 #line 1516
   v_table[49].vd = (u16 )6375U;
 #line 1516
   v_table[49].vm = (u16 )5250U;
 #line 1516
   v_table[50].vd = (u16 )6500U;
 #line 1516
   v_table[50].vm = (u16 )5375U;
 #line 1516
   v_table[51].vd = (u16 )6625U;
 #line 1516
   v_table[51].vm = (u16 )5500U;
 #line 1516
   v_table[52].vd = (u16 )6750U;
 #line 1516
   v_table[52].vm = (u16 )5625U;
 #line 1516
   v_table[53].vd = (u16 )6875U;
 #line 1516
   v_table[53].vm = (u16 )5750U;
 #line 1516
   v_table[54].vd = (u16 )7000U;
 #line 1516
   v_table[54].vm = (u16 )5875U;
 #line 1516
   v_table[55].vd = (u16 )7125U;
 #line 1516
   v_table[55].vm = (u16 )6000U;
 #line 1516
   v_table[56].vd = (u16 )7250U;
 #line 1516
   v_table[56].vm = (u16 )6125U;
 #line 1516
   v_table[57].vd = (u16 )7375U;
 #line 1516
   v_table[57].vm = (u16 )6250U;
 #line 1516
   v_table[58].vd = (u16 )7500U;
 #line 1516
   v_table[58].vm = (u16 )6375U;
 #line 1516
   v_table[59].vd = (u16 )7625U;
 #line 1516
   v_table[59].vm = (u16 )6500U;
 #line 1516
   v_table[60].vd = (u16 )7750U;
 #line 1516
   v_table[60].vm = (u16 )6625U;
 #line 1516
   v_table[61].vd = (u16 )7875U;
 #line 1516
   v_table[61].vm = (u16 )6750U;
 #line 1516
   v_table[62].vd = (u16 )8000U;
 #line 1516
   v_table[62].vm = (u16 )6875U;
 #line 1516
   v_table[63].vd = (u16 )8125U;
 #line 1516
   v_table[63].vm = (u16 )7000U;
 #line 1516
   v_table[64].vd = (u16 )8250U;
 #line 1516
   v_table[64].vm = (u16 )7125U;
 #line 1516
   v_table[65].vd = (u16 )8375U;
 #line 1516
   v_table[65].vm = (u16 )7250U;
 #line 1516
   v_table[66].vd = (u16 )8500U;
 #line 1516
   v_table[66].vm = (u16 )7375U;
 #line 1516
   v_table[67].vd = (u16 )8625U;
 #line 1516
   v_table[67].vm = (u16 )7500U;
 #line 1516
   v_table[68].vd = (u16 )8750U;
 #line 1516
   v_table[68].vm = (u16 )7625U;
 #line 1516
   v_table[69].vd = (u16 )8875U;
 #line 1516
   v_table[69].vm = (u16 )7750U;
 #line 1516
   v_table[70].vd = (u16 )9000U;
 #line 1516
   v_table[70].vm = (u16 )7875U;
 #line 1516
   v_table[71].vd = (u16 )9125U;
 #line 1516
   v_table[71].vm = (u16 )8000U;
 #line 1516
   v_table[72].vd = (u16 )9250U;
 #line 1516
   v_table[72].vm = (u16 )8125U;
 #line 1516
   v_table[73].vd = (u16 )9375U;
 #line 1516
   v_table[73].vm = (u16 )8250U;
 #line 1516
   v_table[74].vd = (u16 )9500U;
 #line 1516
   v_table[74].vm = (u16 )8375U;
 #line 1516
   v_table[75].vd = (u16 )9625U;
 #line 1516
   v_table[75].vm = (u16 )8500U;
 #line 1516
   v_table[76].vd = (u16 )9750U;
 #line 1516
   v_table[76].vm = (u16 )8625U;
 #line 1516
   v_table[77].vd = (u16 )9875U;
 #line 1516
   v_table[77].vm = (u16 )8750U;
 #line 1516
   v_table[78].vd = (u16 )10000U;
 #line 1516
   v_table[78].vm = (u16 )8875U;
 #line 1516
   v_table[79].vd = (u16 )10125U;
 #line 1516
   v_table[79].vm = (u16 )9000U;
 #line 1516
   v_table[80].vd = (u16 )10250U;
 #line 1516
   v_table[80].vm = (u16 )9125U;
 #line 1516
   v_table[81].vd = (u16 )10375U;
 #line 1516
   v_table[81].vm = (u16 )9250U;
 #line 1516
   v_table[82].vd = (u16 )10500U;
 #line 1516
   v_table[82].vm = (u16 )9375U;
 #line 1516
   v_table[83].vd = (u16 )10625U;
 #line 1516
   v_table[83].vm = (u16 )9500U;
 #line 1516
   v_table[84].vd = (u16 )10750U;
 #line 1516
   v_table[84].vm = (u16 )9625U;
 #line 1516
   v_table[85].vd = (u16 )10875U;
 #line 1516
   v_table[85].vm = (u16 )9750U;
 #line 1516
   v_table[86].vd = (u16 )11000U;
 #line 1516
   v_table[86].vm = (u16 )9875U;
 #line 1516
   v_table[87].vd = (u16 )11125U;
 #line 1516
   v_table[87].vm = (u16 )10000U;
 #line 1516
   v_table[88].vd = (u16 )11250U;
 #line 1516
   v_table[88].vm = (u16 )10125U;
 #line 1516
   v_table[89].vd = (u16 )11375U;
 #line 1516
   v_table[89].vm = (u16 )10250U;
 #line 1516
   v_table[90].vd = (u16 )11500U;
 #line 1516
   v_table[90].vm = (u16 )10375U;
 #line 1516
   v_table[91].vd = (u16 )11625U;
 #line 1516
   v_table[91].vm = (u16 )10500U;
 #line 1516
   v_table[92].vd = (u16 )11750U;
 #line 1516
   v_table[92].vm = (u16 )10625U;
 #line 1516
   v_table[93].vd = (u16 )11875U;
 #line 1516
   v_table[93].vm = (u16 )10750U;
 #line 1516
   v_table[94].vd = (u16 )12000U;
 #line 1516
   v_table[94].vm = (u16 )10875U;
 #line 1516
   v_table[95].vd = (u16 )12125U;
 #line 1516
   v_table[95].vm = (u16 )11000U;
 #line 1516
   v_table[96].vd = (u16 )12250U;
 #line 1516
   v_table[96].vm = (u16 )11125U;
 #line 1516
   v_table[97].vd = (u16 )12375U;
 #line 1516
   v_table[97].vm = (u16 )11250U;
 #line 1516
   v_table[98].vd = (u16 )12500U;
 #line 1516
   v_table[98].vm = (u16 )11375U;
 #line 1516
   v_table[99].vd = (u16 )12625U;
 #line 1516
   v_table[99].vm = (u16 )11500U;
 #line 1516
   v_table[100].vd = (u16 )12750U;
 #line 1516
   v_table[100].vm = (u16 )11625U;
 #line 1516
   v_table[101].vd = (u16 )12875U;
 #line 1516
   v_table[101].vm = (u16 )11750U;
 #line 1516
   v_table[102].vd = (u16 )13000U;
 #line 1516
   v_table[102].vm = (u16 )11875U;
 #line 1516
   v_table[103].vd = (u16 )13125U;
 #line 1516
   v_table[103].vm = (u16 )12000U;
 #line 1516
   v_table[104].vd = (u16 )13250U;
 #line 1516
   v_table[104].vm = (u16 )12125U;
 #line 1516
   v_table[105].vd = (u16 )13375U;
 #line 1516
   v_table[105].vm = (u16 )12250U;
 #line 1516
   v_table[106].vd = (u16 )13500U;
 #line 1516
   v_table[106].vm = (u16 )12375U;
 #line 1516
   v_table[107].vd = (u16 )13625U;
 #line 1516
   v_table[107].vm = (u16 )12500U;
 #line 1516
   v_table[108].vd = (u16 )13750U;
 #line 1516
   v_table[108].vm = (u16 )12625U;
 #line 1516
   v_table[109].vd = (u16 )13875U;
 #line 1516
   v_table[109].vm = (u16 )12750U;
 #line 1516
   v_table[110].vd = (u16 )14000U;
 #line 1516
   v_table[110].vm = (u16 )12875U;
 #line 1516
   v_table[111].vd = (u16 )14125U;
 #line 1516
   v_table[111].vm = (u16 )13000U;
 #line 1516
   v_table[112].vd = (u16 )14250U;
 #line 1516
   v_table[112].vm = (u16 )13125U;
 #line 1516
   v_table[113].vd = (u16 )14375U;
 #line 1516
   v_table[113].vm = (u16 )13250U;
 #line 1516
   v_table[114].vd = (u16 )14500U;
 #line 1516
   v_table[114].vm = (u16 )13375U;
 #line 1516
   v_table[115].vd = (u16 )14625U;
 #line 1516
   v_table[115].vm = (u16 )13500U;
 #line 1516
   v_table[116].vd = (u16 )14750U;
 #line 1516
   v_table[116].vm = (u16 )13625U;
 #line 1516
   v_table[117].vd = (u16 )14875U;
 #line 1516
   v_table[117].vm = (u16 )13750U;
 #line 1516
   v_table[118].vd = (u16 )15000U;
 #line 1516
   v_table[118].vm = (u16 )13875U;
 #line 1516
   v_table[119].vd = (u16 )15125U;
 #line 1516
   v_table[119].vm = (u16 )14000U;
 #line 1516
   v_table[120].vd = (u16 )15250U;
 #line 1516
   v_table[120].vm = (u16 )14125U;
 #line 1516
   v_table[121].vd = (u16 )15375U;
 #line 1516
   v_table[121].vm = (u16 )14250U;
 #line 1516
   v_table[122].vd = (u16 )15500U;
 #line 1516
   v_table[122].vm = (u16 )14375U;
 #line 1516
   v_table[123].vd = (u16 )15625U;
 #line 1516
   v_table[123].vm = (u16 )14500U;
 #line 1516
   v_table[124].vd = (u16 )15750U;
 #line 1516
   v_table[124].vm = (u16 )14625U;
 #line 1516
   v_table[125].vd = (u16 )15875U;
 #line 1516
   v_table[125].vm = (u16 )14750U;
 #line 1516
   v_table[126].vd = (u16 )16000U;
 #line 1516
   v_table[126].vm = (u16 )14875U;
 #line 1516
   v_table[127].vd = (u16 )16125U;
 #line 1516
   v_table[127].vm = (u16 )15000U;
   {
 #line 1646
   __cil_tmp4 = dev_priv->info;
 #line 1646
   __cil_tmp5 = (unsigned char *)__cil_tmp4;
 #line 1646
   __cil_tmp6 = __cil_tmp5 + 1UL;
 #line 1646
   __cil_tmp7 = *__cil_tmp6;
 #line 1646
   __cil_tmp8 = (unsigned int )__cil_tmp7;
 #line 1646
   if (__cil_tmp8 != 0U) {
 #line 1647
     return (v_table[(int )pxvid].vm);
   } else {
 #line 1649
     return (v_table[(int )pxvid].vd);
   }
   }
 }
 }
 #line 1652 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 void i915_update_gfx_val(struct drm_i915_private *dev_priv ) 
 { struct timespec now ;
   struct timespec diff1 ;
   u64 diff ;
   unsigned long diffms ;
   u32 count ;
   struct timespec __cil_tmp7 ;
   long __cil_tmp8 ;
   __kernel_time_t __cil_tmp9 ;
   __kernel_time_t __cil_tmp10 ;
   u64 __cil_tmp11 ;
   u64 __cil_tmp12 ;
   u64 __cil_tmp13 ;
   u64 __cil_tmp14 ;
   u64 __cil_tmp15 ;
   u64 __cil_tmp16 ;
   u32 __cil_tmp17 ;
   u32 __cil_tmp18 ;
 
   {
   {
 #line 1659
   getrawmonotonic(& now);
 #line 1660
   __cil_tmp7 = dev_priv->last_time2;
 #line 1660
   diff1 = timespec_sub(now, __cil_tmp7);
 #line 1663
   __cil_tmp8 = diff1.tv_nsec / 1000000L;
 #line 1663
   __cil_tmp9 = diff1.tv_sec * 1000L;
 #line 1663
   __cil_tmp10 = __cil_tmp9 + __cil_tmp8;
 #line 1663
   diffms = (unsigned long )__cil_tmp10;
   }
 #line 1664
   if (diffms == 0UL) {
 #line 1665
     return;
   } else {
 
   }
   {
 #line 1667
   count = i915_read32___0(dev_priv, 70388U);
   }
   {
 #line 1669
   __cil_tmp11 = dev_priv->last_count2;
 #line 1669
   __cil_tmp12 = (u64 )count;
 #line 1669
   if (__cil_tmp12 < __cil_tmp11) {
 #line 1670
     __cil_tmp13 = dev_priv->last_count2;
 #line 1670
     diff = ~ __cil_tmp13;
 #line 1671
     __cil_tmp14 = (u64 )count;
 #line 1671
     diff = __cil_tmp14 + diff;
   } else {
 #line 1673
     __cil_tmp15 = dev_priv->last_count2;
 #line 1673
     __cil_tmp16 = (u64 )count;
 #line 1673
     diff = __cil_tmp16 - __cil_tmp15;
   }
   }
   {
 #line 1676
   dev_priv->last_count2 = (u64 )count;
 #line 1677
   dev_priv->last_time2 = now;
 #line 1680
   diff = diff * 1181ULL;
 #line 1681
   __cil_tmp17 = (u32 )diffms;
 #line 1681
   __cil_tmp18 = __cil_tmp17 * 10U;
 #line 1681
   diff = div_u64(diff, __cil_tmp18);
 #line 1682
   dev_priv->gfx_power = (unsigned long )diff;
   }
 #line 1683
   return;
 }
 }
 #line 1685 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv ) 
 { unsigned long t ;
   unsigned long corr ;
   unsigned long state1 ;
   unsigned long corr2 ;
   unsigned long state2 ;
   u32 pxvid ;
   u32 ext_v ;
   u16 tmp ;
   u8 __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   u32 __cil_tmp15 ;
   u8 __cil_tmp16 ;
   int __cil_tmp17 ;
   u8 __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   u8 __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
 
   {
   {
 #line 1690
   __cil_tmp10 = dev_priv->cur_delay;
 #line 1690
   __cil_tmp11 = (int )__cil_tmp10;
 #line 1690
   __cil_tmp12 = __cil_tmp11 + 17476;
 #line 1690
   __cil_tmp13 = __cil_tmp12 * 4;
 #line 1690
   __cil_tmp14 = (u32 )__cil_tmp13;
 #line 1690
   pxvid = i915_read32___0(dev_priv, __cil_tmp14);
 #line 1691
   __cil_tmp15 = pxvid >> 24;
 #line 1691
   pxvid = __cil_tmp15 & 127U;
 #line 1692
   __cil_tmp16 = (u8 )pxvid;
 #line 1692
   __cil_tmp17 = (int )__cil_tmp16;
 #line 1692
   __cil_tmp18 = (u8 )__cil_tmp17;
 #line 1692
   tmp = pvid_to_extvid(dev_priv, __cil_tmp18);
 #line 1692
   ext_v = (u32 )tmp;
 #line 1694
   state1 = (unsigned long )ext_v;
 #line 1696
   t = i915_mch_val(dev_priv);
   }
 #line 1701
   if (t > 80UL) {
 #line 1702
     __cil_tmp19 = t * 2349UL;
 #line 1702
     corr = __cil_tmp19 + 135940UL;
   } else
 #line 1703
   if (t > 49UL) {
 #line 1704
     __cil_tmp20 = t * 964UL;
 #line 1704
     corr = __cil_tmp20 + 29317UL;
   } else {
 #line 1706
     __cil_tmp21 = t * 301UL;
 #line 1706
     corr = __cil_tmp21 + 1004UL;
   }
   {
 #line 1708
   __cil_tmp22 = state1 * 150142UL;
 #line 1708
   __cil_tmp23 = __cil_tmp22 / 10000UL;
 #line 1708
   __cil_tmp24 = __cil_tmp23 - 78642UL;
 #line 1708
   corr = __cil_tmp24 * corr;
 #line 1709
   corr = corr / 100000UL;
 #line 1710
   __cil_tmp25 = dev_priv->corr;
 #line 1710
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 1710
   corr2 = __cil_tmp26 * corr;
 #line 1712
   __cil_tmp27 = corr2 * state1;
 #line 1712
   state2 = __cil_tmp27 / 10000UL;
 #line 1713
   state2 = state2 / 100UL;
 #line 1715
   i915_update_gfx_val(dev_priv);
   }
   {
 #line 1717
   __cil_tmp28 = dev_priv->gfx_power;
 #line 1717
   return (__cil_tmp28 + state2);
   }
 }
 }
 #line 1721 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static struct drm_i915_private *i915_mch_dev  ;
 #line 1730 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static spinlock_t mchdev_lock  =    {{{{0U}, 3735899821U, 4294967295U, (void *)1152921504606846975UL, {(struct lock_class_key *)0,
                                                                       {(struct lock_class *)0,
                                                                        (struct lock_class *)0},
                                                                       "mchdev_lock",
                                                                       0, 0UL}}}};
 #line 1738 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 unsigned long i915_read_mch_val(void) 
 { struct drm_i915_private *dev_priv ;
   unsigned long chipset_val ;
   unsigned long graphics_val ;
   unsigned long ret ;
   struct drm_i915_private *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
 
   {
   {
 #line 1741
   ret = 0UL;
 #line 1743
   spin_lock(& mchdev_lock);
   }
   {
 #line 1744
   __cil_tmp5 = (struct drm_i915_private *)0;
 #line 1744
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 1744
   __cil_tmp7 = (unsigned long )i915_mch_dev;
 #line 1744
   if (__cil_tmp7 == __cil_tmp6) {
 #line 1745
     goto out_unlock;
   } else {
 
   }
   }
   {
 #line 1746
   dev_priv = i915_mch_dev;
 #line 1748
   chipset_val = i915_chipset_val(dev_priv);
 #line 1749
   graphics_val = i915_gfx_val(dev_priv);
 #line 1751
   ret = chipset_val + graphics_val;
   }
   out_unlock: 
   {
 #line 1754
   spin_unlock(& mchdev_lock);
   }
 #line 1756
   return (ret);
 }
 }
 #line 1765 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 bool i915_gpu_raise(void) 
 { struct drm_i915_private *dev_priv ;
   bool ret ;
   struct drm_i915_private *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   u8 __cil_tmp6 ;
   int __cil_tmp7 ;
   u8 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
 
   {
   {
 #line 1768
   ret = (bool )1;
 #line 1770
   spin_lock(& mchdev_lock);
   }
   {
 #line 1771
   __cil_tmp3 = (struct drm_i915_private *)0;
 #line 1771
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1771
   __cil_tmp5 = (unsigned long )i915_mch_dev;
 #line 1771
   if (__cil_tmp5 == __cil_tmp4) {
 #line 1772
     ret = (bool )0;
 #line 1773
     goto out_unlock;
   } else {
 
   }
   }
 #line 1775
   dev_priv = i915_mch_dev;
   {
 #line 1777
   __cil_tmp6 = dev_priv->fmax;
 #line 1777
   __cil_tmp7 = (int )__cil_tmp6;
 #line 1777
   __cil_tmp8 = dev_priv->max_delay;
 #line 1777
   __cil_tmp9 = (int )__cil_tmp8;
 #line 1777
   if (__cil_tmp9 > __cil_tmp7) {
 #line 1778
     __cil_tmp10 = dev_priv->max_delay;
 #line 1778
     __cil_tmp11 = (int )__cil_tmp10;
 #line 1778
     __cil_tmp12 = __cil_tmp11 - 1;
 #line 1778
     dev_priv->max_delay = (u8 )__cil_tmp12;
   } else {
 
   }
   }
   out_unlock: 
   {
 #line 1781
   spin_unlock(& mchdev_lock);
   }
 #line 1783
   return (ret);
 }
 }
 #line 1793 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 bool i915_gpu_lower(void) 
 { struct drm_i915_private *dev_priv ;
   bool ret ;
   struct drm_i915_private *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   u8 __cil_tmp6 ;
   int __cil_tmp7 ;
   u8 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
 
   {
   {
 #line 1796
   ret = (bool )1;
 #line 1798
   spin_lock(& mchdev_lock);
   }
   {
 #line 1799
   __cil_tmp3 = (struct drm_i915_private *)0;
 #line 1799
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1799
   __cil_tmp5 = (unsigned long )i915_mch_dev;
 #line 1799
   if (__cil_tmp5 == __cil_tmp4) {
 #line 1800
     ret = (bool )0;
 #line 1801
     goto out_unlock;
   } else {
 
   }
   }
 #line 1803
   dev_priv = i915_mch_dev;
   {
 #line 1805
   __cil_tmp6 = dev_priv->min_delay;
 #line 1805
   __cil_tmp7 = (int )__cil_tmp6;
 #line 1805
   __cil_tmp8 = dev_priv->max_delay;
 #line 1805
   __cil_tmp9 = (int )__cil_tmp8;
 #line 1805
   if (__cil_tmp9 < __cil_tmp7) {
 #line 1806
     __cil_tmp10 = dev_priv->max_delay;
 #line 1806
     __cil_tmp11 = (int )__cil_tmp10;
 #line 1806
     __cil_tmp12 = __cil_tmp11 + 1;
 #line 1806
     dev_priv->max_delay = (u8 )__cil_tmp12;
   } else {
 
   }
   }
   out_unlock: 
   {
 #line 1809
   spin_unlock(& mchdev_lock);
   }
 #line 1811
   return (ret);
 }
 }
 #line 1820 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 bool i915_gpu_busy(void) 
 { struct drm_i915_private *dev_priv ;
   bool ret ;
   struct drm_i915_private *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
 
   {
   {
 #line 1823
   ret = (bool )0;
 #line 1825
   spin_lock(& mchdev_lock);
   }
   {
 #line 1826
   __cil_tmp3 = (struct drm_i915_private *)0;
 #line 1826
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1826
   __cil_tmp5 = (unsigned long )i915_mch_dev;
 #line 1826
   if (__cil_tmp5 == __cil_tmp4) {
 #line 1827
     goto out_unlock;
   } else {
 
   }
   }
 #line 1828
   dev_priv = i915_mch_dev;
 #line 1830
   ret = dev_priv->busy;
   out_unlock: 
   {
 #line 1833
   spin_unlock(& mchdev_lock);
   }
 #line 1835
   return (ret);
 }
 }
 #line 1845 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 bool i915_gpu_turbo_disable(void) 
 { struct drm_i915_private *dev_priv ;
   bool ret ;
   bool tmp ;
   int tmp___0 ;
   struct drm_i915_private *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct drm_device *__cil_tmp8 ;
   u8 __cil_tmp9 ;
   int __cil_tmp10 ;
   u8 __cil_tmp11 ;
 
   {
   {
 #line 1848
   ret = (bool )1;
 #line 1850
   spin_lock(& mchdev_lock);
   }
   {
 #line 1851
   __cil_tmp5 = (struct drm_i915_private *)0;
 #line 1851
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 1851
   __cil_tmp7 = (unsigned long )i915_mch_dev;
 #line 1851
   if (__cil_tmp7 == __cil_tmp6) {
 #line 1852
     ret = (bool )0;
 #line 1853
     goto out_unlock;
   } else {
 
   }
   }
   {
 #line 1855
   dev_priv = i915_mch_dev;
 #line 1857
   dev_priv->max_delay = dev_priv->fstart;
 #line 1859
   __cil_tmp8 = dev_priv->dev;
 #line 1859
   __cil_tmp9 = dev_priv->fstart;
 #line 1859
   __cil_tmp10 = (int )__cil_tmp9;
 #line 1859
   __cil_tmp11 = (u8 )__cil_tmp10;
 #line 1859
   tmp = ironlake_set_drps(__cil_tmp8, __cil_tmp11);
   }
 #line 1859
   if (tmp) {
 #line 1859
     tmp___0 = 0;
   } else {
 #line 1859
     tmp___0 = 1;
   }
 #line 1859
   if (tmp___0) {
 #line 1860
     ret = (bool )0;
   } else {
 
   }
   out_unlock: 
   {
 #line 1863
   spin_unlock(& mchdev_lock);
   }
 #line 1865
   return (ret);
 }
 }
 #line 1878 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 static void ips_ping_for_i915_load(void) 
 { void (*link)(void) ;
   void *tmp ;
   void (*__cil_tmp3)(void) ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
 
   {
   {
 #line 1882
   tmp = __symbol_get("ips_link_to_i915_driver");
 #line 1882
   link = (void (*)(void))tmp;
   }
   {
 #line 1883
   __cil_tmp3 = (void (*)(void))0;
 #line 1883
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1883
   __cil_tmp5 = (unsigned long )link;
 #line 1883
   if (__cil_tmp5 != __cil_tmp4) {
     {
 #line 1884
     (*link)();
 #line 1885
     __symbol_put("ips_link_to_i915_driver");
     }
   } else {
 
   }
   }
 #line 1887
   return;
 }
 }
 #line 1900 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_driver_load(struct drm_device *dev , unsigned long flags ) 
 { struct drm_i915_private *dev_priv ;
   int ret ;
   int mmio_bar ;
   uint32_t agp_size ;
   void *tmp ;
   int tmp___0 ;
   struct lock_class_key __key ;
   char const   *__lock_name ;
   struct workqueue_struct *tmp___1 ;
   struct lock_class_key __key___0 ;
   struct lock_class_key __key___1 ;
   struct lock_class_key __key___2 ;
   int tmp___2 ;
   struct lock_class_key __key___3 ;
   unsigned long __cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   u8 __cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   struct pci_dev *__cil_tmp27 ;
   struct device *__cil_tmp28 ;
   void *__cil_tmp29 ;
   struct drm_i915_private *__cil_tmp30 ;
   struct intel_device_info  const  *__cil_tmp31 ;
   unsigned char *__cil_tmp32 ;
   unsigned char *__cil_tmp33 ;
   unsigned char __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   struct pci_dev *__cil_tmp36 ;
   struct device *__cil_tmp37 ;
   void *__cil_tmp38 ;
   struct drm_i915_private *__cil_tmp39 ;
   struct intel_device_info  const  *__cil_tmp40 ;
   unsigned char *__cil_tmp41 ;
   unsigned char *__cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   struct pci_dev *__cil_tmp45 ;
   struct device *__cil_tmp46 ;
   void *__cil_tmp47 ;
   struct drm_i915_private *__cil_tmp48 ;
   struct intel_device_info  const  *__cil_tmp49 ;
   u8 __cil_tmp50 ;
   unsigned char __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   struct pci_dev *__cil_tmp53 ;
   void *__cil_tmp54 ;
   unsigned long __cil_tmp55 ;
   void *__cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   struct intel_gtt  const  *__cil_tmp58 ;
   unsigned long __cil_tmp59 ;
   struct intel_gtt  const  *__cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   struct intel_gtt  const  *__cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   struct drm_agp_head *__cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   resource_size_t __cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   struct io_mapping *__cil_tmp69 ;
   unsigned long __cil_tmp70 ;
   struct io_mapping *__cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   struct drm_agp_head *__cil_tmp73 ;
   unsigned long __cil_tmp74 ;
   unsigned long __cil_tmp75 ;
   bool __cil_tmp76 ;
   int __cil_tmp77 ;
   struct workqueue_struct *__cil_tmp78 ;
   unsigned long __cil_tmp79 ;
   struct workqueue_struct *__cil_tmp80 ;
   unsigned long __cil_tmp81 ;
   void *__cil_tmp82 ;
   struct drm_i915_private *__cil_tmp83 ;
   struct intel_device_info  const  *__cil_tmp84 ;
   unsigned char *__cil_tmp85 ;
   unsigned char *__cil_tmp86 ;
   unsigned char __cil_tmp87 ;
   unsigned int __cil_tmp88 ;
   void *__cil_tmp89 ;
   struct drm_i915_private *__cil_tmp90 ;
   struct intel_device_info  const  *__cil_tmp91 ;
   unsigned char *__cil_tmp92 ;
   unsigned char *__cil_tmp93 ;
   unsigned char __cil_tmp94 ;
   unsigned int __cil_tmp95 ;
   void *__cil_tmp96 ;
   struct drm_i915_private *__cil_tmp97 ;
   struct intel_device_info  const  *__cil_tmp98 ;
   u8 __cil_tmp99 ;
   unsigned char __cil_tmp100 ;
   unsigned int __cil_tmp101 ;
   int __cil_tmp102 ;
   void *__cil_tmp103 ;
   struct drm_i915_private *__cil_tmp104 ;
   struct intel_device_info  const  *__cil_tmp105 ;
   unsigned char *__cil_tmp106 ;
   unsigned char *__cil_tmp107 ;
   unsigned char __cil_tmp108 ;
   unsigned int __cil_tmp109 ;
   struct pci_dev *__cil_tmp110 ;
   spinlock_t *__cil_tmp111 ;
   struct raw_spinlock *__cil_tmp112 ;
   spinlock_t *__cil_tmp113 ;
   struct raw_spinlock *__cil_tmp114 ;
   spinlock_t *__cil_tmp115 ;
   struct raw_spinlock *__cil_tmp116 ;
   void *__cil_tmp117 ;
   struct drm_i915_private *__cil_tmp118 ;
   struct intel_device_info  const  *__cil_tmp119 ;
   unsigned char *__cil_tmp120 ;
   unsigned char *__cil_tmp121 ;
   unsigned char __cil_tmp122 ;
   unsigned int __cil_tmp123 ;
   void *__cil_tmp124 ;
   struct drm_i915_private *__cil_tmp125 ;
   struct intel_device_info  const  *__cil_tmp126 ;
   u8 __cil_tmp127 ;
   unsigned char __cil_tmp128 ;
   unsigned int __cil_tmp129 ;
   int __cil_tmp130 ;
   struct timer_list *__cil_tmp131 ;
   unsigned long __cil_tmp132 ;
   int (*__cil_tmp133)(struct shrinker * , struct shrink_control * ) ;
   unsigned long __cil_tmp134 ;
   int (*__cil_tmp135)(struct shrinker * , struct shrink_control * ) ;
   unsigned long __cil_tmp136 ;
   struct shrinker *__cil_tmp137 ;
   struct pci_dev *__cil_tmp138 ;
   unsigned char *__cil_tmp139 ;
   unsigned char *__cil_tmp140 ;
   unsigned char __cil_tmp141 ;
   unsigned int __cil_tmp142 ;
   struct pci_dev *__cil_tmp143 ;
   struct workqueue_struct *__cil_tmp144 ;
   int __cil_tmp145 ;
   int __cil_tmp146 ;
   struct drm_agp_head *__cil_tmp147 ;
   unsigned long __cil_tmp148 ;
   struct drm_agp_head *__cil_tmp149 ;
   size_t __cil_tmp150 ;
   size_t __cil_tmp151 ;
   struct io_mapping *__cil_tmp152 ;
   struct pci_dev *__cil_tmp153 ;
   void *__cil_tmp154 ;
   struct pci_dev *__cil_tmp155 ;
   void const   *__cil_tmp156 ;
 
   {
   {
 #line 1903
   ret = 0;
 #line 1907
   __cil_tmp17 = dev->counters;
 #line 1907
   dev->counters = __cil_tmp17 + 4UL;
 #line 1908
   dev->types[6] = (enum drm_stat_type )9;
 #line 1909
   dev->types[7] = (enum drm_stat_type )10;
 #line 1910
   dev->types[8] = (enum drm_stat_type )11;
 #line 1911
   dev->types[9] = (enum drm_stat_type )12;
 #line 1913
   tmp = kzalloc(7688UL, 208U);
 #line 1913
   dev_priv = (struct drm_i915_private *)tmp;
   }
   {
 #line 1914
   __cil_tmp18 = (struct drm_i915_private *)0;
 #line 1914
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 1914
   __cil_tmp20 = (unsigned long )dev_priv;
 #line 1914
   if (__cil_tmp20 == __cil_tmp19) {
 #line 1915
     return (-12);
   } else {
 
   }
   }
   {
 #line 1917
   dev->dev_private = (void *)dev_priv;
 #line 1918
   dev_priv->dev = dev;
 #line 1919
   dev_priv->info = (struct intel_device_info  const  *)flags;
 #line 1921
   tmp___0 = i915_get_bridge_dev(dev);
   }
 #line 1921
   if (tmp___0 != 0) {
 #line 1922
     ret = -5;
 #line 1923
     goto free_priv;
   } else {
 
   }
   {
 #line 1927
   __cil_tmp21 = dev->dev_private;
 #line 1927
   __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 1927
   __cil_tmp23 = __cil_tmp22->info;
 #line 1927
   __cil_tmp24 = __cil_tmp23->gen;
 #line 1927
   __cil_tmp25 = (unsigned char )__cil_tmp24;
 #line 1927
   __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 1927
   if (__cil_tmp26 == 2U) {
     {
 #line 1928
     __cil_tmp27 = dev->pdev;
 #line 1928
     __cil_tmp28 = & __cil_tmp27->dev;
 #line 1928
     dma_set_coherent_mask(__cil_tmp28, 1073741823ULL);
     }
   } else {
 
   }
   }
   {
 #line 1938
   __cil_tmp29 = dev->dev_private;
 #line 1938
   __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
 #line 1938
   __cil_tmp31 = __cil_tmp30->info;
 #line 1938
   __cil_tmp32 = (unsigned char *)__cil_tmp31;
 #line 1938
   __cil_tmp33 = __cil_tmp32 + 2UL;
 #line 1938
   __cil_tmp34 = *__cil_tmp33;
 #line 1938
   __cil_tmp35 = (unsigned int )__cil_tmp34;
 #line 1938
   if (__cil_tmp35 != 0U) {
     {
 #line 1939
     __cil_tmp36 = dev->pdev;
 #line 1939
     __cil_tmp37 = & __cil_tmp36->dev;
 #line 1939
     dma_set_coherent_mask(__cil_tmp37, 4294967295ULL);
     }
   } else {
     {
 #line 1938
     __cil_tmp38 = dev->dev_private;
 #line 1938
     __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
 #line 1938
     __cil_tmp40 = __cil_tmp39->info;
 #line 1938
     __cil_tmp41 = (unsigned char *)__cil_tmp40;
 #line 1938
     __cil_tmp42 = __cil_tmp41 + 2UL;
 #line 1938
     __cil_tmp43 = *__cil_tmp42;
 #line 1938
     __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 1938
     if (__cil_tmp44 != 0U) {
       {
 #line 1939
       __cil_tmp45 = dev->pdev;
 #line 1939
       __cil_tmp46 = & __cil_tmp45->dev;
 #line 1939
       dma_set_coherent_mask(__cil_tmp46, 4294967295ULL);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 1941
   __cil_tmp47 = dev->dev_private;
 #line 1941
   __cil_tmp48 = (struct drm_i915_private *)__cil_tmp47;
 #line 1941
   __cil_tmp49 = __cil_tmp48->info;
 #line 1941
   __cil_tmp50 = __cil_tmp49->gen;
 #line 1941
   __cil_tmp51 = (unsigned char )__cil_tmp50;
 #line 1941
   __cil_tmp52 = (unsigned int )__cil_tmp51;
 #line 1941
   mmio_bar = __cil_tmp52 == 2U;
 #line 1942
   __cil_tmp53 = dev->pdev;
 #line 1942
   dev_priv->regs = pci_iomap(__cil_tmp53, mmio_bar, 0UL);
   }
   {
 #line 1943
   __cil_tmp54 = (void *)0;
 #line 1943
   __cil_tmp55 = (unsigned long )__cil_tmp54;
 #line 1943
   __cil_tmp56 = dev_priv->regs;
 #line 1943
   __cil_tmp57 = (unsigned long )__cil_tmp56;
 #line 1943
   if (__cil_tmp57 == __cil_tmp55) {
     {
 #line 1944
     drm_err("i915_driver_load", "failed to map registers\n");
 #line 1945
     ret = -5;
     }
 #line 1946
     goto put_bridge;
   } else {
 
   }
   }
   {
 #line 1949
   dev_priv->mm.gtt = intel_gtt_get();
   }
   {
 #line 1950
   __cil_tmp58 = (struct intel_gtt  const  *)0;
 #line 1950
   __cil_tmp59 = (unsigned long )__cil_tmp58;
 #line 1950
   __cil_tmp60 = dev_priv->mm.gtt;
 #line 1950
   __cil_tmp61 = (unsigned long )__cil_tmp60;
 #line 1950
   if (__cil_tmp61 == __cil_tmp59) {
     {
 #line 1951
     drm_err("i915_driver_load", "Failed to initialize GTT\n");
 #line 1952
     ret = -19;
     }
 #line 1953
     goto out_rmmap;
   } else {
 
   }
   }
   {
 #line 1956
   __cil_tmp62 = dev_priv->mm.gtt;
 #line 1956
   __cil_tmp63 = __cil_tmp62->gtt_mappable_entries;
 #line 1956
   __cil_tmp64 = __cil_tmp63 << 12;
 #line 1956
   agp_size = (uint32_t )__cil_tmp64;
 #line 1958
   __cil_tmp65 = dev->agp;
 #line 1958
   __cil_tmp66 = __cil_tmp65->base;
 #line 1958
   __cil_tmp67 = (resource_size_t )__cil_tmp66;
 #line 1958
   __cil_tmp68 = (unsigned long )agp_size;
 #line 1958
   dev_priv->mm.gtt_mapping = io_mapping_create_wc(__cil_tmp67, __cil_tmp68);
   }
   {
 #line 1960
   __cil_tmp69 = (struct io_mapping *)0;
 #line 1960
   __cil_tmp70 = (unsigned long )__cil_tmp69;
 #line 1960
   __cil_tmp71 = dev_priv->mm.gtt_mapping;
 #line 1960
   __cil_tmp72 = (unsigned long )__cil_tmp71;
 #line 1960
   if (__cil_tmp72 == __cil_tmp70) {
 #line 1961
     ret = -5;
 #line 1962
     goto out_rmmap;
   } else {
 
   }
   }
   {
 #line 1970
   __cil_tmp73 = dev->agp;
 #line 1970
   __cil_tmp74 = __cil_tmp73->base;
 #line 1970
   __cil_tmp75 = (unsigned long )agp_size;
 #line 1970
   __cil_tmp76 = (bool )1;
 #line 1970
   dev_priv->mm.gtt_mtrr = mtrr_add(__cil_tmp74, __cil_tmp75, 1U, __cil_tmp76);
   }
   {
 #line 1973
   __cil_tmp77 = dev_priv->mm.gtt_mtrr;
 #line 1973
   if (__cil_tmp77 < 0) {
     {
 #line 1974
     printk("<6>[drm] MTRR allocation failed.  Graphics performance may suffer.\n");
     }
   } else {
 
   }
   }
   {
 #line 1991
   __lock_name = "i915";
 #line 1991
   tmp___1 = __alloc_workqueue_key("i915", 3U, 1, & __key, __lock_name);
 #line 1991
   dev_priv->wq = tmp___1;
   }
   {
 #line 1994
   __cil_tmp78 = (struct workqueue_struct *)0;
 #line 1994
   __cil_tmp79 = (unsigned long )__cil_tmp78;
 #line 1994
   __cil_tmp80 = dev_priv->wq;
 #line 1994
   __cil_tmp81 = (unsigned long )__cil_tmp80;
 #line 1994
   if (__cil_tmp81 == __cil_tmp79) {
     {
 #line 1995
     drm_err("i915_driver_load", "Failed to create our workqueue.\n");
 #line 1996
     ret = -12;
     }
 #line 1997
     goto out_mtrrfree;
   } else {
 
   }
   }
   {
 #line 2001
   dev_priv->has_gem = 1;
 #line 2003
   intel_irq_init(dev);
 #line 2006
   intel_setup_mchbar(dev);
 #line 2007
   intel_setup_gmbus(dev);
 #line 2008
   intel_opregion_setup(dev);
 #line 2011
   intel_setup_bios(dev);
 #line 2013
   i915_gem_load(dev);
   }
   {
 #line 2016
   __cil_tmp82 = dev->dev_private;
 #line 2016
   __cil_tmp83 = (struct drm_i915_private *)__cil_tmp82;
 #line 2016
   __cil_tmp84 = __cil_tmp83->info;
 #line 2016
   __cil_tmp85 = (unsigned char *)__cil_tmp84;
 #line 2016
   __cil_tmp86 = __cil_tmp85 + 1UL;
 #line 2016
   __cil_tmp87 = *__cil_tmp86;
 #line 2016
   __cil_tmp88 = (unsigned int )__cil_tmp87;
 #line 2016
   if (__cil_tmp88 == 0U) {
     {
 #line 2017
     ret = i915_init_phys_hws(dev);
     }
 #line 2018
     if (ret != 0) {
 #line 2019
       goto out_gem_unload;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 2022
   __cil_tmp89 = dev->dev_private;
 #line 2022
   __cil_tmp90 = (struct drm_i915_private *)__cil_tmp89;
 #line 2022
   __cil_tmp91 = __cil_tmp90->info;
 #line 2022
   __cil_tmp92 = (unsigned char *)__cil_tmp91;
 #line 2022
   __cil_tmp93 = __cil_tmp92 + 1UL;
 #line 2022
   __cil_tmp94 = *__cil_tmp93;
 #line 2022
   __cil_tmp95 = (unsigned int )__cil_tmp94;
 #line 2022
   if (__cil_tmp95 != 0U) {
     {
 #line 2023
     i915_pineview_get_mem_freq(dev);
     }
   } else {
     {
 #line 2024
     __cil_tmp96 = dev->dev_private;
 #line 2024
     __cil_tmp97 = (struct drm_i915_private *)__cil_tmp96;
 #line 2024
     __cil_tmp98 = __cil_tmp97->info;
 #line 2024
     __cil_tmp99 = __cil_tmp98->gen;
 #line 2024
     __cil_tmp100 = (unsigned char )__cil_tmp99;
 #line 2024
     __cil_tmp101 = (unsigned int )__cil_tmp100;
 #line 2024
     if (__cil_tmp101 == 5U) {
       {
 #line 2025
       i915_ironlake_get_mem_freq(dev);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 2038
   __cil_tmp102 = dev->pci_device;
 #line 2038
   if (__cil_tmp102 != 10098) {
     {
 #line 2038
     __cil_tmp103 = dev->dev_private;
 #line 2038
     __cil_tmp104 = (struct drm_i915_private *)__cil_tmp103;
 #line 2038
     __cil_tmp105 = __cil_tmp104->info;
 #line 2038
     __cil_tmp106 = (unsigned char *)__cil_tmp105;
 #line 2038
     __cil_tmp107 = __cil_tmp106 + 1UL;
 #line 2038
     __cil_tmp108 = *__cil_tmp107;
 #line 2038
     __cil_tmp109 = (unsigned int )__cil_tmp108;
 #line 2038
     if (__cil_tmp109 == 0U) {
       {
 #line 2039
       __cil_tmp110 = dev->pdev;
 #line 2039
       pci_enable_msi_block(__cil_tmp110, 1U);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 2041
   __cil_tmp111 = & dev_priv->irq_lock;
 #line 2041
   spinlock_check(__cil_tmp111);
 #line 2041
   __cil_tmp112 = & dev_priv->irq_lock.ldv_6060.rlock;
 #line 2041
   __raw_spin_lock_init(__cil_tmp112, "&(&dev_priv->irq_lock)->rlock", & __key___0);
 #line 2042
   __cil_tmp113 = & dev_priv->error_lock;
 #line 2042
   spinlock_check(__cil_tmp113);
 #line 2042
   __cil_tmp114 = & dev_priv->error_lock.ldv_6060.rlock;
 #line 2042
   __raw_spin_lock_init(__cil_tmp114, "&(&dev_priv->error_lock)->rlock", & __key___1);
 #line 2043
   __cil_tmp115 = & dev_priv->rps_lock;
 #line 2043
   spinlock_check(__cil_tmp115);
 #line 2043
   __cil_tmp116 = & dev_priv->rps_lock.ldv_6060.rlock;
 #line 2043
   __raw_spin_lock_init(__cil_tmp116, "&(&dev_priv->rps_lock)->rlock", & __key___2);
   }
   {
 #line 2045
   __cil_tmp117 = dev->dev_private;
 #line 2045
   __cil_tmp118 = (struct drm_i915_private *)__cil_tmp117;
 #line 2045
   __cil_tmp119 = __cil_tmp118->info;
 #line 2045
   __cil_tmp120 = (unsigned char *)__cil_tmp119;
 #line 2045
   __cil_tmp121 = __cil_tmp120 + 1UL;
 #line 2045
   __cil_tmp122 = *__cil_tmp121;
 #line 2045
   __cil_tmp123 = (unsigned int )__cil_tmp122;
 #line 2045
   if (__cil_tmp123 != 0U) {
 #line 2046
     dev_priv->num_pipe = 2;
   } else {
     {
 #line 2045
     __cil_tmp124 = dev->dev_private;
 #line 2045
     __cil_tmp125 = (struct drm_i915_private *)__cil_tmp124;
 #line 2045
     __cil_tmp126 = __cil_tmp125->info;
 #line 2045
     __cil_tmp127 = __cil_tmp126->gen;
 #line 2045
     __cil_tmp128 = (unsigned char )__cil_tmp127;
 #line 2045
     __cil_tmp129 = (unsigned int )__cil_tmp128;
 #line 2045
     if (__cil_tmp129 != 2U) {
 #line 2046
       dev_priv->num_pipe = 2;
     } else {
 #line 2048
       dev_priv->num_pipe = 1;
     }
     }
   }
   }
   {
 #line 2050
   __cil_tmp130 = dev_priv->num_pipe;
 #line 2050
   ret = drm_vblank_init(dev, __cil_tmp130);
   }
 #line 2051
   if (ret != 0) {
 #line 2052
     goto out_gem_unload;
   } else {
 
   }
   {
 #line 2055
   dev_priv->mm.suspended = 1;
 #line 2057
   intel_detect_pch(dev);
 #line 2059
   tmp___2 = drm_core_check_feature(dev, 8192);
   }
 #line 2059
   if (tmp___2 != 0) {
     {
 #line 2060
     ret = i915_load_modeset_init(dev);
     }
 #line 2061
     if (ret < 0) {
       {
 #line 2062
       drm_err("i915_driver_load", "failed to init modeset\n");
       }
 #line 2063
       goto out_gem_unload;
     } else {
 
     }
   } else {
 
   }
   {
 #line 2068
   intel_opregion_init(dev);
 #line 2069
   acpi_video_register();
 #line 2071
   __cil_tmp131 = & dev_priv->hangcheck_timer;
 #line 2071
   __cil_tmp132 = (unsigned long )dev;
 #line 2071
   setup_timer_key(__cil_tmp131, "&dev_priv->hangcheck_timer", & __key___3, & i915_hangcheck_elapsed,
                   __cil_tmp132);
 #line 2074
   spin_lock(& mchdev_lock);
 #line 2075
   i915_mch_dev = dev_priv;
 #line 2076
   dev_priv->mchdev_lock = & mchdev_lock;
 #line 2077
   spin_unlock(& mchdev_lock);
 #line 2079
   ips_ping_for_i915_load();
   }
 #line 2081
   return (0);
   out_gem_unload: ;
   {
 #line 2084
   __cil_tmp133 = (int (*)(struct shrinker * , struct shrink_control * ))0;
 #line 2084
   __cil_tmp134 = (unsigned long )__cil_tmp133;
 #line 2084
   __cil_tmp135 = dev_priv->mm.inactive_shrinker.shrink;
 #line 2084
   __cil_tmp136 = (unsigned long )__cil_tmp135;
 #line 2084
   if (__cil_tmp136 != __cil_tmp134) {
     {
 #line 2085
     __cil_tmp137 = & dev_priv->mm.inactive_shrinker;
 #line 2085
     unregister_shrinker(__cil_tmp137);
     }
   } else {
 
   }
   }
   {
 #line 2087
   __cil_tmp138 = dev->pdev;
 #line 2087
   __cil_tmp139 = (unsigned char *)__cil_tmp138;
 #line 2087
   __cil_tmp140 = __cil_tmp139 + 2417UL;
 #line 2087
   __cil_tmp141 = *__cil_tmp140;
 #line 2087
   __cil_tmp142 = (unsigned int )__cil_tmp141;
 #line 2087
   if (__cil_tmp142 != 0U) {
     {
 #line 2088
     __cil_tmp143 = dev->pdev;
 #line 2088
     pci_disable_msi(__cil_tmp143);
     }
   } else {
 
   }
   }
   {
 #line 2090
   intel_teardown_gmbus(dev);
 #line 2091
   intel_teardown_mchbar(dev);
 #line 2092
   __cil_tmp144 = dev_priv->wq;
 #line 2092
   destroy_workqueue(__cil_tmp144);
   }
   out_mtrrfree: ;
   {
 #line 2094
   __cil_tmp145 = dev_priv->mm.gtt_mtrr;
 #line 2094
   if (__cil_tmp145 >= 0) {
     {
 #line 2095
     __cil_tmp146 = dev_priv->mm.gtt_mtrr;
 #line 2095
     __cil_tmp147 = dev->agp;
 #line 2095
     __cil_tmp148 = __cil_tmp147->base;
 #line 2095
     __cil_tmp149 = dev->agp;
 #line 2095
     __cil_tmp150 = __cil_tmp149->agp_info.aper_size;
 #line 2095
     __cil_tmp151 = __cil_tmp150 * 1048576UL;
 #line 2095
     mtrr_del(__cil_tmp146, __cil_tmp148, __cil_tmp151);
 #line 2097
     dev_priv->mm.gtt_mtrr = -1;
     }
   } else {
 
   }
   }
   {
 #line 2099
   __cil_tmp152 = dev_priv->mm.gtt_mapping;
 #line 2099
   io_mapping_free(__cil_tmp152);
   }
   out_rmmap: 
   {
 #line 2101
   __cil_tmp153 = dev->pdev;
 #line 2101
   __cil_tmp154 = dev_priv->regs;
 #line 2101
   pci_iounmap(__cil_tmp153, __cil_tmp154);
   }
   put_bridge: 
   {
 #line 2103
   __cil_tmp155 = dev_priv->bridge_dev;
 #line 2103
   pci_dev_put(__cil_tmp155);
   }
   free_priv: 
   {
 #line 2105
   __cil_tmp156 = (void const   *)dev_priv;
 #line 2105
   kfree(__cil_tmp156);
   }
 #line 2106
   return (ret);
 }
 }
 #line 2109 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_driver_unload(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int ret ;
   int tmp ;
   int tmp___0 ;
   void *__cil_tmp6 ;
   int (*__cil_tmp7)(struct shrinker * , struct shrink_control * ) ;
   unsigned long __cil_tmp8 ;
   int (*__cil_tmp9)(struct shrinker * , struct shrink_control * ) ;
   unsigned long __cil_tmp10 ;
   struct shrinker *__cil_tmp11 ;
   struct mutex *__cil_tmp12 ;
   struct mutex *__cil_tmp13 ;
   struct delayed_work *__cil_tmp14 ;
   struct io_mapping *__cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   struct drm_agp_head *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct drm_agp_head *__cil_tmp20 ;
   size_t __cil_tmp21 ;
   size_t __cil_tmp22 ;
   struct child_device_config *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct child_device_config *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   int __cil_tmp27 ;
   struct child_device_config *__cil_tmp28 ;
   void const   *__cil_tmp29 ;
   struct pci_dev *__cil_tmp30 ;
   struct pci_dev *__cil_tmp31 ;
   void *__cil_tmp32 ;
   void (*__cil_tmp33)(void * , bool  ) ;
   unsigned int (*__cil_tmp34)(void * , bool  ) ;
   struct timer_list *__cil_tmp35 ;
   struct work_struct *__cil_tmp36 ;
   struct pci_dev *__cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct pci_dev *__cil_tmp42 ;
   struct workqueue_struct *__cil_tmp43 ;
   struct mutex *__cil_tmp44 ;
   struct mutex *__cil_tmp45 ;
   void *__cil_tmp46 ;
   struct drm_i915_private *__cil_tmp47 ;
   struct intel_device_info  const  *__cil_tmp48 ;
   unsigned char *__cil_tmp49 ;
   unsigned char *__cil_tmp50 ;
   unsigned char __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   struct drm_mm *__cil_tmp53 ;
   void *__cil_tmp54 ;
   struct drm_i915_private *__cil_tmp55 ;
   struct intel_device_info  const  *__cil_tmp56 ;
   unsigned char *__cil_tmp57 ;
   unsigned char *__cil_tmp58 ;
   unsigned char __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   void *__cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   void *__cil_tmp63 ;
   unsigned long __cil_tmp64 ;
   struct pci_dev *__cil_tmp65 ;
   void *__cil_tmp66 ;
   struct workqueue_struct *__cil_tmp67 ;
   struct pci_dev *__cil_tmp68 ;
   void *__cil_tmp69 ;
   void const   *__cil_tmp70 ;
 
   {
   {
 #line 2111
   __cil_tmp6 = dev->dev_private;
 #line 2111
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
 #line 2114
   spin_lock(& mchdev_lock);
 #line 2115
   i915_mch_dev = (struct drm_i915_private *)0;
 #line 2116
   spin_unlock(& mchdev_lock);
   }
   {
 #line 2118
   __cil_tmp7 = (int (*)(struct shrinker * , struct shrink_control * ))0;
 #line 2118
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 2118
   __cil_tmp9 = dev_priv->mm.inactive_shrinker.shrink;
 #line 2118
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 2118
   if (__cil_tmp10 != __cil_tmp8) {
     {
 #line 2119
     __cil_tmp11 = & dev_priv->mm.inactive_shrinker;
 #line 2119
     unregister_shrinker(__cil_tmp11);
     }
   } else {
 
   }
   }
   {
 #line 2121
   __cil_tmp12 = & dev->struct_mutex;
 #line 2121
   mutex_lock_nested(__cil_tmp12, 0U);
 #line 2122
   ret = i915_gpu_idle(dev);
   }
 #line 2123
   if (ret != 0) {
     {
 #line 2124
     drm_err("i915_driver_unload", "failed to idle hardware: %d\n", ret);
     }
   } else {
 
   }
   {
 #line 2125
   __cil_tmp13 = & dev->struct_mutex;
 #line 2125
   mutex_unlock(__cil_tmp13);
 #line 2128
   __cil_tmp14 = & dev_priv->mm.retire_work;
 #line 2128
   cancel_delayed_work_sync(__cil_tmp14);
 #line 2130
   __cil_tmp15 = dev_priv->mm.gtt_mapping;
 #line 2130
   io_mapping_free(__cil_tmp15);
   }
   {
 #line 2131
   __cil_tmp16 = dev_priv->mm.gtt_mtrr;
 #line 2131
   if (__cil_tmp16 >= 0) {
     {
 #line 2132
     __cil_tmp17 = dev_priv->mm.gtt_mtrr;
 #line 2132
     __cil_tmp18 = dev->agp;
 #line 2132
     __cil_tmp19 = __cil_tmp18->base;
 #line 2132
     __cil_tmp20 = dev->agp;
 #line 2132
     __cil_tmp21 = __cil_tmp20->agp_info.aper_size;
 #line 2132
     __cil_tmp22 = __cil_tmp21 * 1048576UL;
 #line 2132
     mtrr_del(__cil_tmp17, __cil_tmp19, __cil_tmp22);
 #line 2134
     dev_priv->mm.gtt_mtrr = -1;
     }
   } else {
 
   }
   }
   {
 #line 2137
   acpi_video_unregister();
 #line 2139
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 2139
   if (tmp != 0) {
     {
 #line 2140
     intel_fbdev_fini(dev);
 #line 2141
     intel_modeset_cleanup(dev);
     }
     {
 #line 2147
     __cil_tmp23 = (struct child_device_config *)0;
 #line 2147
     __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 2147
     __cil_tmp25 = dev_priv->child_dev;
 #line 2147
     __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 2147
     if (__cil_tmp26 != __cil_tmp24) {
       {
 #line 2147
       __cil_tmp27 = dev_priv->child_dev_num;
 #line 2147
       if (__cil_tmp27 != 0) {
         {
 #line 2148
         __cil_tmp28 = dev_priv->child_dev;
 #line 2148
         __cil_tmp29 = (void const   *)__cil_tmp28;
 #line 2148
         kfree(__cil_tmp29);
 #line 2149
         dev_priv->child_dev = (struct child_device_config *)0;
 #line 2150
         dev_priv->child_dev_num = 0;
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
     {
 #line 2153
     __cil_tmp30 = dev->pdev;
 #line 2153
     vga_switcheroo_unregister_client(__cil_tmp30);
 #line 2154
     __cil_tmp31 = dev->pdev;
 #line 2154
     __cil_tmp32 = (void *)0;
 #line 2154
     __cil_tmp33 = (void (*)(void * , bool  ))0;
 #line 2154
     __cil_tmp34 = (unsigned int (*)(void * , bool  ))0;
 #line 2154
     vga_client_register(__cil_tmp31, __cil_tmp32, __cil_tmp33, __cil_tmp34);
     }
   } else {
 
   }
   {
 #line 2158
   __cil_tmp35 = & dev_priv->hangcheck_timer;
 #line 2158
   del_timer_sync(__cil_tmp35);
 #line 2159
   __cil_tmp36 = & dev_priv->error_work;
 #line 2159
   cancel_work_sync(__cil_tmp36);
 #line 2160
   i915_destroy_error_state(dev);
   }
   {
 #line 2162
   __cil_tmp37 = dev->pdev;
 #line 2162
   __cil_tmp38 = (unsigned char *)__cil_tmp37;
 #line 2162
   __cil_tmp39 = __cil_tmp38 + 2417UL;
 #line 2162
   __cil_tmp40 = *__cil_tmp39;
 #line 2162
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 2162
   if (__cil_tmp41 != 0U) {
     {
 #line 2163
     __cil_tmp42 = dev->pdev;
 #line 2163
     pci_disable_msi(__cil_tmp42);
     }
   } else {
 
   }
   }
   {
 #line 2165
   intel_opregion_fini(dev);
 #line 2167
   tmp___0 = drm_core_check_feature(dev, 8192);
   }
 #line 2167
   if (tmp___0 != 0) {
     {
 #line 2169
     __cil_tmp43 = dev_priv->wq;
 #line 2169
     flush_workqueue(__cil_tmp43);
 #line 2171
     __cil_tmp44 = & dev->struct_mutex;
 #line 2171
     mutex_lock_nested(__cil_tmp44, 0U);
 #line 2172
     i915_gem_free_all_phys_object(dev);
 #line 2173
     i915_gem_cleanup_ringbuffer(dev);
 #line 2174
     __cil_tmp45 = & dev->struct_mutex;
 #line 2174
     mutex_unlock(__cil_tmp45);
     }
     {
 #line 2175
     __cil_tmp46 = dev->dev_private;
 #line 2175
     __cil_tmp47 = (struct drm_i915_private *)__cil_tmp46;
 #line 2175
     __cil_tmp48 = __cil_tmp47->info;
 #line 2175
     __cil_tmp49 = (unsigned char *)__cil_tmp48;
 #line 2175
     __cil_tmp50 = __cil_tmp49 + 2UL;
 #line 2175
     __cil_tmp51 = *__cil_tmp50;
 #line 2175
     __cil_tmp52 = (unsigned int )__cil_tmp51;
 #line 2175
     if (__cil_tmp52 != 0U) {
 #line 2175
       if (i915_powersave != 0U) {
         {
 #line 2176
         i915_cleanup_compression(dev);
         }
       } else {
 
       }
     } else {
 
     }
     }
     {
 #line 2177
     __cil_tmp53 = & dev_priv->mm.stolen;
 #line 2177
     drm_mm_takedown(__cil_tmp53);
 #line 2179
     intel_cleanup_overlay(dev);
     }
     {
 #line 2181
     __cil_tmp54 = dev->dev_private;
 #line 2181
     __cil_tmp55 = (struct drm_i915_private *)__cil_tmp54;
 #line 2181
     __cil_tmp56 = __cil_tmp55->info;
 #line 2181
     __cil_tmp57 = (unsigned char *)__cil_tmp56;
 #line 2181
     __cil_tmp58 = __cil_tmp57 + 1UL;
 #line 2181
     __cil_tmp59 = *__cil_tmp58;
 #line 2181
     __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 2181
     if (__cil_tmp60 == 0U) {
       {
 #line 2182
       i915_free_hws(dev);
       }
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 2185
   __cil_tmp61 = (void *)0;
 #line 2185
   __cil_tmp62 = (unsigned long )__cil_tmp61;
 #line 2185
   __cil_tmp63 = dev_priv->regs;
 #line 2185
   __cil_tmp64 = (unsigned long )__cil_tmp63;
 #line 2185
   if (__cil_tmp64 != __cil_tmp62) {
     {
 #line 2186
     __cil_tmp65 = dev->pdev;
 #line 2186
     __cil_tmp66 = dev_priv->regs;
 #line 2186
     pci_iounmap(__cil_tmp65, __cil_tmp66);
     }
   } else {
 
   }
   }
   {
 #line 2188
   intel_teardown_gmbus(dev);
 #line 2189
   intel_teardown_mchbar(dev);
 #line 2191
   __cil_tmp67 = dev_priv->wq;
 #line 2191
   destroy_workqueue(__cil_tmp67);
 #line 2193
   __cil_tmp68 = dev_priv->bridge_dev;
 #line 2193
   pci_dev_put(__cil_tmp68);
 #line 2194
   __cil_tmp69 = dev->dev_private;
 #line 2194
   __cil_tmp70 = (void const   *)__cil_tmp69;
 #line 2194
   kfree(__cil_tmp70);
   }
 #line 2196
   return (0);
 }
 }
 #line 2199 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_driver_open(struct drm_device *dev , struct drm_file *file ) 
 { struct drm_i915_file_private *file_priv ;
   void *tmp ;
   struct lock_class_key __key ;
   struct drm_i915_file_private *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct spinlock *__cil_tmp9 ;
   struct raw_spinlock *__cil_tmp10 ;
   struct list_head *__cil_tmp11 ;
 
   {
   {
 #line 2203
   drm_ut_debug_printk(2U, "drm", "i915_driver_open", "\n");
 #line 2204
   tmp = kmalloc(88UL, 208U);
 #line 2204
   file_priv = (struct drm_i915_file_private *)tmp;
   }
   {
 #line 2205
   __cil_tmp6 = (struct drm_i915_file_private *)0;
 #line 2205
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 2205
   __cil_tmp8 = (unsigned long )file_priv;
 #line 2205
   if (__cil_tmp8 == __cil_tmp7) {
 #line 2206
     return (-12);
   } else {
 
   }
   }
   {
 #line 2208
   file->driver_priv = (void *)file_priv;
 #line 2210
   __cil_tmp9 = & file_priv->mm.lock;
 #line 2210
   spinlock_check(__cil_tmp9);
 #line 2210
   __cil_tmp10 = & file_priv->mm.lock.ldv_6060.rlock;
 #line 2210
   __raw_spin_lock_init(__cil_tmp10, "&(&file_priv->mm.lock)->rlock", & __key);
 #line 2211
   __cil_tmp11 = & file_priv->mm.request_list;
 #line 2211
   INIT_LIST_HEAD(__cil_tmp11);
   }
 #line 2213
   return (0);
 }
 }
 #line 2228 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 void i915_driver_lastclose(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int tmp ;
   void *__cil_tmp4 ;
   drm_i915_private_t *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct mem_block *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   struct mem_block *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct mem_block **__cil_tmp12 ;
 
   {
 #line 2230
   __cil_tmp4 = dev->dev_private;
 #line 2230
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
   {
 #line 2232
   __cil_tmp5 = (drm_i915_private_t *)0;
 #line 2232
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 2232
   __cil_tmp7 = (unsigned long )dev_priv;
 #line 2232
   if (__cil_tmp7 == __cil_tmp6) {
     {
 #line 2233
     intel_fb_restore_mode(dev);
 #line 2234
     vga_switcheroo_process_delayed_switch();
     }
 #line 2235
     return;
   } else {
     {
 #line 2232
     tmp = drm_core_check_feature(dev, 8192);
     }
 #line 2232
     if (tmp != 0) {
       {
 #line 2233
       intel_fb_restore_mode(dev);
 #line 2234
       vga_switcheroo_process_delayed_switch();
       }
 #line 2235
       return;
     } else {
 
     }
   }
   }
   {
 #line 2238
   i915_gem_lastclose(dev);
   }
   {
 #line 2240
   __cil_tmp8 = (struct mem_block *)0;
 #line 2240
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 2240
   __cil_tmp10 = dev_priv->agp_heap;
 #line 2240
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 2240
   if (__cil_tmp11 != __cil_tmp9) {
     {
 #line 2241
     __cil_tmp12 = & dev_priv->agp_heap;
 #line 2241
     i915_mem_takedown(__cil_tmp12);
     }
   } else {
 
   }
   }
   {
 #line 2243
   i915_dma_cleanup(dev);
   }
 #line 2244
   return;
 }
 }
 #line 2246 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 void i915_driver_preclose(struct drm_device *dev , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   int tmp ;
   void *__cil_tmp5 ;
   struct mem_block *__cil_tmp6 ;
 
   {
   {
 #line 2248
   __cil_tmp5 = dev->dev_private;
 #line 2248
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 2249
   i915_gem_release(dev, file_priv);
 #line 2250
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 2250
   if (tmp == 0) {
     {
 #line 2251
     __cil_tmp6 = dev_priv->agp_heap;
 #line 2251
     i915_mem_release(dev, file_priv, __cil_tmp6);
     }
   } else {
 
   }
 #line 2252
   return;
 }
 }
 #line 2254 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 void i915_driver_postclose(struct drm_device *dev , struct drm_file *file ) 
 { struct drm_i915_file_private *file_priv ;
   void *__cil_tmp4 ;
   void const   *__cil_tmp5 ;
 
   {
   {
 #line 2256
   __cil_tmp4 = file->driver_priv;
 #line 2256
   file_priv = (struct drm_i915_file_private *)__cil_tmp4;
 #line 2258
   __cil_tmp5 = (void const   *)file_priv;
 #line 2258
   kfree(__cil_tmp5);
   }
 #line 2259
   return;
 }
 }
 #line 2261 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 struct drm_ioctl_desc i915_ioctls[42U]  = 
 #line 2261
   {      {0U, 7, & i915_dma_init, 1078223936U}, 
         {1U, 1, & i915_flush_ioctl, 25665U}, 
         {2U, 1, & i915_flip_bufs, 25666U}, 
         {3U, 1, & i915_batchbuffer, 1075864643U}, 
         {4U, 1, & i915_irq_emit, 3221775428U}, 
         {5U, 1, & i915_irq_wait, 1074029637U}, 
         {6U, 1, & i915_getparam, 3222299718U}, 
         {7U, 7, & i915_setparam, 1074291783U}, 
         {8U, 1, & i915_mem_alloc, 3222824008U}, 
         {9U, 1, & i915_mem_free, 1074291785U}, 
         {10U, 7, & i915_mem_init_heap, 1074553930U}, 
         {11U, 1, & i915_cmdbuffer, 1075864651U}, 
         {12U, 7, & i915_mem_destroy_heap, 1074029644U}, 
         {13U, 7, & i915_vblank_pipe_set, 1074029645U}, 
         {14U, 1, & i915_vblank_pipe_get, 2147771470U}, 
         {15U, 1, & i915_vblank_swap, 3222037583U}, 
         {0U, 0, (drm_ioctl_t *)0, 0U}, 
         {17U, 7, & i915_set_status_page, 1074816081U}, 
         {0U, 0, (drm_ioctl_t *)0, 0U}, 
         {19U, 23, & i915_gem_init_ioctl, 1074816083U}, 
         {20U, 17, & i915_gem_execbuffer, 1076388948U}, 
         {21U, 21, & i915_gem_pin_ioctl, 3222824021U}, 
         {22U, 21, & i915_gem_unpin_ioctl, 1074291798U}, 
         {23U, 17, & i915_gem_busy_ioctl, 3221775447U}, 
         {24U, 17, & i915_gem_throttle_ioctl, 25688U}, 
         {25U, 23, & i915_gem_entervt_ioctl, 25689U}, 
         {26U, 23, & i915_gem_leavevt_ioctl, 25690U}, 
         {27U, 16, & i915_gem_create_ioctl, 3222299739U}, 
         {28U, 16, & i915_gem_pread_ioctl, 1075864668U}, 
         {29U, 16, & i915_gem_pwrite_ioctl, 1075864669U}, 
         {30U, 16, & i915_gem_mmap_ioctl, 3223348318U}, 
         {31U, 16, & i915_gem_set_domain_ioctl, 1074553951U}, 
         {32U, 16, & i915_gem_sw_finish_ioctl, 1074029664U}, 
         {33U, 16, & i915_gem_set_tiling, 3222299745U}, 
         {34U, 16, & i915_gem_get_tiling, 3222037602U}, 
         {35U, 16, & i915_gem_get_aperture_ioctl, 2148557923U}, 
         {36U, 16, & i915_gem_mmap_gtt_ioctl, 3222299748U}, 
         {37U, 16, & intel_get_pipe_from_crtc_id, 3221775461U}, 
         {38U, 16, & i915_gem_madvise_ioctl, 3222037606U}, 
         {39U, 26, & intel_overlay_put_image, 3224134824U}, 
         {40U, 26, & intel_overlay_attrs, 3224134760U}, 
         {41U, 17, & i915_gem_execbuffer2, 1077961833U}};
 #line 2304 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_max_ioctl  =    42;
 #line 2317 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_dma.c.p"
 int i915_driver_device_is_agp(struct drm_device *dev ) 
 { 
 
   {
 #line 2319
   return (1);
 }
 }
 #line 186 "include/linux/list.h"
 __inline static int list_empty(struct list_head  const  *head ) 
 { unsigned long __cil_tmp2 ;
   struct list_head *__cil_tmp3 ;
   struct list_head  const  *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
 
   {
   {
 #line 188
   __cil_tmp2 = (unsigned long )head;
 #line 188
   __cil_tmp3 = head->next;
 #line 188
   __cil_tmp4 = (struct list_head  const  *)__cil_tmp3;
 #line 188
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 188
   return (__cil_tmp5 == __cil_tmp2);
   }
 }
 }
 #line 315 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/bitops.h"
 __inline static int variable_test_bit(int nr , unsigned long const volatile   *addr ) 
 { int oldbit ;
   unsigned long *__cil_tmp4 ;
 
   {
 #line 319
   __cil_tmp4 = (unsigned long *)addr;
 #line 319
   __asm__  volatile   ("bt %2,%1\n\tsbb %0,%0": "=r" (oldbit): "m" (*__cil_tmp4),
                        "Ir" (nr));
 #line 324
   return (oldbit);
 }
 }
 #line 10 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/current.h"
 extern struct task_struct *current_task ;
 #line 12 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/current.h"
 __inline static struct task_struct *get_current(void) 
 { struct task_struct *pfo_ret__ ;
 
   {
 #line 14
   if (1) {
 #line 14
     goto case_8;
   } else {
 #line 14
     goto switch_default;
 #line 14
     if (0) {
 #line 14
       __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "p" (& current_task));
 #line 14
       goto ldv_2386;
 #line 14
       __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& current_task));
 #line 14
       goto ldv_2386;
 #line 14
       __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& current_task));
 #line 14
       goto ldv_2386;
       case_8: 
 #line 14
       __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& current_task));
 #line 14
       goto ldv_2386;
       switch_default: 
       {
 #line 14
       __bad_percpu_size();
       }
     } else {
 
     }
   }
   ldv_2386: ;
 #line 14
   return (pfo_ret__);
 }
 }
 #line 349 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt_types.h"
 extern struct pv_irq_ops pv_irq_ops ;
 #line 851 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"
 __inline static unsigned long arch_local_save_flags(void) 
 { unsigned long __ret ;
   unsigned long __edi ;
   unsigned long __esi ;
   unsigned long __edx ;
   unsigned long __ecx ;
   unsigned long __eax ;
   long tmp ;
   void *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   int __cil_tmp11 ;
   long __cil_tmp12 ;
 
   {
   {
 #line 853
   __edi = __edi;
 #line 853
   __esi = __esi;
 #line 853
   __edx = __edx;
 #line 853
   __ecx = __ecx;
 #line 853
   __eax = __eax;
 #line 853
   __cil_tmp8 = (void *)0;
 #line 853
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 853
   __cil_tmp10 = (unsigned long )pv_irq_ops.save_fl.func;
 #line 853
   __cil_tmp11 = __cil_tmp10 == __cil_tmp9;
 #line 853
   __cil_tmp12 = (long )__cil_tmp11;
 #line 853
   tmp = __builtin_expect(__cil_tmp12, 0L);
   }
 #line 853
   if (tmp != 0L) {
 #line 853
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"),
                          "i" (853), "i" (12UL));
     ldv_4705: ;
 #line 853
     goto ldv_4705;
   } else {
 
   }
 #line 853
   __asm__  volatile   ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad  771b\n  .byte %c1\n  .byte 772b-771b\n  .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (46UL),
                        [paravirt_opptr] "i" (& pv_irq_ops.save_fl.func), [paravirt_clobber] "i" (1): "memory",
                        "cc");
 #line 853
   __ret = __eax;
 #line 853
   return (__ret);
 }
 }
 #line 856 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"
 __inline static void arch_local_irq_restore(unsigned long f ) 
 { unsigned long __edi ;
   unsigned long __esi ;
   unsigned long __edx ;
   unsigned long __ecx ;
   unsigned long __eax ;
   long tmp ;
   void *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   int __cil_tmp11 ;
   long __cil_tmp12 ;
 
   {
   {
 #line 858
   __edi = __edi;
 #line 858
   __esi = __esi;
 #line 858
   __edx = __edx;
 #line 858
   __ecx = __ecx;
 #line 858
   __eax = __eax;
 #line 858
   __cil_tmp8 = (void *)0;
 #line 858
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 858
   __cil_tmp10 = (unsigned long )pv_irq_ops.restore_fl.func;
 #line 858
   __cil_tmp11 = __cil_tmp10 == __cil_tmp9;
 #line 858
   __cil_tmp12 = (long )__cil_tmp11;
 #line 858
   tmp = __builtin_expect(__cil_tmp12, 0L);
   }
 #line 858
   if (tmp != 0L) {
 #line 858
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"),
                          "i" (858), "i" (12UL));
     ldv_4715: ;
 #line 858
     goto ldv_4715;
   } else {
 
   }
 #line 858
   __asm__  volatile   ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad  771b\n  .byte %c1\n  .byte 772b-771b\n  .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (47UL),
                        [paravirt_opptr] "i" (& pv_irq_ops.restore_fl.func), [paravirt_clobber] "i" (1),
                        "D" (f): "memory", "cc");
 #line 860
   return;
 }
 }
 #line 861 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"
 __inline static void arch_local_irq_disable(void) 
 { unsigned long __edi ;
   unsigned long __esi ;
   unsigned long __edx ;
   unsigned long __ecx ;
   unsigned long __eax ;
   long tmp ;
   void *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   int __cil_tmp10 ;
   long __cil_tmp11 ;
 
   {
   {
 #line 863
   __edi = __edi;
 #line 863
   __esi = __esi;
 #line 863
   __edx = __edx;
 #line 863
   __ecx = __ecx;
 #line 863
   __eax = __eax;
 #line 863
   __cil_tmp7 = (void *)0;
 #line 863
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 863
   __cil_tmp9 = (unsigned long )pv_irq_ops.irq_disable.func;
 #line 863
   __cil_tmp10 = __cil_tmp9 == __cil_tmp8;
 #line 863
   __cil_tmp11 = (long )__cil_tmp10;
 #line 863
   tmp = __builtin_expect(__cil_tmp11, 0L);
   }
 #line 863
   if (tmp != 0L) {
 #line 863
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"),
                          "i" (863), "i" (12UL));
     ldv_4724: ;
 #line 863
     goto ldv_4724;
   } else {
 
   }
 #line 863
   __asm__  volatile   ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad  771b\n  .byte %c1\n  .byte 772b-771b\n  .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (48UL),
                        [paravirt_opptr] "i" (& pv_irq_ops.irq_disable.func), [paravirt_clobber] "i" (1): "memory",
                        "cc");
 #line 865
   return;
 }
 }
 #line 871 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/paravirt.h"
 __inline static unsigned long arch_local_irq_save(void) 
 { unsigned long f ;
 
   {
   {
 #line 875
   f = arch_local_save_flags();
 #line 876
   arch_local_irq_disable();
   }
 #line 877
   return (f);
 }
 }
 #line 154 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/irqflags.h"
 __inline static int arch_irqs_disabled_flags(unsigned long flags ) 
 { unsigned long __cil_tmp2 ;
 
   {
   {
 #line 156
   __cil_tmp2 = flags & 512UL;
 #line 156
   return (__cil_tmp2 == 0UL);
   }
 }
 }
 #line 20 "include/linux/irqflags.h"
 extern void trace_hardirqs_on(void) ;
 #line 21
 extern void trace_hardirqs_off(void) ;
 #line 35 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
 __inline static void atomic_set(atomic_t *v , int i ) 
 { 
 
   {
 #line 37
   v->counter = i;
 #line 38
   return;
 }
 }
 #line 93 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
 __inline static void atomic_inc(atomic_t *v ) 
 { 
 
   {
 #line 95
   __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; incl %0": "+m" (v->counter));
 #line 97
   return;
 }
 }
 #line 82 "include/linux/thread_info.h"
 __inline static int test_ti_thread_flag(struct thread_info *ti , int flag ) 
 { int tmp ;
   __u32 *__cil_tmp4 ;
   unsigned long const volatile   *__cil_tmp5 ;
 
   {
   {
 #line 84
   __cil_tmp4 = & ti->flags;
 #line 84
   __cil_tmp5 = (unsigned long const volatile   *)__cil_tmp4;
 #line 84
   tmp = variable_test_bit(flag, __cil_tmp5);
   }
 #line 84
   return (tmp);
 }
 }
 #line 261 "include/linux/lockdep.h"
 extern void lockdep_init_map(struct lockdep_map * , char const   * , struct lock_class_key * ,
                              int  ) ;
 #line 29 "include/linux/spinlock_api_smp.h"
 extern void _raw_spin_lock_irq(raw_spinlock_t * ) ;
 #line 32
 extern unsigned long _raw_spin_lock_irqsave(raw_spinlock_t * ) ;
 #line 41
 extern void _raw_spin_unlock_irq(raw_spinlock_t * ) ;
 #line 43
 extern void _raw_spin_unlock_irqrestore(raw_spinlock_t * , unsigned long  ) ;
 #line 308 "include/linux/spinlock.h"
 __inline static void spin_lock_irq(spinlock_t *lock ) 
 { struct raw_spinlock *__cil_tmp2 ;
 
   {
   {
 #line 310
   __cil_tmp2 = & lock->ldv_6060.rlock;
 #line 310
   _raw_spin_lock_irq(__cil_tmp2);
   }
 #line 311
   return;
 }
 }
 #line 333 "include/linux/spinlock.h"
 __inline static void spin_unlock_irq(spinlock_t *lock ) 
 { struct raw_spinlock *__cil_tmp2 ;
 
   {
   {
 #line 335
   __cil_tmp2 = & lock->ldv_6060.rlock;
 #line 335
   _raw_spin_unlock_irq(__cil_tmp2);
   }
 #line 336
   return;
 }
 }
 #line 338 "include/linux/spinlock.h"
 __inline static void spin_unlock_irqrestore(spinlock_t *lock , unsigned long flags ) 
 { struct raw_spinlock *__cil_tmp3 ;
 
   {
   {
 #line 340
   __cil_tmp3 = & lock->ldv_6060.rlock;
 #line 340
   _raw_spin_unlock_irqrestore(__cil_tmp3, flags);
   }
 #line 341
   return;
 }
 }
 #line 149 "include/linux/time.h"
 extern void do_gettimeofday(struct timeval * ) ;
 #line 30 "include/linux/wait.h"
 extern int default_wake_function(wait_queue_t * , unsigned int  , int  , void * ) ;
 #line 80
 extern void __init_waitqueue_head(wait_queue_head_t * , struct lock_class_key * ) ;
 #line 113 "include/linux/wait.h"
 __inline static int waitqueue_active(wait_queue_head_t *q ) 
 { int tmp ;
   struct list_head *__cil_tmp3 ;
   struct list_head  const  *__cil_tmp4 ;
 
   {
   {
 #line 115
   __cil_tmp3 = & q->task_list;
 #line 115
   __cil_tmp4 = (struct list_head  const  *)__cil_tmp3;
 #line 115
   tmp = list_empty(__cil_tmp4);
   }
 #line 115
   return (tmp == 0);
 }
 }
 #line 118
 extern void add_wait_queue(wait_queue_head_t * , wait_queue_t * ) ;
 #line 120
 extern void remove_wait_queue(wait_queue_head_t * , wait_queue_t * ) ;
 #line 156
 extern void __wake_up(wait_queue_head_t * , unsigned int  , int  , void * ) ;
 #line 211 "include/linux/timer.h"
 extern int mod_timer(struct timer_list * , unsigned long  ) ;
 #line 156 "include/linux/workqueue.h"
 extern void __init_work(struct work_struct * , int  ) ;
 #line 349
 extern int queue_work(struct workqueue_struct * , struct work_struct * ) ;
 #line 92 "include/linux/completion.h"
 extern void complete_all(struct completion * ) ;
 #line 64 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void writew(unsigned short val , void volatile   *addr ) 
 { unsigned short volatile   *__cil_tmp3 ;
 
   {
 #line 64
   __cil_tmp3 = (unsigned short volatile   *)addr;
 #line 64
   __asm__  volatile   ("movw %0,%1": : "r" (val), "m" (*__cil_tmp3): "memory");
 #line 65
   return;
 }
 }
 #line 86 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static unsigned long readq(void const volatile   *addr ) 
 { unsigned long ret ;
   unsigned long volatile   *__cil_tmp3 ;
 
   {
 #line 86
   __cil_tmp3 = (unsigned long volatile   *)addr;
 #line 86
   __asm__  volatile   ("movq %1,%0": "=r" (ret): "m" (*__cil_tmp3): "memory");
 #line 86
   return (ret);
 }
 }
 #line 211 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void memcpy_fromio(void *dst , void const volatile   *src , size_t count ) 
 { size_t __len ;
   void *__ret ;
   void const   *__cil_tmp6 ;
 
   {
   {
 #line 213
   __len = count;
 #line 213
   __cil_tmp6 = (void const   *)src;
 #line 213
   __ret = __builtin_memcpy(dst, __cil_tmp6, __len);
   }
 #line 215
   return;
 }
 }
 #line 212 "include/linux/kobject.h"
 extern int kobject_uevent_env(struct kobject * , enum kobject_action  , char ** ) ;
 #line 357 "include/linux/sched.h"
 extern long schedule_timeout(long  ) ;
 #line 2441 "include/linux/sched.h"
 __inline static int test_tsk_thread_flag(struct task_struct *tsk , int flag ) 
 { int tmp ;
   void *__cil_tmp4 ;
   struct thread_info *__cil_tmp5 ;
 
   {
   {
 #line 2443
   __cil_tmp4 = tsk->stack;
 #line 2443
   __cil_tmp5 = (struct thread_info *)__cil_tmp4;
 #line 2443
   tmp = test_ti_thread_flag(__cil_tmp5, flag);
   }
 #line 2443
   return (tmp);
 }
 }
 #line 2467 "include/linux/sched.h"
 __inline static int signal_pending(struct task_struct *p ) 
 { int tmp ;
   long tmp___0 ;
   int __cil_tmp4 ;
   long __cil_tmp5 ;
 
   {
   {
 #line 2469
   tmp = test_tsk_thread_flag(p, 2);
 #line 2469
   __cil_tmp4 = tmp != 0;
 #line 2469
   __cil_tmp5 = (long )__cil_tmp4;
 #line 2469
   tmp___0 = __builtin_expect(__cil_tmp5, 0L);
   }
 #line 2469
   return ((int )tmp___0);
 }
 }
 #line 1394 "include/drm/drmP.h"
 extern bool drm_handle_vblank(struct drm_device * , int  ) ;
 #line 1401
 extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device * , int  , int * ,
                                                  struct timeval * , unsigned int  ,
                                                  struct drm_crtc * ) ;
 #line 138 "include/linux/io-mapping.h"
 __inline static void *io_mapping_map_atomic_wc(struct io_mapping *mapping , unsigned long offset ) 
 { void *__cil_tmp3 ;
 
   {
   {
 #line 141
   __cil_tmp3 = (void *)mapping;
 #line 141
   return (__cil_tmp3 + offset);
   }
 }
 }
 #line 145 "include/linux/io-mapping.h"
 __inline static void io_mapping_unmap_atomic(void *vaddr ) 
 { 
 
   {
 #line 147
   return;
 }
 }
 #line 307 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_request_complete ;
 #line 307 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_request_complete(struct intel_ring_buffer *ring ,
                                                      u32 seqno ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct intel_ring_buffer * , u32  ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 304
   __cil_tmp11 = & __tracepoint_i915_gem_request_complete.key;
 #line 304
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 304
   if ((int )tmp___1) {
     {
 #line 304
     rcu_read_lock_sched_notrace();
 #line 304
     __cil_tmp12 = & __tracepoint_i915_gem_request_complete.funcs;
 #line 304
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 304
     __cil_tmp14 = *__cil_tmp13;
 #line 304
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 304
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 304
     if (tmp != 0) {
 #line 304
       if (! __warned) {
         {
 #line 304
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 304
         if (tmp___0 == 0) {
           {
 #line 304
           __warned = (bool )1;
 #line 304
           __cil_tmp15 = (int const   )307;
 #line 304
           __cil_tmp16 = (int )__cil_tmp15;
 #line 304
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 304
     it_func_ptr = _________p1;
     {
 #line 304
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 304
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 304
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 304
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36254: 
       {
 #line 304
       it_func = it_func_ptr->func;
 #line 304
       __data = it_func_ptr->data;
 #line 304
       __cil_tmp20 = (void (*)(void * , struct intel_ring_buffer * , u32  ))it_func;
 #line 304
       (*__cil_tmp20)(__data, ring, seqno);
 #line 304
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 304
       __cil_tmp21 = (void *)0;
 #line 304
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 304
       __cil_tmp23 = it_func_ptr->func;
 #line 304
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 304
       if (__cil_tmp24 != __cil_tmp22) {
 #line 305
         goto ldv_36254;
       } else {
 #line 307
         goto ldv_36255;
       }
       }
       ldv_36255: ;
     } else {
 
     }
     }
     {
 #line 304
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 306
   return;
 }
 }
 #line 1029 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 void i915_handle_error(struct drm_device *dev , bool wedged ) ;
 #line 1045
 void i915_enable_pipestat(drm_i915_private_t *dev_priv , int pipe , u32 mask ) ;
 #line 1048
 void i915_disable_pipestat(drm_i915_private_t *dev_priv , int pipe , u32 mask ) ;
 #line 1050
 void intel_enable_asle(struct drm_device *dev ) ;
 #line 1145 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static bool i915_seqno_passed(uint32_t seq1 , uint32_t seq2 ) 
 { uint32_t __cil_tmp3 ;
   int __cil_tmp4 ;
   int __cil_tmp5 ;
 
   {
   {
 #line 1147
   __cil_tmp3 = seq1 - seq2;
 #line 1147
   __cil_tmp4 = (int )__cil_tmp3;
 #line 1147
   __cil_tmp5 = __cil_tmp4 >= 0;
 #line 1147
   return ((bool )__cil_tmp5);
   }
 }
 }
 #line 1261
 void intel_opregion_asle_intr(struct drm_device *dev ) ;
 #line 1262
 void intel_opregion_gse_intr(struct drm_device *dev ) ;
 #line 1263
 void intel_opregion_enable_asle(struct drm_device *dev ) ;
 #line 1294
 void gen6_set_rps(struct drm_device *dev , u8 val ) ;
 #line 1300
 struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev ) ;
 #line 1303
 struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev ) ;
 #line 1362 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u64 i915_read64(struct drm_i915_private *dev_priv , u32 reg ) 
 { u64 val ;
   unsigned long tmp ;
   unsigned long tmp___0 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   void *__cil_tmp11 ;
   void const volatile   *__cil_tmp12 ;
   void const volatile   *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   void *__cil_tmp15 ;
   void const volatile   *__cil_tmp16 ;
   void const volatile   *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   void *__cil_tmp19 ;
   void const volatile   *__cil_tmp20 ;
   void const volatile   *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   void const volatile   *__cil_tmp24 ;
   void const volatile   *__cil_tmp25 ;
   bool __cil_tmp26 ;
 
   {
 #line 1362
   val = 0ULL;
   {
 #line 1362
   __cil_tmp6 = dev_priv->info;
 #line 1362
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1362
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1362
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1362
   if (__cil_tmp9 > 5U) {
 #line 1362
     if (reg <= 262143U) {
 #line 1362
       if (reg != 41356U) {
         {
 #line 1362
         gen6_gt_force_wake_get(dev_priv);
 #line 1362
         __cil_tmp10 = (unsigned long )reg;
 #line 1362
         __cil_tmp11 = dev_priv->regs;
 #line 1362
         __cil_tmp12 = (void const volatile   *)__cil_tmp11;
 #line 1362
         __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
 #line 1362
         tmp = readq(__cil_tmp13);
 #line 1362
         val = (u64 )tmp;
 #line 1362
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1362
         __cil_tmp14 = (unsigned long )reg;
 #line 1362
         __cil_tmp15 = dev_priv->regs;
 #line 1362
         __cil_tmp16 = (void const volatile   *)__cil_tmp15;
 #line 1362
         __cil_tmp17 = __cil_tmp16 + __cil_tmp14;
 #line 1362
         tmp___0 = readq(__cil_tmp17);
 #line 1362
         val = (u64 )tmp___0;
         }
       }
     } else {
       {
 #line 1362
       __cil_tmp18 = (unsigned long )reg;
 #line 1362
       __cil_tmp19 = dev_priv->regs;
 #line 1362
       __cil_tmp20 = (void const volatile   *)__cil_tmp19;
 #line 1362
       __cil_tmp21 = __cil_tmp20 + __cil_tmp18;
 #line 1362
       tmp___0 = readq(__cil_tmp21);
 #line 1362
       val = (u64 )tmp___0;
       }
     }
   } else {
     {
 #line 1362
     __cil_tmp22 = (unsigned long )reg;
 #line 1362
     __cil_tmp23 = dev_priv->regs;
 #line 1362
     __cil_tmp24 = (void const volatile   *)__cil_tmp23;
 #line 1362
     __cil_tmp25 = __cil_tmp24 + __cil_tmp22;
 #line 1362
     tmp___0 = readq(__cil_tmp25);
 #line 1362
     val = (u64 )tmp___0;
     }
   }
   }
   {
 #line 1362
   __cil_tmp26 = (bool )0;
 #line 1362
   trace_i915_reg_rw(__cil_tmp26, reg, val, 8);
   }
 #line 1362
   return (val);
 }
 }
 #line 1374 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static void i915_write16(struct drm_i915_private *dev_priv , u32 reg , u16 val ) 
 { bool __cil_tmp4 ;
   u64 __cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   unsigned short __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void volatile   *__cil_tmp14 ;
   void volatile   *__cil_tmp15 ;
 
   {
   {
 #line 1374
   __cil_tmp4 = (bool )1;
 #line 1374
   __cil_tmp5 = (u64 )val;
 #line 1374
   trace_i915_reg_rw(__cil_tmp4, reg, __cil_tmp5, 2);
   }
   {
 #line 1374
   __cil_tmp6 = dev_priv->info;
 #line 1374
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1374
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1374
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1374
   if (__cil_tmp9 > 5U) {
 #line 1374
     if (reg <= 262143U) {
 #line 1374
       if (reg != 41356U) {
         {
 #line 1374
         __gen6_gt_wait_for_fifo(dev_priv);
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1374
   __cil_tmp10 = (int )val;
 #line 1374
   __cil_tmp11 = (unsigned short )__cil_tmp10;
 #line 1374
   __cil_tmp12 = (unsigned long )reg;
 #line 1374
   __cil_tmp13 = dev_priv->regs;
 #line 1374
   __cil_tmp14 = (void volatile   *)__cil_tmp13;
 #line 1374
   __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1374
   writew(__cil_tmp11, __cil_tmp15);
   }
 #line 1375
   return;
 }
 }
 #line 143 "include/drm/drm_crtc_helper.h"
 extern void drm_helper_hpd_irq_event(struct drm_device * ) ;
 #line 213 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 __inline static struct drm_crtc *intel_get_crtc_for_pipe(struct drm_device *dev ,
                                                          int pipe ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp4 ;
 
   {
 #line 215
   __cil_tmp4 = dev->dev_private;
 #line 215
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 216
   return (dev_priv->pipe_to_crtc_mapping[pipe]);
 }
 }
 #line 334
 void intel_prepare_page_flip(struct drm_device *dev , int plane ) ;
 #line 335
 void intel_finish_page_flip(struct drm_device *dev , int pipe ) ;
 #line 336
 void intel_finish_page_flip_plane(struct drm_device *dev , int plane ) ;
 #line 76 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void ironlake_enable_display_irq(drm_i915_private_t *dev_priv , u32 mask ) 
 { u32 __cil_tmp3 ;
   unsigned int __cil_tmp4 ;
   u32 __cil_tmp5 ;
   u32 __cil_tmp6 ;
   u32 __cil_tmp7 ;
   void *__cil_tmp8 ;
   void const volatile   *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
 
   {
   {
 #line 78
   __cil_tmp3 = dev_priv->irq_mask;
 #line 78
   __cil_tmp4 = __cil_tmp3 & mask;
 #line 78
   if (__cil_tmp4 != 0U) {
     {
 #line 79
     __cil_tmp5 = ~ mask;
 #line 79
     __cil_tmp6 = dev_priv->irq_mask;
 #line 79
     dev_priv->irq_mask = __cil_tmp6 & __cil_tmp5;
 #line 80
     __cil_tmp7 = dev_priv->irq_mask;
 #line 80
     i915_write32(dev_priv, 278532U, __cil_tmp7);
 #line 81
     __cil_tmp8 = dev_priv->regs;
 #line 81
     __cil_tmp9 = (void const volatile   *)__cil_tmp8;
 #line 81
     __cil_tmp10 = __cil_tmp9 + 278532U;
 #line 81
     readl(__cil_tmp10);
     }
   } else {
 
   }
   }
 #line 83
   return;
 }
 }
 #line 86 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 __inline static void ironlake_disable_display_irq(drm_i915_private_t *dev_priv , u32 mask ) 
 { u32 __cil_tmp3 ;
   unsigned int __cil_tmp4 ;
   u32 __cil_tmp5 ;
   u32 __cil_tmp6 ;
   void *__cil_tmp7 ;
   void const volatile   *__cil_tmp8 ;
   void const volatile   *__cil_tmp9 ;
 
   {
   {
 #line 88
   __cil_tmp3 = dev_priv->irq_mask;
 #line 88
   __cil_tmp4 = __cil_tmp3 & mask;
 #line 88
   if (__cil_tmp4 != mask) {
     {
 #line 89
     __cil_tmp5 = dev_priv->irq_mask;
 #line 89
     dev_priv->irq_mask = __cil_tmp5 | mask;
 #line 90
     __cil_tmp6 = dev_priv->irq_mask;
 #line 90
     i915_write32(dev_priv, 278532U, __cil_tmp6);
 #line 91
     __cil_tmp7 = dev_priv->regs;
 #line 91
     __cil_tmp8 = (void const volatile   *)__cil_tmp7;
 #line 91
     __cil_tmp9 = __cil_tmp8 + 278532U;
 #line 91
     readl(__cil_tmp9);
     }
   } else {
 
   }
   }
 #line 93
   return;
 }
 }
 #line 96 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void i915_enable_pipestat(drm_i915_private_t *dev_priv , int pipe , u32 mask ) 
 { u32 reg ;
   u32 __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   u32 __cil_tmp9 ;
   u32 __cil_tmp10 ;
   u32 __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   void *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   void const volatile   *__cil_tmp16 ;
 
   {
   {
 #line 98
   __cil_tmp5 = dev_priv->pipestat[pipe];
 #line 98
   __cil_tmp6 = __cil_tmp5 & mask;
 #line 98
   if (__cil_tmp6 != mask) {
     {
 #line 99
     __cil_tmp7 = pipe * 4096;
 #line 99
     __cil_tmp8 = __cil_tmp7 + 458788;
 #line 99
     reg = (u32 )__cil_tmp8;
 #line 101
     __cil_tmp9 = dev_priv->pipestat[pipe];
 #line 101
     dev_priv->pipestat[pipe] = __cil_tmp9 | mask;
 #line 103
     __cil_tmp10 = mask >> 16;
 #line 103
     __cil_tmp11 = dev_priv->pipestat[pipe];
 #line 103
     __cil_tmp12 = __cil_tmp11 | __cil_tmp10;
 #line 103
     i915_write32(dev_priv, reg, __cil_tmp12);
 #line 104
     __cil_tmp13 = (unsigned long )reg;
 #line 104
     __cil_tmp14 = dev_priv->regs;
 #line 104
     __cil_tmp15 = (void const volatile   *)__cil_tmp14;
 #line 104
     __cil_tmp16 = __cil_tmp15 + __cil_tmp13;
 #line 104
     readl(__cil_tmp16);
     }
   } else {
 
   }
   }
 #line 106
   return;
 }
 }
 #line 109 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void i915_disable_pipestat(drm_i915_private_t *dev_priv , int pipe , u32 mask ) 
 { u32 reg ;
   u32 __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   u32 __cil_tmp9 ;
   u32 __cil_tmp10 ;
   u32 __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
 
   {
   {
 #line 111
   __cil_tmp5 = dev_priv->pipestat[pipe];
 #line 111
   __cil_tmp6 = __cil_tmp5 & mask;
 #line 111
   if (__cil_tmp6 != 0U) {
     {
 #line 112
     __cil_tmp7 = pipe * 4096;
 #line 112
     __cil_tmp8 = __cil_tmp7 + 458788;
 #line 112
     reg = (u32 )__cil_tmp8;
 #line 114
     __cil_tmp9 = ~ mask;
 #line 114
     __cil_tmp10 = dev_priv->pipestat[pipe];
 #line 114
     dev_priv->pipestat[pipe] = __cil_tmp10 & __cil_tmp9;
 #line 115
     __cil_tmp11 = dev_priv->pipestat[pipe];
 #line 115
     i915_write32(dev_priv, reg, __cil_tmp11);
 #line 116
     __cil_tmp12 = (unsigned long )reg;
 #line 116
     __cil_tmp13 = dev_priv->regs;
 #line 116
     __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 116
     __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 116
     readl(__cil_tmp15);
     }
   } else {
 
   }
   }
 #line 118
   return;
 }
 }
 #line 123 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void intel_enable_asle(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   raw_spinlock_t *tmp ;
   void *__cil_tmp5 ;
   spinlock_t *__cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   u8 __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   void *__cil_tmp13 ;
   struct drm_i915_private *__cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   u8 __cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   void *__cil_tmp19 ;
   struct drm_i915_private *__cil_tmp20 ;
   struct intel_device_info  const  *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct drm_i915_private *__cil_tmp27 ;
   struct intel_device_info  const  *__cil_tmp28 ;
   u8 __cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   spinlock_t *__cil_tmp32 ;
 
   {
   {
 #line 125
   __cil_tmp5 = dev->dev_private;
 #line 125
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 128
   __cil_tmp6 = & dev_priv->irq_lock;
 #line 128
   tmp = spinlock_check(__cil_tmp6);
 #line 128
   irqflags = _raw_spin_lock_irqsave(tmp);
   }
   {
 #line 130
   __cil_tmp7 = dev->dev_private;
 #line 130
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 130
   __cil_tmp9 = __cil_tmp8->info;
 #line 130
   __cil_tmp10 = __cil_tmp9->gen;
 #line 130
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 130
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 130
   if (__cil_tmp12 == 5U) {
     {
 #line 131
     ironlake_enable_display_irq(dev_priv, 262144U);
     }
   } else {
     {
 #line 130
     __cil_tmp13 = dev->dev_private;
 #line 130
     __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
 #line 130
     __cil_tmp15 = __cil_tmp14->info;
 #line 130
     __cil_tmp16 = __cil_tmp15->gen;
 #line 130
     __cil_tmp17 = (unsigned char )__cil_tmp16;
 #line 130
     __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 130
     if (__cil_tmp18 == 6U) {
       {
 #line 131
       ironlake_enable_display_irq(dev_priv, 262144U);
       }
     } else {
       {
 #line 130
       __cil_tmp19 = dev->dev_private;
 #line 130
       __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
 #line 130
       __cil_tmp21 = __cil_tmp20->info;
 #line 130
       __cil_tmp22 = (unsigned char *)__cil_tmp21;
 #line 130
       __cil_tmp23 = __cil_tmp22 + 2UL;
 #line 130
       __cil_tmp24 = *__cil_tmp23;
 #line 130
       __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 130
       if (__cil_tmp25 != 0U) {
         {
 #line 131
         ironlake_enable_display_irq(dev_priv, 262144U);
         }
       } else {
         {
 #line 133
         i915_enable_pipestat(dev_priv, 1, 4194304U);
         }
         {
 #line 135
         __cil_tmp26 = dev->dev_private;
 #line 135
         __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
 #line 135
         __cil_tmp28 = __cil_tmp27->info;
 #line 135
         __cil_tmp29 = __cil_tmp28->gen;
 #line 135
         __cil_tmp30 = (unsigned char )__cil_tmp29;
 #line 135
         __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 135
         if (__cil_tmp31 > 3U) {
           {
 #line 136
           i915_enable_pipestat(dev_priv, 0, 4194304U);
           }
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
   {
 #line 140
   __cil_tmp32 = & dev_priv->irq_lock;
 #line 140
   spin_unlock_irqrestore(__cil_tmp32, irqflags);
   }
 #line 141
   return;
 }
 }
 #line 153 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_pipe_enabled(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   u32 tmp ;
   void *__cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   u32 __cil_tmp8 ;
   int __cil_tmp9 ;
 
   {
   {
 #line 155
   __cil_tmp5 = dev->dev_private;
 #line 155
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 156
   __cil_tmp6 = pipe * 4096;
 #line 156
   __cil_tmp7 = __cil_tmp6 + 458760;
 #line 156
   __cil_tmp8 = (u32 )__cil_tmp7;
 #line 156
   tmp = i915_read32(dev_priv, __cil_tmp8);
   }
   {
 #line 156
   __cil_tmp9 = (int )tmp;
 #line 156
   return (__cil_tmp9 & (-0x7FFFFFFF-1));
   }
 }
 }
 #line 162 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static u32 i915_get_vblank_counter(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long high_frame ;
   unsigned long low_frame ;
   u32 high1 ;
   u32 high2 ;
   u32 low ;
   int tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   u32 __cil_tmp19 ;
   u32 __cil_tmp20 ;
   u32 __cil_tmp21 ;
   u32 __cil_tmp22 ;
 
   {
   {
 #line 164
   __cil_tmp13 = dev->dev_private;
 #line 164
   dev_priv = (drm_i915_private_t *)__cil_tmp13;
 #line 169
   tmp = i915_pipe_enabled(dev, pipe);
   }
 #line 169
   if (tmp == 0) {
     {
 #line 170
     __cil_tmp14 = pipe + 65;
 #line 170
     drm_ut_debug_printk(2U, "drm", "i915_get_vblank_counter", "trying to get vblank count for disabled pipe %c\n",
                         __cil_tmp14);
     }
 #line 172
     return (0U);
   } else {
 
   }
 #line 175
   __cil_tmp15 = pipe * 4096;
 #line 175
   __cil_tmp16 = __cil_tmp15 + 458816;
 #line 175
   high_frame = (unsigned long )__cil_tmp16;
 #line 176
   __cil_tmp17 = pipe * 4096;
 #line 176
   __cil_tmp18 = __cil_tmp17 + 458820;
 #line 176
   low_frame = (unsigned long )__cil_tmp18;
   ldv_37592: 
   {
 #line 184
   __cil_tmp19 = (u32 )high_frame;
 #line 184
   tmp___0 = i915_read32(dev_priv, __cil_tmp19);
 #line 184
   high1 = tmp___0 & 65535U;
 #line 185
   __cil_tmp20 = (u32 )low_frame;
 #line 185
   tmp___1 = i915_read32(dev_priv, __cil_tmp20);
 #line 185
   low = tmp___1 & 4278190080U;
 #line 186
   __cil_tmp21 = (u32 )high_frame;
 #line 186
   tmp___2 = i915_read32(dev_priv, __cil_tmp21);
 #line 186
   high2 = tmp___2 & 65535U;
   }
 #line 187
   if (high1 != high2) {
 #line 188
     goto ldv_37592;
   } else {
 #line 190
     goto ldv_37593;
   }
   ldv_37593: 
 #line 189
   high1 = high1;
 #line 190
   low = low >> 24;
   {
 #line 191
   __cil_tmp22 = high1 << 8;
 #line 191
   return (__cil_tmp22 | low);
   }
 }
 }
 #line 194 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static u32 gm45_get_vblank_counter(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   int reg ;
   int tmp ;
   u32 tmp___0 ;
   void *__cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
   u32 __cil_tmp10 ;
 
   {
   {
 #line 196
   __cil_tmp7 = dev->dev_private;
 #line 196
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 197
   __cil_tmp8 = pipe * 4096;
 #line 197
   reg = __cil_tmp8 + 458816;
 #line 199
   tmp = i915_pipe_enabled(dev, pipe);
   }
 #line 199
   if (tmp == 0) {
     {
 #line 200
     __cil_tmp9 = pipe + 65;
 #line 200
     drm_ut_debug_printk(2U, "drm", "gm45_get_vblank_counter", "trying to get vblank count for disabled pipe %c\n",
                         __cil_tmp9);
     }
 #line 202
     return (0U);
   } else {
 
   }
   {
 #line 205
   __cil_tmp10 = (u32 )reg;
 #line 205
   tmp___0 = i915_read32(dev_priv, __cil_tmp10);
   }
 #line 205
   return (tmp___0);
 }
 }
 #line 208 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_get_crtc_scanoutpos(struct drm_device *dev , int pipe , int *vpos ,
                                     int *hpos ) 
 { drm_i915_private_t *dev_priv ;
   u32 vbl ;
   u32 position ;
   int vbl_start ;
   int vbl_end ;
   int htotal ;
   int vtotal ;
   bool in_vbl ;
   int ret ;
   int tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   u32 __cil_tmp22 ;
   u32 __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct drm_i915_private *__cil_tmp27 ;
   struct intel_device_info  const  *__cil_tmp28 ;
   u8 __cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   u32 __cil_tmp41 ;
   u32 __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   u32 __cil_tmp45 ;
   u32 __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   u32 __cil_tmp49 ;
   u32 __cil_tmp50 ;
   int __cil_tmp51 ;
   int __cil_tmp52 ;
   u32 __cil_tmp53 ;
   int __cil_tmp54 ;
   u32 __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
 
   {
   {
 #line 211
   __cil_tmp18 = dev->dev_private;
 #line 211
   dev_priv = (drm_i915_private_t *)__cil_tmp18;
 #line 212
   vbl = 0U;
 #line 212
   position = 0U;
 #line 214
   in_vbl = (bool )1;
 #line 215
   ret = 0;
 #line 217
   tmp = i915_pipe_enabled(dev, pipe);
   }
 #line 217
   if (tmp == 0) {
     {
 #line 218
     __cil_tmp19 = pipe + 65;
 #line 218
     drm_ut_debug_printk(2U, "drm", "i915_get_crtc_scanoutpos", "trying to get scanoutpos for disabled pipe %c\n",
                         __cil_tmp19);
     }
 #line 220
     return (0);
   } else {
 
   }
   {
 #line 224
   __cil_tmp20 = pipe * 4096;
 #line 224
   __cil_tmp21 = __cil_tmp20 + 393228;
 #line 224
   __cil_tmp22 = (u32 )__cil_tmp21;
 #line 224
   tmp___0 = i915_read32(dev_priv, __cil_tmp22);
 #line 224
   __cil_tmp23 = tmp___0 >> 16;
 #line 224
   __cil_tmp24 = __cil_tmp23 & 8191U;
 #line 224
   __cil_tmp25 = __cil_tmp24 + 1U;
 #line 224
   vtotal = (int )__cil_tmp25;
   }
   {
 #line 226
   __cil_tmp26 = dev->dev_private;
 #line 226
   __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
 #line 226
   __cil_tmp28 = __cil_tmp27->info;
 #line 226
   __cil_tmp29 = __cil_tmp28->gen;
 #line 226
   __cil_tmp30 = (unsigned char )__cil_tmp29;
 #line 226
   __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 226
   if (__cil_tmp31 > 3U) {
     {
 #line 230
     __cil_tmp32 = pipe + 112;
 #line 230
     __cil_tmp33 = __cil_tmp32 * 4096;
 #line 230
     __cil_tmp34 = (u32 )__cil_tmp33;
 #line 230
     position = i915_read32(dev_priv, __cil_tmp34);
 #line 235
     __cil_tmp35 = (int )position;
 #line 235
     *vpos = __cil_tmp35 & 8191;
 #line 236
     *hpos = 0;
     }
   } else {
     {
 #line 242
     __cil_tmp36 = pipe * 4096;
 #line 242
     __cil_tmp37 = __cil_tmp36 + 458820;
 #line 242
     __cil_tmp38 = (u32 )__cil_tmp37;
 #line 242
     tmp___1 = i915_read32(dev_priv, __cil_tmp38);
 #line 242
     position = tmp___1 & 16777215U;
 #line 244
     __cil_tmp39 = pipe + 96;
 #line 244
     __cil_tmp40 = __cil_tmp39 * 4096;
 #line 244
     __cil_tmp41 = (u32 )__cil_tmp40;
 #line 244
     tmp___2 = i915_read32(dev_priv, __cil_tmp41);
 #line 244
     __cil_tmp42 = tmp___2 >> 16;
 #line 244
     __cil_tmp43 = __cil_tmp42 & 8191U;
 #line 244
     __cil_tmp44 = __cil_tmp43 + 1U;
 #line 244
     htotal = (int )__cil_tmp44;
 #line 245
     __cil_tmp45 = (u32 )htotal;
 #line 245
     __cil_tmp46 = position / __cil_tmp45;
 #line 245
     *vpos = (int )__cil_tmp46;
 #line 246
     __cil_tmp47 = *vpos;
 #line 246
     __cil_tmp48 = __cil_tmp47 * htotal;
 #line 246
     __cil_tmp49 = (u32 )__cil_tmp48;
 #line 246
     __cil_tmp50 = position - __cil_tmp49;
 #line 246
     *hpos = (int )__cil_tmp50;
     }
   }
   }
   {
 #line 250
   __cil_tmp51 = pipe * 4096;
 #line 250
   __cil_tmp52 = __cil_tmp51 + 393232;
 #line 250
   __cil_tmp53 = (u32 )__cil_tmp52;
 #line 250
   vbl = i915_read32(dev_priv, __cil_tmp53);
 #line 253
   __cil_tmp54 = (int )vbl;
 #line 253
   vbl_start = __cil_tmp54 & 8191;
 #line 254
   __cil_tmp55 = vbl >> 16;
 #line 254
   __cil_tmp56 = (int )__cil_tmp55;
 #line 254
   vbl_end = __cil_tmp56 & 8191;
   }
   {
 #line 256
   __cil_tmp57 = *vpos;
 #line 256
   if (__cil_tmp57 < vbl_start) {
 #line 257
     in_vbl = (bool )0;
   } else {
     {
 #line 256
     __cil_tmp58 = *vpos;
 #line 256
     if (__cil_tmp58 > vbl_end) {
 #line 257
       in_vbl = (bool )0;
     } else {
 
     }
     }
   }
   }
 #line 260
   if ((int )in_vbl) {
     {
 #line 260
     __cil_tmp59 = *vpos;
 #line 260
     if (__cil_tmp59 >= vbl_start) {
 #line 261
       __cil_tmp60 = *vpos;
 #line 261
       *vpos = __cil_tmp60 - vtotal;
     } else {
 
     }
     }
   } else {
 
   }
 #line 264
   if (vbl != 0U) {
 #line 265
     ret = ret | 5;
   } else {
 
   }
 #line 268
   if ((int )in_vbl) {
 #line 269
     ret = ret | 2;
   } else {
 
   }
 #line 271
   return (ret);
 }
 }
 #line 274 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_get_vblank_timestamp(struct drm_device *dev , int pipe , int *max_error ,
                                      struct timeval *vblank_time , unsigned int flags ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_crtc *crtc ;
   int tmp ;
   void *__cil_tmp9 ;
   int __cil_tmp10 ;
   struct drm_crtc *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   bool __cil_tmp14 ;
 
   {
 #line 279
   __cil_tmp9 = dev->dev_private;
 #line 279
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 282
   if (pipe < 0) {
     {
 #line 283
     drm_err("i915_get_vblank_timestamp", "Invalid crtc %d\n", pipe);
     }
 #line 284
     return (-22);
   } else {
     {
 #line 282
     __cil_tmp10 = dev_priv->num_pipe;
 #line 282
     if (__cil_tmp10 <= pipe) {
       {
 #line 283
       drm_err("i915_get_vblank_timestamp", "Invalid crtc %d\n", pipe);
       }
 #line 284
       return (-22);
     } else {
 
     }
     }
   }
   {
 #line 288
   crtc = intel_get_crtc_for_pipe(dev, pipe);
   }
   {
 #line 289
   __cil_tmp11 = (struct drm_crtc *)0;
 #line 289
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 289
   __cil_tmp13 = (unsigned long )crtc;
 #line 289
   if (__cil_tmp13 == __cil_tmp12) {
     {
 #line 290
     drm_err("i915_get_vblank_timestamp", "Invalid crtc %d\n", pipe);
     }
 #line 291
     return (-22);
   } else {
 
   }
   }
   {
 #line 294
   __cil_tmp14 = crtc->enabled;
 #line 294
   if (! __cil_tmp14) {
     {
 #line 295
     drm_ut_debug_printk(4U, "drm", "i915_get_vblank_timestamp", "crtc %d is disabled\n",
                         pipe);
     }
 #line 296
     return (-16);
   } else {
 
   }
   }
   {
 #line 300
   tmp = drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, flags,
                                               crtc);
   }
 #line 300
   return (tmp);
 }
 }
 #line 308 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_hotplug_work_func(struct work_struct *work ) 
 { drm_i915_private_t *dev_priv ;
   struct work_struct  const  *__mptr ;
   struct drm_device *dev ;
   struct drm_mode_config *mode_config ;
   struct intel_encoder *encoder ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   drm_i915_private_t *__cil_tmp9 ;
   struct list_head *__cil_tmp10 ;
   struct intel_encoder *__cil_tmp11 ;
   void (*__cil_tmp12)(struct intel_encoder * ) ;
   unsigned long __cil_tmp13 ;
   void (*__cil_tmp14)(struct intel_encoder * ) ;
   unsigned long __cil_tmp15 ;
   void (*__cil_tmp16)(struct intel_encoder * ) ;
   struct list_head *__cil_tmp17 ;
   struct intel_encoder *__cil_tmp18 ;
   struct list_head *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
 
   {
   {
 #line 310
   __mptr = (struct work_struct  const  *)work;
 #line 310
   __cil_tmp9 = (drm_i915_private_t *)__mptr;
 #line 310
   dev_priv = __cil_tmp9 + 1152921504606845304UL;
 #line 312
   dev = dev_priv->dev;
 #line 313
   mode_config = & dev->mode_config;
 #line 316
   drm_ut_debug_printk(4U, "drm", "i915_hotplug_work_func", "running encoder hotplug functions\n");
 #line 318
   __cil_tmp10 = mode_config->encoder_list.next;
 #line 318
   __mptr___0 = (struct list_head  const  *)__cil_tmp10;
 #line 318
   __cil_tmp11 = (struct intel_encoder *)__mptr___0;
 #line 318
   encoder = __cil_tmp11 + 1152921504606846968UL;
   }
 #line 318
   goto ldv_37642;
   ldv_37641: ;
   {
 #line 319
   __cil_tmp12 = (void (*)(struct intel_encoder * ))0;
 #line 319
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 319
   __cil_tmp14 = encoder->hot_plug;
 #line 319
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 319
   if (__cil_tmp15 != __cil_tmp13) {
     {
 #line 320
     __cil_tmp16 = encoder->hot_plug;
 #line 320
     (*__cil_tmp16)(encoder);
     }
   } else {
 
   }
   }
 #line 318
   __cil_tmp17 = encoder->base.head.next;
 #line 318
   __mptr___1 = (struct list_head  const  *)__cil_tmp17;
 #line 318
   __cil_tmp18 = (struct intel_encoder *)__mptr___1;
 #line 318
   encoder = __cil_tmp18 + 1152921504606846968UL;
   ldv_37642: ;
   {
 #line 318
   __cil_tmp19 = & mode_config->encoder_list;
 #line 318
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 318
   __cil_tmp21 = & encoder->base.head;
 #line 318
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 318
   if (__cil_tmp22 != __cil_tmp20) {
 #line 319
     goto ldv_37641;
   } else {
 #line 321
     goto ldv_37643;
   }
   }
   ldv_37643: 
   {
 #line 323
   drm_helper_hpd_irq_event(dev);
   }
 #line 324
   return;
 }
 }
 #line 326 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_handle_rps_change(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 busy_up ;
   u32 busy_down ;
   u32 max_avg ;
   u32 min_avg ;
   u8 new_delay ;
   bool tmp ;
   void *__cil_tmp9 ;
   u16 __cil_tmp10 ;
   u8 __cil_tmp11 ;
   int __cil_tmp12 ;
   u8 __cil_tmp13 ;
   int __cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   u8 __cil_tmp19 ;
   int __cil_tmp20 ;
   u8 __cil_tmp21 ;
   int __cil_tmp22 ;
   u8 __cil_tmp23 ;
   int __cil_tmp24 ;
   u8 __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   u8 __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   u8 __cil_tmp32 ;
 
   {
   {
 #line 328
   __cil_tmp9 = dev->dev_private;
 #line 328
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 330
   new_delay = dev_priv->cur_delay;
 #line 332
   __cil_tmp10 = (u16 )16;
 #line 332
   i915_write16(dev_priv, 70020U, __cil_tmp10);
 #line 333
   busy_up = i915_read32(dev_priv, 70584U);
 #line 334
   busy_down = i915_read32(dev_priv, 70588U);
 #line 335
   max_avg = i915_read32(dev_priv, 70044U);
 #line 336
   min_avg = i915_read32(dev_priv, 70048U);
   }
 #line 339
   if (busy_up > max_avg) {
     {
 #line 340
     __cil_tmp11 = dev_priv->max_delay;
 #line 340
     __cil_tmp12 = (int )__cil_tmp11;
 #line 340
     __cil_tmp13 = dev_priv->cur_delay;
 #line 340
     __cil_tmp14 = (int )__cil_tmp13;
 #line 340
     if (__cil_tmp14 != __cil_tmp12) {
 #line 341
       __cil_tmp15 = dev_priv->cur_delay;
 #line 341
       __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 341
       __cil_tmp17 = __cil_tmp16 + 255U;
 #line 341
       new_delay = (u8 )__cil_tmp17;
     } else {
 
     }
     }
     {
 #line 342
     __cil_tmp18 = (int )new_delay;
 #line 342
     __cil_tmp19 = dev_priv->max_delay;
 #line 342
     __cil_tmp20 = (int )__cil_tmp19;
 #line 342
     if (__cil_tmp20 > __cil_tmp18) {
 #line 343
       new_delay = dev_priv->max_delay;
     } else {
 
     }
     }
   } else
 #line 344
   if (busy_down < min_avg) {
     {
 #line 345
     __cil_tmp21 = dev_priv->min_delay;
 #line 345
     __cil_tmp22 = (int )__cil_tmp21;
 #line 345
     __cil_tmp23 = dev_priv->cur_delay;
 #line 345
     __cil_tmp24 = (int )__cil_tmp23;
 #line 345
     if (__cil_tmp24 != __cil_tmp22) {
 #line 346
       __cil_tmp25 = dev_priv->cur_delay;
 #line 346
       __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 346
       __cil_tmp27 = __cil_tmp26 + 1U;
 #line 346
       new_delay = (u8 )__cil_tmp27;
     } else {
 
     }
     }
     {
 #line 347
     __cil_tmp28 = (int )new_delay;
 #line 347
     __cil_tmp29 = dev_priv->min_delay;
 #line 347
     __cil_tmp30 = (int )__cil_tmp29;
 #line 347
     if (__cil_tmp30 < __cil_tmp28) {
 #line 348
       new_delay = dev_priv->min_delay;
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 351
   __cil_tmp31 = (int )new_delay;
 #line 351
   __cil_tmp32 = (u8 )__cil_tmp31;
 #line 351
   tmp = ironlake_set_drps(dev, __cil_tmp32);
   }
 #line 351
   if ((int )tmp) {
 #line 352
     dev_priv->cur_delay = new_delay;
   } else {
 
   }
 #line 354
   return;
 }
 }
 #line 357 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void notify_ring(struct drm_device *dev , struct intel_ring_buffer *ring ) 
 { struct drm_i915_private *dev_priv ;
   u32 seqno ;
   unsigned long tmp ;
   void *__cil_tmp6 ;
   struct drm_i915_gem_object *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_i915_gem_object *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   u32 (*__cil_tmp11)(struct intel_ring_buffer * ) ;
   wait_queue_head_t *__cil_tmp12 ;
   void *__cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   struct timer_list *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
 
   {
 #line 360
   __cil_tmp6 = dev->dev_private;
 #line 360
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
   {
 #line 363
   __cil_tmp7 = (struct drm_i915_gem_object *)0;
 #line 363
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 363
   __cil_tmp9 = ring->obj;
 #line 363
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 363
   if (__cil_tmp10 == __cil_tmp8) {
 #line 364
     return;
   } else {
 
   }
   }
   {
 #line 366
   __cil_tmp11 = ring->get_seqno;
 #line 366
   seqno = (*__cil_tmp11)(ring);
 #line 367
   trace_i915_gem_request_complete(ring, seqno);
 #line 369
   ring->irq_seqno = seqno;
 #line 370
   __cil_tmp12 = & ring->irq_queue;
 #line 370
   __cil_tmp13 = (void *)0;
 #line 370
   __wake_up(__cil_tmp12, 3U, 0, __cil_tmp13);
 #line 372
   dev_priv->hangcheck_count = 0;
 #line 373
   __cil_tmp14 = (unsigned int const   )1500U;
 #line 373
   __cil_tmp15 = (unsigned int )__cil_tmp14;
 #line 373
   tmp = msecs_to_jiffies(__cil_tmp15);
 #line 373
   __cil_tmp16 = & dev_priv->hangcheck_timer;
 #line 373
   __cil_tmp17 = (unsigned long )jiffies;
 #line 373
   __cil_tmp18 = tmp + __cil_tmp17;
 #line 373
   mod_timer(__cil_tmp16, __cil_tmp18);
   }
 #line 375
   return;
 }
 }
 #line 377 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void gen6_pm_rps_work(struct work_struct *work ) 
 { drm_i915_private_t *dev_priv ;
   struct work_struct  const  *__mptr ;
   u8 new_delay ;
   u32 pm_iir ;
   u32 pm_imr ;
   u32 tmp ;
   u32 tmp___0 ;
   drm_i915_private_t *__cil_tmp9 ;
   spinlock_t *__cil_tmp10 ;
   spinlock_t *__cil_tmp11 ;
   struct drm_device *__cil_tmp12 ;
   struct mutex *__cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   u8 __cil_tmp15 ;
   int __cil_tmp16 ;
   u8 __cil_tmp17 ;
   int __cil_tmp18 ;
   u8 __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   int __cil_tmp22 ;
   u8 __cil_tmp23 ;
   int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   u8 __cil_tmp26 ;
   int __cil_tmp27 ;
   u8 __cil_tmp28 ;
   int __cil_tmp29 ;
   u8 __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   int __cil_tmp33 ;
   u8 __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct drm_device *__cil_tmp42 ;
   int __cil_tmp43 ;
   u8 __cil_tmp44 ;
   u32 __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   struct drm_device *__cil_tmp47 ;
   struct mutex *__cil_tmp48 ;
 
   {
   {
 #line 379
   __mptr = (struct work_struct  const  *)work;
 #line 379
   __cil_tmp9 = (drm_i915_private_t *)__mptr;
 #line 379
   dev_priv = __cil_tmp9 + 1152921504606839592UL;
 #line 381
   new_delay = dev_priv->cur_delay;
 #line 384
   __cil_tmp10 = & dev_priv->rps_lock;
 #line 384
   spin_lock_irq(__cil_tmp10);
 #line 385
   pm_iir = dev_priv->pm_iir;
 #line 386
   dev_priv->pm_iir = 0U;
 #line 387
   pm_imr = i915_read32(dev_priv, 278564U);
 #line 388
   __cil_tmp11 = & dev_priv->rps_lock;
 #line 388
   spin_unlock_irq(__cil_tmp11);
   }
 #line 390
   if (pm_iir == 0U) {
 #line 391
     return;
   } else {
 
   }
   {
 #line 393
   __cil_tmp12 = dev_priv->dev;
 #line 393
   __cil_tmp13 = & __cil_tmp12->struct_mutex;
 #line 393
   mutex_lock_nested(__cil_tmp13, 0U);
   }
   {
 #line 394
   __cil_tmp14 = pm_iir & 32U;
 #line 394
   if (__cil_tmp14 != 0U) {
     {
 #line 395
     __cil_tmp15 = dev_priv->max_delay;
 #line 395
     __cil_tmp16 = (int )__cil_tmp15;
 #line 395
     __cil_tmp17 = dev_priv->cur_delay;
 #line 395
     __cil_tmp18 = (int )__cil_tmp17;
 #line 395
     if (__cil_tmp18 != __cil_tmp16) {
 #line 396
       __cil_tmp19 = dev_priv->cur_delay;
 #line 396
       __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 396
       __cil_tmp21 = __cil_tmp20 + 1U;
 #line 396
       new_delay = (u8 )__cil_tmp21;
     } else {
 
     }
     }
     {
 #line 397
     __cil_tmp22 = (int )new_delay;
 #line 397
     __cil_tmp23 = dev_priv->max_delay;
 #line 397
     __cil_tmp24 = (int )__cil_tmp23;
 #line 397
     if (__cil_tmp24 < __cil_tmp22) {
 #line 398
       new_delay = dev_priv->max_delay;
     } else {
 
     }
     }
   } else {
     {
 #line 399
     __cil_tmp25 = pm_iir & 80U;
 #line 399
     if (__cil_tmp25 != 0U) {
       {
 #line 400
       gen6_gt_force_wake_get(dev_priv);
       }
       {
 #line 401
       __cil_tmp26 = dev_priv->min_delay;
 #line 401
       __cil_tmp27 = (int )__cil_tmp26;
 #line 401
       __cil_tmp28 = dev_priv->cur_delay;
 #line 401
       __cil_tmp29 = (int )__cil_tmp28;
 #line 401
       if (__cil_tmp29 != __cil_tmp27) {
 #line 402
         __cil_tmp30 = dev_priv->cur_delay;
 #line 402
         __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 402
         __cil_tmp32 = __cil_tmp31 + 255U;
 #line 402
         new_delay = (u8 )__cil_tmp32;
       } else {
 
       }
       }
       {
 #line 403
       __cil_tmp33 = (int )new_delay;
 #line 403
       __cil_tmp34 = dev_priv->min_delay;
 #line 403
       __cil_tmp35 = (int )__cil_tmp34;
 #line 403
       if (__cil_tmp35 > __cil_tmp33) {
         {
 #line 404
         new_delay = dev_priv->min_delay;
 #line 405
         tmp = i915_read32(dev_priv, 40980U);
 #line 405
         __cil_tmp36 = (int )new_delay;
 #line 405
         __cil_tmp37 = __cil_tmp36 << 16;
 #line 405
         __cil_tmp38 = (u32 )__cil_tmp37;
 #line 405
         __cil_tmp39 = __cil_tmp38 & 4128768U;
 #line 405
         __cil_tmp40 = tmp | __cil_tmp39;
 #line 405
         i915_write32(dev_priv, 40980U, __cil_tmp40);
         }
       } else {
         {
 #line 411
         tmp___0 = i915_read32(dev_priv, 40980U);
 #line 411
         __cil_tmp41 = tmp___0 & 4290838527U;
 #line 411
         i915_write32(dev_priv, 40980U, __cil_tmp41);
         }
       }
       }
       {
 #line 414
       gen6_gt_force_wake_put(dev_priv);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 417
   __cil_tmp42 = dev_priv->dev;
 #line 417
   __cil_tmp43 = (int )new_delay;
 #line 417
   __cil_tmp44 = (u8 )__cil_tmp43;
 #line 417
   gen6_set_rps(__cil_tmp42, __cil_tmp44);
 #line 418
   dev_priv->cur_delay = new_delay;
 #line 425
   __cil_tmp45 = ~ pm_iir;
 #line 425
   __cil_tmp46 = __cil_tmp45 & pm_imr;
 #line 425
   i915_write32(dev_priv, 278564U, __cil_tmp46);
 #line 426
   __cil_tmp47 = dev_priv->dev;
 #line 426
   __cil_tmp48 = & __cil_tmp47->struct_mutex;
 #line 426
   mutex_unlock(__cil_tmp48);
   }
 #line 427
   return;
 }
 }
 #line 429 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void pch_irq_handler(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 pch_iir ;
   int pipe ;
   u32 tmp ;
   void *__cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   u32 __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   int __cil_tmp23 ;
 
   {
   {
 #line 431
   __cil_tmp6 = dev->dev_private;
 #line 431
   dev_priv = (drm_i915_private_t *)__cil_tmp6;
 #line 435
   pch_iir = i915_read32(dev_priv, 802824U);
   }
   {
 #line 437
   __cil_tmp7 = pch_iir & 234881024U;
 #line 437
   if (__cil_tmp7 != 0U) {
     {
 #line 438
     __cil_tmp8 = pch_iir & 234881024U;
 #line 438
     __cil_tmp9 = __cil_tmp8 >> 25;
 #line 438
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH audio power change on port %d\n",
                         __cil_tmp9);
     }
   } else {
 
   }
   }
   {
 #line 442
   __cil_tmp10 = pch_iir & 16777216U;
 #line 442
   if (__cil_tmp10 != 0U) {
     {
 #line 443
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH GMBUS interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 445
   __cil_tmp11 = pch_iir & 12582912U;
 #line 445
   if (__cil_tmp11 != 0U) {
     {
 #line 446
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH HDCP audio interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 448
   __cil_tmp12 = pch_iir & 3145728U;
 #line 448
   if (__cil_tmp12 != 0U) {
     {
 #line 449
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH transcoder audio interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 451
   __cil_tmp13 = pch_iir & 524288U;
 #line 451
   if (__cil_tmp13 != 0U) {
     {
 #line 452
     drm_err("pch_irq_handler", "PCH poison interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 454
   __cil_tmp14 = pch_iir & 196608U;
 #line 454
   if (__cil_tmp14 != 0U) {
 #line 455
     pipe = 0;
 #line 455
     goto ldv_37676;
     ldv_37675: 
     {
 #line 456
     __cil_tmp15 = pipe * 4096;
 #line 456
     __cil_tmp16 = __cil_tmp15 + 983060;
 #line 456
     __cil_tmp17 = (u32 )__cil_tmp16;
 #line 456
     tmp = i915_read32(dev_priv, __cil_tmp17);
 #line 456
     __cil_tmp18 = pipe + 65;
 #line 456
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "  pipe %c FDI IIR: 0x%08x\n",
                         __cil_tmp18, tmp);
 #line 455
     pipe = pipe + 1;
     }
     ldv_37676: ;
     {
 #line 455
     __cil_tmp19 = dev_priv->num_pipe;
 #line 455
     if (__cil_tmp19 > pipe) {
 #line 456
       goto ldv_37675;
     } else {
 #line 458
       goto ldv_37677;
     }
     }
     ldv_37677: ;
   } else {
 
   }
   }
   {
 #line 460
   __cil_tmp20 = pch_iir & 36U;
 #line 460
   if (__cil_tmp20 != 0U) {
     {
 #line 461
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH transcoder CRC done interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 463
   __cil_tmp21 = pch_iir & 18U;
 #line 463
   if (__cil_tmp21 != 0U) {
     {
 #line 464
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH transcoder CRC error interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 466
   __cil_tmp22 = pch_iir & 8U;
 #line 466
   if (__cil_tmp22 != 0U) {
     {
 #line 467
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH transcoder B underrun interrupt\n");
     }
   } else {
 
   }
   }
   {
 #line 468
   __cil_tmp23 = (int )pch_iir;
 #line 468
   if (__cil_tmp23 & 1) {
     {
 #line 469
     drm_ut_debug_printk(2U, "drm", "pch_irq_handler", "PCH transcoder A underrun interrupt\n");
     }
   } else {
 
   }
   }
 #line 470
   return;
 }
 }
 #line 472 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static irqreturn_t ivybridge_irq_handler(int irq , void *arg ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   u32 de_iir ;
   u32 gt_iir ;
   u32 de_ier ;
   u32 pch_iir ;
   u32 pm_iir ;
   struct drm_i915_master_private *master_priv ;
   u32 tmp ;
   unsigned long flags ;
   raw_spinlock_t *tmp___0 ;
   int __ret_warn_on ;
   long tmp___1 ;
   void *__cil_tmp17 ;
   atomic_t *__cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   void *__cil_tmp20 ;
   void const volatile   *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   struct drm_master *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct drm_minor *__cil_tmp25 ;
   struct drm_master *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct drm_minor *__cil_tmp28 ;
   struct drm_master *__cil_tmp29 ;
   void *__cil_tmp30 ;
   struct _drm_i915_sarea *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   struct _drm_i915_sarea *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   struct intel_ring_buffer (*__cil_tmp35)[3U] ;
   struct intel_ring_buffer *__cil_tmp36 ;
   struct _drm_i915_sarea *__cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   struct intel_ring_buffer (*__cil_tmp39)[3U] ;
   struct intel_ring_buffer *__cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct intel_ring_buffer (*__cil_tmp42)[3U] ;
   struct intel_ring_buffer *__cil_tmp43 ;
   struct intel_ring_buffer *__cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   struct intel_ring_buffer (*__cil_tmp46)[3U] ;
   struct intel_ring_buffer *__cil_tmp47 ;
   struct intel_ring_buffer *__cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   int __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   struct workqueue_struct *__cil_tmp56 ;
   struct work_struct *__cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   spinlock_t *__cil_tmp59 ;
   u32 __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   int __cil_tmp62 ;
   long __cil_tmp63 ;
   int __cil_tmp64 ;
   int __cil_tmp65 ;
   int __cil_tmp66 ;
   long __cil_tmp67 ;
   u32 __cil_tmp68 ;
   spinlock_t *__cil_tmp69 ;
   struct workqueue_struct *__cil_tmp70 ;
   struct work_struct *__cil_tmp71 ;
   void *__cil_tmp72 ;
   void const volatile   *__cil_tmp73 ;
   void const volatile   *__cil_tmp74 ;
 
   {
   {
 #line 474
   dev = (struct drm_device *)arg;
 #line 475
   __cil_tmp17 = dev->dev_private;
 #line 475
   dev_priv = (drm_i915_private_t *)__cil_tmp17;
 #line 476
   ret = 0;
 #line 480
   __cil_tmp18 = & dev_priv->irq_received;
 #line 480
   atomic_inc(__cil_tmp18);
 #line 483
   de_ier = i915_read32(dev_priv, 278540U);
 #line 484
   __cil_tmp19 = de_ier & 2147483647U;
 #line 484
   i915_write32(dev_priv, 278540U, __cil_tmp19);
 #line 485
   __cil_tmp20 = dev_priv->regs;
 #line 485
   __cil_tmp21 = (void const volatile   *)__cil_tmp20;
 #line 485
   __cil_tmp22 = __cil_tmp21 + 278540U;
 #line 485
   readl(__cil_tmp22);
 #line 487
   de_iir = i915_read32(dev_priv, 278536U);
 #line 488
   gt_iir = i915_read32(dev_priv, 278552U);
 #line 489
   pch_iir = i915_read32(dev_priv, 802824U);
 #line 490
   pm_iir = i915_read32(dev_priv, 278568U);
   }
 #line 492
   if (de_iir == 0U) {
 #line 492
     if (gt_iir == 0U) {
 #line 492
       if (pch_iir == 0U) {
 #line 492
         if (pm_iir == 0U) {
 #line 493
           goto done;
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
 #line 495
   ret = 1;
   {
 #line 497
   __cil_tmp23 = (struct drm_master *)0;
 #line 497
   __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 497
   __cil_tmp25 = dev->primary;
 #line 497
   __cil_tmp26 = __cil_tmp25->master;
 #line 497
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 497
   if (__cil_tmp27 != __cil_tmp24) {
 #line 498
     __cil_tmp28 = dev->primary;
 #line 498
     __cil_tmp29 = __cil_tmp28->master;
 #line 498
     __cil_tmp30 = __cil_tmp29->driver_priv;
 #line 498
     master_priv = (struct drm_i915_master_private *)__cil_tmp30;
     {
 #line 499
     __cil_tmp31 = (struct _drm_i915_sarea *)0;
 #line 499
     __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 499
     __cil_tmp33 = master_priv->sarea_priv;
 #line 499
     __cil_tmp34 = (unsigned long )__cil_tmp33;
 #line 499
     if (__cil_tmp34 != __cil_tmp32) {
       {
 #line 500
       __cil_tmp35 = & dev_priv->ring;
 #line 500
       __cil_tmp36 = (struct intel_ring_buffer *)__cil_tmp35;
 #line 500
       tmp = intel_read_status_page(__cil_tmp36, 33);
 #line 500
       __cil_tmp37 = master_priv->sarea_priv;
 #line 500
       __cil_tmp37->last_dispatch = (int )tmp;
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 504
   __cil_tmp38 = gt_iir & 17U;
 #line 504
   if (__cil_tmp38 != 0U) {
     {
 #line 505
     __cil_tmp39 = & dev_priv->ring;
 #line 505
     __cil_tmp40 = (struct intel_ring_buffer *)__cil_tmp39;
 #line 505
     notify_ring(dev, __cil_tmp40);
     }
   } else {
 
   }
   }
   {
 #line 506
   __cil_tmp41 = gt_iir & 4096U;
 #line 506
   if (__cil_tmp41 != 0U) {
     {
 #line 507
     __cil_tmp42 = & dev_priv->ring;
 #line 507
     __cil_tmp43 = (struct intel_ring_buffer *)__cil_tmp42;
 #line 507
     __cil_tmp44 = __cil_tmp43 + 1UL;
 #line 507
     notify_ring(dev, __cil_tmp44);
     }
   } else {
 
   }
   }
   {
 #line 508
   __cil_tmp45 = gt_iir & 4194304U;
 #line 508
   if (__cil_tmp45 != 0U) {
     {
 #line 509
     __cil_tmp46 = & dev_priv->ring;
 #line 509
     __cil_tmp47 = (struct intel_ring_buffer *)__cil_tmp46;
 #line 509
     __cil_tmp48 = __cil_tmp47 + 2UL;
 #line 509
     notify_ring(dev, __cil_tmp48);
     }
   } else {
 
   }
   }
   {
 #line 511
   __cil_tmp49 = de_iir & 536870912U;
 #line 511
   if (__cil_tmp49 != 0U) {
     {
 #line 512
     intel_opregion_gse_intr(dev);
     }
   } else {
 
   }
   }
   {
 #line 514
   __cil_tmp50 = de_iir & 8U;
 #line 514
   if (__cil_tmp50 != 0U) {
     {
 #line 515
     intel_prepare_page_flip(dev, 0);
 #line 516
     intel_finish_page_flip_plane(dev, 0);
     }
   } else {
 
   }
   }
   {
 #line 519
   __cil_tmp51 = de_iir & 256U;
 #line 519
   if (__cil_tmp51 != 0U) {
     {
 #line 520
     intel_prepare_page_flip(dev, 1);
 #line 521
     intel_finish_page_flip_plane(dev, 1);
     }
   } else {
 
   }
   }
   {
 #line 524
   __cil_tmp52 = (int )de_iir;
 #line 524
   if (__cil_tmp52 & 1) {
     {
 #line 525
     drm_handle_vblank(dev, 0);
     }
   } else {
 
   }
   }
   {
 #line 527
   __cil_tmp53 = de_iir & 32U;
 #line 527
   if (__cil_tmp53 != 0U) {
     {
 #line 528
     drm_handle_vblank(dev, 1);
     }
   } else {
 
   }
   }
   {
 #line 531
   __cil_tmp54 = de_iir & 268435456U;
 #line 531
   if (__cil_tmp54 != 0U) {
     {
 #line 532
     __cil_tmp55 = pch_iir & 15204352U;
 #line 532
     if (__cil_tmp55 != 0U) {
       {
 #line 533
       __cil_tmp56 = dev_priv->wq;
 #line 533
       __cil_tmp57 = & dev_priv->hotplug_work;
 #line 533
       queue_work(__cil_tmp56, __cil_tmp57);
       }
     } else {
 
     }
     }
     {
 #line 534
     pch_irq_handler(dev);
     }
   } else {
 
   }
   }
   {
 #line 537
   __cil_tmp58 = pm_iir & 112U;
 #line 537
   if (__cil_tmp58 != 0U) {
     {
 #line 539
     __cil_tmp59 = & dev_priv->rps_lock;
 #line 539
     tmp___0 = spinlock_check(__cil_tmp59);
 #line 539
     flags = _raw_spin_lock_irqsave(tmp___0);
 #line 540
     __cil_tmp60 = dev_priv->pm_iir;
 #line 540
     __cil_tmp61 = __cil_tmp60 & pm_iir;
 #line 540
     __ret_warn_on = __cil_tmp61 != 0U;
 #line 540
     __cil_tmp62 = __ret_warn_on != 0;
 #line 540
     __cil_tmp63 = (long )__cil_tmp62;
 #line 540
     tmp___1 = __builtin_expect(__cil_tmp63, 0L);
     }
 #line 540
     if (tmp___1 != 0L) {
       {
 #line 540
       __cil_tmp64 = (int const   )540;
 #line 540
       __cil_tmp65 = (int )__cil_tmp64;
 #line 540
       warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p",
                         __cil_tmp65, "Missed a PM interrupt\n");
       }
     } else {
 
     }
     {
 #line 540
     __cil_tmp66 = __ret_warn_on != 0;
 #line 540
     __cil_tmp67 = (long )__cil_tmp66;
 #line 540
     __builtin_expect(__cil_tmp67, 0L);
 #line 541
     i915_write32(dev_priv, 278564U, pm_iir);
 #line 542
     __cil_tmp68 = dev_priv->pm_iir;
 #line 542
     dev_priv->pm_iir = __cil_tmp68 | pm_iir;
 #line 543
     __cil_tmp69 = & dev_priv->rps_lock;
 #line 543
     spin_unlock_irqrestore(__cil_tmp69, flags);
 #line 544
     __cil_tmp70 = dev_priv->wq;
 #line 544
     __cil_tmp71 = & dev_priv->rps_work;
 #line 544
     queue_work(__cil_tmp70, __cil_tmp71);
     }
   } else {
 
   }
   }
   {
 #line 548
   i915_write32(dev_priv, 802824U, pch_iir);
 #line 549
   i915_write32(dev_priv, 278552U, gt_iir);
 #line 550
   i915_write32(dev_priv, 278536U, de_iir);
 #line 551
   i915_write32(dev_priv, 278568U, pm_iir);
   }
   done: 
   {
 #line 554
   i915_write32(dev_priv, 278540U, de_ier);
 #line 555
   __cil_tmp72 = dev_priv->regs;
 #line 555
   __cil_tmp73 = (void const volatile   *)__cil_tmp72;
 #line 555
   __cil_tmp74 = __cil_tmp73 + 278540U;
 #line 555
   readl(__cil_tmp74);
   }
 #line 557
   return ((irqreturn_t )ret);
 }
 }
 #line 560 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static irqreturn_t ironlake_irq_handler(int irq , void *arg ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   u32 de_iir ;
   u32 gt_iir ;
   u32 de_ier ;
   u32 pch_iir ;
   u32 pm_iir ;
   u32 hotplug_mask ;
   struct drm_i915_master_private *master_priv ;
   u32 bsd_usr_interrupt ;
   u32 tmp ;
   u32 tmp___0 ;
   unsigned long flags ;
   raw_spinlock_t *tmp___1 ;
   int __ret_warn_on ;
   long tmp___2 ;
   void *__cil_tmp20 ;
   atomic_t *__cil_tmp21 ;
   void *__cil_tmp22 ;
   struct drm_i915_private *__cil_tmp23 ;
   struct intel_device_info  const  *__cil_tmp24 ;
   u8 __cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   void *__cil_tmp29 ;
   void const volatile   *__cil_tmp30 ;
   void const volatile   *__cil_tmp31 ;
   void *__cil_tmp32 ;
   struct drm_i915_private *__cil_tmp33 ;
   struct intel_device_info  const  *__cil_tmp34 ;
   u8 __cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   void *__cil_tmp38 ;
   struct drm_i915_private *__cil_tmp39 ;
   enum intel_pch __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct drm_master *__cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   struct drm_minor *__cil_tmp44 ;
   struct drm_master *__cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   struct drm_minor *__cil_tmp47 ;
   struct drm_master *__cil_tmp48 ;
   void *__cil_tmp49 ;
   struct _drm_i915_sarea *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   struct _drm_i915_sarea *__cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   struct intel_ring_buffer (*__cil_tmp54)[3U] ;
   struct intel_ring_buffer *__cil_tmp55 ;
   struct _drm_i915_sarea *__cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   struct intel_ring_buffer (*__cil_tmp58)[3U] ;
   struct intel_ring_buffer *__cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   struct intel_ring_buffer (*__cil_tmp61)[3U] ;
   struct intel_ring_buffer *__cil_tmp62 ;
   struct intel_ring_buffer *__cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   struct intel_ring_buffer (*__cil_tmp65)[3U] ;
   struct intel_ring_buffer *__cil_tmp66 ;
   struct intel_ring_buffer *__cil_tmp67 ;
   unsigned int __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   unsigned int __cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   unsigned int __cil_tmp72 ;
   unsigned int __cil_tmp73 ;
   unsigned int __cil_tmp74 ;
   struct workqueue_struct *__cil_tmp75 ;
   struct work_struct *__cil_tmp76 ;
   unsigned int __cil_tmp77 ;
   u16 __cil_tmp78 ;
   int __cil_tmp79 ;
   u16 __cil_tmp80 ;
   void *__cil_tmp81 ;
   struct drm_i915_private *__cil_tmp82 ;
   struct intel_device_info  const  *__cil_tmp83 ;
   u8 __cil_tmp84 ;
   unsigned char __cil_tmp85 ;
   unsigned int __cil_tmp86 ;
   unsigned int __cil_tmp87 ;
   spinlock_t *__cil_tmp88 ;
   u32 __cil_tmp89 ;
   unsigned int __cil_tmp90 ;
   int __cil_tmp91 ;
   long __cil_tmp92 ;
   int __cil_tmp93 ;
   int __cil_tmp94 ;
   int __cil_tmp95 ;
   long __cil_tmp96 ;
   u32 __cil_tmp97 ;
   spinlock_t *__cil_tmp98 ;
   struct workqueue_struct *__cil_tmp99 ;
   struct work_struct *__cil_tmp100 ;
   void *__cil_tmp101 ;
   void const volatile   *__cil_tmp102 ;
   void const volatile   *__cil_tmp103 ;
 
   {
   {
 #line 562
   dev = (struct drm_device *)arg;
 #line 563
   __cil_tmp20 = dev->dev_private;
 #line 563
   dev_priv = (drm_i915_private_t *)__cil_tmp20;
 #line 564
   ret = 0;
 #line 568
   bsd_usr_interrupt = 32U;
 #line 570
   __cil_tmp21 = & dev_priv->irq_received;
 #line 570
   atomic_inc(__cil_tmp21);
   }
   {
 #line 572
   __cil_tmp22 = dev->dev_private;
 #line 572
   __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
 #line 572
   __cil_tmp24 = __cil_tmp23->info;
 #line 572
   __cil_tmp25 = __cil_tmp24->gen;
 #line 572
   __cil_tmp26 = (unsigned char )__cil_tmp25;
 #line 572
   __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 572
   if (__cil_tmp27 == 6U) {
 #line 573
     bsd_usr_interrupt = 4096U;
   } else {
 
   }
   }
   {
 #line 576
   de_ier = i915_read32(dev_priv, 278540U);
 #line 577
   __cil_tmp28 = de_ier & 2147483647U;
 #line 577
   i915_write32(dev_priv, 278540U, __cil_tmp28);
 #line 578
   __cil_tmp29 = dev_priv->regs;
 #line 578
   __cil_tmp30 = (void const volatile   *)__cil_tmp29;
 #line 578
   __cil_tmp31 = __cil_tmp30 + 278540U;
 #line 578
   readl(__cil_tmp31);
 #line 580
   de_iir = i915_read32(dev_priv, 278536U);
 #line 581
   gt_iir = i915_read32(dev_priv, 278552U);
 #line 582
   pch_iir = i915_read32(dev_priv, 802824U);
 #line 583
   pm_iir = i915_read32(dev_priv, 278568U);
   }
 #line 585
   if (de_iir == 0U) {
 #line 585
     if (gt_iir == 0U) {
 #line 585
       if (pch_iir == 0U) {
         {
 #line 585
         __cil_tmp32 = dev->dev_private;
 #line 585
         __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
 #line 585
         __cil_tmp34 = __cil_tmp33->info;
 #line 585
         __cil_tmp35 = __cil_tmp34->gen;
 #line 585
         __cil_tmp36 = (unsigned char )__cil_tmp35;
 #line 585
         __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 585
         if (__cil_tmp37 != 6U) {
 #line 587
           goto done;
         } else
 #line 585
         if (pm_iir == 0U) {
 #line 587
           goto done;
         } else {
 
         }
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 589
   __cil_tmp38 = dev->dev_private;
 #line 589
   __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
 #line 589
   __cil_tmp40 = __cil_tmp39->pch_type;
 #line 589
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 589
   if (__cil_tmp41 == 1U) {
 #line 590
     hotplug_mask = 15204352U;
   } else {
 #line 592
     hotplug_mask = 3840U;
   }
   }
 #line 594
   ret = 1;
   {
 #line 596
   __cil_tmp42 = (struct drm_master *)0;
 #line 596
   __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 596
   __cil_tmp44 = dev->primary;
 #line 596
   __cil_tmp45 = __cil_tmp44->master;
 #line 596
   __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 596
   if (__cil_tmp46 != __cil_tmp43) {
 #line 597
     __cil_tmp47 = dev->primary;
 #line 597
     __cil_tmp48 = __cil_tmp47->master;
 #line 597
     __cil_tmp49 = __cil_tmp48->driver_priv;
 #line 597
     master_priv = (struct drm_i915_master_private *)__cil_tmp49;
     {
 #line 598
     __cil_tmp50 = (struct _drm_i915_sarea *)0;
 #line 598
     __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 598
     __cil_tmp52 = master_priv->sarea_priv;
 #line 598
     __cil_tmp53 = (unsigned long )__cil_tmp52;
 #line 598
     if (__cil_tmp53 != __cil_tmp51) {
       {
 #line 599
       __cil_tmp54 = & dev_priv->ring;
 #line 599
       __cil_tmp55 = (struct intel_ring_buffer *)__cil_tmp54;
 #line 599
       tmp = intel_read_status_page(__cil_tmp55, 33);
 #line 599
       __cil_tmp56 = master_priv->sarea_priv;
 #line 599
       __cil_tmp56->last_dispatch = (int )tmp;
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 603
   __cil_tmp57 = gt_iir & 17U;
 #line 603
   if (__cil_tmp57 != 0U) {
     {
 #line 604
     __cil_tmp58 = & dev_priv->ring;
 #line 604
     __cil_tmp59 = (struct intel_ring_buffer *)__cil_tmp58;
 #line 604
     notify_ring(dev, __cil_tmp59);
     }
   } else {
 
   }
   }
   {
 #line 605
   __cil_tmp60 = gt_iir & bsd_usr_interrupt;
 #line 605
   if (__cil_tmp60 != 0U) {
     {
 #line 606
     __cil_tmp61 = & dev_priv->ring;
 #line 606
     __cil_tmp62 = (struct intel_ring_buffer *)__cil_tmp61;
 #line 606
     __cil_tmp63 = __cil_tmp62 + 1UL;
 #line 606
     notify_ring(dev, __cil_tmp63);
     }
   } else {
 
   }
   }
   {
 #line 607
   __cil_tmp64 = gt_iir & 4194304U;
 #line 607
   if (__cil_tmp64 != 0U) {
     {
 #line 608
     __cil_tmp65 = & dev_priv->ring;
 #line 608
     __cil_tmp66 = (struct intel_ring_buffer *)__cil_tmp65;
 #line 608
     __cil_tmp67 = __cil_tmp66 + 2UL;
 #line 608
     notify_ring(dev, __cil_tmp67);
     }
   } else {
 
   }
   }
   {
 #line 610
   __cil_tmp68 = de_iir & 262144U;
 #line 610
   if (__cil_tmp68 != 0U) {
     {
 #line 611
     intel_opregion_gse_intr(dev);
     }
   } else {
 
   }
   }
   {
 #line 613
   __cil_tmp69 = de_iir & 67108864U;
 #line 613
   if (__cil_tmp69 != 0U) {
     {
 #line 614
     intel_prepare_page_flip(dev, 0);
 #line 615
     intel_finish_page_flip_plane(dev, 0);
     }
   } else {
 
   }
   }
   {
 #line 618
   __cil_tmp70 = de_iir & 134217728U;
 #line 618
   if (__cil_tmp70 != 0U) {
     {
 #line 619
     intel_prepare_page_flip(dev, 1);
 #line 620
     intel_finish_page_flip_plane(dev, 1);
     }
   } else {
 
   }
   }
   {
 #line 623
   __cil_tmp71 = de_iir & 128U;
 #line 623
   if (__cil_tmp71 != 0U) {
     {
 #line 624
     drm_handle_vblank(dev, 0);
     }
   } else {
 
   }
   }
   {
 #line 626
   __cil_tmp72 = de_iir & 32768U;
 #line 626
   if (__cil_tmp72 != 0U) {
     {
 #line 627
     drm_handle_vblank(dev, 1);
     }
   } else {
 
   }
   }
   {
 #line 630
   __cil_tmp73 = de_iir & 2097152U;
 #line 630
   if (__cil_tmp73 != 0U) {
     {
 #line 631
     __cil_tmp74 = pch_iir & hotplug_mask;
 #line 631
     if (__cil_tmp74 != 0U) {
       {
 #line 632
       __cil_tmp75 = dev_priv->wq;
 #line 632
       __cil_tmp76 = & dev_priv->hotplug_work;
 #line 632
       queue_work(__cil_tmp75, __cil_tmp76);
       }
     } else {
 
     }
     }
     {
 #line 633
     pch_irq_handler(dev);
     }
   } else {
 
   }
   }
   {
 #line 636
   __cil_tmp77 = de_iir & 33554432U;
 #line 636
   if (__cil_tmp77 != 0U) {
     {
 #line 637
     tmp___0 = i915_read32(dev_priv, 70020U);
 #line 637
     __cil_tmp78 = (u16 )tmp___0;
 #line 637
     __cil_tmp79 = (int )__cil_tmp78;
 #line 637
     __cil_tmp80 = (u16 )__cil_tmp79;
 #line 637
     i915_write16(dev_priv, 70020U, __cil_tmp80);
 #line 638
     i915_handle_rps_change(dev);
     }
   } else {
 
   }
   }
   {
 #line 641
   __cil_tmp81 = dev->dev_private;
 #line 641
   __cil_tmp82 = (struct drm_i915_private *)__cil_tmp81;
 #line 641
   __cil_tmp83 = __cil_tmp82->info;
 #line 641
   __cil_tmp84 = __cil_tmp83->gen;
 #line 641
   __cil_tmp85 = (unsigned char )__cil_tmp84;
 #line 641
   __cil_tmp86 = (unsigned int )__cil_tmp85;
 #line 641
   if (__cil_tmp86 == 6U) {
     {
 #line 641
     __cil_tmp87 = pm_iir & 112U;
 #line 641
     if (__cil_tmp87 != 0U) {
       {
 #line 652
       __cil_tmp88 = & dev_priv->rps_lock;
 #line 652
       tmp___1 = spinlock_check(__cil_tmp88);
 #line 652
       flags = _raw_spin_lock_irqsave(tmp___1);
 #line 653
       __cil_tmp89 = dev_priv->pm_iir;
 #line 653
       __cil_tmp90 = __cil_tmp89 & pm_iir;
 #line 653
       __ret_warn_on = __cil_tmp90 != 0U;
 #line 653
       __cil_tmp91 = __ret_warn_on != 0;
 #line 653
       __cil_tmp92 = (long )__cil_tmp91;
 #line 653
       tmp___2 = __builtin_expect(__cil_tmp92, 0L);
       }
 #line 653
       if (tmp___2 != 0L) {
         {
 #line 653
         __cil_tmp93 = (int const   )653;
 #line 653
         __cil_tmp94 = (int )__cil_tmp93;
 #line 653
         warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p",
                           __cil_tmp94, "Missed a PM interrupt\n");
         }
       } else {
 
       }
       {
 #line 653
       __cil_tmp95 = __ret_warn_on != 0;
 #line 653
       __cil_tmp96 = (long )__cil_tmp95;
 #line 653
       __builtin_expect(__cil_tmp96, 0L);
 #line 654
       i915_write32(dev_priv, 278564U, pm_iir);
 #line 655
       __cil_tmp97 = dev_priv->pm_iir;
 #line 655
       dev_priv->pm_iir = __cil_tmp97 | pm_iir;
 #line 656
       __cil_tmp98 = & dev_priv->rps_lock;
 #line 656
       spin_unlock_irqrestore(__cil_tmp98, flags);
 #line 657
       __cil_tmp99 = dev_priv->wq;
 #line 657
       __cil_tmp100 = & dev_priv->rps_work;
 #line 657
       queue_work(__cil_tmp99, __cil_tmp100);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 661
   i915_write32(dev_priv, 802824U, pch_iir);
 #line 662
   i915_write32(dev_priv, 278552U, gt_iir);
 #line 663
   i915_write32(dev_priv, 278536U, de_iir);
 #line 664
   i915_write32(dev_priv, 278568U, pm_iir);
   }
   done: 
   {
 #line 667
   i915_write32(dev_priv, 278540U, de_ier);
 #line 668
   __cil_tmp101 = dev_priv->regs;
 #line 668
   __cil_tmp102 = (void const volatile   *)__cil_tmp101;
 #line 668
   __cil_tmp103 = __cil_tmp102 + 278540U;
 #line 668
   readl(__cil_tmp103);
   }
 #line 670
   return ((irqreturn_t )ret);
 }
 }
 #line 680 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_error_work_func(struct work_struct *work ) 
 { drm_i915_private_t *dev_priv ;
   struct work_struct  const  *__mptr ;
   struct drm_device *dev ;
   char *error_event[2U] ;
   char *reset_event[2U] ;
   char *reset_done_event[2U] ;
   int tmp ;
   int tmp___0 ;
   drm_i915_private_t *__cil_tmp10 ;
   struct drm_minor *__cil_tmp11 ;
   struct kobject *__cil_tmp12 ;
   enum kobject_action __cil_tmp13 ;
   char **__cil_tmp14 ;
   atomic_t *__cil_tmp15 ;
   atomic_t const   *__cil_tmp16 ;
   struct drm_minor *__cil_tmp17 ;
   struct kobject *__cil_tmp18 ;
   enum kobject_action __cil_tmp19 ;
   char **__cil_tmp20 ;
   u8 __cil_tmp21 ;
   atomic_t *__cil_tmp22 ;
   struct drm_minor *__cil_tmp23 ;
   struct kobject *__cil_tmp24 ;
   enum kobject_action __cil_tmp25 ;
   char **__cil_tmp26 ;
   struct completion *__cil_tmp27 ;
 
   {
   {
 #line 682
   __mptr = (struct work_struct  const  *)work;
 #line 682
   __cil_tmp10 = (drm_i915_private_t *)__mptr;
 #line 682
   dev_priv = __cil_tmp10 + 1152921504606844208UL;
 #line 684
   dev = dev_priv->dev;
 #line 685
   error_event[0] = (char *)"ERROR=1";
 #line 685
   error_event[1] = (char *)0;
 #line 686
   reset_event[0] = (char *)"RESET=1";
 #line 686
   reset_event[1] = (char *)0;
 #line 687
   reset_done_event[0] = (char *)"ERROR=0";
 #line 687
   reset_done_event[1] = (char *)0;
 #line 689
   __cil_tmp11 = dev->primary;
 #line 689
   __cil_tmp12 = & __cil_tmp11->kdev.kobj;
 #line 689
   __cil_tmp13 = (enum kobject_action )2;
 #line 689
   __cil_tmp14 = (char **)(& error_event);
 #line 689
   kobject_uevent_env(__cil_tmp12, __cil_tmp13, __cil_tmp14);
 #line 691
   __cil_tmp15 = & dev_priv->mm.wedged;
 #line 691
   __cil_tmp16 = (atomic_t const   *)__cil_tmp15;
 #line 691
   tmp___0 = atomic_read(__cil_tmp16);
   }
 #line 691
   if (tmp___0 != 0) {
     {
 #line 692
     drm_ut_debug_printk(2U, "drm", "i915_error_work_func", "resetting chip\n");
 #line 693
     __cil_tmp17 = dev->primary;
 #line 693
     __cil_tmp18 = & __cil_tmp17->kdev.kobj;
 #line 693
     __cil_tmp19 = (enum kobject_action )2;
 #line 693
     __cil_tmp20 = (char **)(& reset_event);
 #line 693
     kobject_uevent_env(__cil_tmp18, __cil_tmp19, __cil_tmp20);
 #line 694
     __cil_tmp21 = (u8 )4;
 #line 694
     tmp = i915_reset(dev, __cil_tmp21);
     }
 #line 694
     if (tmp == 0) {
       {
 #line 695
       __cil_tmp22 = & dev_priv->mm.wedged;
 #line 695
       atomic_set(__cil_tmp22, 0);
 #line 696
       __cil_tmp23 = dev->primary;
 #line 696
       __cil_tmp24 = & __cil_tmp23->kdev.kobj;
 #line 696
       __cil_tmp25 = (enum kobject_action )2;
 #line 696
       __cil_tmp26 = (char **)(& reset_done_event);
 #line 696
       kobject_uevent_env(__cil_tmp24, __cil_tmp25, __cil_tmp26);
       }
     } else {
 
     }
     {
 #line 698
     __cil_tmp27 = & dev_priv->error_completion;
 #line 698
     complete_all(__cil_tmp27);
     }
   } else {
 
   }
 #line 700
   return;
 }
 }
 #line 704 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static struct drm_i915_error_object *i915_error_object_create(struct drm_i915_private *dev_priv ,
                                                               struct drm_i915_gem_object *src ) 
 { struct drm_i915_error_object *dst ;
   int page ;
   int page_count___0 ;
   u32 reloc_offset ;
   void *tmp ;
   unsigned long flags ;
   void *s ;
   void *d ;
   int tmp___0 ;
   int tmp___1 ;
   struct drm_i915_gem_object *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct page **__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct page **__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   size_t __cil_tmp20 ;
   size_t __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct drm_i915_error_object *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   void *__cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   struct io_mapping *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   void const volatile   *__cil_tmp33 ;
   u32 *__cil_tmp34 ;
   void const   *__cil_tmp35 ;
   void const   *__cil_tmp36 ;
 
   {
   {
 #line 711
   __cil_tmp13 = (struct drm_i915_gem_object *)0;
 #line 711
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 711
   __cil_tmp15 = (unsigned long )src;
 #line 711
   if (__cil_tmp15 == __cil_tmp14) {
 #line 712
     return ((struct drm_i915_error_object *)0);
   } else {
     {
 #line 711
     __cil_tmp16 = (struct page **)0;
 #line 711
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 711
     __cil_tmp18 = src->pages;
 #line 711
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 711
     if (__cil_tmp19 == __cil_tmp17) {
 #line 712
       return ((struct drm_i915_error_object *)0);
     } else {
 
     }
     }
   }
   }
   {
 #line 714
   __cil_tmp20 = src->base.size;
 #line 714
   __cil_tmp21 = __cil_tmp20 / 4096UL;
 #line 714
   page_count___0 = (int )__cil_tmp21;
 #line 716
   __cil_tmp22 = (unsigned long )page_count___0;
 #line 716
   __cil_tmp23 = __cil_tmp22 + 1UL;
 #line 716
   __cil_tmp24 = __cil_tmp23 * 8UL;
 #line 716
   tmp = kmalloc(__cil_tmp24, 32U);
 #line 716
   dst = (struct drm_i915_error_object *)tmp;
   }
   {
 #line 717
   __cil_tmp25 = (struct drm_i915_error_object *)0;
 #line 717
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 717
   __cil_tmp27 = (unsigned long )dst;
 #line 717
   if (__cil_tmp27 == __cil_tmp26) {
 #line 718
     return ((struct drm_i915_error_object *)0);
   } else {
 
   }
   }
 #line 720
   reloc_offset = src->gtt_offset;
 #line 721
   page = 0;
 #line 721
   goto ldv_37757;
   ldv_37756: 
   {
 #line 726
   d = kmalloc(4096UL, 32U);
   }
   {
 #line 727
   __cil_tmp28 = (void *)0;
 #line 727
   __cil_tmp29 = (unsigned long )__cil_tmp28;
 #line 727
   __cil_tmp30 = (unsigned long )d;
 #line 727
   if (__cil_tmp30 == __cil_tmp29) {
 #line 728
     goto unwind;
   } else {
 
   }
   }
   {
 #line 730
   flags = arch_local_irq_save();
 #line 730
   trace_hardirqs_off();
 #line 731
   __cil_tmp31 = dev_priv->mm.gtt_mapping;
 #line 731
   __cil_tmp32 = (unsigned long )reloc_offset;
 #line 731
   s = io_mapping_map_atomic_wc(__cil_tmp31, __cil_tmp32);
 #line 733
   __cil_tmp33 = (void const volatile   *)s;
 #line 733
   memcpy_fromio(d, __cil_tmp33, 4096UL);
 #line 734
   io_mapping_unmap_atomic(s);
 #line 735
   tmp___0 = arch_irqs_disabled_flags(flags);
   }
 #line 735
   if (tmp___0 != 0) {
     {
 #line 735
     arch_local_irq_restore(flags);
 #line 735
     trace_hardirqs_off();
     }
   } else {
     {
 #line 735
     trace_hardirqs_on();
 #line 735
     arch_local_irq_restore(flags);
     }
   }
 #line 737
   dst->pages[page] = (u32 *)d;
 #line 739
   reloc_offset = reloc_offset + 4096U;
 #line 721
   page = page + 1;
   ldv_37757: ;
 #line 721
   if (page < page_count___0) {
 #line 722
     goto ldv_37756;
   } else {
 #line 724
     goto ldv_37758;
   }
   ldv_37758: 
 #line 741
   dst->page_count = page_count___0;
 #line 742
   dst->gtt_offset = src->gtt_offset;
 #line 744
   return (dst);
   unwind: ;
 #line 747
   goto ldv_37760;
   ldv_37759: 
   {
 #line 748
   __cil_tmp34 = dst->pages[page];
 #line 748
   __cil_tmp35 = (void const   *)__cil_tmp34;
 #line 748
   kfree(__cil_tmp35);
   }
   ldv_37760: 
 #line 747
   tmp___1 = page;
 #line 747
   page = page - 1;
 #line 747
   if (tmp___1 != 0) {
 #line 748
     goto ldv_37759;
   } else {
 #line 750
     goto ldv_37761;
   }
   ldv_37761: 
   {
 #line 749
   __cil_tmp36 = (void const   *)dst;
 #line 749
   kfree(__cil_tmp36);
   }
 #line 750
   return ((struct drm_i915_error_object *)0);
 }
 }
 #line 754 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_error_object_free(struct drm_i915_error_object *obj ) 
 { int page ;
   struct drm_i915_error_object *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   u32 *__cil_tmp6 ;
   void const   *__cil_tmp7 ;
   int __cil_tmp8 ;
   void const   *__cil_tmp9 ;
 
   {
   {
 #line 758
   __cil_tmp3 = (struct drm_i915_error_object *)0;
 #line 758
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 758
   __cil_tmp5 = (unsigned long )obj;
 #line 758
   if (__cil_tmp5 == __cil_tmp4) {
 #line 759
     return;
   } else {
 
   }
   }
 #line 761
   page = 0;
 #line 761
   goto ldv_37767;
   ldv_37766: 
   {
 #line 762
   __cil_tmp6 = obj->pages[page];
 #line 762
   __cil_tmp7 = (void const   *)__cil_tmp6;
 #line 762
   kfree(__cil_tmp7);
 #line 761
   page = page + 1;
   }
   ldv_37767: ;
   {
 #line 761
   __cil_tmp8 = obj->page_count;
 #line 761
   if (__cil_tmp8 > page) {
 #line 762
     goto ldv_37766;
   } else {
 #line 764
     goto ldv_37768;
   }
   }
   ldv_37768: 
   {
 #line 764
   __cil_tmp9 = (void const   *)obj;
 #line 764
   kfree(__cil_tmp9);
   }
 #line 765
   return;
 }
 }
 #line 768 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_error_state_free(struct drm_device *dev , struct drm_i915_error_state *error ) 
 { int i ;
   struct drm_i915_error_object *__cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   struct drm_i915_error_object *__cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   struct drm_i915_error_buffer *__cil_tmp8 ;
   void const   *__cil_tmp9 ;
   struct intel_overlay_error_state *__cil_tmp10 ;
   void const   *__cil_tmp11 ;
   void const   *__cil_tmp12 ;
 
   {
 #line 773
   i = 0;
 #line 773
   goto ldv_37777;
   ldv_37776: 
   {
 #line 774
   __cil_tmp4 = error->batchbuffer[i];
 #line 774
   i915_error_object_free(__cil_tmp4);
 #line 773
   i = i + 1;
   }
   ldv_37777: ;
   {
 #line 773
   __cil_tmp5 = (unsigned int )i;
 #line 773
   if (__cil_tmp5 <= 2U) {
 #line 774
     goto ldv_37776;
   } else {
 #line 776
     goto ldv_37778;
   }
   }
   ldv_37778: 
 #line 776
   i = 0;
 #line 776
   goto ldv_37782;
   ldv_37781: 
   {
 #line 777
   __cil_tmp6 = error->ringbuffer[i];
 #line 777
   i915_error_object_free(__cil_tmp6);
 #line 776
   i = i + 1;
   }
   ldv_37782: ;
   {
 #line 776
   __cil_tmp7 = (unsigned int )i;
 #line 776
   if (__cil_tmp7 <= 2U) {
 #line 777
     goto ldv_37781;
   } else {
 #line 779
     goto ldv_37783;
   }
   }
   ldv_37783: 
   {
 #line 779
   __cil_tmp8 = error->active_bo;
 #line 779
   __cil_tmp9 = (void const   *)__cil_tmp8;
 #line 779
   kfree(__cil_tmp9);
 #line 780
   __cil_tmp10 = error->overlay;
 #line 780
   __cil_tmp11 = (void const   *)__cil_tmp10;
 #line 780
   kfree(__cil_tmp11);
 #line 781
   __cil_tmp12 = (void const   *)error;
 #line 781
   kfree(__cil_tmp12);
   }
 #line 782
   return;
 }
 }
 #line 784 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static u32 capture_bo_list(struct drm_i915_error_buffer *err , int count , struct list_head *head ) 
 { struct drm_i915_gem_object *obj ;
   int i ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head *__cil_tmp8 ;
   struct drm_i915_gem_object *__cil_tmp9 ;
   size_t __cil_tmp10 ;
   int __cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   int __cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   struct intel_ring_buffer *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct intel_ring_buffer *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct intel_ring_buffer *__cil_tmp24 ;
   enum intel_ring_id __cil_tmp25 ;
   struct list_head *__cil_tmp26 ;
   struct drm_i915_gem_object *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct list_head *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
 
   {
 #line 789
   i = 0;
 #line 791
   __cil_tmp8 = head->next;
 #line 791
   __mptr = (struct list_head  const  *)__cil_tmp8;
 #line 791
   __cil_tmp9 = (struct drm_i915_gem_object *)__mptr;
 #line 791
   obj = __cil_tmp9 + 1152921504606846800UL;
 #line 791
   goto ldv_37797;
   ldv_37796: 
 #line 792
   __cil_tmp10 = obj->base.size;
 #line 792
   err->size = (u32 )__cil_tmp10;
 #line 793
   __cil_tmp11 = obj->base.name;
 #line 793
   err->name = (u32 )__cil_tmp11;
 #line 794
   err->seqno = obj->last_rendering_seqno;
 #line 795
   err->gtt_offset = obj->gtt_offset;
 #line 796
   err->read_domains = obj->base.read_domains;
 #line 797
   err->write_domain = obj->base.write_domain;
 #line 798
   err->fence_reg = obj->fence_reg;
 #line 799
   err->pinned = (signed char)0;
   {
 #line 800
   __cil_tmp12 = obj->pin_count;
 #line 800
   __cil_tmp13 = (int )__cil_tmp12;
 #line 800
   if (__cil_tmp13 > 0) {
 #line 801
     err->pinned = (signed char)1;
   } else {
 
   }
   }
   {
 #line 802
   __cil_tmp14 = obj->user_pin_count;
 #line 802
   if (__cil_tmp14 != 0U) {
 #line 803
     err->pinned = (signed char)-1;
   } else {
 
   }
   }
 #line 804
   err->tiling = obj->tiling_mode;
 #line 805
   err->dirty = obj->dirty;
 #line 806
   __cil_tmp15 = (unsigned char *)obj;
 #line 806
   __cil_tmp16 = __cil_tmp15 + 225UL;
 #line 806
   __cil_tmp17 = *__cil_tmp16;
 #line 806
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 806
   __cil_tmp19 = __cil_tmp18 != 0U;
 #line 806
   err->purgeable = (unsigned char )__cil_tmp19;
   {
 #line 807
   __cil_tmp20 = (struct intel_ring_buffer *)0;
 #line 807
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 807
   __cil_tmp22 = obj->ring;
 #line 807
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 807
   if (__cil_tmp23 != __cil_tmp21) {
 #line 807
     __cil_tmp24 = obj->ring;
 #line 807
     __cil_tmp25 = __cil_tmp24->id;
 #line 807
     err->ring = (unsigned char )__cil_tmp25;
   } else {
 #line 807
     err->ring = (unsigned char)0;
   }
   }
 #line 808
   err->cache_level = obj->cache_level;
 #line 810
   i = i + 1;
 #line 810
   if (i == count) {
 #line 811
     goto ldv_37795;
   } else {
 
   }
 #line 813
   err = err + 1;
 #line 791
   __cil_tmp26 = obj->mm_list.next;
 #line 791
   __mptr___0 = (struct list_head  const  *)__cil_tmp26;
 #line 791
   __cil_tmp27 = (struct drm_i915_gem_object *)__mptr___0;
 #line 791
   obj = __cil_tmp27 + 1152921504606846800UL;
   ldv_37797: ;
   {
 #line 791
   __cil_tmp28 = (unsigned long )head;
 #line 791
   __cil_tmp29 = & obj->mm_list;
 #line 791
   __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 791
   if (__cil_tmp30 != __cil_tmp28) {
 #line 792
     goto ldv_37796;
   } else {
 #line 794
     goto ldv_37795;
   }
   }
   ldv_37795: ;
 #line 816
   return ((u32 )i);
 }
 }
 #line 819 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_gem_record_fences(struct drm_device *dev , struct drm_i915_error_state *error ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   u32 tmp ;
   u32 tmp___0 ;
   void *__cil_tmp7 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   u8 __cil_tmp11 ;
   int __cil_tmp12 ;
   void *__cil_tmp13 ;
   struct drm_i915_private *__cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   u8 __cil_tmp16 ;
   int __cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   u8 __cil_tmp21 ;
   int __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   u8 __cil_tmp26 ;
   int __cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   u32 __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   int __cil_tmp39 ;
   void *__cil_tmp40 ;
   struct drm_i915_private *__cil_tmp41 ;
   struct intel_device_info  const  *__cil_tmp42 ;
   unsigned char *__cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   void *__cil_tmp47 ;
   struct drm_i915_private *__cil_tmp48 ;
   struct intel_device_info  const  *__cil_tmp49 ;
   unsigned char *__cil_tmp50 ;
   unsigned char *__cil_tmp51 ;
   unsigned char __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   u32 __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   u32 __cil_tmp59 ;
 
   {
 #line 822
   __cil_tmp7 = dev->dev_private;
 #line 822
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
   {
 #line 827
   __cil_tmp8 = dev->dev_private;
 #line 827
   __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 827
   __cil_tmp10 = __cil_tmp9->info;
 #line 827
   __cil_tmp11 = __cil_tmp10->gen;
 #line 827
   __cil_tmp12 = (int )__cil_tmp11;
 #line 827
   if (__cil_tmp12 == 6) {
 #line 827
     goto case_6;
   } else {
     {
 #line 831
     __cil_tmp13 = dev->dev_private;
 #line 831
     __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
 #line 831
     __cil_tmp15 = __cil_tmp14->info;
 #line 831
     __cil_tmp16 = __cil_tmp15->gen;
 #line 831
     __cil_tmp17 = (int )__cil_tmp16;
 #line 831
     if (__cil_tmp17 == 5) {
 #line 831
       goto case_5;
     } else {
       {
 #line 832
       __cil_tmp18 = dev->dev_private;
 #line 832
       __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 832
       __cil_tmp20 = __cil_tmp19->info;
 #line 832
       __cil_tmp21 = __cil_tmp20->gen;
 #line 832
       __cil_tmp22 = (int )__cil_tmp21;
 #line 832
       if (__cil_tmp22 == 4) {
 #line 832
         goto case_4;
       } else {
         {
 #line 836
         __cil_tmp23 = dev->dev_private;
 #line 836
         __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 836
         __cil_tmp25 = __cil_tmp24->info;
 #line 836
         __cil_tmp26 = __cil_tmp25->gen;
 #line 836
         __cil_tmp27 = (int )__cil_tmp26;
 #line 836
         if (__cil_tmp27 == 3) {
 #line 836
           goto case_3;
         } else {
           {
 #line 840
           __cil_tmp28 = dev->dev_private;
 #line 840
           __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 840
           __cil_tmp30 = __cil_tmp29->info;
 #line 840
           __cil_tmp31 = __cil_tmp30->gen;
 #line 840
           __cil_tmp32 = (int )__cil_tmp31;
 #line 840
           if (__cil_tmp32 == 2) {
 #line 840
             goto case_2;
           } else
 #line 826
           if (0) {
             case_6: 
 #line 828
             i = 0;
 #line 828
             goto ldv_37806;
             ldv_37805: 
             {
 #line 829
             __cil_tmp33 = i + 131072;
 #line 829
             __cil_tmp34 = __cil_tmp33 * 8;
 #line 829
             __cil_tmp35 = (u32 )__cil_tmp34;
 #line 829
             error->fence[i] = i915_read64(dev_priv, __cil_tmp35);
 #line 828
             i = i + 1;
             }
             ldv_37806: ;
 #line 828
             if (i <= 15) {
 #line 829
               goto ldv_37805;
             } else {
 #line 831
               goto ldv_37807;
             }
             ldv_37807: ;
 #line 830
             goto ldv_37808;
             case_5: ;
             case_4: 
 #line 833
             i = 0;
 #line 833
             goto ldv_37812;
             ldv_37811: 
             {
 #line 834
             __cil_tmp36 = i + 1536;
 #line 834
             __cil_tmp37 = __cil_tmp36 * 8;
 #line 834
             __cil_tmp38 = (u32 )__cil_tmp37;
 #line 834
             error->fence[i] = i915_read64(dev_priv, __cil_tmp38);
 #line 833
             i = i + 1;
             }
             ldv_37812: ;
 #line 833
             if (i <= 15) {
 #line 834
               goto ldv_37811;
             } else {
 #line 836
               goto ldv_37813;
             }
             ldv_37813: ;
 #line 835
             goto ldv_37808;
             case_3: ;
             {
 #line 837
             __cil_tmp39 = dev->pci_device;
 #line 837
             if (__cil_tmp39 == 10098) {
 #line 837
               goto _L;
             } else {
               {
 #line 837
               __cil_tmp40 = dev->dev_private;
 #line 837
               __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
 #line 837
               __cil_tmp42 = __cil_tmp41->info;
 #line 837
               __cil_tmp43 = (unsigned char *)__cil_tmp42;
 #line 837
               __cil_tmp44 = __cil_tmp43 + 1UL;
 #line 837
               __cil_tmp45 = *__cil_tmp44;
 #line 837
               __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 837
               if (__cil_tmp46 != 0U) {
 #line 837
                 goto _L;
               } else {
                 {
 #line 837
                 __cil_tmp47 = dev->dev_private;
 #line 837
                 __cil_tmp48 = (struct drm_i915_private *)__cil_tmp47;
 #line 837
                 __cil_tmp49 = __cil_tmp48->info;
 #line 837
                 __cil_tmp50 = (unsigned char *)__cil_tmp49;
 #line 837
                 __cil_tmp51 = __cil_tmp50 + 1UL;
 #line 837
                 __cil_tmp52 = *__cil_tmp51;
 #line 837
                 __cil_tmp53 = (unsigned int )__cil_tmp52;
 #line 837
                 if (__cil_tmp53 != 0U) {
                   _L: 
 #line 838
                   i = 0;
 #line 838
                   goto ldv_37816;
                   ldv_37815: 
                   {
 #line 839
                   __cil_tmp54 = i + 3072;
 #line 839
                   __cil_tmp55 = __cil_tmp54 * 4;
 #line 839
                   __cil_tmp56 = (u32 )__cil_tmp55;
 #line 839
                   tmp = i915_read32(dev_priv, __cil_tmp56);
 #line 839
                   error->fence[i + 8] = (u64 )tmp;
 #line 838
                   i = i + 1;
                   }
                   ldv_37816: ;
 #line 838
                   if (i <= 7) {
 #line 839
                     goto ldv_37815;
                   } else {
 #line 841
                     goto ldv_37817;
                   }
                   ldv_37817: ;
                 } else {
 
                 }
                 }
               }
               }
             }
             }
             case_2: 
 #line 841
             i = 0;
 #line 841
             goto ldv_37820;
             ldv_37819: 
             {
 #line 842
             __cil_tmp57 = i + 2048;
 #line 842
             __cil_tmp58 = __cil_tmp57 * 4;
 #line 842
             __cil_tmp59 = (u32 )__cil_tmp58;
 #line 842
             tmp___0 = i915_read32(dev_priv, __cil_tmp59);
 #line 842
             error->fence[i] = (u64 )tmp___0;
 #line 841
             i = i + 1;
             }
             ldv_37820: ;
 #line 841
             if (i <= 7) {
 #line 842
               goto ldv_37819;
             } else {
 #line 844
               goto ldv_37821;
             }
             ldv_37821: ;
 #line 843
             goto ldv_37808;
           } else {
 
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_37808: ;
 #line 847
   return;
 }
 }
 #line 849 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static struct drm_i915_error_object *i915_error_first_batchbuffer(struct drm_i915_private *dev_priv ,
                                                                   struct intel_ring_buffer *ring ) 
 { struct drm_i915_gem_object *obj ;
   u32 seqno ;
   struct list_head  const  *__mptr ;
   bool tmp ;
   struct drm_i915_error_object *tmp___0 ;
   struct list_head  const  *__mptr___0 ;
   u32 (*__cil_tmp9)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp10 ;
   u32 (*__cil_tmp11)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp12 ;
   u32 (*__cil_tmp13)(struct intel_ring_buffer * ) ;
   struct list_head *__cil_tmp14 ;
   struct drm_i915_gem_object *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct intel_ring_buffer *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   uint32_t __cil_tmp19 ;
   uint32_t __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct drm_i915_gem_object *__cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct list_head *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
 
   {
   {
 #line 855
   __cil_tmp9 = (u32 (*)(struct intel_ring_buffer * ))0;
 #line 855
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 855
   __cil_tmp11 = ring->get_seqno;
 #line 855
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 855
   if (__cil_tmp12 == __cil_tmp10) {
 #line 856
     return ((struct drm_i915_error_object *)0);
   } else {
 
   }
   }
   {
 #line 858
   __cil_tmp13 = ring->get_seqno;
 #line 858
   seqno = (*__cil_tmp13)(ring);
 #line 859
   __cil_tmp14 = dev_priv->mm.active_list.next;
 #line 859
   __mptr = (struct list_head  const  *)__cil_tmp14;
 #line 859
   __cil_tmp15 = (struct drm_i915_gem_object *)__mptr;
 #line 859
   obj = __cil_tmp15 + 1152921504606846800UL;
   }
 #line 859
   goto ldv_37834;
   ldv_37833: ;
   {
 #line 860
   __cil_tmp16 = (unsigned long )ring;
 #line 860
   __cil_tmp17 = obj->ring;
 #line 860
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 860
   if (__cil_tmp18 != __cil_tmp16) {
 #line 861
     goto ldv_37832;
   } else {
 
   }
   }
   {
 #line 863
   __cil_tmp19 = obj->last_rendering_seqno;
 #line 863
   tmp = i915_seqno_passed(seqno, __cil_tmp19);
   }
 #line 863
   if ((int )tmp) {
 #line 864
     goto ldv_37832;
   } else {
 
   }
   {
 #line 866
   __cil_tmp20 = obj->base.read_domains;
 #line 866
   __cil_tmp21 = __cil_tmp20 & 8U;
 #line 866
   if (__cil_tmp21 == 0U) {
 #line 867
     goto ldv_37832;
   } else {
 
   }
   }
   {
 #line 872
   tmp___0 = i915_error_object_create(dev_priv, obj);
   }
 #line 872
   return (tmp___0);
   ldv_37832: 
 #line 859
   __cil_tmp22 = obj->mm_list.next;
 #line 859
   __mptr___0 = (struct list_head  const  *)__cil_tmp22;
 #line 859
   __cil_tmp23 = (struct drm_i915_gem_object *)__mptr___0;
 #line 859
   obj = __cil_tmp23 + 1152921504606846800UL;
   ldv_37834: ;
   {
 #line 859
   __cil_tmp24 = & dev_priv->mm.active_list;
 #line 859
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 859
   __cil_tmp26 = & obj->mm_list;
 #line 859
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 859
   if (__cil_tmp27 != __cil_tmp25) {
 #line 860
     goto ldv_37833;
   } else {
 #line 862
     goto ldv_37835;
   }
   }
   ldv_37835: ;
 #line 875
   return ((struct drm_i915_error_object *)0);
 }
 }
 #line 887 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_capture_error_state(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   struct drm_i915_error_state *error ;
   unsigned long flags ;
   int i ;
   int pipe ;
   raw_spinlock_t *tmp ;
   void *tmp___0 ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   struct list_head  const  *__mptr___2 ;
   void *tmp___1 ;
   raw_spinlock_t *tmp___2 ;
   void *__cil_tmp16 ;
   spinlock_t *__cil_tmp17 ;
   spinlock_t *__cil_tmp18 ;
   struct drm_i915_error_state *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct drm_i915_error_state *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct drm_minor *__cil_tmp25 ;
   int __cil_tmp26 ;
   u32 (*__cil_tmp27)(struct intel_ring_buffer * ) ;
   struct intel_ring_buffer (*__cil_tmp28)[3U] ;
   struct intel_ring_buffer *__cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   u32 __cil_tmp32 ;
   int __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   u8 __cil_tmp37 ;
   unsigned char __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   u32 (*__cil_tmp40)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp41 ;
   u32 (*__cil_tmp42)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp43 ;
   u32 (*__cil_tmp44)(struct intel_ring_buffer * ) ;
   struct intel_ring_buffer (*__cil_tmp45)[3U] ;
   struct intel_ring_buffer *__cil_tmp46 ;
   struct intel_ring_buffer *__cil_tmp47 ;
   u32 (*__cil_tmp48)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp49 ;
   u32 (*__cil_tmp50)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp51 ;
   u32 (*__cil_tmp52)(struct intel_ring_buffer * ) ;
   struct intel_ring_buffer (*__cil_tmp53)[3U] ;
   struct intel_ring_buffer *__cil_tmp54 ;
   struct intel_ring_buffer *__cil_tmp55 ;
   void *__cil_tmp56 ;
   struct drm_i915_private *__cil_tmp57 ;
   struct intel_device_info  const  *__cil_tmp58 ;
   u8 __cil_tmp59 ;
   unsigned char __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   struct intel_ring_buffer (*__cil_tmp63)[3U] ;
   struct intel_ring_buffer *__cil_tmp64 ;
   struct intel_ring_buffer *__cil_tmp65 ;
   struct drm_i915_gem_object *__cil_tmp66 ;
   struct list_head *__cil_tmp67 ;
   struct drm_i915_gem_object *__cil_tmp68 ;
   struct list_head *__cil_tmp69 ;
   struct drm_i915_gem_object *__cil_tmp70 ;
   struct list_head *__cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   struct list_head *__cil_tmp73 ;
   unsigned long __cil_tmp74 ;
   struct list_head *__cil_tmp75 ;
   struct drm_i915_gem_object *__cil_tmp76 ;
   struct list_head *__cil_tmp77 ;
   struct drm_i915_gem_object *__cil_tmp78 ;
   struct list_head *__cil_tmp79 ;
   unsigned long __cil_tmp80 ;
   struct list_head *__cil_tmp81 ;
   unsigned long __cil_tmp82 ;
   u32 __cil_tmp83 ;
   u32 __cil_tmp84 ;
   unsigned long __cil_tmp85 ;
   unsigned long __cil_tmp86 ;
   struct drm_i915_error_buffer *__cil_tmp87 ;
   unsigned long __cil_tmp88 ;
   struct drm_i915_error_buffer *__cil_tmp89 ;
   unsigned long __cil_tmp90 ;
   u32 __cil_tmp91 ;
   unsigned long __cil_tmp92 ;
   struct drm_i915_error_buffer *__cil_tmp93 ;
   struct drm_i915_error_buffer *__cil_tmp94 ;
   unsigned long __cil_tmp95 ;
   struct drm_i915_error_buffer *__cil_tmp96 ;
   unsigned long __cil_tmp97 ;
   struct drm_i915_error_buffer *__cil_tmp98 ;
   u32 __cil_tmp99 ;
   int __cil_tmp100 ;
   struct list_head *__cil_tmp101 ;
   struct drm_i915_error_buffer *__cil_tmp102 ;
   unsigned long __cil_tmp103 ;
   struct drm_i915_error_buffer *__cil_tmp104 ;
   unsigned long __cil_tmp105 ;
   struct drm_i915_error_buffer *__cil_tmp106 ;
   u32 __cil_tmp107 ;
   int __cil_tmp108 ;
   struct list_head *__cil_tmp109 ;
   struct timeval *__cil_tmp110 ;
   spinlock_t *__cil_tmp111 ;
   struct drm_i915_error_state *__cil_tmp112 ;
   unsigned long __cil_tmp113 ;
   struct drm_i915_error_state *__cil_tmp114 ;
   unsigned long __cil_tmp115 ;
   spinlock_t *__cil_tmp116 ;
   struct drm_i915_error_state *__cil_tmp117 ;
   unsigned long __cil_tmp118 ;
   unsigned long __cil_tmp119 ;
 
   {
   {
 #line 889
   __cil_tmp16 = dev->dev_private;
 #line 889
   dev_priv = (struct drm_i915_private *)__cil_tmp16;
 #line 895
   __cil_tmp17 = & dev_priv->error_lock;
 #line 895
   tmp = spinlock_check(__cil_tmp17);
 #line 895
   flags = _raw_spin_lock_irqsave(tmp);
 #line 896
   error = dev_priv->first_error;
 #line 897
   __cil_tmp18 = & dev_priv->error_lock;
 #line 897
   spin_unlock_irqrestore(__cil_tmp18, flags);
   }
   {
 #line 898
   __cil_tmp19 = (struct drm_i915_error_state *)0;
 #line 898
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 898
   __cil_tmp21 = (unsigned long )error;
 #line 898
   if (__cil_tmp21 != __cil_tmp20) {
 #line 899
     return;
   } else {
 
   }
   }
   {
 #line 902
   tmp___0 = kmalloc(336UL, 32U);
 #line 902
   error = (struct drm_i915_error_state *)tmp___0;
   }
   {
 #line 903
   __cil_tmp22 = (struct drm_i915_error_state *)0;
 #line 903
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 903
   __cil_tmp24 = (unsigned long )error;
 #line 903
   if (__cil_tmp24 == __cil_tmp23) {
     {
 #line 904
     drm_ut_debug_printk(2U, "drm", "i915_capture_error_state", "out of memory, not capturing error state\n");
     }
 #line 905
     return;
   } else {
 
   }
   }
   {
 #line 908
   __cil_tmp25 = dev->primary;
 #line 908
   __cil_tmp26 = __cil_tmp25->index;
 #line 908
   printk("<6>[drm] capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
          __cil_tmp26);
 #line 911
   __cil_tmp27 = dev_priv->ring[0].get_seqno;
 #line 911
   __cil_tmp28 = & dev_priv->ring;
 #line 911
   __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
 #line 911
   error->seqno = (*__cil_tmp27)(__cil_tmp29);
 #line 912
   error->eir = i915_read32(dev_priv, 8368U);
 #line 913
   error->pgtbl_er = i915_read32(dev_priv, 8228U);
 #line 914
   pipe = 0;
   }
 #line 914
   goto ldv_37850;
   ldv_37849: 
   {
 #line 915
   __cil_tmp30 = pipe * 4096;
 #line 915
   __cil_tmp31 = __cil_tmp30 + 458788;
 #line 915
   __cil_tmp32 = (u32 )__cil_tmp31;
 #line 915
   error->pipestat[pipe] = i915_read32(dev_priv, __cil_tmp32);
 #line 914
   pipe = pipe + 1;
   }
   ldv_37850: ;
   {
 #line 914
   __cil_tmp33 = dev_priv->num_pipe;
 #line 914
   if (__cil_tmp33 > pipe) {
 #line 915
     goto ldv_37849;
   } else {
 #line 917
     goto ldv_37851;
   }
   }
   ldv_37851: 
   {
 #line 916
   error->instpm = i915_read32(dev_priv, 8384U);
 #line 917
   error->error = 0U;
   }
   {
 #line 918
   __cil_tmp34 = dev->dev_private;
 #line 918
   __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 918
   __cil_tmp36 = __cil_tmp35->info;
 #line 918
   __cil_tmp37 = __cil_tmp36->gen;
 #line 918
   __cil_tmp38 = (unsigned char )__cil_tmp37;
 #line 918
   __cil_tmp39 = (unsigned int )__cil_tmp38;
 #line 918
   if (__cil_tmp39 > 5U) {
     {
 #line 919
     error->error = i915_read32(dev_priv, 16544U);
 #line 921
     error->bcs_acthd = i915_read32(dev_priv, 139380U);
 #line 922
     error->bcs_ipehr = i915_read32(dev_priv, 139368U);
 #line 923
     error->bcs_ipeir = i915_read32(dev_priv, 139364U);
 #line 924
     error->bcs_instdone = i915_read32(dev_priv, 139372U);
 #line 925
     error->bcs_seqno = 0U;
     }
     {
 #line 926
     __cil_tmp40 = (u32 (*)(struct intel_ring_buffer * ))0;
 #line 926
     __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 926
     __cil_tmp42 = dev_priv->ring[2].get_seqno;
 #line 926
     __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 926
     if (__cil_tmp43 != __cil_tmp41) {
       {
 #line 927
       __cil_tmp44 = dev_priv->ring[2].get_seqno;
 #line 927
       __cil_tmp45 = & dev_priv->ring;
 #line 927
       __cil_tmp46 = (struct intel_ring_buffer *)__cil_tmp45;
 #line 927
       __cil_tmp47 = __cil_tmp46 + 2UL;
 #line 927
       error->bcs_seqno = (*__cil_tmp44)(__cil_tmp47);
       }
     } else {
 
     }
     }
     {
 #line 929
     error->vcs_acthd = i915_read32(dev_priv, 73844U);
 #line 930
     error->vcs_ipehr = i915_read32(dev_priv, 73832U);
 #line 931
     error->vcs_ipeir = i915_read32(dev_priv, 73828U);
 #line 932
     error->vcs_instdone = i915_read32(dev_priv, 73836U);
 #line 933
     error->vcs_seqno = 0U;
     }
     {
 #line 934
     __cil_tmp48 = (u32 (*)(struct intel_ring_buffer * ))0;
 #line 934
     __cil_tmp49 = (unsigned long )__cil_tmp48;
 #line 934
     __cil_tmp50 = dev_priv->ring[1].get_seqno;
 #line 934
     __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 934
     if (__cil_tmp51 != __cil_tmp49) {
       {
 #line 935
       __cil_tmp52 = dev_priv->ring[1].get_seqno;
 #line 935
       __cil_tmp53 = & dev_priv->ring;
 #line 935
       __cil_tmp54 = (struct intel_ring_buffer *)__cil_tmp53;
 #line 935
       __cil_tmp55 = __cil_tmp54 + 1UL;
 #line 935
       error->vcs_seqno = (*__cil_tmp52)(__cil_tmp55);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 937
   __cil_tmp56 = dev->dev_private;
 #line 937
   __cil_tmp57 = (struct drm_i915_private *)__cil_tmp56;
 #line 937
   __cil_tmp58 = __cil_tmp57->info;
 #line 937
   __cil_tmp59 = __cil_tmp58->gen;
 #line 937
   __cil_tmp60 = (unsigned char )__cil_tmp59;
 #line 937
   __cil_tmp61 = (unsigned int )__cil_tmp60;
 #line 937
   if (__cil_tmp61 > 3U) {
     {
 #line 938
     error->ipeir = i915_read32(dev_priv, 8292U);
 #line 939
     error->ipehr = i915_read32(dev_priv, 8296U);
 #line 940
     error->instdone = i915_read32(dev_priv, 8300U);
 #line 941
     error->instps = i915_read32(dev_priv, 8304U);
 #line 942
     error->instdone1 = i915_read32(dev_priv, 8316U);
 #line 943
     error->acthd = i915_read32(dev_priv, 8308U);
 #line 944
     error->bbaddr = i915_read64(dev_priv, 8512U);
     }
   } else {
     {
 #line 946
     error->ipeir = i915_read32(dev_priv, 8328U);
 #line 947
     error->ipehr = i915_read32(dev_priv, 8332U);
 #line 948
     error->instdone = i915_read32(dev_priv, 8336U);
 #line 949
     error->acthd = i915_read32(dev_priv, 8392U);
 #line 950
     error->bbaddr = 0ULL;
     }
   }
   }
   {
 #line 952
   i915_gem_record_fences(dev, error);
 #line 955
   i = 0;
   }
 #line 955
   goto ldv_37853;
   ldv_37852: 
   {
 #line 956
   __cil_tmp62 = (unsigned long )i;
 #line 956
   __cil_tmp63 = & dev_priv->ring;
 #line 956
   __cil_tmp64 = (struct intel_ring_buffer *)__cil_tmp63;
 #line 956
   __cil_tmp65 = __cil_tmp64 + __cil_tmp62;
 #line 956
   error->batchbuffer[i] = i915_error_first_batchbuffer(dev_priv, __cil_tmp65);
 #line 960
   __cil_tmp66 = dev_priv->ring[i].obj;
 #line 960
   error->ringbuffer[i] = i915_error_object_create(dev_priv, __cil_tmp66);
 #line 955
   i = i + 1;
   }
   ldv_37853: ;
 #line 955
   if (i <= 2) {
 #line 956
     goto ldv_37852;
   } else {
 #line 958
     goto ldv_37854;
   }
   ldv_37854: 
 #line 966
   error->active_bo = (struct drm_i915_error_buffer *)0;
 #line 967
   error->pinned_bo = (struct drm_i915_error_buffer *)0;
 #line 969
   i = 0;
 #line 970
   __cil_tmp67 = dev_priv->mm.active_list.next;
 #line 970
   __mptr = (struct list_head  const  *)__cil_tmp67;
 #line 970
   __cil_tmp68 = (struct drm_i915_gem_object *)__mptr;
 #line 970
   obj = __cil_tmp68 + 1152921504606846800UL;
 #line 970
   goto ldv_37860;
   ldv_37859: 
 #line 971
   i = i + 1;
 #line 970
   __cil_tmp69 = obj->mm_list.next;
 #line 970
   __mptr___0 = (struct list_head  const  *)__cil_tmp69;
 #line 970
   __cil_tmp70 = (struct drm_i915_gem_object *)__mptr___0;
 #line 970
   obj = __cil_tmp70 + 1152921504606846800UL;
   ldv_37860: ;
   {
 #line 970
   __cil_tmp71 = & dev_priv->mm.active_list;
 #line 970
   __cil_tmp72 = (unsigned long )__cil_tmp71;
 #line 970
   __cil_tmp73 = & obj->mm_list;
 #line 970
   __cil_tmp74 = (unsigned long )__cil_tmp73;
 #line 970
   if (__cil_tmp74 != __cil_tmp72) {
 #line 971
     goto ldv_37859;
   } else {
 #line 973
     goto ldv_37861;
   }
   }
   ldv_37861: 
 #line 972
   error->active_bo_count = (u32 )i;
 #line 973
   __cil_tmp75 = dev_priv->mm.pinned_list.next;
 #line 973
   __mptr___1 = (struct list_head  const  *)__cil_tmp75;
 #line 973
   __cil_tmp76 = (struct drm_i915_gem_object *)__mptr___1;
 #line 973
   obj = __cil_tmp76 + 1152921504606846800UL;
 #line 973
   goto ldv_37867;
   ldv_37866: 
 #line 974
   i = i + 1;
 #line 973
   __cil_tmp77 = obj->mm_list.next;
 #line 973
   __mptr___2 = (struct list_head  const  *)__cil_tmp77;
 #line 973
   __cil_tmp78 = (struct drm_i915_gem_object *)__mptr___2;
 #line 973
   obj = __cil_tmp78 + 1152921504606846800UL;
   ldv_37867: ;
   {
 #line 973
   __cil_tmp79 = & dev_priv->mm.pinned_list;
 #line 973
   __cil_tmp80 = (unsigned long )__cil_tmp79;
 #line 973
   __cil_tmp81 = & obj->mm_list;
 #line 973
   __cil_tmp82 = (unsigned long )__cil_tmp81;
 #line 973
   if (__cil_tmp82 != __cil_tmp80) {
 #line 974
     goto ldv_37866;
   } else {
 #line 976
     goto ldv_37868;
   }
   }
   ldv_37868: 
 #line 975
   __cil_tmp83 = error->active_bo_count;
 #line 975
   __cil_tmp84 = (u32 )i;
 #line 975
   error->pinned_bo_count = __cil_tmp84 - __cil_tmp83;
 #line 977
   error->active_bo = (struct drm_i915_error_buffer *)0;
 #line 978
   error->pinned_bo = (struct drm_i915_error_buffer *)0;
 #line 979
   if (i != 0) {
     {
 #line 980
     __cil_tmp85 = (unsigned long )i;
 #line 980
     __cil_tmp86 = __cil_tmp85 * 28UL;
 #line 980
     tmp___1 = kmalloc(__cil_tmp86, 32U);
 #line 980
     error->active_bo = (struct drm_i915_error_buffer *)tmp___1;
     }
     {
 #line 982
     __cil_tmp87 = (struct drm_i915_error_buffer *)0;
 #line 982
     __cil_tmp88 = (unsigned long )__cil_tmp87;
 #line 982
     __cil_tmp89 = error->active_bo;
 #line 982
     __cil_tmp90 = (unsigned long )__cil_tmp89;
 #line 982
     if (__cil_tmp90 != __cil_tmp88) {
 #line 983
       __cil_tmp91 = error->active_bo_count;
 #line 983
       __cil_tmp92 = (unsigned long )__cil_tmp91;
 #line 983
       __cil_tmp93 = error->active_bo;
 #line 983
       error->pinned_bo = __cil_tmp93 + __cil_tmp92;
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 987
   __cil_tmp94 = (struct drm_i915_error_buffer *)0;
 #line 987
   __cil_tmp95 = (unsigned long )__cil_tmp94;
 #line 987
   __cil_tmp96 = error->active_bo;
 #line 987
   __cil_tmp97 = (unsigned long )__cil_tmp96;
 #line 987
   if (__cil_tmp97 != __cil_tmp95) {
     {
 #line 988
     __cil_tmp98 = error->active_bo;
 #line 988
     __cil_tmp99 = error->active_bo_count;
 #line 988
     __cil_tmp100 = (int )__cil_tmp99;
 #line 988
     __cil_tmp101 = & dev_priv->mm.active_list;
 #line 988
     error->active_bo_count = capture_bo_list(__cil_tmp98, __cil_tmp100, __cil_tmp101);
     }
   } else {
 
   }
   }
   {
 #line 993
   __cil_tmp102 = (struct drm_i915_error_buffer *)0;
 #line 993
   __cil_tmp103 = (unsigned long )__cil_tmp102;
 #line 993
   __cil_tmp104 = error->pinned_bo;
 #line 993
   __cil_tmp105 = (unsigned long )__cil_tmp104;
 #line 993
   if (__cil_tmp105 != __cil_tmp103) {
     {
 #line 994
     __cil_tmp106 = error->pinned_bo;
 #line 994
     __cil_tmp107 = error->pinned_bo_count;
 #line 994
     __cil_tmp108 = (int )__cil_tmp107;
 #line 994
     __cil_tmp109 = & dev_priv->mm.pinned_list;
 #line 994
     error->pinned_bo_count = capture_bo_list(__cil_tmp106, __cil_tmp108, __cil_tmp109);
     }
   } else {
 
   }
   }
   {
 #line 999
   __cil_tmp110 = & error->time;
 #line 999
   do_gettimeofday(__cil_tmp110);
 #line 1001
   error->overlay = intel_overlay_capture_error_state(dev);
 #line 1002
   error->display = intel_display_capture_error_state(dev);
 #line 1004
   __cil_tmp111 = & dev_priv->error_lock;
 #line 1004
   tmp___2 = spinlock_check(__cil_tmp111);
 #line 1004
   flags = _raw_spin_lock_irqsave(tmp___2);
   }
   {
 #line 1005
   __cil_tmp112 = (struct drm_i915_error_state *)0;
 #line 1005
   __cil_tmp113 = (unsigned long )__cil_tmp112;
 #line 1005
   __cil_tmp114 = dev_priv->first_error;
 #line 1005
   __cil_tmp115 = (unsigned long )__cil_tmp114;
 #line 1005
   if (__cil_tmp115 == __cil_tmp113) {
 #line 1006
     dev_priv->first_error = error;
 #line 1007
     error = (struct drm_i915_error_state *)0;
   } else {
 
   }
   }
   {
 #line 1009
   __cil_tmp116 = & dev_priv->error_lock;
 #line 1009
   spin_unlock_irqrestore(__cil_tmp116, flags);
   }
   {
 #line 1011
   __cil_tmp117 = (struct drm_i915_error_state *)0;
 #line 1011
   __cil_tmp118 = (unsigned long )__cil_tmp117;
 #line 1011
   __cil_tmp119 = (unsigned long )error;
 #line 1011
   if (__cil_tmp119 != __cil_tmp118) {
     {
 #line 1012
     i915_error_state_free(dev, error);
     }
   } else {
 
   }
   }
 #line 1013
   return;
 }
 }
 #line 1015 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void i915_destroy_error_state(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_error_state *error ;
   void *__cil_tmp4 ;
   spinlock_t *__cil_tmp5 ;
   spinlock_t *__cil_tmp6 ;
   struct drm_i915_error_state *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
 
   {
   {
 #line 1017
   __cil_tmp4 = dev->dev_private;
 #line 1017
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1020
   __cil_tmp5 = & dev_priv->error_lock;
 #line 1020
   spin_lock(__cil_tmp5);
 #line 1021
   error = dev_priv->first_error;
 #line 1022
   dev_priv->first_error = (struct drm_i915_error_state *)0;
 #line 1023
   __cil_tmp6 = & dev_priv->error_lock;
 #line 1023
   spin_unlock(__cil_tmp6);
   }
   {
 #line 1025
   __cil_tmp7 = (struct drm_i915_error_state *)0;
 #line 1025
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 1025
   __cil_tmp9 = (unsigned long )error;
 #line 1025
   if (__cil_tmp9 != __cil_tmp8) {
     {
 #line 1026
     i915_error_state_free(dev, error);
     }
   } else {
 
   }
   }
 #line 1027
   return;
 }
 }
 #line 1032 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_report_and_clear_eir(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 eir ;
   u32 tmp ;
   int pipe ;
   u32 ipeir ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   u32 tmp___3 ;
   u32 tmp___4 ;
   u32 tmp___5 ;
   u32 tmp___6 ;
   u32 pgtbl_err ;
   u32 tmp___7 ;
   u32 pgtbl_err___0 ;
   u32 tmp___8 ;
   u32 tmp___9 ;
   u32 tmp___10 ;
   u32 ipeir___0 ;
   u32 tmp___11 ;
   u32 tmp___12 ;
   u32 tmp___13 ;
   u32 tmp___14 ;
   u32 tmp___15 ;
   u32 ipeir___1 ;
   u32 tmp___16 ;
   u32 tmp___17 ;
   u32 tmp___18 ;
   u32 tmp___19 ;
   u32 tmp___20 ;
   u32 tmp___21 ;
   u32 tmp___22 ;
   u32 tmp___23 ;
   void *__cil_tmp35 ;
   void *__cil_tmp36 ;
   struct drm_i915_private *__cil_tmp37 ;
   struct intel_device_info  const  *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char *__cil_tmp40 ;
   unsigned char __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   void *__cil_tmp44 ;
   void const volatile   *__cil_tmp45 ;
   void const volatile   *__cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   void *__cil_tmp48 ;
   void const volatile   *__cil_tmp49 ;
   void const volatile   *__cil_tmp50 ;
   void *__cil_tmp51 ;
   struct drm_i915_private *__cil_tmp52 ;
   struct intel_device_info  const  *__cil_tmp53 ;
   u8 __cil_tmp54 ;
   unsigned char __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   void *__cil_tmp58 ;
   void const volatile   *__cil_tmp59 ;
   void const volatile   *__cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   int __cil_tmp62 ;
   int __cil_tmp63 ;
   u32 __cil_tmp64 ;
   int __cil_tmp65 ;
   int __cil_tmp66 ;
   int __cil_tmp67 ;
   void *__cil_tmp68 ;
   struct drm_i915_private *__cil_tmp69 ;
   struct intel_device_info  const  *__cil_tmp70 ;
   u8 __cil_tmp71 ;
   unsigned char __cil_tmp72 ;
   unsigned int __cil_tmp73 ;
   void *__cil_tmp74 ;
   void const volatile   *__cil_tmp75 ;
   void const volatile   *__cil_tmp76 ;
   void *__cil_tmp77 ;
   void const volatile   *__cil_tmp78 ;
   void const volatile   *__cil_tmp79 ;
   void *__cil_tmp80 ;
   void const volatile   *__cil_tmp81 ;
   void const volatile   *__cil_tmp82 ;
   unsigned int __cil_tmp83 ;
 
   {
   {
 #line 1034
   __cil_tmp35 = dev->dev_private;
 #line 1034
   dev_priv = (struct drm_i915_private *)__cil_tmp35;
 #line 1035
   tmp = i915_read32(dev_priv, 8368U);
 #line 1035
   eir = tmp;
   }
 #line 1038
   if (eir == 0U) {
 #line 1039
     return;
   } else {
 
   }
   {
 #line 1041
   printk("<3>render error detected, EIR: 0x%08x\n", eir);
   }
   {
 #line 1044
   __cil_tmp36 = dev->dev_private;
 #line 1044
   __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
 #line 1044
   __cil_tmp38 = __cil_tmp37->info;
 #line 1044
   __cil_tmp39 = (unsigned char *)__cil_tmp38;
 #line 1044
   __cil_tmp40 = __cil_tmp39 + 1UL;
 #line 1044
   __cil_tmp41 = *__cil_tmp40;
 #line 1044
   __cil_tmp42 = (unsigned int )__cil_tmp41;
 #line 1044
   if (__cil_tmp42 != 0U) {
     {
 #line 1045
     __cil_tmp43 = eir & 24U;
 #line 1045
     if (__cil_tmp43 != 0U) {
       {
 #line 1046
       tmp___0 = i915_read32(dev_priv, 8292U);
 #line 1046
       ipeir = tmp___0;
 #line 1048
       tmp___1 = i915_read32(dev_priv, 8292U);
 #line 1048
       printk("<3>  IPEIR: 0x%08x\n", tmp___1);
 #line 1050
       tmp___2 = i915_read32(dev_priv, 8296U);
 #line 1050
       printk("<3>  IPEHR: 0x%08x\n", tmp___2);
 #line 1052
       tmp___3 = i915_read32(dev_priv, 8300U);
 #line 1052
       printk("<3>  INSTDONE: 0x%08x\n", tmp___3);
 #line 1054
       tmp___4 = i915_read32(dev_priv, 8304U);
 #line 1054
       printk("<3>  INSTPS: 0x%08x\n", tmp___4);
 #line 1056
       tmp___5 = i915_read32(dev_priv, 8316U);
 #line 1056
       printk("<3>  INSTDONE1: 0x%08x\n", tmp___5);
 #line 1058
       tmp___6 = i915_read32(dev_priv, 8308U);
 #line 1058
       printk("<3>  ACTHD: 0x%08x\n", tmp___6);
 #line 1060
       i915_write32(dev_priv, 8292U, ipeir);
 #line 1061
       __cil_tmp44 = dev_priv->regs;
 #line 1061
       __cil_tmp45 = (void const volatile   *)__cil_tmp44;
 #line 1061
       __cil_tmp46 = __cil_tmp45 + 8292U;
 #line 1061
       readl(__cil_tmp46);
       }
     } else {
 
     }
     }
     {
 #line 1063
     __cil_tmp47 = eir & 32U;
 #line 1063
     if (__cil_tmp47 != 0U) {
       {
 #line 1064
       tmp___7 = i915_read32(dev_priv, 8228U);
 #line 1064
       pgtbl_err = tmp___7;
 #line 1065
       printk("<3>page table error\n");
 #line 1066
       printk("<3>  PGTBL_ER: 0x%08x\n", pgtbl_err);
 #line 1068
       i915_write32(dev_priv, 8228U, pgtbl_err);
 #line 1069
       __cil_tmp48 = dev_priv->regs;
 #line 1069
       __cil_tmp49 = (void const volatile   *)__cil_tmp48;
 #line 1069
       __cil_tmp50 = __cil_tmp49 + 8228U;
 #line 1069
       readl(__cil_tmp50);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1073
   __cil_tmp51 = dev->dev_private;
 #line 1073
   __cil_tmp52 = (struct drm_i915_private *)__cil_tmp51;
 #line 1073
   __cil_tmp53 = __cil_tmp52->info;
 #line 1073
   __cil_tmp54 = __cil_tmp53->gen;
 #line 1073
   __cil_tmp55 = (unsigned char )__cil_tmp54;
 #line 1073
   __cil_tmp56 = (unsigned int )__cil_tmp55;
 #line 1073
   if (__cil_tmp56 != 2U) {
     {
 #line 1074
     __cil_tmp57 = eir & 16U;
 #line 1074
     if (__cil_tmp57 != 0U) {
       {
 #line 1075
       tmp___8 = i915_read32(dev_priv, 8228U);
 #line 1075
       pgtbl_err___0 = tmp___8;
 #line 1076
       printk("<3>page table error\n");
 #line 1077
       printk("<3>  PGTBL_ER: 0x%08x\n", pgtbl_err___0);
 #line 1079
       i915_write32(dev_priv, 8228U, pgtbl_err___0);
 #line 1080
       __cil_tmp58 = dev_priv->regs;
 #line 1080
       __cil_tmp59 = (void const volatile   *)__cil_tmp58;
 #line 1080
       __cil_tmp60 = __cil_tmp59 + 8228U;
 #line 1080
       readl(__cil_tmp60);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1084
   __cil_tmp61 = eir & 2U;
 #line 1084
   if (__cil_tmp61 != 0U) {
     {
 #line 1085
     printk("<3>memory refresh error:\n");
 #line 1086
     pipe = 0;
     }
 #line 1086
     goto ldv_37887;
     ldv_37886: 
     {
 #line 1087
     __cil_tmp62 = pipe * 4096;
 #line 1087
     __cil_tmp63 = __cil_tmp62 + 458788;
 #line 1087
     __cil_tmp64 = (u32 )__cil_tmp63;
 #line 1087
     tmp___9 = i915_read32(dev_priv, __cil_tmp64);
 #line 1087
     __cil_tmp65 = pipe + 65;
 #line 1087
     printk("<3>pipe %c stat: 0x%08x\n", __cil_tmp65, tmp___9);
 #line 1086
     pipe = pipe + 1;
     }
     ldv_37887: ;
     {
 #line 1086
     __cil_tmp66 = dev_priv->num_pipe;
 #line 1086
     if (__cil_tmp66 > pipe) {
 #line 1087
       goto ldv_37886;
     } else {
 #line 1089
       goto ldv_37888;
     }
     }
     ldv_37888: ;
   } else {
 
   }
   }
   {
 #line 1091
   __cil_tmp67 = (int )eir;
 #line 1091
   if (__cil_tmp67 & 1) {
     {
 #line 1092
     printk("<3>instruction error\n");
 #line 1093
     tmp___10 = i915_read32(dev_priv, 8384U);
 #line 1093
     printk("<3>  INSTPM: 0x%08x\n", tmp___10);
     }
     {
 #line 1095
     __cil_tmp68 = dev->dev_private;
 #line 1095
     __cil_tmp69 = (struct drm_i915_private *)__cil_tmp68;
 #line 1095
     __cil_tmp70 = __cil_tmp69->info;
 #line 1095
     __cil_tmp71 = __cil_tmp70->gen;
 #line 1095
     __cil_tmp72 = (unsigned char )__cil_tmp71;
 #line 1095
     __cil_tmp73 = (unsigned int )__cil_tmp72;
 #line 1095
     if (__cil_tmp73 <= 3U) {
       {
 #line 1096
       tmp___11 = i915_read32(dev_priv, 8328U);
 #line 1096
       ipeir___0 = tmp___11;
 #line 1098
       tmp___12 = i915_read32(dev_priv, 8328U);
 #line 1098
       printk("<3>  IPEIR: 0x%08x\n", tmp___12);
 #line 1100
       tmp___13 = i915_read32(dev_priv, 8332U);
 #line 1100
       printk("<3>  IPEHR: 0x%08x\n", tmp___13);
 #line 1102
       tmp___14 = i915_read32(dev_priv, 8336U);
 #line 1102
       printk("<3>  INSTDONE: 0x%08x\n", tmp___14);
 #line 1104
       tmp___15 = i915_read32(dev_priv, 8392U);
 #line 1104
       printk("<3>  ACTHD: 0x%08x\n", tmp___15);
 #line 1106
       i915_write32(dev_priv, 8328U, ipeir___0);
 #line 1107
       __cil_tmp74 = dev_priv->regs;
 #line 1107
       __cil_tmp75 = (void const volatile   *)__cil_tmp74;
 #line 1107
       __cil_tmp76 = __cil_tmp75 + 8328U;
 #line 1107
       readl(__cil_tmp76);
       }
     } else {
       {
 #line 1109
       tmp___16 = i915_read32(dev_priv, 8292U);
 #line 1109
       ipeir___1 = tmp___16;
 #line 1111
       tmp___17 = i915_read32(dev_priv, 8292U);
 #line 1111
       printk("<3>  IPEIR: 0x%08x\n", tmp___17);
 #line 1113
       tmp___18 = i915_read32(dev_priv, 8296U);
 #line 1113
       printk("<3>  IPEHR: 0x%08x\n", tmp___18);
 #line 1115
       tmp___19 = i915_read32(dev_priv, 8300U);
 #line 1115
       printk("<3>  INSTDONE: 0x%08x\n", tmp___19);
 #line 1117
       tmp___20 = i915_read32(dev_priv, 8304U);
 #line 1117
       printk("<3>  INSTPS: 0x%08x\n", tmp___20);
 #line 1119
       tmp___21 = i915_read32(dev_priv, 8316U);
 #line 1119
       printk("<3>  INSTDONE1: 0x%08x\n", tmp___21);
 #line 1121
       tmp___22 = i915_read32(dev_priv, 8308U);
 #line 1121
       printk("<3>  ACTHD: 0x%08x\n", tmp___22);
 #line 1123
       i915_write32(dev_priv, 8292U, ipeir___1);
 #line 1124
       __cil_tmp77 = dev_priv->regs;
 #line 1124
       __cil_tmp78 = (void const volatile   *)__cil_tmp77;
 #line 1124
       __cil_tmp79 = __cil_tmp78 + 8292U;
 #line 1124
       readl(__cil_tmp79);
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 1128
   i915_write32(dev_priv, 8368U, eir);
 #line 1129
   __cil_tmp80 = dev_priv->regs;
 #line 1129
   __cil_tmp81 = (void const volatile   *)__cil_tmp80;
 #line 1129
   __cil_tmp82 = __cil_tmp81 + 8368U;
 #line 1129
   readl(__cil_tmp82);
 #line 1130
   eir = i915_read32(dev_priv, 8368U);
   }
 #line 1131
   if (eir != 0U) {
     {
 #line 1136
     drm_err("i915_report_and_clear_eir", "EIR stuck: 0x%08x, masking\n", eir);
 #line 1137
     tmp___23 = i915_read32(dev_priv, 8372U);
 #line 1137
     __cil_tmp83 = tmp___23 | eir;
 #line 1137
     i915_write32(dev_priv, 8372U, __cil_tmp83);
 #line 1138
     i915_write32(dev_priv, 8356U, 32768U);
     }
   } else {
 
   }
 #line 1140
   return;
 }
 }
 #line 1152 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void i915_handle_error(struct drm_device *dev , bool wedged ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp4 ;
   atomic_t *__cil_tmp5 ;
   wait_queue_head_t *__cil_tmp6 ;
   void *__cil_tmp7 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   unsigned char *__cil_tmp11 ;
   unsigned char *__cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   wait_queue_head_t *__cil_tmp15 ;
   void *__cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   wait_queue_head_t *__cil_tmp24 ;
   void *__cil_tmp25 ;
   struct workqueue_struct *__cil_tmp26 ;
   struct work_struct *__cil_tmp27 ;
 
   {
   {
 #line 1154
   __cil_tmp4 = dev->dev_private;
 #line 1154
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1156
   i915_capture_error_state(dev);
 #line 1157
   i915_report_and_clear_eir(dev);
   }
 #line 1159
   if ((int )wedged) {
     {
 #line 1160
     dev_priv->error_completion.done = 0U;
 #line 1161
     __cil_tmp5 = & dev_priv->mm.wedged;
 #line 1161
     atomic_set(__cil_tmp5, 1);
 #line 1166
     __cil_tmp6 = & dev_priv->ring[0].irq_queue;
 #line 1166
     __cil_tmp7 = (void *)0;
 #line 1166
     __wake_up(__cil_tmp6, 3U, 0, __cil_tmp7);
     }
     {
 #line 1167
     __cil_tmp8 = dev->dev_private;
 #line 1167
     __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 1167
     __cil_tmp10 = __cil_tmp9->info;
 #line 1167
     __cil_tmp11 = (unsigned char *)__cil_tmp10;
 #line 1167
     __cil_tmp12 = __cil_tmp11 + 3UL;
 #line 1167
     __cil_tmp13 = *__cil_tmp12;
 #line 1167
     __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 1167
     if (__cil_tmp14 != 0U) {
       {
 #line 1168
       __cil_tmp15 = & dev_priv->ring[1].irq_queue;
 #line 1168
       __cil_tmp16 = (void *)0;
 #line 1168
       __wake_up(__cil_tmp15, 3U, 0, __cil_tmp16);
       }
     } else {
 
     }
     }
     {
 #line 1169
     __cil_tmp17 = dev->dev_private;
 #line 1169
     __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 1169
     __cil_tmp19 = __cil_tmp18->info;
 #line 1169
     __cil_tmp20 = (unsigned char *)__cil_tmp19;
 #line 1169
     __cil_tmp21 = __cil_tmp20 + 3UL;
 #line 1169
     __cil_tmp22 = *__cil_tmp21;
 #line 1169
     __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 1169
     if (__cil_tmp23 != 0U) {
       {
 #line 1170
       __cil_tmp24 = & dev_priv->ring[2].irq_queue;
 #line 1170
       __cil_tmp25 = (void *)0;
 #line 1170
       __wake_up(__cil_tmp24, 3U, 0, __cil_tmp25);
       }
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 1173
   __cil_tmp26 = dev_priv->wq;
 #line 1173
   __cil_tmp27 = & dev_priv->error_work;
 #line 1173
   queue_work(__cil_tmp26, __cil_tmp27);
   }
 #line 1174
   return;
 }
 }
 #line 1176 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_pageflip_stall_check(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_crtc *crtc ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   struct drm_i915_gem_object *obj ;
   struct intel_unpin_work *work ;
   unsigned long flags ;
   bool stall_detected ;
   raw_spinlock_t *tmp ;
   int dspsurf ;
   u32 tmp___0 ;
   int dspaddr ;
   u32 tmp___1 ;
   void *__cil_tmp16 ;
   struct intel_crtc *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   spinlock_t *__cil_tmp20 ;
   struct intel_unpin_work *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   spinlock_t *__cil_tmp24 ;
   int __cil_tmp25 ;
   spinlock_t *__cil_tmp26 ;
   bool __cil_tmp27 ;
   spinlock_t *__cil_tmp28 ;
   void *__cil_tmp29 ;
   struct drm_i915_private *__cil_tmp30 ;
   struct intel_device_info  const  *__cil_tmp31 ;
   u8 __cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   enum plane __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   uint32_t __cil_tmp40 ;
   int __cil_tmp41 ;
   enum plane __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   u32 __cil_tmp46 ;
   struct drm_framebuffer *__cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   int __cil_tmp51 ;
   uint32_t __cil_tmp52 ;
   struct drm_framebuffer *__cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   int __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   uint32_t __cil_tmp58 ;
   uint32_t __cil_tmp59 ;
   uint32_t __cil_tmp60 ;
   int __cil_tmp61 ;
   spinlock_t *__cil_tmp62 ;
   enum plane __cil_tmp63 ;
   int __cil_tmp64 ;
 
   {
 #line 1178
   __cil_tmp16 = dev->dev_private;
 #line 1178
   dev_priv = (drm_i915_private_t *)__cil_tmp16;
 #line 1179
   crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 #line 1180
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 1180
   intel_crtc = (struct intel_crtc *)__mptr;
   {
 #line 1187
   __cil_tmp17 = (struct intel_crtc *)0;
 #line 1187
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 1187
   __cil_tmp19 = (unsigned long )intel_crtc;
 #line 1187
   if (__cil_tmp19 == __cil_tmp18) {
 #line 1188
     return;
   } else {
 
   }
   }
   {
 #line 1190
   __cil_tmp20 = & dev->event_lock;
 #line 1190
   tmp = spinlock_check(__cil_tmp20);
 #line 1190
   flags = _raw_spin_lock_irqsave(tmp);
 #line 1191
   work = intel_crtc->unpin_work;
   }
   {
 #line 1193
   __cil_tmp21 = (struct intel_unpin_work *)0;
 #line 1193
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 1193
   __cil_tmp23 = (unsigned long )work;
 #line 1193
   if (__cil_tmp23 == __cil_tmp22) {
     {
 #line 1195
     __cil_tmp24 = & dev->event_lock;
 #line 1195
     spin_unlock_irqrestore(__cil_tmp24, flags);
     }
 #line 1196
     return;
   } else {
     {
 #line 1193
     __cil_tmp25 = work->pending;
 #line 1193
     if (__cil_tmp25 != 0) {
       {
 #line 1195
       __cil_tmp26 = & dev->event_lock;
 #line 1195
       spin_unlock_irqrestore(__cil_tmp26, flags);
       }
 #line 1196
       return;
     } else {
       {
 #line 1193
       __cil_tmp27 = work->enable_stall_check;
 #line 1193
       if (! __cil_tmp27) {
         {
 #line 1195
         __cil_tmp28 = & dev->event_lock;
 #line 1195
         spin_unlock_irqrestore(__cil_tmp28, flags);
         }
 #line 1196
         return;
       } else {
 
       }
       }
     }
     }
   }
   }
 #line 1200
   obj = work->pending_flip_obj;
   {
 #line 1201
   __cil_tmp29 = dev->dev_private;
 #line 1201
   __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
 #line 1201
   __cil_tmp31 = __cil_tmp30->info;
 #line 1201
   __cil_tmp32 = __cil_tmp31->gen;
 #line 1201
   __cil_tmp33 = (unsigned char )__cil_tmp32;
 #line 1201
   __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 1201
   if (__cil_tmp34 > 3U) {
     {
 #line 1202
     __cil_tmp35 = intel_crtc->plane;
 #line 1202
     __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 1202
     __cil_tmp37 = __cil_tmp36 * 4096U;
 #line 1202
     __cil_tmp38 = __cil_tmp37 + 459164U;
 #line 1202
     dspsurf = (int )__cil_tmp38;
 #line 1203
     __cil_tmp39 = (u32 )dspsurf;
 #line 1203
     tmp___0 = i915_read32(dev_priv, __cil_tmp39);
 #line 1203
     __cil_tmp40 = obj->gtt_offset;
 #line 1203
     __cil_tmp41 = tmp___0 == __cil_tmp40;
 #line 1203
     stall_detected = (bool )__cil_tmp41;
     }
   } else {
     {
 #line 1205
     __cil_tmp42 = intel_crtc->plane;
 #line 1205
     __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 1205
     __cil_tmp44 = __cil_tmp43 * 4096U;
 #line 1205
     __cil_tmp45 = __cil_tmp44 + 459140U;
 #line 1205
     dspaddr = (int )__cil_tmp45;
 #line 1206
     __cil_tmp46 = (u32 )dspaddr;
 #line 1206
     tmp___1 = i915_read32(dev_priv, __cil_tmp46);
 #line 1206
     __cil_tmp47 = crtc->fb;
 #line 1206
     __cil_tmp48 = __cil_tmp47->bits_per_pixel;
 #line 1206
     __cil_tmp49 = crtc->x;
 #line 1206
     __cil_tmp50 = __cil_tmp49 * __cil_tmp48;
 #line 1206
     __cil_tmp51 = __cil_tmp50 / 8;
 #line 1206
     __cil_tmp52 = (uint32_t )__cil_tmp51;
 #line 1206
     __cil_tmp53 = crtc->fb;
 #line 1206
     __cil_tmp54 = __cil_tmp53->pitch;
 #line 1206
     __cil_tmp55 = crtc->y;
 #line 1206
     __cil_tmp56 = (unsigned int )__cil_tmp55;
 #line 1206
     __cil_tmp57 = __cil_tmp56 * __cil_tmp54;
 #line 1206
     __cil_tmp58 = obj->gtt_offset;
 #line 1206
     __cil_tmp59 = __cil_tmp58 + __cil_tmp57;
 #line 1206
     __cil_tmp60 = __cil_tmp59 + __cil_tmp52;
 #line 1206
     __cil_tmp61 = tmp___1 == __cil_tmp60;
 #line 1206
     stall_detected = (bool )__cil_tmp61;
     }
   }
   }
   {
 #line 1211
   __cil_tmp62 = & dev->event_lock;
 #line 1211
   spin_unlock_irqrestore(__cil_tmp62, flags);
   }
 #line 1213
   if ((int )stall_detected) {
     {
 #line 1214
     drm_ut_debug_printk(2U, "drm", "i915_pageflip_stall_check", "Pageflip stall detected\n");
 #line 1215
     __cil_tmp63 = intel_crtc->plane;
 #line 1215
     __cil_tmp64 = (int )__cil_tmp63;
 #line 1215
     intel_prepare_page_flip(dev, __cil_tmp64);
     }
   } else {
 
   }
 #line 1217
   return;
 }
 }
 #line 1219 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static irqreturn_t i915_driver_irq_handler(int irq , void *arg ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   u32 iir ;
   u32 new_iir ;
   u32 pipe_stats[3U] ;
   u32 vblank_status ;
   int vblank ;
   unsigned long irqflags ;
   int irq_received ;
   int ret ;
   int pipe ;
   bool blc_event ;
   raw_spinlock_t *tmp ;
   int reg ;
   u32 hotplug_status ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   bool tmp___2 ;
   void *__cil_tmp22 ;
   atomic_t *__cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_device_info  const  *__cil_tmp26 ;
   u8 __cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   spinlock_t *__cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   bool __cil_tmp32 ;
   int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   int __cil_tmp39 ;
   spinlock_t *__cil_tmp40 ;
   void *__cil_tmp41 ;
   struct drm_i915_private *__cil_tmp42 ;
   struct intel_device_info  const  *__cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char *__cil_tmp45 ;
   unsigned char __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   u32 __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   struct workqueue_struct *__cil_tmp51 ;
   struct work_struct *__cil_tmp52 ;
   struct drm_master *__cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   struct drm_minor *__cil_tmp55 ;
   struct drm_master *__cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   struct drm_minor *__cil_tmp58 ;
   struct drm_master *__cil_tmp59 ;
   void *__cil_tmp60 ;
   struct _drm_i915_sarea *__cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   struct _drm_i915_sarea *__cil_tmp63 ;
   unsigned long __cil_tmp64 ;
   struct intel_ring_buffer (*__cil_tmp65)[3U] ;
   struct intel_ring_buffer *__cil_tmp66 ;
   struct _drm_i915_sarea *__cil_tmp67 ;
   unsigned int __cil_tmp68 ;
   struct intel_ring_buffer (*__cil_tmp69)[3U] ;
   struct intel_ring_buffer *__cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   struct intel_ring_buffer (*__cil_tmp72)[3U] ;
   struct intel_ring_buffer *__cil_tmp73 ;
   struct intel_ring_buffer *__cil_tmp74 ;
   unsigned int __cil_tmp75 ;
   bool __cil_tmp76 ;
   unsigned int __cil_tmp77 ;
   bool __cil_tmp78 ;
   unsigned int __cil_tmp79 ;
   bool __cil_tmp80 ;
   unsigned long __cil_tmp81 ;
   unsigned long __cil_tmp82 ;
   int __cil_tmp83 ;
   int __cil_tmp84 ;
 
   {
   {
 #line 1221
   dev = (struct drm_device *)arg;
 #line 1222
   __cil_tmp22 = dev->dev_private;
 #line 1222
   dev_priv = (drm_i915_private_t *)__cil_tmp22;
 #line 1227
   vblank = 0;
 #line 1230
   ret = 0;
 #line 1231
   blc_event = (bool )0;
 #line 1233
   __cil_tmp23 = & dev_priv->irq_received;
 #line 1233
   atomic_inc(__cil_tmp23);
 #line 1235
   iir = i915_read32(dev_priv, 8356U);
   }
   {
 #line 1237
   __cil_tmp24 = dev->dev_private;
 #line 1237
   __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 1237
   __cil_tmp26 = __cil_tmp25->info;
 #line 1237
   __cil_tmp27 = __cil_tmp26->gen;
 #line 1237
   __cil_tmp28 = (unsigned char )__cil_tmp27;
 #line 1237
   __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 1237
   if (__cil_tmp29 > 3U) {
 #line 1238
     vblank_status = 4U;
   } else {
 #line 1240
     vblank_status = 2U;
   }
   }
   ldv_37946: 
   {
 #line 1243
   irq_received = iir != 0U;
 #line 1250
   __cil_tmp30 = & dev_priv->irq_lock;
 #line 1250
   tmp = spinlock_check(__cil_tmp30);
 #line 1250
   irqflags = _raw_spin_lock_irqsave(tmp);
   }
   {
 #line 1251
   __cil_tmp31 = iir & 32768U;
 #line 1251
   if (__cil_tmp31 != 0U) {
     {
 #line 1252
     __cil_tmp32 = (bool )0;
 #line 1252
     i915_handle_error(dev, __cil_tmp32);
     }
   } else {
 
   }
   }
 #line 1254
   pipe = 0;
 #line 1254
   goto ldv_37939;
   ldv_37938: 
   {
 #line 1255
   __cil_tmp33 = pipe * 4096;
 #line 1255
   reg = __cil_tmp33 + 458788;
 #line 1256
   __cil_tmp34 = (u32 )reg;
 #line 1256
   pipe_stats[pipe] = i915_read32(dev_priv, __cil_tmp34);
   }
   {
 #line 1261
   __cil_tmp35 = pipe_stats[pipe] & 2147549183U;
 #line 1261
   if (__cil_tmp35 != 0U) {
     {
 #line 1262
     __cil_tmp36 = (int )pipe_stats[pipe];
 #line 1262
     if (__cil_tmp36 < 0) {
       {
 #line 1263
       __cil_tmp37 = pipe + 65;
 #line 1263
       drm_ut_debug_printk(2U, "drm", "i915_driver_irq_handler", "pipe %c underrun\n",
                           __cil_tmp37);
       }
     } else {
 
     }
     }
     {
 #line 1265
     __cil_tmp38 = (u32 )reg;
 #line 1265
     i915_write32(dev_priv, __cil_tmp38, pipe_stats[pipe]);
 #line 1266
     irq_received = 1;
     }
   } else {
 
   }
   }
 #line 1254
   pipe = pipe + 1;
   ldv_37939: ;
   {
 #line 1254
   __cil_tmp39 = dev_priv->num_pipe;
 #line 1254
   if (__cil_tmp39 > pipe) {
 #line 1255
     goto ldv_37938;
   } else {
 #line 1257
     goto ldv_37940;
   }
   }
   ldv_37940: 
   {
 #line 1269
   __cil_tmp40 = & dev_priv->irq_lock;
 #line 1269
   spin_unlock_irqrestore(__cil_tmp40, irqflags);
   }
 #line 1271
   if (irq_received == 0) {
 #line 1272
     goto ldv_37941;
   } else {
 
   }
 #line 1274
   ret = 1;
   {
 #line 1277
   __cil_tmp41 = dev->dev_private;
 #line 1277
   __cil_tmp42 = (struct drm_i915_private *)__cil_tmp41;
 #line 1277
   __cil_tmp43 = __cil_tmp42->info;
 #line 1277
   __cil_tmp44 = (unsigned char *)__cil_tmp43;
 #line 1277
   __cil_tmp45 = __cil_tmp44 + 2UL;
 #line 1277
   __cil_tmp46 = *__cil_tmp45;
 #line 1277
   __cil_tmp47 = (unsigned int )__cil_tmp46;
 #line 1277
   if (__cil_tmp47 != 0U) {
     {
 #line 1277
     __cil_tmp48 = iir & 131072U;
 #line 1277
     if (__cil_tmp48 != 0U) {
       {
 #line 1279
       tmp___0 = i915_read32(dev_priv, 397588U);
 #line 1279
       hotplug_status = tmp___0;
 #line 1281
       drm_ut_debug_printk(2U, "drm", "i915_driver_irq_handler", "hotplug event received, stat 0x%08x\n",
                           hotplug_status);
       }
       {
 #line 1283
       __cil_tmp49 = dev_priv->hotplug_supported_mask;
 #line 1283
       __cil_tmp50 = __cil_tmp49 & hotplug_status;
 #line 1283
       if (__cil_tmp50 != 0U) {
         {
 #line 1284
         __cil_tmp51 = dev_priv->wq;
 #line 1284
         __cil_tmp52 = & dev_priv->hotplug_work;
 #line 1284
         queue_work(__cil_tmp51, __cil_tmp52);
         }
       } else {
 
       }
       }
       {
 #line 1287
       i915_write32(dev_priv, 397588U, hotplug_status);
 #line 1288
       i915_read32(dev_priv, 397588U);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1291
   i915_write32(dev_priv, 8356U, iir);
 #line 1292
   new_iir = i915_read32(dev_priv, 8356U);
   }
   {
 #line 1294
   __cil_tmp53 = (struct drm_master *)0;
 #line 1294
   __cil_tmp54 = (unsigned long )__cil_tmp53;
 #line 1294
   __cil_tmp55 = dev->primary;
 #line 1294
   __cil_tmp56 = __cil_tmp55->master;
 #line 1294
   __cil_tmp57 = (unsigned long )__cil_tmp56;
 #line 1294
   if (__cil_tmp57 != __cil_tmp54) {
 #line 1295
     __cil_tmp58 = dev->primary;
 #line 1295
     __cil_tmp59 = __cil_tmp58->master;
 #line 1295
     __cil_tmp60 = __cil_tmp59->driver_priv;
 #line 1295
     master_priv = (struct drm_i915_master_private *)__cil_tmp60;
     {
 #line 1296
     __cil_tmp61 = (struct _drm_i915_sarea *)0;
 #line 1296
     __cil_tmp62 = (unsigned long )__cil_tmp61;
 #line 1296
     __cil_tmp63 = master_priv->sarea_priv;
 #line 1296
     __cil_tmp64 = (unsigned long )__cil_tmp63;
 #line 1296
     if (__cil_tmp64 != __cil_tmp62) {
       {
 #line 1297
       __cil_tmp65 = & dev_priv->ring;
 #line 1297
       __cil_tmp66 = (struct intel_ring_buffer *)__cil_tmp65;
 #line 1297
       tmp___1 = intel_read_status_page(__cil_tmp66, 33);
 #line 1297
       __cil_tmp67 = master_priv->sarea_priv;
 #line 1297
       __cil_tmp67->last_dispatch = (int )tmp___1;
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1301
   __cil_tmp68 = iir & 2U;
 #line 1301
   if (__cil_tmp68 != 0U) {
     {
 #line 1302
     __cil_tmp69 = & dev_priv->ring;
 #line 1302
     __cil_tmp70 = (struct intel_ring_buffer *)__cil_tmp69;
 #line 1302
     notify_ring(dev, __cil_tmp70);
     }
   } else {
 
   }
   }
   {
 #line 1303
   __cil_tmp71 = iir & 33554432U;
 #line 1303
   if (__cil_tmp71 != 0U) {
     {
 #line 1304
     __cil_tmp72 = & dev_priv->ring;
 #line 1304
     __cil_tmp73 = (struct intel_ring_buffer *)__cil_tmp72;
 #line 1304
     __cil_tmp74 = __cil_tmp73 + 1UL;
 #line 1304
     notify_ring(dev, __cil_tmp74);
     }
   } else {
 
   }
   }
   {
 #line 1306
   __cil_tmp75 = iir & 2048U;
 #line 1306
   if (__cil_tmp75 != 0U) {
     {
 #line 1307
     intel_prepare_page_flip(dev, 0);
     }
     {
 #line 1308
     __cil_tmp76 = dev_priv->flip_pending_is_done;
 #line 1308
     if ((int )__cil_tmp76) {
       {
 #line 1309
       intel_finish_page_flip_plane(dev, 0);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1312
   __cil_tmp77 = iir & 1024U;
 #line 1312
   if (__cil_tmp77 != 0U) {
     {
 #line 1313
     intel_prepare_page_flip(dev, 1);
     }
     {
 #line 1314
     __cil_tmp78 = dev_priv->flip_pending_is_done;
 #line 1314
     if ((int )__cil_tmp78) {
       {
 #line 1315
       intel_finish_page_flip_plane(dev, 1);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 1318
   pipe = 0;
 #line 1318
   goto ldv_37944;
   ldv_37943: ;
   {
 #line 1319
   __cil_tmp79 = pipe_stats[pipe] & vblank_status;
 #line 1319
   if (__cil_tmp79 != 0U) {
     {
 #line 1319
     tmp___2 = drm_handle_vblank(dev, pipe);
     }
 #line 1319
     if ((int )tmp___2) {
 #line 1321
       vblank = vblank + 1;
       {
 #line 1322
       __cil_tmp80 = dev_priv->flip_pending_is_done;
 #line 1322
       if (! __cil_tmp80) {
         {
 #line 1323
         i915_pageflip_stall_check(dev, pipe);
 #line 1324
         intel_finish_page_flip(dev, pipe);
         }
       } else {
 
       }
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1328
   __cil_tmp81 = (unsigned long )pipe_stats[pipe];
 #line 1328
   __cil_tmp82 = __cil_tmp81 & 64UL;
 #line 1328
   if (__cil_tmp82 != 0UL) {
 #line 1329
     blc_event = (bool )1;
   } else {
 
   }
   }
 #line 1318
   pipe = pipe + 1;
   ldv_37944: ;
   {
 #line 1318
   __cil_tmp83 = dev_priv->num_pipe;
 #line 1318
   if (__cil_tmp83 > pipe) {
 #line 1319
     goto ldv_37943;
   } else {
 #line 1321
     goto ldv_37945;
   }
   }
   ldv_37945: ;
 #line 1333
   if ((int )blc_event) {
     {
 #line 1334
     intel_opregion_asle_intr(dev);
     }
   } else {
     {
 #line 1333
     __cil_tmp84 = (int )iir;
 #line 1333
     if (__cil_tmp84 & 1) {
       {
 #line 1334
       intel_opregion_asle_intr(dev);
       }
     } else {
 
     }
     }
   }
 #line 1351
   iir = new_iir;
 #line 1352
   goto ldv_37946;
   ldv_37941: ;
 #line 1354
   return ((irqreturn_t )ret);
 }
 }
 #line 1357 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_emit_irq(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   int tmp ;
   void *__cil_tmp5 ;
   struct drm_minor *__cil_tmp6 ;
   struct drm_master *__cil_tmp7 ;
   void *__cil_tmp8 ;
   uint32_t __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   int __cil_tmp11 ;
   struct _drm_i915_sarea *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct _drm_i915_sarea *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct _drm_i915_sarea *__cil_tmp16 ;
   uint32_t __cil_tmp17 ;
   struct intel_ring_buffer (*__cil_tmp18)[3U] ;
   struct intel_ring_buffer *__cil_tmp19 ;
   struct intel_ring_buffer (*__cil_tmp20)[3U] ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
   struct intel_ring_buffer (*__cil_tmp24)[3U] ;
   struct intel_ring_buffer *__cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   struct intel_ring_buffer (*__cil_tmp27)[3U] ;
   struct intel_ring_buffer *__cil_tmp28 ;
   struct intel_ring_buffer (*__cil_tmp29)[3U] ;
   struct intel_ring_buffer *__cil_tmp30 ;
   uint32_t __cil_tmp31 ;
 
   {
   {
 #line 1359
   __cil_tmp5 = dev->dev_private;
 #line 1359
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 1360
   __cil_tmp6 = dev->primary;
 #line 1360
   __cil_tmp7 = __cil_tmp6->master;
 #line 1360
   __cil_tmp8 = __cil_tmp7->driver_priv;
 #line 1360
   master_priv = (struct drm_i915_master_private *)__cil_tmp8;
 #line 1362
   i915_kernel_lost_context(dev);
 #line 1364
   drm_ut_debug_printk(2U, "drm", "i915_emit_irq", "\n");
 #line 1366
   __cil_tmp9 = dev_priv->counter;
 #line 1366
   dev_priv->counter = __cil_tmp9 + 1U;
   }
   {
 #line 1367
   __cil_tmp10 = dev_priv->counter;
 #line 1367
   __cil_tmp11 = (int )__cil_tmp10;
 #line 1367
   if (__cil_tmp11 < 0) {
 #line 1368
     dev_priv->counter = 1U;
   } else {
 
   }
   }
   {
 #line 1369
   __cil_tmp12 = (struct _drm_i915_sarea *)0;
 #line 1369
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 1369
   __cil_tmp14 = master_priv->sarea_priv;
 #line 1369
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 1369
   if (__cil_tmp15 != __cil_tmp13) {
 #line 1370
     __cil_tmp16 = master_priv->sarea_priv;
 #line 1370
     __cil_tmp17 = dev_priv->counter;
 #line 1370
     __cil_tmp16->last_enqueue = (int )__cil_tmp17;
   } else {
 
   }
   }
   {
 #line 1372
   __cil_tmp18 = & dev_priv->ring;
 #line 1372
   __cil_tmp19 = (struct intel_ring_buffer *)__cil_tmp18;
 #line 1372
   tmp = intel_ring_begin(__cil_tmp19, 4);
   }
 #line 1372
   if (tmp == 0) {
     {
 #line 1373
     __cil_tmp20 = & dev_priv->ring;
 #line 1373
     __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
 #line 1373
     intel_ring_emit(__cil_tmp21, 276824065U);
 #line 1374
     __cil_tmp22 = & dev_priv->ring;
 #line 1374
     __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 1374
     intel_ring_emit(__cil_tmp23, 132U);
 #line 1375
     __cil_tmp24 = & dev_priv->ring;
 #line 1375
     __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
 #line 1375
     __cil_tmp26 = dev_priv->counter;
 #line 1375
     intel_ring_emit(__cil_tmp25, __cil_tmp26);
 #line 1376
     __cil_tmp27 = & dev_priv->ring;
 #line 1376
     __cil_tmp28 = (struct intel_ring_buffer *)__cil_tmp27;
 #line 1376
     intel_ring_emit(__cil_tmp28, 16777216U);
 #line 1377
     __cil_tmp29 = & dev_priv->ring;
 #line 1377
     __cil_tmp30 = (struct intel_ring_buffer *)__cil_tmp29;
 #line 1377
     intel_ring_advance(__cil_tmp30);
     }
   } else {
 
   }
   {
 #line 1380
   __cil_tmp31 = dev_priv->counter;
 #line 1380
   return ((int )__cil_tmp31);
   }
 }
 }
 #line 1383 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_wait_irq(struct drm_device *dev , int irq_nr ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   int ret ;
   struct intel_ring_buffer *ring ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   wait_queue_t entry ;
   struct task_struct *tmp___2 ;
   unsigned long end ;
   struct task_struct *tmp___3 ;
   u32 tmp___4 ;
   struct task_struct *tmp___5 ;
   int tmp___6 ;
   struct task_struct *tmp___7 ;
   unsigned long timeout__ ;
   unsigned long tmp___8 ;
   int ret__ ;
   struct thread_info *tmp___9 ;
   int pfo_ret__ ;
   int tmp___10 ;
   u32 tmp___11 ;
   bool tmp___12 ;
   u32 tmp___13 ;
   void *__cil_tmp27 ;
   struct drm_minor *__cil_tmp28 ;
   struct drm_master *__cil_tmp29 ;
   void *__cil_tmp30 ;
   struct intel_ring_buffer (*__cil_tmp31)[3U] ;
   struct intel_ring_buffer (*__cil_tmp32)[3U] ;
   struct intel_ring_buffer *__cil_tmp33 ;
   struct intel_ring_buffer (*__cil_tmp34)[3U] ;
   struct intel_ring_buffer *__cil_tmp35 ;
   u32 __cil_tmp36 ;
   struct _drm_i915_sarea *__cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   struct _drm_i915_sarea *__cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   struct intel_ring_buffer (*__cil_tmp41)[3U] ;
   struct intel_ring_buffer *__cil_tmp42 ;
   struct _drm_i915_sarea *__cil_tmp43 ;
   struct _drm_i915_sarea *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct _drm_i915_sarea *__cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   struct _drm_i915_sarea *__cil_tmp48 ;
   struct _drm_i915_sarea *__cil_tmp49 ;
   int __cil_tmp50 ;
   bool (*__cil_tmp51)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp52 ;
   wait_queue_head_t *__cil_tmp53 ;
   struct intel_ring_buffer (*__cil_tmp54)[3U] ;
   struct intel_ring_buffer *__cil_tmp55 ;
   u32 __cil_tmp56 ;
   long __cil_tmp57 ;
   long __cil_tmp58 ;
   long __cil_tmp59 ;
   wait_queue_head_t *__cil_tmp60 ;
   void (*__cil_tmp61)(struct intel_ring_buffer * ) ;
   unsigned int __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned long __cil_tmp64 ;
   long __cil_tmp65 ;
   long __cil_tmp66 ;
   long __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   atomic_t const   *__cil_tmp70 ;
   struct intel_ring_buffer (*__cil_tmp71)[3U] ;
   struct intel_ring_buffer *__cil_tmp72 ;
   u32 __cil_tmp73 ;
   struct intel_ring_buffer (*__cil_tmp74)[3U] ;
   struct intel_ring_buffer *__cil_tmp75 ;
   uint32_t __cil_tmp76 ;
   int __cil_tmp77 ;
 
   {
   {
 #line 1385
   __cil_tmp27 = dev->dev_private;
 #line 1385
   dev_priv = (drm_i915_private_t *)__cil_tmp27;
 #line 1386
   __cil_tmp28 = dev->primary;
 #line 1386
   __cil_tmp29 = __cil_tmp28->master;
 #line 1386
   __cil_tmp30 = __cil_tmp29->driver_priv;
 #line 1386
   master_priv = (struct drm_i915_master_private *)__cil_tmp30;
 #line 1387
   ret = 0;
 #line 1388
   __cil_tmp31 = & dev_priv->ring;
 #line 1388
   ring = (struct intel_ring_buffer *)__cil_tmp31;
 #line 1390
   __cil_tmp32 = & dev_priv->ring;
 #line 1390
   __cil_tmp33 = (struct intel_ring_buffer *)__cil_tmp32;
 #line 1390
   tmp = intel_read_status_page(__cil_tmp33, 33);
 #line 1390
   drm_ut_debug_printk(2U, "drm", "i915_wait_irq", "irq_nr=%d breadcrumb=%d\n", irq_nr,
                       tmp);
 #line 1393
   __cil_tmp34 = & dev_priv->ring;
 #line 1393
   __cil_tmp35 = (struct intel_ring_buffer *)__cil_tmp34;
 #line 1393
   tmp___1 = intel_read_status_page(__cil_tmp35, 33);
   }
   {
 #line 1393
   __cil_tmp36 = (u32 )irq_nr;
 #line 1393
   if (tmp___1 >= __cil_tmp36) {
     {
 #line 1394
     __cil_tmp37 = (struct _drm_i915_sarea *)0;
 #line 1394
     __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 1394
     __cil_tmp39 = master_priv->sarea_priv;
 #line 1394
     __cil_tmp40 = (unsigned long )__cil_tmp39;
 #line 1394
     if (__cil_tmp40 != __cil_tmp38) {
       {
 #line 1395
       __cil_tmp41 = & dev_priv->ring;
 #line 1395
       __cil_tmp42 = (struct intel_ring_buffer *)__cil_tmp41;
 #line 1395
       tmp___0 = intel_read_status_page(__cil_tmp42, 33);
 #line 1395
       __cil_tmp43 = master_priv->sarea_priv;
 #line 1395
       __cil_tmp43->last_dispatch = (int )tmp___0;
       }
     } else {
 
     }
     }
 #line 1396
     return (0);
   } else {
 
   }
   }
   {
 #line 1399
   __cil_tmp44 = (struct _drm_i915_sarea *)0;
 #line 1399
   __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 1399
   __cil_tmp46 = master_priv->sarea_priv;
 #line 1399
   __cil_tmp47 = (unsigned long )__cil_tmp46;
 #line 1399
   if (__cil_tmp47 != __cil_tmp45) {
 #line 1400
     __cil_tmp48 = master_priv->sarea_priv;
 #line 1400
     __cil_tmp49 = master_priv->sarea_priv;
 #line 1400
     __cil_tmp50 = __cil_tmp49->perf_boxes;
 #line 1400
     __cil_tmp48->perf_boxes = __cil_tmp50 | 4;
   } else {
 
   }
   }
   {
 #line 1402
   __cil_tmp51 = ring->irq_get;
 #line 1402
   tmp___12 = (*__cil_tmp51)(ring);
   }
 #line 1402
   if ((int )tmp___12) {
     {
 #line 1403
     tmp___2 = get_current();
 #line 1403
     entry.flags = 0U;
 #line 1403
     entry.private = (void *)tmp___2;
 #line 1403
     entry.func = & default_wake_function;
 #line 1403
     entry.task_list.next = (struct list_head *)0;
 #line 1403
     entry.task_list.prev = (struct list_head *)0;
 #line 1403
     __cil_tmp52 = (unsigned long )jiffies;
 #line 1403
     end = __cil_tmp52 + 750UL;
 #line 1403
     __cil_tmp53 = & ring->irq_queue;
 #line 1403
     add_wait_queue(__cil_tmp53, & entry);
     }
     ldv_37971: 
     {
 #line 1403
     tmp___3 = get_current();
 #line 1403
     tmp___3->state = (long volatile   )1L;
 #line 1403
     __cil_tmp54 = & dev_priv->ring;
 #line 1403
     __cil_tmp55 = (struct intel_ring_buffer *)__cil_tmp54;
 #line 1403
     tmp___4 = intel_read_status_page(__cil_tmp55, 33);
     }
     {
 #line 1403
     __cil_tmp56 = (u32 )irq_nr;
 #line 1403
     if (tmp___4 >= __cil_tmp56) {
 #line 1403
       goto ldv_37964;
     } else {
 
     }
     }
     {
 #line 1403
     __cil_tmp57 = (long )end;
 #line 1403
     __cil_tmp58 = (long )jiffies;
 #line 1403
     __cil_tmp59 = __cil_tmp58 - __cil_tmp57;
 #line 1403
     if (__cil_tmp59 >= 0L) {
 #line 1403
       ret = -16;
 #line 1403
       goto ldv_37964;
     } else {
 
     }
     }
     {
 #line 1403
     schedule_timeout(2L);
 #line 1403
     tmp___5 = get_current();
 #line 1403
     tmp___6 = signal_pending(tmp___5);
     }
 #line 1403
     if (tmp___6 != 0) {
 #line 1403
       ret = -4;
 #line 1403
       goto ldv_37964;
     } else {
 
     }
 #line 1403
     goto ldv_37971;
     ldv_37964: 
     {
 #line 1403
     tmp___7 = get_current();
 #line 1403
     tmp___7->state = (long volatile   )0L;
 #line 1403
     __cil_tmp60 = & ring->irq_queue;
 #line 1403
     remove_wait_queue(__cil_tmp60, & entry);
 #line 1405
     __cil_tmp61 = ring->irq_put;
 #line 1405
     (*__cil_tmp61)(ring);
     }
   } else {
     {
 #line 1406
     __cil_tmp62 = (unsigned int const   )3000U;
 #line 1406
     __cil_tmp63 = (unsigned int )__cil_tmp62;
 #line 1406
     tmp___8 = msecs_to_jiffies(__cil_tmp63);
 #line 1406
     __cil_tmp64 = (unsigned long )jiffies;
 #line 1406
     timeout__ = tmp___8 + __cil_tmp64;
 #line 1406
     ret__ = 0;
     }
 #line 1406
     goto ldv_37990;
     ldv_37989: ;
     {
 #line 1406
     __cil_tmp65 = (long )jiffies;
 #line 1406
     __cil_tmp66 = (long )timeout__;
 #line 1406
     __cil_tmp67 = __cil_tmp66 - __cil_tmp65;
 #line 1406
     if (__cil_tmp67 < 0L) {
 #line 1406
       ret__ = -110;
 #line 1406
       goto ldv_37980;
     } else {
 
     }
     }
     {
 #line 1406
     tmp___9 = current_thread_info();
     }
     {
 #line 1406
     __cil_tmp68 = tmp___9->preempt_count;
 #line 1406
     __cil_tmp69 = __cil_tmp68 & -268435457;
 #line 1406
     if (__cil_tmp69 == 0) {
 #line 1406
       if (1) {
 #line 1406
         goto case_4;
       } else {
 #line 1406
         goto switch_default;
 #line 1406
         if (0) {
 #line 1406
           __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 1406
           goto ldv_37983;
 #line 1406
           __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1406
           goto ldv_37983;
           case_4: 
 #line 1406
           __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1406
           goto ldv_37983;
 #line 1406
           __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1406
           goto ldv_37983;
           switch_default: 
           {
 #line 1406
           __bad_percpu_size();
           }
         } else {
 
         }
       }
       ldv_37983: 
       {
 #line 1406
       __cil_tmp70 = (atomic_t const   *)(& kgdb_active);
 #line 1406
       tmp___10 = atomic_read(__cil_tmp70);
       }
 #line 1406
       if (pfo_ret__ != tmp___10) {
         {
 #line 1406
         msleep(1U);
         }
       } else {
 
       }
     } else {
 
     }
     }
     ldv_37990: 
     {
 #line 1406
     __cil_tmp71 = & dev_priv->ring;
 #line 1406
     __cil_tmp72 = (struct intel_ring_buffer *)__cil_tmp71;
 #line 1406
     tmp___11 = intel_read_status_page(__cil_tmp72, 33);
     }
     {
 #line 1406
     __cil_tmp73 = (u32 )irq_nr;
 #line 1406
     if (tmp___11 < __cil_tmp73) {
 #line 1407
       goto ldv_37989;
     } else {
 #line 1409
       goto ldv_37980;
     }
     }
     ldv_37980: ;
 #line 1406
     if (ret__ != 0) {
 #line 1407
       ret = -16;
     } else {
 
     }
   }
 #line 1409
   if (ret == -16) {
     {
 #line 1410
     __cil_tmp74 = & dev_priv->ring;
 #line 1410
     __cil_tmp75 = (struct intel_ring_buffer *)__cil_tmp74;
 #line 1410
     tmp___13 = intel_read_status_page(__cil_tmp75, 33);
 #line 1410
     __cil_tmp76 = dev_priv->counter;
 #line 1410
     __cil_tmp77 = (int )__cil_tmp76;
 #line 1410
     drm_err("i915_wait_irq", "EBUSY -- rec: %d emitted: %d\n", tmp___13, __cil_tmp77);
     }
   } else {
 
   }
 #line 1414
   return (ret);
 }
 }
 #line 1419 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 int i915_irq_emit(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_irq_emit_t *emit ;
   int result ;
   int tmp ;
   void *__cil_tmp8 ;
   drm_i915_private_t *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   void *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct intel_ring_buffer (*__cil_tmp14)[3U] ;
   struct intel_ring_buffer *__cil_tmp15 ;
   void *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct drm_i915_gem_object *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void *__cil_tmp20 ;
   struct drm_i915_private *__cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
   struct drm_i915_gem_object *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_master *__cil_tmp26 ;
   struct drm_hw_lock *__cil_tmp27 ;
   unsigned int volatile   __cil_tmp28 ;
   int __cil_tmp29 ;
   struct drm_master *__cil_tmp30 ;
   struct drm_hw_lock *__cil_tmp31 ;
   unsigned int volatile   __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   struct drm_master *__cil_tmp35 ;
   struct drm_file *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct drm_master *__cil_tmp38 ;
   struct drm_file *__cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   struct drm_master *__cil_tmp41 ;
   struct drm_hw_lock *__cil_tmp42 ;
   unsigned int volatile   __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   struct drm_master *__cil_tmp46 ;
   struct drm_file *__cil_tmp47 ;
   struct mutex *__cil_tmp48 ;
   struct mutex *__cil_tmp49 ;
   int *__cil_tmp50 ;
   void *__cil_tmp51 ;
   void const   *__cil_tmp52 ;
 
   {
 #line 1422
   __cil_tmp8 = dev->dev_private;
 #line 1422
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 1423
   emit = (drm_i915_irq_emit_t *)data;
   {
 #line 1426
   __cil_tmp9 = (drm_i915_private_t *)0;
 #line 1426
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 1426
   __cil_tmp11 = (unsigned long )dev_priv;
 #line 1426
   if (__cil_tmp11 == __cil_tmp10) {
     {
 #line 1427
     drm_err("i915_irq_emit", "called with no initialization\n");
     }
 #line 1428
     return (-22);
   } else {
     {
 #line 1426
     __cil_tmp12 = (void *)0;
 #line 1426
     __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 1426
     __cil_tmp14 = & dev_priv->ring;
 #line 1426
     __cil_tmp15 = (struct intel_ring_buffer *)__cil_tmp14;
 #line 1426
     __cil_tmp16 = __cil_tmp15->virtual_start;
 #line 1426
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 1426
     if (__cil_tmp17 == __cil_tmp13) {
       {
 #line 1427
       drm_err("i915_irq_emit", "called with no initialization\n");
       }
 #line 1428
       return (-22);
     } else {
 
     }
     }
   }
   }
   {
 #line 1431
   __cil_tmp18 = (struct drm_i915_gem_object *)0;
 #line 1431
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 1431
   __cil_tmp20 = dev->dev_private;
 #line 1431
   __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
 #line 1431
   __cil_tmp22 = & __cil_tmp21->ring;
 #line 1431
   __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 1431
   __cil_tmp24 = __cil_tmp23->obj;
 #line 1431
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 1431
   if (__cil_tmp25 == __cil_tmp19) {
     {
 #line 1431
     __cil_tmp26 = file_priv->master;
 #line 1431
     __cil_tmp27 = __cil_tmp26->lock.hw_lock;
 #line 1431
     __cil_tmp28 = __cil_tmp27->lock;
 #line 1431
     __cil_tmp29 = (int )__cil_tmp28;
 #line 1431
     if (__cil_tmp29 >= 0) {
       {
 #line 1431
       __cil_tmp30 = file_priv->master;
 #line 1431
       __cil_tmp31 = __cil_tmp30->lock.hw_lock;
 #line 1431
       __cil_tmp32 = __cil_tmp31->lock;
 #line 1431
       __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 1431
       __cil_tmp34 = __cil_tmp33 & 2147483648U;
 #line 1431
       __cil_tmp35 = file_priv->master;
 #line 1431
       __cil_tmp36 = __cil_tmp35->lock.file_priv;
 #line 1431
       drm_err("i915_irq_emit", "%s called without lock held, held  %d owner %p %p\n",
               "i915_irq_emit", __cil_tmp34, __cil_tmp36, file_priv);
       }
 #line 1431
       return (-22);
     } else {
       {
 #line 1431
       __cil_tmp37 = (unsigned long )file_priv;
 #line 1431
       __cil_tmp38 = file_priv->master;
 #line 1431
       __cil_tmp39 = __cil_tmp38->lock.file_priv;
 #line 1431
       __cil_tmp40 = (unsigned long )__cil_tmp39;
 #line 1431
       if (__cil_tmp40 != __cil_tmp37) {
         {
 #line 1431
         __cil_tmp41 = file_priv->master;
 #line 1431
         __cil_tmp42 = __cil_tmp41->lock.hw_lock;
 #line 1431
         __cil_tmp43 = __cil_tmp42->lock;
 #line 1431
         __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 1431
         __cil_tmp45 = __cil_tmp44 & 2147483648U;
 #line 1431
         __cil_tmp46 = file_priv->master;
 #line 1431
         __cil_tmp47 = __cil_tmp46->lock.file_priv;
 #line 1431
         drm_err("i915_irq_emit", "%s called without lock held, held  %d owner %p %p\n",
                 "i915_irq_emit", __cil_tmp45, __cil_tmp47, file_priv);
         }
 #line 1431
         return (-22);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 1433
   __cil_tmp48 = & dev->struct_mutex;
 #line 1433
   mutex_lock_nested(__cil_tmp48, 0U);
 #line 1434
   result = i915_emit_irq(dev);
 #line 1435
   __cil_tmp49 = & dev->struct_mutex;
 #line 1435
   mutex_unlock(__cil_tmp49);
 #line 1437
   __cil_tmp50 = emit->irq_seq;
 #line 1437
   __cil_tmp51 = (void *)__cil_tmp50;
 #line 1437
   __cil_tmp52 = (void const   *)(& result);
 #line 1437
   tmp = copy_to_user(__cil_tmp51, __cil_tmp52, 4U);
   }
 #line 1437
   if (tmp != 0) {
     {
 #line 1438
     drm_err("i915_irq_emit", "copy_to_user\n");
     }
 #line 1439
     return (-14);
   } else {
 
   }
 #line 1442
   return (0);
 }
 }
 #line 1447 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 int i915_irq_wait(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_irq_wait_t *irqwait ;
   int tmp ;
   void *__cil_tmp7 ;
   drm_i915_private_t *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   int __cil_tmp11 ;
 
   {
 #line 1450
   __cil_tmp7 = dev->dev_private;
 #line 1450
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 1451
   irqwait = (drm_i915_irq_wait_t *)data;
   {
 #line 1453
   __cil_tmp8 = (drm_i915_private_t *)0;
 #line 1453
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 1453
   __cil_tmp10 = (unsigned long )dev_priv;
 #line 1453
   if (__cil_tmp10 == __cil_tmp9) {
     {
 #line 1454
     drm_err("i915_irq_wait", "called with no initialization\n");
     }
 #line 1455
     return (-22);
   } else {
 
   }
   }
   {
 #line 1458
   __cil_tmp11 = irqwait->irq_seq;
 #line 1458
   tmp = i915_wait_irq(dev, __cil_tmp11);
   }
 #line 1458
   return (tmp);
 }
 }
 #line 1464 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_enable_vblank(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   int tmp ;
   raw_spinlock_t *tmp___0 ;
   void *__cil_tmp7 ;
   spinlock_t *__cil_tmp8 ;
   void *__cil_tmp9 ;
   struct drm_i915_private *__cil_tmp10 ;
   struct intel_device_info  const  *__cil_tmp11 ;
   u8 __cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   u8 __cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   spinlock_t *__cil_tmp19 ;
 
   {
   {
 #line 1466
   __cil_tmp7 = dev->dev_private;
 #line 1466
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 1469
   tmp = i915_pipe_enabled(dev, pipe);
   }
 #line 1469
   if (tmp == 0) {
 #line 1470
     return (-22);
   } else {
 
   }
   {
 #line 1472
   __cil_tmp8 = & dev_priv->irq_lock;
 #line 1472
   tmp___0 = spinlock_check(__cil_tmp8);
 #line 1472
   irqflags = _raw_spin_lock_irqsave(tmp___0);
   }
   {
 #line 1473
   __cil_tmp9 = dev->dev_private;
 #line 1473
   __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
 #line 1473
   __cil_tmp11 = __cil_tmp10->info;
 #line 1473
   __cil_tmp12 = __cil_tmp11->gen;
 #line 1473
   __cil_tmp13 = (unsigned char )__cil_tmp12;
 #line 1473
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 1473
   if (__cil_tmp14 > 3U) {
     {
 #line 1474
     i915_enable_pipestat(dev_priv, pipe, 262144U);
     }
   } else {
     {
 #line 1477
     i915_enable_pipestat(dev_priv, pipe, 131072U);
     }
   }
   }
   {
 #line 1481
   __cil_tmp15 = dev_priv->info;
 #line 1481
   __cil_tmp16 = __cil_tmp15->gen;
 #line 1481
   __cil_tmp17 = (unsigned char )__cil_tmp16;
 #line 1481
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 1481
   if (__cil_tmp18 == 3U) {
     {
 #line 1482
     i915_write32(dev_priv, 8384U, 134217728U);
     }
   } else {
 
   }
   }
   {
 #line 1483
   __cil_tmp19 = & dev_priv->irq_lock;
 #line 1483
   spin_unlock_irqrestore(__cil_tmp19, irqflags);
   }
 #line 1485
   return (0);
 }
 }
 #line 1488 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int ironlake_enable_vblank(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   int tmp ;
   raw_spinlock_t *tmp___0 ;
   unsigned int tmp___1 ;
   void *__cil_tmp8 ;
   spinlock_t *__cil_tmp9 ;
   spinlock_t *__cil_tmp10 ;
 
   {
   {
 #line 1490
   __cil_tmp8 = dev->dev_private;
 #line 1490
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 1493
   tmp = i915_pipe_enabled(dev, pipe);
   }
 #line 1493
   if (tmp == 0) {
 #line 1494
     return (-22);
   } else {
 
   }
   {
 #line 1496
   __cil_tmp9 = & dev_priv->irq_lock;
 #line 1496
   tmp___0 = spinlock_check(__cil_tmp9);
 #line 1496
   irqflags = _raw_spin_lock_irqsave(tmp___0);
   }
 #line 1497
   if (pipe == 0) {
 #line 1497
     tmp___1 = 128U;
   } else {
 #line 1497
     tmp___1 = 32768U;
   }
   {
 #line 1497
   ironlake_enable_display_irq(dev_priv, tmp___1);
 #line 1499
   __cil_tmp10 = & dev_priv->irq_lock;
 #line 1499
   spin_unlock_irqrestore(__cil_tmp10, irqflags);
   }
 #line 1501
   return (0);
 }
 }
 #line 1504 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int ivybridge_enable_vblank(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   int tmp ;
   raw_spinlock_t *tmp___0 ;
   unsigned int tmp___1 ;
   void *__cil_tmp8 ;
   spinlock_t *__cil_tmp9 ;
   spinlock_t *__cil_tmp10 ;
 
   {
   {
 #line 1506
   __cil_tmp8 = dev->dev_private;
 #line 1506
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 1509
   tmp = i915_pipe_enabled(dev, pipe);
   }
 #line 1509
   if (tmp == 0) {
 #line 1510
     return (-22);
   } else {
 
   }
   {
 #line 1512
   __cil_tmp9 = & dev_priv->irq_lock;
 #line 1512
   tmp___0 = spinlock_check(__cil_tmp9);
 #line 1512
   irqflags = _raw_spin_lock_irqsave(tmp___0);
   }
 #line 1513
   if (pipe == 0) {
 #line 1513
     tmp___1 = 1U;
   } else {
 #line 1513
     tmp___1 = 32U;
   }
   {
 #line 1513
   ironlake_enable_display_irq(dev_priv, tmp___1);
 #line 1515
   __cil_tmp10 = & dev_priv->irq_lock;
 #line 1515
   spin_unlock_irqrestore(__cil_tmp10, irqflags);
   }
 #line 1517
   return (0);
 }
 }
 #line 1523 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_disable_vblank(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   raw_spinlock_t *tmp ;
   void *__cil_tmp6 ;
   spinlock_t *__cil_tmp7 ;
   struct intel_device_info  const  *__cil_tmp8 ;
   u8 __cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   spinlock_t *__cil_tmp12 ;
 
   {
   {
 #line 1525
   __cil_tmp6 = dev->dev_private;
 #line 1525
   dev_priv = (drm_i915_private_t *)__cil_tmp6;
 #line 1528
   __cil_tmp7 = & dev_priv->irq_lock;
 #line 1528
   tmp = spinlock_check(__cil_tmp7);
 #line 1528
   irqflags = _raw_spin_lock_irqsave(tmp);
   }
   {
 #line 1529
   __cil_tmp8 = dev_priv->info;
 #line 1529
   __cil_tmp9 = __cil_tmp8->gen;
 #line 1529
   __cil_tmp10 = (unsigned char )__cil_tmp9;
 #line 1529
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 1529
   if (__cil_tmp11 == 3U) {
     {
 #line 1530
     i915_write32(dev_priv, 8384U, 134219776U);
     }
   } else {
 
   }
   }
   {
 #line 1533
   i915_disable_pipestat(dev_priv, pipe, 393216U);
 #line 1536
   __cil_tmp12 = & dev_priv->irq_lock;
 #line 1536
   spin_unlock_irqrestore(__cil_tmp12, irqflags);
   }
 #line 1537
   return;
 }
 }
 #line 1539 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void ironlake_disable_vblank(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   raw_spinlock_t *tmp ;
   unsigned int tmp___0 ;
   void *__cil_tmp7 ;
   spinlock_t *__cil_tmp8 ;
   spinlock_t *__cil_tmp9 ;
 
   {
   {
 #line 1541
   __cil_tmp7 = dev->dev_private;
 #line 1541
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 1544
   __cil_tmp8 = & dev_priv->irq_lock;
 #line 1544
   tmp = spinlock_check(__cil_tmp8);
 #line 1544
   irqflags = _raw_spin_lock_irqsave(tmp);
   }
 #line 1545
   if (pipe == 0) {
 #line 1545
     tmp___0 = 128U;
   } else {
 #line 1545
     tmp___0 = 32768U;
   }
   {
 #line 1545
   ironlake_disable_display_irq(dev_priv, tmp___0);
 #line 1547
   __cil_tmp9 = & dev_priv->irq_lock;
 #line 1547
   spin_unlock_irqrestore(__cil_tmp9, irqflags);
   }
 #line 1548
   return;
 }
 }
 #line 1550 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void ivybridge_disable_vblank(struct drm_device *dev , int pipe ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long irqflags ;
   raw_spinlock_t *tmp ;
   unsigned int tmp___0 ;
   void *__cil_tmp7 ;
   spinlock_t *__cil_tmp8 ;
   spinlock_t *__cil_tmp9 ;
 
   {
   {
 #line 1552
   __cil_tmp7 = dev->dev_private;
 #line 1552
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 1555
   __cil_tmp8 = & dev_priv->irq_lock;
 #line 1555
   tmp = spinlock_check(__cil_tmp8);
 #line 1555
   irqflags = _raw_spin_lock_irqsave(tmp);
   }
 #line 1556
   if (pipe == 0) {
 #line 1556
     tmp___0 = 1U;
   } else {
 #line 1556
     tmp___0 = 32U;
   }
   {
 #line 1556
   ironlake_disable_display_irq(dev_priv, tmp___0);
 #line 1558
   __cil_tmp9 = & dev_priv->irq_lock;
 #line 1558
   spin_unlock_irqrestore(__cil_tmp9, irqflags);
   }
 #line 1559
   return;
 }
 }
 #line 1563 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 int i915_vblank_pipe_set(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   void *__cil_tmp5 ;
   drm_i915_private_t *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
 
   {
 #line 1566
   __cil_tmp5 = dev->dev_private;
 #line 1566
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
   {
 #line 1568
   __cil_tmp6 = (drm_i915_private_t *)0;
 #line 1568
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 1568
   __cil_tmp8 = (unsigned long )dev_priv;
 #line 1568
   if (__cil_tmp8 == __cil_tmp7) {
     {
 #line 1569
     drm_err("i915_vblank_pipe_set", "called with no initialization\n");
     }
 #line 1570
     return (-22);
   } else {
 
   }
   }
 #line 1573
   return (0);
 }
 }
 #line 1576 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 int i915_vblank_pipe_get(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_vblank_pipe_t *pipe ;
   void *__cil_tmp6 ;
   drm_i915_private_t *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
 
   {
 #line 1579
   __cil_tmp6 = dev->dev_private;
 #line 1579
   dev_priv = (drm_i915_private_t *)__cil_tmp6;
 #line 1580
   pipe = (drm_i915_vblank_pipe_t *)data;
   {
 #line 1582
   __cil_tmp7 = (drm_i915_private_t *)0;
 #line 1582
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 1582
   __cil_tmp9 = (unsigned long )dev_priv;
 #line 1582
   if (__cil_tmp9 == __cil_tmp8) {
     {
 #line 1583
     drm_err("i915_vblank_pipe_get", "called with no initialization\n");
     }
 #line 1584
     return (-22);
   } else {
 
   }
   }
 #line 1587
   pipe->pipe = 3;
 #line 1589
   return (0);
 }
 }
 #line 1595 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 int i915_vblank_swap(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { 
 
   {
 #line 1612
   return (-22);
 }
 }
 #line 1616 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static u32 ring_last_seqno(struct intel_ring_buffer *ring ) 
 { struct list_head  const  *__mptr ;
   struct list_head *__cil_tmp3 ;
   struct drm_i915_gem_request *__cil_tmp4 ;
   struct drm_i915_gem_request *__cil_tmp5 ;
 
   {
 #line 1618
   __cil_tmp3 = ring->request_list.prev;
 #line 1618
   __mptr = (struct list_head  const  *)__cil_tmp3;
   {
 #line 1618
   __cil_tmp4 = (struct drm_i915_gem_request *)__mptr;
 #line 1618
   __cil_tmp5 = __cil_tmp4 + 1152921504606846952UL;
 #line 1618
   return (__cil_tmp5->seqno);
   }
 }
 }
 #line 1622 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring , bool *err ) 
 { u32 tmp ;
   int tmp___0 ;
   int tmp___1 ;
   u32 tmp___2 ;
   u32 tmp___3 ;
   bool tmp___4 ;
   struct list_head *__cil_tmp9 ;
   struct list_head  const  *__cil_tmp10 ;
   u32 (*__cil_tmp11)(struct intel_ring_buffer * ) ;
   u32 __cil_tmp12 ;
   wait_queue_head_t *__cil_tmp13 ;
   u32 (*__cil_tmp14)(struct intel_ring_buffer * ) ;
   char const   *__cil_tmp15 ;
   u32 __cil_tmp16 ;
   wait_queue_head_t *__cil_tmp17 ;
   void *__cil_tmp18 ;
 
   {
   {
 #line 1624
   __cil_tmp9 = & ring->request_list;
 #line 1624
   __cil_tmp10 = (struct list_head  const  *)__cil_tmp9;
 #line 1624
   tmp___1 = list_empty(__cil_tmp10);
   }
 #line 1624
   if (tmp___1 != 0) {
 #line 1624
     goto _L;
   } else {
     {
 #line 1624
     tmp___2 = ring_last_seqno(ring);
 #line 1624
     __cil_tmp11 = ring->get_seqno;
 #line 1624
     tmp___3 = (*__cil_tmp11)(ring);
 #line 1624
     tmp___4 = i915_seqno_passed(tmp___3, tmp___2);
     }
 #line 1624
     if ((int )tmp___4) {
       _L: 
       {
 #line 1627
       __cil_tmp12 = ring->waiting_seqno;
 #line 1627
       if (__cil_tmp12 != 0U) {
         {
 #line 1627
         __cil_tmp13 = & ring->irq_queue;
 #line 1627
         tmp___0 = waitqueue_active(__cil_tmp13);
         }
 #line 1627
         if (tmp___0 != 0) {
           {
 #line 1628
           __cil_tmp14 = ring->get_seqno;
 #line 1628
           tmp = (*__cil_tmp14)(ring);
 #line 1628
           __cil_tmp15 = ring->name;
 #line 1628
           __cil_tmp16 = ring->waiting_seqno;
 #line 1628
           drm_err("i915_hangcheck_ring_idle", "Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
                   __cil_tmp15, __cil_tmp16, tmp);
 #line 1632
           __cil_tmp17 = & ring->irq_queue;
 #line 1632
           __cil_tmp18 = (void *)0;
 #line 1632
           __wake_up(__cil_tmp17, 3U, 0, __cil_tmp18);
 #line 1633
           *err = (bool )1;
           }
         } else {
 
         }
       } else {
 
       }
       }
 #line 1635
       return ((bool )1);
     } else {
 
     }
   }
 #line 1637
   return ((bool )0);
 }
 }
 #line 1640 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static bool kick_ring(struct intel_ring_buffer *ring ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   u32 tmp ;
   u32 tmp___0 ;
   void *__cil_tmp6 ;
   u32 __cil_tmp7 ;
   u32 __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   char const   *__cil_tmp10 ;
   u32 __cil_tmp11 ;
   u32 __cil_tmp12 ;
   void *__cil_tmp13 ;
   struct drm_i915_private *__cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   u8 __cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   char const   *__cil_tmp20 ;
   u32 __cil_tmp21 ;
   u32 __cil_tmp22 ;
 
   {
   {
 #line 1642
   dev = ring->dev;
 #line 1643
   __cil_tmp6 = dev->dev_private;
 #line 1643
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
 #line 1644
   __cil_tmp7 = ring->mmio_base;
 #line 1644
   __cil_tmp8 = __cil_tmp7 + 60U;
 #line 1644
   tmp___0 = i915_read32(dev_priv, __cil_tmp8);
 #line 1644
   tmp = tmp___0;
   }
   {
 #line 1645
   __cil_tmp9 = tmp & 2048U;
 #line 1645
   if (__cil_tmp9 != 0U) {
     {
 #line 1646
     __cil_tmp10 = ring->name;
 #line 1646
     drm_err("kick_ring", "Kicking stuck wait on %s\n", __cil_tmp10);
 #line 1648
     __cil_tmp11 = ring->mmio_base;
 #line 1648
     __cil_tmp12 = __cil_tmp11 + 60U;
 #line 1648
     i915_write32(dev_priv, __cil_tmp12, tmp);
     }
 #line 1649
     return ((bool )1);
   } else {
 
   }
   }
   {
 #line 1651
   __cil_tmp13 = dev->dev_private;
 #line 1651
   __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
 #line 1651
   __cil_tmp15 = __cil_tmp14->info;
 #line 1651
   __cil_tmp16 = __cil_tmp15->gen;
 #line 1651
   __cil_tmp17 = (unsigned char )__cil_tmp16;
 #line 1651
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 1651
   if (__cil_tmp18 == 6U) {
     {
 #line 1651
     __cil_tmp19 = tmp & 1024U;
 #line 1651
     if (__cil_tmp19 != 0U) {
       {
 #line 1653
       __cil_tmp20 = ring->name;
 #line 1653
       drm_err("kick_ring", "Kicking stuck semaphore on %s\n", __cil_tmp20);
 #line 1655
       __cil_tmp21 = ring->mmio_base;
 #line 1655
       __cil_tmp22 = __cil_tmp21 + 60U;
 #line 1655
       i915_write32(dev_priv, __cil_tmp22, tmp);
       }
 #line 1656
       return ((bool )1);
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 1658
   return ((bool )0);
 }
 }
 #line 1667 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void i915_hangcheck_elapsed(unsigned long data ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   uint32_t acthd ;
   uint32_t instdone ;
   uint32_t instdone1 ;
   bool err ;
   bool tmp ;
   bool tmp___0 ;
   bool tmp___1 ;
   bool tmp___2 ;
   bool tmp___3 ;
   bool tmp___4 ;
   int tmp___5 ;
   unsigned long tmp___6 ;
   void *__cil_tmp16 ;
   struct intel_ring_buffer (*__cil_tmp17)[3U] ;
   struct intel_ring_buffer *__cil_tmp18 ;
   struct intel_ring_buffer (*__cil_tmp19)[3U] ;
   struct intel_ring_buffer *__cil_tmp20 ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
   struct intel_ring_buffer *__cil_tmp24 ;
   void *__cil_tmp25 ;
   struct drm_i915_private *__cil_tmp26 ;
   struct intel_device_info  const  *__cil_tmp27 ;
   u8 __cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   uint32_t __cil_tmp31 ;
   uint32_t __cil_tmp32 ;
   uint32_t __cil_tmp33 ;
   int __cil_tmp34 ;
   void *__cil_tmp35 ;
   struct drm_i915_private *__cil_tmp36 ;
   struct intel_device_info  const  *__cil_tmp37 ;
   u8 __cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   struct intel_ring_buffer (*__cil_tmp41)[3U] ;
   struct intel_ring_buffer *__cil_tmp42 ;
   void *__cil_tmp43 ;
   struct drm_i915_private *__cil_tmp44 ;
   struct intel_device_info  const  *__cil_tmp45 ;
   unsigned char *__cil_tmp46 ;
   unsigned char *__cil_tmp47 ;
   unsigned char __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   struct intel_ring_buffer (*__cil_tmp50)[3U] ;
   struct intel_ring_buffer *__cil_tmp51 ;
   struct intel_ring_buffer *__cil_tmp52 ;
   void *__cil_tmp53 ;
   struct drm_i915_private *__cil_tmp54 ;
   struct intel_device_info  const  *__cil_tmp55 ;
   unsigned char *__cil_tmp56 ;
   unsigned char *__cil_tmp57 ;
   unsigned char __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   struct intel_ring_buffer (*__cil_tmp60)[3U] ;
   struct intel_ring_buffer *__cil_tmp61 ;
   struct intel_ring_buffer *__cil_tmp62 ;
   bool __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   struct timer_list *__cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   unsigned long __cil_tmp68 ;
 
   {
   {
 #line 1669
   dev = (struct drm_device *)data;
 #line 1670
   __cil_tmp16 = dev->dev_private;
 #line 1670
   dev_priv = (drm_i915_private_t *)__cil_tmp16;
 #line 1672
   err = (bool )0;
 #line 1675
   __cil_tmp17 = & dev_priv->ring;
 #line 1675
   __cil_tmp18 = (struct intel_ring_buffer *)__cil_tmp17;
 #line 1675
   tmp = i915_hangcheck_ring_idle(__cil_tmp18, & err);
   }
 #line 1675
   if ((int )tmp) {
     {
 #line 1675
     __cil_tmp19 = & dev_priv->ring;
 #line 1675
     __cil_tmp20 = (struct intel_ring_buffer *)__cil_tmp19;
 #line 1675
     __cil_tmp21 = __cil_tmp20 + 1UL;
 #line 1675
     tmp___0 = i915_hangcheck_ring_idle(__cil_tmp21, & err);
     }
 #line 1675
     if ((int )tmp___0) {
       {
 #line 1675
       __cil_tmp22 = & dev_priv->ring;
 #line 1675
       __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 1675
       __cil_tmp24 = __cil_tmp23 + 2UL;
 #line 1675
       tmp___1 = i915_hangcheck_ring_idle(__cil_tmp24, & err);
       }
 #line 1675
       if ((int )tmp___1) {
 #line 1678
         dev_priv->hangcheck_count = 0;
 #line 1679
         if ((int )err) {
 #line 1680
           goto repeat;
         } else {
 
         }
 #line 1681
         return;
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 1684
   __cil_tmp25 = dev->dev_private;
 #line 1684
   __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
 #line 1684
   __cil_tmp27 = __cil_tmp26->info;
 #line 1684
   __cil_tmp28 = __cil_tmp27->gen;
 #line 1684
   __cil_tmp29 = (unsigned char )__cil_tmp28;
 #line 1684
   __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 1684
   if (__cil_tmp30 <= 3U) {
     {
 #line 1685
     acthd = i915_read32(dev_priv, 8392U);
 #line 1686
     instdone = i915_read32(dev_priv, 8336U);
 #line 1687
     instdone1 = 0U;
     }
   } else {
     {
 #line 1689
     acthd = i915_read32(dev_priv, 8308U);
 #line 1690
     instdone = i915_read32(dev_priv, 8300U);
 #line 1691
     instdone1 = i915_read32(dev_priv, 8316U);
     }
   }
   }
   {
 #line 1694
   __cil_tmp31 = dev_priv->last_acthd;
 #line 1694
   if (__cil_tmp31 == acthd) {
     {
 #line 1694
     __cil_tmp32 = dev_priv->last_instdone;
 #line 1694
     if (__cil_tmp32 == instdone) {
       {
 #line 1694
       __cil_tmp33 = dev_priv->last_instdone1;
 #line 1694
       if (__cil_tmp33 == instdone1) {
 #line 1697
         tmp___5 = dev_priv->hangcheck_count;
 #line 1697
         __cil_tmp34 = dev_priv->hangcheck_count;
 #line 1697
         dev_priv->hangcheck_count = __cil_tmp34 + 1;
 #line 1697
         if (tmp___5 > 1) {
           {
 #line 1698
           drm_err("i915_hangcheck_elapsed", "Hangcheck timer elapsed... GPU hung\n");
           }
           {
 #line 1700
           __cil_tmp35 = dev->dev_private;
 #line 1700
           __cil_tmp36 = (struct drm_i915_private *)__cil_tmp35;
 #line 1700
           __cil_tmp37 = __cil_tmp36->info;
 #line 1700
           __cil_tmp38 = __cil_tmp37->gen;
 #line 1700
           __cil_tmp39 = (unsigned char )__cil_tmp38;
 #line 1700
           __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 1700
           if (__cil_tmp40 != 2U) {
             {
 #line 1707
             __cil_tmp41 = & dev_priv->ring;
 #line 1707
             __cil_tmp42 = (struct intel_ring_buffer *)__cil_tmp41;
 #line 1707
             tmp___2 = kick_ring(__cil_tmp42);
             }
 #line 1707
             if ((int )tmp___2) {
 #line 1708
               goto repeat;
             } else {
 
             }
             {
 #line 1710
             __cil_tmp43 = dev->dev_private;
 #line 1710
             __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
 #line 1710
             __cil_tmp45 = __cil_tmp44->info;
 #line 1710
             __cil_tmp46 = (unsigned char *)__cil_tmp45;
 #line 1710
             __cil_tmp47 = __cil_tmp46 + 3UL;
 #line 1710
             __cil_tmp48 = *__cil_tmp47;
 #line 1710
             __cil_tmp49 = (unsigned int )__cil_tmp48;
 #line 1710
             if (__cil_tmp49 != 0U) {
               {
 #line 1710
               __cil_tmp50 = & dev_priv->ring;
 #line 1710
               __cil_tmp51 = (struct intel_ring_buffer *)__cil_tmp50;
 #line 1710
               __cil_tmp52 = __cil_tmp51 + 1UL;
 #line 1710
               tmp___3 = kick_ring(__cil_tmp52);
               }
 #line 1710
               if ((int )tmp___3) {
 #line 1712
                 goto repeat;
               } else {
 
               }
             } else {
 
             }
             }
             {
 #line 1714
             __cil_tmp53 = dev->dev_private;
 #line 1714
             __cil_tmp54 = (struct drm_i915_private *)__cil_tmp53;
 #line 1714
             __cil_tmp55 = __cil_tmp54->info;
 #line 1714
             __cil_tmp56 = (unsigned char *)__cil_tmp55;
 #line 1714
             __cil_tmp57 = __cil_tmp56 + 3UL;
 #line 1714
             __cil_tmp58 = *__cil_tmp57;
 #line 1714
             __cil_tmp59 = (unsigned int )__cil_tmp58;
 #line 1714
             if (__cil_tmp59 != 0U) {
               {
 #line 1714
               __cil_tmp60 = & dev_priv->ring;
 #line 1714
               __cil_tmp61 = (struct intel_ring_buffer *)__cil_tmp60;
 #line 1714
               __cil_tmp62 = __cil_tmp61 + 2UL;
 #line 1714
               tmp___4 = kick_ring(__cil_tmp62);
               }
 #line 1714
               if ((int )tmp___4) {
 #line 1716
                 goto repeat;
               } else {
 
               }
             } else {
 
             }
             }
           } else {
 
           }
           }
           {
 #line 1719
           __cil_tmp63 = (bool )1;
 #line 1719
           i915_handle_error(dev, __cil_tmp63);
           }
 #line 1720
           return;
         } else {
 #line 1723
           dev_priv->hangcheck_count = 0;
 #line 1725
           dev_priv->last_acthd = acthd;
 #line 1726
           dev_priv->last_instdone = instdone;
 #line 1727
           dev_priv->last_instdone1 = instdone1;
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   repeat: 
   {
 #line 1732
   __cil_tmp64 = (unsigned int const   )1500U;
 #line 1732
   __cil_tmp65 = (unsigned int )__cil_tmp64;
 #line 1732
   tmp___6 = msecs_to_jiffies(__cil_tmp65);
 #line 1732
   __cil_tmp66 = & dev_priv->hangcheck_timer;
 #line 1732
   __cil_tmp67 = (unsigned long )jiffies;
 #line 1732
   __cil_tmp68 = tmp___6 + __cil_tmp67;
 #line 1732
   mod_timer(__cil_tmp66, __cil_tmp68);
   }
 #line 1734
   return;
 }
 }
 #line 1738 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void ironlake_irq_preinstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   struct lock_class_key __key ;
   atomic_long_t __constr_expr_0 ;
   struct lock_class_key __key___0 ;
   atomic_long_t __constr_expr_1 ;
   struct lock_class_key __key___1 ;
   atomic_long_t __constr_expr_2 ;
   void *__cil_tmp9 ;
   atomic_t *__cil_tmp10 ;
   struct work_struct *__cil_tmp11 ;
   struct lockdep_map *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct work_struct *__cil_tmp14 ;
   struct lockdep_map *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   u8 __cil_tmp20 ;
   unsigned char __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   unsigned char *__cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   struct work_struct *__cil_tmp30 ;
   struct lockdep_map *__cil_tmp31 ;
   struct list_head *__cil_tmp32 ;
   void *__cil_tmp33 ;
   struct drm_i915_private *__cil_tmp34 ;
   struct intel_device_info  const  *__cil_tmp35 ;
   u8 __cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   void *__cil_tmp39 ;
   struct drm_i915_private *__cil_tmp40 ;
   struct intel_device_info  const  *__cil_tmp41 ;
   u8 __cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   void *__cil_tmp45 ;
   void const volatile   *__cil_tmp46 ;
   void const volatile   *__cil_tmp47 ;
   void *__cil_tmp48 ;
   void const volatile   *__cil_tmp49 ;
   void const volatile   *__cil_tmp50 ;
   void *__cil_tmp51 ;
   void const volatile   *__cil_tmp52 ;
   void const volatile   *__cil_tmp53 ;
 
   {
   {
 #line 1740
   __cil_tmp9 = dev->dev_private;
 #line 1740
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 1742
   __cil_tmp10 = & dev_priv->irq_received;
 #line 1742
   atomic_set(__cil_tmp10, 0);
 #line 1744
   __cil_tmp11 = & dev_priv->hotplug_work;
 #line 1744
   __init_work(__cil_tmp11, 0);
 #line 1744
   __constr_expr_0.counter = 2097664L;
 #line 1744
   dev_priv->hotplug_work.data = __constr_expr_0;
 #line 1744
   __cil_tmp12 = & dev_priv->hotplug_work.lockdep_map;
 #line 1744
   lockdep_init_map(__cil_tmp12, "(&dev_priv->hotplug_work)", & __key, 0);
 #line 1744
   __cil_tmp13 = & dev_priv->hotplug_work.entry;
 #line 1744
   INIT_LIST_HEAD(__cil_tmp13);
 #line 1744
   dev_priv->hotplug_work.func = & i915_hotplug_work_func;
 #line 1745
   __cil_tmp14 = & dev_priv->error_work;
 #line 1745
   __init_work(__cil_tmp14, 0);
 #line 1745
   __constr_expr_1.counter = 2097664L;
 #line 1745
   dev_priv->error_work.data = __constr_expr_1;
 #line 1745
   __cil_tmp15 = & dev_priv->error_work.lockdep_map;
 #line 1745
   lockdep_init_map(__cil_tmp15, "(&dev_priv->error_work)", & __key___0, 0);
 #line 1745
   __cil_tmp16 = & dev_priv->error_work.entry;
 #line 1745
   INIT_LIST_HEAD(__cil_tmp16);
 #line 1745
   dev_priv->error_work.func = & i915_error_work_func;
   }
   {
 #line 1746
   __cil_tmp17 = dev->dev_private;
 #line 1746
   __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 1746
   __cil_tmp19 = __cil_tmp18->info;
 #line 1746
   __cil_tmp20 = __cil_tmp19->gen;
 #line 1746
   __cil_tmp21 = (unsigned char )__cil_tmp20;
 #line 1746
   __cil_tmp22 = (unsigned int )__cil_tmp21;
 #line 1746
   if (__cil_tmp22 == 6U) {
 #line 1746
     goto _L;
   } else {
     {
 #line 1746
     __cil_tmp23 = dev->dev_private;
 #line 1746
     __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 1746
     __cil_tmp25 = __cil_tmp24->info;
 #line 1746
     __cil_tmp26 = (unsigned char *)__cil_tmp25;
 #line 1746
     __cil_tmp27 = __cil_tmp26 + 2UL;
 #line 1746
     __cil_tmp28 = *__cil_tmp27;
 #line 1746
     __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 1746
     if (__cil_tmp29 != 0U) {
       _L: 
       {
 #line 1747
       __cil_tmp30 = & dev_priv->rps_work;
 #line 1747
       __init_work(__cil_tmp30, 0);
 #line 1747
       __constr_expr_2.counter = 2097664L;
 #line 1747
       dev_priv->rps_work.data = __constr_expr_2;
 #line 1747
       __cil_tmp31 = & dev_priv->rps_work.lockdep_map;
 #line 1747
       lockdep_init_map(__cil_tmp31, "(&dev_priv->rps_work)", & __key___1, 0);
 #line 1747
       __cil_tmp32 = & dev_priv->rps_work.entry;
 #line 1747
       INIT_LIST_HEAD(__cil_tmp32);
 #line 1747
       dev_priv->rps_work.func = & gen6_pm_rps_work;
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 1749
   i915_write32(dev_priv, 8344U, 61438U);
   }
   {
 #line 1750
   __cil_tmp33 = dev->dev_private;
 #line 1750
   __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
 #line 1750
   __cil_tmp35 = __cil_tmp34->info;
 #line 1750
   __cil_tmp36 = __cil_tmp35->gen;
 #line 1750
   __cil_tmp37 = (unsigned char )__cil_tmp36;
 #line 1750
   __cil_tmp38 = (unsigned int )__cil_tmp37;
 #line 1750
   if (__cil_tmp38 == 6U) {
     {
 #line 1758
     i915_write32(dev_priv, 139416U, 4290772991U);
 #line 1759
     i915_write32(dev_priv, 73880U, 4294963199U);
     }
   } else {
     {
 #line 1750
     __cil_tmp39 = dev->dev_private;
 #line 1750
     __cil_tmp40 = (struct drm_i915_private *)__cil_tmp39;
 #line 1750
     __cil_tmp41 = __cil_tmp40->info;
 #line 1750
     __cil_tmp42 = __cil_tmp41->gen;
 #line 1750
     __cil_tmp43 = (unsigned char )__cil_tmp42;
 #line 1750
     __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 1750
     if (__cil_tmp44 == 7U) {
       {
 #line 1758
       i915_write32(dev_priv, 139416U, 4290772991U);
 #line 1759
       i915_write32(dev_priv, 73880U, 4294963199U);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 1764
   i915_write32(dev_priv, 278532U, 4294967295U);
 #line 1765
   i915_write32(dev_priv, 278540U, 0U);
 #line 1766
   __cil_tmp45 = dev_priv->regs;
 #line 1766
   __cil_tmp46 = (void const volatile   *)__cil_tmp45;
 #line 1766
   __cil_tmp47 = __cil_tmp46 + 278540U;
 #line 1766
   readl(__cil_tmp47);
 #line 1769
   i915_write32(dev_priv, 278548U, 4294967295U);
 #line 1770
   i915_write32(dev_priv, 278556U, 0U);
 #line 1771
   __cil_tmp48 = dev_priv->regs;
 #line 1771
   __cil_tmp49 = (void const volatile   *)__cil_tmp48;
 #line 1771
   __cil_tmp50 = __cil_tmp49 + 278556U;
 #line 1771
   readl(__cil_tmp50);
 #line 1774
   i915_write32(dev_priv, 802820U, 4294967295U);
 #line 1775
   i915_write32(dev_priv, 802828U, 0U);
 #line 1776
   __cil_tmp51 = dev_priv->regs;
 #line 1776
   __cil_tmp52 = (void const volatile   *)__cil_tmp51;
 #line 1776
   __cil_tmp53 = __cil_tmp52 + 802828U;
 #line 1776
   readl(__cil_tmp53);
   }
 #line 1777
   return;
 }
 }
 #line 1779 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int ironlake_irq_postinstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 display_mask ;
   u32 render_irqs ;
   u32 hotplug_mask ;
   struct lock_class_key __key ;
   struct lock_class_key __key___0 ;
   struct lock_class_key __key___1 ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp13 ;
   wait_queue_head_t *__cil_tmp14 ;
   void *__cil_tmp15 ;
   struct drm_i915_private *__cil_tmp16 ;
   struct intel_device_info  const  *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char *__cil_tmp19 ;
   unsigned char __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   wait_queue_head_t *__cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   unsigned char *__cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   wait_queue_head_t *__cil_tmp30 ;
   u32 __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   void *__cil_tmp33 ;
   void const volatile   *__cil_tmp34 ;
   void const volatile   *__cil_tmp35 ;
   u32 __cil_tmp36 ;
   void *__cil_tmp37 ;
   struct drm_i915_private *__cil_tmp38 ;
   struct intel_device_info  const  *__cil_tmp39 ;
   u8 __cil_tmp40 ;
   unsigned char __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   void *__cil_tmp43 ;
   void const volatile   *__cil_tmp44 ;
   void const volatile   *__cil_tmp45 ;
   void *__cil_tmp46 ;
   struct drm_i915_private *__cil_tmp47 ;
   enum intel_pch __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   u32 __cil_tmp50 ;
   void *__cil_tmp51 ;
   void const volatile   *__cil_tmp52 ;
   void const volatile   *__cil_tmp53 ;
   int __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
 
   {
   {
 #line 1781
   __cil_tmp13 = dev->dev_private;
 #line 1781
   dev_priv = (drm_i915_private_t *)__cil_tmp13;
 #line 1783
   display_mask = 2351169536U;
 #line 1788
   __cil_tmp14 = & dev_priv->ring[0].irq_queue;
 #line 1788
   __init_waitqueue_head(__cil_tmp14, & __key);
   }
   {
 #line 1789
   __cil_tmp15 = dev->dev_private;
 #line 1789
   __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
 #line 1789
   __cil_tmp17 = __cil_tmp16->info;
 #line 1789
   __cil_tmp18 = (unsigned char *)__cil_tmp17;
 #line 1789
   __cil_tmp19 = __cil_tmp18 + 3UL;
 #line 1789
   __cil_tmp20 = *__cil_tmp19;
 #line 1789
   __cil_tmp21 = (unsigned int )__cil_tmp20;
 #line 1789
   if (__cil_tmp21 != 0U) {
     {
 #line 1790
     __cil_tmp22 = & dev_priv->ring[1].irq_queue;
 #line 1790
     __init_waitqueue_head(__cil_tmp22, & __key___0);
     }
   } else {
 
   }
   }
   {
 #line 1791
   __cil_tmp23 = dev->dev_private;
 #line 1791
   __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 1791
   __cil_tmp25 = __cil_tmp24->info;
 #line 1791
   __cil_tmp26 = (unsigned char *)__cil_tmp25;
 #line 1791
   __cil_tmp27 = __cil_tmp26 + 3UL;
 #line 1791
   __cil_tmp28 = *__cil_tmp27;
 #line 1791
   __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 1791
   if (__cil_tmp29 != 0U) {
     {
 #line 1792
     __cil_tmp30 = & dev_priv->ring[2].irq_queue;
 #line 1792
     __init_waitqueue_head(__cil_tmp30, & __key___1);
     }
   } else {
 
   }
   }
   {
 #line 1794
   dev_priv->vblank_pipe = 3;
 #line 1795
   dev_priv->irq_mask = ~ display_mask;
 #line 1798
   tmp = i915_read32(dev_priv, 278536U);
 #line 1798
   i915_write32(dev_priv, 278536U, tmp);
 #line 1799
   __cil_tmp31 = dev_priv->irq_mask;
 #line 1799
   i915_write32(dev_priv, 278532U, __cil_tmp31);
 #line 1800
   __cil_tmp32 = display_mask | 32896U;
 #line 1800
   i915_write32(dev_priv, 278540U, __cil_tmp32);
 #line 1801
   __cil_tmp33 = dev_priv->regs;
 #line 1801
   __cil_tmp34 = (void const volatile   *)__cil_tmp33;
 #line 1801
   __cil_tmp35 = __cil_tmp34 + 278540U;
 #line 1801
   readl(__cil_tmp35);
 #line 1803
   dev_priv->gt_irq_mask = 4294967295U;
 #line 1805
   tmp___0 = i915_read32(dev_priv, 278552U);
 #line 1805
   i915_write32(dev_priv, 278552U, tmp___0);
 #line 1806
   __cil_tmp36 = dev_priv->gt_irq_mask;
 #line 1806
   i915_write32(dev_priv, 278548U, __cil_tmp36);
   }
   {
 #line 1808
   __cil_tmp37 = dev->dev_private;
 #line 1808
   __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
 #line 1808
   __cil_tmp39 = __cil_tmp38->info;
 #line 1808
   __cil_tmp40 = __cil_tmp39->gen;
 #line 1808
   __cil_tmp41 = (unsigned char )__cil_tmp40;
 #line 1808
   __cil_tmp42 = (unsigned int )__cil_tmp41;
 #line 1808
   if (__cil_tmp42 == 6U) {
 #line 1809
     render_irqs = 4198401U;
   } else {
 #line 1814
     render_irqs = 49U;
   }
   }
   {
 #line 1818
   i915_write32(dev_priv, 278556U, render_irqs);
 #line 1819
   __cil_tmp43 = dev_priv->regs;
 #line 1819
   __cil_tmp44 = (void const volatile   *)__cil_tmp43;
 #line 1819
   __cil_tmp45 = __cil_tmp44 + 278556U;
 #line 1819
   readl(__cil_tmp45);
   }
   {
 #line 1821
   __cil_tmp46 = dev->dev_private;
 #line 1821
   __cil_tmp47 = (struct drm_i915_private *)__cil_tmp46;
 #line 1821
   __cil_tmp48 = __cil_tmp47->pch_type;
 #line 1821
   __cil_tmp49 = (unsigned int )__cil_tmp48;
 #line 1821
   if (__cil_tmp49 == 1U) {
 #line 1822
     hotplug_mask = 15204352U;
   } else {
 #line 1827
     hotplug_mask = 61184U;
   }
   }
   {
 #line 1834
   dev_priv->pch_irq_mask = ~ hotplug_mask;
 #line 1836
   tmp___1 = i915_read32(dev_priv, 802824U);
 #line 1836
   i915_write32(dev_priv, 802824U, tmp___1);
 #line 1837
   __cil_tmp50 = dev_priv->pch_irq_mask;
 #line 1837
   i915_write32(dev_priv, 802820U, __cil_tmp50);
 #line 1838
   i915_write32(dev_priv, 802828U, hotplug_mask);
 #line 1839
   __cil_tmp51 = dev_priv->regs;
 #line 1839
   __cil_tmp52 = (void const volatile   *)__cil_tmp51;
 #line 1839
   __cil_tmp53 = __cil_tmp52 + 802828U;
 #line 1839
   readl(__cil_tmp53);
   }
   {
 #line 1841
   __cil_tmp54 = dev->pci_device;
 #line 1841
   if (__cil_tmp54 == 70) {
     {
 #line 1843
     i915_write32(dev_priv, 278536U, 33554432U);
 #line 1844
     tmp___2 = i915_read32(dev_priv, 278540U);
 #line 1844
     __cil_tmp55 = tmp___2 | 33554432U;
 #line 1844
     i915_write32(dev_priv, 278540U, __cil_tmp55);
 #line 1845
     ironlake_enable_display_irq(dev_priv, 33554432U);
     }
   } else {
 
   }
   }
 #line 1848
   return (0);
 }
 }
 #line 1851 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int ivybridge_irq_postinstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 display_mask ;
   u32 render_irqs ;
   u32 hotplug_mask ;
   struct lock_class_key __key ;
   struct lock_class_key __key___0 ;
   struct lock_class_key __key___1 ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp12 ;
   wait_queue_head_t *__cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   wait_queue_head_t *__cil_tmp21 ;
   void *__cil_tmp22 ;
   struct drm_i915_private *__cil_tmp23 ;
   struct intel_device_info  const  *__cil_tmp24 ;
   unsigned char *__cil_tmp25 ;
   unsigned char *__cil_tmp26 ;
   unsigned char __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   wait_queue_head_t *__cil_tmp29 ;
   u32 __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   void *__cil_tmp32 ;
   void const volatile   *__cil_tmp33 ;
   void const volatile   *__cil_tmp34 ;
   u32 __cil_tmp35 ;
   void *__cil_tmp36 ;
   void const volatile   *__cil_tmp37 ;
   void const volatile   *__cil_tmp38 ;
   u32 __cil_tmp39 ;
   void *__cil_tmp40 ;
   void const volatile   *__cil_tmp41 ;
   void const volatile   *__cil_tmp42 ;
 
   {
   {
 #line 1853
   __cil_tmp12 = dev->dev_private;
 #line 1853
   dev_priv = (drm_i915_private_t *)__cil_tmp12;
 #line 1855
   display_mask = 2952790280U;
 #line 1861
   __cil_tmp13 = & dev_priv->ring[0].irq_queue;
 #line 1861
   __init_waitqueue_head(__cil_tmp13, & __key);
   }
   {
 #line 1862
   __cil_tmp14 = dev->dev_private;
 #line 1862
   __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 1862
   __cil_tmp16 = __cil_tmp15->info;
 #line 1862
   __cil_tmp17 = (unsigned char *)__cil_tmp16;
 #line 1862
   __cil_tmp18 = __cil_tmp17 + 3UL;
 #line 1862
   __cil_tmp19 = *__cil_tmp18;
 #line 1862
   __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 1862
   if (__cil_tmp20 != 0U) {
     {
 #line 1863
     __cil_tmp21 = & dev_priv->ring[1].irq_queue;
 #line 1863
     __init_waitqueue_head(__cil_tmp21, & __key___0);
     }
   } else {
 
   }
   }
   {
 #line 1864
   __cil_tmp22 = dev->dev_private;
 #line 1864
   __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
 #line 1864
   __cil_tmp24 = __cil_tmp23->info;
 #line 1864
   __cil_tmp25 = (unsigned char *)__cil_tmp24;
 #line 1864
   __cil_tmp26 = __cil_tmp25 + 3UL;
 #line 1864
   __cil_tmp27 = *__cil_tmp26;
 #line 1864
   __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 1864
   if (__cil_tmp28 != 0U) {
     {
 #line 1865
     __cil_tmp29 = & dev_priv->ring[2].irq_queue;
 #line 1865
     __init_waitqueue_head(__cil_tmp29, & __key___1);
     }
   } else {
 
   }
   }
   {
 #line 1867
   dev_priv->vblank_pipe = 3;
 #line 1868
   dev_priv->irq_mask = ~ display_mask;
 #line 1871
   tmp = i915_read32(dev_priv, 278536U);
 #line 1871
   i915_write32(dev_priv, 278536U, tmp);
 #line 1872
   __cil_tmp30 = dev_priv->irq_mask;
 #line 1872
   i915_write32(dev_priv, 278532U, __cil_tmp30);
 #line 1873
   __cil_tmp31 = display_mask | 33U;
 #line 1873
   i915_write32(dev_priv, 278540U, __cil_tmp31);
 #line 1875
   __cil_tmp32 = dev_priv->regs;
 #line 1875
   __cil_tmp33 = (void const volatile   *)__cil_tmp32;
 #line 1875
   __cil_tmp34 = __cil_tmp33 + 278540U;
 #line 1875
   readl(__cil_tmp34);
 #line 1877
   dev_priv->gt_irq_mask = 4294967295U;
 #line 1879
   tmp___0 = i915_read32(dev_priv, 278552U);
 #line 1879
   i915_write32(dev_priv, 278552U, tmp___0);
 #line 1880
   __cil_tmp35 = dev_priv->gt_irq_mask;
 #line 1880
   i915_write32(dev_priv, 278548U, __cil_tmp35);
 #line 1882
   render_irqs = 4198401U;
 #line 1884
   i915_write32(dev_priv, 278556U, render_irqs);
 #line 1885
   __cil_tmp36 = dev_priv->regs;
 #line 1885
   __cil_tmp37 = (void const volatile   *)__cil_tmp36;
 #line 1885
   __cil_tmp38 = __cil_tmp37 + 278556U;
 #line 1885
   readl(__cil_tmp38);
 #line 1887
   hotplug_mask = 15204352U;
 #line 1891
   dev_priv->pch_irq_mask = ~ hotplug_mask;
 #line 1893
   tmp___1 = i915_read32(dev_priv, 802824U);
 #line 1893
   i915_write32(dev_priv, 802824U, tmp___1);
 #line 1894
   __cil_tmp39 = dev_priv->pch_irq_mask;
 #line 1894
   i915_write32(dev_priv, 802820U, __cil_tmp39);
 #line 1895
   i915_write32(dev_priv, 802828U, hotplug_mask);
 #line 1896
   __cil_tmp40 = dev_priv->regs;
 #line 1896
   __cil_tmp41 = (void const volatile   *)__cil_tmp40;
 #line 1896
   __cil_tmp42 = __cil_tmp41 + 802828U;
 #line 1896
   readl(__cil_tmp42);
   }
 #line 1898
   return (0);
 }
 }
 #line 1901 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_driver_irq_preinstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int pipe ;
   struct lock_class_key __key ;
   atomic_long_t __constr_expr_0 ;
   struct lock_class_key __key___0 ;
   atomic_long_t __constr_expr_1 ;
   u32 tmp ;
   void *__cil_tmp9 ;
   atomic_t *__cil_tmp10 ;
   struct work_struct *__cil_tmp11 ;
   struct lockdep_map *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct work_struct *__cil_tmp14 ;
   struct lockdep_map *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   u32 __cil_tmp26 ;
   int __cil_tmp27 ;
   void *__cil_tmp28 ;
   void const volatile   *__cil_tmp29 ;
   void const volatile   *__cil_tmp30 ;
 
   {
   {
 #line 1903
   __cil_tmp9 = dev->dev_private;
 #line 1903
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 1906
   __cil_tmp10 = & dev_priv->irq_received;
 #line 1906
   atomic_set(__cil_tmp10, 0);
 #line 1908
   __cil_tmp11 = & dev_priv->hotplug_work;
 #line 1908
   __init_work(__cil_tmp11, 0);
 #line 1908
   __constr_expr_0.counter = 2097664L;
 #line 1908
   dev_priv->hotplug_work.data = __constr_expr_0;
 #line 1908
   __cil_tmp12 = & dev_priv->hotplug_work.lockdep_map;
 #line 1908
   lockdep_init_map(__cil_tmp12, "(&dev_priv->hotplug_work)", & __key, 0);
 #line 1908
   __cil_tmp13 = & dev_priv->hotplug_work.entry;
 #line 1908
   INIT_LIST_HEAD(__cil_tmp13);
 #line 1908
   dev_priv->hotplug_work.func = & i915_hotplug_work_func;
 #line 1909
   __cil_tmp14 = & dev_priv->error_work;
 #line 1909
   __init_work(__cil_tmp14, 0);
 #line 1909
   __constr_expr_1.counter = 2097664L;
 #line 1909
   dev_priv->error_work.data = __constr_expr_1;
 #line 1909
   __cil_tmp15 = & dev_priv->error_work.lockdep_map;
 #line 1909
   lockdep_init_map(__cil_tmp15, "(&dev_priv->error_work)", & __key___0, 0);
 #line 1909
   __cil_tmp16 = & dev_priv->error_work.entry;
 #line 1909
   INIT_LIST_HEAD(__cil_tmp16);
 #line 1909
   dev_priv->error_work.func = & i915_error_work_func;
   }
   {
 #line 1911
   __cil_tmp17 = dev->dev_private;
 #line 1911
   __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 1911
   __cil_tmp19 = __cil_tmp18->info;
 #line 1911
   __cil_tmp20 = (unsigned char *)__cil_tmp19;
 #line 1911
   __cil_tmp21 = __cil_tmp20 + 2UL;
 #line 1911
   __cil_tmp22 = *__cil_tmp21;
 #line 1911
   __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 1911
   if (__cil_tmp23 != 0U) {
     {
 #line 1912
     i915_write32(dev_priv, 397584U, 0U);
 #line 1913
     tmp = i915_read32(dev_priv, 397588U);
 #line 1913
     i915_write32(dev_priv, 397588U, tmp);
     }
   } else {
 
   }
   }
   {
 #line 1916
   i915_write32(dev_priv, 8344U, 61438U);
 #line 1917
   pipe = 0;
   }
 #line 1917
   goto ldv_38151;
   ldv_38150: 
   {
 #line 1918
   __cil_tmp24 = pipe * 4096;
 #line 1918
   __cil_tmp25 = __cil_tmp24 + 458788;
 #line 1918
   __cil_tmp26 = (u32 )__cil_tmp25;
 #line 1918
   i915_write32(dev_priv, __cil_tmp26, 0U);
 #line 1917
   pipe = pipe + 1;
   }
   ldv_38151: ;
   {
 #line 1917
   __cil_tmp27 = dev_priv->num_pipe;
 #line 1917
   if (__cil_tmp27 > pipe) {
 #line 1918
     goto ldv_38150;
   } else {
 #line 1920
     goto ldv_38152;
   }
   }
   ldv_38152: 
   {
 #line 1919
   i915_write32(dev_priv, 8360U, 4294967295U);
 #line 1920
   i915_write32(dev_priv, 8352U, 0U);
 #line 1921
   __cil_tmp28 = dev_priv->regs;
 #line 1921
   __cil_tmp29 = (void const volatile   *)__cil_tmp28;
 #line 1921
   __cil_tmp30 = __cil_tmp29 + 8352U;
 #line 1921
   readl(__cil_tmp30);
   }
 #line 1922
   return;
 }
 }
 #line 1928 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static int i915_driver_irq_postinstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 enable_mask ;
   u32 error_mask ;
   u32 hotplug_en ;
   u32 tmp ;
   void *__cil_tmp7 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   unsigned char *__cil_tmp11 ;
   unsigned char *__cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   u32 __cil_tmp15 ;
   void *__cil_tmp16 ;
   struct drm_i915_private *__cil_tmp17 ;
   struct intel_device_info  const  *__cil_tmp18 ;
   unsigned char *__cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   u32 __cil_tmp23 ;
   void *__cil_tmp24 ;
   void const volatile   *__cil_tmp25 ;
   void const volatile   *__cil_tmp26 ;
   void *__cil_tmp27 ;
   struct drm_i915_private *__cil_tmp28 ;
   struct intel_device_info  const  *__cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   u32 __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   u32 __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   u32 __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   void *__cil_tmp46 ;
   struct drm_i915_private *__cil_tmp47 ;
   struct intel_device_info  const  *__cil_tmp48 ;
   unsigned char *__cil_tmp49 ;
   unsigned char *__cil_tmp50 ;
   unsigned char __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
 
   {
 #line 1930
   __cil_tmp7 = dev->dev_private;
 #line 1930
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 1931
   enable_mask = 33590355U;
 #line 1934
   dev_priv->vblank_pipe = 3;
 #line 1937
   dev_priv->irq_mask = 4294931374U;
 #line 1939
   dev_priv->pipestat[0] = 0U;
 #line 1940
   dev_priv->pipestat[1] = 0U;
   {
 #line 1942
   __cil_tmp8 = dev->dev_private;
 #line 1942
   __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 1942
   __cil_tmp10 = __cil_tmp9->info;
 #line 1942
   __cil_tmp11 = (unsigned char *)__cil_tmp10;
 #line 1942
   __cil_tmp12 = __cil_tmp11 + 2UL;
 #line 1942
   __cil_tmp13 = *__cil_tmp12;
 #line 1942
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 1942
   if (__cil_tmp14 != 0U) {
 #line 1944
     enable_mask = enable_mask | 131072U;
 #line 1946
     __cil_tmp15 = dev_priv->irq_mask;
 #line 1946
     dev_priv->irq_mask = __cil_tmp15 & 4294836223U;
   } else {
 
   }
   }
   {
 #line 1953
   __cil_tmp16 = dev->dev_private;
 #line 1953
   __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
 #line 1953
   __cil_tmp18 = __cil_tmp17->info;
 #line 1953
   __cil_tmp19 = (unsigned char *)__cil_tmp18;
 #line 1953
   __cil_tmp20 = __cil_tmp19 + 1UL;
 #line 1953
   __cil_tmp21 = *__cil_tmp20;
 #line 1953
   __cil_tmp22 = (unsigned int )__cil_tmp21;
 #line 1953
   if (__cil_tmp22 != 0U) {
 #line 1954
     error_mask = 4294967237U;
   } else {
 #line 1959
     error_mask = 4294967277U;
   }
   }
   {
 #line 1962
   i915_write32(dev_priv, 8372U, error_mask);
 #line 1964
   __cil_tmp23 = dev_priv->irq_mask;
 #line 1964
   i915_write32(dev_priv, 8360U, __cil_tmp23);
 #line 1965
   i915_write32(dev_priv, 8352U, enable_mask);
 #line 1966
   __cil_tmp24 = dev_priv->regs;
 #line 1966
   __cil_tmp25 = (void const volatile   *)__cil_tmp24;
 #line 1966
   __cil_tmp26 = __cil_tmp25 + 8352U;
 #line 1966
   readl(__cil_tmp26);
   }
   {
 #line 1968
   __cil_tmp27 = dev->dev_private;
 #line 1968
   __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
 #line 1968
   __cil_tmp29 = __cil_tmp28->info;
 #line 1968
   __cil_tmp30 = (unsigned char *)__cil_tmp29;
 #line 1968
   __cil_tmp31 = __cil_tmp30 + 2UL;
 #line 1968
   __cil_tmp32 = *__cil_tmp31;
 #line 1968
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 1968
   if (__cil_tmp33 != 0U) {
     {
 #line 1969
     tmp = i915_read32(dev_priv, 397584U);
 #line 1969
     hotplug_en = tmp;
     }
     {
 #line 1972
     __cil_tmp34 = dev_priv->hotplug_supported_mask;
 #line 1972
     __cil_tmp35 = __cil_tmp34 & 536870912U;
 #line 1972
     if (__cil_tmp35 != 0U) {
 #line 1973
       hotplug_en = hotplug_en | 536870912U;
     } else {
 
     }
     }
     {
 #line 1974
     __cil_tmp36 = dev_priv->hotplug_supported_mask;
 #line 1974
     __cil_tmp37 = __cil_tmp36 & 268435456U;
 #line 1974
     if (__cil_tmp37 != 0U) {
 #line 1975
       hotplug_en = hotplug_en | 268435456U;
     } else {
 
     }
     }
     {
 #line 1976
     __cil_tmp38 = dev_priv->hotplug_supported_mask;
 #line 1976
     __cil_tmp39 = __cil_tmp38 & 134217728U;
 #line 1976
     if (__cil_tmp39 != 0U) {
 #line 1977
       hotplug_en = hotplug_en | 134217728U;
     } else {
 
     }
     }
     {
 #line 1978
     __cil_tmp40 = dev_priv->hotplug_supported_mask;
 #line 1978
     __cil_tmp41 = __cil_tmp40 & 128U;
 #line 1978
     if (__cil_tmp41 != 0U) {
 #line 1979
       hotplug_en = hotplug_en | 33554432U;
     } else {
 
     }
     }
     {
 #line 1980
     __cil_tmp42 = dev_priv->hotplug_supported_mask;
 #line 1980
     __cil_tmp43 = __cil_tmp42 & 64U;
 #line 1980
     if (__cil_tmp43 != 0U) {
 #line 1981
       hotplug_en = hotplug_en | 67108864U;
     } else {
 
     }
     }
     {
 #line 1982
     __cil_tmp44 = dev_priv->hotplug_supported_mask;
 #line 1982
     __cil_tmp45 = __cil_tmp44 & 2048U;
 #line 1982
     if (__cil_tmp45 != 0U) {
 #line 1983
       hotplug_en = hotplug_en | 512U;
       {
 #line 1989
       __cil_tmp46 = dev->dev_private;
 #line 1989
       __cil_tmp47 = (struct drm_i915_private *)__cil_tmp46;
 #line 1989
       __cil_tmp48 = __cil_tmp47->info;
 #line 1989
       __cil_tmp49 = (unsigned char *)__cil_tmp48;
 #line 1989
       __cil_tmp50 = __cil_tmp49 + 1UL;
 #line 1989
       __cil_tmp51 = *__cil_tmp50;
 #line 1989
       __cil_tmp52 = (unsigned int )__cil_tmp51;
 #line 1989
       if (__cil_tmp52 != 0U) {
 #line 1990
         hotplug_en = hotplug_en | 256U;
       } else {
 
       }
       }
 #line 1991
       hotplug_en = hotplug_en | 32U;
     } else {
 
     }
     }
     {
 #line 1996
     i915_write32(dev_priv, 397584U, hotplug_en);
     }
   } else {
 
   }
   }
   {
 #line 1999
   intel_opregion_enable_asle(dev);
   }
 #line 2001
   return (0);
 }
 }
 #line 2004 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void ironlake_irq_uninstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   u32 tmp ;
   u32 tmp___0 ;
   void *__cil_tmp5 ;
   drm_i915_private_t *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
 
   {
 #line 2006
   __cil_tmp5 = dev->dev_private;
 #line 2006
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
   {
 #line 2008
   __cil_tmp6 = (drm_i915_private_t *)0;
 #line 2008
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 2008
   __cil_tmp8 = (unsigned long )dev_priv;
 #line 2008
   if (__cil_tmp8 == __cil_tmp7) {
 #line 2009
     return;
   } else {
 
   }
   }
   {
 #line 2011
   dev_priv->vblank_pipe = 0;
 #line 2013
   i915_write32(dev_priv, 8344U, 4294967295U);
 #line 2015
   i915_write32(dev_priv, 278532U, 4294967295U);
 #line 2016
   i915_write32(dev_priv, 278540U, 0U);
 #line 2017
   tmp = i915_read32(dev_priv, 278536U);
 #line 2017
   i915_write32(dev_priv, 278536U, tmp);
 #line 2019
   i915_write32(dev_priv, 278548U, 4294967295U);
 #line 2020
   i915_write32(dev_priv, 278556U, 0U);
 #line 2021
   tmp___0 = i915_read32(dev_priv, 278552U);
 #line 2021
   i915_write32(dev_priv, 278552U, tmp___0);
   }
 #line 2022
   return;
 }
 }
 #line 2024 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 static void i915_driver_irq_uninstall(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int pipe ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp7 ;
   drm_i915_private_t *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   u32 __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   u32 __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   u32 __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
 
   {
 #line 2026
   __cil_tmp7 = dev->dev_private;
 #line 2026
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
   {
 #line 2029
   __cil_tmp8 = (drm_i915_private_t *)0;
 #line 2029
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 2029
   __cil_tmp10 = (unsigned long )dev_priv;
 #line 2029
   if (__cil_tmp10 == __cil_tmp9) {
 #line 2030
     return;
   } else {
 
   }
   }
 #line 2032
   dev_priv->vblank_pipe = 0;
   {
 #line 2034
   __cil_tmp11 = dev->dev_private;
 #line 2034
   __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 2034
   __cil_tmp13 = __cil_tmp12->info;
 #line 2034
   __cil_tmp14 = (unsigned char *)__cil_tmp13;
 #line 2034
   __cil_tmp15 = __cil_tmp14 + 2UL;
 #line 2034
   __cil_tmp16 = *__cil_tmp15;
 #line 2034
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 2034
   if (__cil_tmp17 != 0U) {
     {
 #line 2035
     i915_write32(dev_priv, 397584U, 0U);
 #line 2036
     tmp = i915_read32(dev_priv, 397588U);
 #line 2036
     i915_write32(dev_priv, 397588U, tmp);
     }
   } else {
 
   }
   }
   {
 #line 2039
   i915_write32(dev_priv, 8344U, 4294967295U);
 #line 2040
   pipe = 0;
   }
 #line 2040
   goto ldv_38170;
   ldv_38169: 
   {
 #line 2041
   __cil_tmp18 = pipe * 4096;
 #line 2041
   __cil_tmp19 = __cil_tmp18 + 458788;
 #line 2041
   __cil_tmp20 = (u32 )__cil_tmp19;
 #line 2041
   i915_write32(dev_priv, __cil_tmp20, 0U);
 #line 2040
   pipe = pipe + 1;
   }
   ldv_38170: ;
   {
 #line 2040
   __cil_tmp21 = dev_priv->num_pipe;
 #line 2040
   if (__cil_tmp21 > pipe) {
 #line 2041
     goto ldv_38169;
   } else {
 #line 2043
     goto ldv_38171;
   }
   }
   ldv_38171: 
   {
 #line 2042
   i915_write32(dev_priv, 8360U, 4294967295U);
 #line 2043
   i915_write32(dev_priv, 8352U, 0U);
 #line 2045
   pipe = 0;
   }
 #line 2045
   goto ldv_38173;
   ldv_38172: 
   {
 #line 2046
   __cil_tmp22 = pipe * 4096;
 #line 2046
   __cil_tmp23 = __cil_tmp22 + 458788;
 #line 2046
   __cil_tmp24 = (u32 )__cil_tmp23;
 #line 2046
   tmp___0 = i915_read32(dev_priv, __cil_tmp24);
 #line 2046
   __cil_tmp25 = pipe * 4096;
 #line 2046
   __cil_tmp26 = __cil_tmp25 + 458788;
 #line 2046
   __cil_tmp27 = (u32 )__cil_tmp26;
 #line 2046
   __cil_tmp28 = tmp___0 & 2147549183U;
 #line 2046
   i915_write32(dev_priv, __cil_tmp27, __cil_tmp28);
 #line 2045
   pipe = pipe + 1;
   }
   ldv_38173: ;
   {
 #line 2045
   __cil_tmp29 = dev_priv->num_pipe;
 #line 2045
   if (__cil_tmp29 > pipe) {
 #line 2046
     goto ldv_38172;
   } else {
 #line 2048
     goto ldv_38174;
   }
   }
   ldv_38174: 
   {
 #line 2048
   tmp___1 = i915_read32(dev_priv, 8356U);
 #line 2048
   i915_write32(dev_priv, 8356U, tmp___1);
   }
 #line 2049
   return;
 }
 }
 #line 2051 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_irq.c.p"
 void intel_irq_init(struct drm_device *dev ) 
 { struct drm_driver *__cil_tmp2 ;
   void *__cil_tmp3 ;
   struct drm_i915_private *__cil_tmp4 ;
   struct intel_device_info  const  *__cil_tmp5 ;
   unsigned char *__cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   struct drm_driver *__cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   struct drm_driver *__cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   u8 __cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   struct drm_driver *__cil_tmp24 ;
   void *__cil_tmp25 ;
   struct drm_i915_private *__cil_tmp26 ;
   struct intel_device_info  const  *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char *__cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   struct drm_driver *__cil_tmp32 ;
   struct drm_driver *__cil_tmp33 ;
   struct drm_driver *__cil_tmp34 ;
   void *__cil_tmp35 ;
   struct drm_i915_private *__cil_tmp36 ;
   struct intel_device_info  const  *__cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct drm_driver *__cil_tmp42 ;
   struct drm_driver *__cil_tmp43 ;
   struct drm_driver *__cil_tmp44 ;
   struct drm_driver *__cil_tmp45 ;
   struct drm_driver *__cil_tmp46 ;
   struct drm_driver *__cil_tmp47 ;
   void *__cil_tmp48 ;
   struct drm_i915_private *__cil_tmp49 ;
   struct intel_device_info  const  *__cil_tmp50 ;
   u8 __cil_tmp51 ;
   unsigned char __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   void *__cil_tmp54 ;
   struct drm_i915_private *__cil_tmp55 ;
   struct intel_device_info  const  *__cil_tmp56 ;
   u8 __cil_tmp57 ;
   unsigned char __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   void *__cil_tmp60 ;
   struct drm_i915_private *__cil_tmp61 ;
   struct intel_device_info  const  *__cil_tmp62 ;
   unsigned char *__cil_tmp63 ;
   unsigned char *__cil_tmp64 ;
   unsigned char __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   struct drm_driver *__cil_tmp67 ;
   struct drm_driver *__cil_tmp68 ;
   struct drm_driver *__cil_tmp69 ;
   struct drm_driver *__cil_tmp70 ;
   struct drm_driver *__cil_tmp71 ;
   struct drm_driver *__cil_tmp72 ;
   struct drm_driver *__cil_tmp73 ;
   struct drm_driver *__cil_tmp74 ;
   struct drm_driver *__cil_tmp75 ;
   struct drm_driver *__cil_tmp76 ;
   struct drm_driver *__cil_tmp77 ;
   struct drm_driver *__cil_tmp78 ;
 
   {
 #line 2053
   __cil_tmp2 = dev->driver;
 #line 2053
   __cil_tmp2->get_vblank_counter = & i915_get_vblank_counter;
 #line 2054
   dev->max_vblank_count = 16777215U;
   {
 #line 2055
   __cil_tmp3 = dev->dev_private;
 #line 2055
   __cil_tmp4 = (struct drm_i915_private *)__cil_tmp3;
 #line 2055
   __cil_tmp5 = __cil_tmp4->info;
 #line 2055
   __cil_tmp6 = (unsigned char *)__cil_tmp5;
 #line 2055
   __cil_tmp7 = __cil_tmp6 + 1UL;
 #line 2055
   __cil_tmp8 = *__cil_tmp7;
 #line 2055
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 2055
   if (__cil_tmp9 != 0U) {
 #line 2056
     dev->max_vblank_count = 4294967295U;
 #line 2057
     __cil_tmp10 = dev->driver;
 #line 2057
     __cil_tmp10->get_vblank_counter = & gm45_get_vblank_counter;
   } else {
     {
 #line 2055
     __cil_tmp11 = dev->dev_private;
 #line 2055
     __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 2055
     __cil_tmp13 = __cil_tmp12->info;
 #line 2055
     __cil_tmp14 = __cil_tmp13->gen;
 #line 2055
     __cil_tmp15 = (unsigned char )__cil_tmp14;
 #line 2055
     __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 2055
     if (__cil_tmp16 == 5U) {
 #line 2056
       dev->max_vblank_count = 4294967295U;
 #line 2057
       __cil_tmp17 = dev->driver;
 #line 2057
       __cil_tmp17->get_vblank_counter = & gm45_get_vblank_counter;
     } else {
       {
 #line 2055
       __cil_tmp18 = dev->dev_private;
 #line 2055
       __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 2055
       __cil_tmp20 = __cil_tmp19->info;
 #line 2055
       __cil_tmp21 = __cil_tmp20->gen;
 #line 2055
       __cil_tmp22 = (unsigned char )__cil_tmp21;
 #line 2055
       __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 2055
       if (__cil_tmp23 == 6U) {
 #line 2056
         dev->max_vblank_count = 4294967295U;
 #line 2057
         __cil_tmp24 = dev->driver;
 #line 2057
         __cil_tmp24->get_vblank_counter = & gm45_get_vblank_counter;
       } else {
         {
 #line 2055
         __cil_tmp25 = dev->dev_private;
 #line 2055
         __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
 #line 2055
         __cil_tmp27 = __cil_tmp26->info;
 #line 2055
         __cil_tmp28 = (unsigned char *)__cil_tmp27;
 #line 2055
         __cil_tmp29 = __cil_tmp28 + 2UL;
 #line 2055
         __cil_tmp30 = *__cil_tmp29;
 #line 2055
         __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 2055
         if (__cil_tmp31 != 0U) {
 #line 2056
           dev->max_vblank_count = 4294967295U;
 #line 2057
           __cil_tmp32 = dev->driver;
 #line 2057
           __cil_tmp32->get_vblank_counter = & gm45_get_vblank_counter;
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
 #line 2061
   __cil_tmp33 = dev->driver;
 #line 2061
   __cil_tmp33->get_vblank_timestamp = & i915_get_vblank_timestamp;
 #line 2062
   __cil_tmp34 = dev->driver;
 #line 2062
   __cil_tmp34->get_scanout_position = & i915_get_crtc_scanoutpos;
   {
 #line 2064
   __cil_tmp35 = dev->dev_private;
 #line 2064
   __cil_tmp36 = (struct drm_i915_private *)__cil_tmp35;
 #line 2064
   __cil_tmp37 = __cil_tmp36->info;
 #line 2064
   __cil_tmp38 = (unsigned char *)__cil_tmp37;
 #line 2064
   __cil_tmp39 = __cil_tmp38 + 2UL;
 #line 2064
   __cil_tmp40 = *__cil_tmp39;
 #line 2064
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 2064
   if (__cil_tmp41 != 0U) {
 #line 2066
     __cil_tmp42 = dev->driver;
 #line 2066
     __cil_tmp42->irq_handler = & ivybridge_irq_handler;
 #line 2067
     __cil_tmp43 = dev->driver;
 #line 2067
     __cil_tmp43->irq_preinstall = & ironlake_irq_preinstall;
 #line 2068
     __cil_tmp44 = dev->driver;
 #line 2068
     __cil_tmp44->irq_postinstall = & ivybridge_irq_postinstall;
 #line 2069
     __cil_tmp45 = dev->driver;
 #line 2069
     __cil_tmp45->irq_uninstall = & ironlake_irq_uninstall;
 #line 2070
     __cil_tmp46 = dev->driver;
 #line 2070
     __cil_tmp46->enable_vblank = & ivybridge_enable_vblank;
 #line 2071
     __cil_tmp47 = dev->driver;
 #line 2071
     __cil_tmp47->disable_vblank = & ivybridge_disable_vblank;
   } else {
     {
 #line 2072
     __cil_tmp48 = dev->dev_private;
 #line 2072
     __cil_tmp49 = (struct drm_i915_private *)__cil_tmp48;
 #line 2072
     __cil_tmp50 = __cil_tmp49->info;
 #line 2072
     __cil_tmp51 = __cil_tmp50->gen;
 #line 2072
     __cil_tmp52 = (unsigned char )__cil_tmp51;
 #line 2072
     __cil_tmp53 = (unsigned int )__cil_tmp52;
 #line 2072
     if (__cil_tmp53 == 5U) {
 #line 2072
       goto _L;
     } else {
       {
 #line 2072
       __cil_tmp54 = dev->dev_private;
 #line 2072
       __cil_tmp55 = (struct drm_i915_private *)__cil_tmp54;
 #line 2072
       __cil_tmp56 = __cil_tmp55->info;
 #line 2072
       __cil_tmp57 = __cil_tmp56->gen;
 #line 2072
       __cil_tmp58 = (unsigned char )__cil_tmp57;
 #line 2072
       __cil_tmp59 = (unsigned int )__cil_tmp58;
 #line 2072
       if (__cil_tmp59 == 6U) {
 #line 2072
         goto _L;
       } else {
         {
 #line 2072
         __cil_tmp60 = dev->dev_private;
 #line 2072
         __cil_tmp61 = (struct drm_i915_private *)__cil_tmp60;
 #line 2072
         __cil_tmp62 = __cil_tmp61->info;
 #line 2072
         __cil_tmp63 = (unsigned char *)__cil_tmp62;
 #line 2072
         __cil_tmp64 = __cil_tmp63 + 2UL;
 #line 2072
         __cil_tmp65 = *__cil_tmp64;
 #line 2072
         __cil_tmp66 = (unsigned int )__cil_tmp65;
 #line 2072
         if (__cil_tmp66 != 0U) {
           _L: 
 #line 2073
           __cil_tmp67 = dev->driver;
 #line 2073
           __cil_tmp67->irq_handler = & ironlake_irq_handler;
 #line 2074
           __cil_tmp68 = dev->driver;
 #line 2074
           __cil_tmp68->irq_preinstall = & ironlake_irq_preinstall;
 #line 2075
           __cil_tmp69 = dev->driver;
 #line 2075
           __cil_tmp69->irq_postinstall = & ironlake_irq_postinstall;
 #line 2076
           __cil_tmp70 = dev->driver;
 #line 2076
           __cil_tmp70->irq_uninstall = & ironlake_irq_uninstall;
 #line 2077
           __cil_tmp71 = dev->driver;
 #line 2077
           __cil_tmp71->enable_vblank = & ironlake_enable_vblank;
 #line 2078
           __cil_tmp72 = dev->driver;
 #line 2078
           __cil_tmp72->disable_vblank = & ironlake_disable_vblank;
         } else {
 #line 2080
           __cil_tmp73 = dev->driver;
 #line 2080
           __cil_tmp73->irq_preinstall = & i915_driver_irq_preinstall;
 #line 2081
           __cil_tmp74 = dev->driver;
 #line 2081
           __cil_tmp74->irq_postinstall = & i915_driver_irq_postinstall;
 #line 2082
           __cil_tmp75 = dev->driver;
 #line 2082
           __cil_tmp75->irq_uninstall = & i915_driver_irq_uninstall;
 #line 2083
           __cil_tmp76 = dev->driver;
 #line 2083
           __cil_tmp76->irq_handler = & i915_driver_irq_handler;
 #line 2084
           __cil_tmp77 = dev->driver;
 #line 2084
           __cil_tmp77->enable_vblank = & i915_enable_vblank;
 #line 2085
           __cil_tmp78 = dev->driver;
 #line 2085
           __cil_tmp78->disable_vblank = & i915_disable_vblank;
         }
         }
       }
       }
     }
     }
   }
   }
 #line 2087
   return;
 }
 }
 #line 53 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static void mark_block(struct drm_device *dev , struct mem_block *p , int in_use ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   drm_i915_sarea_t *sarea_priv ;
   struct drm_tex_region *list ;
   unsigned int shift ;
   unsigned int nr ;
   unsigned int start ;
   unsigned int end ;
   unsigned int i ;
   int age ;
   void *__cil_tmp14 ;
   struct drm_minor *__cil_tmp15 ;
   struct drm_master *__cil_tmp16 ;
   void *__cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   struct drm_tex_region (*__cil_tmp29)[256U] ;
   unsigned long __cil_tmp30 ;
   struct drm_tex_region *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   struct drm_tex_region *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   struct drm_tex_region *__cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct drm_tex_region *__cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   struct drm_tex_region *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   struct drm_tex_region *__cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   struct drm_tex_region *__cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   struct drm_tex_region *__cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   struct drm_tex_region *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   struct drm_tex_region *__cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   struct drm_tex_region *__cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   struct drm_tex_region *__cil_tmp55 ;
   unsigned char __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   struct drm_tex_region *__cil_tmp58 ;
   unsigned long __cil_tmp59 ;
   struct drm_tex_region *__cil_tmp60 ;
 
   {
 #line 55
   __cil_tmp14 = dev->dev_private;
 #line 55
   dev_priv = (drm_i915_private_t *)__cil_tmp14;
 #line 56
   __cil_tmp15 = dev->primary;
 #line 56
   __cil_tmp16 = __cil_tmp15->master;
 #line 56
   __cil_tmp17 = __cil_tmp16->driver_priv;
 #line 56
   master_priv = (struct drm_i915_master_private *)__cil_tmp17;
 #line 57
   sarea_priv = master_priv->sarea_priv;
 #line 65
   __cil_tmp18 = dev_priv->tex_lru_log_granularity;
 #line 65
   shift = (unsigned int )__cil_tmp18;
 #line 66
   nr = 255U;
 #line 68
   __cil_tmp19 = (int )shift;
 #line 68
   __cil_tmp20 = p->start;
 #line 68
   __cil_tmp21 = __cil_tmp20 >> __cil_tmp19;
 #line 68
   start = (unsigned int )__cil_tmp21;
 #line 69
   __cil_tmp22 = (int )shift;
 #line 69
   __cil_tmp23 = p->size;
 #line 69
   __cil_tmp24 = p->start;
 #line 69
   __cil_tmp25 = __cil_tmp24 + __cil_tmp23;
 #line 69
   __cil_tmp26 = __cil_tmp25 + -1;
 #line 69
   __cil_tmp27 = __cil_tmp26 >> __cil_tmp22;
 #line 69
   end = (unsigned int )__cil_tmp27;
 #line 71
   __cil_tmp28 = sarea_priv->texAge;
 #line 71
   sarea_priv->texAge = __cil_tmp28 + 1;
 #line 71
   age = sarea_priv->texAge;
 #line 72
   __cil_tmp29 = & sarea_priv->texList;
 #line 72
   list = (struct drm_tex_region *)__cil_tmp29;
 #line 77
   i = start;
 #line 77
   goto ldv_37072;
   ldv_37071: 
 #line 78
   __cil_tmp30 = (unsigned long )i;
 #line 78
   __cil_tmp31 = list + __cil_tmp30;
 #line 78
   __cil_tmp31->in_use = (unsigned char )in_use;
 #line 79
   __cil_tmp32 = (unsigned long )i;
 #line 79
   __cil_tmp33 = list + __cil_tmp32;
 #line 79
   __cil_tmp33->age = (unsigned int )age;
 #line 83
   __cil_tmp34 = (unsigned long )i;
 #line 83
   __cil_tmp35 = list + __cil_tmp34;
 #line 83
   __cil_tmp36 = __cil_tmp35->next;
 #line 83
   __cil_tmp37 = (unsigned long )__cil_tmp36;
 #line 83
   __cil_tmp38 = list + __cil_tmp37;
 #line 83
   __cil_tmp39 = (unsigned long )i;
 #line 83
   __cil_tmp40 = list + __cil_tmp39;
 #line 83
   __cil_tmp38->prev = __cil_tmp40->prev;
 #line 84
   __cil_tmp41 = (unsigned long )i;
 #line 84
   __cil_tmp42 = list + __cil_tmp41;
 #line 84
   __cil_tmp43 = __cil_tmp42->prev;
 #line 84
   __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 84
   __cil_tmp45 = list + __cil_tmp44;
 #line 84
   __cil_tmp46 = (unsigned long )i;
 #line 84
   __cil_tmp47 = list + __cil_tmp46;
 #line 84
   __cil_tmp45->next = __cil_tmp47->next;
 #line 88
   __cil_tmp48 = (unsigned long )i;
 #line 88
   __cil_tmp49 = list + __cil_tmp48;
 #line 88
   __cil_tmp49->prev = (unsigned char )nr;
 #line 89
   __cil_tmp50 = (unsigned long )i;
 #line 89
   __cil_tmp51 = list + __cil_tmp50;
 #line 89
   __cil_tmp52 = (unsigned long )nr;
 #line 89
   __cil_tmp53 = list + __cil_tmp52;
 #line 89
   __cil_tmp51->next = __cil_tmp53->next;
 #line 90
   __cil_tmp54 = (unsigned long )nr;
 #line 90
   __cil_tmp55 = list + __cil_tmp54;
 #line 90
   __cil_tmp56 = __cil_tmp55->next;
 #line 90
   __cil_tmp57 = (unsigned long )__cil_tmp56;
 #line 90
   __cil_tmp58 = list + __cil_tmp57;
 #line 90
   __cil_tmp58->prev = (unsigned char )i;
 #line 91
   __cil_tmp59 = (unsigned long )nr;
 #line 91
   __cil_tmp60 = list + __cil_tmp59;
 #line 91
   __cil_tmp60->next = (unsigned char )i;
 #line 77
   i = i + 1U;
   ldv_37072: ;
 #line 77
   if (i <= end) {
 #line 78
     goto ldv_37071;
   } else {
 #line 80
     goto ldv_37073;
   }
   ldv_37073: ;
 #line 82
   return;
 }
 }
 #line 99 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static struct mem_block *split_block(struct mem_block *p , int start , int size ,
                                      struct drm_file *file_priv ) 
 { struct mem_block *newblock ;
   void *tmp ;
   struct mem_block *newblock___0 ;
   void *tmp___0 ;
   int __cil_tmp9 ;
   struct mem_block *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   struct mem_block *__cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   struct mem_block *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   int __cil_tmp23 ;
   struct mem_block *__cil_tmp24 ;
 
   {
   {
 #line 103
   __cil_tmp9 = p->start;
 #line 103
   if (__cil_tmp9 < start) {
     {
 #line 104
     tmp = kmalloc(32UL, 208U);
 #line 104
     newblock = (struct mem_block *)tmp;
     }
     {
 #line 106
     __cil_tmp10 = (struct mem_block *)0;
 #line 106
     __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 106
     __cil_tmp12 = (unsigned long )newblock;
 #line 106
     if (__cil_tmp12 == __cil_tmp11) {
 #line 107
       goto out;
     } else {
 
     }
     }
 #line 108
     newblock->start = start;
 #line 109
     __cil_tmp13 = p->start;
 #line 109
     __cil_tmp14 = __cil_tmp13 - start;
 #line 109
     __cil_tmp15 = p->size;
 #line 109
     newblock->size = __cil_tmp15 + __cil_tmp14;
 #line 110
     newblock->file_priv = (struct drm_file *)0;
 #line 111
     newblock->next = p->next;
 #line 112
     newblock->prev = p;
 #line 113
     __cil_tmp16 = p->next;
 #line 113
     __cil_tmp16->prev = newblock;
 #line 114
     p->next = newblock;
 #line 115
     __cil_tmp17 = newblock->size;
 #line 115
     __cil_tmp18 = p->size;
 #line 115
     p->size = __cil_tmp18 - __cil_tmp17;
 #line 116
     p = newblock;
   } else {
 
   }
   }
   {
 #line 120
   __cil_tmp19 = p->size;
 #line 120
   if (__cil_tmp19 > size) {
     {
 #line 121
     tmp___0 = kmalloc(32UL, 208U);
 #line 121
     newblock___0 = (struct mem_block *)tmp___0;
     }
     {
 #line 123
     __cil_tmp20 = (struct mem_block *)0;
 #line 123
     __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 123
     __cil_tmp22 = (unsigned long )newblock___0;
 #line 123
     if (__cil_tmp22 == __cil_tmp21) {
 #line 124
       goto out;
     } else {
 
     }
     }
 #line 125
     newblock___0->start = start + size;
 #line 126
     __cil_tmp23 = p->size;
 #line 126
     newblock___0->size = __cil_tmp23 - size;
 #line 127
     newblock___0->file_priv = (struct drm_file *)0;
 #line 128
     newblock___0->next = p->next;
 #line 129
     newblock___0->prev = p;
 #line 130
     __cil_tmp24 = p->next;
 #line 130
     __cil_tmp24->prev = newblock___0;
 #line 131
     p->next = newblock___0;
 #line 132
     p->size = size;
   } else {
 
   }
   }
   out: 
 #line 137
   p->file_priv = file_priv;
 #line 138
   return (p);
 }
 }
 #line 141 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static struct mem_block *alloc_block(struct mem_block *heap , int size , int align2 ,
                                      struct drm_file *file_priv ) 
 { struct mem_block *p ;
   int mask ;
   int start ;
   struct mem_block *tmp ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   struct drm_file *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct drm_file *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
 
   {
 #line 145
   __cil_tmp9 = 1 << align2;
 #line 145
   mask = __cil_tmp9 + -1;
 #line 147
   p = heap->next;
 #line 147
   goto ldv_37093;
   ldv_37092: 
 #line 148
   __cil_tmp10 = ~ mask;
 #line 148
   __cil_tmp11 = p->start;
 #line 148
   __cil_tmp12 = __cil_tmp11 + mask;
 #line 148
   start = __cil_tmp12 & __cil_tmp10;
   {
 #line 149
   __cil_tmp13 = (struct drm_file *)0;
 #line 149
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 149
   __cil_tmp15 = p->file_priv;
 #line 149
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 149
   if (__cil_tmp16 == __cil_tmp14) {
     {
 #line 149
     __cil_tmp17 = p->size;
 #line 149
     __cil_tmp18 = p->start;
 #line 149
     __cil_tmp19 = __cil_tmp18 + __cil_tmp17;
 #line 149
     __cil_tmp20 = start + size;
 #line 149
     if (__cil_tmp20 <= __cil_tmp19) {
       {
 #line 150
       tmp = split_block(p, start, size, file_priv);
       }
 #line 150
       return (tmp);
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 147
   p = p->next;
   ldv_37093: ;
   {
 #line 147
   __cil_tmp21 = (unsigned long )heap;
 #line 147
   __cil_tmp22 = (unsigned long )p;
 #line 147
   if (__cil_tmp22 != __cil_tmp21) {
 #line 148
     goto ldv_37092;
   } else {
 #line 150
     goto ldv_37094;
   }
   }
   ldv_37094: ;
 #line 153
   return ((struct mem_block *)0);
 }
 }
 #line 156 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static struct mem_block *find_block(struct mem_block *heap , int start ) 
 { struct mem_block *p ;
   int __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
 
   {
 #line 160
   p = heap->next;
 #line 160
   goto ldv_37101;
   ldv_37100: ;
   {
 #line 161
   __cil_tmp4 = p->start;
 #line 161
   if (__cil_tmp4 == start) {
 #line 162
     return (p);
   } else {
 
   }
   }
 #line 160
   p = p->next;
   ldv_37101: ;
   {
 #line 160
   __cil_tmp5 = (unsigned long )heap;
 #line 160
   __cil_tmp6 = (unsigned long )p;
 #line 160
   if (__cil_tmp6 != __cil_tmp5) {
 #line 161
     goto ldv_37100;
   } else {
 #line 163
     goto ldv_37102;
   }
   }
   ldv_37102: ;
 #line 164
   return ((struct mem_block *)0);
 }
 }
 #line 167 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static void free_block(struct mem_block *p ) 
 { struct mem_block *q ;
   struct mem_block *q___0 ;
   struct drm_file *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   struct mem_block *__cil_tmp6 ;
   struct drm_file *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   struct mem_block *__cil_tmp11 ;
   void const   *__cil_tmp12 ;
   struct drm_file *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct mem_block *__cil_tmp15 ;
   struct drm_file *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   struct mem_block *__cil_tmp20 ;
   void const   *__cil_tmp21 ;
 
   {
 #line 169
   p->file_priv = (struct drm_file *)0;
   {
 #line 174
   __cil_tmp4 = (struct drm_file *)0;
 #line 174
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 174
   __cil_tmp6 = p->next;
 #line 174
   __cil_tmp7 = __cil_tmp6->file_priv;
 #line 174
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 174
   if (__cil_tmp8 == __cil_tmp5) {
     {
 #line 175
     q = p->next;
 #line 176
     __cil_tmp9 = q->size;
 #line 176
     __cil_tmp10 = p->size;
 #line 176
     p->size = __cil_tmp10 + __cil_tmp9;
 #line 177
     p->next = q->next;
 #line 178
     __cil_tmp11 = p->next;
 #line 178
     __cil_tmp11->prev = p;
 #line 179
     __cil_tmp12 = (void const   *)q;
 #line 179
     kfree(__cil_tmp12);
     }
   } else {
 
   }
   }
   {
 #line 182
   __cil_tmp13 = (struct drm_file *)0;
 #line 182
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 182
   __cil_tmp15 = p->prev;
 #line 182
   __cil_tmp16 = __cil_tmp15->file_priv;
 #line 182
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 182
   if (__cil_tmp17 == __cil_tmp14) {
     {
 #line 183
     q___0 = p->prev;
 #line 184
     __cil_tmp18 = p->size;
 #line 184
     __cil_tmp19 = q___0->size;
 #line 184
     q___0->size = __cil_tmp19 + __cil_tmp18;
 #line 185
     q___0->next = p->next;
 #line 186
     __cil_tmp20 = q___0->next;
 #line 186
     __cil_tmp20->prev = q___0;
 #line 187
     __cil_tmp21 = (void const   *)p;
 #line 187
     kfree(__cil_tmp21);
     }
   } else {
 
   }
   }
 #line 189
   return;
 }
 }
 #line 193 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static int init_heap(struct mem_block **heap , int start , int size ) 
 { struct mem_block *blocks ;
   void *tmp ;
   void *tmp___0 ;
   struct mem_block *tmp___1 ;
   struct mem_block *tmp___2 ;
   struct mem_block *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct mem_block *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct mem_block *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   void const   *__cil_tmp16 ;
   struct mem_block *__cil_tmp17 ;
   void *__cil_tmp18 ;
   struct mem_block *__cil_tmp19 ;
   struct mem_block *__cil_tmp20 ;
   struct mem_block *__cil_tmp21 ;
 
   {
   {
 #line 195
   tmp = kmalloc(32UL, 208U);
 #line 195
   blocks = (struct mem_block *)tmp;
   }
   {
 #line 197
   __cil_tmp9 = (struct mem_block *)0;
 #line 197
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 197
   __cil_tmp11 = (unsigned long )blocks;
 #line 197
   if (__cil_tmp11 == __cil_tmp10) {
 #line 198
     return (-12);
   } else {
 
   }
   }
   {
 #line 200
   tmp___0 = kmalloc(32UL, 208U);
 #line 200
   *heap = (struct mem_block *)tmp___0;
   }
   {
 #line 201
   __cil_tmp12 = (struct mem_block *)0;
 #line 201
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 201
   __cil_tmp14 = *heap;
 #line 201
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 201
   if (__cil_tmp15 == __cil_tmp13) {
     {
 #line 202
     __cil_tmp16 = (void const   *)blocks;
 #line 202
     kfree(__cil_tmp16);
     }
 #line 203
     return (-12);
   } else {
 
   }
   }
   {
 #line 206
   blocks->start = start;
 #line 207
   blocks->size = size;
 #line 208
   blocks->file_priv = (struct drm_file *)0;
 #line 209
   tmp___1 = *heap;
 #line 209
   blocks->prev = tmp___1;
 #line 209
   blocks->next = tmp___1;
 #line 211
   __cil_tmp17 = *heap;
 #line 211
   __cil_tmp18 = (void *)__cil_tmp17;
 #line 211
   memset(__cil_tmp18, 0, 32UL);
 #line 212
   __cil_tmp19 = *heap;
 #line 212
   __cil_tmp19->file_priv = (struct drm_file *)1152921504606846975UL;
 #line 213
   tmp___2 = blocks;
 #line 213
   __cil_tmp20 = *heap;
 #line 213
   __cil_tmp20->prev = tmp___2;
 #line 213
   __cil_tmp21 = *heap;
 #line 213
   __cil_tmp21->next = tmp___2;
   }
 #line 214
   return (0);
 }
 }
 #line 219 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 void i915_mem_release(struct drm_device *dev , struct drm_file *file_priv , struct mem_block *heap ) 
 { struct mem_block *p ;
   struct mem_block *q ;
   struct mem_block *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct mem_block *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct mem_block *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct drm_file *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   struct mem_block *__cil_tmp20 ;
   void const   *__cil_tmp21 ;
   struct drm_file *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct drm_file *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_file *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct mem_block *__cil_tmp28 ;
   struct drm_file *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
 
   {
   {
 #line 224
   __cil_tmp6 = (struct mem_block *)0;
 #line 224
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 224
   __cil_tmp8 = (unsigned long )heap;
 #line 224
   if (__cil_tmp8 == __cil_tmp7) {
 #line 225
     return;
   } else {
     {
 #line 224
     __cil_tmp9 = (struct mem_block *)0;
 #line 224
     __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 224
     __cil_tmp11 = heap->next;
 #line 224
     __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 224
     if (__cil_tmp12 == __cil_tmp10) {
 #line 225
       return;
     } else {
 
     }
     }
   }
   }
 #line 227
   p = heap->next;
 #line 227
   goto ldv_37121;
   ldv_37120: ;
   {
 #line 228
   __cil_tmp13 = (unsigned long )file_priv;
 #line 228
   __cil_tmp14 = p->file_priv;
 #line 228
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 228
   if (__cil_tmp15 == __cil_tmp13) {
     {
 #line 229
     p->file_priv = (struct drm_file *)0;
 #line 230
     mark_block(dev, p, 0);
     }
   } else {
 
   }
   }
 #line 227
   p = p->next;
   ldv_37121: ;
   {
 #line 227
   __cil_tmp16 = (unsigned long )heap;
 #line 227
   __cil_tmp17 = (unsigned long )p;
 #line 227
   if (__cil_tmp17 != __cil_tmp16) {
 #line 228
     goto ldv_37120;
   } else {
 #line 230
     goto ldv_37122;
   }
   }
   ldv_37122: 
 #line 237
   p = heap->next;
 #line 237
   goto ldv_37128;
   ldv_37127: ;
 #line 238
   goto ldv_37125;
   ldv_37124: 
   {
 #line 239
   q = p->next;
 #line 240
   __cil_tmp18 = q->size;
 #line 240
   __cil_tmp19 = p->size;
 #line 240
   p->size = __cil_tmp19 + __cil_tmp18;
 #line 241
   p->next = q->next;
 #line 242
   __cil_tmp20 = p->next;
 #line 242
   __cil_tmp20->prev = p;
 #line 243
   __cil_tmp21 = (void const   *)q;
 #line 243
   kfree(__cil_tmp21);
   }
   ldv_37125: ;
   {
 #line 238
   __cil_tmp22 = (struct drm_file *)0;
 #line 238
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 238
   __cil_tmp24 = p->file_priv;
 #line 238
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 238
   if (__cil_tmp25 == __cil_tmp23) {
     {
 #line 238
     __cil_tmp26 = (struct drm_file *)0;
 #line 238
     __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 238
     __cil_tmp28 = p->next;
 #line 238
     __cil_tmp29 = __cil_tmp28->file_priv;
 #line 238
     __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 238
     if (__cil_tmp30 == __cil_tmp27) {
 #line 239
       goto ldv_37124;
     } else {
 #line 241
       goto ldv_37126;
     }
     }
   } else {
 #line 241
     goto ldv_37126;
   }
   }
   ldv_37126: 
 #line 237
   p = p->next;
   ldv_37128: ;
   {
 #line 237
   __cil_tmp31 = (unsigned long )heap;
 #line 237
   __cil_tmp32 = (unsigned long )p;
 #line 237
   if (__cil_tmp32 != __cil_tmp31) {
 #line 238
     goto ldv_37127;
   } else {
 #line 240
     goto ldv_37129;
   }
   }
   ldv_37129: ;
 #line 242
   return;
 }
 }
 #line 250 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 void i915_mem_takedown(struct mem_block **heap ) 
 { struct mem_block *p ;
   struct mem_block *q ;
   struct mem_block *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   struct mem_block *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct mem_block *__cil_tmp8 ;
   void const   *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct mem_block *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct mem_block *__cil_tmp13 ;
   void const   *__cil_tmp14 ;
 
   {
   {
 #line 254
   __cil_tmp4 = (struct mem_block *)0;
 #line 254
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 254
   __cil_tmp6 = *heap;
 #line 254
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 254
   if (__cil_tmp7 == __cil_tmp5) {
 #line 255
     return;
   } else {
 
   }
   }
 #line 257
   __cil_tmp8 = *heap;
 #line 257
   p = __cil_tmp8->next;
 #line 257
   goto ldv_37136;
   ldv_37135: 
   {
 #line 258
   q = p;
 #line 259
   p = p->next;
 #line 260
   __cil_tmp9 = (void const   *)q;
 #line 260
   kfree(__cil_tmp9);
   }
   ldv_37136: ;
   {
 #line 257
   __cil_tmp10 = (unsigned long )p;
 #line 257
   __cil_tmp11 = *heap;
 #line 257
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 257
   if (__cil_tmp12 != __cil_tmp10) {
 #line 258
     goto ldv_37135;
   } else {
 #line 260
     goto ldv_37137;
   }
   }
   ldv_37137: 
   {
 #line 263
   __cil_tmp13 = *heap;
 #line 263
   __cil_tmp14 = (void const   *)__cil_tmp13;
 #line 263
   kfree(__cil_tmp14);
 #line 264
   *heap = (struct mem_block *)0;
   }
 #line 265
   return;
 }
 }
 #line 267 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 static struct mem_block **get_heap(drm_i915_private_t *dev_priv , int region ) 
 { 
 
   {
 #line 270
   if (region == 1) {
 #line 270
     goto case_1;
   } else {
 #line 272
     goto switch_default;
 #line 269
     if (0) {
       case_1: ;
 #line 271
       return (& dev_priv->agp_heap);
       switch_default: ;
 #line 273
       return ((struct mem_block **)0);
     } else {
 
     }
   }
 }
 }
 #line 279 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 int i915_mem_alloc(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_mem_alloc_t *alloc ;
   struct mem_block *block ;
   struct mem_block **heap ;
   int tmp ;
   void *__cil_tmp9 ;
   drm_i915_private_t *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   int __cil_tmp13 ;
   struct mem_block **__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct mem_block *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct mem_block *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   int __cil_tmp21 ;
   struct mem_block *__cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   struct mem_block *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   int *__cil_tmp28 ;
   void *__cil_tmp29 ;
   int *__cil_tmp30 ;
   void const   *__cil_tmp31 ;
 
   {
 #line 282
   __cil_tmp9 = dev->dev_private;
 #line 282
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 283
   alloc = (drm_i915_mem_alloc_t *)data;
   {
 #line 286
   __cil_tmp10 = (drm_i915_private_t *)0;
 #line 286
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 286
   __cil_tmp12 = (unsigned long )dev_priv;
 #line 286
   if (__cil_tmp12 == __cil_tmp11) {
     {
 #line 287
     drm_err("i915_mem_alloc", "called with no initialization\n");
     }
 #line 288
     return (-22);
   } else {
 
   }
   }
   {
 #line 291
   __cil_tmp13 = alloc->region;
 #line 291
   heap = get_heap(dev_priv, __cil_tmp13);
   }
   {
 #line 292
   __cil_tmp14 = (struct mem_block **)0;
 #line 292
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 292
   __cil_tmp16 = (unsigned long )heap;
 #line 292
   if (__cil_tmp16 == __cil_tmp15) {
 #line 293
     return (-14);
   } else {
     {
 #line 292
     __cil_tmp17 = (struct mem_block *)0;
 #line 292
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 292
     __cil_tmp19 = *heap;
 #line 292
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 292
     if (__cil_tmp20 == __cil_tmp18) {
 #line 293
       return (-14);
     } else {
 
     }
     }
   }
   }
   {
 #line 298
   __cil_tmp21 = alloc->alignment;
 #line 298
   if (__cil_tmp21 <= 11) {
 #line 299
     alloc->alignment = 12;
   } else {
 
   }
   }
   {
 #line 301
   __cil_tmp22 = *heap;
 #line 301
   __cil_tmp23 = alloc->size;
 #line 301
   __cil_tmp24 = alloc->alignment;
 #line 301
   block = alloc_block(__cil_tmp22, __cil_tmp23, __cil_tmp24, file_priv);
   }
   {
 #line 303
   __cil_tmp25 = (struct mem_block *)0;
 #line 303
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 303
   __cil_tmp27 = (unsigned long )block;
 #line 303
   if (__cil_tmp27 == __cil_tmp26) {
 #line 304
     return (-12);
   } else {
 
   }
   }
   {
 #line 306
   mark_block(dev, block, 1);
 #line 308
   __cil_tmp28 = alloc->region_offset;
 #line 308
   __cil_tmp29 = (void *)__cil_tmp28;
 #line 308
   __cil_tmp30 = & block->start;
 #line 308
   __cil_tmp31 = (void const   *)__cil_tmp30;
 #line 308
   tmp = copy_to_user(__cil_tmp29, __cil_tmp31, 4U);
   }
 #line 308
   if (tmp != 0) {
     {
 #line 310
     drm_err("i915_mem_alloc", "copy_to_user\n");
     }
 #line 311
     return (-14);
   } else {
 
   }
 #line 314
   return (0);
 }
 }
 #line 317 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 int i915_mem_free(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_mem_free_t *memfree ;
   struct mem_block *block ;
   struct mem_block **heap ;
   void *__cil_tmp8 ;
   drm_i915_private_t *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   int __cil_tmp12 ;
   struct mem_block **__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct mem_block *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct mem_block *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct mem_block *__cil_tmp20 ;
   int __cil_tmp21 ;
   struct mem_block *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_file *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
 
   {
 #line 320
   __cil_tmp8 = dev->dev_private;
 #line 320
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 321
   memfree = (drm_i915_mem_free_t *)data;
   {
 #line 324
   __cil_tmp9 = (drm_i915_private_t *)0;
 #line 324
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 324
   __cil_tmp11 = (unsigned long )dev_priv;
 #line 324
   if (__cil_tmp11 == __cil_tmp10) {
     {
 #line 325
     drm_err("i915_mem_free", "called with no initialization\n");
     }
 #line 326
     return (-22);
   } else {
 
   }
   }
   {
 #line 329
   __cil_tmp12 = memfree->region;
 #line 329
   heap = get_heap(dev_priv, __cil_tmp12);
   }
   {
 #line 330
   __cil_tmp13 = (struct mem_block **)0;
 #line 330
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 330
   __cil_tmp15 = (unsigned long )heap;
 #line 330
   if (__cil_tmp15 == __cil_tmp14) {
 #line 331
     return (-14);
   } else {
     {
 #line 330
     __cil_tmp16 = (struct mem_block *)0;
 #line 330
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 330
     __cil_tmp18 = *heap;
 #line 330
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 330
     if (__cil_tmp19 == __cil_tmp17) {
 #line 331
       return (-14);
     } else {
 
     }
     }
   }
   }
   {
 #line 333
   __cil_tmp20 = *heap;
 #line 333
   __cil_tmp21 = memfree->region_offset;
 #line 333
   block = find_block(__cil_tmp20, __cil_tmp21);
   }
   {
 #line 334
   __cil_tmp22 = (struct mem_block *)0;
 #line 334
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 334
   __cil_tmp24 = (unsigned long )block;
 #line 334
   if (__cil_tmp24 == __cil_tmp23) {
 #line 335
     return (-14);
   } else {
 
   }
   }
   {
 #line 337
   __cil_tmp25 = (unsigned long )file_priv;
 #line 337
   __cil_tmp26 = block->file_priv;
 #line 337
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 337
   if (__cil_tmp27 != __cil_tmp25) {
 #line 338
     return (-1);
   } else {
 
   }
   }
   {
 #line 340
   mark_block(dev, block, 0);
 #line 341
   free_block(block);
   }
 #line 342
   return (0);
 }
 }
 #line 345 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 int i915_mem_init_heap(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_mem_init_heap_t *initheap ;
   struct mem_block **heap ;
   int tmp ;
   void *__cil_tmp8 ;
   drm_i915_private_t *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   int __cil_tmp12 ;
   struct mem_block **__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct mem_block *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct mem_block *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
 
   {
 #line 348
   __cil_tmp8 = dev->dev_private;
 #line 348
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 349
   initheap = (drm_i915_mem_init_heap_t *)data;
   {
 #line 352
   __cil_tmp9 = (drm_i915_private_t *)0;
 #line 352
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 352
   __cil_tmp11 = (unsigned long )dev_priv;
 #line 352
   if (__cil_tmp11 == __cil_tmp10) {
     {
 #line 353
     drm_err("i915_mem_init_heap", "called with no initialization\n");
     }
 #line 354
     return (-22);
   } else {
 
   }
   }
   {
 #line 357
   __cil_tmp12 = initheap->region;
 #line 357
   heap = get_heap(dev_priv, __cil_tmp12);
   }
   {
 #line 358
   __cil_tmp13 = (struct mem_block **)0;
 #line 358
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 358
   __cil_tmp15 = (unsigned long )heap;
 #line 358
   if (__cil_tmp15 == __cil_tmp14) {
 #line 359
     return (-14);
   } else {
 
   }
   }
   {
 #line 361
   __cil_tmp16 = (struct mem_block *)0;
 #line 361
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 361
   __cil_tmp18 = *heap;
 #line 361
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 361
   if (__cil_tmp19 != __cil_tmp17) {
     {
 #line 362
     drm_err("i915_mem_init_heap", "heap already initialized?");
     }
 #line 363
     return (-14);
   } else {
 
   }
   }
   {
 #line 366
   __cil_tmp20 = initheap->start;
 #line 366
   __cil_tmp21 = initheap->size;
 #line 366
   tmp = init_heap(heap, __cil_tmp20, __cil_tmp21);
   }
 #line 366
   return (tmp);
 }
 }
 #line 369 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_mem.c.p"
 int i915_mem_destroy_heap(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   drm_i915_mem_destroy_heap_t *destroyheap ;
   struct mem_block **heap ;
   void *__cil_tmp7 ;
   drm_i915_private_t *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   int __cil_tmp11 ;
   struct mem_block **__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct mem_block *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct mem_block *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
 
   {
 #line 372
   __cil_tmp7 = dev->dev_private;
 #line 372
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 373
   destroyheap = (drm_i915_mem_destroy_heap_t *)data;
   {
 #line 376
   __cil_tmp8 = (drm_i915_private_t *)0;
 #line 376
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 376
   __cil_tmp10 = (unsigned long )dev_priv;
 #line 376
   if (__cil_tmp10 == __cil_tmp9) {
     {
 #line 377
     drm_err("i915_mem_destroy_heap", "called with no initialization\n");
     }
 #line 378
     return (-22);
   } else {
 
   }
   }
   {
 #line 381
   __cil_tmp11 = destroyheap->region;
 #line 381
   heap = get_heap(dev_priv, __cil_tmp11);
   }
   {
 #line 382
   __cil_tmp12 = (struct mem_block **)0;
 #line 382
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 382
   __cil_tmp14 = (unsigned long )heap;
 #line 382
   if (__cil_tmp14 == __cil_tmp13) {
     {
 #line 383
     drm_err("i915_mem_destroy_heap", "get_heap failed");
     }
 #line 384
     return (-14);
   } else {
 
   }
   }
   {
 #line 387
   __cil_tmp15 = (struct mem_block *)0;
 #line 387
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 387
   __cil_tmp17 = *heap;
 #line 387
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 387
   if (__cil_tmp18 == __cil_tmp16) {
     {
 #line 388
     drm_err("i915_mem_destroy_heap", "heap not initialized?");
     }
 #line 389
     return (-14);
   } else {
 
   }
   }
   {
 #line 392
   i915_mem_takedown(heap);
   }
 #line 393
   return (0);
 }
 }
 #line 47 "include/linux/list.h"
 extern void __list_add(struct list_head * , struct list_head * , struct list_head * ) ;
 #line 60 "include/linux/list.h"
 __inline static void list_add(struct list_head *new , struct list_head *head ) 
 { struct list_head *__cil_tmp3 ;
 
   {
   {
 #line 62
   __cil_tmp3 = head->next;
 #line 62
   __list_add(new, head, __cil_tmp3);
   }
 #line 63
   return;
 }
 }
 #line 282 "include/linux/kernel.h"
 extern unsigned long simple_strtoul(char const   * , char ** , unsigned int  ) ;
 #line 295
 extern int snprintf(char * , size_t  , char const   *  , ...) ;
 #line 27 "include/linux/err.h"
 __inline static long PTR_ERR(void const   *ptr ) 
 { 
 
   {
 #line 29
   return ((long )ptr);
 }
 }
 #line 32 "include/linux/err.h"
 __inline static long IS_ERR(void const   *ptr ) 
 { long tmp ;
   unsigned long __cil_tmp3 ;
   int __cil_tmp4 ;
   long __cil_tmp5 ;
 
   {
   {
 #line 34
   __cil_tmp3 = (unsigned long )ptr;
 #line 34
   __cil_tmp4 = __cil_tmp3 > 1152921504606842880UL;
 #line 34
   __cil_tmp5 = (long )__cil_tmp4;
 #line 34
   tmp = __builtin_expect(__cil_tmp5, 0L);
   }
 #line 34
   return (tmp);
 }
 }
 #line 136 "include/linux/mutex.h"
 extern int mutex_lock_interruptible_nested(struct mutex * , unsigned int  ) ;
 #line 84 "include/linux/seq_file.h"
 extern int seq_write(struct seq_file * , void const   * , size_t  ) ;
 #line 86
 extern int seq_printf(struct seq_file * , char const   *  , ...) ;
 #line 2246 "include/linux/fs.h"
 extern loff_t default_llseek(struct file * , loff_t  , int  ) ;
 #line 2467
 extern ssize_t simple_read_from_buffer(void * , size_t  , loff_t * , void const   * ,
                                        size_t  ) ;
 #line 37 "include/linux/debugfs.h"
 extern struct dentry *debugfs_create_file(char const   * , mode_t  , struct dentry * ,
                                           void * , struct file_operations  const  * ) ;
 #line 46
 extern void debugfs_remove(struct dentry * ) ;
 #line 1483 "include/drm/drmP.h"
 extern int drm_debugfs_create_files(struct drm_info_list * , int  , struct dentry * ,
                                     struct drm_minor * ) ;
 #line 1485
 extern int drm_debugfs_remove_files(struct drm_info_list * , int  , struct drm_minor * ) ;
 #line 191 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring ) ;
 #line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_reg_rw___2(bool write , u32 reg , u64 val , int len ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp13 ;
   struct tracepoint_func **__cil_tmp14 ;
   struct tracepoint_func * volatile  *__cil_tmp15 ;
   struct tracepoint_func * volatile  __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct tracepoint_func *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   void *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   void *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
 
   {
   {
 #line 387
   __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
 #line 387
   tmp___1 = static_branch(__cil_tmp13);
   }
 #line 387
   if ((int )tmp___1) {
     {
 #line 387
     rcu_read_lock_sched_notrace();
 #line 387
     __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
 #line 387
     __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
 #line 387
     __cil_tmp16 = *__cil_tmp15;
 #line 387
     _________p1 = (struct tracepoint_func *)__cil_tmp16;
 #line 387
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 387
     if (tmp != 0) {
 #line 387
       if (! __warned) {
         {
 #line 387
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 387
         if (tmp___0 == 0) {
           {
 #line 387
           __warned = (bool )1;
 #line 387
           __cil_tmp17 = (int const   )411;
 #line 387
           __cil_tmp18 = (int )__cil_tmp17;
 #line 387
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp18);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 387
     it_func_ptr = _________p1;
     {
 #line 387
     __cil_tmp19 = (struct tracepoint_func *)0;
 #line 387
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 387
     __cil_tmp21 = (unsigned long )it_func_ptr;
 #line 387
     if (__cil_tmp21 != __cil_tmp20) {
       ldv_36339: 
       {
 #line 387
       it_func = it_func_ptr->func;
 #line 387
       __data = it_func_ptr->data;
 #line 387
       __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
 #line 387
       __cil_tmp23 = (int )write;
 #line 387
       __cil_tmp24 = (bool )__cil_tmp23;
 #line 387
       (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
 #line 387
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 387
       __cil_tmp25 = (void *)0;
 #line 387
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 387
       __cil_tmp27 = it_func_ptr->func;
 #line 387
       __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 387
       if (__cil_tmp28 != __cil_tmp26) {
 #line 388
         goto ldv_36339;
       } else {
 #line 390
         goto ldv_36340;
       }
       }
       ldv_36340: ;
     } else {
 
     }
     }
     {
 #line 387
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 389
   return;
 }
 }
 #line 1291 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 bool intel_fbc_enabled(struct drm_device *dev ) ;
 #line 1301
 void intel_overlay_print_error_state(struct seq_file *m , struct intel_overlay_error_state *error ) ;
 #line 1304
 void intel_display_print_error_state(struct seq_file *m , struct drm_device *dev ,
                                      struct intel_display_error_state *error ) ;
 #line 1360 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u16 i915_read16___0(struct drm_i915_private *dev_priv , u32 reg ) 
 { u16 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1360
   val = (u16 )0U;
   {
 #line 1360
   __cil_tmp4 = dev_priv->info;
 #line 1360
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1360
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1360
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1360
   if (__cil_tmp7 > 5U) {
 #line 1360
     if (reg <= 262143U) {
 #line 1360
       if (reg != 41356U) {
         {
 #line 1360
         gen6_gt_force_wake_get(dev_priv);
 #line 1360
         __cil_tmp8 = (unsigned long )reg;
 #line 1360
         __cil_tmp9 = dev_priv->regs;
 #line 1360
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1360
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1360
         val = readw(__cil_tmp11);
 #line 1360
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1360
         __cil_tmp12 = (unsigned long )reg;
 #line 1360
         __cil_tmp13 = dev_priv->regs;
 #line 1360
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1360
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1360
         val = readw(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1360
       __cil_tmp16 = (unsigned long )reg;
 #line 1360
       __cil_tmp17 = dev_priv->regs;
 #line 1360
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1360
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1360
       val = readw(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1360
     __cil_tmp20 = (unsigned long )reg;
 #line 1360
     __cil_tmp21 = dev_priv->regs;
 #line 1360
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1360
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1360
     val = readw(__cil_tmp23);
     }
   }
   }
   {
 #line 1360
   __cil_tmp24 = (bool )0;
 #line 1360
   __cil_tmp25 = (u64 )val;
 #line 1360
   trace_i915_reg_rw___2(__cil_tmp24, reg, __cil_tmp25, 2);
   }
 #line 1360
   return (val);
 }
 }
 #line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u32 i915_read32___2(struct drm_i915_private *dev_priv , u32 reg ) 
 { u32 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1361
   val = 0U;
   {
 #line 1361
   __cil_tmp4 = dev_priv->info;
 #line 1361
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1361
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1361
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1361
   if (__cil_tmp7 > 5U) {
 #line 1361
     if (reg <= 262143U) {
 #line 1361
       if (reg != 41356U) {
         {
 #line 1361
         gen6_gt_force_wake_get(dev_priv);
 #line 1361
         __cil_tmp8 = (unsigned long )reg;
 #line 1361
         __cil_tmp9 = dev_priv->regs;
 #line 1361
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1361
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1361
         val = readl(__cil_tmp11);
 #line 1361
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1361
         __cil_tmp12 = (unsigned long )reg;
 #line 1361
         __cil_tmp13 = dev_priv->regs;
 #line 1361
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1361
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1361
         val = readl(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1361
       __cil_tmp16 = (unsigned long )reg;
 #line 1361
       __cil_tmp17 = dev_priv->regs;
 #line 1361
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1361
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1361
       val = readl(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1361
     __cil_tmp20 = (unsigned long )reg;
 #line 1361
     __cil_tmp21 = dev_priv->regs;
 #line 1361
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1361
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1361
     val = readl(__cil_tmp23);
     }
   }
   }
   {
 #line 1361
   __cil_tmp24 = (bool )0;
 #line 1361
   __cil_tmp25 = (u64 )val;
 #line 1361
   trace_i915_reg_rw___2(__cil_tmp24, reg, __cil_tmp25, 4);
   }
 #line 1361
   return (val);
 }
 }
 #line 60 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *yesno(int v ) 
 { char const   *tmp ;
 
   {
 #line 62
   if (v != 0) {
 #line 62
     tmp = "yes";
   } else {
 #line 62
     tmp = "no";
   }
 #line 62
   return (tmp);
 }
 }
 #line 65 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_capabilities(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   struct intel_device_info  const  *info ;
   char const   *tmp ;
   char const   *tmp___0 ;
   char const   *tmp___1 ;
   char const   *tmp___2 ;
   char const   *tmp___3 ;
   char const   *tmp___4 ;
   char const   *tmp___5 ;
   char const   *tmp___6 ;
   char const   *tmp___7 ;
   char const   *tmp___8 ;
   char const   *tmp___9 ;
   char const   *tmp___10 ;
   char const   *tmp___11 ;
   char const   *tmp___12 ;
   char const   *tmp___13 ;
   char const   *tmp___14 ;
   char const   *tmp___15 ;
   char const   *tmp___16 ;
   char const   *tmp___17 ;
   void *__cil_tmp25 ;
   struct drm_minor *__cil_tmp26 ;
   void *__cil_tmp27 ;
   struct drm_i915_private *__cil_tmp28 ;
   u8 __cil_tmp29 ;
   int __cil_tmp30 ;
   unsigned char __cil_tmp31 ;
   int __cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   int __cil_tmp34 ;
   unsigned char __cil_tmp35 ;
   int __cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   int __cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   int __cil_tmp40 ;
   unsigned char __cil_tmp41 ;
   int __cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   int __cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   int __cil_tmp46 ;
   unsigned char __cil_tmp47 ;
   int __cil_tmp48 ;
   unsigned char __cil_tmp49 ;
   int __cil_tmp50 ;
   unsigned char __cil_tmp51 ;
   int __cil_tmp52 ;
   unsigned char __cil_tmp53 ;
   int __cil_tmp54 ;
   unsigned char __cil_tmp55 ;
   int __cil_tmp56 ;
   unsigned char __cil_tmp57 ;
   int __cil_tmp58 ;
   unsigned char __cil_tmp59 ;
   int __cil_tmp60 ;
   unsigned char __cil_tmp61 ;
   int __cil_tmp62 ;
   unsigned char __cil_tmp63 ;
   int __cil_tmp64 ;
   unsigned char __cil_tmp65 ;
   int __cil_tmp66 ;
   unsigned char __cil_tmp67 ;
   int __cil_tmp68 ;
 
   {
   {
 #line 67
   __cil_tmp25 = m->private;
 #line 67
   node = (struct drm_info_node *)__cil_tmp25;
 #line 68
   __cil_tmp26 = node->minor;
 #line 68
   dev = __cil_tmp26->dev;
 #line 69
   __cil_tmp27 = dev->dev_private;
 #line 69
   __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
 #line 69
   info = __cil_tmp28->info;
 #line 71
   __cil_tmp29 = info->gen;
 #line 71
   __cil_tmp30 = (int )__cil_tmp29;
 #line 71
   seq_printf(m, "gen: %d\n", __cil_tmp30);
 #line 73
   __cil_tmp31 = info->is_mobile;
 #line 73
   __cil_tmp32 = (int )__cil_tmp31;
 #line 73
   tmp = yesno(__cil_tmp32);
 #line 73
   seq_printf(m, "is_mobile: %s\n", tmp);
 #line 74
   __cil_tmp33 = info->is_i85x;
 #line 74
   __cil_tmp34 = (int )__cil_tmp33;
 #line 74
   tmp___0 = yesno(__cil_tmp34);
 #line 74
   seq_printf(m, "is_i85x: %s\n", tmp___0);
 #line 75
   __cil_tmp35 = info->is_i915g;
 #line 75
   __cil_tmp36 = (int )__cil_tmp35;
 #line 75
   tmp___1 = yesno(__cil_tmp36);
 #line 75
   seq_printf(m, "is_i915g: %s\n", tmp___1);
 #line 76
   __cil_tmp37 = info->is_i945gm;
 #line 76
   __cil_tmp38 = (int )__cil_tmp37;
 #line 76
   tmp___2 = yesno(__cil_tmp38);
 #line 76
   seq_printf(m, "is_i945gm: %s\n", tmp___2);
 #line 77
   __cil_tmp39 = info->is_g33;
 #line 77
   __cil_tmp40 = (int )__cil_tmp39;
 #line 77
   tmp___3 = yesno(__cil_tmp40);
 #line 77
   seq_printf(m, "is_g33: %s\n", tmp___3);
 #line 78
   __cil_tmp41 = info->need_gfx_hws;
 #line 78
   __cil_tmp42 = (int )__cil_tmp41;
 #line 78
   tmp___4 = yesno(__cil_tmp42);
 #line 78
   seq_printf(m, "need_gfx_hws: %s\n", tmp___4);
 #line 79
   __cil_tmp43 = info->is_g4x;
 #line 79
   __cil_tmp44 = (int )__cil_tmp43;
 #line 79
   tmp___5 = yesno(__cil_tmp44);
 #line 79
   seq_printf(m, "is_g4x: %s\n", tmp___5);
 #line 80
   __cil_tmp45 = info->is_pineview;
 #line 80
   __cil_tmp46 = (int )__cil_tmp45;
 #line 80
   tmp___6 = yesno(__cil_tmp46);
 #line 80
   seq_printf(m, "is_pineview: %s\n", tmp___6);
 #line 81
   __cil_tmp47 = info->is_broadwater;
 #line 81
   __cil_tmp48 = (int )__cil_tmp47;
 #line 81
   tmp___7 = yesno(__cil_tmp48);
 #line 81
   seq_printf(m, "is_broadwater: %s\n", tmp___7);
 #line 82
   __cil_tmp49 = info->is_crestline;
 #line 82
   __cil_tmp50 = (int )__cil_tmp49;
 #line 82
   tmp___8 = yesno(__cil_tmp50);
 #line 82
   seq_printf(m, "is_crestline: %s\n", tmp___8);
 #line 83
   __cil_tmp51 = info->has_fbc;
 #line 83
   __cil_tmp52 = (int )__cil_tmp51;
 #line 83
   tmp___9 = yesno(__cil_tmp52);
 #line 83
   seq_printf(m, "has_fbc: %s\n", tmp___9);
 #line 84
   __cil_tmp53 = info->has_pipe_cxsr;
 #line 84
   __cil_tmp54 = (int )__cil_tmp53;
 #line 84
   tmp___10 = yesno(__cil_tmp54);
 #line 84
   seq_printf(m, "has_pipe_cxsr: %s\n", tmp___10);
 #line 85
   __cil_tmp55 = info->has_hotplug;
 #line 85
   __cil_tmp56 = (int )__cil_tmp55;
 #line 85
   tmp___11 = yesno(__cil_tmp56);
 #line 85
   seq_printf(m, "has_hotplug: %s\n", tmp___11);
 #line 86
   __cil_tmp57 = info->cursor_needs_physical;
 #line 86
   __cil_tmp58 = (int )__cil_tmp57;
 #line 86
   tmp___12 = yesno(__cil_tmp58);
 #line 86
   seq_printf(m, "cursor_needs_physical: %s\n", tmp___12);
 #line 87
   __cil_tmp59 = info->has_overlay;
 #line 87
   __cil_tmp60 = (int )__cil_tmp59;
 #line 87
   tmp___13 = yesno(__cil_tmp60);
 #line 87
   seq_printf(m, "has_overlay: %s\n", tmp___13);
 #line 88
   __cil_tmp61 = info->overlay_needs_physical;
 #line 88
   __cil_tmp62 = (int )__cil_tmp61;
 #line 88
   tmp___14 = yesno(__cil_tmp62);
 #line 88
   seq_printf(m, "overlay_needs_physical: %s\n", tmp___14);
 #line 89
   __cil_tmp63 = info->supports_tv;
 #line 89
   __cil_tmp64 = (int )__cil_tmp63;
 #line 89
   tmp___15 = yesno(__cil_tmp64);
 #line 89
   seq_printf(m, "supports_tv: %s\n", tmp___15);
 #line 90
   __cil_tmp65 = info->has_bsd_ring;
 #line 90
   __cil_tmp66 = (int )__cil_tmp65;
 #line 90
   tmp___16 = yesno(__cil_tmp66);
 #line 90
   seq_printf(m, "has_bsd_ring: %s\n", tmp___16);
 #line 91
   __cil_tmp67 = info->has_blt_ring;
 #line 91
   __cil_tmp68 = (int )__cil_tmp67;
 #line 91
   tmp___17 = yesno(__cil_tmp68);
 #line 91
   seq_printf(m, "has_blt_ring: %s\n", tmp___17);
   }
 #line 94
   return (0);
 }
 }
 #line 97 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *get_pin_flag(struct drm_i915_gem_object *obj ) 
 { uint32_t __cil_tmp2 ;
   unsigned char __cil_tmp3 ;
   int __cil_tmp4 ;
 
   {
   {
 #line 99
   __cil_tmp2 = obj->user_pin_count;
 #line 99
   if (__cil_tmp2 != 0U) {
 #line 100
     return ("P");
   } else {
     {
 #line 101
     __cil_tmp3 = obj->pin_count;
 #line 101
     __cil_tmp4 = (int )__cil_tmp3;
 #line 101
     if (__cil_tmp4 > 0) {
 #line 102
       return ("p");
     } else {
 #line 104
       return (" ");
     }
     }
   }
   }
 }
 }
 #line 107 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *get_tiling_flag(struct drm_i915_gem_object *obj ) 
 { unsigned char __cil_tmp2 ;
   int __cil_tmp3 ;
   unsigned char __cil_tmp4 ;
   int __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   int __cil_tmp7 ;
 
   {
   {
 #line 111
   __cil_tmp2 = obj->tiling_mode;
 #line 111
   __cil_tmp3 = (int )__cil_tmp2;
 #line 111
   if (__cil_tmp3 == 0) {
 #line 111
     goto case_0;
   } else {
     {
 #line 112
     __cil_tmp4 = obj->tiling_mode;
 #line 112
     __cil_tmp5 = (int )__cil_tmp4;
 #line 112
     if (__cil_tmp5 == 1) {
 #line 112
       goto case_1;
     } else {
       {
 #line 113
       __cil_tmp6 = obj->tiling_mode;
 #line 113
       __cil_tmp7 = (int )__cil_tmp6;
 #line 113
       if (__cil_tmp7 == 2) {
 #line 113
         goto case_2;
       } else {
 #line 110
         goto switch_default;
 #line 109
         if (0) {
           switch_default: ;
           case_0: ;
 #line 111
           return (" ");
           case_1: ;
 #line 112
           return ("X");
           case_2: ;
 #line 113
           return ("Y");
         } else {
 
         }
       }
       }
     }
     }
   }
   }
 }
 }
 #line 117 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *cache_level_str(int type ) 
 { 
 
   {
 #line 120
   if (type == 0) {
 #line 120
     goto case_0;
   } else
 #line 121
   if (type == 1) {
 #line 121
     goto case_1;
   } else
 #line 122
   if (type == 2) {
 #line 122
     goto case_2;
   } else {
 #line 123
     goto switch_default;
 #line 119
     if (0) {
       case_0: ;
 #line 120
       return (" uncached");
       case_1: ;
 #line 121
       return (" snooped (LLC)");
       case_2: ;
 #line 122
       return (" snooped (LLC+MLC)");
       switch_default: ;
 #line 123
       return ("");
     } else {
 
     }
   }
 }
 }
 #line 128 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static void describe_obj(struct seq_file *m , struct drm_i915_gem_object *obj ) 
 { char *tmp ;
   char *tmp___0 ;
   char const   *tmp___1 ;
   char const   *tmp___2 ;
   char const   *tmp___3 ;
   char s[3U] ;
   char *t ;
   char *tmp___4 ;
   char *tmp___5 ;
   unsigned char *__cil_tmp12 ;
   unsigned char *__cil_tmp13 ;
   unsigned char __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   unsigned char __cil_tmp20 ;
   int __cil_tmp21 ;
   struct drm_gem_object *__cil_tmp22 ;
   size_t __cil_tmp23 ;
   uint32_t __cil_tmp24 ;
   uint32_t __cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   uint32_t __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   signed char __cil_tmp34 ;
   int __cil_tmp35 ;
   struct drm_mm_node *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct drm_mm_node *__cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   uint32_t __cil_tmp40 ;
   struct drm_mm_node *__cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char *__cil_tmp45 ;
   unsigned char __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   unsigned char *__cil_tmp48 ;
   unsigned char *__cil_tmp49 ;
   unsigned char __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned char *__cil_tmp52 ;
   unsigned char *__cil_tmp53 ;
   unsigned char __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   unsigned char *__cil_tmp56 ;
   unsigned char *__cil_tmp57 ;
   unsigned char __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   char *__cil_tmp60 ;
   struct intel_ring_buffer *__cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   struct intel_ring_buffer *__cil_tmp63 ;
   unsigned long __cil_tmp64 ;
   struct intel_ring_buffer *__cil_tmp65 ;
   char const   *__cil_tmp66 ;
 
   {
   {
 #line 130
   __cil_tmp12 = (unsigned char *)obj;
 #line 130
   __cil_tmp13 = __cil_tmp12 + 225UL;
 #line 130
   __cil_tmp14 = *__cil_tmp13;
 #line 130
   __cil_tmp15 = (unsigned int )__cil_tmp14;
 #line 130
   if (__cil_tmp15 == 1U) {
 #line 130
     tmp = (char *)" purgeable";
   } else {
 #line 130
     tmp = (char *)"";
   }
   }
   {
 #line 130
   __cil_tmp16 = (unsigned char *)obj;
 #line 130
   __cil_tmp17 = __cil_tmp16 + 224UL;
 #line 130
   __cil_tmp18 = *__cil_tmp17;
 #line 130
   __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 130
   if (__cil_tmp19 != 0U) {
 #line 130
     tmp___0 = (char *)" dirty";
   } else {
 #line 130
     tmp___0 = (char *)"";
   }
   }
   {
 #line 130
   __cil_tmp20 = obj->cache_level;
 #line 130
   __cil_tmp21 = (int )__cil_tmp20;
 #line 130
   tmp___1 = cache_level_str(__cil_tmp21);
 #line 130
   tmp___2 = get_tiling_flag(obj);
 #line 130
   tmp___3 = get_pin_flag(obj);
 #line 130
   __cil_tmp22 = & obj->base;
 #line 130
   __cil_tmp23 = obj->base.size;
 #line 130
   __cil_tmp24 = obj->base.read_domains;
 #line 130
   __cil_tmp25 = obj->base.write_domain;
 #line 130
   __cil_tmp26 = obj->last_rendering_seqno;
 #line 130
   __cil_tmp27 = obj->last_fenced_seqno;
 #line 130
   seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s", __cil_tmp22, tmp___3, tmp___2,
              __cil_tmp23, __cil_tmp24, __cil_tmp25, __cil_tmp26, __cil_tmp27, tmp___1,
              tmp___0, tmp);
   }
   {
 #line 142
   __cil_tmp28 = obj->base.name;
 #line 142
   if (__cil_tmp28 != 0) {
     {
 #line 143
     __cil_tmp29 = obj->base.name;
 #line 143
     seq_printf(m, " (name: %d)", __cil_tmp29);
     }
   } else {
 
   }
   }
   {
 #line 144
   __cil_tmp30 = (unsigned char *)obj;
 #line 144
   __cil_tmp31 = __cil_tmp30 + 224UL;
 #line 144
   __cil_tmp32 = *__cil_tmp31;
 #line 144
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 144
   if (__cil_tmp33 != 248U) {
     {
 #line 145
     __cil_tmp34 = obj->fence_reg;
 #line 145
     __cil_tmp35 = (int )__cil_tmp34;
 #line 145
     seq_printf(m, " (fence: %d)", __cil_tmp35);
     }
   } else {
 
   }
   }
   {
 #line 146
   __cil_tmp36 = (struct drm_mm_node *)0;
 #line 146
   __cil_tmp37 = (unsigned long )__cil_tmp36;
 #line 146
   __cil_tmp38 = obj->gtt_space;
 #line 146
   __cil_tmp39 = (unsigned long )__cil_tmp38;
 #line 146
   if (__cil_tmp39 != __cil_tmp37) {
     {
 #line 147
     __cil_tmp40 = obj->gtt_offset;
 #line 147
     __cil_tmp41 = obj->gtt_space;
 #line 147
     __cil_tmp42 = __cil_tmp41->size;
 #line 147
     __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 147
     seq_printf(m, " (gtt offset: %08x, size: %08x)", __cil_tmp40, __cil_tmp43);
     }
   } else {
 
   }
   }
   {
 #line 149
   __cil_tmp44 = (unsigned char *)obj;
 #line 149
   __cil_tmp45 = __cil_tmp44 + 226UL;
 #line 149
   __cil_tmp46 = *__cil_tmp45;
 #line 149
   __cil_tmp47 = (unsigned int )__cil_tmp46;
 #line 149
   if (__cil_tmp47 != 0U) {
 #line 149
     goto _L;
   } else {
     {
 #line 149
     __cil_tmp48 = (unsigned char *)obj;
 #line 149
     __cil_tmp49 = __cil_tmp48 + 226UL;
 #line 149
     __cil_tmp50 = *__cil_tmp49;
 #line 149
     __cil_tmp51 = (unsigned int )__cil_tmp50;
 #line 149
     if (__cil_tmp51 != 0U) {
       _L: 
 #line 150
       t = (char *)(& s);
       {
 #line 151
       __cil_tmp52 = (unsigned char *)obj;
 #line 151
       __cil_tmp53 = __cil_tmp52 + 226UL;
 #line 151
       __cil_tmp54 = *__cil_tmp53;
 #line 151
       __cil_tmp55 = (unsigned int )__cil_tmp54;
 #line 151
       if (__cil_tmp55 != 0U) {
 #line 152
         tmp___4 = t;
 #line 152
         t = t + 1;
 #line 152
         *tmp___4 = (char)112;
       } else {
 
       }
       }
       {
 #line 153
       __cil_tmp56 = (unsigned char *)obj;
 #line 153
       __cil_tmp57 = __cil_tmp56 + 226UL;
 #line 153
       __cil_tmp58 = *__cil_tmp57;
 #line 153
       __cil_tmp59 = (unsigned int )__cil_tmp58;
 #line 153
       if (__cil_tmp59 != 0U) {
 #line 154
         tmp___5 = t;
 #line 154
         t = t + 1;
 #line 154
         *tmp___5 = (char)102;
       } else {
 
       }
       }
       {
 #line 155
       *t = (char)0;
 #line 156
       __cil_tmp60 = (char *)(& s);
 #line 156
       seq_printf(m, " (%s mappable)", __cil_tmp60);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 158
   __cil_tmp61 = (struct intel_ring_buffer *)0;
 #line 158
   __cil_tmp62 = (unsigned long )__cil_tmp61;
 #line 158
   __cil_tmp63 = obj->ring;
 #line 158
   __cil_tmp64 = (unsigned long )__cil_tmp63;
 #line 158
   if (__cil_tmp64 != __cil_tmp62) {
     {
 #line 159
     __cil_tmp65 = obj->ring;
 #line 159
     __cil_tmp66 = __cil_tmp65->name;
 #line 159
     seq_printf(m, " (%s)", __cil_tmp66);
     }
   } else {
 
   }
   }
 #line 160
   return;
 }
 }
 #line 162 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_object_list_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   uintptr_t list ;
   struct list_head *head ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_object *obj ;
   size_t total_obj_size ;
   size_t total_gtt_size ;
   int count ;
   int ret ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp15 ;
   struct drm_info_list *__cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_minor *__cil_tmp18 ;
   void *__cil_tmp19 ;
   struct mutex *__cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   struct mutex *__cil_tmp26 ;
   struct list_head *__cil_tmp27 ;
   struct drm_i915_gem_object *__cil_tmp28 ;
   size_t __cil_tmp29 ;
   struct drm_mm_node *__cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   struct list_head *__cil_tmp32 ;
   struct drm_i915_gem_object *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   struct list_head *__cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   struct mutex *__cil_tmp37 ;
 
   {
   {
 #line 164
   __cil_tmp15 = m->private;
 #line 164
   node = (struct drm_info_node *)__cil_tmp15;
 #line 165
   __cil_tmp16 = node->info_ent;
 #line 165
   __cil_tmp17 = __cil_tmp16->data;
 #line 165
   list = (unsigned long )__cil_tmp17;
 #line 167
   __cil_tmp18 = node->minor;
 #line 167
   dev = __cil_tmp18->dev;
 #line 168
   __cil_tmp19 = dev->dev_private;
 #line 168
   dev_priv = (drm_i915_private_t *)__cil_tmp19;
 #line 173
   __cil_tmp20 = & dev->struct_mutex;
 #line 173
   ret = mutex_lock_interruptible_nested(__cil_tmp20, 0U);
   }
 #line 174
   if (ret != 0) {
 #line 175
     return (ret);
   } else {
 
   }
   {
 #line 178
   __cil_tmp21 = (int )list;
 #line 178
   if (__cil_tmp21 == 0) {
 #line 178
     goto case_0;
   } else {
     {
 #line 182
     __cil_tmp22 = (int )list;
 #line 182
     if (__cil_tmp22 == 2) {
 #line 182
       goto case_2;
     } else {
       {
 #line 186
       __cil_tmp23 = (int )list;
 #line 186
       if (__cil_tmp23 == 3) {
 #line 186
         goto case_3;
       } else {
         {
 #line 190
         __cil_tmp24 = (int )list;
 #line 190
         if (__cil_tmp24 == 1) {
 #line 190
           goto case_1;
         } else {
           {
 #line 194
           __cil_tmp25 = (int )list;
 #line 194
           if (__cil_tmp25 == 4) {
 #line 194
             goto case_4;
           } else {
 #line 198
             goto switch_default;
 #line 177
             if (0) {
               case_0: 
               {
 #line 179
               seq_printf(m, "Active:\n");
 #line 180
               head = & dev_priv->mm.active_list;
               }
 #line 181
               goto ldv_37687;
               case_2: 
               {
 #line 183
               seq_printf(m, "Inactive:\n");
 #line 184
               head = & dev_priv->mm.inactive_list;
               }
 #line 185
               goto ldv_37687;
               case_3: 
               {
 #line 187
               seq_printf(m, "Pinned:\n");
 #line 188
               head = & dev_priv->mm.pinned_list;
               }
 #line 189
               goto ldv_37687;
               case_1: 
               {
 #line 191
               seq_printf(m, "Flushing:\n");
 #line 192
               head = & dev_priv->mm.flushing_list;
               }
 #line 193
               goto ldv_37687;
               case_4: 
               {
 #line 195
               seq_printf(m, "Deferred free:\n");
 #line 196
               head = & dev_priv->mm.deferred_free_list;
               }
 #line 197
               goto ldv_37687;
               switch_default: 
               {
 #line 199
               __cil_tmp26 = & dev->struct_mutex;
 #line 199
               mutex_unlock(__cil_tmp26);
               }
 #line 200
               return (-22);
             } else {
 
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_37687: 
 #line 203
   count = 0;
 #line 203
   total_gtt_size = 0UL;
 #line 203
   total_obj_size = total_gtt_size;
 #line 204
   __cil_tmp27 = head->next;
 #line 204
   __mptr = (struct list_head  const  *)__cil_tmp27;
 #line 204
   __cil_tmp28 = (struct drm_i915_gem_object *)__mptr;
 #line 204
   obj = __cil_tmp28 + 1152921504606846800UL;
 #line 204
   goto ldv_37698;
   ldv_37697: 
   {
 #line 205
   seq_printf(m, "   ");
 #line 206
   describe_obj(m, obj);
 #line 207
   seq_printf(m, "\n");
 #line 208
   __cil_tmp29 = obj->base.size;
 #line 208
   total_obj_size = __cil_tmp29 + total_obj_size;
 #line 209
   __cil_tmp30 = obj->gtt_space;
 #line 209
   __cil_tmp31 = __cil_tmp30->size;
 #line 209
   total_gtt_size = __cil_tmp31 + total_gtt_size;
 #line 210
   count = count + 1;
 #line 204
   __cil_tmp32 = obj->mm_list.next;
 #line 204
   __mptr___0 = (struct list_head  const  *)__cil_tmp32;
 #line 204
   __cil_tmp33 = (struct drm_i915_gem_object *)__mptr___0;
 #line 204
   obj = __cil_tmp33 + 1152921504606846800UL;
   }
   ldv_37698: ;
   {
 #line 204
   __cil_tmp34 = (unsigned long )head;
 #line 204
   __cil_tmp35 = & obj->mm_list;
 #line 204
   __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 204
   if (__cil_tmp36 != __cil_tmp34) {
 #line 205
     goto ldv_37697;
   } else {
 #line 207
     goto ldv_37699;
   }
   }
   ldv_37699: 
   {
 #line 212
   __cil_tmp37 = & dev->struct_mutex;
 #line 212
   mutex_unlock(__cil_tmp37);
 #line 214
   seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", count, total_obj_size,
              total_gtt_size);
   }
 #line 216
   return (0);
 }
 }
 #line 230 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_object_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   u32 count ;
   u32 mappable_count ;
   size_t size ;
   size_t mappable_size ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   struct list_head  const  *__mptr___2 ;
   struct list_head  const  *__mptr___3 ;
   struct list_head  const  *__mptr___4 ;
   struct list_head  const  *__mptr___5 ;
   struct list_head  const  *__mptr___6 ;
   struct list_head  const  *__mptr___7 ;
   struct list_head  const  *__mptr___8 ;
   struct list_head  const  *__mptr___9 ;
   struct list_head  const  *__mptr___10 ;
   struct list_head  const  *__mptr___11 ;
   struct list_head  const  *__mptr___12 ;
   void *__cil_tmp26 ;
   struct drm_minor *__cil_tmp27 ;
   void *__cil_tmp28 ;
   struct mutex *__cil_tmp29 ;
   u32 __cil_tmp30 ;
   size_t __cil_tmp31 ;
   struct list_head *__cil_tmp32 ;
   struct drm_i915_gem_object *__cil_tmp33 ;
   struct drm_mm_node *__cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned char *__cil_tmp36 ;
   unsigned char *__cil_tmp37 ;
   unsigned char __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   struct drm_mm_node *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   struct list_head *__cil_tmp42 ;
   struct drm_i915_gem_object *__cil_tmp43 ;
   struct list_head *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct list_head *__cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   struct list_head *__cil_tmp48 ;
   struct drm_i915_gem_object *__cil_tmp49 ;
   struct drm_mm_node *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   unsigned char *__cil_tmp52 ;
   unsigned char *__cil_tmp53 ;
   unsigned char __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   struct drm_mm_node *__cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   struct list_head *__cil_tmp58 ;
   struct drm_i915_gem_object *__cil_tmp59 ;
   struct list_head *__cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   struct list_head *__cil_tmp62 ;
   unsigned long __cil_tmp63 ;
   struct list_head *__cil_tmp64 ;
   struct drm_i915_gem_object *__cil_tmp65 ;
   struct drm_mm_node *__cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   unsigned char *__cil_tmp68 ;
   unsigned char *__cil_tmp69 ;
   unsigned char __cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   struct drm_mm_node *__cil_tmp72 ;
   unsigned long __cil_tmp73 ;
   struct list_head *__cil_tmp74 ;
   struct drm_i915_gem_object *__cil_tmp75 ;
   struct list_head *__cil_tmp76 ;
   unsigned long __cil_tmp77 ;
   struct list_head *__cil_tmp78 ;
   unsigned long __cil_tmp79 ;
   struct list_head *__cil_tmp80 ;
   struct drm_i915_gem_object *__cil_tmp81 ;
   struct drm_mm_node *__cil_tmp82 ;
   unsigned long __cil_tmp83 ;
   unsigned char *__cil_tmp84 ;
   unsigned char *__cil_tmp85 ;
   unsigned char __cil_tmp86 ;
   unsigned int __cil_tmp87 ;
   struct drm_mm_node *__cil_tmp88 ;
   unsigned long __cil_tmp89 ;
   struct list_head *__cil_tmp90 ;
   struct drm_i915_gem_object *__cil_tmp91 ;
   struct list_head *__cil_tmp92 ;
   unsigned long __cil_tmp93 ;
   struct list_head *__cil_tmp94 ;
   unsigned long __cil_tmp95 ;
   struct list_head *__cil_tmp96 ;
   struct drm_i915_gem_object *__cil_tmp97 ;
   struct drm_mm_node *__cil_tmp98 ;
   unsigned long __cil_tmp99 ;
   unsigned char *__cil_tmp100 ;
   unsigned char *__cil_tmp101 ;
   unsigned char __cil_tmp102 ;
   unsigned int __cil_tmp103 ;
   struct drm_mm_node *__cil_tmp104 ;
   unsigned long __cil_tmp105 ;
   struct list_head *__cil_tmp106 ;
   struct drm_i915_gem_object *__cil_tmp107 ;
   struct list_head *__cil_tmp108 ;
   unsigned long __cil_tmp109 ;
   struct list_head *__cil_tmp110 ;
   unsigned long __cil_tmp111 ;
   struct list_head *__cil_tmp112 ;
   struct drm_i915_gem_object *__cil_tmp113 ;
   struct drm_mm_node *__cil_tmp114 ;
   unsigned long __cil_tmp115 ;
   unsigned char *__cil_tmp116 ;
   unsigned char *__cil_tmp117 ;
   unsigned char __cil_tmp118 ;
   unsigned int __cil_tmp119 ;
   struct drm_mm_node *__cil_tmp120 ;
   unsigned long __cil_tmp121 ;
   struct list_head *__cil_tmp122 ;
   struct drm_i915_gem_object *__cil_tmp123 ;
   struct list_head *__cil_tmp124 ;
   unsigned long __cil_tmp125 ;
   struct list_head *__cil_tmp126 ;
   unsigned long __cil_tmp127 ;
   struct list_head *__cil_tmp128 ;
   struct drm_i915_gem_object *__cil_tmp129 ;
   unsigned char *__cil_tmp130 ;
   unsigned char *__cil_tmp131 ;
   unsigned char __cil_tmp132 ;
   unsigned int __cil_tmp133 ;
   struct drm_mm_node *__cil_tmp134 ;
   unsigned long __cil_tmp135 ;
   unsigned char *__cil_tmp136 ;
   unsigned char *__cil_tmp137 ;
   unsigned char __cil_tmp138 ;
   unsigned int __cil_tmp139 ;
   struct drm_mm_node *__cil_tmp140 ;
   unsigned long __cil_tmp141 ;
   struct list_head *__cil_tmp142 ;
   struct drm_i915_gem_object *__cil_tmp143 ;
   struct list_head *__cil_tmp144 ;
   unsigned long __cil_tmp145 ;
   struct list_head *__cil_tmp146 ;
   unsigned long __cil_tmp147 ;
   size_t __cil_tmp148 ;
   size_t __cil_tmp149 ;
   struct mutex *__cil_tmp150 ;
 
   {
   {
 #line 232
   __cil_tmp26 = m->private;
 #line 232
   node = (struct drm_info_node *)__cil_tmp26;
 #line 233
   __cil_tmp27 = node->minor;
 #line 233
   dev = __cil_tmp27->dev;
 #line 234
   __cil_tmp28 = dev->dev_private;
 #line 234
   dev_priv = (struct drm_i915_private *)__cil_tmp28;
 #line 240
   __cil_tmp29 = & dev->struct_mutex;
 #line 240
   ret = mutex_lock_interruptible_nested(__cil_tmp29, 0U);
   }
 #line 241
   if (ret != 0) {
 #line 242
     return (ret);
   } else {
 
   }
   {
 #line 244
   __cil_tmp30 = dev_priv->mm.object_count;
 #line 244
   __cil_tmp31 = dev_priv->mm.object_memory;
 #line 244
   seq_printf(m, "%u objects, %zu bytes\n", __cil_tmp30, __cil_tmp31);
 #line 248
   mappable_count = 0U;
 #line 248
   mappable_size = 0UL;
 #line 248
   count = (u32 )mappable_size;
 #line 248
   size = (size_t )count;
 #line 249
   __cil_tmp32 = dev_priv->mm.gtt_list.next;
 #line 249
   __mptr = (struct list_head  const  *)__cil_tmp32;
 #line 249
   __cil_tmp33 = (struct drm_i915_gem_object *)__mptr;
 #line 249
   obj = __cil_tmp33 + 1152921504606846832UL;
   }
 #line 249
   goto ldv_37718;
   ldv_37717: 
 #line 249
   __cil_tmp34 = obj->gtt_space;
 #line 249
   __cil_tmp35 = __cil_tmp34->size;
 #line 249
   size = __cil_tmp35 + size;
 #line 249
   count = count + 1U;
   {
 #line 249
   __cil_tmp36 = (unsigned char *)obj;
 #line 249
   __cil_tmp37 = __cil_tmp36 + 226UL;
 #line 249
   __cil_tmp38 = *__cil_tmp37;
 #line 249
   __cil_tmp39 = (unsigned int )__cil_tmp38;
 #line 249
   if (__cil_tmp39 != 0U) {
 #line 249
     __cil_tmp40 = obj->gtt_space;
 #line 249
     __cil_tmp41 = __cil_tmp40->size;
 #line 249
     mappable_size = __cil_tmp41 + mappable_size;
 #line 249
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 249
   __cil_tmp42 = obj->gtt_list.next;
 #line 249
   __mptr___0 = (struct list_head  const  *)__cil_tmp42;
 #line 249
   __cil_tmp43 = (struct drm_i915_gem_object *)__mptr___0;
 #line 249
   obj = __cil_tmp43 + 1152921504606846832UL;
   ldv_37718: ;
   {
 #line 249
   __cil_tmp44 = & dev_priv->mm.gtt_list;
 #line 249
   __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 249
   __cil_tmp46 = & obj->gtt_list;
 #line 249
   __cil_tmp47 = (unsigned long )__cil_tmp46;
 #line 249
   if (__cil_tmp47 != __cil_tmp45) {
 #line 250
     goto ldv_37717;
   } else {
 #line 252
     goto ldv_37719;
   }
   }
   ldv_37719: 
   {
 #line 250
   seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", count, mappable_count,
              size, mappable_size);
 #line 253
   mappable_count = 0U;
 #line 253
   mappable_size = 0UL;
 #line 253
   count = (u32 )mappable_size;
 #line 253
   size = (size_t )count;
 #line 254
   __cil_tmp48 = dev_priv->mm.active_list.next;
 #line 254
   __mptr___1 = (struct list_head  const  *)__cil_tmp48;
 #line 254
   __cil_tmp49 = (struct drm_i915_gem_object *)__mptr___1;
 #line 254
   obj = __cil_tmp49 + 1152921504606846800UL;
   }
 #line 254
   goto ldv_37725;
   ldv_37724: 
 #line 254
   __cil_tmp50 = obj->gtt_space;
 #line 254
   __cil_tmp51 = __cil_tmp50->size;
 #line 254
   size = __cil_tmp51 + size;
 #line 254
   count = count + 1U;
   {
 #line 254
   __cil_tmp52 = (unsigned char *)obj;
 #line 254
   __cil_tmp53 = __cil_tmp52 + 226UL;
 #line 254
   __cil_tmp54 = *__cil_tmp53;
 #line 254
   __cil_tmp55 = (unsigned int )__cil_tmp54;
 #line 254
   if (__cil_tmp55 != 0U) {
 #line 254
     __cil_tmp56 = obj->gtt_space;
 #line 254
     __cil_tmp57 = __cil_tmp56->size;
 #line 254
     mappable_size = __cil_tmp57 + mappable_size;
 #line 254
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 254
   __cil_tmp58 = obj->mm_list.next;
 #line 254
   __mptr___2 = (struct list_head  const  *)__cil_tmp58;
 #line 254
   __cil_tmp59 = (struct drm_i915_gem_object *)__mptr___2;
 #line 254
   obj = __cil_tmp59 + 1152921504606846800UL;
   ldv_37725: ;
   {
 #line 254
   __cil_tmp60 = & dev_priv->mm.active_list;
 #line 254
   __cil_tmp61 = (unsigned long )__cil_tmp60;
 #line 254
   __cil_tmp62 = & obj->mm_list;
 #line 254
   __cil_tmp63 = (unsigned long )__cil_tmp62;
 #line 254
   if (__cil_tmp63 != __cil_tmp61) {
 #line 255
     goto ldv_37724;
   } else {
 #line 257
     goto ldv_37726;
   }
   }
   ldv_37726: 
 #line 255
   __cil_tmp64 = dev_priv->mm.flushing_list.next;
 #line 255
   __mptr___3 = (struct list_head  const  *)__cil_tmp64;
 #line 255
   __cil_tmp65 = (struct drm_i915_gem_object *)__mptr___3;
 #line 255
   obj = __cil_tmp65 + 1152921504606846800UL;
 #line 255
   goto ldv_37732;
   ldv_37731: 
 #line 255
   __cil_tmp66 = obj->gtt_space;
 #line 255
   __cil_tmp67 = __cil_tmp66->size;
 #line 255
   size = __cil_tmp67 + size;
 #line 255
   count = count + 1U;
   {
 #line 255
   __cil_tmp68 = (unsigned char *)obj;
 #line 255
   __cil_tmp69 = __cil_tmp68 + 226UL;
 #line 255
   __cil_tmp70 = *__cil_tmp69;
 #line 255
   __cil_tmp71 = (unsigned int )__cil_tmp70;
 #line 255
   if (__cil_tmp71 != 0U) {
 #line 255
     __cil_tmp72 = obj->gtt_space;
 #line 255
     __cil_tmp73 = __cil_tmp72->size;
 #line 255
     mappable_size = __cil_tmp73 + mappable_size;
 #line 255
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 255
   __cil_tmp74 = obj->mm_list.next;
 #line 255
   __mptr___4 = (struct list_head  const  *)__cil_tmp74;
 #line 255
   __cil_tmp75 = (struct drm_i915_gem_object *)__mptr___4;
 #line 255
   obj = __cil_tmp75 + 1152921504606846800UL;
   ldv_37732: ;
   {
 #line 255
   __cil_tmp76 = & dev_priv->mm.flushing_list;
 #line 255
   __cil_tmp77 = (unsigned long )__cil_tmp76;
 #line 255
   __cil_tmp78 = & obj->mm_list;
 #line 255
   __cil_tmp79 = (unsigned long )__cil_tmp78;
 #line 255
   if (__cil_tmp79 != __cil_tmp77) {
 #line 256
     goto ldv_37731;
   } else {
 #line 258
     goto ldv_37733;
   }
   }
   ldv_37733: 
   {
 #line 256
   seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n", count, mappable_count,
              size, mappable_size);
 #line 259
   mappable_count = 0U;
 #line 259
   mappable_size = 0UL;
 #line 259
   count = (u32 )mappable_size;
 #line 259
   size = (size_t )count;
 #line 260
   __cil_tmp80 = dev_priv->mm.pinned_list.next;
 #line 260
   __mptr___5 = (struct list_head  const  *)__cil_tmp80;
 #line 260
   __cil_tmp81 = (struct drm_i915_gem_object *)__mptr___5;
 #line 260
   obj = __cil_tmp81 + 1152921504606846800UL;
   }
 #line 260
   goto ldv_37739;
   ldv_37738: 
 #line 260
   __cil_tmp82 = obj->gtt_space;
 #line 260
   __cil_tmp83 = __cil_tmp82->size;
 #line 260
   size = __cil_tmp83 + size;
 #line 260
   count = count + 1U;
   {
 #line 260
   __cil_tmp84 = (unsigned char *)obj;
 #line 260
   __cil_tmp85 = __cil_tmp84 + 226UL;
 #line 260
   __cil_tmp86 = *__cil_tmp85;
 #line 260
   __cil_tmp87 = (unsigned int )__cil_tmp86;
 #line 260
   if (__cil_tmp87 != 0U) {
 #line 260
     __cil_tmp88 = obj->gtt_space;
 #line 260
     __cil_tmp89 = __cil_tmp88->size;
 #line 260
     mappable_size = __cil_tmp89 + mappable_size;
 #line 260
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 260
   __cil_tmp90 = obj->mm_list.next;
 #line 260
   __mptr___6 = (struct list_head  const  *)__cil_tmp90;
 #line 260
   __cil_tmp91 = (struct drm_i915_gem_object *)__mptr___6;
 #line 260
   obj = __cil_tmp91 + 1152921504606846800UL;
   ldv_37739: ;
   {
 #line 260
   __cil_tmp92 = & dev_priv->mm.pinned_list;
 #line 260
   __cil_tmp93 = (unsigned long )__cil_tmp92;
 #line 260
   __cil_tmp94 = & obj->mm_list;
 #line 260
   __cil_tmp95 = (unsigned long )__cil_tmp94;
 #line 260
   if (__cil_tmp95 != __cil_tmp93) {
 #line 261
     goto ldv_37738;
   } else {
 #line 263
     goto ldv_37740;
   }
   }
   ldv_37740: 
   {
 #line 261
   seq_printf(m, "  %u [%u] pinned objects, %zu [%zu] bytes\n", count, mappable_count,
              size, mappable_size);
 #line 264
   mappable_count = 0U;
 #line 264
   mappable_size = 0UL;
 #line 264
   count = (u32 )mappable_size;
 #line 264
   size = (size_t )count;
 #line 265
   __cil_tmp96 = dev_priv->mm.inactive_list.next;
 #line 265
   __mptr___7 = (struct list_head  const  *)__cil_tmp96;
 #line 265
   __cil_tmp97 = (struct drm_i915_gem_object *)__mptr___7;
 #line 265
   obj = __cil_tmp97 + 1152921504606846800UL;
   }
 #line 265
   goto ldv_37746;
   ldv_37745: 
 #line 265
   __cil_tmp98 = obj->gtt_space;
 #line 265
   __cil_tmp99 = __cil_tmp98->size;
 #line 265
   size = __cil_tmp99 + size;
 #line 265
   count = count + 1U;
   {
 #line 265
   __cil_tmp100 = (unsigned char *)obj;
 #line 265
   __cil_tmp101 = __cil_tmp100 + 226UL;
 #line 265
   __cil_tmp102 = *__cil_tmp101;
 #line 265
   __cil_tmp103 = (unsigned int )__cil_tmp102;
 #line 265
   if (__cil_tmp103 != 0U) {
 #line 265
     __cil_tmp104 = obj->gtt_space;
 #line 265
     __cil_tmp105 = __cil_tmp104->size;
 #line 265
     mappable_size = __cil_tmp105 + mappable_size;
 #line 265
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 265
   __cil_tmp106 = obj->mm_list.next;
 #line 265
   __mptr___8 = (struct list_head  const  *)__cil_tmp106;
 #line 265
   __cil_tmp107 = (struct drm_i915_gem_object *)__mptr___8;
 #line 265
   obj = __cil_tmp107 + 1152921504606846800UL;
   ldv_37746: ;
   {
 #line 265
   __cil_tmp108 = & dev_priv->mm.inactive_list;
 #line 265
   __cil_tmp109 = (unsigned long )__cil_tmp108;
 #line 265
   __cil_tmp110 = & obj->mm_list;
 #line 265
   __cil_tmp111 = (unsigned long )__cil_tmp110;
 #line 265
   if (__cil_tmp111 != __cil_tmp109) {
 #line 266
     goto ldv_37745;
   } else {
 #line 268
     goto ldv_37747;
   }
   }
   ldv_37747: 
   {
 #line 266
   seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n", count, mappable_count,
              size, mappable_size);
 #line 269
   mappable_count = 0U;
 #line 269
   mappable_size = 0UL;
 #line 269
   count = (u32 )mappable_size;
 #line 269
   size = (size_t )count;
 #line 270
   __cil_tmp112 = dev_priv->mm.deferred_free_list.next;
 #line 270
   __mptr___9 = (struct list_head  const  *)__cil_tmp112;
 #line 270
   __cil_tmp113 = (struct drm_i915_gem_object *)__mptr___9;
 #line 270
   obj = __cil_tmp113 + 1152921504606846800UL;
   }
 #line 270
   goto ldv_37753;
   ldv_37752: 
 #line 270
   __cil_tmp114 = obj->gtt_space;
 #line 270
   __cil_tmp115 = __cil_tmp114->size;
 #line 270
   size = __cil_tmp115 + size;
 #line 270
   count = count + 1U;
   {
 #line 270
   __cil_tmp116 = (unsigned char *)obj;
 #line 270
   __cil_tmp117 = __cil_tmp116 + 226UL;
 #line 270
   __cil_tmp118 = *__cil_tmp117;
 #line 270
   __cil_tmp119 = (unsigned int )__cil_tmp118;
 #line 270
   if (__cil_tmp119 != 0U) {
 #line 270
     __cil_tmp120 = obj->gtt_space;
 #line 270
     __cil_tmp121 = __cil_tmp120->size;
 #line 270
     mappable_size = __cil_tmp121 + mappable_size;
 #line 270
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 270
   __cil_tmp122 = obj->mm_list.next;
 #line 270
   __mptr___10 = (struct list_head  const  *)__cil_tmp122;
 #line 270
   __cil_tmp123 = (struct drm_i915_gem_object *)__mptr___10;
 #line 270
   obj = __cil_tmp123 + 1152921504606846800UL;
   ldv_37753: ;
   {
 #line 270
   __cil_tmp124 = & dev_priv->mm.deferred_free_list;
 #line 270
   __cil_tmp125 = (unsigned long )__cil_tmp124;
 #line 270
   __cil_tmp126 = & obj->mm_list;
 #line 270
   __cil_tmp127 = (unsigned long )__cil_tmp126;
 #line 270
   if (__cil_tmp127 != __cil_tmp125) {
 #line 271
     goto ldv_37752;
   } else {
 #line 273
     goto ldv_37754;
   }
   }
   ldv_37754: 
   {
 #line 271
   seq_printf(m, "  %u [%u] freed objects, %zu [%zu] bytes\n", count, mappable_count,
              size, mappable_size);
 #line 274
   mappable_count = 0U;
 #line 274
   mappable_size = 0UL;
 #line 274
   count = (u32 )mappable_size;
 #line 274
   size = (size_t )count;
 #line 275
   __cil_tmp128 = dev_priv->mm.gtt_list.next;
 #line 275
   __mptr___11 = (struct list_head  const  *)__cil_tmp128;
 #line 275
   __cil_tmp129 = (struct drm_i915_gem_object *)__mptr___11;
 #line 275
   obj = __cil_tmp129 + 1152921504606846832UL;
   }
 #line 275
   goto ldv_37760;
   ldv_37759: ;
   {
 #line 276
   __cil_tmp130 = (unsigned char *)obj;
 #line 276
   __cil_tmp131 = __cil_tmp130 + 226UL;
 #line 276
   __cil_tmp132 = *__cil_tmp131;
 #line 276
   __cil_tmp133 = (unsigned int )__cil_tmp132;
 #line 276
   if (__cil_tmp133 != 0U) {
 #line 277
     __cil_tmp134 = obj->gtt_space;
 #line 277
     __cil_tmp135 = __cil_tmp134->size;
 #line 277
     size = __cil_tmp135 + size;
 #line 278
     count = count + 1U;
   } else {
 
   }
   }
   {
 #line 280
   __cil_tmp136 = (unsigned char *)obj;
 #line 280
   __cil_tmp137 = __cil_tmp136 + 226UL;
 #line 280
   __cil_tmp138 = *__cil_tmp137;
 #line 280
   __cil_tmp139 = (unsigned int )__cil_tmp138;
 #line 280
   if (__cil_tmp139 != 0U) {
 #line 281
     __cil_tmp140 = obj->gtt_space;
 #line 281
     __cil_tmp141 = __cil_tmp140->size;
 #line 281
     mappable_size = __cil_tmp141 + mappable_size;
 #line 282
     mappable_count = mappable_count + 1U;
   } else {
 
   }
   }
 #line 275
   __cil_tmp142 = obj->gtt_list.next;
 #line 275
   __mptr___12 = (struct list_head  const  *)__cil_tmp142;
 #line 275
   __cil_tmp143 = (struct drm_i915_gem_object *)__mptr___12;
 #line 275
   obj = __cil_tmp143 + 1152921504606846832UL;
   ldv_37760: ;
   {
 #line 275
   __cil_tmp144 = & dev_priv->mm.gtt_list;
 #line 275
   __cil_tmp145 = (unsigned long )__cil_tmp144;
 #line 275
   __cil_tmp146 = & obj->gtt_list;
 #line 275
   __cil_tmp147 = (unsigned long )__cil_tmp146;
 #line 275
   if (__cil_tmp147 != __cil_tmp145) {
 #line 276
     goto ldv_37759;
   } else {
 #line 278
     goto ldv_37761;
   }
   }
   ldv_37761: 
   {
 #line 285
   seq_printf(m, "%u pinned mappable objects, %zu bytes\n", mappable_count, mappable_size);
 #line 287
   seq_printf(m, "%u fault mappable objects, %zu bytes\n", count, size);
 #line 290
   __cil_tmp148 = dev_priv->mm.gtt_total;
 #line 290
   __cil_tmp149 = dev_priv->mm.mappable_gtt_total;
 #line 290
   seq_printf(m, "%zu [%zu] gtt total\n", __cil_tmp148, __cil_tmp149);
 #line 293
   __cil_tmp150 = & dev->struct_mutex;
 #line 293
   mutex_unlock(__cil_tmp150);
   }
 #line 295
   return (0);
 }
 }
 #line 298 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_gtt_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   size_t total_obj_size ;
   size_t total_gtt_size ;
   int count ;
   int ret ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp13 ;
   struct drm_minor *__cil_tmp14 ;
   void *__cil_tmp15 ;
   struct mutex *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct drm_i915_gem_object *__cil_tmp18 ;
   size_t __cil_tmp19 ;
   struct drm_mm_node *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct drm_i915_gem_object *__cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct list_head *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct mutex *__cil_tmp28 ;
 
   {
   {
 #line 300
   __cil_tmp13 = m->private;
 #line 300
   node = (struct drm_info_node *)__cil_tmp13;
 #line 301
   __cil_tmp14 = node->minor;
 #line 301
   dev = __cil_tmp14->dev;
 #line 302
   __cil_tmp15 = dev->dev_private;
 #line 302
   dev_priv = (struct drm_i915_private *)__cil_tmp15;
 #line 307
   __cil_tmp16 = & dev->struct_mutex;
 #line 307
   ret = mutex_lock_interruptible_nested(__cil_tmp16, 0U);
   }
 #line 308
   if (ret != 0) {
 #line 309
     return (ret);
   } else {
 
   }
 #line 311
   count = 0;
 #line 311
   total_gtt_size = 0UL;
 #line 311
   total_obj_size = total_gtt_size;
 #line 312
   __cil_tmp17 = dev_priv->mm.gtt_list.next;
 #line 312
   __mptr = (struct list_head  const  *)__cil_tmp17;
 #line 312
   __cil_tmp18 = (struct drm_i915_gem_object *)__mptr;
 #line 312
   obj = __cil_tmp18 + 1152921504606846832UL;
 #line 312
   goto ldv_37779;
   ldv_37778: 
   {
 #line 313
   seq_printf(m, "   ");
 #line 314
   describe_obj(m, obj);
 #line 315
   seq_printf(m, "\n");
 #line 316
   __cil_tmp19 = obj->base.size;
 #line 316
   total_obj_size = __cil_tmp19 + total_obj_size;
 #line 317
   __cil_tmp20 = obj->gtt_space;
 #line 317
   __cil_tmp21 = __cil_tmp20->size;
 #line 317
   total_gtt_size = __cil_tmp21 + total_gtt_size;
 #line 318
   count = count + 1;
 #line 312
   __cil_tmp22 = obj->gtt_list.next;
 #line 312
   __mptr___0 = (struct list_head  const  *)__cil_tmp22;
 #line 312
   __cil_tmp23 = (struct drm_i915_gem_object *)__mptr___0;
 #line 312
   obj = __cil_tmp23 + 1152921504606846832UL;
   }
   ldv_37779: ;
   {
 #line 312
   __cil_tmp24 = & dev_priv->mm.gtt_list;
 #line 312
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 312
   __cil_tmp26 = & obj->gtt_list;
 #line 312
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 312
   if (__cil_tmp27 != __cil_tmp25) {
 #line 313
     goto ldv_37778;
   } else {
 #line 315
     goto ldv_37780;
   }
   }
   ldv_37780: 
   {
 #line 321
   __cil_tmp28 = & dev->struct_mutex;
 #line 321
   mutex_unlock(__cil_tmp28);
 #line 323
   seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", count, total_obj_size,
              total_gtt_size);
   }
 #line 326
   return (0);
 }
 }
 #line 330 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_pageflip_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   unsigned long flags ;
   struct intel_crtc *crtc ;
   struct list_head  const  *__mptr ;
   char pipe ;
   char plane ;
   struct intel_unpin_work *work ;
   raw_spinlock_t *tmp ;
   struct drm_i915_gem_object *obj ;
   struct drm_i915_gem_object *obj___0 ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp15 ;
   struct drm_minor *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct intel_crtc *__cil_tmp18 ;
   enum pipe __cil_tmp19 ;
   unsigned char __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   char __cil_tmp23 ;
   enum plane __cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   char __cil_tmp28 ;
   spinlock_t *__cil_tmp29 ;
   struct intel_unpin_work *__cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   bool __cil_tmp40 ;
   int __cil_tmp41 ;
   struct drm_i915_gem_object *__cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   struct drm_i915_gem_object *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct drm_i915_gem_object *__cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   uint32_t __cil_tmp49 ;
   struct drm_i915_gem_object *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   struct drm_i915_gem_object *__cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   struct drm_i915_gem_object *__cil_tmp54 ;
   unsigned long __cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   uint32_t __cil_tmp57 ;
   spinlock_t *__cil_tmp58 ;
   struct list_head *__cil_tmp59 ;
   struct intel_crtc *__cil_tmp60 ;
   struct list_head *__cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   struct list_head *__cil_tmp63 ;
   unsigned long __cil_tmp64 ;
 
   {
 #line 332
   __cil_tmp15 = m->private;
 #line 332
   node = (struct drm_info_node *)__cil_tmp15;
 #line 333
   __cil_tmp16 = node->minor;
 #line 333
   dev = __cil_tmp16->dev;
 #line 337
   __cil_tmp17 = dev->mode_config.crtc_list.next;
 #line 337
   __mptr = (struct list_head  const  *)__cil_tmp17;
 #line 337
   __cil_tmp18 = (struct intel_crtc *)__mptr;
 #line 337
   crtc = __cil_tmp18 + 1152921504606846968UL;
 #line 337
   goto ldv_37802;
   ldv_37801: 
   {
 #line 338
   __cil_tmp19 = crtc->pipe;
 #line 338
   __cil_tmp20 = (unsigned char )__cil_tmp19;
 #line 338
   __cil_tmp21 = (unsigned int )__cil_tmp20;
 #line 338
   __cil_tmp22 = __cil_tmp21 + 65U;
 #line 338
   __cil_tmp23 = (char const   )__cil_tmp22;
 #line 338
   pipe = (char )__cil_tmp23;
 #line 339
   __cil_tmp24 = crtc->plane;
 #line 339
   __cil_tmp25 = (unsigned char )__cil_tmp24;
 #line 339
   __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 339
   __cil_tmp27 = __cil_tmp26 + 65U;
 #line 339
   __cil_tmp28 = (char const   )__cil_tmp27;
 #line 339
   plane = (char )__cil_tmp28;
 #line 342
   __cil_tmp29 = & dev->event_lock;
 #line 342
   tmp = spinlock_check(__cil_tmp29);
 #line 342
   flags = _raw_spin_lock_irqsave(tmp);
 #line 343
   work = crtc->unpin_work;
   }
   {
 #line 344
   __cil_tmp30 = (struct intel_unpin_work *)0;
 #line 344
   __cil_tmp31 = (unsigned long )__cil_tmp30;
 #line 344
   __cil_tmp32 = (unsigned long )work;
 #line 344
   if (__cil_tmp32 == __cil_tmp31) {
     {
 #line 345
     __cil_tmp33 = (int )pipe;
 #line 345
     __cil_tmp34 = (int )plane;
 #line 345
     seq_printf(m, "No flip due on pipe %c (plane %c)\n", __cil_tmp33, __cil_tmp34);
     }
   } else {
     {
 #line 348
     __cil_tmp35 = work->pending;
 #line 348
     if (__cil_tmp35 == 0) {
       {
 #line 349
       __cil_tmp36 = (int )pipe;
 #line 349
       __cil_tmp37 = (int )plane;
 #line 349
       seq_printf(m, "Flip queued on pipe %c (plane %c)\n", __cil_tmp36, __cil_tmp37);
       }
     } else {
       {
 #line 352
       __cil_tmp38 = (int )pipe;
 #line 352
       __cil_tmp39 = (int )plane;
 #line 352
       seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", __cil_tmp38,
                  __cil_tmp39);
       }
     }
     }
     {
 #line 355
     __cil_tmp40 = work->enable_stall_check;
 #line 355
     if ((int )__cil_tmp40) {
       {
 #line 356
       seq_printf(m, "Stall check enabled, ");
       }
     } else {
       {
 #line 358
       seq_printf(m, "Stall check waiting for page flip ioctl, ");
       }
     }
     }
     {
 #line 359
     __cil_tmp41 = work->pending;
 #line 359
     seq_printf(m, "%d prepares\n", __cil_tmp41);
     }
     {
 #line 361
     __cil_tmp42 = (struct drm_i915_gem_object *)0;
 #line 361
     __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 361
     __cil_tmp44 = work->old_fb_obj;
 #line 361
     __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 361
     if (__cil_tmp45 != __cil_tmp43) {
 #line 362
       obj = work->old_fb_obj;
       {
 #line 363
       __cil_tmp46 = (struct drm_i915_gem_object *)0;
 #line 363
       __cil_tmp47 = (unsigned long )__cil_tmp46;
 #line 363
       __cil_tmp48 = (unsigned long )obj;
 #line 363
       if (__cil_tmp48 != __cil_tmp47) {
         {
 #line 364
         __cil_tmp49 = obj->gtt_offset;
 #line 364
         seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", __cil_tmp49);
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
     {
 #line 366
     __cil_tmp50 = (struct drm_i915_gem_object *)0;
 #line 366
     __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 366
     __cil_tmp52 = work->pending_flip_obj;
 #line 366
     __cil_tmp53 = (unsigned long )__cil_tmp52;
 #line 366
     if (__cil_tmp53 != __cil_tmp51) {
 #line 367
       obj___0 = work->pending_flip_obj;
       {
 #line 368
       __cil_tmp54 = (struct drm_i915_gem_object *)0;
 #line 368
       __cil_tmp55 = (unsigned long )__cil_tmp54;
 #line 368
       __cil_tmp56 = (unsigned long )obj___0;
 #line 368
       if (__cil_tmp56 != __cil_tmp55) {
         {
 #line 369
         __cil_tmp57 = obj___0->gtt_offset;
 #line 369
         seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", __cil_tmp57);
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 372
   __cil_tmp58 = & dev->event_lock;
 #line 372
   spin_unlock_irqrestore(__cil_tmp58, flags);
 #line 337
   __cil_tmp59 = crtc->base.head.next;
 #line 337
   __mptr___0 = (struct list_head  const  *)__cil_tmp59;
 #line 337
   __cil_tmp60 = (struct intel_crtc *)__mptr___0;
 #line 337
   crtc = __cil_tmp60 + 1152921504606846968UL;
   }
   ldv_37802: ;
   {
 #line 337
   __cil_tmp61 = & dev->mode_config.crtc_list;
 #line 337
   __cil_tmp62 = (unsigned long )__cil_tmp61;
 #line 337
   __cil_tmp63 = & crtc->base.head;
 #line 337
   __cil_tmp64 = (unsigned long )__cil_tmp63;
 #line 337
   if (__cil_tmp64 != __cil_tmp62) {
 #line 338
     goto ldv_37801;
   } else {
 #line 340
     goto ldv_37803;
   }
   }
   ldv_37803: ;
 #line 375
   return (0);
 }
 }
 #line 378 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_request_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_request *gem_request ;
   int ret ;
   int count ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   int tmp ;
   struct list_head  const  *__mptr___1 ;
   struct list_head  const  *__mptr___2 ;
   int tmp___0 ;
   struct list_head  const  *__mptr___3 ;
   struct list_head  const  *__mptr___4 ;
   int tmp___1 ;
   void *__cil_tmp18 ;
   struct drm_minor *__cil_tmp19 ;
   void *__cil_tmp20 ;
   struct mutex *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct list_head  const  *__cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   struct drm_i915_gem_request *__cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   struct list_head *__cil_tmp32 ;
   struct drm_i915_gem_request *__cil_tmp33 ;
   struct list_head *__cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   struct list_head *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct list_head *__cil_tmp38 ;
   struct list_head  const  *__cil_tmp39 ;
   struct list_head *__cil_tmp40 ;
   struct drm_i915_gem_request *__cil_tmp41 ;
   uint32_t __cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   struct list_head *__cil_tmp48 ;
   struct drm_i915_gem_request *__cil_tmp49 ;
   struct list_head *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   struct list_head *__cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   struct list_head *__cil_tmp54 ;
   struct list_head  const  *__cil_tmp55 ;
   struct list_head *__cil_tmp56 ;
   struct drm_i915_gem_request *__cil_tmp57 ;
   uint32_t __cil_tmp58 ;
   unsigned long __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   int __cil_tmp63 ;
   struct list_head *__cil_tmp64 ;
   struct drm_i915_gem_request *__cil_tmp65 ;
   struct list_head *__cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   struct list_head *__cil_tmp68 ;
   unsigned long __cil_tmp69 ;
   struct mutex *__cil_tmp70 ;
 
   {
   {
 #line 380
   __cil_tmp18 = m->private;
 #line 380
   node = (struct drm_info_node *)__cil_tmp18;
 #line 381
   __cil_tmp19 = node->minor;
 #line 381
   dev = __cil_tmp19->dev;
 #line 382
   __cil_tmp20 = dev->dev_private;
 #line 382
   dev_priv = (drm_i915_private_t *)__cil_tmp20;
 #line 386
   __cil_tmp21 = & dev->struct_mutex;
 #line 386
   ret = mutex_lock_interruptible_nested(__cil_tmp21, 0U);
   }
 #line 387
   if (ret != 0) {
 #line 388
     return (ret);
   } else {
 
   }
   {
 #line 390
   count = 0;
 #line 391
   __cil_tmp22 = & dev_priv->ring[0].request_list;
 #line 391
   __cil_tmp23 = (struct list_head  const  *)__cil_tmp22;
 #line 391
   tmp = list_empty(__cil_tmp23);
   }
 #line 391
   if (tmp == 0) {
     {
 #line 392
     seq_printf(m, "Render requests:\n");
 #line 393
     __cil_tmp24 = dev_priv->ring[0].request_list.next;
 #line 393
     __mptr = (struct list_head  const  *)__cil_tmp24;
 #line 393
     __cil_tmp25 = (struct drm_i915_gem_request *)__mptr;
 #line 393
     gem_request = __cil_tmp25 + 1152921504606846952UL;
     }
 #line 393
     goto ldv_37819;
     ldv_37818: 
     {
 #line 396
     __cil_tmp26 = gem_request->seqno;
 #line 396
     __cil_tmp27 = gem_request->emitted_jiffies;
 #line 396
     __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 396
     __cil_tmp29 = (unsigned int )jiffies;
 #line 396
     __cil_tmp30 = __cil_tmp29 - __cil_tmp28;
 #line 396
     __cil_tmp31 = (int )__cil_tmp30;
 #line 396
     seq_printf(m, "    %d @ %d\n", __cil_tmp26, __cil_tmp31);
 #line 393
     __cil_tmp32 = gem_request->list.next;
 #line 393
     __mptr___0 = (struct list_head  const  *)__cil_tmp32;
 #line 393
     __cil_tmp33 = (struct drm_i915_gem_request *)__mptr___0;
 #line 393
     gem_request = __cil_tmp33 + 1152921504606846952UL;
     }
     ldv_37819: ;
     {
 #line 393
     __cil_tmp34 = & dev_priv->ring[0].request_list;
 #line 393
     __cil_tmp35 = (unsigned long )__cil_tmp34;
 #line 393
     __cil_tmp36 = & gem_request->list;
 #line 393
     __cil_tmp37 = (unsigned long )__cil_tmp36;
 #line 393
     if (__cil_tmp37 != __cil_tmp35) {
 #line 394
       goto ldv_37818;
     } else {
 #line 396
       goto ldv_37820;
     }
     }
     ldv_37820: 
 #line 400
     count = count + 1;
   } else {
 
   }
   {
 #line 402
   __cil_tmp38 = & dev_priv->ring[1].request_list;
 #line 402
   __cil_tmp39 = (struct list_head  const  *)__cil_tmp38;
 #line 402
   tmp___0 = list_empty(__cil_tmp39);
   }
 #line 402
   if (tmp___0 == 0) {
     {
 #line 403
     seq_printf(m, "BSD requests:\n");
 #line 404
     __cil_tmp40 = dev_priv->ring[1].request_list.next;
 #line 404
     __mptr___1 = (struct list_head  const  *)__cil_tmp40;
 #line 404
     __cil_tmp41 = (struct drm_i915_gem_request *)__mptr___1;
 #line 404
     gem_request = __cil_tmp41 + 1152921504606846952UL;
     }
 #line 404
     goto ldv_37826;
     ldv_37825: 
     {
 #line 407
     __cil_tmp42 = gem_request->seqno;
 #line 407
     __cil_tmp43 = gem_request->emitted_jiffies;
 #line 407
     __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 407
     __cil_tmp45 = (unsigned int )jiffies;
 #line 407
     __cil_tmp46 = __cil_tmp45 - __cil_tmp44;
 #line 407
     __cil_tmp47 = (int )__cil_tmp46;
 #line 407
     seq_printf(m, "    %d @ %d\n", __cil_tmp42, __cil_tmp47);
 #line 404
     __cil_tmp48 = gem_request->list.next;
 #line 404
     __mptr___2 = (struct list_head  const  *)__cil_tmp48;
 #line 404
     __cil_tmp49 = (struct drm_i915_gem_request *)__mptr___2;
 #line 404
     gem_request = __cil_tmp49 + 1152921504606846952UL;
     }
     ldv_37826: ;
     {
 #line 404
     __cil_tmp50 = & dev_priv->ring[1].request_list;
 #line 404
     __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 404
     __cil_tmp52 = & gem_request->list;
 #line 404
     __cil_tmp53 = (unsigned long )__cil_tmp52;
 #line 404
     if (__cil_tmp53 != __cil_tmp51) {
 #line 405
       goto ldv_37825;
     } else {
 #line 407
       goto ldv_37827;
     }
     }
     ldv_37827: 
 #line 411
     count = count + 1;
   } else {
 
   }
   {
 #line 413
   __cil_tmp54 = & dev_priv->ring[2].request_list;
 #line 413
   __cil_tmp55 = (struct list_head  const  *)__cil_tmp54;
 #line 413
   tmp___1 = list_empty(__cil_tmp55);
   }
 #line 413
   if (tmp___1 == 0) {
     {
 #line 414
     seq_printf(m, "BLT requests:\n");
 #line 415
     __cil_tmp56 = dev_priv->ring[2].request_list.next;
 #line 415
     __mptr___3 = (struct list_head  const  *)__cil_tmp56;
 #line 415
     __cil_tmp57 = (struct drm_i915_gem_request *)__mptr___3;
 #line 415
     gem_request = __cil_tmp57 + 1152921504606846952UL;
     }
 #line 415
     goto ldv_37833;
     ldv_37832: 
     {
 #line 418
     __cil_tmp58 = gem_request->seqno;
 #line 418
     __cil_tmp59 = gem_request->emitted_jiffies;
 #line 418
     __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 418
     __cil_tmp61 = (unsigned int )jiffies;
 #line 418
     __cil_tmp62 = __cil_tmp61 - __cil_tmp60;
 #line 418
     __cil_tmp63 = (int )__cil_tmp62;
 #line 418
     seq_printf(m, "    %d @ %d\n", __cil_tmp58, __cil_tmp63);
 #line 415
     __cil_tmp64 = gem_request->list.next;
 #line 415
     __mptr___4 = (struct list_head  const  *)__cil_tmp64;
 #line 415
     __cil_tmp65 = (struct drm_i915_gem_request *)__mptr___4;
 #line 415
     gem_request = __cil_tmp65 + 1152921504606846952UL;
     }
     ldv_37833: ;
     {
 #line 415
     __cil_tmp66 = & dev_priv->ring[2].request_list;
 #line 415
     __cil_tmp67 = (unsigned long )__cil_tmp66;
 #line 415
     __cil_tmp68 = & gem_request->list;
 #line 415
     __cil_tmp69 = (unsigned long )__cil_tmp68;
 #line 415
     if (__cil_tmp69 != __cil_tmp67) {
 #line 416
       goto ldv_37832;
     } else {
 #line 418
       goto ldv_37834;
     }
     }
     ldv_37834: 
 #line 422
     count = count + 1;
   } else {
 
   }
   {
 #line 424
   __cil_tmp70 = & dev->struct_mutex;
 #line 424
   mutex_unlock(__cil_tmp70);
   }
 #line 426
   if (count == 0) {
     {
 #line 427
     seq_printf(m, "No requests\n");
     }
   } else {
 
   }
 #line 429
   return (0);
 }
 }
 #line 432 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static void i915_ring_seqno_info(struct seq_file *m , struct intel_ring_buffer *ring ) 
 { u32 tmp ;
   u32 (*__cil_tmp4)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp5 ;
   u32 (*__cil_tmp6)(struct intel_ring_buffer * ) ;
   unsigned long __cil_tmp7 ;
   u32 (*__cil_tmp8)(struct intel_ring_buffer * ) ;
   char const   *__cil_tmp9 ;
   char const   *__cil_tmp10 ;
   u32 __cil_tmp11 ;
   char const   *__cil_tmp12 ;
   u32 __cil_tmp13 ;
 
   {
   {
 #line 435
   __cil_tmp4 = (u32 (*)(struct intel_ring_buffer * ))0;
 #line 435
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 435
   __cil_tmp6 = ring->get_seqno;
 #line 435
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 435
   if (__cil_tmp7 != __cil_tmp5) {
     {
 #line 436
     __cil_tmp8 = ring->get_seqno;
 #line 436
     tmp = (*__cil_tmp8)(ring);
 #line 436
     __cil_tmp9 = ring->name;
 #line 436
     seq_printf(m, "Current sequence (%s): %d\n", __cil_tmp9, tmp);
 #line 438
     __cil_tmp10 = ring->name;
 #line 438
     __cil_tmp11 = ring->waiting_seqno;
 #line 438
     seq_printf(m, "Waiter sequence (%s):  %d\n", __cil_tmp10, __cil_tmp11);
 #line 440
     __cil_tmp12 = ring->name;
 #line 440
     __cil_tmp13 = ring->irq_seqno;
 #line 440
     seq_printf(m, "IRQ sequence (%s):     %d\n", __cil_tmp12, __cil_tmp13);
     }
   } else {
 
   }
   }
 #line 443
   return;
 }
 }
 #line 445 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_seqno_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   int i ;
   void *__cil_tmp8 ;
   struct drm_minor *__cil_tmp9 ;
   void *__cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct intel_ring_buffer (*__cil_tmp13)[3U] ;
   struct intel_ring_buffer *__cil_tmp14 ;
   struct intel_ring_buffer *__cil_tmp15 ;
   struct mutex *__cil_tmp16 ;
 
   {
   {
 #line 447
   __cil_tmp8 = m->private;
 #line 447
   node = (struct drm_info_node *)__cil_tmp8;
 #line 448
   __cil_tmp9 = node->minor;
 #line 448
   dev = __cil_tmp9->dev;
 #line 449
   __cil_tmp10 = dev->dev_private;
 #line 449
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 452
   __cil_tmp11 = & dev->struct_mutex;
 #line 452
   ret = mutex_lock_interruptible_nested(__cil_tmp11, 0U);
   }
 #line 453
   if (ret != 0) {
 #line 454
     return (ret);
   } else {
 
   }
 #line 456
   i = 0;
 #line 456
   goto ldv_37849;
   ldv_37848: 
   {
 #line 457
   __cil_tmp12 = (unsigned long )i;
 #line 457
   __cil_tmp13 = & dev_priv->ring;
 #line 457
   __cil_tmp14 = (struct intel_ring_buffer *)__cil_tmp13;
 #line 457
   __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 457
   i915_ring_seqno_info(m, __cil_tmp15);
 #line 456
   i = i + 1;
   }
   ldv_37849: ;
 #line 456
   if (i <= 2) {
 #line 457
     goto ldv_37848;
   } else {
 #line 459
     goto ldv_37850;
   }
   ldv_37850: 
   {
 #line 459
   __cil_tmp16 = & dev->struct_mutex;
 #line 459
   mutex_unlock(__cil_tmp16);
   }
 #line 461
   return (0);
 }
 }
 #line 465 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_interrupt_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   int i ;
   int pipe ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   u32 tmp___3 ;
   u32 tmp___4 ;
   u32 tmp___5 ;
   u32 tmp___6 ;
   u32 tmp___7 ;
   u32 tmp___8 ;
   u32 tmp___9 ;
   u32 tmp___10 ;
   u32 tmp___11 ;
   int tmp___12 ;
   u32 tmp___13 ;
   void *__cil_tmp24 ;
   struct drm_minor *__cil_tmp25 ;
   void *__cil_tmp26 ;
   struct mutex *__cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   u8 __cil_tmp37 ;
   unsigned char __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   void *__cil_tmp40 ;
   struct drm_i915_private *__cil_tmp41 ;
   struct intel_device_info  const  *__cil_tmp42 ;
   unsigned char *__cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   u32 __cil_tmp49 ;
   int __cil_tmp50 ;
   int __cil_tmp51 ;
   atomic_t *__cil_tmp52 ;
   atomic_t const   *__cil_tmp53 ;
   void *__cil_tmp54 ;
   struct drm_i915_private *__cil_tmp55 ;
   struct intel_device_info  const  *__cil_tmp56 ;
   u8 __cil_tmp57 ;
   unsigned char __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned long __cil_tmp60 ;
   struct intel_ring_buffer (*__cil_tmp61)[3U] ;
   struct intel_ring_buffer *__cil_tmp62 ;
   struct intel_ring_buffer *__cil_tmp63 ;
   u32 __cil_tmp64 ;
   u32 __cil_tmp65 ;
   char const   *__cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   struct intel_ring_buffer (*__cil_tmp68)[3U] ;
   struct intel_ring_buffer *__cil_tmp69 ;
   struct intel_ring_buffer *__cil_tmp70 ;
   struct mutex *__cil_tmp71 ;
 
   {
   {
 #line 467
   __cil_tmp24 = m->private;
 #line 467
   node = (struct drm_info_node *)__cil_tmp24;
 #line 468
   __cil_tmp25 = node->minor;
 #line 468
   dev = __cil_tmp25->dev;
 #line 469
   __cil_tmp26 = dev->dev_private;
 #line 469
   dev_priv = (drm_i915_private_t *)__cil_tmp26;
 #line 472
   __cil_tmp27 = & dev->struct_mutex;
 #line 472
   ret = mutex_lock_interruptible_nested(__cil_tmp27, 0U);
   }
 #line 473
   if (ret != 0) {
 #line 474
     return (ret);
   } else {
 
   }
   {
 #line 476
   __cil_tmp28 = dev->dev_private;
 #line 476
   __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 476
   __cil_tmp30 = __cil_tmp29->info;
 #line 476
   __cil_tmp31 = __cil_tmp30->gen;
 #line 476
   __cil_tmp32 = (unsigned char )__cil_tmp31;
 #line 476
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 476
   if (__cil_tmp33 != 5U) {
     {
 #line 476
     __cil_tmp34 = dev->dev_private;
 #line 476
     __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 476
     __cil_tmp36 = __cil_tmp35->info;
 #line 476
     __cil_tmp37 = __cil_tmp36->gen;
 #line 476
     __cil_tmp38 = (unsigned char )__cil_tmp37;
 #line 476
     __cil_tmp39 = (unsigned int )__cil_tmp38;
 #line 476
     if (__cil_tmp39 != 6U) {
       {
 #line 476
       __cil_tmp40 = dev->dev_private;
 #line 476
       __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
 #line 476
       __cil_tmp42 = __cil_tmp41->info;
 #line 476
       __cil_tmp43 = (unsigned char *)__cil_tmp42;
 #line 476
       __cil_tmp44 = __cil_tmp43 + 2UL;
 #line 476
       __cil_tmp45 = *__cil_tmp44;
 #line 476
       __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 476
       if (__cil_tmp46 == 0U) {
         {
 #line 477
         tmp = i915_read32___2(dev_priv, 8352U);
 #line 477
         seq_printf(m, "Interrupt enable:    %08x\n", tmp);
 #line 479
         tmp___0 = i915_read32___2(dev_priv, 8356U);
 #line 479
         seq_printf(m, "Interrupt identity:  %08x\n", tmp___0);
 #line 481
         tmp___1 = i915_read32___2(dev_priv, 8360U);
 #line 481
         seq_printf(m, "Interrupt mask:      %08x\n", tmp___1);
 #line 483
         pipe = 0;
         }
 #line 483
         goto ldv_37862;
         ldv_37861: 
         {
 #line 484
         __cil_tmp47 = pipe * 4096;
 #line 484
         __cil_tmp48 = __cil_tmp47 + 458788;
 #line 484
         __cil_tmp49 = (u32 )__cil_tmp48;
 #line 484
         tmp___2 = i915_read32___2(dev_priv, __cil_tmp49);
 #line 484
         __cil_tmp50 = pipe + 65;
 #line 484
         seq_printf(m, "Pipe %c stat:         %08x\n", __cil_tmp50, tmp___2);
 #line 483
         pipe = pipe + 1;
         }
         ldv_37862: ;
         {
 #line 483
         __cil_tmp51 = dev_priv->num_pipe;
 #line 483
         if (__cil_tmp51 > pipe) {
 #line 484
           goto ldv_37861;
         } else {
 #line 486
           goto ldv_37863;
         }
         }
         ldv_37863: ;
       } else {
 #line 476
         goto _L___0;
       }
       }
     } else {
 #line 476
       goto _L___0;
     }
     }
   } else {
     _L___0: 
     {
 #line 488
     tmp___3 = i915_read32___2(dev_priv, 278540U);
 #line 488
     seq_printf(m, "North Display Interrupt enable:\t\t%08x\n", tmp___3);
 #line 490
     tmp___4 = i915_read32___2(dev_priv, 278536U);
 #line 490
     seq_printf(m, "North Display Interrupt identity:\t%08x\n", tmp___4);
 #line 492
     tmp___5 = i915_read32___2(dev_priv, 278532U);
 #line 492
     seq_printf(m, "North Display Interrupt mask:\t\t%08x\n", tmp___5);
 #line 494
     tmp___6 = i915_read32___2(dev_priv, 802828U);
 #line 494
     seq_printf(m, "South Display Interrupt enable:\t\t%08x\n", tmp___6);
 #line 496
     tmp___7 = i915_read32___2(dev_priv, 802824U);
 #line 496
     seq_printf(m, "South Display Interrupt identity:\t%08x\n", tmp___7);
 #line 498
     tmp___8 = i915_read32___2(dev_priv, 802820U);
 #line 498
     seq_printf(m, "South Display Interrupt mask:\t\t%08x\n", tmp___8);
 #line 500
     tmp___9 = i915_read32___2(dev_priv, 278556U);
 #line 500
     seq_printf(m, "Graphics Interrupt enable:\t\t%08x\n", tmp___9);
 #line 502
     tmp___10 = i915_read32___2(dev_priv, 278552U);
 #line 502
     seq_printf(m, "Graphics Interrupt identity:\t\t%08x\n", tmp___10);
 #line 504
     tmp___11 = i915_read32___2(dev_priv, 278548U);
 #line 504
     seq_printf(m, "Graphics Interrupt mask:\t\t%08x\n", tmp___11);
     }
   }
   }
   {
 #line 507
   __cil_tmp52 = & dev_priv->irq_received;
 #line 507
   __cil_tmp53 = (atomic_t const   *)__cil_tmp52;
 #line 507
   tmp___12 = atomic_read(__cil_tmp53);
 #line 507
   seq_printf(m, "Interrupts received: %d\n", tmp___12);
 #line 509
   i = 0;
   }
 #line 509
   goto ldv_37865;
   ldv_37864: ;
   {
 #line 510
   __cil_tmp54 = dev->dev_private;
 #line 510
   __cil_tmp55 = (struct drm_i915_private *)__cil_tmp54;
 #line 510
   __cil_tmp56 = __cil_tmp55->info;
 #line 510
   __cil_tmp57 = __cil_tmp56->gen;
 #line 510
   __cil_tmp58 = (unsigned char )__cil_tmp57;
 #line 510
   __cil_tmp59 = (unsigned int )__cil_tmp58;
 #line 510
   if (__cil_tmp59 == 6U) {
     {
 #line 511
     __cil_tmp60 = (unsigned long )i;
 #line 511
     __cil_tmp61 = & dev_priv->ring;
 #line 511
     __cil_tmp62 = (struct intel_ring_buffer *)__cil_tmp61;
 #line 511
     __cil_tmp63 = __cil_tmp62 + __cil_tmp60;
 #line 511
     __cil_tmp64 = __cil_tmp63->mmio_base;
 #line 511
     __cil_tmp65 = __cil_tmp64 + 168U;
 #line 511
     tmp___13 = i915_read32___2(dev_priv, __cil_tmp65);
 #line 511
     __cil_tmp66 = dev_priv->ring[i].name;
 #line 511
     seq_printf(m, "Graphics Interrupt mask (%s):\t%08x\n", __cil_tmp66, tmp___13);
     }
   } else {
 
   }
   }
   {
 #line 515
   __cil_tmp67 = (unsigned long )i;
 #line 515
   __cil_tmp68 = & dev_priv->ring;
 #line 515
   __cil_tmp69 = (struct intel_ring_buffer *)__cil_tmp68;
 #line 515
   __cil_tmp70 = __cil_tmp69 + __cil_tmp67;
 #line 515
   i915_ring_seqno_info(m, __cil_tmp70);
 #line 509
   i = i + 1;
   }
   ldv_37865: ;
 #line 509
   if (i <= 2) {
 #line 510
     goto ldv_37864;
   } else {
 #line 512
     goto ldv_37866;
   }
   ldv_37866: 
   {
 #line 517
   __cil_tmp71 = & dev->struct_mutex;
 #line 517
   mutex_unlock(__cil_tmp71);
   }
 #line 519
   return (0);
 }
 }
 #line 522 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_fence_regs_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int i ;
   int ret ;
   struct drm_i915_gem_object *obj ;
   void *__cil_tmp9 ;
   struct drm_minor *__cil_tmp10 ;
   void *__cil_tmp11 ;
   struct mutex *__cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   struct drm_i915_gem_object *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   int __cil_tmp18 ;
   struct mutex *__cil_tmp19 ;
 
   {
   {
 #line 524
   __cil_tmp9 = m->private;
 #line 524
   node = (struct drm_info_node *)__cil_tmp9;
 #line 525
   __cil_tmp10 = node->minor;
 #line 525
   dev = __cil_tmp10->dev;
 #line 526
   __cil_tmp11 = dev->dev_private;
 #line 526
   dev_priv = (drm_i915_private_t *)__cil_tmp11;
 #line 529
   __cil_tmp12 = & dev->struct_mutex;
 #line 529
   ret = mutex_lock_interruptible_nested(__cil_tmp12, 0U);
   }
 #line 530
   if (ret != 0) {
 #line 531
     return (ret);
   } else {
 
   }
   {
 #line 533
   __cil_tmp13 = dev_priv->fence_reg_start;
 #line 533
   seq_printf(m, "Reserved fences = %d\n", __cil_tmp13);
 #line 534
   __cil_tmp14 = dev_priv->num_fence_regs;
 #line 534
   seq_printf(m, "Total fences = %d\n", __cil_tmp14);
 #line 535
   i = 0;
   }
 #line 535
   goto ldv_37878;
   ldv_37877: 
   {
 #line 536
   obj = dev_priv->fence_regs[i].obj;
 #line 538
   seq_printf(m, "Fenced object[%2d] = ", i);
   }
   {
 #line 539
   __cil_tmp15 = (struct drm_i915_gem_object *)0;
 #line 539
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 539
   __cil_tmp17 = (unsigned long )obj;
 #line 539
   if (__cil_tmp17 == __cil_tmp16) {
     {
 #line 540
     seq_printf(m, "unused");
     }
   } else {
     {
 #line 542
     describe_obj(m, obj);
     }
   }
   }
   {
 #line 543
   seq_printf(m, "\n");
 #line 535
   i = i + 1;
   }
   ldv_37878: ;
   {
 #line 535
   __cil_tmp18 = dev_priv->num_fence_regs;
 #line 535
   if (__cil_tmp18 > i) {
 #line 536
     goto ldv_37877;
   } else {
 #line 538
     goto ldv_37879;
   }
   }
   ldv_37879: 
   {
 #line 546
   __cil_tmp19 = & dev->struct_mutex;
 #line 546
   mutex_unlock(__cil_tmp19);
   }
 #line 547
   return (0);
 }
 }
 #line 550 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_hws_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct intel_ring_buffer *ring ;
   u32 const volatile   *hws ;
   int i ;
   void *__cil_tmp9 ;
   struct drm_minor *__cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_info_list *__cil_tmp12 ;
   void *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct intel_ring_buffer (*__cil_tmp15)[3U] ;
   struct intel_ring_buffer *__cil_tmp16 ;
   u32 *__cil_tmp17 ;
   u32 const volatile   *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   int __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   u32 const volatile   *__cil_tmp23 ;
   u32 volatile   __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   u32 const volatile   *__cil_tmp27 ;
   u32 volatile   __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   u32 const volatile   *__cil_tmp31 ;
   u32 volatile   __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   u32 const volatile   *__cil_tmp35 ;
   u32 volatile   __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
 
   {
 #line 552
   __cil_tmp9 = m->private;
 #line 552
   node = (struct drm_info_node *)__cil_tmp9;
 #line 553
   __cil_tmp10 = node->minor;
 #line 553
   dev = __cil_tmp10->dev;
 #line 554
   __cil_tmp11 = dev->dev_private;
 #line 554
   dev_priv = (drm_i915_private_t *)__cil_tmp11;
 #line 559
   __cil_tmp12 = node->info_ent;
 #line 559
   __cil_tmp13 = __cil_tmp12->data;
 #line 559
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 559
   __cil_tmp15 = & dev_priv->ring;
 #line 559
   __cil_tmp16 = (struct intel_ring_buffer *)__cil_tmp15;
 #line 559
   ring = __cil_tmp16 + __cil_tmp14;
 #line 560
   __cil_tmp17 = ring->status_page.page_addr;
 #line 560
   hws = (u32 const volatile   *)__cil_tmp17;
   {
 #line 561
   __cil_tmp18 = (u32 const volatile   *)0;
 #line 561
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 561
   __cil_tmp20 = (unsigned long )hws;
 #line 561
   if (__cil_tmp20 == __cil_tmp19) {
 #line 562
     return (0);
   } else {
 
   }
   }
 #line 564
   i = 0;
 #line 564
   goto ldv_37891;
   ldv_37890: 
   {
 #line 565
   __cil_tmp21 = i * 4;
 #line 565
   __cil_tmp22 = (unsigned long )i;
 #line 565
   __cil_tmp23 = hws + __cil_tmp22;
 #line 565
   __cil_tmp24 = *__cil_tmp23;
 #line 565
   __cil_tmp25 = (unsigned long )i;
 #line 565
   __cil_tmp26 = __cil_tmp25 + 1UL;
 #line 565
   __cil_tmp27 = hws + __cil_tmp26;
 #line 565
   __cil_tmp28 = *__cil_tmp27;
 #line 565
   __cil_tmp29 = (unsigned long )i;
 #line 565
   __cil_tmp30 = __cil_tmp29 + 2UL;
 #line 565
   __cil_tmp31 = hws + __cil_tmp30;
 #line 565
   __cil_tmp32 = *__cil_tmp31;
 #line 565
   __cil_tmp33 = (unsigned long )i;
 #line 565
   __cil_tmp34 = __cil_tmp33 + 3UL;
 #line 565
   __cil_tmp35 = hws + __cil_tmp34;
 #line 565
   __cil_tmp36 = *__cil_tmp35;
 #line 565
   seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", __cil_tmp21, __cil_tmp24,
              __cil_tmp28, __cil_tmp32, __cil_tmp36);
 #line 564
   i = i + 4;
   }
   ldv_37891: ;
   {
 #line 564
   __cil_tmp37 = (unsigned int )i;
 #line 564
   if (__cil_tmp37 <= 255U) {
 #line 565
     goto ldv_37890;
   } else {
 #line 567
     goto ldv_37892;
   }
   }
   ldv_37892: ;
 #line 569
   return (0);
 }
 }
 #line 572 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static void i915_dump_object(struct seq_file *m , struct io_mapping *mapping , struct drm_i915_gem_object *obj ) 
 { int page ;
   int page_count___0 ;
   int i ;
   u32 *mem ;
   void *tmp ;
   size_t __cil_tmp9 ;
   size_t __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   uint32_t __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   int __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   u32 *__cil_tmp18 ;
   u32 __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   void *__cil_tmp21 ;
 
   {
 #line 578
   __cil_tmp9 = obj->base.size;
 #line 578
   __cil_tmp10 = __cil_tmp9 / 4096UL;
 #line 578
   page_count___0 = (int )__cil_tmp10;
 #line 579
   page = 0;
 #line 579
   goto ldv_37906;
   ldv_37905: 
   {
 #line 580
   __cil_tmp11 = (unsigned long )page;
 #line 580
   __cil_tmp12 = __cil_tmp11 * 4096UL;
 #line 580
   __cil_tmp13 = obj->gtt_offset;
 #line 580
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 580
   __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 580
   tmp = io_mapping_map_atomic_wc(mapping, __cil_tmp15);
 #line 580
   mem = (u32 *)tmp;
 #line 582
   i = 0;
   }
 #line 582
   goto ldv_37903;
   ldv_37902: 
   {
 #line 583
   __cil_tmp16 = i / 4;
 #line 583
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 583
   __cil_tmp18 = mem + __cil_tmp17;
 #line 583
   __cil_tmp19 = *__cil_tmp18;
 #line 583
   seq_printf(m, "%08x :  %08x\n", i, __cil_tmp19);
 #line 582
   i = i + 4;
   }
   ldv_37903: ;
   {
 #line 582
   __cil_tmp20 = (unsigned int )i;
 #line 582
   if (__cil_tmp20 <= 4095U) {
 #line 583
     goto ldv_37902;
   } else {
 #line 585
     goto ldv_37904;
   }
   }
   ldv_37904: 
   {
 #line 584
   __cil_tmp21 = (void *)mem;
 #line 584
   io_mapping_unmap_atomic(__cil_tmp21);
 #line 579
   page = page + 1;
   }
   ldv_37906: ;
 #line 579
   if (page < page_count___0) {
 #line 580
     goto ldv_37905;
   } else {
 #line 582
     goto ldv_37907;
   }
   ldv_37907: ;
 #line 584
   return;
 }
 }
 #line 588 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_batchbuffer_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp10 ;
   struct drm_minor *__cil_tmp11 ;
   void *__cil_tmp12 ;
   struct mutex *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct drm_i915_gem_object *__cil_tmp15 ;
   uint32_t __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   uint32_t __cil_tmp18 ;
   struct io_mapping *__cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   struct drm_i915_gem_object *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct mutex *__cil_tmp26 ;
 
   {
   {
 #line 590
   __cil_tmp10 = m->private;
 #line 590
   node = (struct drm_info_node *)__cil_tmp10;
 #line 591
   __cil_tmp11 = node->minor;
 #line 591
   dev = __cil_tmp11->dev;
 #line 592
   __cil_tmp12 = dev->dev_private;
 #line 592
   dev_priv = (drm_i915_private_t *)__cil_tmp12;
 #line 596
   __cil_tmp13 = & dev->struct_mutex;
 #line 596
   ret = mutex_lock_interruptible_nested(__cil_tmp13, 0U);
   }
 #line 597
   if (ret != 0) {
 #line 598
     return (ret);
   } else {
 
   }
 #line 600
   __cil_tmp14 = dev_priv->mm.active_list.next;
 #line 600
   __mptr = (struct list_head  const  *)__cil_tmp14;
 #line 600
   __cil_tmp15 = (struct drm_i915_gem_object *)__mptr;
 #line 600
   obj = __cil_tmp15 + 1152921504606846800UL;
 #line 600
   goto ldv_37922;
   ldv_37921: ;
   {
 #line 601
   __cil_tmp16 = obj->base.read_domains;
 #line 601
   __cil_tmp17 = __cil_tmp16 & 8U;
 #line 601
   if (__cil_tmp17 != 0U) {
     {
 #line 602
     __cil_tmp18 = obj->gtt_offset;
 #line 602
     seq_printf(m, "--- gtt_offset = 0x%08x\n", __cil_tmp18);
 #line 603
     __cil_tmp19 = dev_priv->mm.gtt_mapping;
 #line 603
     i915_dump_object(m, __cil_tmp19, obj);
     }
   } else {
 
   }
   }
 #line 600
   __cil_tmp20 = obj->mm_list.next;
 #line 600
   __mptr___0 = (struct list_head  const  *)__cil_tmp20;
 #line 600
   __cil_tmp21 = (struct drm_i915_gem_object *)__mptr___0;
 #line 600
   obj = __cil_tmp21 + 1152921504606846800UL;
   ldv_37922: ;
   {
 #line 600
   __cil_tmp22 = & dev_priv->mm.active_list;
 #line 600
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 600
   __cil_tmp24 = & obj->mm_list;
 #line 600
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 600
   if (__cil_tmp25 != __cil_tmp23) {
 #line 601
     goto ldv_37921;
   } else {
 #line 603
     goto ldv_37923;
   }
   }
   ldv_37923: 
   {
 #line 607
   __cil_tmp26 = & dev->struct_mutex;
 #line 607
   mutex_unlock(__cil_tmp26);
   }
 #line 608
   return (0);
 }
 }
 #line 611 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_ringbuffer_data(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct intel_ring_buffer *ring ;
   int ret ;
   u8 const   *virt ;
   uint32_t off ;
   uint32_t *ptr ;
   void *__cil_tmp11 ;
   struct drm_minor *__cil_tmp12 ;
   void *__cil_tmp13 ;
   struct mutex *__cil_tmp14 ;
   struct drm_info_list *__cil_tmp15 ;
   void *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct intel_ring_buffer (*__cil_tmp18)[3U] ;
   struct intel_ring_buffer *__cil_tmp19 ;
   struct drm_i915_gem_object *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct drm_i915_gem_object *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   void *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   uint32_t *__cil_tmp26 ;
   uint32_t __cil_tmp27 ;
   int __cil_tmp28 ;
   uint32_t __cil_tmp29 ;
   struct mutex *__cil_tmp30 ;
 
   {
   {
 #line 613
   __cil_tmp11 = m->private;
 #line 613
   node = (struct drm_info_node *)__cil_tmp11;
 #line 614
   __cil_tmp12 = node->minor;
 #line 614
   dev = __cil_tmp12->dev;
 #line 615
   __cil_tmp13 = dev->dev_private;
 #line 615
   dev_priv = (drm_i915_private_t *)__cil_tmp13;
 #line 619
   __cil_tmp14 = & dev->struct_mutex;
 #line 619
   ret = mutex_lock_interruptible_nested(__cil_tmp14, 0U);
   }
 #line 620
   if (ret != 0) {
 #line 621
     return (ret);
   } else {
 
   }
 #line 623
   __cil_tmp15 = node->info_ent;
 #line 623
   __cil_tmp16 = __cil_tmp15->data;
 #line 623
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 623
   __cil_tmp18 = & dev_priv->ring;
 #line 623
   __cil_tmp19 = (struct intel_ring_buffer *)__cil_tmp18;
 #line 623
   ring = __cil_tmp19 + __cil_tmp17;
   {
 #line 624
   __cil_tmp20 = (struct drm_i915_gem_object *)0;
 #line 624
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 624
   __cil_tmp22 = ring->obj;
 #line 624
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 624
   if (__cil_tmp23 == __cil_tmp21) {
     {
 #line 625
     seq_printf(m, "No ringbuffer setup\n");
     }
   } else {
 #line 627
     __cil_tmp24 = ring->virtual_start;
 #line 627
     virt = (u8 const   *)__cil_tmp24;
 #line 630
     off = 0U;
 #line 630
     goto ldv_37937;
     ldv_37936: 
     {
 #line 631
     __cil_tmp25 = (unsigned long )off;
 #line 631
     __cil_tmp26 = (uint32_t *)virt;
 #line 631
     ptr = __cil_tmp26 + __cil_tmp25;
 #line 632
     __cil_tmp27 = *ptr;
 #line 632
     seq_printf(m, "%08x :  %08x\n", off, __cil_tmp27);
 #line 630
     off = off + 4U;
     }
     ldv_37937: ;
     {
 #line 630
     __cil_tmp28 = ring->size;
 #line 630
     __cil_tmp29 = (uint32_t )__cil_tmp28;
 #line 630
     if (__cil_tmp29 > off) {
 #line 631
       goto ldv_37936;
     } else {
 #line 633
       goto ldv_37938;
     }
     }
     ldv_37938: ;
   }
   }
   {
 #line 635
   __cil_tmp30 = & dev->struct_mutex;
 #line 635
   mutex_unlock(__cil_tmp30);
   }
 #line 637
   return (0);
 }
 }
 #line 640 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_ringbuffer_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct intel_ring_buffer *ring ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   u32 tmp___3 ;
   u32 tmp___4 ;
   u32 tmp___5 ;
   u32 tmp___6 ;
   void *__cil_tmp15 ;
   struct drm_minor *__cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_info_list *__cil_tmp18 ;
   void *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   struct intel_ring_buffer (*__cil_tmp21)[3U] ;
   struct intel_ring_buffer *__cil_tmp22 ;
   int __cil_tmp23 ;
   char const   *__cil_tmp24 ;
   u32 __cil_tmp25 ;
   u32 __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   u32 __cil_tmp28 ;
   u32 __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   u32 __cil_tmp32 ;
   u32 __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   u8 __cil_tmp37 ;
   unsigned char __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   u32 __cil_tmp40 ;
   u32 __cil_tmp41 ;
   u32 __cil_tmp42 ;
   u32 __cil_tmp43 ;
   u32 __cil_tmp44 ;
   u32 __cil_tmp45 ;
   u32 __cil_tmp46 ;
   u32 __cil_tmp47 ;
 
   {
 #line 642
   __cil_tmp15 = m->private;
 #line 642
   node = (struct drm_info_node *)__cil_tmp15;
 #line 643
   __cil_tmp16 = node->minor;
 #line 643
   dev = __cil_tmp16->dev;
 #line 644
   __cil_tmp17 = dev->dev_private;
 #line 644
   dev_priv = (drm_i915_private_t *)__cil_tmp17;
 #line 647
   __cil_tmp18 = node->info_ent;
 #line 647
   __cil_tmp19 = __cil_tmp18->data;
 #line 647
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 647
   __cil_tmp21 = & dev_priv->ring;
 #line 647
   __cil_tmp22 = (struct intel_ring_buffer *)__cil_tmp21;
 #line 647
   ring = __cil_tmp22 + __cil_tmp20;
   {
 #line 648
   __cil_tmp23 = ring->size;
 #line 648
   if (__cil_tmp23 == 0) {
 #line 649
     return (0);
   } else {
 
   }
   }
   {
 #line 651
   __cil_tmp24 = ring->name;
 #line 651
   seq_printf(m, "Ring %s:\n", __cil_tmp24);
 #line 652
   __cil_tmp25 = ring->mmio_base;
 #line 652
   __cil_tmp26 = __cil_tmp25 + 52U;
 #line 652
   tmp = i915_read32___2(dev_priv, __cil_tmp26);
 #line 652
   __cil_tmp27 = tmp & 2097148U;
 #line 652
   seq_printf(m, "  Head :    %08x\n", __cil_tmp27);
 #line 653
   __cil_tmp28 = ring->mmio_base;
 #line 653
   __cil_tmp29 = __cil_tmp28 + 48U;
 #line 653
   tmp___0 = i915_read32___2(dev_priv, __cil_tmp29);
 #line 653
   __cil_tmp30 = tmp___0 & 2097144U;
 #line 653
   seq_printf(m, "  Tail :    %08x\n", __cil_tmp30);
 #line 654
   __cil_tmp31 = ring->size;
 #line 654
   seq_printf(m, "  Size :    %08x\n", __cil_tmp31);
 #line 655
   tmp___1 = intel_ring_get_active_head(ring);
 #line 655
   seq_printf(m, "  Active :  %08x\n", tmp___1);
 #line 656
   __cil_tmp32 = ring->mmio_base;
 #line 656
   __cil_tmp33 = __cil_tmp32 + 148U;
 #line 656
   tmp___2 = i915_read32___2(dev_priv, __cil_tmp33);
 #line 656
   seq_printf(m, "  NOPID :   %08x\n", tmp___2);
   }
   {
 #line 657
   __cil_tmp34 = dev->dev_private;
 #line 657
   __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 657
   __cil_tmp36 = __cil_tmp35->info;
 #line 657
   __cil_tmp37 = __cil_tmp36->gen;
 #line 657
   __cil_tmp38 = (unsigned char )__cil_tmp37;
 #line 657
   __cil_tmp39 = (unsigned int )__cil_tmp38;
 #line 657
   if (__cil_tmp39 == 6U) {
     {
 #line 658
     __cil_tmp40 = ring->mmio_base;
 #line 658
     __cil_tmp41 = __cil_tmp40 + 64U;
 #line 658
     tmp___3 = i915_read32___2(dev_priv, __cil_tmp41);
 #line 658
     seq_printf(m, "  Sync 0 :   %08x\n", tmp___3);
 #line 659
     __cil_tmp42 = ring->mmio_base;
 #line 659
     __cil_tmp43 = __cil_tmp42 + 68U;
 #line 659
     tmp___4 = i915_read32___2(dev_priv, __cil_tmp43);
 #line 659
     seq_printf(m, "  Sync 1 :   %08x\n", tmp___4);
     }
   } else {
 
   }
   }
   {
 #line 661
   __cil_tmp44 = ring->mmio_base;
 #line 661
   __cil_tmp45 = __cil_tmp44 + 60U;
 #line 661
   tmp___5 = i915_read32___2(dev_priv, __cil_tmp45);
 #line 661
   seq_printf(m, "  Control : %08x\n", tmp___5);
 #line 662
   __cil_tmp46 = ring->mmio_base;
 #line 662
   __cil_tmp47 = __cil_tmp46 + 56U;
 #line 662
   tmp___6 = i915_read32___2(dev_priv, __cil_tmp47);
 #line 662
   seq_printf(m, "  Start :   %08x\n", tmp___6);
   }
 #line 664
   return (0);
 }
 }
 #line 667 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *ring_str(int ring ) 
 { 
 
   {
 #line 670
   if (ring == 1) {
 #line 670
     goto case_1;
   } else
 #line 671
   if (ring == 2) {
 #line 671
     goto case_2;
   } else
 #line 672
   if (ring == 4) {
 #line 672
     goto case_4;
   } else {
 #line 673
     goto switch_default;
 #line 669
     if (0) {
       case_1: ;
 #line 670
       return (" render");
       case_2: ;
 #line 671
       return (" bsd");
       case_4: ;
 #line 672
       return (" blt");
       switch_default: ;
 #line 673
       return ("");
     } else {
 
     }
   }
 }
 }
 #line 677 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *pin_flag(int pinned ) 
 { 
 
   {
 #line 679
   if (pinned > 0) {
 #line 680
     return (" P");
   } else
 #line 681
   if (pinned < 0) {
 #line 682
     return (" p");
   } else {
 #line 684
     return ("");
   }
 }
 }
 #line 687 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *tiling_flag(int tiling ) 
 { 
 
   {
 #line 691
   if (tiling == 0) {
 #line 691
     goto case_0;
   } else
 #line 692
   if (tiling == 1) {
 #line 692
     goto case_1;
   } else
 #line 693
   if (tiling == 2) {
 #line 693
     goto case_2;
   } else {
 #line 690
     goto switch_default;
 #line 689
     if (0) {
       switch_default: ;
       case_0: ;
 #line 691
       return ("");
       case_1: ;
 #line 692
       return (" X");
       case_2: ;
 #line 693
       return (" Y");
     } else {
 
     }
   }
 }
 }
 #line 697 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *dirty_flag(int dirty ) 
 { char const   *tmp ;
 
   {
 #line 699
   if (dirty != 0) {
 #line 699
     tmp = " dirty";
   } else {
 #line 699
     tmp = "";
   }
 #line 699
   return (tmp);
 }
 }
 #line 702 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static char const   *purgeable_flag(int purgeable ) 
 { char const   *tmp ;
 
   {
 #line 704
   if (purgeable != 0) {
 #line 704
     tmp = " purgeable";
   } else {
 #line 704
     tmp = "";
   }
 #line 704
   return (tmp);
 }
 }
 #line 707 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static void print_error_buffers(struct seq_file *m , char const   *name , struct drm_i915_error_buffer *err ,
                                 int count ) 
 { char const   *tmp ;
   char const   *tmp___0 ;
   char const   *tmp___1 ;
   char const   *tmp___2 ;
   char const   *tmp___3 ;
   char const   *tmp___4 ;
   int tmp___5 ;
   unsigned char __cil_tmp12 ;
   int __cil_tmp13 ;
   unsigned char __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   int __cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   int __cil_tmp19 ;
   unsigned char __cil_tmp20 ;
   int __cil_tmp21 ;
   signed char __cil_tmp22 ;
   int __cil_tmp23 ;
   u32 __cil_tmp24 ;
   u32 __cil_tmp25 ;
   u32 __cil_tmp26 ;
   u32 __cil_tmp27 ;
   u32 __cil_tmp28 ;
   u32 __cil_tmp29 ;
   u32 __cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char *__cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   signed char __cil_tmp35 ;
   int __cil_tmp36 ;
 
   {
   {
 #line 712
   seq_printf(m, "%s [%d]:\n", name, count);
   }
 #line 714
   goto ldv_37977;
   ldv_37976: 
   {
 #line 715
   __cil_tmp12 = err->cache_level;
 #line 715
   __cil_tmp13 = (int )__cil_tmp12;
 #line 715
   tmp = cache_level_str(__cil_tmp13);
 #line 715
   __cil_tmp14 = err->ring;
 #line 715
   __cil_tmp15 = (int )__cil_tmp14;
 #line 715
   tmp___0 = ring_str(__cil_tmp15);
 #line 715
   __cil_tmp16 = err->purgeable;
 #line 715
   __cil_tmp17 = (int )__cil_tmp16;
 #line 715
   tmp___1 = purgeable_flag(__cil_tmp17);
 #line 715
   __cil_tmp18 = err->dirty;
 #line 715
   __cil_tmp19 = (int )__cil_tmp18;
 #line 715
   tmp___2 = dirty_flag(__cil_tmp19);
 #line 715
   __cil_tmp20 = err->tiling;
 #line 715
   __cil_tmp21 = (int )__cil_tmp20;
 #line 715
   tmp___3 = tiling_flag(__cil_tmp21);
 #line 715
   __cil_tmp22 = err->pinned;
 #line 715
   __cil_tmp23 = (int )__cil_tmp22;
 #line 715
   tmp___4 = pin_flag(__cil_tmp23);
 #line 715
   __cil_tmp24 = err->gtt_offset;
 #line 715
   __cil_tmp25 = err->size;
 #line 715
   __cil_tmp26 = err->read_domains;
 #line 715
   __cil_tmp27 = err->write_domain;
 #line 715
   __cil_tmp28 = err->seqno;
 #line 715
   seq_printf(m, "  %08x %8u %04x %04x %08x%s%s%s%s%s%s", __cil_tmp24, __cil_tmp25,
              __cil_tmp26, __cil_tmp27, __cil_tmp28, tmp___4, tmp___3, tmp___2, tmp___1,
              tmp___0, tmp);
   }
   {
 #line 728
   __cil_tmp29 = err->name;
 #line 728
   if (__cil_tmp29 != 0U) {
     {
 #line 729
     __cil_tmp30 = err->name;
 #line 729
     seq_printf(m, " (name: %d)", __cil_tmp30);
     }
   } else {
 
   }
   }
   {
 #line 730
   __cil_tmp31 = (unsigned char *)err;
 #line 730
   __cil_tmp32 = __cil_tmp31 + 24UL;
 #line 730
   __cil_tmp33 = *__cil_tmp32;
 #line 730
   __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 730
   if (__cil_tmp34 != 31U) {
     {
 #line 731
     __cil_tmp35 = err->fence_reg;
 #line 731
     __cil_tmp36 = (int )__cil_tmp35;
 #line 731
     seq_printf(m, " (fence: %d)", __cil_tmp36);
     }
   } else {
 
   }
   }
   {
 #line 733
   seq_printf(m, "\n");
 #line 734
   err = err + 1;
   }
   ldv_37977: 
 #line 714
   tmp___5 = count;
 #line 714
   count = count - 1;
 #line 714
   if (tmp___5 != 0) {
 #line 715
     goto ldv_37976;
   } else {
 #line 717
     goto ldv_37978;
   }
   ldv_37978: ;
 #line 719
   return;
 }
 }
 #line 738 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_error_state(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_error_state *error ;
   unsigned long flags ;
   int i ;
   int page ;
   int offset ;
   int elt ;
   raw_spinlock_t *tmp ;
   struct drm_i915_error_object *obj ;
   struct drm_i915_error_object *obj___0 ;
   void *__cil_tmp15 ;
   struct drm_minor *__cil_tmp16 ;
   void *__cil_tmp17 ;
   spinlock_t *__cil_tmp18 ;
   struct drm_i915_error_state *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   struct drm_i915_error_state *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   __kernel_time_t __cil_tmp23 ;
   __kernel_suseconds_t __cil_tmp24 ;
   int __cil_tmp25 ;
   u32 __cil_tmp26 ;
   u32 __cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   u32 __cil_tmp35 ;
   u32 __cil_tmp36 ;
   u32 __cil_tmp37 ;
   u32 __cil_tmp38 ;
   u32 __cil_tmp39 ;
   u32 __cil_tmp40 ;
   u32 __cil_tmp41 ;
   u32 __cil_tmp42 ;
   u32 __cil_tmp43 ;
   u32 __cil_tmp44 ;
   u32 __cil_tmp45 ;
   u32 __cil_tmp46 ;
   u32 __cil_tmp47 ;
   u32 __cil_tmp48 ;
   void *__cil_tmp49 ;
   struct drm_i915_private *__cil_tmp50 ;
   struct intel_device_info  const  *__cil_tmp51 ;
   u8 __cil_tmp52 ;
   unsigned char __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   u32 __cil_tmp55 ;
   u32 __cil_tmp56 ;
   u32 __cil_tmp57 ;
   u32 __cil_tmp58 ;
   u64 __cil_tmp59 ;
   int __cil_tmp60 ;
   struct drm_i915_error_buffer *__cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   struct drm_i915_error_buffer *__cil_tmp63 ;
   unsigned long __cil_tmp64 ;
   struct drm_i915_error_buffer *__cil_tmp65 ;
   u32 __cil_tmp66 ;
   int __cil_tmp67 ;
   struct drm_i915_error_buffer *__cil_tmp68 ;
   unsigned long __cil_tmp69 ;
   struct drm_i915_error_buffer *__cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   struct drm_i915_error_buffer *__cil_tmp72 ;
   u32 __cil_tmp73 ;
   int __cil_tmp74 ;
   struct drm_i915_error_object *__cil_tmp75 ;
   unsigned long __cil_tmp76 ;
   struct drm_i915_error_object *__cil_tmp77 ;
   unsigned long __cil_tmp78 ;
   char const   *__cil_tmp79 ;
   u32 __cil_tmp80 ;
   unsigned long __cil_tmp81 ;
   u32 *__cil_tmp82 ;
   u32 *__cil_tmp83 ;
   u32 __cil_tmp84 ;
   unsigned int __cil_tmp85 ;
   int __cil_tmp86 ;
   unsigned int __cil_tmp87 ;
   struct drm_i915_error_object *__cil_tmp88 ;
   unsigned long __cil_tmp89 ;
   struct drm_i915_error_object *__cil_tmp90 ;
   unsigned long __cil_tmp91 ;
   char const   *__cil_tmp92 ;
   u32 __cil_tmp93 ;
   unsigned long __cil_tmp94 ;
   u32 *__cil_tmp95 ;
   u32 *__cil_tmp96 ;
   u32 __cil_tmp97 ;
   unsigned int __cil_tmp98 ;
   int __cil_tmp99 ;
   unsigned int __cil_tmp100 ;
   struct intel_overlay_error_state *__cil_tmp101 ;
   unsigned long __cil_tmp102 ;
   struct intel_overlay_error_state *__cil_tmp103 ;
   unsigned long __cil_tmp104 ;
   struct intel_overlay_error_state *__cil_tmp105 ;
   struct intel_display_error_state *__cil_tmp106 ;
   unsigned long __cil_tmp107 ;
   struct intel_display_error_state *__cil_tmp108 ;
   unsigned long __cil_tmp109 ;
   struct intel_display_error_state *__cil_tmp110 ;
   spinlock_t *__cil_tmp111 ;
 
   {
   {
 #line 740
   __cil_tmp15 = m->private;
 #line 740
   node = (struct drm_info_node *)__cil_tmp15;
 #line 741
   __cil_tmp16 = node->minor;
 #line 741
   dev = __cil_tmp16->dev;
 #line 742
   __cil_tmp17 = dev->dev_private;
 #line 742
   dev_priv = (drm_i915_private_t *)__cil_tmp17;
 #line 747
   __cil_tmp18 = & dev_priv->error_lock;
 #line 747
   tmp = spinlock_check(__cil_tmp18);
 #line 747
   flags = _raw_spin_lock_irqsave(tmp);
   }
   {
 #line 748
   __cil_tmp19 = (struct drm_i915_error_state *)0;
 #line 748
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 748
   __cil_tmp21 = dev_priv->first_error;
 #line 748
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 748
   if (__cil_tmp22 == __cil_tmp20) {
     {
 #line 749
     seq_printf(m, "no error state collected\n");
     }
 #line 750
     goto out;
   } else {
 
   }
   }
   {
 #line 753
   error = dev_priv->first_error;
 #line 755
   __cil_tmp23 = error->time.tv_sec;
 #line 755
   __cil_tmp24 = error->time.tv_usec;
 #line 755
   seq_printf(m, "Time: %ld s %ld us\n", __cil_tmp23, __cil_tmp24);
 #line 757
   __cil_tmp25 = dev->pci_device;
 #line 757
   seq_printf(m, "PCI ID: 0x%04x\n", __cil_tmp25);
 #line 758
   __cil_tmp26 = error->eir;
 #line 758
   seq_printf(m, "EIR: 0x%08x\n", __cil_tmp26);
 #line 759
   __cil_tmp27 = error->pgtbl_er;
 #line 759
   seq_printf(m, "PGTBL_ER: 0x%08x\n", __cil_tmp27);
   }
   {
 #line 760
   __cil_tmp28 = dev->dev_private;
 #line 760
   __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 760
   __cil_tmp30 = __cil_tmp29->info;
 #line 760
   __cil_tmp31 = __cil_tmp30->gen;
 #line 760
   __cil_tmp32 = (unsigned char )__cil_tmp31;
 #line 760
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 760
   if (__cil_tmp33 > 5U) {
     {
 #line 761
     __cil_tmp34 = error->error;
 #line 761
     seq_printf(m, "ERROR: 0x%08x\n", __cil_tmp34);
 #line 762
     seq_printf(m, "Blitter command stream:\n");
 #line 763
     __cil_tmp35 = error->bcs_acthd;
 #line 763
     seq_printf(m, "  ACTHD:    0x%08x\n", __cil_tmp35);
 #line 764
     __cil_tmp36 = error->bcs_ipeir;
 #line 764
     seq_printf(m, "  IPEIR:    0x%08x\n", __cil_tmp36);
 #line 765
     __cil_tmp37 = error->bcs_ipehr;
 #line 765
     seq_printf(m, "  IPEHR:    0x%08x\n", __cil_tmp37);
 #line 766
     __cil_tmp38 = error->bcs_instdone;
 #line 766
     seq_printf(m, "  INSTDONE: 0x%08x\n", __cil_tmp38);
 #line 767
     __cil_tmp39 = error->bcs_seqno;
 #line 767
     seq_printf(m, "  seqno:    0x%08x\n", __cil_tmp39);
 #line 768
     seq_printf(m, "Video (BSD) command stream:\n");
 #line 769
     __cil_tmp40 = error->vcs_acthd;
 #line 769
     seq_printf(m, "  ACTHD:    0x%08x\n", __cil_tmp40);
 #line 770
     __cil_tmp41 = error->vcs_ipeir;
 #line 770
     seq_printf(m, "  IPEIR:    0x%08x\n", __cil_tmp41);
 #line 771
     __cil_tmp42 = error->vcs_ipehr;
 #line 771
     seq_printf(m, "  IPEHR:    0x%08x\n", __cil_tmp42);
 #line 772
     __cil_tmp43 = error->vcs_instdone;
 #line 772
     seq_printf(m, "  INSTDONE: 0x%08x\n", __cil_tmp43);
 #line 773
     __cil_tmp44 = error->vcs_seqno;
 #line 773
     seq_printf(m, "  seqno:    0x%08x\n", __cil_tmp44);
     }
   } else {
 
   }
   }
   {
 #line 775
   seq_printf(m, "Render command stream:\n");
 #line 776
   __cil_tmp45 = error->acthd;
 #line 776
   seq_printf(m, "  ACTHD: 0x%08x\n", __cil_tmp45);
 #line 777
   __cil_tmp46 = error->ipeir;
 #line 777
   seq_printf(m, "  IPEIR: 0x%08x\n", __cil_tmp46);
 #line 778
   __cil_tmp47 = error->ipehr;
 #line 778
   seq_printf(m, "  IPEHR: 0x%08x\n", __cil_tmp47);
 #line 779
   __cil_tmp48 = error->instdone;
 #line 779
   seq_printf(m, "  INSTDONE: 0x%08x\n", __cil_tmp48);
   }
   {
 #line 780
   __cil_tmp49 = dev->dev_private;
 #line 780
   __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
 #line 780
   __cil_tmp51 = __cil_tmp50->info;
 #line 780
   __cil_tmp52 = __cil_tmp51->gen;
 #line 780
   __cil_tmp53 = (unsigned char )__cil_tmp52;
 #line 780
   __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 780
   if (__cil_tmp54 > 3U) {
     {
 #line 781
     __cil_tmp55 = error->instdone1;
 #line 781
     seq_printf(m, "  INSTDONE1: 0x%08x\n", __cil_tmp55);
 #line 782
     __cil_tmp56 = error->instps;
 #line 782
     seq_printf(m, "  INSTPS: 0x%08x\n", __cil_tmp56);
     }
   } else {
 
   }
   }
   {
 #line 784
   __cil_tmp57 = error->instpm;
 #line 784
   seq_printf(m, "  INSTPM: 0x%08x\n", __cil_tmp57);
 #line 785
   __cil_tmp58 = error->seqno;
 #line 785
   seq_printf(m, "  seqno: 0x%08x\n", __cil_tmp58);
 #line 787
   i = 0;
   }
 #line 787
   goto ldv_37997;
   ldv_37996: 
   {
 #line 788
   __cil_tmp59 = error->fence[i];
 #line 788
   seq_printf(m, "  fence[%d] = %08llx\n", i, __cil_tmp59);
 #line 787
   i = i + 1;
   }
   ldv_37997: ;
   {
 #line 787
   __cil_tmp60 = dev_priv->num_fence_regs;
 #line 787
   if (__cil_tmp60 > i) {
 #line 788
     goto ldv_37996;
   } else {
 #line 790
     goto ldv_37998;
   }
   }
   ldv_37998: ;
   {
 #line 790
   __cil_tmp61 = (struct drm_i915_error_buffer *)0;
 #line 790
   __cil_tmp62 = (unsigned long )__cil_tmp61;
 #line 790
   __cil_tmp63 = error->active_bo;
 #line 790
   __cil_tmp64 = (unsigned long )__cil_tmp63;
 #line 790
   if (__cil_tmp64 != __cil_tmp62) {
     {
 #line 791
     __cil_tmp65 = error->active_bo;
 #line 791
     __cil_tmp66 = error->active_bo_count;
 #line 791
     __cil_tmp67 = (int )__cil_tmp66;
 #line 791
     print_error_buffers(m, "Active", __cil_tmp65, __cil_tmp67);
     }
   } else {
 
   }
   }
   {
 #line 795
   __cil_tmp68 = (struct drm_i915_error_buffer *)0;
 #line 795
   __cil_tmp69 = (unsigned long )__cil_tmp68;
 #line 795
   __cil_tmp70 = error->pinned_bo;
 #line 795
   __cil_tmp71 = (unsigned long )__cil_tmp70;
 #line 795
   if (__cil_tmp71 != __cil_tmp69) {
     {
 #line 796
     __cil_tmp72 = error->pinned_bo;
 #line 796
     __cil_tmp73 = error->pinned_bo_count;
 #line 796
     __cil_tmp74 = (int )__cil_tmp73;
 #line 796
     print_error_buffers(m, "Pinned", __cil_tmp72, __cil_tmp74);
     }
   } else {
 
   }
   }
 #line 800
   i = 0;
 #line 800
   goto ldv_38009;
   ldv_38008: ;
   {
 #line 801
   __cil_tmp75 = (struct drm_i915_error_object *)0;
 #line 801
   __cil_tmp76 = (unsigned long )__cil_tmp75;
 #line 801
   __cil_tmp77 = error->batchbuffer[i];
 #line 801
   __cil_tmp78 = (unsigned long )__cil_tmp77;
 #line 801
   if (__cil_tmp78 != __cil_tmp76) {
     {
 #line 802
     obj = error->batchbuffer[i];
 #line 804
     __cil_tmp79 = dev_priv->ring[i].name;
 #line 804
     __cil_tmp80 = obj->gtt_offset;
 #line 804
     seq_printf(m, "%s --- gtt_offset = 0x%08x\n", __cil_tmp79, __cil_tmp80);
 #line 807
     offset = 0;
 #line 808
     page = 0;
     }
 #line 808
     goto ldv_38006;
     ldv_38005: 
 #line 809
     elt = 0;
 #line 809
     goto ldv_38003;
     ldv_38002: 
     {
 #line 810
     __cil_tmp81 = (unsigned long )elt;
 #line 810
     __cil_tmp82 = obj->pages[page];
 #line 810
     __cil_tmp83 = __cil_tmp82 + __cil_tmp81;
 #line 810
     __cil_tmp84 = *__cil_tmp83;
 #line 810
     seq_printf(m, "%08x :  %08x\n", offset, __cil_tmp84);
 #line 811
     offset = offset + 4;
 #line 809
     elt = elt + 1;
     }
     ldv_38003: ;
     {
 #line 809
     __cil_tmp85 = (unsigned int )elt;
 #line 809
     if (__cil_tmp85 <= 1023U) {
 #line 810
       goto ldv_38002;
     } else {
 #line 812
       goto ldv_38004;
     }
     }
     ldv_38004: 
 #line 808
     page = page + 1;
     ldv_38006: ;
     {
 #line 808
     __cil_tmp86 = obj->page_count;
 #line 808
     if (__cil_tmp86 > page) {
 #line 809
       goto ldv_38005;
     } else {
 #line 811
       goto ldv_38007;
     }
     }
     ldv_38007: ;
   } else {
 
   }
   }
 #line 800
   i = i + 1;
   ldv_38009: ;
   {
 #line 800
   __cil_tmp87 = (unsigned int )i;
 #line 800
   if (__cil_tmp87 <= 2U) {
 #line 801
     goto ldv_38008;
   } else {
 #line 803
     goto ldv_38010;
   }
   }
   ldv_38010: 
 #line 817
   i = 0;
 #line 817
   goto ldv_38021;
   ldv_38020: ;
   {
 #line 818
   __cil_tmp88 = (struct drm_i915_error_object *)0;
 #line 818
   __cil_tmp89 = (unsigned long )__cil_tmp88;
 #line 818
   __cil_tmp90 = error->ringbuffer[i];
 #line 818
   __cil_tmp91 = (unsigned long )__cil_tmp90;
 #line 818
   if (__cil_tmp91 != __cil_tmp89) {
     {
 #line 819
     obj___0 = error->ringbuffer[i];
 #line 820
     __cil_tmp92 = dev_priv->ring[i].name;
 #line 820
     __cil_tmp93 = obj___0->gtt_offset;
 #line 820
     seq_printf(m, "%s --- ringbuffer = 0x%08x\n", __cil_tmp92, __cil_tmp93);
 #line 823
     offset = 0;
 #line 824
     page = 0;
     }
 #line 824
     goto ldv_38018;
     ldv_38017: 
 #line 825
     elt = 0;
 #line 825
     goto ldv_38015;
     ldv_38014: 
     {
 #line 826
     __cil_tmp94 = (unsigned long )elt;
 #line 826
     __cil_tmp95 = obj___0->pages[page];
 #line 826
     __cil_tmp96 = __cil_tmp95 + __cil_tmp94;
 #line 826
     __cil_tmp97 = *__cil_tmp96;
 #line 826
     seq_printf(m, "%08x :  %08x\n", offset, __cil_tmp97);
 #line 829
     offset = offset + 4;
 #line 825
     elt = elt + 1;
     }
     ldv_38015: ;
     {
 #line 825
     __cil_tmp98 = (unsigned int )elt;
 #line 825
     if (__cil_tmp98 <= 1023U) {
 #line 826
       goto ldv_38014;
     } else {
 #line 828
       goto ldv_38016;
     }
     }
     ldv_38016: 
 #line 824
     page = page + 1;
     ldv_38018: ;
     {
 #line 824
     __cil_tmp99 = obj___0->page_count;
 #line 824
     if (__cil_tmp99 > page) {
 #line 825
       goto ldv_38017;
     } else {
 #line 827
       goto ldv_38019;
     }
     }
     ldv_38019: ;
   } else {
 
   }
   }
 #line 817
   i = i + 1;
   ldv_38021: ;
   {
 #line 817
   __cil_tmp100 = (unsigned int )i;
 #line 817
   if (__cil_tmp100 <= 2U) {
 #line 818
     goto ldv_38020;
   } else {
 #line 820
     goto ldv_38022;
   }
   }
   ldv_38022: ;
   {
 #line 835
   __cil_tmp101 = (struct intel_overlay_error_state *)0;
 #line 835
   __cil_tmp102 = (unsigned long )__cil_tmp101;
 #line 835
   __cil_tmp103 = error->overlay;
 #line 835
   __cil_tmp104 = (unsigned long )__cil_tmp103;
 #line 835
   if (__cil_tmp104 != __cil_tmp102) {
     {
 #line 836
     __cil_tmp105 = error->overlay;
 #line 836
     intel_overlay_print_error_state(m, __cil_tmp105);
     }
   } else {
 
   }
   }
   {
 #line 838
   __cil_tmp106 = (struct intel_display_error_state *)0;
 #line 838
   __cil_tmp107 = (unsigned long )__cil_tmp106;
 #line 838
   __cil_tmp108 = error->display;
 #line 838
   __cil_tmp109 = (unsigned long )__cil_tmp108;
 #line 838
   if (__cil_tmp109 != __cil_tmp107) {
     {
 #line 839
     __cil_tmp110 = error->display;
 #line 839
     intel_display_print_error_state(m, dev, __cil_tmp110);
     }
   } else {
 
   }
   }
   out: 
   {
 #line 842
   __cil_tmp111 = & dev_priv->error_lock;
 #line 842
   spin_unlock_irqrestore(__cil_tmp111, flags);
   }
 #line 844
   return (0);
 }
 }
 #line 847 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_rstdby_delays(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u16 crstanddelay ;
   u16 tmp ;
   void *__cil_tmp8 ;
   struct drm_minor *__cil_tmp9 ;
   void *__cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
 
   {
   {
 #line 849
   __cil_tmp8 = m->private;
 #line 849
   node = (struct drm_info_node *)__cil_tmp8;
 #line 850
   __cil_tmp9 = node->minor;
 #line 850
   dev = __cil_tmp9->dev;
 #line 851
   __cil_tmp10 = dev->dev_private;
 #line 851
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 852
   tmp = i915_read16___0(dev_priv, 69888U);
 #line 852
   crstanddelay = tmp;
 #line 854
   __cil_tmp11 = (int )crstanddelay;
 #line 854
   __cil_tmp12 = __cil_tmp11 >> 8;
 #line 854
   __cil_tmp13 = __cil_tmp12 & 63;
 #line 854
   __cil_tmp14 = (int )crstanddelay;
 #line 854
   __cil_tmp15 = __cil_tmp14 & 63;
 #line 854
   seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", __cil_tmp13, __cil_tmp15);
   }
 #line 856
   return (0);
 }
 }
 #line 859 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_cur_delayinfo(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   u16 rgvswctl ;
   u16 tmp ;
   u16 rgvstat ;
   u16 tmp___0 ;
   u32 gt_perf_status ;
   u32 tmp___1 ;
   u32 rp_state_limits ;
   u32 tmp___2 ;
   u32 rp_state_cap ;
   u32 tmp___3 ;
   u32 rpstat ;
   u32 rpupei ;
   u32 rpcurup ;
   u32 rpprevup ;
   u32 rpdownei ;
   u32 rpcurdown ;
   u32 rpprevdown ;
   int max_freq ;
   void *__cil_tmp25 ;
   struct drm_minor *__cil_tmp26 ;
   void *__cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   int __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   void *__cil_tmp45 ;
   struct drm_i915_private *__cil_tmp46 ;
   struct intel_device_info  const  *__cil_tmp47 ;
   u8 __cil_tmp48 ;
   unsigned char __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   struct mutex *__cil_tmp51 ;
   struct mutex *__cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   int __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   unsigned int __cil_tmp70 ;
   int __cil_tmp71 ;
   int __cil_tmp72 ;
   int __cil_tmp73 ;
 
   {
 #line 861
   __cil_tmp25 = m->private;
 #line 861
   node = (struct drm_info_node *)__cil_tmp25;
 #line 862
   __cil_tmp26 = node->minor;
 #line 862
   dev = __cil_tmp26->dev;
 #line 863
   __cil_tmp27 = dev->dev_private;
 #line 863
   dev_priv = (drm_i915_private_t *)__cil_tmp27;
   {
 #line 866
   __cil_tmp28 = dev->dev_private;
 #line 866
   __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 866
   __cil_tmp30 = __cil_tmp29->info;
 #line 866
   __cil_tmp31 = __cil_tmp30->gen;
 #line 866
   __cil_tmp32 = (unsigned char )__cil_tmp31;
 #line 866
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 866
   if (__cil_tmp33 == 5U) {
     {
 #line 867
     tmp = i915_read16___0(dev_priv, 70000U);
 #line 867
     rgvswctl = tmp;
 #line 868
     tmp___0 = i915_read16___0(dev_priv, 70136U);
 #line 868
     rgvstat = tmp___0;
 #line 870
     __cil_tmp34 = (int )rgvswctl;
 #line 870
     __cil_tmp35 = __cil_tmp34 >> 8;
 #line 870
     __cil_tmp36 = __cil_tmp35 & 15;
 #line 870
     seq_printf(m, "Requested P-state: %d\n", __cil_tmp36);
 #line 871
     __cil_tmp37 = (int )rgvswctl;
 #line 871
     __cil_tmp38 = __cil_tmp37 & 63;
 #line 871
     seq_printf(m, "Requested VID: %d\n", __cil_tmp38);
 #line 872
     __cil_tmp39 = (int )rgvstat;
 #line 872
     __cil_tmp40 = __cil_tmp39 & 32512;
 #line 872
     __cil_tmp41 = __cil_tmp40 >> 8;
 #line 872
     seq_printf(m, "Current VID: %d\n", __cil_tmp41);
 #line 874
     __cil_tmp42 = (int )rgvstat;
 #line 874
     __cil_tmp43 = __cil_tmp42 & 248;
 #line 874
     __cil_tmp44 = __cil_tmp43 >> 3;
 #line 874
     seq_printf(m, "Current P-state: %d\n", __cil_tmp44);
     }
   } else {
     {
 #line 876
     __cil_tmp45 = dev->dev_private;
 #line 876
     __cil_tmp46 = (struct drm_i915_private *)__cil_tmp45;
 #line 876
     __cil_tmp47 = __cil_tmp46->info;
 #line 876
     __cil_tmp48 = __cil_tmp47->gen;
 #line 876
     __cil_tmp49 = (unsigned char )__cil_tmp48;
 #line 876
     __cil_tmp50 = (unsigned int )__cil_tmp49;
 #line 876
     if (__cil_tmp50 == 6U) {
       {
 #line 877
       tmp___1 = i915_read32___2(dev_priv, 1333576U);
 #line 877
       gt_perf_status = tmp___1;
 #line 878
       tmp___2 = i915_read32___2(dev_priv, 1333652U);
 #line 878
       rp_state_limits = tmp___2;
 #line 879
       tmp___3 = i915_read32___2(dev_priv, 1333656U);
 #line 879
       rp_state_cap = tmp___3;
 #line 886
       __cil_tmp51 = & dev->struct_mutex;
 #line 886
       ret = mutex_lock_interruptible_nested(__cil_tmp51, 0U);
       }
 #line 887
       if (ret != 0) {
 #line 888
         return (ret);
       } else {
 
       }
       {
 #line 890
       gen6_gt_force_wake_get(dev_priv);
 #line 892
       rpstat = i915_read32___2(dev_priv, 40988U);
 #line 893
       rpupei = i915_read32___2(dev_priv, 41040U);
 #line 894
       rpcurup = i915_read32___2(dev_priv, 41044U);
 #line 895
       rpprevup = i915_read32___2(dev_priv, 41048U);
 #line 896
       rpdownei = i915_read32___2(dev_priv, 41052U);
 #line 897
       rpcurdown = i915_read32___2(dev_priv, 41056U);
 #line 898
       rpprevdown = i915_read32___2(dev_priv, 41060U);
 #line 900
       gen6_gt_force_wake_put(dev_priv);
 #line 901
       __cil_tmp52 = & dev->struct_mutex;
 #line 901
       mutex_unlock(__cil_tmp52);
 #line 903
       seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 #line 904
       seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 #line 905
       __cil_tmp53 = gt_perf_status & 65280U;
 #line 905
       __cil_tmp54 = __cil_tmp53 >> 8;
 #line 905
       seq_printf(m, "Render p-state ratio: %d\n", __cil_tmp54);
 #line 907
       __cil_tmp55 = gt_perf_status & 255U;
 #line 907
       seq_printf(m, "Render p-state VID: %d\n", __cil_tmp55);
 #line 909
       __cil_tmp56 = rp_state_limits & 255U;
 #line 909
       seq_printf(m, "Render p-state limit: %d\n", __cil_tmp56);
 #line 911
       __cil_tmp57 = rpstat & 32512U;
 #line 911
       __cil_tmp58 = __cil_tmp57 >> 8;
 #line 911
       __cil_tmp59 = __cil_tmp58 * 50U;
 #line 911
       seq_printf(m, "CAGF: %dMHz\n", __cil_tmp59);
 #line 913
       __cil_tmp60 = rpupei & 16777215U;
 #line 913
       seq_printf(m, "RP CUR UP EI: %dus\n", __cil_tmp60);
 #line 915
       __cil_tmp61 = rpcurup & 16777215U;
 #line 915
       seq_printf(m, "RP CUR UP: %dus\n", __cil_tmp61);
 #line 917
       __cil_tmp62 = rpprevup & 16777215U;
 #line 917
       seq_printf(m, "RP PREV UP: %dus\n", __cil_tmp62);
 #line 919
       __cil_tmp63 = rpdownei & 16777215U;
 #line 919
       seq_printf(m, "RP CUR DOWN EI: %dus\n", __cil_tmp63);
 #line 921
       __cil_tmp64 = rpcurdown & 16777215U;
 #line 921
       seq_printf(m, "RP CUR DOWN: %dus\n", __cil_tmp64);
 #line 923
       __cil_tmp65 = rpprevdown & 16777215U;
 #line 923
       seq_printf(m, "RP PREV DOWN: %dus\n", __cil_tmp65);
 #line 926
       __cil_tmp66 = rp_state_cap & 16711680U;
 #line 926
       __cil_tmp67 = __cil_tmp66 >> 16;
 #line 926
       max_freq = (int )__cil_tmp67;
 #line 927
       __cil_tmp68 = max_freq * 50;
 #line 927
       seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", __cil_tmp68);
 #line 930
       __cil_tmp69 = rp_state_cap & 65280U;
 #line 930
       __cil_tmp70 = __cil_tmp69 >> 8;
 #line 930
       max_freq = (int )__cil_tmp70;
 #line 931
       __cil_tmp71 = max_freq * 50;
 #line 931
       seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", __cil_tmp71);
 #line 934
       __cil_tmp72 = (int )rp_state_cap;
 #line 934
       max_freq = __cil_tmp72 & 255;
 #line 935
       __cil_tmp73 = max_freq * 50;
 #line 935
       seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", __cil_tmp73);
       }
     } else {
       {
 #line 938
       seq_printf(m, "no P-state info available\n");
       }
     }
     }
   }
   }
 #line 941
   return (0);
 }
 }
 #line 944 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_delayfreq_table(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 delayfreq ;
   int i ;
   void *__cil_tmp8 ;
   struct drm_minor *__cil_tmp9 ;
   void *__cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   u32 __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
 
   {
 #line 946
   __cil_tmp8 = m->private;
 #line 946
   node = (struct drm_info_node *)__cil_tmp8;
 #line 947
   __cil_tmp9 = node->minor;
 #line 947
   dev = __cil_tmp9->dev;
 #line 948
   __cil_tmp10 = dev->dev_private;
 #line 948
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 952
   i = 0;
 #line 952
   goto ldv_38062;
   ldv_38061: 
   {
 #line 953
   __cil_tmp11 = i + 17476;
 #line 953
   __cil_tmp12 = __cil_tmp11 * 4;
 #line 953
   __cil_tmp13 = (u32 )__cil_tmp12;
 #line 953
   delayfreq = i915_read32___2(dev_priv, __cil_tmp13);
 #line 954
   __cil_tmp14 = delayfreq & 2130706432U;
 #line 954
   __cil_tmp15 = __cil_tmp14 >> 24;
 #line 954
   seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, __cil_tmp15);
 #line 952
   i = i + 1;
   }
   ldv_38062: ;
 #line 952
   if (i <= 15) {
 #line 953
     goto ldv_38061;
   } else {
 #line 955
     goto ldv_38063;
   }
   ldv_38063: ;
 #line 958
   return (0);
 }
 }
 #line 966 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_inttoext_table(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 inttoext ;
   int i ;
   void *__cil_tmp8 ;
   struct drm_minor *__cil_tmp9 ;
   void *__cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   u32 __cil_tmp13 ;
 
   {
 #line 968
   __cil_tmp8 = m->private;
 #line 968
   node = (struct drm_info_node *)__cil_tmp8;
 #line 969
   __cil_tmp9 = node->minor;
 #line 969
   dev = __cil_tmp9->dev;
 #line 970
   __cil_tmp10 = dev->dev_private;
 #line 970
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 974
   i = 1;
 #line 974
   goto ldv_38077;
   ldv_38076: 
   {
 #line 975
   __cil_tmp11 = i + 17600;
 #line 975
   __cil_tmp12 = __cil_tmp11 * 4;
 #line 975
   __cil_tmp13 = (u32 )__cil_tmp12;
 #line 975
   inttoext = i915_read32___2(dev_priv, __cil_tmp13);
 #line 976
   seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 #line 974
   i = i + 1;
   }
   ldv_38077: ;
 #line 974
   if (i <= 32) {
 #line 975
     goto ldv_38076;
   } else {
 #line 977
     goto ldv_38078;
   }
   ldv_38078: ;
 #line 979
   return (0);
 }
 }
 #line 982 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_drpc_info(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 rgvmodectl ;
   u32 tmp ;
   u32 rstdbyctl ;
   u32 tmp___0 ;
   u16 crstandvid ;
   u16 tmp___1 ;
   char *tmp___2 ;
   char *tmp___3 ;
   char *tmp___4 ;
   char *tmp___5 ;
   char *tmp___6 ;
   void *__cil_tmp17 ;
   struct drm_minor *__cil_tmp18 ;
   void *__cil_tmp19 ;
   int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   int __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   int __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   int __cil_tmp48 ;
 
   {
   {
 #line 984
   __cil_tmp17 = m->private;
 #line 984
   node = (struct drm_info_node *)__cil_tmp17;
 #line 985
   __cil_tmp18 = node->minor;
 #line 985
   dev = __cil_tmp18->dev;
 #line 986
   __cil_tmp19 = dev->dev_private;
 #line 986
   dev_priv = (drm_i915_private_t *)__cil_tmp19;
 #line 987
   tmp = i915_read32___2(dev_priv, 70032U);
 #line 987
   rgvmodectl = tmp;
 #line 988
   tmp___0 = i915_read32___2(dev_priv, 70072U);
 #line 988
   rstdbyctl = tmp___0;
 #line 989
   tmp___1 = i915_read16___0(dev_priv, 69888U);
 #line 989
   crstandvid = tmp___1;
   }
   {
 #line 991
   __cil_tmp20 = (int )rgvmodectl;
 #line 991
   if (__cil_tmp20 < 0) {
 #line 991
     tmp___2 = (char *)"yes";
   } else {
 #line 991
     tmp___2 = (char *)"no";
   }
   }
   {
 #line 991
   seq_printf(m, "HD boost: %s\n", tmp___2);
 #line 993
   __cil_tmp21 = rgvmodectl & 251658240U;
 #line 993
   __cil_tmp22 = __cil_tmp21 >> 24;
 #line 993
   seq_printf(m, "Boost freq: %d\n", __cil_tmp22);
   }
   {
 #line 996
   __cil_tmp23 = rgvmodectl & 32768U;
 #line 996
   if (__cil_tmp23 != 0U) {
 #line 996
     tmp___3 = (char *)"yes";
   } else {
 #line 996
     tmp___3 = (char *)"no";
   }
   }
   {
 #line 996
   seq_printf(m, "HW control enabled: %s\n", tmp___3);
   }
   {
 #line 998
   __cil_tmp24 = rgvmodectl & 16384U;
 #line 998
   if (__cil_tmp24 != 0U) {
 #line 998
     tmp___4 = (char *)"yes";
   } else {
 #line 998
     tmp___4 = (char *)"no";
   }
   }
   {
 #line 998
   seq_printf(m, "SW control enabled: %s\n", tmp___4);
   }
   {
 #line 1000
   __cil_tmp25 = rgvmodectl & 8192U;
 #line 1000
   if (__cil_tmp25 != 0U) {
 #line 1000
     tmp___5 = (char *)"yes";
   } else {
 #line 1000
     tmp___5 = (char *)"no";
   }
   }
   {
 #line 1000
   seq_printf(m, "Gated voltage change: %s\n", tmp___5);
 #line 1002
   __cil_tmp26 = rgvmodectl & 3840U;
 #line 1002
   __cil_tmp27 = __cil_tmp26 >> 8;
 #line 1002
   seq_printf(m, "Starting frequency: P%d\n", __cil_tmp27);
 #line 1004
   __cil_tmp28 = rgvmodectl & 240U;
 #line 1004
   __cil_tmp29 = __cil_tmp28 >> 4;
 #line 1004
   seq_printf(m, "Max P-state: P%d\n", __cil_tmp29);
 #line 1006
   __cil_tmp30 = rgvmodectl & 15U;
 #line 1006
   seq_printf(m, "Min P-state: P%d\n", __cil_tmp30);
 #line 1007
   __cil_tmp31 = (int )crstandvid;
 #line 1007
   __cil_tmp32 = __cil_tmp31 & 63;
 #line 1007
   seq_printf(m, "RS1 VID: %d\n", __cil_tmp32);
 #line 1008
   __cil_tmp33 = (int )crstandvid;
 #line 1008
   __cil_tmp34 = __cil_tmp33 >> 8;
 #line 1008
   __cil_tmp35 = __cil_tmp34 & 63;
 #line 1008
   seq_printf(m, "RS2 VID: %d\n", __cil_tmp35);
   }
   {
 #line 1009
   __cil_tmp36 = rstdbyctl & 8388608U;
 #line 1009
   if (__cil_tmp36 != 0U) {
 #line 1009
     tmp___6 = (char *)"no";
   } else {
 #line 1009
     tmp___6 = (char *)"yes";
   }
   }
   {
 #line 1009
   seq_printf(m, "Render standby enabled: %s\n", tmp___6);
 #line 1011
   seq_printf(m, "Current RS state: ");
   }
   {
 #line 1013
   __cil_tmp37 = rstdbyctl & 7340032U;
 #line 1013
   __cil_tmp38 = (int )__cil_tmp37;
 #line 1013
   if (__cil_tmp38 == 0) {
 #line 1013
     goto case_0;
   } else {
     {
 #line 1016
     __cil_tmp39 = rstdbyctl & 7340032U;
 #line 1016
     __cil_tmp40 = (int )__cil_tmp39;
 #line 1016
     if (__cil_tmp40 == 1048576) {
 #line 1016
       goto case_1048576;
     } else {
       {
 #line 1019
       __cil_tmp41 = rstdbyctl & 7340032U;
 #line 1019
       __cil_tmp42 = (int )__cil_tmp41;
 #line 1019
       if (__cil_tmp42 == 2097152) {
 #line 1019
         goto case_2097152;
       } else {
         {
 #line 1022
         __cil_tmp43 = rstdbyctl & 7340032U;
 #line 1022
         __cil_tmp44 = (int )__cil_tmp43;
 #line 1022
         if (__cil_tmp44 == 3145728) {
 #line 1022
           goto case_3145728;
         } else {
           {
 #line 1025
           __cil_tmp45 = rstdbyctl & 7340032U;
 #line 1025
           __cil_tmp46 = (int )__cil_tmp45;
 #line 1025
           if (__cil_tmp46 == 4194304) {
 #line 1025
             goto case_4194304;
           } else {
             {
 #line 1028
             __cil_tmp47 = rstdbyctl & 7340032U;
 #line 1028
             __cil_tmp48 = (int )__cil_tmp47;
 #line 1028
             if (__cil_tmp48 == 6291456) {
 #line 1028
               goto case_6291456;
             } else {
 #line 1031
               goto switch_default;
 #line 1012
               if (0) {
                 case_0: 
                 {
 #line 1014
                 seq_printf(m, "on\n");
                 }
 #line 1015
                 goto ldv_38090;
                 case_1048576: 
                 {
 #line 1017
                 seq_printf(m, "RC1\n");
                 }
 #line 1018
                 goto ldv_38090;
                 case_2097152: 
                 {
 #line 1020
                 seq_printf(m, "RC1E\n");
                 }
 #line 1021
                 goto ldv_38090;
                 case_3145728: 
                 {
 #line 1023
                 seq_printf(m, "RS1\n");
                 }
 #line 1024
                 goto ldv_38090;
                 case_4194304: 
                 {
 #line 1026
                 seq_printf(m, "RS2 (RC6)\n");
                 }
 #line 1027
                 goto ldv_38090;
                 case_6291456: 
                 {
 #line 1029
                 seq_printf(m, "RC3 (RC6+)\n");
                 }
 #line 1030
                 goto ldv_38090;
                 switch_default: 
                 {
 #line 1032
                 seq_printf(m, "unknown\n");
                 }
 #line 1033
                 goto ldv_38090;
               } else {
 
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_38090: ;
 #line 1036
   return (0);
 }
 }
 #line 1039 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_fbc_status(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   bool tmp ;
   void *__cil_tmp7 ;
   struct drm_minor *__cil_tmp8 ;
   void *__cil_tmp9 ;
   void *__cil_tmp10 ;
   struct drm_i915_private *__cil_tmp11 ;
   struct intel_device_info  const  *__cil_tmp12 ;
   unsigned char *__cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   enum no_fbc_reason __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   enum no_fbc_reason __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   int __cil_tmp22 ;
   enum no_fbc_reason __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   int __cil_tmp25 ;
   enum no_fbc_reason __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   enum no_fbc_reason __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   enum no_fbc_reason __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   int __cil_tmp34 ;
   enum no_fbc_reason __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   int __cil_tmp37 ;
   enum no_fbc_reason __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   int __cil_tmp40 ;
 
   {
 #line 1041
   __cil_tmp7 = m->private;
 #line 1041
   node = (struct drm_info_node *)__cil_tmp7;
 #line 1042
   __cil_tmp8 = node->minor;
 #line 1042
   dev = __cil_tmp8->dev;
 #line 1043
   __cil_tmp9 = dev->dev_private;
 #line 1043
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
   {
 #line 1045
   __cil_tmp10 = dev->dev_private;
 #line 1045
   __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
 #line 1045
   __cil_tmp12 = __cil_tmp11->info;
 #line 1045
   __cil_tmp13 = (unsigned char *)__cil_tmp12;
 #line 1045
   __cil_tmp14 = __cil_tmp13 + 2UL;
 #line 1045
   __cil_tmp15 = *__cil_tmp14;
 #line 1045
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 1045
   if (__cil_tmp16 == 0U) {
     {
 #line 1046
     seq_printf(m, "FBC unsupported on this chipset\n");
     }
 #line 1047
     return (0);
   } else {
 
   }
   }
   {
 #line 1050
   tmp = intel_fbc_enabled(dev);
   }
 #line 1050
   if ((int )tmp) {
     {
 #line 1051
     seq_printf(m, "FBC enabled\n");
     }
   } else {
     {
 #line 1053
     seq_printf(m, "FBC disabled: ");
     }
     {
 #line 1055
     __cil_tmp17 = dev_priv->no_fbc_reason;
 #line 1055
     __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 1055
     __cil_tmp19 = (int )__cil_tmp18;
 #line 1055
     if (__cil_tmp19 == 0) {
 #line 1055
       goto case_0;
     } else {
       {
 #line 1058
       __cil_tmp20 = dev_priv->no_fbc_reason;
 #line 1058
       __cil_tmp21 = (unsigned int )__cil_tmp20;
 #line 1058
       __cil_tmp22 = (int )__cil_tmp21;
 #line 1058
       if (__cil_tmp22 == 1) {
 #line 1058
         goto case_1;
       } else {
         {
 #line 1061
         __cil_tmp23 = dev_priv->no_fbc_reason;
 #line 1061
         __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 1061
         __cil_tmp25 = (int )__cil_tmp24;
 #line 1061
         if (__cil_tmp25 == 2) {
 #line 1061
           goto case_2;
         } else {
           {
 #line 1064
           __cil_tmp26 = dev_priv->no_fbc_reason;
 #line 1064
           __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1064
           __cil_tmp28 = (int )__cil_tmp27;
 #line 1064
           if (__cil_tmp28 == 3) {
 #line 1064
             goto case_3;
           } else {
             {
 #line 1067
             __cil_tmp29 = dev_priv->no_fbc_reason;
 #line 1067
             __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 1067
             __cil_tmp31 = (int )__cil_tmp30;
 #line 1067
             if (__cil_tmp31 == 4) {
 #line 1067
               goto case_4;
             } else {
               {
 #line 1070
               __cil_tmp32 = dev_priv->no_fbc_reason;
 #line 1070
               __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 1070
               __cil_tmp34 = (int )__cil_tmp33;
 #line 1070
               if (__cil_tmp34 == 5) {
 #line 1070
                 goto case_5;
               } else {
                 {
 #line 1073
                 __cil_tmp35 = dev_priv->no_fbc_reason;
 #line 1073
                 __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 1073
                 __cil_tmp37 = (int )__cil_tmp36;
 #line 1073
                 if (__cil_tmp37 == 6) {
 #line 1073
                   goto case_6;
                 } else {
                   {
 #line 1076
                   __cil_tmp38 = dev_priv->no_fbc_reason;
 #line 1076
                   __cil_tmp39 = (unsigned int )__cil_tmp38;
 #line 1076
                   __cil_tmp40 = (int )__cil_tmp39;
 #line 1076
                   if (__cil_tmp40 == 7) {
 #line 1076
                     goto case_7;
                   } else {
 #line 1079
                     goto switch_default;
 #line 1054
                     if (0) {
                       case_0: 
                       {
 #line 1056
                       seq_printf(m, "no outputs");
                       }
 #line 1057
                       goto ldv_38105;
                       case_1: 
                       {
 #line 1059
                       seq_printf(m, "not enough stolen memory");
                       }
 #line 1060
                       goto ldv_38105;
                       case_2: 
                       {
 #line 1062
                       seq_printf(m, "mode not supported");
                       }
 #line 1063
                       goto ldv_38105;
                       case_3: 
                       {
 #line 1065
                       seq_printf(m, "mode too large");
                       }
 #line 1066
                       goto ldv_38105;
                       case_4: 
                       {
 #line 1068
                       seq_printf(m, "FBC unsupported on plane");
                       }
 #line 1069
                       goto ldv_38105;
                       case_5: 
                       {
 #line 1071
                       seq_printf(m, "scanout buffer not tiled");
                       }
 #line 1072
                       goto ldv_38105;
                       case_6: 
                       {
 #line 1074
                       seq_printf(m, "multiple pipes are enabled");
                       }
 #line 1075
                       goto ldv_38105;
                       case_7: 
                       {
 #line 1077
                       seq_printf(m, "disabled per module param (default off)");
                       }
 #line 1078
                       goto ldv_38105;
                       switch_default: 
                       {
 #line 1080
                       seq_printf(m, "unknown reason");
                       }
                     } else {
 
                     }
                   }
                   }
                 }
                 }
               }
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
     ldv_38105: 
     {
 #line 1082
     seq_printf(m, "\n");
     }
   }
 #line 1084
   return (0);
 }
 }
 #line 1087 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_sr_status(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   bool sr_enabled ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   char *tmp___3 ;
   void *__cil_tmp12 ;
   struct drm_minor *__cil_tmp13 ;
   void *__cil_tmp14 ;
   void *__cil_tmp15 ;
   struct drm_i915_private *__cil_tmp16 ;
   struct intel_device_info  const  *__cil_tmp17 ;
   u8 __cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   int __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   u8 __cil_tmp26 ;
   unsigned char __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   int __cil_tmp30 ;
   void *__cil_tmp31 ;
   struct drm_i915_private *__cil_tmp32 ;
   struct intel_device_info  const  *__cil_tmp33 ;
   unsigned char *__cil_tmp34 ;
   unsigned char *__cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   int __cil_tmp39 ;
   void *__cil_tmp40 ;
   struct drm_i915_private *__cil_tmp41 ;
   struct intel_device_info  const  *__cil_tmp42 ;
   unsigned char *__cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   int __cil_tmp51 ;
   void *__cil_tmp52 ;
   struct drm_i915_private *__cil_tmp53 ;
   struct intel_device_info  const  *__cil_tmp54 ;
   unsigned char *__cil_tmp55 ;
   unsigned char *__cil_tmp56 ;
   unsigned char __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   int __cil_tmp60 ;
   int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   int __cil_tmp63 ;
   void *__cil_tmp64 ;
   struct drm_i915_private *__cil_tmp65 ;
   struct intel_device_info  const  *__cil_tmp66 ;
   unsigned char *__cil_tmp67 ;
   unsigned char *__cil_tmp68 ;
   unsigned char __cil_tmp69 ;
   unsigned int __cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   int __cil_tmp72 ;
 
   {
 #line 1089
   __cil_tmp12 = m->private;
 #line 1089
   node = (struct drm_info_node *)__cil_tmp12;
 #line 1090
   __cil_tmp13 = node->minor;
 #line 1090
   dev = __cil_tmp13->dev;
 #line 1091
   __cil_tmp14 = dev->dev_private;
 #line 1091
   dev_priv = (drm_i915_private_t *)__cil_tmp14;
 #line 1092
   sr_enabled = (bool )0;
   {
 #line 1094
   __cil_tmp15 = dev->dev_private;
 #line 1094
   __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
 #line 1094
   __cil_tmp17 = __cil_tmp16->info;
 #line 1094
   __cil_tmp18 = __cil_tmp17->gen;
 #line 1094
   __cil_tmp19 = (unsigned char )__cil_tmp18;
 #line 1094
   __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 1094
   if (__cil_tmp20 == 5U) {
     {
 #line 1095
     tmp = i915_read32___2(dev_priv, 282888U);
 #line 1095
     __cil_tmp21 = tmp & 2147483648U;
 #line 1095
     __cil_tmp22 = __cil_tmp21 != 0U;
 #line 1095
     sr_enabled = (bool )__cil_tmp22;
     }
   } else {
     {
 #line 1094
     __cil_tmp23 = dev->dev_private;
 #line 1094
     __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 1094
     __cil_tmp25 = __cil_tmp24->info;
 #line 1094
     __cil_tmp26 = __cil_tmp25->gen;
 #line 1094
     __cil_tmp27 = (unsigned char )__cil_tmp26;
 #line 1094
     __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 1094
     if (__cil_tmp28 == 6U) {
       {
 #line 1095
       tmp = i915_read32___2(dev_priv, 282888U);
 #line 1095
       __cil_tmp29 = tmp & 2147483648U;
 #line 1095
       __cil_tmp30 = __cil_tmp29 != 0U;
 #line 1095
       sr_enabled = (bool )__cil_tmp30;
       }
     } else {
       {
 #line 1094
       __cil_tmp31 = dev->dev_private;
 #line 1094
       __cil_tmp32 = (struct drm_i915_private *)__cil_tmp31;
 #line 1094
       __cil_tmp33 = __cil_tmp32->info;
 #line 1094
       __cil_tmp34 = (unsigned char *)__cil_tmp33;
 #line 1094
       __cil_tmp35 = __cil_tmp34 + 2UL;
 #line 1094
       __cil_tmp36 = *__cil_tmp35;
 #line 1094
       __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 1094
       if (__cil_tmp37 != 0U) {
         {
 #line 1095
         tmp = i915_read32___2(dev_priv, 282888U);
 #line 1095
         __cil_tmp38 = tmp & 2147483648U;
 #line 1095
         __cil_tmp39 = __cil_tmp38 != 0U;
 #line 1095
         sr_enabled = (bool )__cil_tmp39;
         }
       } else {
         {
 #line 1096
         __cil_tmp40 = dev->dev_private;
 #line 1096
         __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
 #line 1096
         __cil_tmp42 = __cil_tmp41->info;
 #line 1096
         __cil_tmp43 = (unsigned char *)__cil_tmp42;
 #line 1096
         __cil_tmp44 = __cil_tmp43 + 2UL;
 #line 1096
         __cil_tmp45 = *__cil_tmp44;
 #line 1096
         __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 1096
         if (__cil_tmp46 != 0U) {
           {
 #line 1097
           tmp___0 = i915_read32___2(dev_priv, 8416U);
 #line 1097
           __cil_tmp47 = tmp___0 & 32768U;
 #line 1097
           __cil_tmp48 = __cil_tmp47 != 0U;
 #line 1097
           sr_enabled = (bool )__cil_tmp48;
           }
         } else {
           {
 #line 1096
           __cil_tmp49 = dev->pci_device;
 #line 1096
           if (__cil_tmp49 == 10098) {
             {
 #line 1097
             tmp___0 = i915_read32___2(dev_priv, 8416U);
 #line 1097
             __cil_tmp50 = tmp___0 & 32768U;
 #line 1097
             __cil_tmp51 = __cil_tmp50 != 0U;
 #line 1097
             sr_enabled = (bool )__cil_tmp51;
             }
           } else {
             {
 #line 1096
             __cil_tmp52 = dev->dev_private;
 #line 1096
             __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
 #line 1096
             __cil_tmp54 = __cil_tmp53->info;
 #line 1096
             __cil_tmp55 = (unsigned char *)__cil_tmp54;
 #line 1096
             __cil_tmp56 = __cil_tmp55 + 1UL;
 #line 1096
             __cil_tmp57 = *__cil_tmp56;
 #line 1096
             __cil_tmp58 = (unsigned int )__cil_tmp57;
 #line 1096
             if (__cil_tmp58 != 0U) {
               {
 #line 1097
               tmp___0 = i915_read32___2(dev_priv, 8416U);
 #line 1097
               __cil_tmp59 = tmp___0 & 32768U;
 #line 1097
               __cil_tmp60 = __cil_tmp59 != 0U;
 #line 1097
               sr_enabled = (bool )__cil_tmp60;
               }
             } else {
               {
 #line 1098
               __cil_tmp61 = dev->pci_device;
 #line 1098
               if (__cil_tmp61 == 9618) {
                 {
 #line 1099
                 tmp___1 = i915_read32___2(dev_priv, 8384U);
 #line 1099
                 __cil_tmp62 = tmp___1 & 4096U;
 #line 1099
                 __cil_tmp63 = __cil_tmp62 != 0U;
 #line 1099
                 sr_enabled = (bool )__cil_tmp63;
                 }
               } else {
                 {
 #line 1100
                 __cil_tmp64 = dev->dev_private;
 #line 1100
                 __cil_tmp65 = (struct drm_i915_private *)__cil_tmp64;
 #line 1100
                 __cil_tmp66 = __cil_tmp65->info;
 #line 1100
                 __cil_tmp67 = (unsigned char *)__cil_tmp66;
 #line 1100
                 __cil_tmp68 = __cil_tmp67 + 1UL;
 #line 1100
                 __cil_tmp69 = *__cil_tmp68;
 #line 1100
                 __cil_tmp70 = (unsigned int )__cil_tmp69;
 #line 1100
                 if (__cil_tmp70 != 0U) {
                   {
 #line 1101
                   tmp___2 = i915_read32___2(dev_priv, 458812U);
 #line 1101
                   __cil_tmp71 = tmp___2 & 1073741824U;
 #line 1101
                   __cil_tmp72 = __cil_tmp71 != 0U;
 #line 1101
                   sr_enabled = (bool )__cil_tmp72;
                   }
                 } else {
 
                 }
                 }
               }
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
 #line 1103
   if ((int )sr_enabled) {
 #line 1103
     tmp___3 = (char *)"enabled";
   } else {
 #line 1103
     tmp___3 = (char *)"disabled";
   }
   {
 #line 1103
   seq_printf(m, "self-refresh: %s\n", tmp___3);
   }
 #line 1106
   return (0);
 }
 }
 #line 1109 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_emon_status(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   unsigned long temp ;
   unsigned long chipset ;
   unsigned long gfx ;
   int ret ;
   void *__cil_tmp10 ;
   struct drm_minor *__cil_tmp11 ;
   void *__cil_tmp12 ;
   struct mutex *__cil_tmp13 ;
   struct mutex *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
 
   {
   {
 #line 1111
   __cil_tmp10 = m->private;
 #line 1111
   node = (struct drm_info_node *)__cil_tmp10;
 #line 1112
   __cil_tmp11 = node->minor;
 #line 1112
   dev = __cil_tmp11->dev;
 #line 1113
   __cil_tmp12 = dev->dev_private;
 #line 1113
   dev_priv = (drm_i915_private_t *)__cil_tmp12;
 #line 1117
   __cil_tmp13 = & dev->struct_mutex;
 #line 1117
   ret = mutex_lock_interruptible_nested(__cil_tmp13, 0U);
   }
 #line 1118
   if (ret != 0) {
 #line 1119
     return (ret);
   } else {
 
   }
   {
 #line 1121
   temp = i915_mch_val(dev_priv);
 #line 1122
   chipset = i915_chipset_val(dev_priv);
 #line 1123
   gfx = i915_gfx_val(dev_priv);
 #line 1124
   __cil_tmp14 = & dev->struct_mutex;
 #line 1124
   mutex_unlock(__cil_tmp14);
 #line 1126
   seq_printf(m, "GMCH temp: %ld\n", temp);
 #line 1127
   seq_printf(m, "Chipset power: %ld\n", chipset);
 #line 1128
   seq_printf(m, "GFX power: %ld\n", gfx);
 #line 1129
   __cil_tmp15 = chipset + gfx;
 #line 1129
   seq_printf(m, "Total power: %ld\n", __cil_tmp15);
   }
 #line 1131
   return (0);
 }
 }
 #line 1134 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gfxec(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 tmp ;
   void *__cil_tmp7 ;
   struct drm_minor *__cil_tmp8 ;
   void *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
 
   {
   {
 #line 1136
   __cil_tmp7 = m->private;
 #line 1136
   node = (struct drm_info_node *)__cil_tmp7;
 #line 1137
   __cil_tmp8 = node->minor;
 #line 1137
   dev = __cil_tmp8->dev;
 #line 1138
   __cil_tmp9 = dev->dev_private;
 #line 1138
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 1140
   tmp = i915_read32___2(dev_priv, 70388U);
 #line 1140
   __cil_tmp10 = (unsigned long )tmp;
 #line 1140
   seq_printf(m, "GFXEC: %ld\n", __cil_tmp10);
   }
 #line 1142
   return (0);
 }
 }
 #line 1145 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_opregion(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct intel_opregion *opregion ;
   int ret ;
   void *__cil_tmp8 ;
   struct drm_minor *__cil_tmp9 ;
   void *__cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   struct opregion_header *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct opregion_header *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct opregion_header *__cil_tmp16 ;
   void const   *__cil_tmp17 ;
   struct mutex *__cil_tmp18 ;
 
   {
   {
 #line 1147
   __cil_tmp8 = m->private;
 #line 1147
   node = (struct drm_info_node *)__cil_tmp8;
 #line 1148
   __cil_tmp9 = node->minor;
 #line 1148
   dev = __cil_tmp9->dev;
 #line 1149
   __cil_tmp10 = dev->dev_private;
 #line 1149
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 1150
   opregion = & dev_priv->opregion;
 #line 1153
   __cil_tmp11 = & dev->struct_mutex;
 #line 1153
   ret = mutex_lock_interruptible_nested(__cil_tmp11, 0U);
   }
 #line 1154
   if (ret != 0) {
 #line 1155
     return (ret);
   } else {
 
   }
   {
 #line 1157
   __cil_tmp12 = (struct opregion_header *)0;
 #line 1157
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 1157
   __cil_tmp14 = opregion->header;
 #line 1157
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 1157
   if (__cil_tmp15 != __cil_tmp13) {
     {
 #line 1158
     __cil_tmp16 = opregion->header;
 #line 1158
     __cil_tmp17 = (void const   *)__cil_tmp16;
 #line 1158
     seq_write(m, __cil_tmp17, 8192UL);
     }
   } else {
 
   }
   }
   {
 #line 1160
   __cil_tmp18 = & dev->struct_mutex;
 #line 1160
   mutex_unlock(__cil_tmp18);
   }
 #line 1162
   return (0);
 }
 }
 #line 1165 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gem_framebuffer_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct intel_fbdev *ifbdev ;
   struct intel_framebuffer *fb ;
   int ret ;
   struct drm_framebuffer  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   void *__cil_tmp12 ;
   struct drm_minor *__cil_tmp13 ;
   void *__cil_tmp14 ;
   struct mutex *__cil_tmp15 ;
   struct drm_framebuffer *__cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   int __cil_tmp20 ;
   struct drm_i915_gem_object *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct intel_framebuffer *__cil_tmp23 ;
   struct drm_framebuffer *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_framebuffer *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   struct drm_i915_gem_object *__cil_tmp32 ;
   struct list_head *__cil_tmp33 ;
   struct intel_framebuffer *__cil_tmp34 ;
   struct list_head *__cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   struct list_head *__cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   struct mutex *__cil_tmp39 ;
 
   {
   {
 #line 1167
   __cil_tmp12 = m->private;
 #line 1167
   node = (struct drm_info_node *)__cil_tmp12;
 #line 1168
   __cil_tmp13 = node->minor;
 #line 1168
   dev = __cil_tmp13->dev;
 #line 1169
   __cil_tmp14 = dev->dev_private;
 #line 1169
   dev_priv = (drm_i915_private_t *)__cil_tmp14;
 #line 1174
   __cil_tmp15 = & dev->mode_config.mutex;
 #line 1174
   ret = mutex_lock_interruptible_nested(__cil_tmp15, 0U);
   }
 #line 1175
   if (ret != 0) {
 #line 1176
     return (ret);
   } else {
 
   }
   {
 #line 1178
   ifbdev = dev_priv->fbdev;
 #line 1179
   __cil_tmp16 = ifbdev->helper.fb;
 #line 1179
   __mptr = (struct drm_framebuffer  const  *)__cil_tmp16;
 #line 1179
   fb = (struct intel_framebuffer *)__mptr;
 #line 1181
   __cil_tmp17 = fb->base.width;
 #line 1181
   __cil_tmp18 = fb->base.height;
 #line 1181
   __cil_tmp19 = fb->base.depth;
 #line 1181
   __cil_tmp20 = fb->base.bits_per_pixel;
 #line 1181
   seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ", __cil_tmp17, __cil_tmp18,
              __cil_tmp19, __cil_tmp20);
 #line 1186
   __cil_tmp21 = fb->obj;
 #line 1186
   describe_obj(m, __cil_tmp21);
 #line 1187
   seq_printf(m, "\n");
 #line 1189
   __cil_tmp22 = dev->mode_config.fb_list.next;
 #line 1189
   __mptr___0 = (struct list_head  const  *)__cil_tmp22;
 #line 1189
   __cil_tmp23 = (struct intel_framebuffer *)__mptr___0;
 #line 1189
   fb = __cil_tmp23 + 1152921504606846968UL;
   }
 #line 1189
   goto ldv_38167;
   ldv_38166: ;
   {
 #line 1190
   __cil_tmp24 = ifbdev->helper.fb;
 #line 1190
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 1190
   __cil_tmp26 = & fb->base;
 #line 1190
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 1190
   if (__cil_tmp27 == __cil_tmp25) {
 #line 1191
     goto ldv_38165;
   } else {
 
   }
   }
   {
 #line 1193
   __cil_tmp28 = fb->base.width;
 #line 1193
   __cil_tmp29 = fb->base.height;
 #line 1193
   __cil_tmp30 = fb->base.depth;
 #line 1193
   __cil_tmp31 = fb->base.bits_per_pixel;
 #line 1193
   seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ", __cil_tmp28, __cil_tmp29,
              __cil_tmp30, __cil_tmp31);
 #line 1198
   __cil_tmp32 = fb->obj;
 #line 1198
   describe_obj(m, __cil_tmp32);
 #line 1199
   seq_printf(m, "\n");
   }
   ldv_38165: 
 #line 1189
   __cil_tmp33 = fb->base.head.next;
 #line 1189
   __mptr___1 = (struct list_head  const  *)__cil_tmp33;
 #line 1189
   __cil_tmp34 = (struct intel_framebuffer *)__mptr___1;
 #line 1189
   fb = __cil_tmp34 + 1152921504606846968UL;
   ldv_38167: ;
   {
 #line 1189
   __cil_tmp35 = & dev->mode_config.fb_list;
 #line 1189
   __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 1189
   __cil_tmp37 = & fb->base.head;
 #line 1189
   __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 1189
   if (__cil_tmp38 != __cil_tmp36) {
 #line 1190
     goto ldv_38166;
   } else {
 #line 1192
     goto ldv_38168;
   }
   }
   ldv_38168: 
   {
 #line 1202
   __cil_tmp39 = & dev->mode_config.mutex;
 #line 1202
   mutex_unlock(__cil_tmp39);
   }
 #line 1204
   return (0);
 }
 }
 #line 1207 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_context_status(struct seq_file *m , void *unused ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   void *__cil_tmp7 ;
   struct drm_minor *__cil_tmp8 ;
   void *__cil_tmp9 ;
   struct mutex *__cil_tmp10 ;
   struct drm_i915_gem_object *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_i915_gem_object *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct drm_i915_gem_object *__cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct drm_i915_gem_object *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct drm_i915_gem_object *__cil_tmp20 ;
   struct mutex *__cil_tmp21 ;
 
   {
   {
 #line 1209
   __cil_tmp7 = m->private;
 #line 1209
   node = (struct drm_info_node *)__cil_tmp7;
 #line 1210
   __cil_tmp8 = node->minor;
 #line 1210
   dev = __cil_tmp8->dev;
 #line 1211
   __cil_tmp9 = dev->dev_private;
 #line 1211
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 1214
   __cil_tmp10 = & dev->mode_config.mutex;
 #line 1214
   ret = mutex_lock_interruptible_nested(__cil_tmp10, 0U);
   }
 #line 1215
   if (ret != 0) {
 #line 1216
     return (ret);
   } else {
 
   }
   {
 #line 1218
   __cil_tmp11 = (struct drm_i915_gem_object *)0;
 #line 1218
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 1218
   __cil_tmp13 = dev_priv->pwrctx;
 #line 1218
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 1218
   if (__cil_tmp14 != __cil_tmp12) {
     {
 #line 1219
     seq_printf(m, "power context ");
 #line 1220
     __cil_tmp15 = dev_priv->pwrctx;
 #line 1220
     describe_obj(m, __cil_tmp15);
 #line 1221
     seq_printf(m, "\n");
     }
   } else {
 
   }
   }
   {
 #line 1224
   __cil_tmp16 = (struct drm_i915_gem_object *)0;
 #line 1224
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 1224
   __cil_tmp18 = dev_priv->renderctx;
 #line 1224
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 1224
   if (__cil_tmp19 != __cil_tmp17) {
     {
 #line 1225
     seq_printf(m, "render context ");
 #line 1226
     __cil_tmp20 = dev_priv->renderctx;
 #line 1226
     describe_obj(m, __cil_tmp20);
 #line 1227
     seq_printf(m, "\n");
     }
   } else {
 
   }
   }
   {
 #line 1230
   __cil_tmp21 = & dev->mode_config.mutex;
 #line 1230
   mutex_unlock(__cil_tmp21);
   }
 #line 1232
   return (0);
 }
 }
 #line 1235 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_gen6_forcewake_count_info(struct seq_file *m , void *data ) 
 { struct drm_info_node *node ;
   struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   int tmp ;
   void *__cil_tmp7 ;
   struct drm_minor *__cil_tmp8 ;
   void *__cil_tmp9 ;
   atomic_t *__cil_tmp10 ;
   atomic_t const   *__cil_tmp11 ;
 
   {
   {
 #line 1237
   __cil_tmp7 = m->private;
 #line 1237
   node = (struct drm_info_node *)__cil_tmp7;
 #line 1238
   __cil_tmp8 = node->minor;
 #line 1238
   dev = __cil_tmp8->dev;
 #line 1239
   __cil_tmp9 = dev->dev_private;
 #line 1239
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 1241
   __cil_tmp10 = & dev_priv->forcewake_count;
 #line 1241
   __cil_tmp11 = (atomic_t const   *)__cil_tmp10;
 #line 1241
   tmp = atomic_read(__cil_tmp11);
 #line 1241
   seq_printf(m, "forcewake count = %d\n", tmp);
   }
 #line 1244
   return (0);
 }
 }
 #line 1248 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_wedged_open(struct inode *inode , struct file *filp ) 
 { 
 
   {
 #line 1251
   filp->private_data = inode->i_private;
 #line 1252
   return (0);
 }
 }
 #line 1256 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static ssize_t i915_wedged_read(struct file *filp , char *ubuf , size_t max , loff_t *ppos ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   char buf[80U] ;
   int len ;
   int tmp ;
   ssize_t tmp___0 ;
   void *__cil_tmp11 ;
   void *__cil_tmp12 ;
   atomic_t *__cil_tmp13 ;
   atomic_t const   *__cil_tmp14 ;
   char *__cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const   *__cil_tmp18 ;
   size_t __cil_tmp19 ;
 
   {
   {
 #line 1261
   __cil_tmp11 = filp->private_data;
 #line 1261
   dev = (struct drm_device *)__cil_tmp11;
 #line 1262
   __cil_tmp12 = dev->dev_private;
 #line 1262
   dev_priv = (drm_i915_private_t *)__cil_tmp12;
 #line 1266
   __cil_tmp13 = & dev_priv->mm.wedged;
 #line 1266
   __cil_tmp14 = (atomic_t const   *)__cil_tmp13;
 #line 1266
   tmp = atomic_read(__cil_tmp14);
 #line 1266
   __cil_tmp15 = (char *)(& buf);
 #line 1266
   len = snprintf(__cil_tmp15, 80UL, "wedged :  %d\n", tmp);
   }
   {
 #line 1270
   __cil_tmp16 = (unsigned int )len;
 #line 1270
   if (__cil_tmp16 > 80U) {
 #line 1271
     len = 80;
   } else {
 
   }
   }
   {
 #line 1273
   __cil_tmp17 = (void *)ubuf;
 #line 1273
   __cil_tmp18 = (void const   *)(& buf);
 #line 1273
   __cil_tmp19 = (size_t )len;
 #line 1273
   tmp___0 = simple_read_from_buffer(__cil_tmp17, max, ppos, __cil_tmp18, __cil_tmp19);
   }
 #line 1273
   return (tmp___0);
 }
 }
 #line 1277 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static ssize_t i915_wedged_write(struct file *filp , char const   *ubuf , size_t cnt ,
                                  loff_t *ppos ) 
 { struct drm_device *dev ;
   char buf[20U] ;
   int val ;
   unsigned long tmp ;
   unsigned long tmp___0 ;
   void *__cil_tmp10 ;
   void *__cil_tmp11 ;
   void const   *__cil_tmp12 ;
   char const   *__cil_tmp13 ;
   char **__cil_tmp14 ;
   int __cil_tmp15 ;
   bool __cil_tmp16 ;
 
   {
 #line 1282
   __cil_tmp10 = filp->private_data;
 #line 1282
   dev = (struct drm_device *)__cil_tmp10;
 #line 1284
   val = 1;
 #line 1286
   if (cnt != 0UL) {
 #line 1287
     if (cnt > 19UL) {
 #line 1288
       return (-22L);
     } else {
 
     }
     {
 #line 1290
     __cil_tmp11 = (void *)(& buf);
 #line 1290
     __cil_tmp12 = (void const   *)ubuf;
 #line 1290
     tmp = copy_from_user(__cil_tmp11, __cil_tmp12, cnt);
     }
 #line 1290
     if (tmp != 0UL) {
 #line 1291
       return (-14L);
     } else {
 
     }
     {
 #line 1292
     buf[cnt] = (char)0;
 #line 1294
     __cil_tmp13 = (char const   *)(& buf);
 #line 1294
     __cil_tmp14 = (char **)0;
 #line 1294
     tmp___0 = simple_strtoul(__cil_tmp13, __cil_tmp14, 0U);
 #line 1294
     val = (int )tmp___0;
     }
   } else {
 
   }
   {
 #line 1297
   printk("<6>[drm] Manually setting wedged to %d\n", val);
 #line 1298
   __cil_tmp15 = val != 0;
 #line 1298
   __cil_tmp16 = (bool )__cil_tmp15;
 #line 1298
   i915_handle_error(dev, __cil_tmp16);
   }
 #line 1300
   return ((ssize_t )cnt);
 }
 }
 #line 1303 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static struct file_operations  const  i915_wedged_fops  = 
 #line 1303
      {& __this_module, & default_llseek, & i915_wedged_read, & i915_wedged_write, (ssize_t (*)(struct kiocb * ,
                                                                                              struct iovec  const  * ,
                                                                                              unsigned long  ,
                                                                                              loff_t  ))0,
     (ssize_t (*)(struct kiocb * , struct iovec  const  * , unsigned long  , loff_t  ))0,
     (int (*)(struct file * , void * , int (*)(void * , char const   * , int  , loff_t  ,
                                               u64  , unsigned int  ) ))0, (unsigned int (*)(struct file * ,
                                                                                             struct poll_table_struct * ))0,
     (long (*)(struct file * , unsigned int  , unsigned long  ))0, (long (*)(struct file * ,
                                                                             unsigned int  ,
                                                                             unsigned long  ))0,
     (int (*)(struct file * , struct vm_area_struct * ))0, & i915_wedged_open, (int (*)(struct file * ,
                                                                                        fl_owner_t  ))0,
     (int (*)(struct inode * , struct file * ))0, (int (*)(struct file * , int  ))0,
     (int (*)(struct kiocb * , int  ))0, (int (*)(int  , struct file * , int  ))0,
     (int (*)(struct file * , int  , struct file_lock * ))0, (ssize_t (*)(struct file * ,
                                                                          struct page * ,
                                                                          int  , size_t  ,
                                                                          loff_t * ,
                                                                          int  ))0,
     (unsigned long (*)(struct file * , unsigned long  , unsigned long  , unsigned long  ,
                        unsigned long  ))0, (int (*)(int  ))0, (int (*)(struct file * ,
                                                                        int  , struct file_lock * ))0,
     (ssize_t (*)(struct pipe_inode_info * , struct file * , loff_t * , size_t  , unsigned int  ))0,
     (ssize_t (*)(struct file * , loff_t * , struct pipe_inode_info * , size_t  , unsigned int  ))0,
     (int (*)(struct file * , long  , struct file_lock ** ))0, (long (*)(struct file * ,
                                                                         int  , loff_t  ,
                                                                         loff_t  ))0};
 #line 1314 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int drm_add_fake_info_node(struct drm_minor *minor , struct dentry *ent , void const   *key ) 
 { struct drm_info_node *node ;
   void *tmp ;
   struct drm_info_node *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct list_head *__cil_tmp9 ;
   struct list_head *__cil_tmp10 ;
 
   {
   {
 #line 1320
   tmp = kmalloc(40UL, 208U);
 #line 1320
   node = (struct drm_info_node *)tmp;
   }
   {
 #line 1321
   __cil_tmp6 = (struct drm_info_node *)0;
 #line 1321
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 1321
   __cil_tmp8 = (unsigned long )node;
 #line 1321
   if (__cil_tmp8 == __cil_tmp7) {
     {
 #line 1322
     debugfs_remove(ent);
     }
 #line 1323
     return (-12);
   } else {
 
   }
   }
   {
 #line 1326
   node->minor = minor;
 #line 1327
   node->dent = ent;
 #line 1328
   node->info_ent = (struct drm_info_list *)key;
 #line 1329
   __cil_tmp9 = & node->list;
 #line 1329
   __cil_tmp10 = & minor->debugfs_nodes.list;
 #line 1329
   list_add(__cil_tmp9, __cil_tmp10);
   }
 #line 1331
   return (0);
 }
 }
 #line 1334 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_wedged_create(struct dentry *root , struct drm_minor *minor ) 
 { struct drm_device *dev ;
   struct dentry *ent ;
   long tmp ;
   long tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp8 ;
   void const   *__cil_tmp9 ;
   void const   *__cil_tmp10 ;
   void const   *__cil_tmp11 ;
 
   {
   {
 #line 1336
   dev = minor->dev;
 #line 1339
   __cil_tmp8 = (void *)dev;
 #line 1339
   ent = debugfs_create_file("i915_wedged", 420U, root, __cil_tmp8, & i915_wedged_fops);
 #line 1343
   __cil_tmp9 = (void const   *)ent;
 #line 1343
   tmp___0 = IS_ERR(__cil_tmp9);
   }
 #line 1343
   if (tmp___0 != 0L) {
     {
 #line 1344
     __cil_tmp10 = (void const   *)ent;
 #line 1344
     tmp = PTR_ERR(__cil_tmp10);
     }
 #line 1344
     return ((int )tmp);
   } else {
 
   }
   {
 #line 1346
   __cil_tmp11 = (void const   *)(& i915_wedged_fops);
 #line 1346
   tmp___1 = drm_add_fake_info_node(minor, ent, __cil_tmp11);
   }
 #line 1346
   return (tmp___1);
 }
 }
 #line 1349 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_forcewake_open(struct inode *inode , struct file *file ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   int ret ;
   void *__cil_tmp6 ;
   void *__cil_tmp7 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   u8 __cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   struct mutex *__cil_tmp14 ;
   struct mutex *__cil_tmp15 ;
 
   {
 #line 1351
   __cil_tmp6 = inode->i_private;
 #line 1351
   dev = (struct drm_device *)__cil_tmp6;
 #line 1352
   __cil_tmp7 = dev->dev_private;
 #line 1352
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
   {
 #line 1355
   __cil_tmp8 = dev->dev_private;
 #line 1355
   __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 1355
   __cil_tmp10 = __cil_tmp9->info;
 #line 1355
   __cil_tmp11 = __cil_tmp10->gen;
 #line 1355
   __cil_tmp12 = (unsigned char )__cil_tmp11;
 #line 1355
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 1355
   if (__cil_tmp13 != 6U) {
 #line 1356
     return (0);
   } else {
 
   }
   }
   {
 #line 1358
   __cil_tmp14 = & dev->struct_mutex;
 #line 1358
   ret = mutex_lock_interruptible_nested(__cil_tmp14, 0U);
   }
 #line 1359
   if (ret != 0) {
 #line 1360
     return (ret);
   } else {
 
   }
   {
 #line 1361
   gen6_gt_force_wake_get(dev_priv);
 #line 1362
   __cil_tmp15 = & dev->struct_mutex;
 #line 1362
   mutex_unlock(__cil_tmp15);
   }
 #line 1364
   return (0);
 }
 }
 #line 1367 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 int i915_forcewake_release(struct inode *inode , struct file *file ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   void *__cil_tmp5 ;
   void *__cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   u8 __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   struct mutex *__cil_tmp13 ;
   struct mutex *__cil_tmp14 ;
 
   {
 #line 1369
   __cil_tmp5 = inode->i_private;
 #line 1369
   dev = (struct drm_device *)__cil_tmp5;
 #line 1370
   __cil_tmp6 = dev->dev_private;
 #line 1370
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
   {
 #line 1372
   __cil_tmp7 = dev->dev_private;
 #line 1372
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 1372
   __cil_tmp9 = __cil_tmp8->info;
 #line 1372
   __cil_tmp10 = __cil_tmp9->gen;
 #line 1372
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 1372
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 1372
   if (__cil_tmp12 != 6U) {
 #line 1373
     return (0);
   } else {
 
   }
   }
   {
 #line 1382
   __cil_tmp13 = & dev->struct_mutex;
 #line 1382
   mutex_lock_nested(__cil_tmp13, 0U);
 #line 1383
   gen6_gt_force_wake_put(dev_priv);
 #line 1384
   __cil_tmp14 = & dev->struct_mutex;
 #line 1384
   mutex_unlock(__cil_tmp14);
   }
 #line 1386
   return (0);
 }
 }
 #line 1389 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static struct file_operations  const  i915_forcewake_fops  = 
 #line 1389
      {& __this_module, (loff_t (*)(struct file * , loff_t  , int  ))0, (ssize_t (*)(struct file * ,
                                                                                   char * ,
                                                                                   size_t  ,
                                                                                   loff_t * ))0,
     (ssize_t (*)(struct file * , char const   * , size_t  , loff_t * ))0, (ssize_t (*)(struct kiocb * ,
                                                                                        struct iovec  const  * ,
                                                                                        unsigned long  ,
                                                                                        loff_t  ))0,
     (ssize_t (*)(struct kiocb * , struct iovec  const  * , unsigned long  , loff_t  ))0,
     (int (*)(struct file * , void * , int (*)(void * , char const   * , int  , loff_t  ,
                                               u64  , unsigned int  ) ))0, (unsigned int (*)(struct file * ,
                                                                                             struct poll_table_struct * ))0,
     (long (*)(struct file * , unsigned int  , unsigned long  ))0, (long (*)(struct file * ,
                                                                             unsigned int  ,
                                                                             unsigned long  ))0,
     (int (*)(struct file * , struct vm_area_struct * ))0, & i915_forcewake_open, (int (*)(struct file * ,
                                                                                           fl_owner_t  ))0,
     & i915_forcewake_release, (int (*)(struct file * , int  ))0, (int (*)(struct kiocb * ,
                                                                           int  ))0,
     (int (*)(int  , struct file * , int  ))0, (int (*)(struct file * , int  , struct file_lock * ))0,
     (ssize_t (*)(struct file * , struct page * , int  , size_t  , loff_t * , int  ))0,
     (unsigned long (*)(struct file * , unsigned long  , unsigned long  , unsigned long  ,
                        unsigned long  ))0, (int (*)(int  ))0, (int (*)(struct file * ,
                                                                        int  , struct file_lock * ))0,
     (ssize_t (*)(struct pipe_inode_info * , struct file * , loff_t * , size_t  , unsigned int  ))0,
     (ssize_t (*)(struct file * , loff_t * , struct pipe_inode_info * , size_t  , unsigned int  ))0,
     (int (*)(struct file * , long  , struct file_lock ** ))0, (long (*)(struct file * ,
                                                                         int  , loff_t  ,
                                                                         loff_t  ))0};
 #line 1395 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static int i915_forcewake_create(struct dentry *root , struct drm_minor *minor ) 
 { struct drm_device *dev ;
   struct dentry *ent ;
   long tmp ;
   long tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp8 ;
   void const   *__cil_tmp9 ;
   void const   *__cil_tmp10 ;
   void const   *__cil_tmp11 ;
 
   {
   {
 #line 1397
   dev = minor->dev;
 #line 1400
   __cil_tmp8 = (void *)dev;
 #line 1400
   ent = debugfs_create_file("i915_forcewake_user", 256U, root, __cil_tmp8, & i915_forcewake_fops);
 #line 1404
   __cil_tmp9 = (void const   *)ent;
 #line 1404
   tmp___0 = IS_ERR(__cil_tmp9);
   }
 #line 1404
   if (tmp___0 != 0L) {
     {
 #line 1405
     __cil_tmp10 = (void const   *)ent;
 #line 1405
     tmp = PTR_ERR(__cil_tmp10);
     }
 #line 1405
     return ((int )tmp);
   } else {
 
   }
   {
 #line 1407
   __cil_tmp11 = (void const   *)(& i915_forcewake_fops);
 #line 1407
   tmp___1 = drm_add_fake_info_node(minor, ent, __cil_tmp11);
   }
 #line 1407
   return (tmp___1);
 }
 }
 #line 1410 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 static struct drm_info_list i915_debugfs_list[37U]  = 
 #line 1410
   {      {"i915_capabilities", & i915_capabilities, 0U, (void *)0}, 
         {"i915_gem_objects", & i915_gem_object_info, 0U, (void *)0}, 
         {"i915_gem_gtt", & i915_gem_gtt_info, 0U, (void *)0}, 
         {"i915_gem_active", & i915_gem_object_list_info, 0U, (void *)0}, 
         {"i915_gem_flushing", & i915_gem_object_list_info, 0U, (void *)1}, 
         {"i915_gem_inactive", & i915_gem_object_list_info, 0U, (void *)2}, 
         {"i915_gem_pinned", & i915_gem_object_list_info, 0U, (void *)3}, 
         {"i915_gem_deferred_free", & i915_gem_object_list_info, 0U, (void *)4}, 
         {"i915_gem_pageflip", & i915_gem_pageflip_info, 0U, (void *)0}, 
         {"i915_gem_request", & i915_gem_request_info, 0U, (void *)0}, 
         {"i915_gem_seqno", & i915_gem_seqno_info, 0U, (void *)0}, 
         {"i915_gem_fence_regs", & i915_gem_fence_regs_info, 0U, (void *)0}, 
         {"i915_gem_interrupt", & i915_interrupt_info, 0U, (void *)0}, 
         {"i915_gem_hws", & i915_hws_info, 0U, (void *)0}, 
         {"i915_gem_hws_blt", & i915_hws_info, 0U, (void *)2}, 
         {"i915_gem_hws_bsd", & i915_hws_info, 0U, (void *)1}, 
         {"i915_ringbuffer_data", & i915_ringbuffer_data, 0U, (void *)0}, 
         {"i915_ringbuffer_info", & i915_ringbuffer_info, 0U, (void *)0}, 
         {"i915_bsd_ringbuffer_data", & i915_ringbuffer_data, 0U, (void *)1}, 
         {"i915_bsd_ringbuffer_info", & i915_ringbuffer_info, 0U, (void *)1}, 
         {"i915_blt_ringbuffer_data", & i915_ringbuffer_data, 0U, (void *)2}, 
         {"i915_blt_ringbuffer_info", & i915_ringbuffer_info, 0U, (void *)2}, 
         {"i915_batchbuffers", & i915_batchbuffer_info, 0U, (void *)0}, 
         {"i915_error_state", & i915_error_state, 0U, (void *)0}, 
         {"i915_rstdby_delays", & i915_rstdby_delays, 0U, (void *)0}, 
         {"i915_cur_delayinfo", & i915_cur_delayinfo, 0U, (void *)0}, 
         {"i915_delayfreq_table", & i915_delayfreq_table, 0U, (void *)0}, 
         {"i915_inttoext_table", & i915_inttoext_table, 0U, (void *)0}, 
         {"i915_drpc_info", & i915_drpc_info, 0U, (void *)0}, 
         {"i915_emon_status", & i915_emon_status, 0U, (void *)0}, 
         {"i915_gfxec", & i915_gfxec, 0U, (void *)0}, 
         {"i915_fbc_status", & i915_fbc_status, 0U, (void *)0}, 
         {"i915_sr_status", & i915_sr_status, 0U, (void *)0}, 
         {"i915_opregion", & i915_opregion, 0U, (void *)0}, 
         {"i915_gem_framebuffer", & i915_gem_framebuffer_info, 0U, (void *)0}, 
         {"i915_context_status", & i915_context_status, 0U, (void *)0}, 
         {"i915_gen6_forcewake_count", & i915_gen6_forcewake_count_info, 0U, (void *)0}};
 #line 1451 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 int i915_debugfs_init(struct drm_minor *minor ) 
 { int ret ;
   int tmp ;
   struct dentry *__cil_tmp4 ;
   struct dentry *__cil_tmp5 ;
   struct drm_info_list *__cil_tmp6 ;
   struct dentry *__cil_tmp7 ;
 
   {
   {
 #line 1455
   __cil_tmp4 = minor->debugfs_root;
 #line 1455
   ret = i915_wedged_create(__cil_tmp4, minor);
   }
 #line 1456
   if (ret != 0) {
 #line 1457
     return (ret);
   } else {
 
   }
   {
 #line 1459
   __cil_tmp5 = minor->debugfs_root;
 #line 1459
   ret = i915_forcewake_create(__cil_tmp5, minor);
   }
 #line 1460
   if (ret != 0) {
 #line 1461
     return (ret);
   } else {
 
   }
   {
 #line 1463
   __cil_tmp6 = (struct drm_info_list *)(& i915_debugfs_list);
 #line 1463
   __cil_tmp7 = minor->debugfs_root;
 #line 1463
   tmp = drm_debugfs_create_files(__cil_tmp6, 37, __cil_tmp7, minor);
   }
 #line 1463
   return (tmp);
 }
 }
 #line 1468 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_debugfs.c.p"
 void i915_debugfs_cleanup(struct drm_minor *minor ) 
 { struct drm_info_list *__cil_tmp2 ;
   struct drm_info_list *__cil_tmp3 ;
   struct drm_info_list *__cil_tmp4 ;
 
   {
   {
 #line 1470
   __cil_tmp2 = (struct drm_info_list *)(& i915_debugfs_list);
 #line 1470
   drm_debugfs_remove_files(__cil_tmp2, 37, minor);
 #line 1472
   __cil_tmp3 = (struct drm_info_list *)(& i915_forcewake_fops);
 #line 1472
   drm_debugfs_remove_files(__cil_tmp3, 1, minor);
 #line 1474
   __cil_tmp4 = (struct drm_info_list *)(& i915_wedged_fops);
 #line 1474
   drm_debugfs_remove_files(__cil_tmp4, 1, minor);
   }
 #line 1475
   return;
 }
 }
 #line 63 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void writeb(unsigned char val , void volatile   *addr ) 
 { unsigned char volatile   *__cil_tmp3 ;
 
   {
 #line 63
   __cil_tmp3 = (unsigned char volatile   *)addr;
 #line 63
   __asm__  volatile   ("movb %0,%1": : "q" (val), "m" (*__cil_tmp3): "memory");
 #line 64
   return;
 }
 }
 #line 87 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void writeq(unsigned long val , void volatile   *addr ) 
 { unsigned long volatile   *__cil_tmp3 ;
 
   {
 #line 87
   __cil_tmp3 = (unsigned long volatile   *)addr;
 #line 87
   __asm__  volatile   ("movq %0,%1": : "r" (val), "m" (*__cil_tmp3): "memory");
 #line 88
   return;
 }
 }
 #line 1254 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 void intel_i2c_reset(struct drm_device *dev ) ;
 #line 1286
 void i8xx_disable_fbc(struct drm_device *dev ) ;
 #line 1287
 void g4x_disable_fbc(struct drm_device *dev ) ;
 #line 1288
 void ironlake_disable_fbc(struct drm_device *dev ) ;
 #line 1359 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u8 i915_read8___0(struct drm_i915_private *dev_priv , u32 reg ) 
 { u8 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1359
   val = (u8 )0U;
   {
 #line 1359
   __cil_tmp4 = dev_priv->info;
 #line 1359
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1359
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1359
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1359
   if (__cil_tmp7 > 5U) {
 #line 1359
     if (reg <= 262143U) {
 #line 1359
       if (reg != 41356U) {
         {
 #line 1359
         gen6_gt_force_wake_get(dev_priv);
 #line 1359
         __cil_tmp8 = (unsigned long )reg;
 #line 1359
         __cil_tmp9 = dev_priv->regs;
 #line 1359
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1359
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1359
         val = readb(__cil_tmp11);
 #line 1359
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1359
         __cil_tmp12 = (unsigned long )reg;
 #line 1359
         __cil_tmp13 = dev_priv->regs;
 #line 1359
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1359
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1359
         val = readb(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1359
       __cil_tmp16 = (unsigned long )reg;
 #line 1359
       __cil_tmp17 = dev_priv->regs;
 #line 1359
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1359
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1359
       val = readb(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1359
     __cil_tmp20 = (unsigned long )reg;
 #line 1359
     __cil_tmp21 = dev_priv->regs;
 #line 1359
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1359
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1359
     val = readb(__cil_tmp23);
     }
   }
   }
   {
 #line 1359
   __cil_tmp24 = (bool )0;
 #line 1359
   __cil_tmp25 = (u64 )val;
 #line 1359
   trace_i915_reg_rw(__cil_tmp24, reg, __cil_tmp25, 1);
   }
 #line 1359
   return (val);
 }
 }
 #line 1373 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static void i915_write8(struct drm_i915_private *dev_priv , u32 reg , u8 val ) 
 { bool __cil_tmp4 ;
   u64 __cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void volatile   *__cil_tmp14 ;
   void volatile   *__cil_tmp15 ;
 
   {
   {
 #line 1373
   __cil_tmp4 = (bool )1;
 #line 1373
   __cil_tmp5 = (u64 )val;
 #line 1373
   trace_i915_reg_rw(__cil_tmp4, reg, __cil_tmp5, 1);
   }
   {
 #line 1373
   __cil_tmp6 = dev_priv->info;
 #line 1373
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1373
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1373
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1373
   if (__cil_tmp9 > 5U) {
 #line 1373
     if (reg <= 262143U) {
 #line 1373
       if (reg != 41356U) {
         {
 #line 1373
         __gen6_gt_wait_for_fifo(dev_priv);
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1373
   __cil_tmp10 = (int )val;
 #line 1373
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 1373
   __cil_tmp12 = (unsigned long )reg;
 #line 1373
   __cil_tmp13 = dev_priv->regs;
 #line 1373
   __cil_tmp14 = (void volatile   *)__cil_tmp13;
 #line 1373
   __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1373
   writeb(__cil_tmp11, __cil_tmp15);
   }
 #line 1374
   return;
 }
 }
 #line 1376 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static void i915_write64(struct drm_i915_private *dev_priv , u32 reg , u64 val ) 
 { bool __cil_tmp4 ;
   struct intel_device_info  const  *__cil_tmp5 ;
   u8 __cil_tmp6 ;
   unsigned char __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   void *__cil_tmp11 ;
   void volatile   *__cil_tmp12 ;
   void volatile   *__cil_tmp13 ;
 
   {
   {
 #line 1376
   __cil_tmp4 = (bool )1;
 #line 1376
   trace_i915_reg_rw(__cil_tmp4, reg, val, 8);
   }
   {
 #line 1376
   __cil_tmp5 = dev_priv->info;
 #line 1376
   __cil_tmp6 = __cil_tmp5->gen;
 #line 1376
   __cil_tmp7 = (unsigned char )__cil_tmp6;
 #line 1376
   __cil_tmp8 = (unsigned int )__cil_tmp7;
 #line 1376
   if (__cil_tmp8 > 5U) {
 #line 1376
     if (reg <= 262143U) {
 #line 1376
       if (reg != 41356U) {
         {
 #line 1376
         __gen6_gt_wait_for_fifo(dev_priv);
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1376
   __cil_tmp9 = (unsigned long )val;
 #line 1376
   __cil_tmp10 = (unsigned long )reg;
 #line 1376
   __cil_tmp11 = dev_priv->regs;
 #line 1376
   __cil_tmp12 = (void volatile   *)__cil_tmp11;
 #line 1376
   __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
 #line 1376
   writeq(__cil_tmp9, __cil_tmp13);
   }
 #line 1377
   return;
 }
 }
 #line 317 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 void ironlake_enable_drps(struct drm_device *dev ) ;
 #line 318
 void ironlake_disable_drps(struct drm_device *dev ) ;
 #line 319
 void gen6_enable_rps(struct drm_i915_private *dev_priv ) ;
 #line 320
 void gen6_disable_rps(struct drm_device *dev ) ;
 #line 321
 void intel_init_emon(struct drm_device *dev ) ;
 #line 349
 void intel_init_clock_gating(struct drm_device *dev ) ;
 #line 39 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static bool i915_pipe_enabled___0(struct drm_device *dev , enum pipe pipe ) 
 { struct drm_i915_private *dev_priv ;
   u32 dpll_reg ;
   u32 tmp ;
   void *__cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   u8 __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   void *__cil_tmp13 ;
   struct drm_i915_private *__cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   u8 __cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   void *__cil_tmp19 ;
   struct drm_i915_private *__cil_tmp20 ;
   struct intel_device_info  const  *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
 
   {
 #line 41
   __cil_tmp6 = dev->dev_private;
 #line 41
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
   {
 #line 44
   __cil_tmp7 = dev->dev_private;
 #line 44
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 44
   __cil_tmp9 = __cil_tmp8->info;
 #line 44
   __cil_tmp10 = __cil_tmp9->gen;
 #line 44
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 44
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 44
   if (__cil_tmp12 == 5U) {
 #line 44
     goto _L;
   } else {
     {
 #line 44
     __cil_tmp13 = dev->dev_private;
 #line 44
     __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
 #line 44
     __cil_tmp15 = __cil_tmp14->info;
 #line 44
     __cil_tmp16 = __cil_tmp15->gen;
 #line 44
     __cil_tmp17 = (unsigned char )__cil_tmp16;
 #line 44
     __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 44
     if (__cil_tmp18 == 6U) {
 #line 44
       goto _L;
     } else {
       {
 #line 44
       __cil_tmp19 = dev->dev_private;
 #line 44
       __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
 #line 44
       __cil_tmp21 = __cil_tmp20->info;
 #line 44
       __cil_tmp22 = (unsigned char *)__cil_tmp21;
 #line 44
       __cil_tmp23 = __cil_tmp22 + 2UL;
 #line 44
       __cil_tmp24 = *__cil_tmp23;
 #line 44
       __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 44
       if (__cil_tmp25 != 0U) {
         _L: 
         {
 #line 45
         __cil_tmp26 = (unsigned int )pipe;
 #line 45
         if (__cil_tmp26 == 0U) {
 #line 45
           dpll_reg = 811028U;
         } else {
 #line 45
           dpll_reg = 811032U;
         }
         }
       } else {
         {
 #line 47
         __cil_tmp27 = (unsigned int )pipe;
 #line 47
         if (__cil_tmp27 == 0U) {
 #line 47
           dpll_reg = 24596U;
         } else {
 #line 47
           dpll_reg = 24600U;
         }
         }
       }
       }
     }
     }
   }
   }
   {
 #line 49
   tmp = i915_read32(dev_priv, dpll_reg);
   }
   {
 #line 49
   __cil_tmp28 = tmp & 2147483648U;
 #line 49
   __cil_tmp29 = __cil_tmp28 != 0U;
 #line 49
   return ((bool )__cil_tmp29);
   }
 }
 }
 #line 52 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_save_palette(struct drm_device *dev , enum pipe pipe ) 
 { struct drm_i915_private *dev_priv ;
   unsigned long reg ;
   unsigned long tmp ;
   u32 *array ;
   int i ;
   bool tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   u8 __cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_device_info  const  *__cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   u32 (*__cil_tmp33)[256U] ;
   u32 (*__cil_tmp34)[256U] ;
   unsigned long __cil_tmp35 ;
   u32 *__cil_tmp36 ;
   u32 __cil_tmp37 ;
   int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   u32 __cil_tmp40 ;
 
   {
 #line 54
   __cil_tmp10 = dev->dev_private;
 #line 54
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
   {
 #line 55
   __cil_tmp11 = (unsigned int )pipe;
 #line 55
   if (__cil_tmp11 == 0U) {
 #line 55
     tmp = 40960UL;
   } else {
 #line 55
     tmp = 43008UL;
   }
   }
   {
 #line 55
   reg = tmp;
 #line 59
   tmp___0 = i915_pipe_enabled___0(dev, pipe);
   }
 #line 59
   if (tmp___0) {
 #line 59
     tmp___1 = 0;
   } else {
 #line 59
     tmp___1 = 1;
   }
 #line 59
   if (tmp___1) {
 #line 60
     return;
   } else {
 
   }
   {
 #line 62
   __cil_tmp12 = dev->dev_private;
 #line 62
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 62
   __cil_tmp14 = __cil_tmp13->info;
 #line 62
   __cil_tmp15 = __cil_tmp14->gen;
 #line 62
   __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 62
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 62
   if (__cil_tmp17 == 5U) {
 #line 62
     goto _L;
   } else {
     {
 #line 62
     __cil_tmp18 = dev->dev_private;
 #line 62
     __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 62
     __cil_tmp20 = __cil_tmp19->info;
 #line 62
     __cil_tmp21 = __cil_tmp20->gen;
 #line 62
     __cil_tmp22 = (unsigned char )__cil_tmp21;
 #line 62
     __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 62
     if (__cil_tmp23 == 6U) {
 #line 62
       goto _L;
     } else {
       {
 #line 62
       __cil_tmp24 = dev->dev_private;
 #line 62
       __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 62
       __cil_tmp26 = __cil_tmp25->info;
 #line 62
       __cil_tmp27 = (unsigned char *)__cil_tmp26;
 #line 62
       __cil_tmp28 = __cil_tmp27 + 2UL;
 #line 62
       __cil_tmp29 = *__cil_tmp28;
 #line 62
       __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 62
       if (__cil_tmp30 != 0U) {
         _L: 
         {
 #line 63
         __cil_tmp31 = (unsigned int )pipe;
 #line 63
         if (__cil_tmp31 == 0U) {
 #line 63
           reg = 303104UL;
         } else {
 #line 63
           reg = 305152UL;
         }
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 65
   __cil_tmp32 = (unsigned int )pipe;
 #line 65
   if (__cil_tmp32 == 0U) {
 #line 66
     __cil_tmp33 = & dev_priv->save_palette_a;
 #line 66
     array = (u32 *)__cil_tmp33;
   } else {
 #line 68
     __cil_tmp34 = & dev_priv->save_palette_b;
 #line 68
     array = (u32 *)__cil_tmp34;
   }
   }
 #line 70
   i = 0;
 #line 70
   goto ldv_37563;
   ldv_37562: 
   {
 #line 71
   __cil_tmp35 = (unsigned long )i;
 #line 71
   __cil_tmp36 = array + __cil_tmp35;
 #line 71
   __cil_tmp37 = (u32 )reg;
 #line 71
   __cil_tmp38 = i << 2;
 #line 71
   __cil_tmp39 = (u32 )__cil_tmp38;
 #line 71
   __cil_tmp40 = __cil_tmp39 + __cil_tmp37;
 #line 71
   *__cil_tmp36 = i915_read32(dev_priv, __cil_tmp40);
 #line 70
   i = i + 1;
   }
   ldv_37563: ;
 #line 70
   if (i <= 255) {
 #line 71
     goto ldv_37562;
   } else {
 #line 73
     goto ldv_37564;
   }
   ldv_37564: ;
 #line 75
   return;
 }
 }
 #line 74 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_restore_palette(struct drm_device *dev , enum pipe pipe ) 
 { struct drm_i915_private *dev_priv ;
   unsigned long reg ;
   unsigned long tmp ;
   u32 *array ;
   int i ;
   bool tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   u8 __cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_device_info  const  *__cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   u32 (*__cil_tmp33)[256U] ;
   u32 (*__cil_tmp34)[256U] ;
   u32 __cil_tmp35 ;
   int __cil_tmp36 ;
   u32 __cil_tmp37 ;
   u32 __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   u32 *__cil_tmp40 ;
   u32 __cil_tmp41 ;
 
   {
 #line 76
   __cil_tmp10 = dev->dev_private;
 #line 76
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
   {
 #line 77
   __cil_tmp11 = (unsigned int )pipe;
 #line 77
   if (__cil_tmp11 == 0U) {
 #line 77
     tmp = 40960UL;
   } else {
 #line 77
     tmp = 43008UL;
   }
   }
   {
 #line 77
   reg = tmp;
 #line 81
   tmp___0 = i915_pipe_enabled___0(dev, pipe);
   }
 #line 81
   if (tmp___0) {
 #line 81
     tmp___1 = 0;
   } else {
 #line 81
     tmp___1 = 1;
   }
 #line 81
   if (tmp___1) {
 #line 82
     return;
   } else {
 
   }
   {
 #line 84
   __cil_tmp12 = dev->dev_private;
 #line 84
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 84
   __cil_tmp14 = __cil_tmp13->info;
 #line 84
   __cil_tmp15 = __cil_tmp14->gen;
 #line 84
   __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 84
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 84
   if (__cil_tmp17 == 5U) {
 #line 84
     goto _L;
   } else {
     {
 #line 84
     __cil_tmp18 = dev->dev_private;
 #line 84
     __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 84
     __cil_tmp20 = __cil_tmp19->info;
 #line 84
     __cil_tmp21 = __cil_tmp20->gen;
 #line 84
     __cil_tmp22 = (unsigned char )__cil_tmp21;
 #line 84
     __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 84
     if (__cil_tmp23 == 6U) {
 #line 84
       goto _L;
     } else {
       {
 #line 84
       __cil_tmp24 = dev->dev_private;
 #line 84
       __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 84
       __cil_tmp26 = __cil_tmp25->info;
 #line 84
       __cil_tmp27 = (unsigned char *)__cil_tmp26;
 #line 84
       __cil_tmp28 = __cil_tmp27 + 2UL;
 #line 84
       __cil_tmp29 = *__cil_tmp28;
 #line 84
       __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 84
       if (__cil_tmp30 != 0U) {
         _L: 
         {
 #line 85
         __cil_tmp31 = (unsigned int )pipe;
 #line 85
         if (__cil_tmp31 == 0U) {
 #line 85
           reg = 303104UL;
         } else {
 #line 85
           reg = 305152UL;
         }
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 87
   __cil_tmp32 = (unsigned int )pipe;
 #line 87
   if (__cil_tmp32 == 0U) {
 #line 88
     __cil_tmp33 = & dev_priv->save_palette_a;
 #line 88
     array = (u32 *)__cil_tmp33;
   } else {
 #line 90
     __cil_tmp34 = & dev_priv->save_palette_b;
 #line 90
     array = (u32 *)__cil_tmp34;
   }
   }
 #line 92
   i = 0;
 #line 92
   goto ldv_37574;
   ldv_37573: 
   {
 #line 93
   __cil_tmp35 = (u32 )reg;
 #line 93
   __cil_tmp36 = i << 2;
 #line 93
   __cil_tmp37 = (u32 )__cil_tmp36;
 #line 93
   __cil_tmp38 = __cil_tmp37 + __cil_tmp35;
 #line 93
   __cil_tmp39 = (unsigned long )i;
 #line 93
   __cil_tmp40 = array + __cil_tmp39;
 #line 93
   __cil_tmp41 = *__cil_tmp40;
 #line 93
   i915_write32(dev_priv, __cil_tmp38, __cil_tmp41);
 #line 92
   i = i + 1;
   }
   ldv_37574: ;
 #line 92
   if (i <= 255) {
 #line 93
     goto ldv_37573;
   } else {
 #line 95
     goto ldv_37575;
   }
   ldv_37575: ;
 #line 97
   return;
 }
 }
 #line 96 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static u8 i915_read_indexed(struct drm_device *dev , u16 index_port , u16 data_port ,
                             u8 reg ) 
 { struct drm_i915_private *dev_priv ;
   u8 tmp ;
   void *__cil_tmp7 ;
   u32 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   u32 __cil_tmp11 ;
 
   {
   {
 #line 98
   __cil_tmp7 = dev->dev_private;
 #line 98
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 100
   __cil_tmp8 = (u32 )index_port;
 #line 100
   __cil_tmp9 = (int )reg;
 #line 100
   __cil_tmp10 = (u8 )__cil_tmp9;
 #line 100
   i915_write8(dev_priv, __cil_tmp8, __cil_tmp10);
 #line 101
   __cil_tmp11 = (u32 )data_port;
 #line 101
   tmp = i915_read8___0(dev_priv, __cil_tmp11);
   }
 #line 101
   return (tmp);
 }
 }
 #line 104 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static u8 i915_read_ar(struct drm_device *dev , u16 st01 , u8 reg , u16 palette_enable ) 
 { struct drm_i915_private *dev_priv ;
   u8 tmp ;
   void *__cil_tmp7 ;
   u32 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   u8 __cil_tmp13 ;
 
   {
   {
 #line 106
   __cil_tmp7 = dev->dev_private;
 #line 106
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 108
   __cil_tmp8 = (u32 )st01;
 #line 108
   i915_read8___0(dev_priv, __cil_tmp8);
 #line 109
   __cil_tmp9 = (int )reg;
 #line 109
   __cil_tmp10 = (u8 )palette_enable;
 #line 109
   __cil_tmp11 = (int )__cil_tmp10;
 #line 109
   __cil_tmp12 = __cil_tmp11 | __cil_tmp9;
 #line 109
   __cil_tmp13 = (u8 )__cil_tmp12;
 #line 109
   i915_write8(dev_priv, 960U, __cil_tmp13);
 #line 110
   tmp = i915_read8___0(dev_priv, 961U);
   }
 #line 110
   return (tmp);
 }
 }
 #line 113 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_write_ar(struct drm_device *dev , u16 st01 , u8 reg , u8 val , u16 palette_enable ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp7 ;
   u32 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   u8 __cil_tmp13 ;
   int __cil_tmp14 ;
   u8 __cil_tmp15 ;
 
   {
   {
 #line 115
   __cil_tmp7 = dev->dev_private;
 #line 115
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 117
   __cil_tmp8 = (u32 )st01;
 #line 117
   i915_read8___0(dev_priv, __cil_tmp8);
 #line 118
   __cil_tmp9 = (int )reg;
 #line 118
   __cil_tmp10 = (u8 )palette_enable;
 #line 118
   __cil_tmp11 = (int )__cil_tmp10;
 #line 118
   __cil_tmp12 = __cil_tmp11 | __cil_tmp9;
 #line 118
   __cil_tmp13 = (u8 )__cil_tmp12;
 #line 118
   i915_write8(dev_priv, 960U, __cil_tmp13);
 #line 119
   __cil_tmp14 = (int )val;
 #line 119
   __cil_tmp15 = (u8 )__cil_tmp14;
 #line 119
   i915_write8(dev_priv, 960U, __cil_tmp15);
   }
 #line 120
   return;
 }
 }
 #line 122 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_write_indexed(struct drm_device *dev , u16 index_port , u16 data_port ,
                                u8 reg , u8 val ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp7 ;
   u32 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   u32 __cil_tmp11 ;
   int __cil_tmp12 ;
   u8 __cil_tmp13 ;
 
   {
   {
 #line 124
   __cil_tmp7 = dev->dev_private;
 #line 124
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 126
   __cil_tmp8 = (u32 )index_port;
 #line 126
   __cil_tmp9 = (int )reg;
 #line 126
   __cil_tmp10 = (u8 )__cil_tmp9;
 #line 126
   i915_write8(dev_priv, __cil_tmp8, __cil_tmp10);
 #line 127
   __cil_tmp11 = (u32 )data_port;
 #line 127
   __cil_tmp12 = (int )val;
 #line 127
   __cil_tmp13 = (u8 )__cil_tmp12;
 #line 127
   i915_write8(dev_priv, __cil_tmp11, __cil_tmp13);
   }
 #line 128
   return;
 }
 }
 #line 130 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_save_vga(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   u16 cr_index ;
   u16 cr_data ;
   u16 st01 ;
   u8 tmp ;
   void *__cil_tmp8 ;
   u8 __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   u16 __cil_tmp12 ;
   int __cil_tmp13 ;
   u16 __cil_tmp14 ;
   u8 __cil_tmp15 ;
   int __cil_tmp16 ;
   u16 __cil_tmp17 ;
   int __cil_tmp18 ;
   u16 __cil_tmp19 ;
   u8 __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   u8 __cil_tmp23 ;
   int __cil_tmp24 ;
   u16 __cil_tmp25 ;
   int __cil_tmp26 ;
   u16 __cil_tmp27 ;
   u8 __cil_tmp28 ;
   int __cil_tmp29 ;
   u8 __cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   int __cil_tmp35 ;
   u16 __cil_tmp36 ;
   u8 __cil_tmp37 ;
   int __cil_tmp38 ;
   u8 __cil_tmp39 ;
   u16 __cil_tmp40 ;
   u32 __cil_tmp41 ;
   u8 __cil_tmp42 ;
   int __cil_tmp43 ;
   u8 __cil_tmp44 ;
   u32 __cil_tmp45 ;
   u16 __cil_tmp46 ;
   u16 __cil_tmp47 ;
   u8 __cil_tmp48 ;
   int __cil_tmp49 ;
   u8 __cil_tmp50 ;
   u16 __cil_tmp51 ;
   u16 __cil_tmp52 ;
   u8 __cil_tmp53 ;
   u16 __cil_tmp54 ;
   u16 __cil_tmp55 ;
   u8 __cil_tmp56 ;
   u16 __cil_tmp57 ;
   u16 __cil_tmp58 ;
   u8 __cil_tmp59 ;
   u16 __cil_tmp60 ;
   u16 __cil_tmp61 ;
   u8 __cil_tmp62 ;
   int __cil_tmp63 ;
   u8 __cil_tmp64 ;
 
   {
   {
 #line 132
   __cil_tmp8 = dev->dev_private;
 #line 132
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 137
   dev_priv->saveDACMASK = i915_read8___0(dev_priv, 966U);
 #line 140
   dev_priv->saveMSR = i915_read8___0(dev_priv, 972U);
   }
   {
 #line 141
   __cil_tmp9 = dev_priv->saveMSR;
 #line 141
   __cil_tmp10 = (int )__cil_tmp9;
 #line 141
   if (__cil_tmp10 & 1) {
 #line 142
     cr_index = (u16 )980U;
 #line 143
     cr_data = (u16 )981U;
 #line 144
     st01 = (u16 )986U;
   } else {
 #line 146
     cr_index = (u16 )948U;
 #line 147
     cr_data = (u16 )949U;
 #line 148
     st01 = (u16 )954U;
   }
   }
   {
 #line 152
   __cil_tmp11 = (int )cr_index;
 #line 152
   __cil_tmp12 = (u16 )__cil_tmp11;
 #line 152
   __cil_tmp13 = (int )cr_data;
 #line 152
   __cil_tmp14 = (u16 )__cil_tmp13;
 #line 152
   __cil_tmp15 = (u8 )17;
 #line 152
   tmp = i915_read_indexed(dev, __cil_tmp12, __cil_tmp14, __cil_tmp15);
 #line 152
   __cil_tmp16 = (int )cr_index;
 #line 152
   __cil_tmp17 = (u16 )__cil_tmp16;
 #line 152
   __cil_tmp18 = (int )cr_data;
 #line 152
   __cil_tmp19 = (u16 )__cil_tmp18;
 #line 152
   __cil_tmp20 = (u8 )17;
 #line 152
   __cil_tmp21 = (int )tmp;
 #line 152
   __cil_tmp22 = __cil_tmp21 & 127;
 #line 152
   __cil_tmp23 = (u8 )__cil_tmp22;
 #line 152
   i915_write_indexed(dev, __cil_tmp17, __cil_tmp19, __cil_tmp20, __cil_tmp23);
 #line 155
   i = 0;
   }
 #line 155
   goto ldv_37615;
   ldv_37614: 
   {
 #line 156
   __cil_tmp24 = (int )cr_index;
 #line 156
   __cil_tmp25 = (u16 )__cil_tmp24;
 #line 156
   __cil_tmp26 = (int )cr_data;
 #line 156
   __cil_tmp27 = (u16 )__cil_tmp26;
 #line 156
   __cil_tmp28 = (u8 )i;
 #line 156
   __cil_tmp29 = (int )__cil_tmp28;
 #line 156
   __cil_tmp30 = (u8 )__cil_tmp29;
 #line 156
   dev_priv->saveCR[i] = i915_read_indexed(dev, __cil_tmp25, __cil_tmp27, __cil_tmp30);
 #line 155
   i = i + 1;
   }
   ldv_37615: ;
 #line 155
   if (i <= 36) {
 #line 156
     goto ldv_37614;
   } else {
 #line 158
     goto ldv_37616;
   }
   ldv_37616: 
   {
 #line 159
   __cil_tmp31 = dev_priv->saveCR[17];
 #line 159
   __cil_tmp32 = (unsigned int )__cil_tmp31;
 #line 159
   __cil_tmp33 = __cil_tmp32 & 127U;
 #line 159
   dev_priv->saveCR[17] = (u8 )__cil_tmp33;
 #line 162
   __cil_tmp34 = (u32 )st01;
 #line 162
   i915_read8___0(dev_priv, __cil_tmp34);
 #line 163
   dev_priv->saveAR_INDEX = i915_read8___0(dev_priv, 960U);
 #line 164
   i = 0;
   }
 #line 164
   goto ldv_37618;
   ldv_37617: 
   {
 #line 165
   __cil_tmp35 = (int )st01;
 #line 165
   __cil_tmp36 = (u16 )__cil_tmp35;
 #line 165
   __cil_tmp37 = (u8 )i;
 #line 165
   __cil_tmp38 = (int )__cil_tmp37;
 #line 165
   __cil_tmp39 = (u8 )__cil_tmp38;
 #line 165
   __cil_tmp40 = (u16 )0;
 #line 165
   dev_priv->saveAR[i] = i915_read_ar(dev, __cil_tmp36, __cil_tmp39, __cil_tmp40);
 #line 164
   i = i + 1;
   }
   ldv_37618: ;
 #line 164
   if (i <= 20) {
 #line 165
     goto ldv_37617;
   } else {
 #line 167
     goto ldv_37619;
   }
   ldv_37619: 
   {
 #line 166
   __cil_tmp41 = (u32 )st01;
 #line 166
   i915_read8___0(dev_priv, __cil_tmp41);
 #line 167
   __cil_tmp42 = dev_priv->saveAR_INDEX;
 #line 167
   __cil_tmp43 = (int )__cil_tmp42;
 #line 167
   __cil_tmp44 = (u8 )__cil_tmp43;
 #line 167
   i915_write8(dev_priv, 960U, __cil_tmp44);
 #line 168
   __cil_tmp45 = (u32 )st01;
 #line 168
   i915_read8___0(dev_priv, __cil_tmp45);
 #line 171
   i = 0;
   }
 #line 171
   goto ldv_37621;
   ldv_37620: 
   {
 #line 172
   __cil_tmp46 = (u16 )974;
 #line 172
   __cil_tmp47 = (u16 )975;
 #line 172
   __cil_tmp48 = (u8 )i;
 #line 172
   __cil_tmp49 = (int )__cil_tmp48;
 #line 172
   __cil_tmp50 = (u8 )__cil_tmp49;
 #line 172
   dev_priv->saveGR[i] = i915_read_indexed(dev, __cil_tmp46, __cil_tmp47, __cil_tmp50);
 #line 171
   i = i + 1;
   }
   ldv_37621: ;
 #line 171
   if (i <= 8) {
 #line 172
     goto ldv_37620;
   } else {
 #line 174
     goto ldv_37622;
   }
   ldv_37622: 
   {
 #line 175
   __cil_tmp51 = (u16 )974;
 #line 175
   __cil_tmp52 = (u16 )975;
 #line 175
   __cil_tmp53 = (u8 )16;
 #line 175
   dev_priv->saveGR[16] = i915_read_indexed(dev, __cil_tmp51, __cil_tmp52, __cil_tmp53);
 #line 177
   __cil_tmp54 = (u16 )974;
 #line 177
   __cil_tmp55 = (u16 )975;
 #line 177
   __cil_tmp56 = (u8 )17;
 #line 177
   dev_priv->saveGR[17] = i915_read_indexed(dev, __cil_tmp54, __cil_tmp55, __cil_tmp56);
 #line 179
   __cil_tmp57 = (u16 )974;
 #line 179
   __cil_tmp58 = (u16 )975;
 #line 179
   __cil_tmp59 = (u8 )24;
 #line 179
   dev_priv->saveGR[24] = i915_read_indexed(dev, __cil_tmp57, __cil_tmp58, __cil_tmp59);
 #line 183
   i = 0;
   }
 #line 183
   goto ldv_37624;
   ldv_37623: 
   {
 #line 184
   __cil_tmp60 = (u16 )964;
 #line 184
   __cil_tmp61 = (u16 )965;
 #line 184
   __cil_tmp62 = (u8 )i;
 #line 184
   __cil_tmp63 = (int )__cil_tmp62;
 #line 184
   __cil_tmp64 = (u8 )__cil_tmp63;
 #line 184
   dev_priv->saveSR[i] = i915_read_indexed(dev, __cil_tmp60, __cil_tmp61, __cil_tmp64);
 #line 183
   i = i + 1;
   }
   ldv_37624: ;
 #line 183
   if (i <= 7) {
 #line 184
     goto ldv_37623;
   } else {
 #line 186
     goto ldv_37625;
   }
   ldv_37625: ;
 #line 188
   return;
 }
 }
 #line 188 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_restore_vga(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   u16 cr_index ;
   u16 cr_data ;
   u16 st01 ;
   void *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   int __cil_tmp9 ;
   u8 __cil_tmp10 ;
   u8 __cil_tmp11 ;
   int __cil_tmp12 ;
   u16 __cil_tmp13 ;
   u16 __cil_tmp14 ;
   u8 __cil_tmp15 ;
   int __cil_tmp16 ;
   u8 __cil_tmp17 ;
   u8 __cil_tmp18 ;
   int __cil_tmp19 ;
   u8 __cil_tmp20 ;
   int __cil_tmp21 ;
   u16 __cil_tmp22 ;
   int __cil_tmp23 ;
   u16 __cil_tmp24 ;
   u8 __cil_tmp25 ;
   u8 __cil_tmp26 ;
   int __cil_tmp27 ;
   u8 __cil_tmp28 ;
   int __cil_tmp29 ;
   u16 __cil_tmp30 ;
   int __cil_tmp31 ;
   u16 __cil_tmp32 ;
   u8 __cil_tmp33 ;
   int __cil_tmp34 ;
   u8 __cil_tmp35 ;
   u8 __cil_tmp36 ;
   int __cil_tmp37 ;
   u8 __cil_tmp38 ;
   u16 __cil_tmp39 ;
   u16 __cil_tmp40 ;
   u8 __cil_tmp41 ;
   int __cil_tmp42 ;
   u8 __cil_tmp43 ;
   u8 __cil_tmp44 ;
   int __cil_tmp45 ;
   u8 __cil_tmp46 ;
   u16 __cil_tmp47 ;
   u16 __cil_tmp48 ;
   u8 __cil_tmp49 ;
   u8 __cil_tmp50 ;
   int __cil_tmp51 ;
   u8 __cil_tmp52 ;
   u16 __cil_tmp53 ;
   u16 __cil_tmp54 ;
   u8 __cil_tmp55 ;
   u8 __cil_tmp56 ;
   int __cil_tmp57 ;
   u8 __cil_tmp58 ;
   u16 __cil_tmp59 ;
   u16 __cil_tmp60 ;
   u8 __cil_tmp61 ;
   u8 __cil_tmp62 ;
   int __cil_tmp63 ;
   u8 __cil_tmp64 ;
   u32 __cil_tmp65 ;
   int __cil_tmp66 ;
   u16 __cil_tmp67 ;
   u8 __cil_tmp68 ;
   int __cil_tmp69 ;
   u8 __cil_tmp70 ;
   u8 __cil_tmp71 ;
   int __cil_tmp72 ;
   u8 __cil_tmp73 ;
   u16 __cil_tmp74 ;
   u32 __cil_tmp75 ;
   u8 __cil_tmp76 ;
   unsigned int __cil_tmp77 ;
   unsigned int __cil_tmp78 ;
   int __cil_tmp79 ;
   u8 __cil_tmp80 ;
   u32 __cil_tmp81 ;
   u8 __cil_tmp82 ;
   int __cil_tmp83 ;
   u8 __cil_tmp84 ;
 
   {
   {
 #line 190
   __cil_tmp7 = dev->dev_private;
 #line 190
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 195
   __cil_tmp8 = dev_priv->saveMSR;
 #line 195
   __cil_tmp9 = (int )__cil_tmp8;
 #line 195
   __cil_tmp10 = (u8 )__cil_tmp9;
 #line 195
   i915_write8(dev_priv, 962U, __cil_tmp10);
   }
   {
 #line 196
   __cil_tmp11 = dev_priv->saveMSR;
 #line 196
   __cil_tmp12 = (int )__cil_tmp11;
 #line 196
   if (__cil_tmp12 & 1) {
 #line 197
     cr_index = (u16 )980U;
 #line 198
     cr_data = (u16 )981U;
 #line 199
     st01 = (u16 )986U;
   } else {
 #line 201
     cr_index = (u16 )948U;
 #line 202
     cr_data = (u16 )949U;
 #line 203
     st01 = (u16 )954U;
   }
   }
 #line 207
   i = 0;
 #line 207
   goto ldv_37635;
   ldv_37634: 
   {
 #line 208
   __cil_tmp13 = (u16 )964;
 #line 208
   __cil_tmp14 = (u16 )965;
 #line 208
   __cil_tmp15 = (u8 )i;
 #line 208
   __cil_tmp16 = (int )__cil_tmp15;
 #line 208
   __cil_tmp17 = (u8 )__cil_tmp16;
 #line 208
   __cil_tmp18 = dev_priv->saveSR[i];
 #line 208
   __cil_tmp19 = (int )__cil_tmp18;
 #line 208
   __cil_tmp20 = (u8 )__cil_tmp19;
 #line 208
   i915_write_indexed(dev, __cil_tmp13, __cil_tmp14, __cil_tmp17, __cil_tmp20);
 #line 207
   i = i + 1;
   }
   ldv_37635: ;
 #line 207
   if (i <= 6) {
 #line 208
     goto ldv_37634;
   } else {
 #line 210
     goto ldv_37636;
   }
   ldv_37636: 
   {
 #line 213
   __cil_tmp21 = (int )cr_index;
 #line 213
   __cil_tmp22 = (u16 )__cil_tmp21;
 #line 213
   __cil_tmp23 = (int )cr_data;
 #line 213
   __cil_tmp24 = (u16 )__cil_tmp23;
 #line 213
   __cil_tmp25 = (u8 )17;
 #line 213
   __cil_tmp26 = dev_priv->saveCR[17];
 #line 213
   __cil_tmp27 = (int )__cil_tmp26;
 #line 213
   __cil_tmp28 = (u8 )__cil_tmp27;
 #line 213
   i915_write_indexed(dev, __cil_tmp22, __cil_tmp24, __cil_tmp25, __cil_tmp28);
 #line 214
   i = 0;
   }
 #line 214
   goto ldv_37638;
   ldv_37637: 
   {
 #line 215
   __cil_tmp29 = (int )cr_index;
 #line 215
   __cil_tmp30 = (u16 )__cil_tmp29;
 #line 215
   __cil_tmp31 = (int )cr_data;
 #line 215
   __cil_tmp32 = (u16 )__cil_tmp31;
 #line 215
   __cil_tmp33 = (u8 )i;
 #line 215
   __cil_tmp34 = (int )__cil_tmp33;
 #line 215
   __cil_tmp35 = (u8 )__cil_tmp34;
 #line 215
   __cil_tmp36 = dev_priv->saveCR[i];
 #line 215
   __cil_tmp37 = (int )__cil_tmp36;
 #line 215
   __cil_tmp38 = (u8 )__cil_tmp37;
 #line 215
   i915_write_indexed(dev, __cil_tmp30, __cil_tmp32, __cil_tmp35, __cil_tmp38);
 #line 214
   i = i + 1;
   }
   ldv_37638: ;
 #line 214
   if (i <= 36) {
 #line 215
     goto ldv_37637;
   } else {
 #line 217
     goto ldv_37639;
   }
   ldv_37639: 
 #line 218
   i = 0;
 #line 218
   goto ldv_37641;
   ldv_37640: 
   {
 #line 219
   __cil_tmp39 = (u16 )974;
 #line 219
   __cil_tmp40 = (u16 )975;
 #line 219
   __cil_tmp41 = (u8 )i;
 #line 219
   __cil_tmp42 = (int )__cil_tmp41;
 #line 219
   __cil_tmp43 = (u8 )__cil_tmp42;
 #line 219
   __cil_tmp44 = dev_priv->saveGR[i];
 #line 219
   __cil_tmp45 = (int )__cil_tmp44;
 #line 219
   __cil_tmp46 = (u8 )__cil_tmp45;
 #line 219
   i915_write_indexed(dev, __cil_tmp39, __cil_tmp40, __cil_tmp43, __cil_tmp46);
 #line 218
   i = i + 1;
   }
   ldv_37641: ;
 #line 218
   if (i <= 8) {
 #line 219
     goto ldv_37640;
   } else {
 #line 221
     goto ldv_37642;
   }
   ldv_37642: 
   {
 #line 222
   __cil_tmp47 = (u16 )974;
 #line 222
   __cil_tmp48 = (u16 )975;
 #line 222
   __cil_tmp49 = (u8 )16;
 #line 222
   __cil_tmp50 = dev_priv->saveGR[16];
 #line 222
   __cil_tmp51 = (int )__cil_tmp50;
 #line 222
   __cil_tmp52 = (u8 )__cil_tmp51;
 #line 222
   i915_write_indexed(dev, __cil_tmp47, __cil_tmp48, __cil_tmp49, __cil_tmp52);
 #line 224
   __cil_tmp53 = (u16 )974;
 #line 224
   __cil_tmp54 = (u16 )975;
 #line 224
   __cil_tmp55 = (u8 )17;
 #line 224
   __cil_tmp56 = dev_priv->saveGR[17];
 #line 224
   __cil_tmp57 = (int )__cil_tmp56;
 #line 224
   __cil_tmp58 = (u8 )__cil_tmp57;
 #line 224
   i915_write_indexed(dev, __cil_tmp53, __cil_tmp54, __cil_tmp55, __cil_tmp58);
 #line 226
   __cil_tmp59 = (u16 )974;
 #line 226
   __cil_tmp60 = (u16 )975;
 #line 226
   __cil_tmp61 = (u8 )24;
 #line 226
   __cil_tmp62 = dev_priv->saveGR[24];
 #line 226
   __cil_tmp63 = (int )__cil_tmp62;
 #line 226
   __cil_tmp64 = (u8 )__cil_tmp63;
 #line 226
   i915_write_indexed(dev, __cil_tmp59, __cil_tmp60, __cil_tmp61, __cil_tmp64);
 #line 230
   __cil_tmp65 = (u32 )st01;
 #line 230
   i915_read8___0(dev_priv, __cil_tmp65);
 #line 231
   i = 0;
   }
 #line 231
   goto ldv_37644;
   ldv_37643: 
   {
 #line 232
   __cil_tmp66 = (int )st01;
 #line 232
   __cil_tmp67 = (u16 )__cil_tmp66;
 #line 232
   __cil_tmp68 = (u8 )i;
 #line 232
   __cil_tmp69 = (int )__cil_tmp68;
 #line 232
   __cil_tmp70 = (u8 )__cil_tmp69;
 #line 232
   __cil_tmp71 = dev_priv->saveAR[i];
 #line 232
   __cil_tmp72 = (int )__cil_tmp71;
 #line 232
   __cil_tmp73 = (u8 )__cil_tmp72;
 #line 232
   __cil_tmp74 = (u16 )0;
 #line 232
   i915_write_ar(dev, __cil_tmp67, __cil_tmp70, __cil_tmp73, __cil_tmp74);
 #line 231
   i = i + 1;
   }
   ldv_37644: ;
 #line 231
   if (i <= 20) {
 #line 232
     goto ldv_37643;
   } else {
 #line 234
     goto ldv_37645;
   }
   ldv_37645: 
   {
 #line 233
   __cil_tmp75 = (u32 )st01;
 #line 233
   i915_read8___0(dev_priv, __cil_tmp75);
 #line 234
   __cil_tmp76 = dev_priv->saveAR_INDEX;
 #line 234
   __cil_tmp77 = (unsigned int )__cil_tmp76;
 #line 234
   __cil_tmp78 = __cil_tmp77 | 32U;
 #line 234
   __cil_tmp79 = (int )__cil_tmp78;
 #line 234
   __cil_tmp80 = (u8 )__cil_tmp79;
 #line 234
   i915_write8(dev_priv, 960U, __cil_tmp80);
 #line 235
   __cil_tmp81 = (u32 )st01;
 #line 235
   i915_read8___0(dev_priv, __cil_tmp81);
 #line 238
   __cil_tmp82 = dev_priv->saveDACMASK;
 #line 238
   __cil_tmp83 = (int )__cil_tmp82;
 #line 238
   __cil_tmp84 = (u8 )__cil_tmp83;
 #line 238
   i915_write8(dev_priv, 966U, __cil_tmp84);
   }
 #line 239
   return;
 }
 }
 #line 241 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_save_modeset_reg(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   int tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp7 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   u8 __cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   u8 __cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   void *__cil_tmp20 ;
   struct drm_i915_private *__cil_tmp21 ;
   struct intel_device_info  const  *__cil_tmp22 ;
   u8 __cil_tmp23 ;
   unsigned char __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct drm_i915_private *__cil_tmp27 ;
   struct intel_device_info  const  *__cil_tmp28 ;
   unsigned char *__cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   void *__cil_tmp33 ;
   struct drm_i915_private *__cil_tmp34 ;
   struct intel_device_info  const  *__cil_tmp35 ;
   u8 __cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   void *__cil_tmp39 ;
   struct drm_i915_private *__cil_tmp40 ;
   struct intel_device_info  const  *__cil_tmp41 ;
   u8 __cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   void *__cil_tmp45 ;
   struct drm_i915_private *__cil_tmp46 ;
   struct intel_device_info  const  *__cil_tmp47 ;
   unsigned char *__cil_tmp48 ;
   unsigned char *__cil_tmp49 ;
   unsigned char __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   void *__cil_tmp52 ;
   struct drm_i915_private *__cil_tmp53 ;
   struct intel_device_info  const  *__cil_tmp54 ;
   u8 __cil_tmp55 ;
   unsigned char __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   void *__cil_tmp58 ;
   struct drm_i915_private *__cil_tmp59 ;
   struct intel_device_info  const  *__cil_tmp60 ;
   u8 __cil_tmp61 ;
   unsigned char __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   void *__cil_tmp64 ;
   struct drm_i915_private *__cil_tmp65 ;
   struct intel_device_info  const  *__cil_tmp66 ;
   u8 __cil_tmp67 ;
   unsigned char __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   void *__cil_tmp70 ;
   struct drm_i915_private *__cil_tmp71 ;
   struct intel_device_info  const  *__cil_tmp72 ;
   unsigned char *__cil_tmp73 ;
   unsigned char *__cil_tmp74 ;
   unsigned char __cil_tmp75 ;
   unsigned int __cil_tmp76 ;
   void *__cil_tmp77 ;
   struct drm_i915_private *__cil_tmp78 ;
   struct intel_device_info  const  *__cil_tmp79 ;
   u8 __cil_tmp80 ;
   unsigned char __cil_tmp81 ;
   unsigned int __cil_tmp82 ;
   void *__cil_tmp83 ;
   struct drm_i915_private *__cil_tmp84 ;
   struct intel_device_info  const  *__cil_tmp85 ;
   u8 __cil_tmp86 ;
   unsigned char __cil_tmp87 ;
   unsigned int __cil_tmp88 ;
   void *__cil_tmp89 ;
   struct drm_i915_private *__cil_tmp90 ;
   struct intel_device_info  const  *__cil_tmp91 ;
   unsigned char *__cil_tmp92 ;
   unsigned char *__cil_tmp93 ;
   unsigned char __cil_tmp94 ;
   unsigned int __cil_tmp95 ;
   void *__cil_tmp96 ;
   struct drm_i915_private *__cil_tmp97 ;
   struct intel_device_info  const  *__cil_tmp98 ;
   u8 __cil_tmp99 ;
   unsigned char __cil_tmp100 ;
   unsigned int __cil_tmp101 ;
   void *__cil_tmp102 ;
   struct drm_i915_private *__cil_tmp103 ;
   struct intel_device_info  const  *__cil_tmp104 ;
   u8 __cil_tmp105 ;
   unsigned char __cil_tmp106 ;
   unsigned int __cil_tmp107 ;
   void *__cil_tmp108 ;
   struct drm_i915_private *__cil_tmp109 ;
   struct intel_device_info  const  *__cil_tmp110 ;
   unsigned char *__cil_tmp111 ;
   unsigned char *__cil_tmp112 ;
   unsigned char __cil_tmp113 ;
   unsigned int __cil_tmp114 ;
   void *__cil_tmp115 ;
   struct drm_i915_private *__cil_tmp116 ;
   struct intel_device_info  const  *__cil_tmp117 ;
   u8 __cil_tmp118 ;
   unsigned char __cil_tmp119 ;
   unsigned int __cil_tmp120 ;
   enum pipe __cil_tmp121 ;
   void *__cil_tmp122 ;
   struct drm_i915_private *__cil_tmp123 ;
   struct intel_device_info  const  *__cil_tmp124 ;
   u8 __cil_tmp125 ;
   unsigned char __cil_tmp126 ;
   unsigned int __cil_tmp127 ;
   void *__cil_tmp128 ;
   struct drm_i915_private *__cil_tmp129 ;
   struct intel_device_info  const  *__cil_tmp130 ;
   u8 __cil_tmp131 ;
   unsigned char __cil_tmp132 ;
   unsigned int __cil_tmp133 ;
   void *__cil_tmp134 ;
   struct drm_i915_private *__cil_tmp135 ;
   struct intel_device_info  const  *__cil_tmp136 ;
   unsigned char *__cil_tmp137 ;
   unsigned char *__cil_tmp138 ;
   unsigned char __cil_tmp139 ;
   unsigned int __cil_tmp140 ;
   void *__cil_tmp141 ;
   struct drm_i915_private *__cil_tmp142 ;
   struct intel_device_info  const  *__cil_tmp143 ;
   u8 __cil_tmp144 ;
   unsigned char __cil_tmp145 ;
   unsigned int __cil_tmp146 ;
   void *__cil_tmp147 ;
   struct drm_i915_private *__cil_tmp148 ;
   struct intel_device_info  const  *__cil_tmp149 ;
   u8 __cil_tmp150 ;
   unsigned char __cil_tmp151 ;
   unsigned int __cil_tmp152 ;
   void *__cil_tmp153 ;
   struct drm_i915_private *__cil_tmp154 ;
   struct intel_device_info  const  *__cil_tmp155 ;
   u8 __cil_tmp156 ;
   unsigned char __cil_tmp157 ;
   unsigned int __cil_tmp158 ;
   void *__cil_tmp159 ;
   struct drm_i915_private *__cil_tmp160 ;
   struct intel_device_info  const  *__cil_tmp161 ;
   unsigned char *__cil_tmp162 ;
   unsigned char *__cil_tmp163 ;
   unsigned char __cil_tmp164 ;
   unsigned int __cil_tmp165 ;
   void *__cil_tmp166 ;
   struct drm_i915_private *__cil_tmp167 ;
   struct intel_device_info  const  *__cil_tmp168 ;
   u8 __cil_tmp169 ;
   unsigned char __cil_tmp170 ;
   unsigned int __cil_tmp171 ;
   void *__cil_tmp172 ;
   struct drm_i915_private *__cil_tmp173 ;
   struct intel_device_info  const  *__cil_tmp174 ;
   u8 __cil_tmp175 ;
   unsigned char __cil_tmp176 ;
   unsigned int __cil_tmp177 ;
   void *__cil_tmp178 ;
   struct drm_i915_private *__cil_tmp179 ;
   struct intel_device_info  const  *__cil_tmp180 ;
   unsigned char *__cil_tmp181 ;
   unsigned char *__cil_tmp182 ;
   unsigned char __cil_tmp183 ;
   unsigned int __cil_tmp184 ;
   void *__cil_tmp185 ;
   struct drm_i915_private *__cil_tmp186 ;
   struct intel_device_info  const  *__cil_tmp187 ;
   u8 __cil_tmp188 ;
   unsigned char __cil_tmp189 ;
   unsigned int __cil_tmp190 ;
   void *__cil_tmp191 ;
   struct drm_i915_private *__cil_tmp192 ;
   struct intel_device_info  const  *__cil_tmp193 ;
   u8 __cil_tmp194 ;
   unsigned char __cil_tmp195 ;
   unsigned int __cil_tmp196 ;
   void *__cil_tmp197 ;
   struct drm_i915_private *__cil_tmp198 ;
   struct intel_device_info  const  *__cil_tmp199 ;
   unsigned char *__cil_tmp200 ;
   unsigned char *__cil_tmp201 ;
   unsigned char __cil_tmp202 ;
   unsigned int __cil_tmp203 ;
   void *__cil_tmp204 ;
   struct drm_i915_private *__cil_tmp205 ;
   struct intel_device_info  const  *__cil_tmp206 ;
   u8 __cil_tmp207 ;
   unsigned char __cil_tmp208 ;
   unsigned int __cil_tmp209 ;
   enum pipe __cil_tmp210 ;
   void *__cil_tmp211 ;
   struct drm_i915_private *__cil_tmp212 ;
   struct intel_device_info  const  *__cil_tmp213 ;
   u8 __cil_tmp214 ;
   int __cil_tmp215 ;
   void *__cil_tmp216 ;
   struct drm_i915_private *__cil_tmp217 ;
   struct intel_device_info  const  *__cil_tmp218 ;
   u8 __cil_tmp219 ;
   int __cil_tmp220 ;
   void *__cil_tmp221 ;
   struct drm_i915_private *__cil_tmp222 ;
   struct intel_device_info  const  *__cil_tmp223 ;
   u8 __cil_tmp224 ;
   int __cil_tmp225 ;
   void *__cil_tmp226 ;
   struct drm_i915_private *__cil_tmp227 ;
   struct intel_device_info  const  *__cil_tmp228 ;
   u8 __cil_tmp229 ;
   int __cil_tmp230 ;
   void *__cil_tmp231 ;
   struct drm_i915_private *__cil_tmp232 ;
   struct intel_device_info  const  *__cil_tmp233 ;
   u8 __cil_tmp234 ;
   int __cil_tmp235 ;
   int __cil_tmp236 ;
   int __cil_tmp237 ;
   u32 __cil_tmp238 ;
   int __cil_tmp239 ;
   int __cil_tmp240 ;
   u32 __cil_tmp241 ;
   int __cil_tmp242 ;
   void *__cil_tmp243 ;
   struct drm_i915_private *__cil_tmp244 ;
   struct intel_device_info  const  *__cil_tmp245 ;
   unsigned char *__cil_tmp246 ;
   unsigned char *__cil_tmp247 ;
   unsigned char __cil_tmp248 ;
   unsigned int __cil_tmp249 ;
   void *__cil_tmp250 ;
   struct drm_i915_private *__cil_tmp251 ;
   struct intel_device_info  const  *__cil_tmp252 ;
   unsigned char *__cil_tmp253 ;
   unsigned char *__cil_tmp254 ;
   unsigned char __cil_tmp255 ;
   unsigned int __cil_tmp256 ;
   int __cil_tmp257 ;
   int __cil_tmp258 ;
   u32 __cil_tmp259 ;
   int __cil_tmp260 ;
   int __cil_tmp261 ;
   u32 __cil_tmp262 ;
 
   {
   {
 #line 243
   __cil_tmp7 = dev->dev_private;
 #line 243
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 246
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 246
   if (tmp != 0) {
 #line 247
     return;
   } else {
 
   }
   {
 #line 250
   dev_priv->saveCURACNTR = i915_read32(dev_priv, 458880U);
 #line 251
   dev_priv->saveCURAPOS = i915_read32(dev_priv, 458888U);
 #line 252
   dev_priv->saveCURABASE = i915_read32(dev_priv, 458884U);
 #line 253
   dev_priv->saveCURBCNTR = i915_read32(dev_priv, 458944U);
 #line 254
   dev_priv->saveCURBPOS = i915_read32(dev_priv, 458952U);
 #line 255
   dev_priv->saveCURBBASE = i915_read32(dev_priv, 458948U);
   }
   {
 #line 256
   __cil_tmp8 = dev->dev_private;
 #line 256
   __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 256
   __cil_tmp10 = __cil_tmp9->info;
 #line 256
   __cil_tmp11 = __cil_tmp10->gen;
 #line 256
   __cil_tmp12 = (unsigned char )__cil_tmp11;
 #line 256
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 256
   if (__cil_tmp13 == 2U) {
     {
 #line 257
     dev_priv->saveCURSIZE = i915_read32(dev_priv, 458912U);
     }
   } else {
 
   }
   }
   {
 #line 259
   __cil_tmp14 = dev->dev_private;
 #line 259
   __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 259
   __cil_tmp16 = __cil_tmp15->info;
 #line 259
   __cil_tmp17 = __cil_tmp16->gen;
 #line 259
   __cil_tmp18 = (unsigned char )__cil_tmp17;
 #line 259
   __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 259
   if (__cil_tmp19 == 5U) {
     {
 #line 260
     dev_priv->savePCH_DREF_CONTROL = i915_read32(dev_priv, 811520U);
 #line 261
     dev_priv->saveDISP_ARB_CTL = i915_read32(dev_priv, 282624U);
     }
   } else {
     {
 #line 259
     __cil_tmp20 = dev->dev_private;
 #line 259
     __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
 #line 259
     __cil_tmp22 = __cil_tmp21->info;
 #line 259
     __cil_tmp23 = __cil_tmp22->gen;
 #line 259
     __cil_tmp24 = (unsigned char )__cil_tmp23;
 #line 259
     __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 259
     if (__cil_tmp25 == 6U) {
       {
 #line 260
       dev_priv->savePCH_DREF_CONTROL = i915_read32(dev_priv, 811520U);
 #line 261
       dev_priv->saveDISP_ARB_CTL = i915_read32(dev_priv, 282624U);
       }
     } else {
       {
 #line 259
       __cil_tmp26 = dev->dev_private;
 #line 259
       __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
 #line 259
       __cil_tmp28 = __cil_tmp27->info;
 #line 259
       __cil_tmp29 = (unsigned char *)__cil_tmp28;
 #line 259
       __cil_tmp30 = __cil_tmp29 + 2UL;
 #line 259
       __cil_tmp31 = *__cil_tmp30;
 #line 259
       __cil_tmp32 = (unsigned int )__cil_tmp31;
 #line 259
       if (__cil_tmp32 != 0U) {
         {
 #line 260
         dev_priv->savePCH_DREF_CONTROL = i915_read32(dev_priv, 811520U);
 #line 261
         dev_priv->saveDISP_ARB_CTL = i915_read32(dev_priv, 282624U);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 265
   dev_priv->savePIPEACONF = i915_read32(dev_priv, 458760U);
 #line 266
   dev_priv->savePIPEASRC = i915_read32(dev_priv, 393244U);
   }
   {
 #line 267
   __cil_tmp33 = dev->dev_private;
 #line 267
   __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
 #line 267
   __cil_tmp35 = __cil_tmp34->info;
 #line 267
   __cil_tmp36 = __cil_tmp35->gen;
 #line 267
   __cil_tmp37 = (unsigned char )__cil_tmp36;
 #line 267
   __cil_tmp38 = (unsigned int )__cil_tmp37;
 #line 267
   if (__cil_tmp38 == 5U) {
     {
 #line 268
     dev_priv->saveFPA0 = i915_read32(dev_priv, 811072U);
 #line 269
     dev_priv->saveFPA1 = i915_read32(dev_priv, 811076U);
 #line 270
     dev_priv->saveDPLL_A = i915_read32(dev_priv, 811028U);
     }
   } else {
     {
 #line 267
     __cil_tmp39 = dev->dev_private;
 #line 267
     __cil_tmp40 = (struct drm_i915_private *)__cil_tmp39;
 #line 267
     __cil_tmp41 = __cil_tmp40->info;
 #line 267
     __cil_tmp42 = __cil_tmp41->gen;
 #line 267
     __cil_tmp43 = (unsigned char )__cil_tmp42;
 #line 267
     __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 267
     if (__cil_tmp44 == 6U) {
       {
 #line 268
       dev_priv->saveFPA0 = i915_read32(dev_priv, 811072U);
 #line 269
       dev_priv->saveFPA1 = i915_read32(dev_priv, 811076U);
 #line 270
       dev_priv->saveDPLL_A = i915_read32(dev_priv, 811028U);
       }
     } else {
       {
 #line 267
       __cil_tmp45 = dev->dev_private;
 #line 267
       __cil_tmp46 = (struct drm_i915_private *)__cil_tmp45;
 #line 267
       __cil_tmp47 = __cil_tmp46->info;
 #line 267
       __cil_tmp48 = (unsigned char *)__cil_tmp47;
 #line 267
       __cil_tmp49 = __cil_tmp48 + 2UL;
 #line 267
       __cil_tmp50 = *__cil_tmp49;
 #line 267
       __cil_tmp51 = (unsigned int )__cil_tmp50;
 #line 267
       if (__cil_tmp51 != 0U) {
         {
 #line 268
         dev_priv->saveFPA0 = i915_read32(dev_priv, 811072U);
 #line 269
         dev_priv->saveFPA1 = i915_read32(dev_priv, 811076U);
 #line 270
         dev_priv->saveDPLL_A = i915_read32(dev_priv, 811028U);
         }
       } else {
         {
 #line 272
         dev_priv->saveFPA0 = i915_read32(dev_priv, 24640U);
 #line 273
         dev_priv->saveFPA1 = i915_read32(dev_priv, 24644U);
 #line 274
         dev_priv->saveDPLL_A = i915_read32(dev_priv, 24596U);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 276
   __cil_tmp52 = dev->dev_private;
 #line 276
   __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
 #line 276
   __cil_tmp54 = __cil_tmp53->info;
 #line 276
   __cil_tmp55 = __cil_tmp54->gen;
 #line 276
   __cil_tmp56 = (unsigned char )__cil_tmp55;
 #line 276
   __cil_tmp57 = (unsigned int )__cil_tmp56;
 #line 276
   if (__cil_tmp57 > 3U) {
     {
 #line 276
     __cil_tmp58 = dev->dev_private;
 #line 276
     __cil_tmp59 = (struct drm_i915_private *)__cil_tmp58;
 #line 276
     __cil_tmp60 = __cil_tmp59->info;
 #line 276
     __cil_tmp61 = __cil_tmp60->gen;
 #line 276
     __cil_tmp62 = (unsigned char )__cil_tmp61;
 #line 276
     __cil_tmp63 = (unsigned int )__cil_tmp62;
 #line 276
     if (__cil_tmp63 != 5U) {
       {
 #line 276
       __cil_tmp64 = dev->dev_private;
 #line 276
       __cil_tmp65 = (struct drm_i915_private *)__cil_tmp64;
 #line 276
       __cil_tmp66 = __cil_tmp65->info;
 #line 276
       __cil_tmp67 = __cil_tmp66->gen;
 #line 276
       __cil_tmp68 = (unsigned char )__cil_tmp67;
 #line 276
       __cil_tmp69 = (unsigned int )__cil_tmp68;
 #line 276
       if (__cil_tmp69 != 6U) {
         {
 #line 276
         __cil_tmp70 = dev->dev_private;
 #line 276
         __cil_tmp71 = (struct drm_i915_private *)__cil_tmp70;
 #line 276
         __cil_tmp72 = __cil_tmp71->info;
 #line 276
         __cil_tmp73 = (unsigned char *)__cil_tmp72;
 #line 276
         __cil_tmp74 = __cil_tmp73 + 2UL;
 #line 276
         __cil_tmp75 = *__cil_tmp74;
 #line 276
         __cil_tmp76 = (unsigned int )__cil_tmp75;
 #line 276
         if (__cil_tmp76 == 0U) {
           {
 #line 277
           dev_priv->saveDPLL_A_MD = i915_read32(dev_priv, 24604U);
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 278
   dev_priv->saveHTOTAL_A = i915_read32(dev_priv, 393216U);
 #line 279
   dev_priv->saveHBLANK_A = i915_read32(dev_priv, 393220U);
 #line 280
   dev_priv->saveHSYNC_A = i915_read32(dev_priv, 393224U);
 #line 281
   dev_priv->saveVTOTAL_A = i915_read32(dev_priv, 393228U);
 #line 282
   dev_priv->saveVBLANK_A = i915_read32(dev_priv, 393232U);
 #line 283
   dev_priv->saveVSYNC_A = i915_read32(dev_priv, 393236U);
   }
   {
 #line 284
   __cil_tmp77 = dev->dev_private;
 #line 284
   __cil_tmp78 = (struct drm_i915_private *)__cil_tmp77;
 #line 284
   __cil_tmp79 = __cil_tmp78->info;
 #line 284
   __cil_tmp80 = __cil_tmp79->gen;
 #line 284
   __cil_tmp81 = (unsigned char )__cil_tmp80;
 #line 284
   __cil_tmp82 = (unsigned int )__cil_tmp81;
 #line 284
   if (__cil_tmp82 != 5U) {
     {
 #line 284
     __cil_tmp83 = dev->dev_private;
 #line 284
     __cil_tmp84 = (struct drm_i915_private *)__cil_tmp83;
 #line 284
     __cil_tmp85 = __cil_tmp84->info;
 #line 284
     __cil_tmp86 = __cil_tmp85->gen;
 #line 284
     __cil_tmp87 = (unsigned char )__cil_tmp86;
 #line 284
     __cil_tmp88 = (unsigned int )__cil_tmp87;
 #line 284
     if (__cil_tmp88 != 6U) {
       {
 #line 284
       __cil_tmp89 = dev->dev_private;
 #line 284
       __cil_tmp90 = (struct drm_i915_private *)__cil_tmp89;
 #line 284
       __cil_tmp91 = __cil_tmp90->info;
 #line 284
       __cil_tmp92 = (unsigned char *)__cil_tmp91;
 #line 284
       __cil_tmp93 = __cil_tmp92 + 2UL;
 #line 284
       __cil_tmp94 = *__cil_tmp93;
 #line 284
       __cil_tmp95 = (unsigned int )__cil_tmp94;
 #line 284
       if (__cil_tmp95 == 0U) {
         {
 #line 285
         dev_priv->saveBCLRPAT_A = i915_read32(dev_priv, 393248U);
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 287
   __cil_tmp96 = dev->dev_private;
 #line 287
   __cil_tmp97 = (struct drm_i915_private *)__cil_tmp96;
 #line 287
   __cil_tmp98 = __cil_tmp97->info;
 #line 287
   __cil_tmp99 = __cil_tmp98->gen;
 #line 287
   __cil_tmp100 = (unsigned char )__cil_tmp99;
 #line 287
   __cil_tmp101 = (unsigned int )__cil_tmp100;
 #line 287
   if (__cil_tmp101 == 5U) {
 #line 287
     goto _L;
   } else {
     {
 #line 287
     __cil_tmp102 = dev->dev_private;
 #line 287
     __cil_tmp103 = (struct drm_i915_private *)__cil_tmp102;
 #line 287
     __cil_tmp104 = __cil_tmp103->info;
 #line 287
     __cil_tmp105 = __cil_tmp104->gen;
 #line 287
     __cil_tmp106 = (unsigned char )__cil_tmp105;
 #line 287
     __cil_tmp107 = (unsigned int )__cil_tmp106;
 #line 287
     if (__cil_tmp107 == 6U) {
 #line 287
       goto _L;
     } else {
       {
 #line 287
       __cil_tmp108 = dev->dev_private;
 #line 287
       __cil_tmp109 = (struct drm_i915_private *)__cil_tmp108;
 #line 287
       __cil_tmp110 = __cil_tmp109->info;
 #line 287
       __cil_tmp111 = (unsigned char *)__cil_tmp110;
 #line 287
       __cil_tmp112 = __cil_tmp111 + 2UL;
 #line 287
       __cil_tmp113 = *__cil_tmp112;
 #line 287
       __cil_tmp114 = (unsigned int )__cil_tmp113;
 #line 287
       if (__cil_tmp114 != 0U) {
         _L: 
         {
 #line 288
         dev_priv->savePIPEA_DATA_M1 = i915_read32(dev_priv, 393264U);
 #line 289
         dev_priv->savePIPEA_DATA_N1 = i915_read32(dev_priv, 393268U);
 #line 290
         dev_priv->savePIPEA_LINK_M1 = i915_read32(dev_priv, 393280U);
 #line 291
         dev_priv->savePIPEA_LINK_N1 = i915_read32(dev_priv, 393284U);
 #line 293
         dev_priv->saveFDI_TXA_CTL = i915_read32(dev_priv, 393472U);
 #line 294
         dev_priv->saveFDI_RXA_CTL = i915_read32(dev_priv, 983052U);
 #line 296
         dev_priv->savePFA_CTL_1 = i915_read32(dev_priv, 426112U);
 #line 297
         dev_priv->savePFA_WIN_SZ = i915_read32(dev_priv, 426100U);
 #line 298
         dev_priv->savePFA_WIN_POS = i915_read32(dev_priv, 426096U);
 #line 300
         dev_priv->saveTRANSACONF = i915_read32(dev_priv, 983048U);
 #line 301
         dev_priv->saveTRANS_HTOTAL_A = i915_read32(dev_priv, 917504U);
 #line 302
         dev_priv->saveTRANS_HBLANK_A = i915_read32(dev_priv, 917508U);
 #line 303
         dev_priv->saveTRANS_HSYNC_A = i915_read32(dev_priv, 917512U);
 #line 304
         dev_priv->saveTRANS_VTOTAL_A = i915_read32(dev_priv, 917516U);
 #line 305
         dev_priv->saveTRANS_VBLANK_A = i915_read32(dev_priv, 917520U);
 #line 306
         dev_priv->saveTRANS_VSYNC_A = i915_read32(dev_priv, 917524U);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 309
   dev_priv->saveDSPACNTR = i915_read32(dev_priv, 459136U);
 #line 310
   dev_priv->saveDSPASTRIDE = i915_read32(dev_priv, 459144U);
 #line 311
   dev_priv->saveDSPASIZE = i915_read32(dev_priv, 459152U);
 #line 312
   dev_priv->saveDSPAPOS = i915_read32(dev_priv, 459148U);
 #line 313
   dev_priv->saveDSPAADDR = i915_read32(dev_priv, 459140U);
   }
   {
 #line 314
   __cil_tmp115 = dev->dev_private;
 #line 314
   __cil_tmp116 = (struct drm_i915_private *)__cil_tmp115;
 #line 314
   __cil_tmp117 = __cil_tmp116->info;
 #line 314
   __cil_tmp118 = __cil_tmp117->gen;
 #line 314
   __cil_tmp119 = (unsigned char )__cil_tmp118;
 #line 314
   __cil_tmp120 = (unsigned int )__cil_tmp119;
 #line 314
   if (__cil_tmp120 > 3U) {
     {
 #line 315
     dev_priv->saveDSPASURF = i915_read32(dev_priv, 459164U);
 #line 316
     dev_priv->saveDSPATILEOFF = i915_read32(dev_priv, 459172U);
     }
   } else {
 
   }
   }
   {
 #line 318
   __cil_tmp121 = (enum pipe )0;
 #line 318
   i915_save_palette(dev, __cil_tmp121);
 #line 319
   dev_priv->savePIPEASTAT = i915_read32(dev_priv, 458788U);
 #line 322
   dev_priv->savePIPEBCONF = i915_read32(dev_priv, 462856U);
 #line 323
   dev_priv->savePIPEBSRC = i915_read32(dev_priv, 397340U);
   }
   {
 #line 324
   __cil_tmp122 = dev->dev_private;
 #line 324
   __cil_tmp123 = (struct drm_i915_private *)__cil_tmp122;
 #line 324
   __cil_tmp124 = __cil_tmp123->info;
 #line 324
   __cil_tmp125 = __cil_tmp124->gen;
 #line 324
   __cil_tmp126 = (unsigned char )__cil_tmp125;
 #line 324
   __cil_tmp127 = (unsigned int )__cil_tmp126;
 #line 324
   if (__cil_tmp127 == 5U) {
     {
 #line 325
     dev_priv->saveFPB0 = i915_read32(dev_priv, 811080U);
 #line 326
     dev_priv->saveFPB1 = i915_read32(dev_priv, 811084U);
 #line 327
     dev_priv->saveDPLL_B = i915_read32(dev_priv, 811032U);
     }
   } else {
     {
 #line 324
     __cil_tmp128 = dev->dev_private;
 #line 324
     __cil_tmp129 = (struct drm_i915_private *)__cil_tmp128;
 #line 324
     __cil_tmp130 = __cil_tmp129->info;
 #line 324
     __cil_tmp131 = __cil_tmp130->gen;
 #line 324
     __cil_tmp132 = (unsigned char )__cil_tmp131;
 #line 324
     __cil_tmp133 = (unsigned int )__cil_tmp132;
 #line 324
     if (__cil_tmp133 == 6U) {
       {
 #line 325
       dev_priv->saveFPB0 = i915_read32(dev_priv, 811080U);
 #line 326
       dev_priv->saveFPB1 = i915_read32(dev_priv, 811084U);
 #line 327
       dev_priv->saveDPLL_B = i915_read32(dev_priv, 811032U);
       }
     } else {
       {
 #line 324
       __cil_tmp134 = dev->dev_private;
 #line 324
       __cil_tmp135 = (struct drm_i915_private *)__cil_tmp134;
 #line 324
       __cil_tmp136 = __cil_tmp135->info;
 #line 324
       __cil_tmp137 = (unsigned char *)__cil_tmp136;
 #line 324
       __cil_tmp138 = __cil_tmp137 + 2UL;
 #line 324
       __cil_tmp139 = *__cil_tmp138;
 #line 324
       __cil_tmp140 = (unsigned int )__cil_tmp139;
 #line 324
       if (__cil_tmp140 != 0U) {
         {
 #line 325
         dev_priv->saveFPB0 = i915_read32(dev_priv, 811080U);
 #line 326
         dev_priv->saveFPB1 = i915_read32(dev_priv, 811084U);
 #line 327
         dev_priv->saveDPLL_B = i915_read32(dev_priv, 811032U);
         }
       } else {
         {
 #line 329
         dev_priv->saveFPB0 = i915_read32(dev_priv, 24648U);
 #line 330
         dev_priv->saveFPB1 = i915_read32(dev_priv, 24652U);
 #line 331
         dev_priv->saveDPLL_B = i915_read32(dev_priv, 24600U);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 333
   __cil_tmp141 = dev->dev_private;
 #line 333
   __cil_tmp142 = (struct drm_i915_private *)__cil_tmp141;
 #line 333
   __cil_tmp143 = __cil_tmp142->info;
 #line 333
   __cil_tmp144 = __cil_tmp143->gen;
 #line 333
   __cil_tmp145 = (unsigned char )__cil_tmp144;
 #line 333
   __cil_tmp146 = (unsigned int )__cil_tmp145;
 #line 333
   if (__cil_tmp146 > 3U) {
     {
 #line 333
     __cil_tmp147 = dev->dev_private;
 #line 333
     __cil_tmp148 = (struct drm_i915_private *)__cil_tmp147;
 #line 333
     __cil_tmp149 = __cil_tmp148->info;
 #line 333
     __cil_tmp150 = __cil_tmp149->gen;
 #line 333
     __cil_tmp151 = (unsigned char )__cil_tmp150;
 #line 333
     __cil_tmp152 = (unsigned int )__cil_tmp151;
 #line 333
     if (__cil_tmp152 != 5U) {
       {
 #line 333
       __cil_tmp153 = dev->dev_private;
 #line 333
       __cil_tmp154 = (struct drm_i915_private *)__cil_tmp153;
 #line 333
       __cil_tmp155 = __cil_tmp154->info;
 #line 333
       __cil_tmp156 = __cil_tmp155->gen;
 #line 333
       __cil_tmp157 = (unsigned char )__cil_tmp156;
 #line 333
       __cil_tmp158 = (unsigned int )__cil_tmp157;
 #line 333
       if (__cil_tmp158 != 6U) {
         {
 #line 333
         __cil_tmp159 = dev->dev_private;
 #line 333
         __cil_tmp160 = (struct drm_i915_private *)__cil_tmp159;
 #line 333
         __cil_tmp161 = __cil_tmp160->info;
 #line 333
         __cil_tmp162 = (unsigned char *)__cil_tmp161;
 #line 333
         __cil_tmp163 = __cil_tmp162 + 2UL;
 #line 333
         __cil_tmp164 = *__cil_tmp163;
 #line 333
         __cil_tmp165 = (unsigned int )__cil_tmp164;
 #line 333
         if (__cil_tmp165 == 0U) {
           {
 #line 334
           dev_priv->saveDPLL_B_MD = i915_read32(dev_priv, 24608U);
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 335
   dev_priv->saveHTOTAL_B = i915_read32(dev_priv, 397312U);
 #line 336
   dev_priv->saveHBLANK_B = i915_read32(dev_priv, 397316U);
 #line 337
   dev_priv->saveHSYNC_B = i915_read32(dev_priv, 397320U);
 #line 338
   dev_priv->saveVTOTAL_B = i915_read32(dev_priv, 397324U);
 #line 339
   dev_priv->saveVBLANK_B = i915_read32(dev_priv, 397328U);
 #line 340
   dev_priv->saveVSYNC_B = i915_read32(dev_priv, 397332U);
   }
   {
 #line 341
   __cil_tmp166 = dev->dev_private;
 #line 341
   __cil_tmp167 = (struct drm_i915_private *)__cil_tmp166;
 #line 341
   __cil_tmp168 = __cil_tmp167->info;
 #line 341
   __cil_tmp169 = __cil_tmp168->gen;
 #line 341
   __cil_tmp170 = (unsigned char )__cil_tmp169;
 #line 341
   __cil_tmp171 = (unsigned int )__cil_tmp170;
 #line 341
   if (__cil_tmp171 != 5U) {
     {
 #line 341
     __cil_tmp172 = dev->dev_private;
 #line 341
     __cil_tmp173 = (struct drm_i915_private *)__cil_tmp172;
 #line 341
     __cil_tmp174 = __cil_tmp173->info;
 #line 341
     __cil_tmp175 = __cil_tmp174->gen;
 #line 341
     __cil_tmp176 = (unsigned char )__cil_tmp175;
 #line 341
     __cil_tmp177 = (unsigned int )__cil_tmp176;
 #line 341
     if (__cil_tmp177 != 6U) {
       {
 #line 341
       __cil_tmp178 = dev->dev_private;
 #line 341
       __cil_tmp179 = (struct drm_i915_private *)__cil_tmp178;
 #line 341
       __cil_tmp180 = __cil_tmp179->info;
 #line 341
       __cil_tmp181 = (unsigned char *)__cil_tmp180;
 #line 341
       __cil_tmp182 = __cil_tmp181 + 2UL;
 #line 341
       __cil_tmp183 = *__cil_tmp182;
 #line 341
       __cil_tmp184 = (unsigned int )__cil_tmp183;
 #line 341
       if (__cil_tmp184 == 0U) {
         {
 #line 342
         dev_priv->saveBCLRPAT_B = i915_read32(dev_priv, 397344U);
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 344
   __cil_tmp185 = dev->dev_private;
 #line 344
   __cil_tmp186 = (struct drm_i915_private *)__cil_tmp185;
 #line 344
   __cil_tmp187 = __cil_tmp186->info;
 #line 344
   __cil_tmp188 = __cil_tmp187->gen;
 #line 344
   __cil_tmp189 = (unsigned char )__cil_tmp188;
 #line 344
   __cil_tmp190 = (unsigned int )__cil_tmp189;
 #line 344
   if (__cil_tmp190 == 5U) {
 #line 344
     goto _L___0;
   } else {
     {
 #line 344
     __cil_tmp191 = dev->dev_private;
 #line 344
     __cil_tmp192 = (struct drm_i915_private *)__cil_tmp191;
 #line 344
     __cil_tmp193 = __cil_tmp192->info;
 #line 344
     __cil_tmp194 = __cil_tmp193->gen;
 #line 344
     __cil_tmp195 = (unsigned char )__cil_tmp194;
 #line 344
     __cil_tmp196 = (unsigned int )__cil_tmp195;
 #line 344
     if (__cil_tmp196 == 6U) {
 #line 344
       goto _L___0;
     } else {
       {
 #line 344
       __cil_tmp197 = dev->dev_private;
 #line 344
       __cil_tmp198 = (struct drm_i915_private *)__cil_tmp197;
 #line 344
       __cil_tmp199 = __cil_tmp198->info;
 #line 344
       __cil_tmp200 = (unsigned char *)__cil_tmp199;
 #line 344
       __cil_tmp201 = __cil_tmp200 + 2UL;
 #line 344
       __cil_tmp202 = *__cil_tmp201;
 #line 344
       __cil_tmp203 = (unsigned int )__cil_tmp202;
 #line 344
       if (__cil_tmp203 != 0U) {
         _L___0: 
         {
 #line 345
         dev_priv->savePIPEB_DATA_M1 = i915_read32(dev_priv, 397360U);
 #line 346
         dev_priv->savePIPEB_DATA_N1 = i915_read32(dev_priv, 397364U);
 #line 347
         dev_priv->savePIPEB_LINK_M1 = i915_read32(dev_priv, 397376U);
 #line 348
         dev_priv->savePIPEB_LINK_N1 = i915_read32(dev_priv, 397380U);
 #line 350
         dev_priv->saveFDI_TXB_CTL = i915_read32(dev_priv, 397568U);
 #line 351
         dev_priv->saveFDI_RXB_CTL = i915_read32(dev_priv, 987148U);
 #line 353
         dev_priv->savePFB_CTL_1 = i915_read32(dev_priv, 428160U);
 #line 354
         dev_priv->savePFB_WIN_SZ = i915_read32(dev_priv, 428148U);
 #line 355
         dev_priv->savePFB_WIN_POS = i915_read32(dev_priv, 428144U);
 #line 357
         dev_priv->saveTRANSBCONF = i915_read32(dev_priv, 987144U);
 #line 358
         dev_priv->saveTRANS_HTOTAL_B = i915_read32(dev_priv, 921600U);
 #line 359
         dev_priv->saveTRANS_HBLANK_B = i915_read32(dev_priv, 921604U);
 #line 360
         dev_priv->saveTRANS_HSYNC_B = i915_read32(dev_priv, 921608U);
 #line 361
         dev_priv->saveTRANS_VTOTAL_B = i915_read32(dev_priv, 921612U);
 #line 362
         dev_priv->saveTRANS_VBLANK_B = i915_read32(dev_priv, 921616U);
 #line 363
         dev_priv->saveTRANS_VSYNC_B = i915_read32(dev_priv, 921620U);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 366
   dev_priv->saveDSPBCNTR = i915_read32(dev_priv, 463232U);
 #line 367
   dev_priv->saveDSPBSTRIDE = i915_read32(dev_priv, 463240U);
 #line 368
   dev_priv->saveDSPBSIZE = i915_read32(dev_priv, 463248U);
 #line 369
   dev_priv->saveDSPBPOS = i915_read32(dev_priv, 463244U);
 #line 370
   dev_priv->saveDSPBADDR = i915_read32(dev_priv, 463236U);
   }
   {
 #line 371
   __cil_tmp204 = dev->dev_private;
 #line 371
   __cil_tmp205 = (struct drm_i915_private *)__cil_tmp204;
 #line 371
   __cil_tmp206 = __cil_tmp205->info;
 #line 371
   __cil_tmp207 = __cil_tmp206->gen;
 #line 371
   __cil_tmp208 = (unsigned char )__cil_tmp207;
 #line 371
   __cil_tmp209 = (unsigned int )__cil_tmp208;
 #line 371
   if (__cil_tmp209 > 3U) {
     {
 #line 372
     dev_priv->saveDSPBSURF = i915_read32(dev_priv, 463260U);
 #line 373
     dev_priv->saveDSPBTILEOFF = i915_read32(dev_priv, 463268U);
     }
   } else {
 
   }
   }
   {
 #line 375
   __cil_tmp210 = (enum pipe )1;
 #line 375
   i915_save_palette(dev, __cil_tmp210);
 #line 376
   dev_priv->savePIPEBSTAT = i915_read32(dev_priv, 462884U);
   }
   {
 #line 380
   __cil_tmp211 = dev->dev_private;
 #line 380
   __cil_tmp212 = (struct drm_i915_private *)__cil_tmp211;
 #line 380
   __cil_tmp213 = __cil_tmp212->info;
 #line 380
   __cil_tmp214 = __cil_tmp213->gen;
 #line 380
   __cil_tmp215 = (int )__cil_tmp214;
 #line 380
   if (__cil_tmp215 == 6) {
 #line 380
     goto case_6;
   } else {
     {
 #line 384
     __cil_tmp216 = dev->dev_private;
 #line 384
     __cil_tmp217 = (struct drm_i915_private *)__cil_tmp216;
 #line 384
     __cil_tmp218 = __cil_tmp217->info;
 #line 384
     __cil_tmp219 = __cil_tmp218->gen;
 #line 384
     __cil_tmp220 = (int )__cil_tmp219;
 #line 384
     if (__cil_tmp220 == 5) {
 #line 384
       goto case_5;
     } else {
       {
 #line 385
       __cil_tmp221 = dev->dev_private;
 #line 385
       __cil_tmp222 = (struct drm_i915_private *)__cil_tmp221;
 #line 385
       __cil_tmp223 = __cil_tmp222->info;
 #line 385
       __cil_tmp224 = __cil_tmp223->gen;
 #line 385
       __cil_tmp225 = (int )__cil_tmp224;
 #line 385
       if (__cil_tmp225 == 4) {
 #line 385
         goto case_4;
       } else {
         {
 #line 389
         __cil_tmp226 = dev->dev_private;
 #line 389
         __cil_tmp227 = (struct drm_i915_private *)__cil_tmp226;
 #line 389
         __cil_tmp228 = __cil_tmp227->info;
 #line 389
         __cil_tmp229 = __cil_tmp228->gen;
 #line 389
         __cil_tmp230 = (int )__cil_tmp229;
 #line 389
         if (__cil_tmp230 == 3) {
 #line 389
           goto case_3;
         } else {
           {
 #line 393
           __cil_tmp231 = dev->dev_private;
 #line 393
           __cil_tmp232 = (struct drm_i915_private *)__cil_tmp231;
 #line 393
           __cil_tmp233 = __cil_tmp232->info;
 #line 393
           __cil_tmp234 = __cil_tmp233->gen;
 #line 393
           __cil_tmp235 = (int )__cil_tmp234;
 #line 393
           if (__cil_tmp235 == 2) {
 #line 393
             goto case_2;
           } else
 #line 379
           if (0) {
             case_6: 
 #line 381
             i = 0;
 #line 381
             goto ldv_37653;
             ldv_37652: 
             {
 #line 382
             __cil_tmp236 = i + 131072;
 #line 382
             __cil_tmp237 = __cil_tmp236 * 8;
 #line 382
             __cil_tmp238 = (u32 )__cil_tmp237;
 #line 382
             dev_priv->saveFENCE[i] = i915_read64(dev_priv, __cil_tmp238);
 #line 381
             i = i + 1;
             }
             ldv_37653: ;
 #line 381
             if (i <= 15) {
 #line 382
               goto ldv_37652;
             } else {
 #line 384
               goto ldv_37654;
             }
             ldv_37654: ;
 #line 383
             goto ldv_37655;
             case_5: ;
             case_4: 
 #line 386
             i = 0;
 #line 386
             goto ldv_37659;
             ldv_37658: 
             {
 #line 387
             __cil_tmp239 = i + 1536;
 #line 387
             __cil_tmp240 = __cil_tmp239 * 8;
 #line 387
             __cil_tmp241 = (u32 )__cil_tmp240;
 #line 387
             dev_priv->saveFENCE[i] = i915_read64(dev_priv, __cil_tmp241);
 #line 386
             i = i + 1;
             }
             ldv_37659: ;
 #line 386
             if (i <= 15) {
 #line 387
               goto ldv_37658;
             } else {
 #line 389
               goto ldv_37660;
             }
             ldv_37660: ;
 #line 388
             goto ldv_37655;
             case_3: ;
             {
 #line 390
             __cil_tmp242 = dev->pci_device;
 #line 390
             if (__cil_tmp242 == 10098) {
 #line 390
               goto _L___1;
             } else {
               {
 #line 390
               __cil_tmp243 = dev->dev_private;
 #line 390
               __cil_tmp244 = (struct drm_i915_private *)__cil_tmp243;
 #line 390
               __cil_tmp245 = __cil_tmp244->info;
 #line 390
               __cil_tmp246 = (unsigned char *)__cil_tmp245;
 #line 390
               __cil_tmp247 = __cil_tmp246 + 1UL;
 #line 390
               __cil_tmp248 = *__cil_tmp247;
 #line 390
               __cil_tmp249 = (unsigned int )__cil_tmp248;
 #line 390
               if (__cil_tmp249 != 0U) {
 #line 390
                 goto _L___1;
               } else {
                 {
 #line 390
                 __cil_tmp250 = dev->dev_private;
 #line 390
                 __cil_tmp251 = (struct drm_i915_private *)__cil_tmp250;
 #line 390
                 __cil_tmp252 = __cil_tmp251->info;
 #line 390
                 __cil_tmp253 = (unsigned char *)__cil_tmp252;
 #line 390
                 __cil_tmp254 = __cil_tmp253 + 1UL;
 #line 390
                 __cil_tmp255 = *__cil_tmp254;
 #line 390
                 __cil_tmp256 = (unsigned int )__cil_tmp255;
 #line 390
                 if (__cil_tmp256 != 0U) {
                   _L___1: 
 #line 391
                   i = 0;
 #line 391
                   goto ldv_37663;
                   ldv_37662: 
                   {
 #line 392
                   __cil_tmp257 = i + 3072;
 #line 392
                   __cil_tmp258 = __cil_tmp257 * 4;
 #line 392
                   __cil_tmp259 = (u32 )__cil_tmp258;
 #line 392
                   tmp___0 = i915_read32(dev_priv, __cil_tmp259);
 #line 392
                   dev_priv->saveFENCE[i + 8] = (uint64_t )tmp___0;
 #line 391
                   i = i + 1;
                   }
                   ldv_37663: ;
 #line 391
                   if (i <= 7) {
 #line 392
                     goto ldv_37662;
                   } else {
 #line 394
                     goto ldv_37664;
                   }
                   ldv_37664: ;
                 } else {
 
                 }
                 }
               }
               }
             }
             }
             case_2: 
 #line 394
             i = 0;
 #line 394
             goto ldv_37667;
             ldv_37666: 
             {
 #line 395
             __cil_tmp260 = i + 2048;
 #line 395
             __cil_tmp261 = __cil_tmp260 * 4;
 #line 395
             __cil_tmp262 = (u32 )__cil_tmp261;
 #line 395
             tmp___1 = i915_read32(dev_priv, __cil_tmp262);
 #line 395
             dev_priv->saveFENCE[i] = (uint64_t )tmp___1;
 #line 394
             i = i + 1;
             }
             ldv_37667: ;
 #line 394
             if (i <= 7) {
 #line 395
               goto ldv_37666;
             } else {
 #line 397
               goto ldv_37668;
             }
             ldv_37668: ;
 #line 396
             goto ldv_37655;
           } else {
 
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_37655: ;
 #line 399
   return;
 }
 }
 #line 402 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_restore_modeset_reg(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int dpll_a_reg ;
   int fpa0_reg ;
   int fpa1_reg ;
   int dpll_b_reg ;
   int fpb0_reg ;
   int fpb1_reg ;
   int i ;
   int tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   u8 __cil_tmp17 ;
   int __cil_tmp18 ;
   void *__cil_tmp19 ;
   struct drm_i915_private *__cil_tmp20 ;
   struct intel_device_info  const  *__cil_tmp21 ;
   u8 __cil_tmp22 ;
   int __cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_device_info  const  *__cil_tmp26 ;
   u8 __cil_tmp27 ;
   int __cil_tmp28 ;
   void *__cil_tmp29 ;
   struct drm_i915_private *__cil_tmp30 ;
   struct intel_device_info  const  *__cil_tmp31 ;
   u8 __cil_tmp32 ;
   int __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   u8 __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   u32 __cil_tmp41 ;
   uint64_t __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   u32 __cil_tmp45 ;
   uint64_t __cil_tmp46 ;
   int __cil_tmp47 ;
   void *__cil_tmp48 ;
   struct drm_i915_private *__cil_tmp49 ;
   struct intel_device_info  const  *__cil_tmp50 ;
   unsigned char *__cil_tmp51 ;
   unsigned char *__cil_tmp52 ;
   unsigned char __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   void *__cil_tmp55 ;
   struct drm_i915_private *__cil_tmp56 ;
   struct intel_device_info  const  *__cil_tmp57 ;
   unsigned char *__cil_tmp58 ;
   unsigned char *__cil_tmp59 ;
   unsigned char __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   int __cil_tmp62 ;
   int __cil_tmp63 ;
   u32 __cil_tmp64 ;
   uint64_t __cil_tmp65 ;
   u32 __cil_tmp66 ;
   int __cil_tmp67 ;
   int __cil_tmp68 ;
   u32 __cil_tmp69 ;
   uint64_t __cil_tmp70 ;
   u32 __cil_tmp71 ;
   void *__cil_tmp72 ;
   struct drm_i915_private *__cil_tmp73 ;
   struct intel_device_info  const  *__cil_tmp74 ;
   u8 __cil_tmp75 ;
   unsigned char __cil_tmp76 ;
   unsigned int __cil_tmp77 ;
   void *__cil_tmp78 ;
   struct drm_i915_private *__cil_tmp79 ;
   struct intel_device_info  const  *__cil_tmp80 ;
   u8 __cil_tmp81 ;
   unsigned char __cil_tmp82 ;
   unsigned int __cil_tmp83 ;
   void *__cil_tmp84 ;
   struct drm_i915_private *__cil_tmp85 ;
   struct intel_device_info  const  *__cil_tmp86 ;
   unsigned char *__cil_tmp87 ;
   unsigned char *__cil_tmp88 ;
   unsigned char __cil_tmp89 ;
   unsigned int __cil_tmp90 ;
   void *__cil_tmp91 ;
   struct drm_i915_private *__cil_tmp92 ;
   struct intel_device_info  const  *__cil_tmp93 ;
   u8 __cil_tmp94 ;
   unsigned char __cil_tmp95 ;
   unsigned int __cil_tmp96 ;
   u32 __cil_tmp97 ;
   u32 __cil_tmp98 ;
   void *__cil_tmp99 ;
   struct drm_i915_private *__cil_tmp100 ;
   struct intel_device_info  const  *__cil_tmp101 ;
   u8 __cil_tmp102 ;
   unsigned char __cil_tmp103 ;
   unsigned int __cil_tmp104 ;
   u32 __cil_tmp105 ;
   u32 __cil_tmp106 ;
   void *__cil_tmp107 ;
   struct drm_i915_private *__cil_tmp108 ;
   struct intel_device_info  const  *__cil_tmp109 ;
   unsigned char *__cil_tmp110 ;
   unsigned char *__cil_tmp111 ;
   unsigned char __cil_tmp112 ;
   unsigned int __cil_tmp113 ;
   u32 __cil_tmp114 ;
   u32 __cil_tmp115 ;
   u32 __cil_tmp116 ;
   int __cil_tmp117 ;
   u32 __cil_tmp118 ;
   u32 __cil_tmp119 ;
   unsigned int __cil_tmp120 ;
   unsigned long __cil_tmp121 ;
   void *__cil_tmp122 ;
   void const volatile   *__cil_tmp123 ;
   void const volatile   *__cil_tmp124 ;
   u32 __cil_tmp125 ;
   u32 __cil_tmp126 ;
   u32 __cil_tmp127 ;
   u32 __cil_tmp128 ;
   u32 __cil_tmp129 ;
   u32 __cil_tmp130 ;
   unsigned long __cil_tmp131 ;
   void *__cil_tmp132 ;
   void const volatile   *__cil_tmp133 ;
   void const volatile   *__cil_tmp134 ;
   void *__cil_tmp135 ;
   struct drm_i915_private *__cil_tmp136 ;
   struct intel_device_info  const  *__cil_tmp137 ;
   u8 __cil_tmp138 ;
   unsigned char __cil_tmp139 ;
   unsigned int __cil_tmp140 ;
   void *__cil_tmp141 ;
   struct drm_i915_private *__cil_tmp142 ;
   struct intel_device_info  const  *__cil_tmp143 ;
   u8 __cil_tmp144 ;
   unsigned char __cil_tmp145 ;
   unsigned int __cil_tmp146 ;
   void *__cil_tmp147 ;
   struct drm_i915_private *__cil_tmp148 ;
   struct intel_device_info  const  *__cil_tmp149 ;
   u8 __cil_tmp150 ;
   unsigned char __cil_tmp151 ;
   unsigned int __cil_tmp152 ;
   void *__cil_tmp153 ;
   struct drm_i915_private *__cil_tmp154 ;
   struct intel_device_info  const  *__cil_tmp155 ;
   unsigned char *__cil_tmp156 ;
   unsigned char *__cil_tmp157 ;
   unsigned char __cil_tmp158 ;
   unsigned int __cil_tmp159 ;
   u32 __cil_tmp160 ;
   void *__cil_tmp161 ;
   void const volatile   *__cil_tmp162 ;
   void const volatile   *__cil_tmp163 ;
   u32 __cil_tmp164 ;
   u32 __cil_tmp165 ;
   u32 __cil_tmp166 ;
   u32 __cil_tmp167 ;
   u32 __cil_tmp168 ;
   u32 __cil_tmp169 ;
   void *__cil_tmp170 ;
   struct drm_i915_private *__cil_tmp171 ;
   struct intel_device_info  const  *__cil_tmp172 ;
   u8 __cil_tmp173 ;
   unsigned char __cil_tmp174 ;
   unsigned int __cil_tmp175 ;
   void *__cil_tmp176 ;
   struct drm_i915_private *__cil_tmp177 ;
   struct intel_device_info  const  *__cil_tmp178 ;
   u8 __cil_tmp179 ;
   unsigned char __cil_tmp180 ;
   unsigned int __cil_tmp181 ;
   void *__cil_tmp182 ;
   struct drm_i915_private *__cil_tmp183 ;
   struct intel_device_info  const  *__cil_tmp184 ;
   unsigned char *__cil_tmp185 ;
   unsigned char *__cil_tmp186 ;
   unsigned char __cil_tmp187 ;
   unsigned int __cil_tmp188 ;
   u32 __cil_tmp189 ;
   void *__cil_tmp190 ;
   struct drm_i915_private *__cil_tmp191 ;
   struct intel_device_info  const  *__cil_tmp192 ;
   u8 __cil_tmp193 ;
   unsigned char __cil_tmp194 ;
   unsigned int __cil_tmp195 ;
   void *__cil_tmp196 ;
   struct drm_i915_private *__cil_tmp197 ;
   struct intel_device_info  const  *__cil_tmp198 ;
   u8 __cil_tmp199 ;
   unsigned char __cil_tmp200 ;
   unsigned int __cil_tmp201 ;
   void *__cil_tmp202 ;
   struct drm_i915_private *__cil_tmp203 ;
   struct intel_device_info  const  *__cil_tmp204 ;
   unsigned char *__cil_tmp205 ;
   unsigned char *__cil_tmp206 ;
   unsigned char __cil_tmp207 ;
   unsigned int __cil_tmp208 ;
   u32 __cil_tmp209 ;
   u32 __cil_tmp210 ;
   u32 __cil_tmp211 ;
   u32 __cil_tmp212 ;
   u32 __cil_tmp213 ;
   u32 __cil_tmp214 ;
   u32 __cil_tmp215 ;
   u32 __cil_tmp216 ;
   u32 __cil_tmp217 ;
   u32 __cil_tmp218 ;
   u32 __cil_tmp219 ;
   u32 __cil_tmp220 ;
   u32 __cil_tmp221 ;
   u32 __cil_tmp222 ;
   u32 __cil_tmp223 ;
   u32 __cil_tmp224 ;
   u32 __cil_tmp225 ;
   u32 __cil_tmp226 ;
   u32 __cil_tmp227 ;
   u32 __cil_tmp228 ;
   u32 __cil_tmp229 ;
   void *__cil_tmp230 ;
   struct drm_i915_private *__cil_tmp231 ;
   struct intel_device_info  const  *__cil_tmp232 ;
   u8 __cil_tmp233 ;
   unsigned char __cil_tmp234 ;
   unsigned int __cil_tmp235 ;
   u32 __cil_tmp236 ;
   u32 __cil_tmp237 ;
   u32 __cil_tmp238 ;
   enum pipe __cil_tmp239 ;
   u32 __cil_tmp240 ;
   u32 __cil_tmp241 ;
   int __cil_tmp242 ;
   u32 __cil_tmp243 ;
   u32 __cil_tmp244 ;
   unsigned int __cil_tmp245 ;
   unsigned long __cil_tmp246 ;
   void *__cil_tmp247 ;
   void const volatile   *__cil_tmp248 ;
   void const volatile   *__cil_tmp249 ;
   u32 __cil_tmp250 ;
   u32 __cil_tmp251 ;
   u32 __cil_tmp252 ;
   u32 __cil_tmp253 ;
   u32 __cil_tmp254 ;
   u32 __cil_tmp255 ;
   unsigned long __cil_tmp256 ;
   void *__cil_tmp257 ;
   void const volatile   *__cil_tmp258 ;
   void const volatile   *__cil_tmp259 ;
   void *__cil_tmp260 ;
   struct drm_i915_private *__cil_tmp261 ;
   struct intel_device_info  const  *__cil_tmp262 ;
   u8 __cil_tmp263 ;
   unsigned char __cil_tmp264 ;
   unsigned int __cil_tmp265 ;
   void *__cil_tmp266 ;
   struct drm_i915_private *__cil_tmp267 ;
   struct intel_device_info  const  *__cil_tmp268 ;
   u8 __cil_tmp269 ;
   unsigned char __cil_tmp270 ;
   unsigned int __cil_tmp271 ;
   void *__cil_tmp272 ;
   struct drm_i915_private *__cil_tmp273 ;
   struct intel_device_info  const  *__cil_tmp274 ;
   u8 __cil_tmp275 ;
   unsigned char __cil_tmp276 ;
   unsigned int __cil_tmp277 ;
   void *__cil_tmp278 ;
   struct drm_i915_private *__cil_tmp279 ;
   struct intel_device_info  const  *__cil_tmp280 ;
   unsigned char *__cil_tmp281 ;
   unsigned char *__cil_tmp282 ;
   unsigned char __cil_tmp283 ;
   unsigned int __cil_tmp284 ;
   u32 __cil_tmp285 ;
   void *__cil_tmp286 ;
   void const volatile   *__cil_tmp287 ;
   void const volatile   *__cil_tmp288 ;
   u32 __cil_tmp289 ;
   u32 __cil_tmp290 ;
   u32 __cil_tmp291 ;
   u32 __cil_tmp292 ;
   u32 __cil_tmp293 ;
   u32 __cil_tmp294 ;
   void *__cil_tmp295 ;
   struct drm_i915_private *__cil_tmp296 ;
   struct intel_device_info  const  *__cil_tmp297 ;
   u8 __cil_tmp298 ;
   unsigned char __cil_tmp299 ;
   unsigned int __cil_tmp300 ;
   void *__cil_tmp301 ;
   struct drm_i915_private *__cil_tmp302 ;
   struct intel_device_info  const  *__cil_tmp303 ;
   u8 __cil_tmp304 ;
   unsigned char __cil_tmp305 ;
   unsigned int __cil_tmp306 ;
   void *__cil_tmp307 ;
   struct drm_i915_private *__cil_tmp308 ;
   struct intel_device_info  const  *__cil_tmp309 ;
   unsigned char *__cil_tmp310 ;
   unsigned char *__cil_tmp311 ;
   unsigned char __cil_tmp312 ;
   unsigned int __cil_tmp313 ;
   u32 __cil_tmp314 ;
   void *__cil_tmp315 ;
   struct drm_i915_private *__cil_tmp316 ;
   struct intel_device_info  const  *__cil_tmp317 ;
   u8 __cil_tmp318 ;
   unsigned char __cil_tmp319 ;
   unsigned int __cil_tmp320 ;
   void *__cil_tmp321 ;
   struct drm_i915_private *__cil_tmp322 ;
   struct intel_device_info  const  *__cil_tmp323 ;
   u8 __cil_tmp324 ;
   unsigned char __cil_tmp325 ;
   unsigned int __cil_tmp326 ;
   void *__cil_tmp327 ;
   struct drm_i915_private *__cil_tmp328 ;
   struct intel_device_info  const  *__cil_tmp329 ;
   unsigned char *__cil_tmp330 ;
   unsigned char *__cil_tmp331 ;
   unsigned char __cil_tmp332 ;
   unsigned int __cil_tmp333 ;
   u32 __cil_tmp334 ;
   u32 __cil_tmp335 ;
   u32 __cil_tmp336 ;
   u32 __cil_tmp337 ;
   u32 __cil_tmp338 ;
   u32 __cil_tmp339 ;
   u32 __cil_tmp340 ;
   u32 __cil_tmp341 ;
   u32 __cil_tmp342 ;
   u32 __cil_tmp343 ;
   u32 __cil_tmp344 ;
   u32 __cil_tmp345 ;
   u32 __cil_tmp346 ;
   u32 __cil_tmp347 ;
   u32 __cil_tmp348 ;
   u32 __cil_tmp349 ;
   u32 __cil_tmp350 ;
   u32 __cil_tmp351 ;
   u32 __cil_tmp352 ;
   u32 __cil_tmp353 ;
   u32 __cil_tmp354 ;
   void *__cil_tmp355 ;
   struct drm_i915_private *__cil_tmp356 ;
   struct intel_device_info  const  *__cil_tmp357 ;
   u8 __cil_tmp358 ;
   unsigned char __cil_tmp359 ;
   unsigned int __cil_tmp360 ;
   u32 __cil_tmp361 ;
   u32 __cil_tmp362 ;
   u32 __cil_tmp363 ;
   enum pipe __cil_tmp364 ;
   u32 __cil_tmp365 ;
   u32 __cil_tmp366 ;
   u32 __cil_tmp367 ;
   u32 __cil_tmp368 ;
   u32 __cil_tmp369 ;
   u32 __cil_tmp370 ;
   u32 __cil_tmp371 ;
   void *__cil_tmp372 ;
   struct drm_i915_private *__cil_tmp373 ;
   struct intel_device_info  const  *__cil_tmp374 ;
   u8 __cil_tmp375 ;
   unsigned char __cil_tmp376 ;
   unsigned int __cil_tmp377 ;
   u32 __cil_tmp378 ;
 
   {
   {
 #line 404
   __cil_tmp13 = dev->dev_private;
 #line 404
   dev_priv = (struct drm_i915_private *)__cil_tmp13;
 #line 409
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 409
   if (tmp != 0) {
 #line 410
     return;
   } else {
 
   }
   {
 #line 414
   __cil_tmp14 = dev->dev_private;
 #line 414
   __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 414
   __cil_tmp16 = __cil_tmp15->info;
 #line 414
   __cil_tmp17 = __cil_tmp16->gen;
 #line 414
   __cil_tmp18 = (int )__cil_tmp17;
 #line 414
   if (__cil_tmp18 == 6) {
 #line 414
     goto case_6;
   } else {
     {
 #line 418
     __cil_tmp19 = dev->dev_private;
 #line 418
     __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
 #line 418
     __cil_tmp21 = __cil_tmp20->info;
 #line 418
     __cil_tmp22 = __cil_tmp21->gen;
 #line 418
     __cil_tmp23 = (int )__cil_tmp22;
 #line 418
     if (__cil_tmp23 == 5) {
 #line 418
       goto case_5;
     } else {
       {
 #line 419
       __cil_tmp24 = dev->dev_private;
 #line 419
       __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 419
       __cil_tmp26 = __cil_tmp25->info;
 #line 419
       __cil_tmp27 = __cil_tmp26->gen;
 #line 419
       __cil_tmp28 = (int )__cil_tmp27;
 #line 419
       if (__cil_tmp28 == 4) {
 #line 419
         goto case_4;
       } else {
         {
 #line 423
         __cil_tmp29 = dev->dev_private;
 #line 423
         __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
 #line 423
         __cil_tmp31 = __cil_tmp30->info;
 #line 423
         __cil_tmp32 = __cil_tmp31->gen;
 #line 423
         __cil_tmp33 = (int )__cil_tmp32;
 #line 423
         if (__cil_tmp33 == 3) {
 #line 423
           goto case_3;
         } else {
           {
 #line 424
           __cil_tmp34 = dev->dev_private;
 #line 424
           __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 424
           __cil_tmp36 = __cil_tmp35->info;
 #line 424
           __cil_tmp37 = __cil_tmp36->gen;
 #line 424
           __cil_tmp38 = (int )__cil_tmp37;
 #line 424
           if (__cil_tmp38 == 2) {
 #line 424
             goto case_2;
           } else
 #line 413
           if (0) {
             case_6: 
 #line 415
             i = 0;
 #line 415
             goto ldv_37682;
             ldv_37681: 
             {
 #line 416
             __cil_tmp39 = i + 131072;
 #line 416
             __cil_tmp40 = __cil_tmp39 * 8;
 #line 416
             __cil_tmp41 = (u32 )__cil_tmp40;
 #line 416
             __cil_tmp42 = dev_priv->saveFENCE[i];
 #line 416
             i915_write64(dev_priv, __cil_tmp41, __cil_tmp42);
 #line 415
             i = i + 1;
             }
             ldv_37682: ;
 #line 415
             if (i <= 15) {
 #line 416
               goto ldv_37681;
             } else {
 #line 418
               goto ldv_37683;
             }
             ldv_37683: ;
 #line 417
             goto ldv_37684;
             case_5: ;
             case_4: 
 #line 420
             i = 0;
 #line 420
             goto ldv_37688;
             ldv_37687: 
             {
 #line 421
             __cil_tmp43 = i + 1536;
 #line 421
             __cil_tmp44 = __cil_tmp43 * 8;
 #line 421
             __cil_tmp45 = (u32 )__cil_tmp44;
 #line 421
             __cil_tmp46 = dev_priv->saveFENCE[i];
 #line 421
             i915_write64(dev_priv, __cil_tmp45, __cil_tmp46);
 #line 420
             i = i + 1;
             }
             ldv_37688: ;
 #line 420
             if (i <= 15) {
 #line 421
               goto ldv_37687;
             } else {
 #line 423
               goto ldv_37689;
             }
             ldv_37689: ;
 #line 422
             goto ldv_37684;
             case_3: ;
             case_2: ;
             {
 #line 425
             __cil_tmp47 = dev->pci_device;
 #line 425
             if (__cil_tmp47 == 10098) {
 #line 425
               goto _L;
             } else {
               {
 #line 425
               __cil_tmp48 = dev->dev_private;
 #line 425
               __cil_tmp49 = (struct drm_i915_private *)__cil_tmp48;
 #line 425
               __cil_tmp50 = __cil_tmp49->info;
 #line 425
               __cil_tmp51 = (unsigned char *)__cil_tmp50;
 #line 425
               __cil_tmp52 = __cil_tmp51 + 1UL;
 #line 425
               __cil_tmp53 = *__cil_tmp52;
 #line 425
               __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 425
               if (__cil_tmp54 != 0U) {
 #line 425
                 goto _L;
               } else {
                 {
 #line 425
                 __cil_tmp55 = dev->dev_private;
 #line 425
                 __cil_tmp56 = (struct drm_i915_private *)__cil_tmp55;
 #line 425
                 __cil_tmp57 = __cil_tmp56->info;
 #line 425
                 __cil_tmp58 = (unsigned char *)__cil_tmp57;
 #line 425
                 __cil_tmp59 = __cil_tmp58 + 1UL;
 #line 425
                 __cil_tmp60 = *__cil_tmp59;
 #line 425
                 __cil_tmp61 = (unsigned int )__cil_tmp60;
 #line 425
                 if (__cil_tmp61 != 0U) {
                   _L: 
 #line 426
                   i = 0;
 #line 426
                   goto ldv_37693;
                   ldv_37692: 
                   {
 #line 427
                   __cil_tmp62 = i + 3072;
 #line 427
                   __cil_tmp63 = __cil_tmp62 * 4;
 #line 427
                   __cil_tmp64 = (u32 )__cil_tmp63;
 #line 427
                   __cil_tmp65 = dev_priv->saveFENCE[i + 8];
 #line 427
                   __cil_tmp66 = (u32 )__cil_tmp65;
 #line 427
                   i915_write32(dev_priv, __cil_tmp64, __cil_tmp66);
 #line 426
                   i = i + 1;
                   }
                   ldv_37693: ;
 #line 426
                   if (i <= 7) {
 #line 427
                     goto ldv_37692;
                   } else {
 #line 429
                     goto ldv_37694;
                   }
                   ldv_37694: ;
                 } else {
 
                 }
                 }
               }
               }
             }
             }
 #line 428
             i = 0;
 #line 428
             goto ldv_37696;
             ldv_37695: 
             {
 #line 429
             __cil_tmp67 = i + 2048;
 #line 429
             __cil_tmp68 = __cil_tmp67 * 4;
 #line 429
             __cil_tmp69 = (u32 )__cil_tmp68;
 #line 429
             __cil_tmp70 = dev_priv->saveFENCE[i];
 #line 429
             __cil_tmp71 = (u32 )__cil_tmp70;
 #line 429
             i915_write32(dev_priv, __cil_tmp69, __cil_tmp71);
 #line 428
             i = i + 1;
             }
             ldv_37696: ;
 #line 428
             if (i <= 7) {
 #line 429
               goto ldv_37695;
             } else {
 #line 431
               goto ldv_37697;
             }
             ldv_37697: ;
 #line 430
             goto ldv_37684;
           } else {
 
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_37684: ;
   {
 #line 434
   __cil_tmp72 = dev->dev_private;
 #line 434
   __cil_tmp73 = (struct drm_i915_private *)__cil_tmp72;
 #line 434
   __cil_tmp74 = __cil_tmp73->info;
 #line 434
   __cil_tmp75 = __cil_tmp74->gen;
 #line 434
   __cil_tmp76 = (unsigned char )__cil_tmp75;
 #line 434
   __cil_tmp77 = (unsigned int )__cil_tmp76;
 #line 434
   if (__cil_tmp77 == 5U) {
 #line 434
     goto _L___0;
   } else {
     {
 #line 434
     __cil_tmp78 = dev->dev_private;
 #line 434
     __cil_tmp79 = (struct drm_i915_private *)__cil_tmp78;
 #line 434
     __cil_tmp80 = __cil_tmp79->info;
 #line 434
     __cil_tmp81 = __cil_tmp80->gen;
 #line 434
     __cil_tmp82 = (unsigned char )__cil_tmp81;
 #line 434
     __cil_tmp83 = (unsigned int )__cil_tmp82;
 #line 434
     if (__cil_tmp83 == 6U) {
 #line 434
       goto _L___0;
     } else {
       {
 #line 434
       __cil_tmp84 = dev->dev_private;
 #line 434
       __cil_tmp85 = (struct drm_i915_private *)__cil_tmp84;
 #line 434
       __cil_tmp86 = __cil_tmp85->info;
 #line 434
       __cil_tmp87 = (unsigned char *)__cil_tmp86;
 #line 434
       __cil_tmp88 = __cil_tmp87 + 2UL;
 #line 434
       __cil_tmp89 = *__cil_tmp88;
 #line 434
       __cil_tmp90 = (unsigned int )__cil_tmp89;
 #line 434
       if (__cil_tmp90 != 0U) {
         _L___0: 
 #line 435
         dpll_a_reg = 811028;
 #line 436
         dpll_b_reg = 811032;
 #line 437
         fpa0_reg = 811072;
 #line 438
         fpb0_reg = 811080;
 #line 439
         fpa1_reg = 811076;
 #line 440
         fpb1_reg = 811084;
       } else {
 #line 442
         dpll_a_reg = 24596;
 #line 443
         dpll_b_reg = 24600;
 #line 444
         fpa0_reg = 24640;
 #line 445
         fpb0_reg = 24648;
 #line 446
         fpa1_reg = 24644;
 #line 447
         fpb1_reg = 24652;
       }
       }
     }
     }
   }
   }
   {
 #line 450
   __cil_tmp91 = dev->dev_private;
 #line 450
   __cil_tmp92 = (struct drm_i915_private *)__cil_tmp91;
 #line 450
   __cil_tmp93 = __cil_tmp92->info;
 #line 450
   __cil_tmp94 = __cil_tmp93->gen;
 #line 450
   __cil_tmp95 = (unsigned char )__cil_tmp94;
 #line 450
   __cil_tmp96 = (unsigned int )__cil_tmp95;
 #line 450
   if (__cil_tmp96 == 5U) {
     {
 #line 451
     __cil_tmp97 = dev_priv->savePCH_DREF_CONTROL;
 #line 451
     i915_write32(dev_priv, 811520U, __cil_tmp97);
 #line 452
     __cil_tmp98 = dev_priv->saveDISP_ARB_CTL;
 #line 452
     i915_write32(dev_priv, 282624U, __cil_tmp98);
     }
   } else {
     {
 #line 450
     __cil_tmp99 = dev->dev_private;
 #line 450
     __cil_tmp100 = (struct drm_i915_private *)__cil_tmp99;
 #line 450
     __cil_tmp101 = __cil_tmp100->info;
 #line 450
     __cil_tmp102 = __cil_tmp101->gen;
 #line 450
     __cil_tmp103 = (unsigned char )__cil_tmp102;
 #line 450
     __cil_tmp104 = (unsigned int )__cil_tmp103;
 #line 450
     if (__cil_tmp104 == 6U) {
       {
 #line 451
       __cil_tmp105 = dev_priv->savePCH_DREF_CONTROL;
 #line 451
       i915_write32(dev_priv, 811520U, __cil_tmp105);
 #line 452
       __cil_tmp106 = dev_priv->saveDISP_ARB_CTL;
 #line 452
       i915_write32(dev_priv, 282624U, __cil_tmp106);
       }
     } else {
       {
 #line 450
       __cil_tmp107 = dev->dev_private;
 #line 450
       __cil_tmp108 = (struct drm_i915_private *)__cil_tmp107;
 #line 450
       __cil_tmp109 = __cil_tmp108->info;
 #line 450
       __cil_tmp110 = (unsigned char *)__cil_tmp109;
 #line 450
       __cil_tmp111 = __cil_tmp110 + 2UL;
 #line 450
       __cil_tmp112 = *__cil_tmp111;
 #line 450
       __cil_tmp113 = (unsigned int )__cil_tmp112;
 #line 450
       if (__cil_tmp113 != 0U) {
         {
 #line 451
         __cil_tmp114 = dev_priv->savePCH_DREF_CONTROL;
 #line 451
         i915_write32(dev_priv, 811520U, __cil_tmp114);
 #line 452
         __cil_tmp115 = dev_priv->saveDISP_ARB_CTL;
 #line 452
         i915_write32(dev_priv, 282624U, __cil_tmp115);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 457
   __cil_tmp116 = dev_priv->saveDPLL_A;
 #line 457
   __cil_tmp117 = (int )__cil_tmp116;
 #line 457
   if (__cil_tmp117 < 0) {
     {
 #line 458
     __cil_tmp118 = (u32 )dpll_a_reg;
 #line 458
     __cil_tmp119 = dev_priv->saveDPLL_A;
 #line 458
     __cil_tmp120 = __cil_tmp119 & 2147483647U;
 #line 458
     i915_write32(dev_priv, __cil_tmp118, __cil_tmp120);
 #line 460
     __cil_tmp121 = (unsigned long )dpll_a_reg;
 #line 460
     __cil_tmp122 = dev_priv->regs;
 #line 460
     __cil_tmp123 = (void const volatile   *)__cil_tmp122;
 #line 460
     __cil_tmp124 = __cil_tmp123 + __cil_tmp121;
 #line 460
     readl(__cil_tmp124);
 #line 461
     __const_udelay(644250UL);
     }
   } else {
 
   }
   }
   {
 #line 463
   __cil_tmp125 = (u32 )fpa0_reg;
 #line 463
   __cil_tmp126 = dev_priv->saveFPA0;
 #line 463
   i915_write32(dev_priv, __cil_tmp125, __cil_tmp126);
 #line 464
   __cil_tmp127 = (u32 )fpa1_reg;
 #line 464
   __cil_tmp128 = dev_priv->saveFPA1;
 #line 464
   i915_write32(dev_priv, __cil_tmp127, __cil_tmp128);
 #line 466
   __cil_tmp129 = (u32 )dpll_a_reg;
 #line 466
   __cil_tmp130 = dev_priv->saveDPLL_A;
 #line 466
   i915_write32(dev_priv, __cil_tmp129, __cil_tmp130);
 #line 467
   __cil_tmp131 = (unsigned long )dpll_a_reg;
 #line 467
   __cil_tmp132 = dev_priv->regs;
 #line 467
   __cil_tmp133 = (void const volatile   *)__cil_tmp132;
 #line 467
   __cil_tmp134 = __cil_tmp133 + __cil_tmp131;
 #line 467
   readl(__cil_tmp134);
 #line 468
   __const_udelay(644250UL);
   }
   {
 #line 469
   __cil_tmp135 = dev->dev_private;
 #line 469
   __cil_tmp136 = (struct drm_i915_private *)__cil_tmp135;
 #line 469
   __cil_tmp137 = __cil_tmp136->info;
 #line 469
   __cil_tmp138 = __cil_tmp137->gen;
 #line 469
   __cil_tmp139 = (unsigned char )__cil_tmp138;
 #line 469
   __cil_tmp140 = (unsigned int )__cil_tmp139;
 #line 469
   if (__cil_tmp140 > 3U) {
     {
 #line 469
     __cil_tmp141 = dev->dev_private;
 #line 469
     __cil_tmp142 = (struct drm_i915_private *)__cil_tmp141;
 #line 469
     __cil_tmp143 = __cil_tmp142->info;
 #line 469
     __cil_tmp144 = __cil_tmp143->gen;
 #line 469
     __cil_tmp145 = (unsigned char )__cil_tmp144;
 #line 469
     __cil_tmp146 = (unsigned int )__cil_tmp145;
 #line 469
     if (__cil_tmp146 != 5U) {
       {
 #line 469
       __cil_tmp147 = dev->dev_private;
 #line 469
       __cil_tmp148 = (struct drm_i915_private *)__cil_tmp147;
 #line 469
       __cil_tmp149 = __cil_tmp148->info;
 #line 469
       __cil_tmp150 = __cil_tmp149->gen;
 #line 469
       __cil_tmp151 = (unsigned char )__cil_tmp150;
 #line 469
       __cil_tmp152 = (unsigned int )__cil_tmp151;
 #line 469
       if (__cil_tmp152 != 6U) {
         {
 #line 469
         __cil_tmp153 = dev->dev_private;
 #line 469
         __cil_tmp154 = (struct drm_i915_private *)__cil_tmp153;
 #line 469
         __cil_tmp155 = __cil_tmp154->info;
 #line 469
         __cil_tmp156 = (unsigned char *)__cil_tmp155;
 #line 469
         __cil_tmp157 = __cil_tmp156 + 2UL;
 #line 469
         __cil_tmp158 = *__cil_tmp157;
 #line 469
         __cil_tmp159 = (unsigned int )__cil_tmp158;
 #line 469
         if (__cil_tmp159 == 0U) {
           {
 #line 470
           __cil_tmp160 = dev_priv->saveDPLL_A_MD;
 #line 470
           i915_write32(dev_priv, 24604U, __cil_tmp160);
 #line 471
           __cil_tmp161 = dev_priv->regs;
 #line 471
           __cil_tmp162 = (void const volatile   *)__cil_tmp161;
 #line 471
           __cil_tmp163 = __cil_tmp162 + 24604U;
 #line 471
           readl(__cil_tmp163);
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 473
   __const_udelay(644250UL);
 #line 476
   __cil_tmp164 = dev_priv->saveHTOTAL_A;
 #line 476
   i915_write32(dev_priv, 393216U, __cil_tmp164);
 #line 477
   __cil_tmp165 = dev_priv->saveHBLANK_A;
 #line 477
   i915_write32(dev_priv, 393220U, __cil_tmp165);
 #line 478
   __cil_tmp166 = dev_priv->saveHSYNC_A;
 #line 478
   i915_write32(dev_priv, 393224U, __cil_tmp166);
 #line 479
   __cil_tmp167 = dev_priv->saveVTOTAL_A;
 #line 479
   i915_write32(dev_priv, 393228U, __cil_tmp167);
 #line 480
   __cil_tmp168 = dev_priv->saveVBLANK_A;
 #line 480
   i915_write32(dev_priv, 393232U, __cil_tmp168);
 #line 481
   __cil_tmp169 = dev_priv->saveVSYNC_A;
 #line 481
   i915_write32(dev_priv, 393236U, __cil_tmp169);
   }
   {
 #line 482
   __cil_tmp170 = dev->dev_private;
 #line 482
   __cil_tmp171 = (struct drm_i915_private *)__cil_tmp170;
 #line 482
   __cil_tmp172 = __cil_tmp171->info;
 #line 482
   __cil_tmp173 = __cil_tmp172->gen;
 #line 482
   __cil_tmp174 = (unsigned char )__cil_tmp173;
 #line 482
   __cil_tmp175 = (unsigned int )__cil_tmp174;
 #line 482
   if (__cil_tmp175 != 5U) {
     {
 #line 482
     __cil_tmp176 = dev->dev_private;
 #line 482
     __cil_tmp177 = (struct drm_i915_private *)__cil_tmp176;
 #line 482
     __cil_tmp178 = __cil_tmp177->info;
 #line 482
     __cil_tmp179 = __cil_tmp178->gen;
 #line 482
     __cil_tmp180 = (unsigned char )__cil_tmp179;
 #line 482
     __cil_tmp181 = (unsigned int )__cil_tmp180;
 #line 482
     if (__cil_tmp181 != 6U) {
       {
 #line 482
       __cil_tmp182 = dev->dev_private;
 #line 482
       __cil_tmp183 = (struct drm_i915_private *)__cil_tmp182;
 #line 482
       __cil_tmp184 = __cil_tmp183->info;
 #line 482
       __cil_tmp185 = (unsigned char *)__cil_tmp184;
 #line 482
       __cil_tmp186 = __cil_tmp185 + 2UL;
 #line 482
       __cil_tmp187 = *__cil_tmp186;
 #line 482
       __cil_tmp188 = (unsigned int )__cil_tmp187;
 #line 482
       if (__cil_tmp188 == 0U) {
         {
 #line 483
         __cil_tmp189 = dev_priv->saveBCLRPAT_A;
 #line 483
         i915_write32(dev_priv, 393248U, __cil_tmp189);
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 485
   __cil_tmp190 = dev->dev_private;
 #line 485
   __cil_tmp191 = (struct drm_i915_private *)__cil_tmp190;
 #line 485
   __cil_tmp192 = __cil_tmp191->info;
 #line 485
   __cil_tmp193 = __cil_tmp192->gen;
 #line 485
   __cil_tmp194 = (unsigned char )__cil_tmp193;
 #line 485
   __cil_tmp195 = (unsigned int )__cil_tmp194;
 #line 485
   if (__cil_tmp195 == 5U) {
 #line 485
     goto _L___1;
   } else {
     {
 #line 485
     __cil_tmp196 = dev->dev_private;
 #line 485
     __cil_tmp197 = (struct drm_i915_private *)__cil_tmp196;
 #line 485
     __cil_tmp198 = __cil_tmp197->info;
 #line 485
     __cil_tmp199 = __cil_tmp198->gen;
 #line 485
     __cil_tmp200 = (unsigned char )__cil_tmp199;
 #line 485
     __cil_tmp201 = (unsigned int )__cil_tmp200;
 #line 485
     if (__cil_tmp201 == 6U) {
 #line 485
       goto _L___1;
     } else {
       {
 #line 485
       __cil_tmp202 = dev->dev_private;
 #line 485
       __cil_tmp203 = (struct drm_i915_private *)__cil_tmp202;
 #line 485
       __cil_tmp204 = __cil_tmp203->info;
 #line 485
       __cil_tmp205 = (unsigned char *)__cil_tmp204;
 #line 485
       __cil_tmp206 = __cil_tmp205 + 2UL;
 #line 485
       __cil_tmp207 = *__cil_tmp206;
 #line 485
       __cil_tmp208 = (unsigned int )__cil_tmp207;
 #line 485
       if (__cil_tmp208 != 0U) {
         _L___1: 
         {
 #line 486
         __cil_tmp209 = dev_priv->savePIPEA_DATA_M1;
 #line 486
         i915_write32(dev_priv, 393264U, __cil_tmp209);
 #line 487
         __cil_tmp210 = dev_priv->savePIPEA_DATA_N1;
 #line 487
         i915_write32(dev_priv, 393268U, __cil_tmp210);
 #line 488
         __cil_tmp211 = dev_priv->savePIPEA_LINK_M1;
 #line 488
         i915_write32(dev_priv, 393280U, __cil_tmp211);
 #line 489
         __cil_tmp212 = dev_priv->savePIPEA_LINK_N1;
 #line 489
         i915_write32(dev_priv, 393284U, __cil_tmp212);
 #line 491
         __cil_tmp213 = dev_priv->saveFDI_RXA_CTL;
 #line 491
         i915_write32(dev_priv, 983052U, __cil_tmp213);
 #line 492
         __cil_tmp214 = dev_priv->saveFDI_TXA_CTL;
 #line 492
         i915_write32(dev_priv, 393472U, __cil_tmp214);
 #line 494
         __cil_tmp215 = dev_priv->savePFA_CTL_1;
 #line 494
         i915_write32(dev_priv, 426112U, __cil_tmp215);
 #line 495
         __cil_tmp216 = dev_priv->savePFA_WIN_SZ;
 #line 495
         i915_write32(dev_priv, 426100U, __cil_tmp216);
 #line 496
         __cil_tmp217 = dev_priv->savePFA_WIN_POS;
 #line 496
         i915_write32(dev_priv, 426096U, __cil_tmp217);
 #line 498
         __cil_tmp218 = dev_priv->saveTRANSACONF;
 #line 498
         i915_write32(dev_priv, 983048U, __cil_tmp218);
 #line 499
         __cil_tmp219 = dev_priv->saveTRANS_HTOTAL_A;
 #line 499
         i915_write32(dev_priv, 917504U, __cil_tmp219);
 #line 500
         __cil_tmp220 = dev_priv->saveTRANS_HBLANK_A;
 #line 500
         i915_write32(dev_priv, 917508U, __cil_tmp220);
 #line 501
         __cil_tmp221 = dev_priv->saveTRANS_HSYNC_A;
 #line 501
         i915_write32(dev_priv, 917512U, __cil_tmp221);
 #line 502
         __cil_tmp222 = dev_priv->saveTRANS_VTOTAL_A;
 #line 502
         i915_write32(dev_priv, 917516U, __cil_tmp222);
 #line 503
         __cil_tmp223 = dev_priv->saveTRANS_VBLANK_A;
 #line 503
         i915_write32(dev_priv, 917520U, __cil_tmp223);
 #line 504
         __cil_tmp224 = dev_priv->saveTRANS_VSYNC_A;
 #line 504
         i915_write32(dev_priv, 917524U, __cil_tmp224);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 508
   __cil_tmp225 = dev_priv->saveDSPASIZE;
 #line 508
   i915_write32(dev_priv, 459152U, __cil_tmp225);
 #line 509
   __cil_tmp226 = dev_priv->saveDSPAPOS;
 #line 509
   i915_write32(dev_priv, 459148U, __cil_tmp226);
 #line 510
   __cil_tmp227 = dev_priv->savePIPEASRC;
 #line 510
   i915_write32(dev_priv, 393244U, __cil_tmp227);
 #line 511
   __cil_tmp228 = dev_priv->saveDSPAADDR;
 #line 511
   i915_write32(dev_priv, 459140U, __cil_tmp228);
 #line 512
   __cil_tmp229 = dev_priv->saveDSPASTRIDE;
 #line 512
   i915_write32(dev_priv, 459144U, __cil_tmp229);
   }
   {
 #line 513
   __cil_tmp230 = dev->dev_private;
 #line 513
   __cil_tmp231 = (struct drm_i915_private *)__cil_tmp230;
 #line 513
   __cil_tmp232 = __cil_tmp231->info;
 #line 513
   __cil_tmp233 = __cil_tmp232->gen;
 #line 513
   __cil_tmp234 = (unsigned char )__cil_tmp233;
 #line 513
   __cil_tmp235 = (unsigned int )__cil_tmp234;
 #line 513
   if (__cil_tmp235 > 3U) {
     {
 #line 514
     __cil_tmp236 = dev_priv->saveDSPASURF;
 #line 514
     i915_write32(dev_priv, 459164U, __cil_tmp236);
 #line 515
     __cil_tmp237 = dev_priv->saveDSPATILEOFF;
 #line 515
     i915_write32(dev_priv, 459172U, __cil_tmp237);
     }
   } else {
 
   }
   }
   {
 #line 518
   __cil_tmp238 = dev_priv->savePIPEACONF;
 #line 518
   i915_write32(dev_priv, 458760U, __cil_tmp238);
 #line 520
   __cil_tmp239 = (enum pipe )0;
 #line 520
   i915_restore_palette(dev, __cil_tmp239);
 #line 522
   __cil_tmp240 = dev_priv->saveDSPACNTR;
 #line 522
   i915_write32(dev_priv, 459136U, __cil_tmp240);
 #line 523
   tmp___0 = i915_read32(dev_priv, 459140U);
 #line 523
   i915_write32(dev_priv, 459140U, tmp___0);
   }
   {
 #line 526
   __cil_tmp241 = dev_priv->saveDPLL_B;
 #line 526
   __cil_tmp242 = (int )__cil_tmp241;
 #line 526
   if (__cil_tmp242 < 0) {
     {
 #line 527
     __cil_tmp243 = (u32 )dpll_b_reg;
 #line 527
     __cil_tmp244 = dev_priv->saveDPLL_B;
 #line 527
     __cil_tmp245 = __cil_tmp244 & 2147483647U;
 #line 527
     i915_write32(dev_priv, __cil_tmp243, __cil_tmp245);
 #line 529
     __cil_tmp246 = (unsigned long )dpll_b_reg;
 #line 529
     __cil_tmp247 = dev_priv->regs;
 #line 529
     __cil_tmp248 = (void const volatile   *)__cil_tmp247;
 #line 529
     __cil_tmp249 = __cil_tmp248 + __cil_tmp246;
 #line 529
     readl(__cil_tmp249);
 #line 530
     __const_udelay(644250UL);
     }
   } else {
 
   }
   }
   {
 #line 532
   __cil_tmp250 = (u32 )fpb0_reg;
 #line 532
   __cil_tmp251 = dev_priv->saveFPB0;
 #line 532
   i915_write32(dev_priv, __cil_tmp250, __cil_tmp251);
 #line 533
   __cil_tmp252 = (u32 )fpb1_reg;
 #line 533
   __cil_tmp253 = dev_priv->saveFPB1;
 #line 533
   i915_write32(dev_priv, __cil_tmp252, __cil_tmp253);
 #line 535
   __cil_tmp254 = (u32 )dpll_b_reg;
 #line 535
   __cil_tmp255 = dev_priv->saveDPLL_B;
 #line 535
   i915_write32(dev_priv, __cil_tmp254, __cil_tmp255);
 #line 536
   __cil_tmp256 = (unsigned long )dpll_b_reg;
 #line 536
   __cil_tmp257 = dev_priv->regs;
 #line 536
   __cil_tmp258 = (void const volatile   *)__cil_tmp257;
 #line 536
   __cil_tmp259 = __cil_tmp258 + __cil_tmp256;
 #line 536
   readl(__cil_tmp259);
 #line 537
   __const_udelay(644250UL);
   }
   {
 #line 538
   __cil_tmp260 = dev->dev_private;
 #line 538
   __cil_tmp261 = (struct drm_i915_private *)__cil_tmp260;
 #line 538
   __cil_tmp262 = __cil_tmp261->info;
 #line 538
   __cil_tmp263 = __cil_tmp262->gen;
 #line 538
   __cil_tmp264 = (unsigned char )__cil_tmp263;
 #line 538
   __cil_tmp265 = (unsigned int )__cil_tmp264;
 #line 538
   if (__cil_tmp265 > 3U) {
     {
 #line 538
     __cil_tmp266 = dev->dev_private;
 #line 538
     __cil_tmp267 = (struct drm_i915_private *)__cil_tmp266;
 #line 538
     __cil_tmp268 = __cil_tmp267->info;
 #line 538
     __cil_tmp269 = __cil_tmp268->gen;
 #line 538
     __cil_tmp270 = (unsigned char )__cil_tmp269;
 #line 538
     __cil_tmp271 = (unsigned int )__cil_tmp270;
 #line 538
     if (__cil_tmp271 != 5U) {
       {
 #line 538
       __cil_tmp272 = dev->dev_private;
 #line 538
       __cil_tmp273 = (struct drm_i915_private *)__cil_tmp272;
 #line 538
       __cil_tmp274 = __cil_tmp273->info;
 #line 538
       __cil_tmp275 = __cil_tmp274->gen;
 #line 538
       __cil_tmp276 = (unsigned char )__cil_tmp275;
 #line 538
       __cil_tmp277 = (unsigned int )__cil_tmp276;
 #line 538
       if (__cil_tmp277 != 6U) {
         {
 #line 538
         __cil_tmp278 = dev->dev_private;
 #line 538
         __cil_tmp279 = (struct drm_i915_private *)__cil_tmp278;
 #line 538
         __cil_tmp280 = __cil_tmp279->info;
 #line 538
         __cil_tmp281 = (unsigned char *)__cil_tmp280;
 #line 538
         __cil_tmp282 = __cil_tmp281 + 2UL;
 #line 538
         __cil_tmp283 = *__cil_tmp282;
 #line 538
         __cil_tmp284 = (unsigned int )__cil_tmp283;
 #line 538
         if (__cil_tmp284 == 0U) {
           {
 #line 539
           __cil_tmp285 = dev_priv->saveDPLL_B_MD;
 #line 539
           i915_write32(dev_priv, 24608U, __cil_tmp285);
 #line 540
           __cil_tmp286 = dev_priv->regs;
 #line 540
           __cil_tmp287 = (void const volatile   *)__cil_tmp286;
 #line 540
           __cil_tmp288 = __cil_tmp287 + 24608U;
 #line 540
           readl(__cil_tmp288);
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 542
   __const_udelay(644250UL);
 #line 545
   __cil_tmp289 = dev_priv->saveHTOTAL_B;
 #line 545
   i915_write32(dev_priv, 397312U, __cil_tmp289);
 #line 546
   __cil_tmp290 = dev_priv->saveHBLANK_B;
 #line 546
   i915_write32(dev_priv, 397316U, __cil_tmp290);
 #line 547
   __cil_tmp291 = dev_priv->saveHSYNC_B;
 #line 547
   i915_write32(dev_priv, 397320U, __cil_tmp291);
 #line 548
   __cil_tmp292 = dev_priv->saveVTOTAL_B;
 #line 548
   i915_write32(dev_priv, 397324U, __cil_tmp292);
 #line 549
   __cil_tmp293 = dev_priv->saveVBLANK_B;
 #line 549
   i915_write32(dev_priv, 397328U, __cil_tmp293);
 #line 550
   __cil_tmp294 = dev_priv->saveVSYNC_B;
 #line 550
   i915_write32(dev_priv, 397332U, __cil_tmp294);
   }
   {
 #line 551
   __cil_tmp295 = dev->dev_private;
 #line 551
   __cil_tmp296 = (struct drm_i915_private *)__cil_tmp295;
 #line 551
   __cil_tmp297 = __cil_tmp296->info;
 #line 551
   __cil_tmp298 = __cil_tmp297->gen;
 #line 551
   __cil_tmp299 = (unsigned char )__cil_tmp298;
 #line 551
   __cil_tmp300 = (unsigned int )__cil_tmp299;
 #line 551
   if (__cil_tmp300 != 5U) {
     {
 #line 551
     __cil_tmp301 = dev->dev_private;
 #line 551
     __cil_tmp302 = (struct drm_i915_private *)__cil_tmp301;
 #line 551
     __cil_tmp303 = __cil_tmp302->info;
 #line 551
     __cil_tmp304 = __cil_tmp303->gen;
 #line 551
     __cil_tmp305 = (unsigned char )__cil_tmp304;
 #line 551
     __cil_tmp306 = (unsigned int )__cil_tmp305;
 #line 551
     if (__cil_tmp306 != 6U) {
       {
 #line 551
       __cil_tmp307 = dev->dev_private;
 #line 551
       __cil_tmp308 = (struct drm_i915_private *)__cil_tmp307;
 #line 551
       __cil_tmp309 = __cil_tmp308->info;
 #line 551
       __cil_tmp310 = (unsigned char *)__cil_tmp309;
 #line 551
       __cil_tmp311 = __cil_tmp310 + 2UL;
 #line 551
       __cil_tmp312 = *__cil_tmp311;
 #line 551
       __cil_tmp313 = (unsigned int )__cil_tmp312;
 #line 551
       if (__cil_tmp313 == 0U) {
         {
 #line 552
         __cil_tmp314 = dev_priv->saveBCLRPAT_B;
 #line 552
         i915_write32(dev_priv, 397344U, __cil_tmp314);
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 554
   __cil_tmp315 = dev->dev_private;
 #line 554
   __cil_tmp316 = (struct drm_i915_private *)__cil_tmp315;
 #line 554
   __cil_tmp317 = __cil_tmp316->info;
 #line 554
   __cil_tmp318 = __cil_tmp317->gen;
 #line 554
   __cil_tmp319 = (unsigned char )__cil_tmp318;
 #line 554
   __cil_tmp320 = (unsigned int )__cil_tmp319;
 #line 554
   if (__cil_tmp320 == 5U) {
 #line 554
     goto _L___2;
   } else {
     {
 #line 554
     __cil_tmp321 = dev->dev_private;
 #line 554
     __cil_tmp322 = (struct drm_i915_private *)__cil_tmp321;
 #line 554
     __cil_tmp323 = __cil_tmp322->info;
 #line 554
     __cil_tmp324 = __cil_tmp323->gen;
 #line 554
     __cil_tmp325 = (unsigned char )__cil_tmp324;
 #line 554
     __cil_tmp326 = (unsigned int )__cil_tmp325;
 #line 554
     if (__cil_tmp326 == 6U) {
 #line 554
       goto _L___2;
     } else {
       {
 #line 554
       __cil_tmp327 = dev->dev_private;
 #line 554
       __cil_tmp328 = (struct drm_i915_private *)__cil_tmp327;
 #line 554
       __cil_tmp329 = __cil_tmp328->info;
 #line 554
       __cil_tmp330 = (unsigned char *)__cil_tmp329;
 #line 554
       __cil_tmp331 = __cil_tmp330 + 2UL;
 #line 554
       __cil_tmp332 = *__cil_tmp331;
 #line 554
       __cil_tmp333 = (unsigned int )__cil_tmp332;
 #line 554
       if (__cil_tmp333 != 0U) {
         _L___2: 
         {
 #line 555
         __cil_tmp334 = dev_priv->savePIPEB_DATA_M1;
 #line 555
         i915_write32(dev_priv, 397360U, __cil_tmp334);
 #line 556
         __cil_tmp335 = dev_priv->savePIPEB_DATA_N1;
 #line 556
         i915_write32(dev_priv, 397364U, __cil_tmp335);
 #line 557
         __cil_tmp336 = dev_priv->savePIPEB_LINK_M1;
 #line 557
         i915_write32(dev_priv, 397376U, __cil_tmp336);
 #line 558
         __cil_tmp337 = dev_priv->savePIPEB_LINK_N1;
 #line 558
         i915_write32(dev_priv, 397380U, __cil_tmp337);
 #line 560
         __cil_tmp338 = dev_priv->saveFDI_RXB_CTL;
 #line 560
         i915_write32(dev_priv, 987148U, __cil_tmp338);
 #line 561
         __cil_tmp339 = dev_priv->saveFDI_TXB_CTL;
 #line 561
         i915_write32(dev_priv, 397568U, __cil_tmp339);
 #line 563
         __cil_tmp340 = dev_priv->savePFB_CTL_1;
 #line 563
         i915_write32(dev_priv, 428160U, __cil_tmp340);
 #line 564
         __cil_tmp341 = dev_priv->savePFB_WIN_SZ;
 #line 564
         i915_write32(dev_priv, 428148U, __cil_tmp341);
 #line 565
         __cil_tmp342 = dev_priv->savePFB_WIN_POS;
 #line 565
         i915_write32(dev_priv, 428144U, __cil_tmp342);
 #line 567
         __cil_tmp343 = dev_priv->saveTRANSBCONF;
 #line 567
         i915_write32(dev_priv, 987144U, __cil_tmp343);
 #line 568
         __cil_tmp344 = dev_priv->saveTRANS_HTOTAL_B;
 #line 568
         i915_write32(dev_priv, 921600U, __cil_tmp344);
 #line 569
         __cil_tmp345 = dev_priv->saveTRANS_HBLANK_B;
 #line 569
         i915_write32(dev_priv, 921604U, __cil_tmp345);
 #line 570
         __cil_tmp346 = dev_priv->saveTRANS_HSYNC_B;
 #line 570
         i915_write32(dev_priv, 921608U, __cil_tmp346);
 #line 571
         __cil_tmp347 = dev_priv->saveTRANS_VTOTAL_B;
 #line 571
         i915_write32(dev_priv, 921612U, __cil_tmp347);
 #line 572
         __cil_tmp348 = dev_priv->saveTRANS_VBLANK_B;
 #line 572
         i915_write32(dev_priv, 921616U, __cil_tmp348);
 #line 573
         __cil_tmp349 = dev_priv->saveTRANS_VSYNC_B;
 #line 573
         i915_write32(dev_priv, 921620U, __cil_tmp349);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 577
   __cil_tmp350 = dev_priv->saveDSPBSIZE;
 #line 577
   i915_write32(dev_priv, 463248U, __cil_tmp350);
 #line 578
   __cil_tmp351 = dev_priv->saveDSPBPOS;
 #line 578
   i915_write32(dev_priv, 463244U, __cil_tmp351);
 #line 579
   __cil_tmp352 = dev_priv->savePIPEBSRC;
 #line 579
   i915_write32(dev_priv, 397340U, __cil_tmp352);
 #line 580
   __cil_tmp353 = dev_priv->saveDSPBADDR;
 #line 580
   i915_write32(dev_priv, 463236U, __cil_tmp353);
 #line 581
   __cil_tmp354 = dev_priv->saveDSPBSTRIDE;
 #line 581
   i915_write32(dev_priv, 463240U, __cil_tmp354);
   }
   {
 #line 582
   __cil_tmp355 = dev->dev_private;
 #line 582
   __cil_tmp356 = (struct drm_i915_private *)__cil_tmp355;
 #line 582
   __cil_tmp357 = __cil_tmp356->info;
 #line 582
   __cil_tmp358 = __cil_tmp357->gen;
 #line 582
   __cil_tmp359 = (unsigned char )__cil_tmp358;
 #line 582
   __cil_tmp360 = (unsigned int )__cil_tmp359;
 #line 582
   if (__cil_tmp360 > 3U) {
     {
 #line 583
     __cil_tmp361 = dev_priv->saveDSPBSURF;
 #line 583
     i915_write32(dev_priv, 463260U, __cil_tmp361);
 #line 584
     __cil_tmp362 = dev_priv->saveDSPBTILEOFF;
 #line 584
     i915_write32(dev_priv, 463268U, __cil_tmp362);
     }
   } else {
 
   }
   }
   {
 #line 587
   __cil_tmp363 = dev_priv->savePIPEBCONF;
 #line 587
   i915_write32(dev_priv, 462856U, __cil_tmp363);
 #line 589
   __cil_tmp364 = (enum pipe )1;
 #line 589
   i915_restore_palette(dev, __cil_tmp364);
 #line 591
   __cil_tmp365 = dev_priv->saveDSPBCNTR;
 #line 591
   i915_write32(dev_priv, 463232U, __cil_tmp365);
 #line 592
   tmp___1 = i915_read32(dev_priv, 463236U);
 #line 592
   i915_write32(dev_priv, 463236U, tmp___1);
 #line 595
   __cil_tmp366 = dev_priv->saveCURAPOS;
 #line 595
   i915_write32(dev_priv, 458888U, __cil_tmp366);
 #line 596
   __cil_tmp367 = dev_priv->saveCURACNTR;
 #line 596
   i915_write32(dev_priv, 458880U, __cil_tmp367);
 #line 597
   __cil_tmp368 = dev_priv->saveCURABASE;
 #line 597
   i915_write32(dev_priv, 458884U, __cil_tmp368);
 #line 598
   __cil_tmp369 = dev_priv->saveCURBPOS;
 #line 598
   i915_write32(dev_priv, 458952U, __cil_tmp369);
 #line 599
   __cil_tmp370 = dev_priv->saveCURBCNTR;
 #line 599
   i915_write32(dev_priv, 458944U, __cil_tmp370);
 #line 600
   __cil_tmp371 = dev_priv->saveCURBBASE;
 #line 600
   i915_write32(dev_priv, 458948U, __cil_tmp371);
   }
   {
 #line 601
   __cil_tmp372 = dev->dev_private;
 #line 601
   __cil_tmp373 = (struct drm_i915_private *)__cil_tmp372;
 #line 601
   __cil_tmp374 = __cil_tmp373->info;
 #line 601
   __cil_tmp375 = __cil_tmp374->gen;
 #line 601
   __cil_tmp376 = (unsigned char )__cil_tmp375;
 #line 601
   __cil_tmp377 = (unsigned int )__cil_tmp376;
 #line 601
   if (__cil_tmp377 == 2U) {
     {
 #line 602
     __cil_tmp378 = dev_priv->saveCURSIZE;
 #line 602
     i915_write32(dev_priv, 458912U, __cil_tmp378);
     }
   } else {
 
   }
   }
 #line 604
   return;
 }
 }
 #line 607 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_save_display(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp3 ;
   void *__cil_tmp4 ;
   struct drm_i915_private *__cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   void *__cil_tmp10 ;
   struct drm_i915_private *__cil_tmp11 ;
   struct intel_device_info  const  *__cil_tmp12 ;
   u8 __cil_tmp13 ;
   unsigned char __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   void *__cil_tmp16 ;
   struct drm_i915_private *__cil_tmp17 ;
   struct intel_device_info  const  *__cil_tmp18 ;
   unsigned char *__cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   u8 __cil_tmp26 ;
   unsigned char __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   void *__cil_tmp29 ;
   struct drm_i915_private *__cil_tmp30 ;
   struct intel_device_info  const  *__cil_tmp31 ;
   u8 __cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   void *__cil_tmp35 ;
   struct drm_i915_private *__cil_tmp36 ;
   struct intel_device_info  const  *__cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   void *__cil_tmp42 ;
   struct drm_i915_private *__cil_tmp43 ;
   struct intel_device_info  const  *__cil_tmp44 ;
   u8 __cil_tmp45 ;
   unsigned char __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   void *__cil_tmp48 ;
   struct drm_i915_private *__cil_tmp49 ;
   struct intel_device_info  const  *__cil_tmp50 ;
   unsigned char *__cil_tmp51 ;
   unsigned char *__cil_tmp52 ;
   unsigned char __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   void *__cil_tmp58 ;
   struct drm_i915_private *__cil_tmp59 ;
   struct intel_device_info  const  *__cil_tmp60 ;
   u8 __cil_tmp61 ;
   unsigned char __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   void *__cil_tmp64 ;
   struct drm_i915_private *__cil_tmp65 ;
   struct intel_device_info  const  *__cil_tmp66 ;
   u8 __cil_tmp67 ;
   unsigned char __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   void *__cil_tmp70 ;
   struct drm_i915_private *__cil_tmp71 ;
   struct intel_device_info  const  *__cil_tmp72 ;
   unsigned char *__cil_tmp73 ;
   unsigned char *__cil_tmp74 ;
   unsigned char __cil_tmp75 ;
   unsigned int __cil_tmp76 ;
   void *__cil_tmp77 ;
   struct drm_i915_private *__cil_tmp78 ;
   struct intel_device_info  const  *__cil_tmp79 ;
   u8 __cil_tmp80 ;
   unsigned char __cil_tmp81 ;
   unsigned int __cil_tmp82 ;
   void *__cil_tmp83 ;
   struct drm_i915_private *__cil_tmp84 ;
   struct intel_device_info  const  *__cil_tmp85 ;
   u8 __cil_tmp86 ;
   unsigned char __cil_tmp87 ;
   unsigned int __cil_tmp88 ;
   void *__cil_tmp89 ;
   struct drm_i915_private *__cil_tmp90 ;
   struct intel_device_info  const  *__cil_tmp91 ;
   unsigned char *__cil_tmp92 ;
   unsigned char *__cil_tmp93 ;
   unsigned char __cil_tmp94 ;
   unsigned int __cil_tmp95 ;
   void *__cil_tmp96 ;
   struct drm_i915_private *__cil_tmp97 ;
   struct intel_device_info  const  *__cil_tmp98 ;
   unsigned char *__cil_tmp99 ;
   unsigned char *__cil_tmp100 ;
   unsigned char __cil_tmp101 ;
   unsigned int __cil_tmp102 ;
   void *__cil_tmp103 ;
   struct drm_i915_private *__cil_tmp104 ;
   struct intel_device_info  const  *__cil_tmp105 ;
   u8 __cil_tmp106 ;
   unsigned char __cil_tmp107 ;
   unsigned int __cil_tmp108 ;
   void *__cil_tmp109 ;
   struct drm_i915_private *__cil_tmp110 ;
   struct intel_device_info  const  *__cil_tmp111 ;
   unsigned char *__cil_tmp112 ;
   unsigned char *__cil_tmp113 ;
   unsigned char __cil_tmp114 ;
   unsigned int __cil_tmp115 ;
   void *__cil_tmp116 ;
   struct drm_i915_private *__cil_tmp117 ;
   struct intel_device_info  const  *__cil_tmp118 ;
   u8 __cil_tmp119 ;
   unsigned char __cil_tmp120 ;
   unsigned int __cil_tmp121 ;
   void *__cil_tmp122 ;
   struct drm_i915_private *__cil_tmp123 ;
   struct intel_device_info  const  *__cil_tmp124 ;
   u8 __cil_tmp125 ;
   unsigned char __cil_tmp126 ;
   unsigned int __cil_tmp127 ;
   void *__cil_tmp128 ;
   struct drm_i915_private *__cil_tmp129 ;
   struct intel_device_info  const  *__cil_tmp130 ;
   unsigned char *__cil_tmp131 ;
   unsigned char *__cil_tmp132 ;
   unsigned char __cil_tmp133 ;
   unsigned int __cil_tmp134 ;
   int __cil_tmp135 ;
   void *__cil_tmp136 ;
   struct drm_i915_private *__cil_tmp137 ;
   struct intel_device_info  const  *__cil_tmp138 ;
   u8 __cil_tmp139 ;
   unsigned char __cil_tmp140 ;
   unsigned int __cil_tmp141 ;
   void *__cil_tmp142 ;
   struct drm_i915_private *__cil_tmp143 ;
   struct intel_device_info  const  *__cil_tmp144 ;
   u8 __cil_tmp145 ;
   unsigned char __cil_tmp146 ;
   unsigned int __cil_tmp147 ;
   void *__cil_tmp148 ;
   struct drm_i915_private *__cil_tmp149 ;
   struct intel_device_info  const  *__cil_tmp150 ;
   unsigned char *__cil_tmp151 ;
   unsigned char *__cil_tmp152 ;
   unsigned char __cil_tmp153 ;
   unsigned int __cil_tmp154 ;
 
   {
   {
 #line 609
   __cil_tmp3 = dev->dev_private;
 #line 609
   dev_priv = (struct drm_i915_private *)__cil_tmp3;
 #line 612
   dev_priv->saveDSPARB = i915_read32(dev_priv, 458800U);
 #line 616
   i915_save_modeset_reg(dev);
   }
   {
 #line 619
   __cil_tmp4 = dev->dev_private;
 #line 619
   __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
 #line 619
   __cil_tmp6 = __cil_tmp5->info;
 #line 619
   __cil_tmp7 = __cil_tmp6->gen;
 #line 619
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 619
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 619
   if (__cil_tmp9 == 5U) {
     {
 #line 620
     dev_priv->saveADPA = i915_read32(dev_priv, 921856U);
     }
   } else {
     {
 #line 619
     __cil_tmp10 = dev->dev_private;
 #line 619
     __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
 #line 619
     __cil_tmp12 = __cil_tmp11->info;
 #line 619
     __cil_tmp13 = __cil_tmp12->gen;
 #line 619
     __cil_tmp14 = (unsigned char )__cil_tmp13;
 #line 619
     __cil_tmp15 = (unsigned int )__cil_tmp14;
 #line 619
     if (__cil_tmp15 == 6U) {
       {
 #line 620
       dev_priv->saveADPA = i915_read32(dev_priv, 921856U);
       }
     } else {
       {
 #line 619
       __cil_tmp16 = dev->dev_private;
 #line 619
       __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
 #line 619
       __cil_tmp18 = __cil_tmp17->info;
 #line 619
       __cil_tmp19 = (unsigned char *)__cil_tmp18;
 #line 619
       __cil_tmp20 = __cil_tmp19 + 2UL;
 #line 619
       __cil_tmp21 = *__cil_tmp20;
 #line 619
       __cil_tmp22 = (unsigned int )__cil_tmp21;
 #line 619
       if (__cil_tmp22 != 0U) {
         {
 #line 620
         dev_priv->saveADPA = i915_read32(dev_priv, 921856U);
         }
       } else {
         {
 #line 622
         dev_priv->saveADPA = i915_read32(dev_priv, 397568U);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 626
   __cil_tmp23 = dev->dev_private;
 #line 626
   __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 626
   __cil_tmp25 = __cil_tmp24->info;
 #line 626
   __cil_tmp26 = __cil_tmp25->gen;
 #line 626
   __cil_tmp27 = (unsigned char )__cil_tmp26;
 #line 626
   __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 626
   if (__cil_tmp28 == 5U) {
 #line 626
     goto _L;
   } else {
     {
 #line 626
     __cil_tmp29 = dev->dev_private;
 #line 626
     __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
 #line 626
     __cil_tmp31 = __cil_tmp30->info;
 #line 626
     __cil_tmp32 = __cil_tmp31->gen;
 #line 626
     __cil_tmp33 = (unsigned char )__cil_tmp32;
 #line 626
     __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 626
     if (__cil_tmp34 == 6U) {
 #line 626
       goto _L;
     } else {
       {
 #line 626
       __cil_tmp35 = dev->dev_private;
 #line 626
       __cil_tmp36 = (struct drm_i915_private *)__cil_tmp35;
 #line 626
       __cil_tmp37 = __cil_tmp36->info;
 #line 626
       __cil_tmp38 = (unsigned char *)__cil_tmp37;
 #line 626
       __cil_tmp39 = __cil_tmp38 + 2UL;
 #line 626
       __cil_tmp40 = *__cil_tmp39;
 #line 626
       __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 626
       if (__cil_tmp41 != 0U) {
         _L: 
         {
 #line 627
         dev_priv->savePP_CONTROL = i915_read32(dev_priv, 815620U);
 #line 628
         dev_priv->saveBLC_PWM_CTL = i915_read32(dev_priv, 819792U);
 #line 629
         dev_priv->saveBLC_PWM_CTL2 = i915_read32(dev_priv, 819796U);
 #line 630
         dev_priv->saveBLC_CPU_PWM_CTL = i915_read32(dev_priv, 295508U);
 #line 631
         dev_priv->saveBLC_CPU_PWM_CTL2 = i915_read32(dev_priv, 295504U);
 #line 632
         dev_priv->saveLVDS = i915_read32(dev_priv, 921984U);
         }
       } else {
         {
 #line 634
         dev_priv->savePP_CONTROL = i915_read32(dev_priv, 397828U);
 #line 635
         dev_priv->savePFIT_PGM_RATIOS = i915_read32(dev_priv, 397876U);
 #line 636
         dev_priv->saveBLC_PWM_CTL = i915_read32(dev_priv, 397908U);
 #line 637
         dev_priv->saveBLC_HIST_CTL = i915_read32(dev_priv, 397920U);
         }
         {
 #line 638
         __cil_tmp42 = dev->dev_private;
 #line 638
         __cil_tmp43 = (struct drm_i915_private *)__cil_tmp42;
 #line 638
         __cil_tmp44 = __cil_tmp43->info;
 #line 638
         __cil_tmp45 = __cil_tmp44->gen;
 #line 638
         __cil_tmp46 = (unsigned char )__cil_tmp45;
 #line 638
         __cil_tmp47 = (unsigned int )__cil_tmp46;
 #line 638
         if (__cil_tmp47 > 3U) {
           {
 #line 639
           dev_priv->saveBLC_PWM_CTL2 = i915_read32(dev_priv, 397904U);
           }
         } else {
 
         }
         }
         {
 #line 640
         __cil_tmp48 = dev->dev_private;
 #line 640
         __cil_tmp49 = (struct drm_i915_private *)__cil_tmp48;
 #line 640
         __cil_tmp50 = __cil_tmp49->info;
 #line 640
         __cil_tmp51 = (unsigned char *)__cil_tmp50;
 #line 640
         __cil_tmp52 = __cil_tmp51 + 1UL;
 #line 640
         __cil_tmp53 = *__cil_tmp52;
 #line 640
         __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 640
         if (__cil_tmp54 != 0U) {
           {
 #line 640
           __cil_tmp55 = dev->pci_device;
 #line 640
           if (__cil_tmp55 != 13687) {
             {
 #line 641
             dev_priv->saveLVDS = i915_read32(dev_priv, 397696U);
             }
           } else {
 
           }
           }
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
   {
 #line 644
   __cil_tmp56 = dev->pci_device;
 #line 644
   if (__cil_tmp56 != 13687) {
     {
 #line 644
     __cil_tmp57 = dev->pci_device;
 #line 644
     if (__cil_tmp57 != 9570) {
       {
 #line 644
       __cil_tmp58 = dev->dev_private;
 #line 644
       __cil_tmp59 = (struct drm_i915_private *)__cil_tmp58;
 #line 644
       __cil_tmp60 = __cil_tmp59->info;
 #line 644
       __cil_tmp61 = __cil_tmp60->gen;
 #line 644
       __cil_tmp62 = (unsigned char )__cil_tmp61;
 #line 644
       __cil_tmp63 = (unsigned int )__cil_tmp62;
 #line 644
       if (__cil_tmp63 != 5U) {
         {
 #line 644
         __cil_tmp64 = dev->dev_private;
 #line 644
         __cil_tmp65 = (struct drm_i915_private *)__cil_tmp64;
 #line 644
         __cil_tmp66 = __cil_tmp65->info;
 #line 644
         __cil_tmp67 = __cil_tmp66->gen;
 #line 644
         __cil_tmp68 = (unsigned char )__cil_tmp67;
 #line 644
         __cil_tmp69 = (unsigned int )__cil_tmp68;
 #line 644
         if (__cil_tmp69 != 6U) {
           {
 #line 644
           __cil_tmp70 = dev->dev_private;
 #line 644
           __cil_tmp71 = (struct drm_i915_private *)__cil_tmp70;
 #line 644
           __cil_tmp72 = __cil_tmp71->info;
 #line 644
           __cil_tmp73 = (unsigned char *)__cil_tmp72;
 #line 644
           __cil_tmp74 = __cil_tmp73 + 2UL;
 #line 644
           __cil_tmp75 = *__cil_tmp74;
 #line 644
           __cil_tmp76 = (unsigned int )__cil_tmp75;
 #line 644
           if (__cil_tmp76 == 0U) {
             {
 #line 645
             dev_priv->savePFIT_CONTROL = i915_read32(dev_priv, 397872U);
             }
           } else {
 
           }
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 647
   __cil_tmp77 = dev->dev_private;
 #line 647
   __cil_tmp78 = (struct drm_i915_private *)__cil_tmp77;
 #line 647
   __cil_tmp79 = __cil_tmp78->info;
 #line 647
   __cil_tmp80 = __cil_tmp79->gen;
 #line 647
   __cil_tmp81 = (unsigned char )__cil_tmp80;
 #line 647
   __cil_tmp82 = (unsigned int )__cil_tmp81;
 #line 647
   if (__cil_tmp82 == 5U) {
     {
 #line 648
     dev_priv->savePP_ON_DELAYS = i915_read32(dev_priv, 815624U);
 #line 649
     dev_priv->savePP_OFF_DELAYS = i915_read32(dev_priv, 815628U);
 #line 650
     dev_priv->savePP_DIVISOR = i915_read32(dev_priv, 815632U);
     }
   } else {
     {
 #line 647
     __cil_tmp83 = dev->dev_private;
 #line 647
     __cil_tmp84 = (struct drm_i915_private *)__cil_tmp83;
 #line 647
     __cil_tmp85 = __cil_tmp84->info;
 #line 647
     __cil_tmp86 = __cil_tmp85->gen;
 #line 647
     __cil_tmp87 = (unsigned char )__cil_tmp86;
 #line 647
     __cil_tmp88 = (unsigned int )__cil_tmp87;
 #line 647
     if (__cil_tmp88 == 6U) {
       {
 #line 648
       dev_priv->savePP_ON_DELAYS = i915_read32(dev_priv, 815624U);
 #line 649
       dev_priv->savePP_OFF_DELAYS = i915_read32(dev_priv, 815628U);
 #line 650
       dev_priv->savePP_DIVISOR = i915_read32(dev_priv, 815632U);
       }
     } else {
       {
 #line 647
       __cil_tmp89 = dev->dev_private;
 #line 647
       __cil_tmp90 = (struct drm_i915_private *)__cil_tmp89;
 #line 647
       __cil_tmp91 = __cil_tmp90->info;
 #line 647
       __cil_tmp92 = (unsigned char *)__cil_tmp91;
 #line 647
       __cil_tmp93 = __cil_tmp92 + 2UL;
 #line 647
       __cil_tmp94 = *__cil_tmp93;
 #line 647
       __cil_tmp95 = (unsigned int )__cil_tmp94;
 #line 647
       if (__cil_tmp95 != 0U) {
         {
 #line 648
         dev_priv->savePP_ON_DELAYS = i915_read32(dev_priv, 815624U);
 #line 649
         dev_priv->savePP_OFF_DELAYS = i915_read32(dev_priv, 815628U);
 #line 650
         dev_priv->savePP_DIVISOR = i915_read32(dev_priv, 815632U);
         }
       } else {
         {
 #line 652
         dev_priv->savePP_ON_DELAYS = i915_read32(dev_priv, 397832U);
 #line 653
         dev_priv->savePP_OFF_DELAYS = i915_read32(dev_priv, 397836U);
 #line 654
         dev_priv->savePP_DIVISOR = i915_read32(dev_priv, 397840U);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 658
   __cil_tmp96 = dev->dev_private;
 #line 658
   __cil_tmp97 = (struct drm_i915_private *)__cil_tmp96;
 #line 658
   __cil_tmp98 = __cil_tmp97->info;
 #line 658
   __cil_tmp99 = (unsigned char *)__cil_tmp98;
 #line 658
   __cil_tmp100 = __cil_tmp99 + 1UL;
 #line 658
   __cil_tmp101 = *__cil_tmp100;
 #line 658
   __cil_tmp102 = (unsigned int )__cil_tmp101;
 #line 658
   if (__cil_tmp102 != 0U) {
 #line 658
     goto _L___0;
   } else {
     {
 #line 658
     __cil_tmp103 = dev->dev_private;
 #line 658
     __cil_tmp104 = (struct drm_i915_private *)__cil_tmp103;
 #line 658
     __cil_tmp105 = __cil_tmp104->info;
 #line 658
     __cil_tmp106 = __cil_tmp105->gen;
 #line 658
     __cil_tmp107 = (unsigned char )__cil_tmp106;
 #line 658
     __cil_tmp108 = (unsigned int )__cil_tmp107;
 #line 658
     if (__cil_tmp108 == 5U) {
       _L___0: 
       {
 #line 659
       dev_priv->saveDP_B = i915_read32(dev_priv, 409856U);
 #line 660
       dev_priv->saveDP_C = i915_read32(dev_priv, 410112U);
 #line 661
       dev_priv->saveDP_D = i915_read32(dev_priv, 410368U);
 #line 662
       dev_priv->savePIPEA_GMCH_DATA_M = i915_read32(dev_priv, 458832U);
 #line 663
       dev_priv->savePIPEB_GMCH_DATA_M = i915_read32(dev_priv, 462928U);
 #line 664
       dev_priv->savePIPEA_GMCH_DATA_N = i915_read32(dev_priv, 458836U);
 #line 665
       dev_priv->savePIPEB_GMCH_DATA_N = i915_read32(dev_priv, 462932U);
 #line 666
       dev_priv->savePIPEA_DP_LINK_M = i915_read32(dev_priv, 458848U);
 #line 667
       dev_priv->savePIPEB_DP_LINK_M = i915_read32(dev_priv, 462944U);
 #line 668
       dev_priv->savePIPEA_DP_LINK_N = i915_read32(dev_priv, 458852U);
 #line 669
       dev_priv->savePIPEB_DP_LINK_N = i915_read32(dev_priv, 462948U);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 674
   __cil_tmp109 = dev->dev_private;
 #line 674
   __cil_tmp110 = (struct drm_i915_private *)__cil_tmp109;
 #line 674
   __cil_tmp111 = __cil_tmp110->info;
 #line 674
   __cil_tmp112 = (unsigned char *)__cil_tmp111;
 #line 674
   __cil_tmp113 = __cil_tmp112 + 2UL;
 #line 674
   __cil_tmp114 = *__cil_tmp113;
 #line 674
   __cil_tmp115 = (unsigned int )__cil_tmp114;
 #line 674
   if (__cil_tmp115 != 0U) {
     {
 #line 675
     __cil_tmp116 = dev->dev_private;
 #line 675
     __cil_tmp117 = (struct drm_i915_private *)__cil_tmp116;
 #line 675
     __cil_tmp118 = __cil_tmp117->info;
 #line 675
     __cil_tmp119 = __cil_tmp118->gen;
 #line 675
     __cil_tmp120 = (unsigned char )__cil_tmp119;
 #line 675
     __cil_tmp121 = (unsigned int )__cil_tmp120;
 #line 675
     if (__cil_tmp121 == 5U) {
       {
 #line 676
       dev_priv->saveDPFC_CB_BASE = i915_read32(dev_priv, 274944U);
       }
     } else {
       {
 #line 675
       __cil_tmp122 = dev->dev_private;
 #line 675
       __cil_tmp123 = (struct drm_i915_private *)__cil_tmp122;
 #line 675
       __cil_tmp124 = __cil_tmp123->info;
 #line 675
       __cil_tmp125 = __cil_tmp124->gen;
 #line 675
       __cil_tmp126 = (unsigned char )__cil_tmp125;
 #line 675
       __cil_tmp127 = (unsigned int )__cil_tmp126;
 #line 675
       if (__cil_tmp127 == 6U) {
         {
 #line 676
         dev_priv->saveDPFC_CB_BASE = i915_read32(dev_priv, 274944U);
         }
       } else {
         {
 #line 675
         __cil_tmp128 = dev->dev_private;
 #line 675
         __cil_tmp129 = (struct drm_i915_private *)__cil_tmp128;
 #line 675
         __cil_tmp130 = __cil_tmp129->info;
 #line 675
         __cil_tmp131 = (unsigned char *)__cil_tmp130;
 #line 675
         __cil_tmp132 = __cil_tmp131 + 2UL;
 #line 675
         __cil_tmp133 = *__cil_tmp132;
 #line 675
         __cil_tmp134 = (unsigned int )__cil_tmp133;
 #line 675
         if (__cil_tmp134 != 0U) {
           {
 #line 676
           dev_priv->saveDPFC_CB_BASE = i915_read32(dev_priv, 274944U);
           }
         } else {
           {
 #line 677
           __cil_tmp135 = dev->pci_device;
 #line 677
           if (__cil_tmp135 == 10818) {
             {
 #line 678
             dev_priv->saveDPFC_CB_BASE = i915_read32(dev_priv, 12800U);
             }
           } else {
             {
 #line 680
             dev_priv->saveFBC_CFB_BASE = i915_read32(dev_priv, 12800U);
 #line 681
             dev_priv->saveFBC_LL_BASE = i915_read32(dev_priv, 12804U);
 #line 682
             dev_priv->saveFBC_CONTROL2 = i915_read32(dev_priv, 12820U);
 #line 683
             dev_priv->saveFBC_CONTROL = i915_read32(dev_priv, 12808U);
             }
           }
           }
         }
         }
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 688
   dev_priv->saveVGA0 = i915_read32(dev_priv, 24576U);
 #line 689
   dev_priv->saveVGA1 = i915_read32(dev_priv, 24580U);
 #line 690
   dev_priv->saveVGA_PD = i915_read32(dev_priv, 24592U);
   }
   {
 #line 691
   __cil_tmp136 = dev->dev_private;
 #line 691
   __cil_tmp137 = (struct drm_i915_private *)__cil_tmp136;
 #line 691
   __cil_tmp138 = __cil_tmp137->info;
 #line 691
   __cil_tmp139 = __cil_tmp138->gen;
 #line 691
   __cil_tmp140 = (unsigned char )__cil_tmp139;
 #line 691
   __cil_tmp141 = (unsigned int )__cil_tmp140;
 #line 691
   if (__cil_tmp141 == 5U) {
     {
 #line 692
     dev_priv->saveVGACNTRL = i915_read32(dev_priv, 266240U);
     }
   } else {
     {
 #line 691
     __cil_tmp142 = dev->dev_private;
 #line 691
     __cil_tmp143 = (struct drm_i915_private *)__cil_tmp142;
 #line 691
     __cil_tmp144 = __cil_tmp143->info;
 #line 691
     __cil_tmp145 = __cil_tmp144->gen;
 #line 691
     __cil_tmp146 = (unsigned char )__cil_tmp145;
 #line 691
     __cil_tmp147 = (unsigned int )__cil_tmp146;
 #line 691
     if (__cil_tmp147 == 6U) {
       {
 #line 692
       dev_priv->saveVGACNTRL = i915_read32(dev_priv, 266240U);
       }
     } else {
       {
 #line 691
       __cil_tmp148 = dev->dev_private;
 #line 691
       __cil_tmp149 = (struct drm_i915_private *)__cil_tmp148;
 #line 691
       __cil_tmp150 = __cil_tmp149->info;
 #line 691
       __cil_tmp151 = (unsigned char *)__cil_tmp150;
 #line 691
       __cil_tmp152 = __cil_tmp151 + 2UL;
 #line 691
       __cil_tmp153 = *__cil_tmp152;
 #line 691
       __cil_tmp154 = (unsigned int )__cil_tmp153;
 #line 691
       if (__cil_tmp154 != 0U) {
         {
 #line 692
         dev_priv->saveVGACNTRL = i915_read32(dev_priv, 266240U);
         }
       } else {
         {
 #line 694
         dev_priv->saveVGACNTRL = i915_read32(dev_priv, 463872U);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 696
   i915_save_vga(dev);
   }
 #line 697
   return;
 }
 }
 #line 699 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 static void i915_restore_display(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp3 ;
   u32 __cil_tmp4 ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char *__cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   u32 __cil_tmp18 ;
   u32 __cil_tmp19 ;
   u32 __cil_tmp20 ;
   u32 __cil_tmp21 ;
   u32 __cil_tmp22 ;
   u32 __cil_tmp23 ;
   u32 __cil_tmp24 ;
   u32 __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct drm_i915_private *__cil_tmp27 ;
   struct intel_device_info  const  *__cil_tmp28 ;
   u8 __cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   u32 __cil_tmp32 ;
   void *__cil_tmp33 ;
   struct drm_i915_private *__cil_tmp34 ;
   struct intel_device_info  const  *__cil_tmp35 ;
   u8 __cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   void *__cil_tmp40 ;
   struct drm_i915_private *__cil_tmp41 ;
   struct intel_device_info  const  *__cil_tmp42 ;
   unsigned char *__cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   u32 __cil_tmp47 ;
   u32 __cil_tmp48 ;
   void *__cil_tmp49 ;
   struct drm_i915_private *__cil_tmp50 ;
   struct intel_device_info  const  *__cil_tmp51 ;
   u8 __cil_tmp52 ;
   unsigned char __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   void *__cil_tmp55 ;
   struct drm_i915_private *__cil_tmp56 ;
   struct intel_device_info  const  *__cil_tmp57 ;
   u8 __cil_tmp58 ;
   unsigned char __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   void *__cil_tmp61 ;
   struct drm_i915_private *__cil_tmp62 ;
   struct intel_device_info  const  *__cil_tmp63 ;
   u8 __cil_tmp64 ;
   unsigned char __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   void *__cil_tmp67 ;
   struct drm_i915_private *__cil_tmp68 ;
   struct intel_device_info  const  *__cil_tmp69 ;
   unsigned char *__cil_tmp70 ;
   unsigned char *__cil_tmp71 ;
   unsigned char __cil_tmp72 ;
   unsigned int __cil_tmp73 ;
   u32 __cil_tmp74 ;
   void *__cil_tmp75 ;
   struct drm_i915_private *__cil_tmp76 ;
   struct intel_device_info  const  *__cil_tmp77 ;
   u8 __cil_tmp78 ;
   unsigned char __cil_tmp79 ;
   unsigned int __cil_tmp80 ;
   u32 __cil_tmp81 ;
   void *__cil_tmp82 ;
   struct drm_i915_private *__cil_tmp83 ;
   struct intel_device_info  const  *__cil_tmp84 ;
   u8 __cil_tmp85 ;
   unsigned char __cil_tmp86 ;
   unsigned int __cil_tmp87 ;
   u32 __cil_tmp88 ;
   void *__cil_tmp89 ;
   struct drm_i915_private *__cil_tmp90 ;
   struct intel_device_info  const  *__cil_tmp91 ;
   unsigned char *__cil_tmp92 ;
   unsigned char *__cil_tmp93 ;
   unsigned char __cil_tmp94 ;
   unsigned int __cil_tmp95 ;
   u32 __cil_tmp96 ;
   void *__cil_tmp97 ;
   struct drm_i915_private *__cil_tmp98 ;
   struct intel_device_info  const  *__cil_tmp99 ;
   unsigned char *__cil_tmp100 ;
   unsigned char *__cil_tmp101 ;
   unsigned char __cil_tmp102 ;
   unsigned int __cil_tmp103 ;
   int __cil_tmp104 ;
   u32 __cil_tmp105 ;
   int __cil_tmp106 ;
   int __cil_tmp107 ;
   void *__cil_tmp108 ;
   struct drm_i915_private *__cil_tmp109 ;
   struct intel_device_info  const  *__cil_tmp110 ;
   u8 __cil_tmp111 ;
   unsigned char __cil_tmp112 ;
   unsigned int __cil_tmp113 ;
   void *__cil_tmp114 ;
   struct drm_i915_private *__cil_tmp115 ;
   struct intel_device_info  const  *__cil_tmp116 ;
   u8 __cil_tmp117 ;
   unsigned char __cil_tmp118 ;
   unsigned int __cil_tmp119 ;
   void *__cil_tmp120 ;
   struct drm_i915_private *__cil_tmp121 ;
   struct intel_device_info  const  *__cil_tmp122 ;
   unsigned char *__cil_tmp123 ;
   unsigned char *__cil_tmp124 ;
   unsigned char __cil_tmp125 ;
   unsigned int __cil_tmp126 ;
   u32 __cil_tmp127 ;
   void *__cil_tmp128 ;
   struct drm_i915_private *__cil_tmp129 ;
   struct intel_device_info  const  *__cil_tmp130 ;
   u8 __cil_tmp131 ;
   unsigned char __cil_tmp132 ;
   unsigned int __cil_tmp133 ;
   void *__cil_tmp134 ;
   struct drm_i915_private *__cil_tmp135 ;
   struct intel_device_info  const  *__cil_tmp136 ;
   u8 __cil_tmp137 ;
   unsigned char __cil_tmp138 ;
   unsigned int __cil_tmp139 ;
   void *__cil_tmp140 ;
   struct drm_i915_private *__cil_tmp141 ;
   struct intel_device_info  const  *__cil_tmp142 ;
   unsigned char *__cil_tmp143 ;
   unsigned char *__cil_tmp144 ;
   unsigned char __cil_tmp145 ;
   unsigned int __cil_tmp146 ;
   u32 __cil_tmp147 ;
   u32 __cil_tmp148 ;
   u32 __cil_tmp149 ;
   u32 __cil_tmp150 ;
   u32 __cil_tmp151 ;
   u32 __cil_tmp152 ;
   u32 __cil_tmp153 ;
   u32 __cil_tmp154 ;
   u32 __cil_tmp155 ;
   u32 __cil_tmp156 ;
   u32 __cil_tmp157 ;
   u32 __cil_tmp158 ;
   u32 __cil_tmp159 ;
   u32 __cil_tmp160 ;
   u32 __cil_tmp161 ;
   u32 __cil_tmp162 ;
   void *__cil_tmp163 ;
   struct drm_i915_private *__cil_tmp164 ;
   struct intel_device_info  const  *__cil_tmp165 ;
   unsigned char *__cil_tmp166 ;
   unsigned char *__cil_tmp167 ;
   unsigned char __cil_tmp168 ;
   unsigned int __cil_tmp169 ;
   u32 __cil_tmp170 ;
   u32 __cil_tmp171 ;
   u32 __cil_tmp172 ;
   void *__cil_tmp173 ;
   struct drm_i915_private *__cil_tmp174 ;
   struct intel_device_info  const  *__cil_tmp175 ;
   u8 __cil_tmp176 ;
   unsigned char __cil_tmp177 ;
   unsigned int __cil_tmp178 ;
   u32 __cil_tmp179 ;
   u32 __cil_tmp180 ;
   u32 __cil_tmp181 ;
   void *__cil_tmp182 ;
   struct drm_i915_private *__cil_tmp183 ;
   struct intel_device_info  const  *__cil_tmp184 ;
   unsigned char *__cil_tmp185 ;
   unsigned char *__cil_tmp186 ;
   unsigned char __cil_tmp187 ;
   unsigned int __cil_tmp188 ;
   void *__cil_tmp189 ;
   struct drm_i915_private *__cil_tmp190 ;
   struct intel_device_info  const  *__cil_tmp191 ;
   u8 __cil_tmp192 ;
   unsigned char __cil_tmp193 ;
   unsigned int __cil_tmp194 ;
   u32 __cil_tmp195 ;
   void *__cil_tmp196 ;
   struct drm_i915_private *__cil_tmp197 ;
   struct intel_device_info  const  *__cil_tmp198 ;
   u8 __cil_tmp199 ;
   unsigned char __cil_tmp200 ;
   unsigned int __cil_tmp201 ;
   u32 __cil_tmp202 ;
   void *__cil_tmp203 ;
   struct drm_i915_private *__cil_tmp204 ;
   struct intel_device_info  const  *__cil_tmp205 ;
   unsigned char *__cil_tmp206 ;
   unsigned char *__cil_tmp207 ;
   unsigned char __cil_tmp208 ;
   unsigned int __cil_tmp209 ;
   u32 __cil_tmp210 ;
   int __cil_tmp211 ;
   u32 __cil_tmp212 ;
   u32 __cil_tmp213 ;
   u32 __cil_tmp214 ;
   u32 __cil_tmp215 ;
   u32 __cil_tmp216 ;
   void *__cil_tmp217 ;
   struct drm_i915_private *__cil_tmp218 ;
   struct intel_device_info  const  *__cil_tmp219 ;
   u8 __cil_tmp220 ;
   unsigned char __cil_tmp221 ;
   unsigned int __cil_tmp222 ;
   u32 __cil_tmp223 ;
   void *__cil_tmp224 ;
   struct drm_i915_private *__cil_tmp225 ;
   struct intel_device_info  const  *__cil_tmp226 ;
   u8 __cil_tmp227 ;
   unsigned char __cil_tmp228 ;
   unsigned int __cil_tmp229 ;
   u32 __cil_tmp230 ;
   void *__cil_tmp231 ;
   struct drm_i915_private *__cil_tmp232 ;
   struct intel_device_info  const  *__cil_tmp233 ;
   unsigned char *__cil_tmp234 ;
   unsigned char *__cil_tmp235 ;
   unsigned char __cil_tmp236 ;
   unsigned int __cil_tmp237 ;
   u32 __cil_tmp238 ;
   u32 __cil_tmp239 ;
   u32 __cil_tmp240 ;
   u32 __cil_tmp241 ;
   u32 __cil_tmp242 ;
   void *__cil_tmp243 ;
   void const volatile   *__cil_tmp244 ;
   void const volatile   *__cil_tmp245 ;
 
   {
   {
 #line 701
   __cil_tmp3 = dev->dev_private;
 #line 701
   dev_priv = (struct drm_i915_private *)__cil_tmp3;
 #line 704
   __cil_tmp4 = dev_priv->saveDSPARB;
 #line 704
   i915_write32(dev_priv, 458800U, __cil_tmp4);
   }
   {
 #line 707
   __cil_tmp5 = dev->dev_private;
 #line 707
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 707
   __cil_tmp7 = __cil_tmp6->info;
 #line 707
   __cil_tmp8 = (unsigned char *)__cil_tmp7;
 #line 707
   __cil_tmp9 = __cil_tmp8 + 1UL;
 #line 707
   __cil_tmp10 = *__cil_tmp9;
 #line 707
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 707
   if (__cil_tmp11 != 0U) {
 #line 707
     goto _L;
   } else {
     {
 #line 707
     __cil_tmp12 = dev->dev_private;
 #line 707
     __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 707
     __cil_tmp14 = __cil_tmp13->info;
 #line 707
     __cil_tmp15 = __cil_tmp14->gen;
 #line 707
     __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 707
     __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 707
     if (__cil_tmp17 == 5U) {
       _L: 
       {
 #line 708
       __cil_tmp18 = dev_priv->savePIPEA_GMCH_DATA_M;
 #line 708
       i915_write32(dev_priv, 458832U, __cil_tmp18);
 #line 709
       __cil_tmp19 = dev_priv->savePIPEB_GMCH_DATA_M;
 #line 709
       i915_write32(dev_priv, 462928U, __cil_tmp19);
 #line 710
       __cil_tmp20 = dev_priv->savePIPEA_GMCH_DATA_N;
 #line 710
       i915_write32(dev_priv, 458836U, __cil_tmp20);
 #line 711
       __cil_tmp21 = dev_priv->savePIPEB_GMCH_DATA_N;
 #line 711
       i915_write32(dev_priv, 462932U, __cil_tmp21);
 #line 712
       __cil_tmp22 = dev_priv->savePIPEA_DP_LINK_M;
 #line 712
       i915_write32(dev_priv, 458848U, __cil_tmp22);
 #line 713
       __cil_tmp23 = dev_priv->savePIPEB_DP_LINK_M;
 #line 713
       i915_write32(dev_priv, 462944U, __cil_tmp23);
 #line 714
       __cil_tmp24 = dev_priv->savePIPEA_DP_LINK_N;
 #line 714
       i915_write32(dev_priv, 458852U, __cil_tmp24);
 #line 715
       __cil_tmp25 = dev_priv->savePIPEB_DP_LINK_N;
 #line 715
       i915_write32(dev_priv, 462948U, __cil_tmp25);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 720
   i915_restore_modeset_reg(dev);
   }
   {
 #line 723
   __cil_tmp26 = dev->dev_private;
 #line 723
   __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
 #line 723
   __cil_tmp28 = __cil_tmp27->info;
 #line 723
   __cil_tmp29 = __cil_tmp28->gen;
 #line 723
   __cil_tmp30 = (unsigned char )__cil_tmp29;
 #line 723
   __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 723
   if (__cil_tmp31 == 5U) {
     {
 #line 724
     __cil_tmp32 = dev_priv->saveADPA;
 #line 724
     i915_write32(dev_priv, 921856U, __cil_tmp32);
     }
   } else {
     {
 #line 723
     __cil_tmp33 = dev->dev_private;
 #line 723
     __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
 #line 723
     __cil_tmp35 = __cil_tmp34->info;
 #line 723
     __cil_tmp36 = __cil_tmp35->gen;
 #line 723
     __cil_tmp37 = (unsigned char )__cil_tmp36;
 #line 723
     __cil_tmp38 = (unsigned int )__cil_tmp37;
 #line 723
     if (__cil_tmp38 == 6U) {
       {
 #line 724
       __cil_tmp39 = dev_priv->saveADPA;
 #line 724
       i915_write32(dev_priv, 921856U, __cil_tmp39);
       }
     } else {
       {
 #line 723
       __cil_tmp40 = dev->dev_private;
 #line 723
       __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
 #line 723
       __cil_tmp42 = __cil_tmp41->info;
 #line 723
       __cil_tmp43 = (unsigned char *)__cil_tmp42;
 #line 723
       __cil_tmp44 = __cil_tmp43 + 2UL;
 #line 723
       __cil_tmp45 = *__cil_tmp44;
 #line 723
       __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 723
       if (__cil_tmp46 != 0U) {
         {
 #line 724
         __cil_tmp47 = dev_priv->saveADPA;
 #line 724
         i915_write32(dev_priv, 921856U, __cil_tmp47);
         }
       } else {
         {
 #line 726
         __cil_tmp48 = dev_priv->saveADPA;
 #line 726
         i915_write32(dev_priv, 397568U, __cil_tmp48);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 729
   __cil_tmp49 = dev->dev_private;
 #line 729
   __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
 #line 729
   __cil_tmp51 = __cil_tmp50->info;
 #line 729
   __cil_tmp52 = __cil_tmp51->gen;
 #line 729
   __cil_tmp53 = (unsigned char )__cil_tmp52;
 #line 729
   __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 729
   if (__cil_tmp54 > 3U) {
     {
 #line 729
     __cil_tmp55 = dev->dev_private;
 #line 729
     __cil_tmp56 = (struct drm_i915_private *)__cil_tmp55;
 #line 729
     __cil_tmp57 = __cil_tmp56->info;
 #line 729
     __cil_tmp58 = __cil_tmp57->gen;
 #line 729
     __cil_tmp59 = (unsigned char )__cil_tmp58;
 #line 729
     __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 729
     if (__cil_tmp60 != 5U) {
       {
 #line 729
       __cil_tmp61 = dev->dev_private;
 #line 729
       __cil_tmp62 = (struct drm_i915_private *)__cil_tmp61;
 #line 729
       __cil_tmp63 = __cil_tmp62->info;
 #line 729
       __cil_tmp64 = __cil_tmp63->gen;
 #line 729
       __cil_tmp65 = (unsigned char )__cil_tmp64;
 #line 729
       __cil_tmp66 = (unsigned int )__cil_tmp65;
 #line 729
       if (__cil_tmp66 != 6U) {
         {
 #line 729
         __cil_tmp67 = dev->dev_private;
 #line 729
         __cil_tmp68 = (struct drm_i915_private *)__cil_tmp67;
 #line 729
         __cil_tmp69 = __cil_tmp68->info;
 #line 729
         __cil_tmp70 = (unsigned char *)__cil_tmp69;
 #line 729
         __cil_tmp71 = __cil_tmp70 + 2UL;
 #line 729
         __cil_tmp72 = *__cil_tmp71;
 #line 729
         __cil_tmp73 = (unsigned int )__cil_tmp72;
 #line 729
         if (__cil_tmp73 == 0U) {
           {
 #line 730
           __cil_tmp74 = dev_priv->saveBLC_PWM_CTL2;
 #line 730
           i915_write32(dev_priv, 397904U, __cil_tmp74);
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 732
   __cil_tmp75 = dev->dev_private;
 #line 732
   __cil_tmp76 = (struct drm_i915_private *)__cil_tmp75;
 #line 732
   __cil_tmp77 = __cil_tmp76->info;
 #line 732
   __cil_tmp78 = __cil_tmp77->gen;
 #line 732
   __cil_tmp79 = (unsigned char )__cil_tmp78;
 #line 732
   __cil_tmp80 = (unsigned int )__cil_tmp79;
 #line 732
   if (__cil_tmp80 == 5U) {
     {
 #line 733
     __cil_tmp81 = dev_priv->saveLVDS;
 #line 733
     i915_write32(dev_priv, 921984U, __cil_tmp81);
     }
   } else {
     {
 #line 732
     __cil_tmp82 = dev->dev_private;
 #line 732
     __cil_tmp83 = (struct drm_i915_private *)__cil_tmp82;
 #line 732
     __cil_tmp84 = __cil_tmp83->info;
 #line 732
     __cil_tmp85 = __cil_tmp84->gen;
 #line 732
     __cil_tmp86 = (unsigned char )__cil_tmp85;
 #line 732
     __cil_tmp87 = (unsigned int )__cil_tmp86;
 #line 732
     if (__cil_tmp87 == 6U) {
       {
 #line 733
       __cil_tmp88 = dev_priv->saveLVDS;
 #line 733
       i915_write32(dev_priv, 921984U, __cil_tmp88);
       }
     } else {
       {
 #line 732
       __cil_tmp89 = dev->dev_private;
 #line 732
       __cil_tmp90 = (struct drm_i915_private *)__cil_tmp89;
 #line 732
       __cil_tmp91 = __cil_tmp90->info;
 #line 732
       __cil_tmp92 = (unsigned char *)__cil_tmp91;
 #line 732
       __cil_tmp93 = __cil_tmp92 + 2UL;
 #line 732
       __cil_tmp94 = *__cil_tmp93;
 #line 732
       __cil_tmp95 = (unsigned int )__cil_tmp94;
 #line 732
       if (__cil_tmp95 != 0U) {
         {
 #line 733
         __cil_tmp96 = dev_priv->saveLVDS;
 #line 733
         i915_write32(dev_priv, 921984U, __cil_tmp96);
         }
       } else {
         {
 #line 734
         __cil_tmp97 = dev->dev_private;
 #line 734
         __cil_tmp98 = (struct drm_i915_private *)__cil_tmp97;
 #line 734
         __cil_tmp99 = __cil_tmp98->info;
 #line 734
         __cil_tmp100 = (unsigned char *)__cil_tmp99;
 #line 734
         __cil_tmp101 = __cil_tmp100 + 1UL;
 #line 734
         __cil_tmp102 = *__cil_tmp101;
 #line 734
         __cil_tmp103 = (unsigned int )__cil_tmp102;
 #line 734
         if (__cil_tmp103 != 0U) {
           {
 #line 734
           __cil_tmp104 = dev->pci_device;
 #line 734
           if (__cil_tmp104 != 13687) {
             {
 #line 735
             __cil_tmp105 = dev_priv->saveLVDS;
 #line 735
             i915_write32(dev_priv, 397696U, __cil_tmp105);
             }
           } else {
 
           }
           }
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
   {
 #line 737
   __cil_tmp106 = dev->pci_device;
 #line 737
   if (__cil_tmp106 != 13687) {
     {
 #line 737
     __cil_tmp107 = dev->pci_device;
 #line 737
     if (__cil_tmp107 != 9570) {
       {
 #line 737
       __cil_tmp108 = dev->dev_private;
 #line 737
       __cil_tmp109 = (struct drm_i915_private *)__cil_tmp108;
 #line 737
       __cil_tmp110 = __cil_tmp109->info;
 #line 737
       __cil_tmp111 = __cil_tmp110->gen;
 #line 737
       __cil_tmp112 = (unsigned char )__cil_tmp111;
 #line 737
       __cil_tmp113 = (unsigned int )__cil_tmp112;
 #line 737
       if (__cil_tmp113 != 5U) {
         {
 #line 737
         __cil_tmp114 = dev->dev_private;
 #line 737
         __cil_tmp115 = (struct drm_i915_private *)__cil_tmp114;
 #line 737
         __cil_tmp116 = __cil_tmp115->info;
 #line 737
         __cil_tmp117 = __cil_tmp116->gen;
 #line 737
         __cil_tmp118 = (unsigned char )__cil_tmp117;
 #line 737
         __cil_tmp119 = (unsigned int )__cil_tmp118;
 #line 737
         if (__cil_tmp119 != 6U) {
           {
 #line 737
           __cil_tmp120 = dev->dev_private;
 #line 737
           __cil_tmp121 = (struct drm_i915_private *)__cil_tmp120;
 #line 737
           __cil_tmp122 = __cil_tmp121->info;
 #line 737
           __cil_tmp123 = (unsigned char *)__cil_tmp122;
 #line 737
           __cil_tmp124 = __cil_tmp123 + 2UL;
 #line 737
           __cil_tmp125 = *__cil_tmp124;
 #line 737
           __cil_tmp126 = (unsigned int )__cil_tmp125;
 #line 737
           if (__cil_tmp126 == 0U) {
             {
 #line 738
             __cil_tmp127 = dev_priv->savePFIT_CONTROL;
 #line 738
             i915_write32(dev_priv, 397872U, __cil_tmp127);
             }
           } else {
 
           }
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 740
   __cil_tmp128 = dev->dev_private;
 #line 740
   __cil_tmp129 = (struct drm_i915_private *)__cil_tmp128;
 #line 740
   __cil_tmp130 = __cil_tmp129->info;
 #line 740
   __cil_tmp131 = __cil_tmp130->gen;
 #line 740
   __cil_tmp132 = (unsigned char )__cil_tmp131;
 #line 740
   __cil_tmp133 = (unsigned int )__cil_tmp132;
 #line 740
   if (__cil_tmp133 == 5U) {
 #line 740
     goto _L___0;
   } else {
     {
 #line 740
     __cil_tmp134 = dev->dev_private;
 #line 740
     __cil_tmp135 = (struct drm_i915_private *)__cil_tmp134;
 #line 740
     __cil_tmp136 = __cil_tmp135->info;
 #line 740
     __cil_tmp137 = __cil_tmp136->gen;
 #line 740
     __cil_tmp138 = (unsigned char )__cil_tmp137;
 #line 740
     __cil_tmp139 = (unsigned int )__cil_tmp138;
 #line 740
     if (__cil_tmp139 == 6U) {
 #line 740
       goto _L___0;
     } else {
       {
 #line 740
       __cil_tmp140 = dev->dev_private;
 #line 740
       __cil_tmp141 = (struct drm_i915_private *)__cil_tmp140;
 #line 740
       __cil_tmp142 = __cil_tmp141->info;
 #line 740
       __cil_tmp143 = (unsigned char *)__cil_tmp142;
 #line 740
       __cil_tmp144 = __cil_tmp143 + 2UL;
 #line 740
       __cil_tmp145 = *__cil_tmp144;
 #line 740
       __cil_tmp146 = (unsigned int )__cil_tmp145;
 #line 740
       if (__cil_tmp146 != 0U) {
         _L___0: 
         {
 #line 741
         __cil_tmp147 = dev_priv->saveBLC_PWM_CTL;
 #line 741
         i915_write32(dev_priv, 819792U, __cil_tmp147);
 #line 742
         __cil_tmp148 = dev_priv->saveBLC_PWM_CTL2;
 #line 742
         i915_write32(dev_priv, 819796U, __cil_tmp148);
 #line 743
         __cil_tmp149 = dev_priv->saveBLC_CPU_PWM_CTL;
 #line 743
         i915_write32(dev_priv, 295508U, __cil_tmp149);
 #line 744
         __cil_tmp150 = dev_priv->saveBLC_CPU_PWM_CTL2;
 #line 744
         i915_write32(dev_priv, 295504U, __cil_tmp150);
 #line 745
         __cil_tmp151 = dev_priv->savePP_ON_DELAYS;
 #line 745
         i915_write32(dev_priv, 815624U, __cil_tmp151);
 #line 746
         __cil_tmp152 = dev_priv->savePP_OFF_DELAYS;
 #line 746
         i915_write32(dev_priv, 815628U, __cil_tmp152);
 #line 747
         __cil_tmp153 = dev_priv->savePP_DIVISOR;
 #line 747
         i915_write32(dev_priv, 815632U, __cil_tmp153);
 #line 748
         __cil_tmp154 = dev_priv->savePP_CONTROL;
 #line 748
         i915_write32(dev_priv, 815620U, __cil_tmp154);
 #line 749
         __cil_tmp155 = dev_priv->saveMCHBAR_RENDER_STANDBY;
 #line 749
         i915_write32(dev_priv, 70072U, __cil_tmp155);
         }
       } else {
         {
 #line 752
         __cil_tmp156 = dev_priv->savePFIT_PGM_RATIOS;
 #line 752
         i915_write32(dev_priv, 397876U, __cil_tmp156);
 #line 753
         __cil_tmp157 = dev_priv->saveBLC_PWM_CTL;
 #line 753
         i915_write32(dev_priv, 397908U, __cil_tmp157);
 #line 754
         __cil_tmp158 = dev_priv->saveBLC_HIST_CTL;
 #line 754
         i915_write32(dev_priv, 397920U, __cil_tmp158);
 #line 755
         __cil_tmp159 = dev_priv->savePP_ON_DELAYS;
 #line 755
         i915_write32(dev_priv, 397832U, __cil_tmp159);
 #line 756
         __cil_tmp160 = dev_priv->savePP_OFF_DELAYS;
 #line 756
         i915_write32(dev_priv, 397836U, __cil_tmp160);
 #line 757
         __cil_tmp161 = dev_priv->savePP_DIVISOR;
 #line 757
         i915_write32(dev_priv, 397840U, __cil_tmp161);
 #line 758
         __cil_tmp162 = dev_priv->savePP_CONTROL;
 #line 758
         i915_write32(dev_priv, 397828U, __cil_tmp162);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 762
   __cil_tmp163 = dev->dev_private;
 #line 762
   __cil_tmp164 = (struct drm_i915_private *)__cil_tmp163;
 #line 762
   __cil_tmp165 = __cil_tmp164->info;
 #line 762
   __cil_tmp166 = (unsigned char *)__cil_tmp165;
 #line 762
   __cil_tmp167 = __cil_tmp166 + 1UL;
 #line 762
   __cil_tmp168 = *__cil_tmp167;
 #line 762
   __cil_tmp169 = (unsigned int )__cil_tmp168;
 #line 762
   if (__cil_tmp169 != 0U) {
     {
 #line 763
     __cil_tmp170 = dev_priv->saveDP_B;
 #line 763
     i915_write32(dev_priv, 409856U, __cil_tmp170);
 #line 764
     __cil_tmp171 = dev_priv->saveDP_C;
 #line 764
     i915_write32(dev_priv, 410112U, __cil_tmp171);
 #line 765
     __cil_tmp172 = dev_priv->saveDP_D;
 #line 765
     i915_write32(dev_priv, 410368U, __cil_tmp172);
     }
   } else {
     {
 #line 762
     __cil_tmp173 = dev->dev_private;
 #line 762
     __cil_tmp174 = (struct drm_i915_private *)__cil_tmp173;
 #line 762
     __cil_tmp175 = __cil_tmp174->info;
 #line 762
     __cil_tmp176 = __cil_tmp175->gen;
 #line 762
     __cil_tmp177 = (unsigned char )__cil_tmp176;
 #line 762
     __cil_tmp178 = (unsigned int )__cil_tmp177;
 #line 762
     if (__cil_tmp178 == 5U) {
       {
 #line 763
       __cil_tmp179 = dev_priv->saveDP_B;
 #line 763
       i915_write32(dev_priv, 409856U, __cil_tmp179);
 #line 764
       __cil_tmp180 = dev_priv->saveDP_C;
 #line 764
       i915_write32(dev_priv, 410112U, __cil_tmp180);
 #line 765
       __cil_tmp181 = dev_priv->saveDP_D;
 #line 765
       i915_write32(dev_priv, 410368U, __cil_tmp181);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 770
   __cil_tmp182 = dev->dev_private;
 #line 770
   __cil_tmp183 = (struct drm_i915_private *)__cil_tmp182;
 #line 770
   __cil_tmp184 = __cil_tmp183->info;
 #line 770
   __cil_tmp185 = (unsigned char *)__cil_tmp184;
 #line 770
   __cil_tmp186 = __cil_tmp185 + 2UL;
 #line 770
   __cil_tmp187 = *__cil_tmp186;
 #line 770
   __cil_tmp188 = (unsigned int )__cil_tmp187;
 #line 770
   if (__cil_tmp188 != 0U) {
     {
 #line 771
     __cil_tmp189 = dev->dev_private;
 #line 771
     __cil_tmp190 = (struct drm_i915_private *)__cil_tmp189;
 #line 771
     __cil_tmp191 = __cil_tmp190->info;
 #line 771
     __cil_tmp192 = __cil_tmp191->gen;
 #line 771
     __cil_tmp193 = (unsigned char )__cil_tmp192;
 #line 771
     __cil_tmp194 = (unsigned int )__cil_tmp193;
 #line 771
     if (__cil_tmp194 == 5U) {
       {
 #line 772
       ironlake_disable_fbc(dev);
 #line 773
       __cil_tmp195 = dev_priv->saveDPFC_CB_BASE;
 #line 773
       i915_write32(dev_priv, 274944U, __cil_tmp195);
       }
     } else {
       {
 #line 771
       __cil_tmp196 = dev->dev_private;
 #line 771
       __cil_tmp197 = (struct drm_i915_private *)__cil_tmp196;
 #line 771
       __cil_tmp198 = __cil_tmp197->info;
 #line 771
       __cil_tmp199 = __cil_tmp198->gen;
 #line 771
       __cil_tmp200 = (unsigned char )__cil_tmp199;
 #line 771
       __cil_tmp201 = (unsigned int )__cil_tmp200;
 #line 771
       if (__cil_tmp201 == 6U) {
         {
 #line 772
         ironlake_disable_fbc(dev);
 #line 773
         __cil_tmp202 = dev_priv->saveDPFC_CB_BASE;
 #line 773
         i915_write32(dev_priv, 274944U, __cil_tmp202);
         }
       } else {
         {
 #line 771
         __cil_tmp203 = dev->dev_private;
 #line 771
         __cil_tmp204 = (struct drm_i915_private *)__cil_tmp203;
 #line 771
         __cil_tmp205 = __cil_tmp204->info;
 #line 771
         __cil_tmp206 = (unsigned char *)__cil_tmp205;
 #line 771
         __cil_tmp207 = __cil_tmp206 + 2UL;
 #line 771
         __cil_tmp208 = *__cil_tmp207;
 #line 771
         __cil_tmp209 = (unsigned int )__cil_tmp208;
 #line 771
         if (__cil_tmp209 != 0U) {
           {
 #line 772
           ironlake_disable_fbc(dev);
 #line 773
           __cil_tmp210 = dev_priv->saveDPFC_CB_BASE;
 #line 773
           i915_write32(dev_priv, 274944U, __cil_tmp210);
           }
         } else {
           {
 #line 774
           __cil_tmp211 = dev->pci_device;
 #line 774
           if (__cil_tmp211 == 10818) {
             {
 #line 775
             g4x_disable_fbc(dev);
 #line 776
             __cil_tmp212 = dev_priv->saveDPFC_CB_BASE;
 #line 776
             i915_write32(dev_priv, 12800U, __cil_tmp212);
             }
           } else {
             {
 #line 778
             i8xx_disable_fbc(dev);
 #line 779
             __cil_tmp213 = dev_priv->saveFBC_CFB_BASE;
 #line 779
             i915_write32(dev_priv, 12800U, __cil_tmp213);
 #line 780
             __cil_tmp214 = dev_priv->saveFBC_LL_BASE;
 #line 780
             i915_write32(dev_priv, 12804U, __cil_tmp214);
 #line 781
             __cil_tmp215 = dev_priv->saveFBC_CONTROL2;
 #line 781
             i915_write32(dev_priv, 12820U, __cil_tmp215);
 #line 782
             __cil_tmp216 = dev_priv->saveFBC_CONTROL;
 #line 782
             i915_write32(dev_priv, 12808U, __cil_tmp216);
             }
           }
           }
         }
         }
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 786
   __cil_tmp217 = dev->dev_private;
 #line 786
   __cil_tmp218 = (struct drm_i915_private *)__cil_tmp217;
 #line 786
   __cil_tmp219 = __cil_tmp218->info;
 #line 786
   __cil_tmp220 = __cil_tmp219->gen;
 #line 786
   __cil_tmp221 = (unsigned char )__cil_tmp220;
 #line 786
   __cil_tmp222 = (unsigned int )__cil_tmp221;
 #line 786
   if (__cil_tmp222 == 5U) {
     {
 #line 787
     __cil_tmp223 = dev_priv->saveVGACNTRL;
 #line 787
     i915_write32(dev_priv, 266240U, __cil_tmp223);
     }
   } else {
     {
 #line 786
     __cil_tmp224 = dev->dev_private;
 #line 786
     __cil_tmp225 = (struct drm_i915_private *)__cil_tmp224;
 #line 786
     __cil_tmp226 = __cil_tmp225->info;
 #line 786
     __cil_tmp227 = __cil_tmp226->gen;
 #line 786
     __cil_tmp228 = (unsigned char )__cil_tmp227;
 #line 786
     __cil_tmp229 = (unsigned int )__cil_tmp228;
 #line 786
     if (__cil_tmp229 == 6U) {
       {
 #line 787
       __cil_tmp230 = dev_priv->saveVGACNTRL;
 #line 787
       i915_write32(dev_priv, 266240U, __cil_tmp230);
       }
     } else {
       {
 #line 786
       __cil_tmp231 = dev->dev_private;
 #line 786
       __cil_tmp232 = (struct drm_i915_private *)__cil_tmp231;
 #line 786
       __cil_tmp233 = __cil_tmp232->info;
 #line 786
       __cil_tmp234 = (unsigned char *)__cil_tmp233;
 #line 786
       __cil_tmp235 = __cil_tmp234 + 2UL;
 #line 786
       __cil_tmp236 = *__cil_tmp235;
 #line 786
       __cil_tmp237 = (unsigned int )__cil_tmp236;
 #line 786
       if (__cil_tmp237 != 0U) {
         {
 #line 787
         __cil_tmp238 = dev_priv->saveVGACNTRL;
 #line 787
         i915_write32(dev_priv, 266240U, __cil_tmp238);
         }
       } else {
         {
 #line 789
         __cil_tmp239 = dev_priv->saveVGACNTRL;
 #line 789
         i915_write32(dev_priv, 463872U, __cil_tmp239);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 791
   __cil_tmp240 = dev_priv->saveVGA0;
 #line 791
   i915_write32(dev_priv, 24576U, __cil_tmp240);
 #line 792
   __cil_tmp241 = dev_priv->saveVGA1;
 #line 792
   i915_write32(dev_priv, 24580U, __cil_tmp241);
 #line 793
   __cil_tmp242 = dev_priv->saveVGA_PD;
 #line 793
   i915_write32(dev_priv, 24592U, __cil_tmp242);
 #line 794
   __cil_tmp243 = dev_priv->regs;
 #line 794
   __cil_tmp244 = (void const volatile   *)__cil_tmp243;
 #line 794
   __cil_tmp245 = __cil_tmp244 + 24592U;
 #line 794
   readl(__cil_tmp245);
 #line 795
   __const_udelay(644250UL);
 #line 797
   i915_restore_vga(dev);
   }
 #line 798
   return;
 }
 }
 #line 800 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 int i915_save_state(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   void *__cil_tmp4 ;
   struct pci_dev *__cil_tmp5 ;
   u8 *__cil_tmp6 ;
   struct mutex *__cil_tmp7 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   u8 __cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   u8 __cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   void *__cil_tmp20 ;
   struct drm_i915_private *__cil_tmp21 ;
   struct intel_device_info  const  *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   int __cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   u32 __cil_tmp42 ;
   struct mutex *__cil_tmp43 ;
 
   {
   {
 #line 802
   __cil_tmp4 = dev->dev_private;
 #line 802
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 805
   __cil_tmp5 = dev->pdev;
 #line 805
   __cil_tmp6 = & dev_priv->saveLBB;
 #line 805
   pci_read_config_byte(__cil_tmp5, 244, __cil_tmp6);
 #line 807
   __cil_tmp7 = & dev->struct_mutex;
 #line 807
   mutex_lock_nested(__cil_tmp7, 0U);
 #line 810
   dev_priv->saveHWS = i915_read32(dev_priv, 8320U);
 #line 812
   i915_save_display(dev);
   }
   {
 #line 815
   __cil_tmp8 = dev->dev_private;
 #line 815
   __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 815
   __cil_tmp10 = __cil_tmp9->info;
 #line 815
   __cil_tmp11 = __cil_tmp10->gen;
 #line 815
   __cil_tmp12 = (unsigned char )__cil_tmp11;
 #line 815
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 815
   if (__cil_tmp13 == 5U) {
 #line 815
     goto _L;
   } else {
     {
 #line 815
     __cil_tmp14 = dev->dev_private;
 #line 815
     __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 815
     __cil_tmp16 = __cil_tmp15->info;
 #line 815
     __cil_tmp17 = __cil_tmp16->gen;
 #line 815
     __cil_tmp18 = (unsigned char )__cil_tmp17;
 #line 815
     __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 815
     if (__cil_tmp19 == 6U) {
 #line 815
       goto _L;
     } else {
       {
 #line 815
       __cil_tmp20 = dev->dev_private;
 #line 815
       __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
 #line 815
       __cil_tmp22 = __cil_tmp21->info;
 #line 815
       __cil_tmp23 = (unsigned char *)__cil_tmp22;
 #line 815
       __cil_tmp24 = __cil_tmp23 + 2UL;
 #line 815
       __cil_tmp25 = *__cil_tmp24;
 #line 815
       __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 815
       if (__cil_tmp26 != 0U) {
         _L: 
         {
 #line 816
         dev_priv->saveDEIER = i915_read32(dev_priv, 278540U);
 #line 817
         dev_priv->saveDEIMR = i915_read32(dev_priv, 278532U);
 #line 818
         dev_priv->saveGTIER = i915_read32(dev_priv, 278556U);
 #line 819
         dev_priv->saveGTIMR = i915_read32(dev_priv, 278548U);
 #line 820
         dev_priv->saveFDI_RXA_IMR = i915_read32(dev_priv, 983064U);
 #line 821
         dev_priv->saveFDI_RXB_IMR = i915_read32(dev_priv, 987160U);
 #line 822
         dev_priv->saveMCHBAR_RENDER_STANDBY = i915_read32(dev_priv, 70072U);
         }
       } else {
         {
 #line 825
         dev_priv->saveIER = i915_read32(dev_priv, 8352U);
 #line 826
         dev_priv->saveIMR = i915_read32(dev_priv, 8360U);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 829
   __cil_tmp27 = dev->pci_device;
 #line 829
   if (__cil_tmp27 == 70) {
     {
 #line 830
     ironlake_disable_drps(dev);
     }
   } else {
 
   }
   }
   {
 #line 831
   __cil_tmp28 = dev->dev_private;
 #line 831
   __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 831
   __cil_tmp30 = __cil_tmp29->info;
 #line 831
   __cil_tmp31 = __cil_tmp30->gen;
 #line 831
   __cil_tmp32 = (unsigned char )__cil_tmp31;
 #line 831
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 831
   if (__cil_tmp33 == 6U) {
     {
 #line 832
     gen6_disable_rps(dev);
     }
   } else {
 
   }
   }
   {
 #line 835
   dev_priv->saveCACHE_MODE_0 = i915_read32(dev_priv, 8480U);
 #line 838
   dev_priv->saveMI_ARB_STATE = i915_read32(dev_priv, 8420U);
 #line 841
   i = 0;
   }
 #line 841
   goto ldv_37712;
   ldv_37711: 
   {
 #line 842
   __cil_tmp34 = i << 2;
 #line 842
   __cil_tmp35 = __cil_tmp34 + 463888;
 #line 842
   __cil_tmp36 = (u32 )__cil_tmp35;
 #line 842
   dev_priv->saveSWF0[i] = i915_read32(dev_priv, __cil_tmp36);
 #line 843
   __cil_tmp37 = i << 2;
 #line 843
   __cil_tmp38 = __cil_tmp37 + 459792;
 #line 843
   __cil_tmp39 = (u32 )__cil_tmp38;
 #line 843
   dev_priv->saveSWF1[i] = i915_read32(dev_priv, __cil_tmp39);
 #line 841
   i = i + 1;
   }
   ldv_37712: ;
 #line 841
   if (i <= 15) {
 #line 842
     goto ldv_37711;
   } else {
 #line 844
     goto ldv_37713;
   }
   ldv_37713: 
 #line 845
   i = 0;
 #line 845
   goto ldv_37715;
   ldv_37714: 
   {
 #line 846
   __cil_tmp40 = i << 2;
 #line 846
   __cil_tmp41 = __cil_tmp40 + 467988;
 #line 846
   __cil_tmp42 = (u32 )__cil_tmp41;
 #line 846
   dev_priv->saveSWF2[i] = i915_read32(dev_priv, __cil_tmp42);
 #line 845
   i = i + 1;
   }
   ldv_37715: ;
 #line 845
   if (i <= 2) {
 #line 846
     goto ldv_37714;
   } else {
 #line 848
     goto ldv_37716;
   }
   ldv_37716: 
   {
 #line 848
   __cil_tmp43 = & dev->struct_mutex;
 #line 848
   mutex_unlock(__cil_tmp43);
   }
 #line 850
   return (0);
 }
 }
 #line 853 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_suspend.c.p"
 int i915_restore_state(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   void *__cil_tmp4 ;
   struct pci_dev *__cil_tmp5 ;
   u8 __cil_tmp6 ;
   int __cil_tmp7 ;
   u8 __cil_tmp8 ;
   struct mutex *__cil_tmp9 ;
   u32 __cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   u8 __cil_tmp20 ;
   unsigned char __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   unsigned char *__cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   u32 __cil_tmp30 ;
   u32 __cil_tmp31 ;
   u32 __cil_tmp32 ;
   u32 __cil_tmp33 ;
   u32 __cil_tmp34 ;
   u32 __cil_tmp35 ;
   u32 __cil_tmp36 ;
   u32 __cil_tmp37 ;
   struct mutex *__cil_tmp38 ;
   int __cil_tmp39 ;
   void *__cil_tmp40 ;
   struct drm_i915_private *__cil_tmp41 ;
   struct intel_device_info  const  *__cil_tmp42 ;
   u8 __cil_tmp43 ;
   unsigned char __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   struct mutex *__cil_tmp46 ;
   u32 __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   u32 __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   int __cil_tmp51 ;
   int __cil_tmp52 ;
   u32 __cil_tmp53 ;
   u32 __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   u32 __cil_tmp57 ;
   u32 __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   u32 __cil_tmp61 ;
   u32 __cil_tmp62 ;
   struct mutex *__cil_tmp63 ;
 
   {
   {
 #line 855
   __cil_tmp4 = dev->dev_private;
 #line 855
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 858
   __cil_tmp5 = dev->pdev;
 #line 858
   __cil_tmp6 = dev_priv->saveLBB;
 #line 858
   __cil_tmp7 = (int )__cil_tmp6;
 #line 858
   __cil_tmp8 = (u8 )__cil_tmp7;
 #line 858
   pci_write_config_byte(__cil_tmp5, 244, __cil_tmp8);
 #line 860
   __cil_tmp9 = & dev->struct_mutex;
 #line 860
   mutex_lock_nested(__cil_tmp9, 0U);
 #line 863
   __cil_tmp10 = dev_priv->saveHWS;
 #line 863
   i915_write32(dev_priv, 8320U, __cil_tmp10);
 #line 865
   i915_restore_display(dev);
   }
   {
 #line 868
   __cil_tmp11 = dev->dev_private;
 #line 868
   __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 868
   __cil_tmp13 = __cil_tmp12->info;
 #line 868
   __cil_tmp14 = __cil_tmp13->gen;
 #line 868
   __cil_tmp15 = (unsigned char )__cil_tmp14;
 #line 868
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 868
   if (__cil_tmp16 == 5U) {
 #line 868
     goto _L;
   } else {
     {
 #line 868
     __cil_tmp17 = dev->dev_private;
 #line 868
     __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 868
     __cil_tmp19 = __cil_tmp18->info;
 #line 868
     __cil_tmp20 = __cil_tmp19->gen;
 #line 868
     __cil_tmp21 = (unsigned char )__cil_tmp20;
 #line 868
     __cil_tmp22 = (unsigned int )__cil_tmp21;
 #line 868
     if (__cil_tmp22 == 6U) {
 #line 868
       goto _L;
     } else {
       {
 #line 868
       __cil_tmp23 = dev->dev_private;
 #line 868
       __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 868
       __cil_tmp25 = __cil_tmp24->info;
 #line 868
       __cil_tmp26 = (unsigned char *)__cil_tmp25;
 #line 868
       __cil_tmp27 = __cil_tmp26 + 2UL;
 #line 868
       __cil_tmp28 = *__cil_tmp27;
 #line 868
       __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 868
       if (__cil_tmp29 != 0U) {
         _L: 
         {
 #line 869
         __cil_tmp30 = dev_priv->saveDEIER;
 #line 869
         i915_write32(dev_priv, 278540U, __cil_tmp30);
 #line 870
         __cil_tmp31 = dev_priv->saveDEIMR;
 #line 870
         i915_write32(dev_priv, 278532U, __cil_tmp31);
 #line 871
         __cil_tmp32 = dev_priv->saveGTIER;
 #line 871
         i915_write32(dev_priv, 278556U, __cil_tmp32);
 #line 872
         __cil_tmp33 = dev_priv->saveGTIMR;
 #line 872
         i915_write32(dev_priv, 278548U, __cil_tmp33);
 #line 873
         __cil_tmp34 = dev_priv->saveFDI_RXA_IMR;
 #line 873
         i915_write32(dev_priv, 983064U, __cil_tmp34);
 #line 874
         __cil_tmp35 = dev_priv->saveFDI_RXB_IMR;
 #line 874
         i915_write32(dev_priv, 987160U, __cil_tmp35);
         }
       } else {
         {
 #line 876
         __cil_tmp36 = dev_priv->saveIER;
 #line 876
         i915_write32(dev_priv, 8352U, __cil_tmp36);
 #line 877
         __cil_tmp37 = dev_priv->saveIMR;
 #line 877
         i915_write32(dev_priv, 8360U, __cil_tmp37);
         }
       }
       }
     }
     }
   }
   }
   {
 #line 879
   __cil_tmp38 = & dev->struct_mutex;
 #line 879
   mutex_unlock(__cil_tmp38);
 #line 881
   intel_init_clock_gating(dev);
   }
   {
 #line 883
   __cil_tmp39 = dev->pci_device;
 #line 883
   if (__cil_tmp39 == 70) {
     {
 #line 884
     ironlake_enable_drps(dev);
 #line 885
     intel_init_emon(dev);
     }
   } else {
 
   }
   }
   {
 #line 888
   __cil_tmp40 = dev->dev_private;
 #line 888
   __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
 #line 888
   __cil_tmp42 = __cil_tmp41->info;
 #line 888
   __cil_tmp43 = __cil_tmp42->gen;
 #line 888
   __cil_tmp44 = (unsigned char )__cil_tmp43;
 #line 888
   __cil_tmp45 = (unsigned int )__cil_tmp44;
 #line 888
   if (__cil_tmp45 == 6U) {
     {
 #line 889
     gen6_enable_rps(dev_priv);
     }
   } else {
 
   }
   }
   {
 #line 891
   __cil_tmp46 = & dev->struct_mutex;
 #line 891
   mutex_lock_nested(__cil_tmp46, 0U);
 #line 894
   __cil_tmp47 = dev_priv->saveCACHE_MODE_0;
 #line 894
   __cil_tmp48 = __cil_tmp47 | 4294901760U;
 #line 894
   i915_write32(dev_priv, 8480U, __cil_tmp48);
 #line 897
   __cil_tmp49 = dev_priv->saveMI_ARB_STATE;
 #line 897
   __cil_tmp50 = __cil_tmp49 | 4294901760U;
 #line 897
   i915_write32(dev_priv, 8420U, __cil_tmp50);
 #line 899
   i = 0;
   }
 #line 899
   goto ldv_37723;
   ldv_37722: 
   {
 #line 900
   __cil_tmp51 = i << 2;
 #line 900
   __cil_tmp52 = __cil_tmp51 + 463888;
 #line 900
   __cil_tmp53 = (u32 )__cil_tmp52;
 #line 900
   __cil_tmp54 = dev_priv->saveSWF0[i];
 #line 900
   i915_write32(dev_priv, __cil_tmp53, __cil_tmp54);
 #line 901
   __cil_tmp55 = i << 2;
 #line 901
   __cil_tmp56 = __cil_tmp55 + 459792;
 #line 901
   __cil_tmp57 = (u32 )__cil_tmp56;
 #line 901
   __cil_tmp58 = dev_priv->saveSWF1[i];
 #line 901
   i915_write32(dev_priv, __cil_tmp57, __cil_tmp58);
 #line 899
   i = i + 1;
   }
   ldv_37723: ;
 #line 899
   if (i <= 15) {
 #line 900
     goto ldv_37722;
   } else {
 #line 902
     goto ldv_37724;
   }
   ldv_37724: 
 #line 903
   i = 0;
 #line 903
   goto ldv_37726;
   ldv_37725: 
   {
 #line 904
   __cil_tmp59 = i << 2;
 #line 904
   __cil_tmp60 = __cil_tmp59 + 467988;
 #line 904
   __cil_tmp61 = (u32 )__cil_tmp60;
 #line 904
   __cil_tmp62 = dev_priv->saveSWF2[i];
 #line 904
   i915_write32(dev_priv, __cil_tmp61, __cil_tmp62);
 #line 903
   i = i + 1;
   }
   ldv_37726: ;
 #line 903
   if (i <= 2) {
 #line 904
     goto ldv_37725;
   } else {
 #line 906
     goto ldv_37727;
   }
   ldv_37727: 
   {
 #line 906
   __cil_tmp63 = & dev->struct_mutex;
 #line 906
   mutex_unlock(__cil_tmp63);
 #line 908
   intel_i2c_reset(dev);
   }
 #line 910
   return (0);
 }
 }
 #line 74 "include/linux/list.h"
 __inline static void list_add_tail(struct list_head *new , struct list_head *head ) 
 { struct list_head *__cil_tmp3 ;
 
   {
   {
 #line 76
   __cil_tmp3 = head->prev;
 #line 76
   __list_add(new, __cil_tmp3, head);
   }
 #line 77
   return;
 }
 }
 #line 111
 extern void __list_del_entry(struct list_head * ) ;
 #line 112
 extern void list_del(struct list_head * ) ;
 #line 142 "include/linux/list.h"
 __inline static void list_del_init(struct list_head *entry ) 
 { 
 
   {
   {
 #line 144
   __list_del_entry(entry);
 #line 145
   INIT_LIST_HEAD(entry);
   }
 #line 146
   return;
 }
 }
 #line 153 "include/linux/list.h"
 __inline static void list_move(struct list_head *list , struct list_head *head ) 
 { 
 
   {
   {
 #line 155
   __list_del_entry(list);
 #line 156
   list_add(list, head);
   }
 #line 157
   return;
 }
 }
 #line 164 "include/linux/list.h"
 __inline static void list_move_tail(struct list_head *list , struct list_head *head ) 
 { 
 
   {
   {
 #line 167
   __list_del_entry(list);
 #line 168
   list_add_tail(list, head);
   }
 #line 169
   return;
 }
 }
 #line 60 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/bitops.h"
 __inline static void set_bit(unsigned int nr , unsigned long volatile   *addr ) 
 { long volatile   *__cil_tmp3 ;
 
   {
 #line 68
   __cil_tmp3 = (long volatile   *)addr;
 #line 68
   __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; bts %1,%0": "+m" (*__cil_tmp3): "Ir" (nr): "memory");
 #line 70
   return;
 }
 }
 #line 395 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/bitops.h"
 __inline static int ffs(int x ) 
 { int r ;
 
   {
 #line 399
   __asm__  ("bsfl %1,%0\n\tcmovzl %2,%0": "=r" (r): "rm" (x), "r" (-1));
 #line 408
   return (r + 1);
 }
 }
 #line 125 "include/linux/kernel.h"
 extern void __might_sleep(char const   * , int  , int  ) ;
 #line 34 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/string_64.h"
 extern void *__memcpy(void * , void const   * , size_t  ) ;
 #line 62 "include/linux/thread_info.h"
 __inline static void set_ti_thread_flag(struct thread_info *ti , int flag ) 
 { unsigned int __cil_tmp3 ;
   __u32 *__cil_tmp4 ;
   unsigned long volatile   *__cil_tmp5 ;
 
   {
   {
 #line 64
   __cil_tmp3 = (unsigned int )flag;
 #line 64
   __cil_tmp4 = & ti->flags;
 #line 64
   __cil_tmp5 = (unsigned long volatile   *)__cil_tmp4;
 #line 64
   set_bit(__cil_tmp3, __cil_tmp5);
   }
 #line 65
   return;
 }
 }
 #line 584 "include/linux/wait.h"
 extern void prepare_to_wait(wait_queue_head_t * , wait_queue_t * , int  ) ;
 #line 586
 extern void finish_wait(wait_queue_head_t * , wait_queue_t * ) ;
 #line 589
 extern int autoremove_wake_function(wait_queue_t * , unsigned int  , int  , void * ) ;
 #line 79 "include/linux/rwsem.h"
 extern void down_read(struct rw_semaphore * ) ;
 #line 89
 extern void down_write(struct rw_semaphore * ) ;
 #line 99
 extern void up_read(struct rw_semaphore * ) ;
 #line 104
 extern void up_write(struct rw_semaphore * ) ;
 #line 352 "include/linux/workqueue.h"
 extern int queue_delayed_work(struct workqueue_struct * , struct delayed_work * ,
                               unsigned long  ) ;
 #line 73 "include/linux/completion.h"
 __inline static void init_completion(struct completion *x ) 
 { struct lock_class_key __key ;
   wait_queue_head_t *__cil_tmp3 ;
 
   {
   {
 #line 75
   x->done = 0U;
 #line 76
   __cil_tmp3 = & x->wait;
 #line 76
   __init_waitqueue_head(__cil_tmp3, & __key);
   }
 #line 78
   return;
 }
 }
 #line 80
 extern int wait_for_completion_interruptible(struct completion * ) ;
 #line 61 "include/linux/vmalloc.h"
 extern void *__vmalloc(unsigned long  , gfp_t  , pgprot_t  ) ;
 #line 65
 extern void vfree(void const   * ) ;
 #line 217 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void memcpy_toio(void volatile   *dst , void const   *src , size_t count ) 
 { size_t __len ;
   void *__ret ;
   void *__cil_tmp6 ;
 
   {
   {
 #line 219
   __len = count;
 #line 219
   __cil_tmp6 = (void *)dst;
 #line 219
   __ret = __builtin_memcpy(__cil_tmp6, src, __len);
   }
 #line 221
   return;
 }
 }
 #line 25 "include/linux/kref.h"
 extern void kref_get(struct kref * ) ;
 #line 26
 extern int kref_put(struct kref * , void (*)(struct kref * ) ) ;
 #line 421 "include/linux/dcache.h"
 extern int sysctl_vfs_cache_pressure ;
 #line 202 "include/linux/page-flags.h"
 __inline static void SetPageDirty(struct page *page ) 
 { unsigned long *__cil_tmp2 ;
   unsigned long volatile   *__cil_tmp3 ;
 
   {
   {
 #line 202
   __cil_tmp2 = & page->flags;
 #line 202
   __cil_tmp3 = (unsigned long volatile   *)__cil_tmp2;
 #line 202
   set_bit(4U, __cil_tmp3);
   }
 #line 203
   return;
 }
 }
 #line 299 "include/linux/mm.h"
 __inline static int is_vmalloc_addr(void const   *x ) 
 { unsigned long addr ;
   int tmp ;
 
   {
 #line 302
   addr = (unsigned long )x;
 #line 304
   if (addr > 1152861031467319295UL) {
 #line 304
     if (addr <= 1152896215839408126UL) {
 #line 304
       tmp = 1;
     } else {
 #line 304
       tmp = 0;
     }
   } else {
 #line 304
     tmp = 0;
   }
 #line 304
   return (tmp);
 }
 }
 #line 433
 extern void put_page(struct page * ) ;
 #line 720 "include/linux/mm.h"
 __inline static void *lowmem_page_address(struct page *page ) 
 { long __cil_tmp2 ;
   long __cil_tmp3 ;
   long __cil_tmp4 ;
   unsigned long long __cil_tmp5 ;
   unsigned long long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
 
   {
   {
 #line 722
   __cil_tmp2 = (long )page;
 #line 722
   __cil_tmp3 = __cil_tmp2 + 24189255811072L;
 #line 722
   __cil_tmp4 = __cil_tmp3 / 56L;
 #line 722
   __cil_tmp5 = (unsigned long long )__cil_tmp4;
 #line 722
   __cil_tmp6 = __cil_tmp5 << 12;
 #line 722
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 722
   __cil_tmp8 = __cil_tmp7 + 1152789563211513856UL;
 #line 722
   return ((void *)__cil_tmp8);
   }
 }
 }
 #line 934
 extern void unmap_mapping_range(struct address_space * , loff_t  , loff_t  , int  ) ;
 #line 982
 extern int get_user_pages(struct task_struct * , struct mm_struct * , unsigned long  ,
                           int  , int  , int  , struct page ** , struct vm_area_struct ** ) ;
 #line 1000
 extern int set_page_dirty(struct page * ) ;
 #line 1161
 extern void register_shrinker(struct shrinker * ) ;
 #line 1426
 extern unsigned long do_mmap_pgoff(struct file * , unsigned long  , unsigned long  ,
                                    unsigned long  , unsigned long  , unsigned long  ) ;
 #line 1433 "include/linux/mm.h"
 __inline static unsigned long do_mmap(struct file *file , unsigned long addr , unsigned long len ,
                                       unsigned long prot , unsigned long flag , unsigned long offset ) 
 { unsigned long ret ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
 
   {
 #line 1437
   ret = 1152921504606846954UL;
   {
 #line 1438
   __cil_tmp8 = len + 4095UL;
 #line 1438
   __cil_tmp9 = __cil_tmp8 & 1152921504606842880UL;
 #line 1438
   __cil_tmp10 = __cil_tmp9 + offset;
 #line 1438
   if (__cil_tmp10 < offset) {
 #line 1439
     goto out;
   } else {
 
   }
   }
   {
 #line 1440
   __cil_tmp11 = offset & 4095UL;
 #line 1440
   if (__cil_tmp11 == 0UL) {
     {
 #line 1441
     __cil_tmp12 = offset >> 12;
 #line 1441
     ret = do_mmap_pgoff(file, addr, len, prot, flag, __cil_tmp12);
     }
   } else {
 
   }
   }
   out: ;
 #line 1443
   return (ret);
 }
 }
 #line 1534
 extern int vm_insert_pfn(struct vm_area_struct * , unsigned long  , unsigned long  ) ;
 #line 119 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess.h"
 extern int __get_user_bad(void) ;
 #line 220
 extern void __put_user_bad(void) ;
 #line 20 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 extern unsigned long copy_user_generic_string(void * , void const   * , unsigned int  ) ;
 #line 22
 extern unsigned long copy_user_generic_unrolled(void * , void const   * , unsigned int  ) ;
 #line 25 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 __inline static unsigned long copy_user_generic(void *to , void const   *from , unsigned int len ) 
 { unsigned int ret ;
 
   {
 #line 29
   __asm__  volatile   ("661:\n\tcall %P4\n662:\n.section .altinstructions,\"a\"\n .balign 8 \n .quad 661b\n .quad 663f\n\t .word (3*32+16)\n\t .byte 662b-661b\n\t .byte 664f-663f\n.previous\n.section .discard,\"aw\",@progbits\n\t .byte 0xff + (664f-663f) - (662b-661b)\n.previous\n.section .altinstr_replacement, \"ax\"\n663:\n\tcall %P5\n664:\n.previous": "=a" (ret),
                        "=D" (to), "=S" (from), "=d" (len): [old] "i" (& copy_user_generic_unrolled),
                        [new] "i" (& copy_user_generic_string), "1" (to), "2" (from),
                        "3" (len): "memory", "rcx", "r8", "r9", "r10", "r11");
 #line 36
   return ((unsigned long )ret);
 }
 }
 #line 222 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 __inline static int __copy_from_user_inatomic(void *dst , void const   *src , unsigned int size ) 
 { unsigned long tmp ;
 
   {
   {
 #line 224
   tmp = copy_user_generic(dst, src, size);
   }
 #line 224
   return ((int )tmp);
 }
 }
 #line 233
 extern long __copy_user_nocache(void * , void const   * , unsigned int  , int  ) ;
 #line 244 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/uaccess_64.h"
 __inline static int __copy_from_user_inatomic_nocache(void *dst , void const   *src ,
                                                       unsigned int size ) 
 { long tmp ;
 
   {
   {
 #line 247
   tmp = __copy_user_nocache(dst, src, size, 0);
   }
 #line 247
   return ((int )tmp);
 }
 }
 #line 361 "include/linux/sched.h"
 extern void schedule(void) ;
 #line 16 "include/linux/uaccess.h"
 __inline static void pagefault_disable(void) 
 { struct thread_info *tmp ;
   int __cil_tmp2 ;
 
   {
   {
 #line 18
   tmp = current_thread_info();
 #line 18
   __cil_tmp2 = tmp->preempt_count;
 #line 18
   tmp->preempt_count = __cil_tmp2 + 1;
 #line 23
   __asm__  volatile   ("": : : "memory");
   }
 #line 24
   return;
 }
 }
 #line 26 "include/linux/uaccess.h"
 __inline static void pagefault_enable(void) 
 { struct thread_info *tmp ;
   int __cil_tmp2 ;
 
   {
   {
 #line 32
   __asm__  volatile   ("": : : "memory");
 #line 33
   tmp = current_thread_info();
 #line 33
   __cil_tmp2 = tmp->preempt_count;
 #line 33
   tmp->preempt_count = __cil_tmp2 + -1;
 #line 37
   __asm__  volatile   ("": : : "memory");
   }
 #line 38
   return;
 }
 }
 #line 98 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/cacheflush.h"
 extern int set_memory_wc(unsigned long  , int  ) ;
 #line 99
 extern int set_memory_wb(unsigned long  , int  ) ;
 #line 48 "include/linux/highmem.h"
 __inline static void *kmap(struct page *page ) 
 { void *tmp ;
 
   {
   {
 #line 50
   __might_sleep("include/linux/highmem.h", 50, 0);
 #line 51
   tmp = lowmem_page_address(page);
   }
 #line 51
   return (tmp);
 }
 }
 #line 54 "include/linux/highmem.h"
 __inline static void kunmap(struct page *page ) 
 { 
 
   {
 #line 56
   return;
 }
 }
 #line 58 "include/linux/highmem.h"
 __inline static void *__kmap_atomic(struct page *page ) 
 { void *tmp ;
 
   {
   {
 #line 60
   pagefault_disable();
 #line 61
   tmp = lowmem_page_address(page);
   }
 #line 61
   return (tmp);
 }
 }
 #line 65 "include/linux/highmem.h"
 __inline static void __kunmap_atomic(void *addr ) 
 { 
 
   {
   {
 #line 67
   pagefault_enable();
   }
 #line 68
   return;
 }
 }
 #line 56 "include/linux/pagemap.h"
 __inline static gfp_t mapping_gfp_mask(struct address_space *mapping ) 
 { unsigned long __cil_tmp2 ;
   gfp_t __cil_tmp3 ;
 
   {
   {
 #line 58
   __cil_tmp2 = mapping->flags;
 #line 58
   __cil_tmp3 = (gfp_t )__cil_tmp2;
 #line 58
   return (__cil_tmp3 & 8388607U);
   }
 }
 }
 #line 65 "include/linux/pagemap.h"
 __inline static void mapping_set_gfp_mask(struct address_space *m , gfp_t mask ) 
 { unsigned long __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
 
   {
 #line 67
   __cil_tmp3 = (unsigned long )mask;
 #line 67
   __cil_tmp4 = m->flags;
 #line 67
   __cil_tmp5 = __cil_tmp4 & 1152921504598458368UL;
 #line 67
   m->flags = __cil_tmp5 | __cil_tmp3;
 #line 69
   return;
 }
 }
 #line 410 "include/linux/pagemap.h"
 __inline static int fault_in_pages_writeable(char *uaddr , int size ) 
 { int ret ;
   long tmp ;
   int __pu_err ;
   char *end ;
   int __pu_err___0 ;
   int __cil_tmp8 ;
   long __cil_tmp9 ;
   struct __large_struct *__cil_tmp10 ;
   struct __large_struct *__cil_tmp11 ;
   struct __large_struct *__cil_tmp12 ;
   struct __large_struct *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct __large_struct *__cil_tmp20 ;
   struct __large_struct *__cil_tmp21 ;
   struct __large_struct *__cil_tmp22 ;
   struct __large_struct *__cil_tmp23 ;
 
   {
   {
 #line 414
   __cil_tmp8 = size == 0;
 #line 414
   __cil_tmp9 = (long )__cil_tmp8;
 #line 414
   tmp = __builtin_expect(__cil_tmp9, 0L);
   }
 #line 414
   if (tmp != 0L) {
 #line 415
     return (0);
   } else {
 
   }
 #line 421
   __pu_err = 0;
 #line 421
   if (1) {
 #line 421
     goto case_1;
   } else {
 #line 421
     goto switch_default;
 #line 421
     if (0) {
       case_1: 
 #line 421
       __cil_tmp10 = (struct __large_struct *)uaddr;
 #line 421
       __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "iq" (0),
                            "m" (*__cil_tmp10), "i" (-14), "0" (__pu_err));
 #line 421
       goto ldv_28703;
 #line 421
       __cil_tmp11 = (struct __large_struct *)uaddr;
 #line 421
       __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (0),
                            "m" (*__cil_tmp11), "i" (-14), "0" (__pu_err));
 #line 421
       goto ldv_28703;
 #line 421
       __cil_tmp12 = (struct __large_struct *)uaddr;
 #line 421
       __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (0),
                            "m" (*__cil_tmp12), "i" (-14), "0" (__pu_err));
 #line 421
       goto ldv_28703;
 #line 421
       __cil_tmp13 = (struct __large_struct *)uaddr;
 #line 421
       __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "er" (0),
                            "m" (*__cil_tmp13), "i" (-14), "0" (__pu_err));
 #line 421
       goto ldv_28703;
       switch_default: 
       {
 #line 421
       __put_user_bad();
       }
     } else {
 
     }
   }
   ldv_28703: 
 #line 421
   ret = __pu_err;
 #line 422
   if (ret == 0) {
 #line 423
     __cil_tmp14 = (unsigned long )size;
 #line 423
     __cil_tmp15 = __cil_tmp14 + 1152921504606846975UL;
 #line 423
     end = uaddr + __cil_tmp15;
     {
 #line 429
     __cil_tmp16 = (unsigned long )end;
 #line 429
     __cil_tmp17 = (unsigned long )uaddr;
 #line 429
     __cil_tmp18 = __cil_tmp17 ^ __cil_tmp16;
 #line 429
     __cil_tmp19 = __cil_tmp18 & 1152921504606842880UL;
 #line 429
     if (__cil_tmp19 != 0UL) {
 #line 431
       __pu_err___0 = 0;
 #line 431
       if (1) {
 #line 431
         goto case_1___0;
       } else {
 #line 431
         goto switch_default___0;
 #line 431
         if (0) {
           case_1___0: 
 #line 431
           __cil_tmp20 = (struct __large_struct *)end;
 #line 431
           __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "iq" (0),
                                "m" (*__cil_tmp20), "i" (-14), "0" (__pu_err___0));
 #line 431
           goto ldv_28712;
 #line 431
           __cil_tmp21 = (struct __large_struct *)end;
 #line 431
           __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (0),
                                "m" (*__cil_tmp21), "i" (-14), "0" (__pu_err___0));
 #line 431
           goto ldv_28712;
 #line 431
           __cil_tmp22 = (struct __large_struct *)end;
 #line 431
           __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (0),
                                "m" (*__cil_tmp22), "i" (-14), "0" (__pu_err___0));
 #line 431
           goto ldv_28712;
 #line 431
           __cil_tmp23 = (struct __large_struct *)end;
 #line 431
           __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "er" (0),
                                "m" (*__cil_tmp23), "i" (-14), "0" (__pu_err___0));
 #line 431
           goto ldv_28712;
           switch_default___0: 
           {
 #line 431
           __put_user_bad();
           }
         } else {
 
         }
       }
       ldv_28712: 
 #line 431
       ret = __pu_err___0;
     } else {
 
     }
     }
   } else {
 
   }
 #line 433
   return (ret);
 }
 }
 #line 436 "include/linux/pagemap.h"
 __inline static int fault_in_pages_readable(char const   *uaddr , int size ) 
 { char volatile   c ;
   int ret ;
   long tmp ;
   int __gu_err ;
   unsigned long __gu_val ;
   int tmp___0 ;
   char const   *end ;
   int __gu_err___0 ;
   unsigned long __gu_val___0 ;
   int tmp___1 ;
   int __cil_tmp13 ;
   long __cil_tmp14 ;
   struct __large_struct *__cil_tmp15 ;
   struct __large_struct *__cil_tmp16 ;
   struct __large_struct *__cil_tmp17 ;
   struct __large_struct *__cil_tmp18 ;
   char __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct __large_struct *__cil_tmp26 ;
   struct __large_struct *__cil_tmp27 ;
   struct __large_struct *__cil_tmp28 ;
   struct __large_struct *__cil_tmp29 ;
   char __cil_tmp30 ;
 
   {
   {
 #line 441
   __cil_tmp13 = size == 0;
 #line 441
   __cil_tmp14 = (long )__cil_tmp13;
 #line 441
   tmp = __builtin_expect(__cil_tmp14, 0L);
   }
 #line 441
   if (tmp != 0L) {
 #line 442
     return (0);
   } else {
 
   }
 #line 444
   __gu_err = 0;
 #line 444
   if (1) {
 #line 444
     goto case_1;
   } else {
 #line 444
     goto switch_default;
 #line 444
     if (0) {
       case_1: 
 #line 444
       __cil_tmp15 = (struct __large_struct *)uaddr;
 #line 444
       __asm__  volatile   ("1:\tmovb %2,%b1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorb %b1,%b1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err),
                            "=q" (__gu_val): "m" (*__cil_tmp15), "i" (-14), "0" (__gu_err));
 #line 444
       goto ldv_28727;
 #line 444
       __cil_tmp16 = (struct __large_struct *)uaddr;
 #line 444
       __asm__  volatile   ("1:\tmovw %2,%w1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorw %w1,%w1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err),
                            "=r" (__gu_val): "m" (*__cil_tmp16), "i" (-14), "0" (__gu_err));
 #line 444
       goto ldv_28727;
 #line 444
       __cil_tmp17 = (struct __large_struct *)uaddr;
 #line 444
       __asm__  volatile   ("1:\tmovl %2,%k1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorl %k1,%k1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err),
                            "=r" (__gu_val): "m" (*__cil_tmp17), "i" (-14), "0" (__gu_err));
 #line 444
       goto ldv_28727;
 #line 444
       __cil_tmp18 = (struct __large_struct *)uaddr;
 #line 444
       __asm__  volatile   ("1:\tmovq %2,%1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorq %1,%1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err),
                            "=r" (__gu_val): "m" (*__cil_tmp18), "i" (-14), "0" (__gu_err));
 #line 444
       goto ldv_28727;
       switch_default: 
       {
 #line 444
       tmp___0 = __get_user_bad();
 #line 444
       __gu_val = (unsigned long )tmp___0;
       }
     } else {
 
     }
   }
   ldv_28727: 
 #line 444
   __cil_tmp19 = (char )__gu_val;
 #line 444
   c = (char volatile   )__cil_tmp19;
 #line 444
   ret = __gu_err;
 #line 445
   if (ret == 0) {
 #line 446
     __cil_tmp20 = (unsigned long )size;
 #line 446
     __cil_tmp21 = __cil_tmp20 + 1152921504606846975UL;
 #line 446
     end = uaddr + __cil_tmp21;
     {
 #line 448
     __cil_tmp22 = (unsigned long )end;
 #line 448
     __cil_tmp23 = (unsigned long )uaddr;
 #line 448
     __cil_tmp24 = __cil_tmp23 ^ __cil_tmp22;
 #line 448
     __cil_tmp25 = __cil_tmp24 & 1152921504606842880UL;
 #line 448
     if (__cil_tmp25 != 0UL) {
 #line 450
       __gu_err___0 = 0;
 #line 450
       if (1) {
 #line 450
         goto case_1___0;
       } else {
 #line 450
         goto switch_default___0;
 #line 450
         if (0) {
           case_1___0: 
 #line 450
           __cil_tmp26 = (struct __large_struct *)end;
 #line 450
           __asm__  volatile   ("1:\tmovb %2,%b1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorb %b1,%b1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err___0),
                                "=q" (__gu_val___0): "m" (*__cil_tmp26), "i" (-14),
                                "0" (__gu_err___0));
 #line 450
           goto ldv_28737;
 #line 450
           __cil_tmp27 = (struct __large_struct *)end;
 #line 450
           __asm__  volatile   ("1:\tmovw %2,%w1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorw %w1,%w1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err___0),
                                "=r" (__gu_val___0): "m" (*__cil_tmp27), "i" (-14),
                                "0" (__gu_err___0));
 #line 450
           goto ldv_28737;
 #line 450
           __cil_tmp28 = (struct __large_struct *)end;
 #line 450
           __asm__  volatile   ("1:\tmovl %2,%k1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorl %k1,%k1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err___0),
                                "=r" (__gu_val___0): "m" (*__cil_tmp28), "i" (-14),
                                "0" (__gu_err___0));
 #line 450
           goto ldv_28737;
 #line 450
           __cil_tmp29 = (struct __large_struct *)end;
 #line 450
           __asm__  volatile   ("1:\tmovq %2,%1\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\txorq %1,%1\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__gu_err___0),
                                "=r" (__gu_val___0): "m" (*__cil_tmp29), "i" (-14),
                                "0" (__gu_err___0));
 #line 450
           goto ldv_28737;
           switch_default___0: 
           {
 #line 450
           tmp___1 = __get_user_bad();
 #line 450
           __gu_val___0 = (unsigned long )tmp___1;
           }
         } else {
 
         }
       }
       ldv_28737: 
 #line 450
       __cil_tmp30 = (char )__gu_val___0;
 #line 450
       c = (char volatile   )__cil_tmp30;
 #line 450
       ret = __gu_err___0;
     } else {
 
     }
     }
   } else {
 
   }
 #line 454
   return (ret);
 }
 }
 #line 53 "include/drm/drm_hashtab.h"
 extern int drm_ht_insert_item(struct drm_open_hash * , struct drm_hash_item * ) ;
 #line 61
 extern int drm_ht_remove_item(struct drm_open_hash * , struct drm_hash_item * ) ;
 #line 104 "include/drm/drm_mm.h"
 extern struct drm_mm_node *drm_mm_get_block_range_generic(struct drm_mm_node * , unsigned long  ,
                                                           unsigned int  , unsigned long  ,
                                                           unsigned long  , int  ) ;
 #line 156
 extern struct drm_mm_node *drm_mm_search_free_in_range(struct drm_mm  const  * , unsigned long  ,
                                                        unsigned int  , unsigned long  ,
                                                        unsigned long  , int  ) ;
 #line 1328 "include/drm/drmP.h"
 extern void drm_clflush_pages(struct page ** , unsigned long  ) ;
 #line 1536
 extern void drm_gem_object_release(struct drm_gem_object * ) ;
 #line 1537
 extern void drm_gem_object_free(struct kref * ) ;
 #line 1540
 extern int drm_gem_object_init(struct drm_device * , struct drm_gem_object * , size_t  ) ;
 #line 1550 "include/drm/drmP.h"
 __inline static void drm_gem_object_reference(struct drm_gem_object *obj ) 
 { struct kref *__cil_tmp2 ;
 
   {
   {
 #line 1552
   __cil_tmp2 = & obj->refcount;
 #line 1552
   kref_get(__cil_tmp2);
   }
 #line 1553
   return;
 }
 }
 #line 1556 "include/drm/drmP.h"
 __inline static void drm_gem_object_unreference(struct drm_gem_object *obj ) 
 { struct drm_gem_object *__cil_tmp2 ;
   unsigned long __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   struct kref *__cil_tmp5 ;
 
   {
   {
 #line 1558
   __cil_tmp2 = (struct drm_gem_object *)0;
 #line 1558
   __cil_tmp3 = (unsigned long )__cil_tmp2;
 #line 1558
   __cil_tmp4 = (unsigned long )obj;
 #line 1558
   if (__cil_tmp4 != __cil_tmp3) {
     {
 #line 1559
     __cil_tmp5 = & obj->refcount;
 #line 1559
     kref_put(__cil_tmp5, & drm_gem_object_free);
     }
   } else {
 
   }
   }
 #line 1560
   return;
 }
 }
 #line 1563 "include/drm/drmP.h"
 __inline static void drm_gem_object_unreference_unlocked(struct drm_gem_object *obj ) 
 { struct drm_device *dev ;
   struct drm_gem_object *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   struct mutex *__cil_tmp6 ;
   struct kref *__cil_tmp7 ;
   struct mutex *__cil_tmp8 ;
 
   {
   {
 #line 1565
   __cil_tmp3 = (struct drm_gem_object *)0;
 #line 1565
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1565
   __cil_tmp5 = (unsigned long )obj;
 #line 1565
   if (__cil_tmp5 != __cil_tmp4) {
     {
 #line 1566
     dev = obj->dev;
 #line 1567
     __cil_tmp6 = & dev->struct_mutex;
 #line 1567
     mutex_lock_nested(__cil_tmp6, 0U);
 #line 1568
     __cil_tmp7 = & obj->refcount;
 #line 1568
     kref_put(__cil_tmp7, & drm_gem_object_free);
 #line 1569
     __cil_tmp8 = & dev->struct_mutex;
 #line 1569
     mutex_unlock(__cil_tmp8);
     }
   } else {
 
   }
   }
 #line 1571
   return;
 }
 }
 #line 1573
 extern int drm_gem_handle_create(struct drm_file * , struct drm_gem_object * , u32 * ) ;
 #line 1576
 extern int drm_gem_handle_delete(struct drm_file * , u32  ) ;
 #line 1623
 extern struct drm_gem_object *drm_gem_object_lookup(struct drm_device * , struct drm_file * ,
                                                     u32  ) ;
 #line 45 "include/drm/drm_mem_util.h"
 __inline static void *drm_malloc_ab(size_t nmemb , size_t size ) 
 { void *tmp ;
   pgprot_t __constr_expr_0 ;
   void *tmp___0 ;
   unsigned long __cil_tmp6 ;
   size_t __cil_tmp7 ;
   size_t __cil_tmp8 ;
   size_t __cil_tmp9 ;
 
   {
 #line 47
   if (size != 0UL) {
     {
 #line 47
     __cil_tmp6 = 1152921504606846975UL / size;
 #line 47
     if (__cil_tmp6 < nmemb) {
 #line 48
       return ((void *)0);
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 50
   __cil_tmp7 = size * nmemb;
 #line 50
   if (__cil_tmp7 <= 4096UL) {
     {
 #line 51
     __cil_tmp8 = nmemb * size;
 #line 51
     tmp = kmalloc(__cil_tmp8, 208U);
     }
 #line 51
     return (tmp);
   } else {
 
   }
   }
   {
 #line 53
   __constr_expr_0.pgprot = 355UL;
 #line 53
   __cil_tmp9 = size * nmemb;
 #line 53
   tmp___0 = __vmalloc(__cil_tmp9, 210U, __constr_expr_0);
   }
 #line 53
   return (tmp___0);
 }
 }
 #line 57 "include/drm/drm_mem_util.h"
 __inline static void drm_free_large(void *ptr ) 
 { int tmp ;
   void const   *__cil_tmp3 ;
   void const   *__cil_tmp4 ;
 
   {
   {
 #line 59
   __cil_tmp3 = (void const   *)ptr;
 #line 59
   tmp = is_vmalloc_addr(__cil_tmp3);
   }
 #line 59
   if (tmp == 0) {
 #line 60
     return;
   } else {
 
   }
   {
 #line 62
   __cil_tmp4 = (void const   *)ptr;
 #line 62
   vfree(__cil_tmp4);
   }
 #line 63
   return;
 }
 }
 #line 187 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
 int intel_init_render_ring_buffer(struct drm_device *dev ) ;
 #line 188
 int intel_init_bsd_ring_buffer(struct drm_device *dev ) ;
 #line 189
 int intel_init_blt_ring_buffer(struct drm_device *dev ) ;
 #line 18 "include/drm/intel-gtt.h"
 extern void intel_gtt_chipset_flush(void) ;
 #line 20
 extern void intel_gtt_clear_range(unsigned int  , unsigned int  ) ;
 #line 34 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_create ;
 #line 34 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_create(struct drm_i915_gem_object *obj ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp10 ;
   struct tracepoint_func **__cil_tmp11 ;
   struct tracepoint_func * volatile  *__cil_tmp12 ;
   struct tracepoint_func * volatile  __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   struct tracepoint_func *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   void (*__cil_tmp19)(void * , struct drm_i915_gem_object * ) ;
   void *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
 
   {
   {
 #line 19
   __cil_tmp10 = & __tracepoint_i915_gem_object_create.key;
 #line 19
   tmp___1 = static_branch(__cil_tmp10);
   }
 #line 19
   if ((int )tmp___1) {
     {
 #line 19
     rcu_read_lock_sched_notrace();
 #line 19
     __cil_tmp11 = & __tracepoint_i915_gem_object_create.funcs;
 #line 19
     __cil_tmp12 = (struct tracepoint_func * volatile  *)__cil_tmp11;
 #line 19
     __cil_tmp13 = *__cil_tmp12;
 #line 19
     _________p1 = (struct tracepoint_func *)__cil_tmp13;
 #line 19
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 19
     if (tmp != 0) {
 #line 19
       if (! __warned) {
         {
 #line 19
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 19
         if (tmp___0 == 0) {
           {
 #line 19
           __warned = (bool )1;
 #line 19
           __cil_tmp14 = (int const   )34;
 #line 19
           __cil_tmp15 = (int )__cil_tmp14;
 #line 19
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp15);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 19
     it_func_ptr = _________p1;
     {
 #line 19
     __cil_tmp16 = (struct tracepoint_func *)0;
 #line 19
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 19
     __cil_tmp18 = (unsigned long )it_func_ptr;
 #line 19
     if (__cil_tmp18 != __cil_tmp17) {
       ldv_35728: 
       {
 #line 19
       it_func = it_func_ptr->func;
 #line 19
       __data = it_func_ptr->data;
 #line 19
       __cil_tmp19 = (void (*)(void * , struct drm_i915_gem_object * ))it_func;
 #line 19
       (*__cil_tmp19)(__data, obj);
 #line 19
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 19
       __cil_tmp20 = (void *)0;
 #line 19
       __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 19
       __cil_tmp22 = it_func_ptr->func;
 #line 19
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 19
       if (__cil_tmp23 != __cil_tmp21) {
 #line 20
         goto ldv_35728;
       } else {
 #line 22
         goto ldv_35729;
       }
       }
       ldv_35729: ;
     } else {
 
     }
     }
     {
 #line 19
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 21
   return;
 }
 }
 #line 57
 struct tracepoint __tracepoint_i915_gem_object_bind ;
 #line 57 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_bind(struct drm_i915_gem_object *obj ,
                                                 bool mappable ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct drm_i915_gem_object * , bool  ) ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   void *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
 
   {
   {
 #line 36
   __cil_tmp11 = & __tracepoint_i915_gem_object_bind.key;
 #line 36
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 36
   if ((int )tmp___1) {
     {
 #line 36
     rcu_read_lock_sched_notrace();
 #line 36
     __cil_tmp12 = & __tracepoint_i915_gem_object_bind.funcs;
 #line 36
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 36
     __cil_tmp14 = *__cil_tmp13;
 #line 36
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 36
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 36
     if (tmp != 0) {
 #line 36
       if (! __warned) {
         {
 #line 36
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 36
         if (tmp___0 == 0) {
           {
 #line 36
           __warned = (bool )1;
 #line 36
           __cil_tmp15 = (int const   )57;
 #line 36
           __cil_tmp16 = (int )__cil_tmp15;
 #line 36
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 36
     it_func_ptr = _________p1;
     {
 #line 36
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 36
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 36
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 36
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_35761: 
       {
 #line 36
       it_func = it_func_ptr->func;
 #line 36
       __data = it_func_ptr->data;
 #line 36
       __cil_tmp20 = (void (*)(void * , struct drm_i915_gem_object * , bool  ))it_func;
 #line 36
       __cil_tmp21 = (int )mappable;
 #line 36
       __cil_tmp22 = (bool )__cil_tmp21;
 #line 36
       (*__cil_tmp20)(__data, obj, __cil_tmp22);
 #line 36
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 36
       __cil_tmp23 = (void *)0;
 #line 36
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 36
       __cil_tmp25 = it_func_ptr->func;
 #line 36
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 36
       if (__cil_tmp26 != __cil_tmp24) {
 #line 37
         goto ldv_35761;
       } else {
 #line 39
         goto ldv_35762;
       }
       }
       ldv_35762: ;
     } else {
 
     }
     }
     {
 #line 36
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 38
   return;
 }
 }
 #line 77
 struct tracepoint __tracepoint_i915_gem_object_unbind ;
 #line 77 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_unbind(struct drm_i915_gem_object *obj ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp10 ;
   struct tracepoint_func **__cil_tmp11 ;
   struct tracepoint_func * volatile  *__cil_tmp12 ;
   struct tracepoint_func * volatile  __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   struct tracepoint_func *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   void (*__cil_tmp19)(void * , struct drm_i915_gem_object * ) ;
   void *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
 
   {
   {
 #line 59
   __cil_tmp10 = & __tracepoint_i915_gem_object_unbind.key;
 #line 59
   tmp___1 = static_branch(__cil_tmp10);
   }
 #line 59
   if ((int )tmp___1) {
     {
 #line 59
     rcu_read_lock_sched_notrace();
 #line 59
     __cil_tmp11 = & __tracepoint_i915_gem_object_unbind.funcs;
 #line 59
     __cil_tmp12 = (struct tracepoint_func * volatile  *)__cil_tmp11;
 #line 59
     __cil_tmp13 = *__cil_tmp12;
 #line 59
     _________p1 = (struct tracepoint_func *)__cil_tmp13;
 #line 59
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 59
     if (tmp != 0) {
 #line 59
       if (! __warned) {
         {
 #line 59
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 59
         if (tmp___0 == 0) {
           {
 #line 59
           __warned = (bool )1;
 #line 59
           __cil_tmp14 = (int const   )77;
 #line 59
           __cil_tmp15 = (int )__cil_tmp14;
 #line 59
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp15);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 59
     it_func_ptr = _________p1;
     {
 #line 59
     __cil_tmp16 = (struct tracepoint_func *)0;
 #line 59
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 59
     __cil_tmp18 = (unsigned long )it_func_ptr;
 #line 59
     if (__cil_tmp18 != __cil_tmp17) {
       ldv_35795: 
       {
 #line 59
       it_func = it_func_ptr->func;
 #line 59
       __data = it_func_ptr->data;
 #line 59
       __cil_tmp19 = (void (*)(void * , struct drm_i915_gem_object * ))it_func;
 #line 59
       (*__cil_tmp19)(__data, obj);
 #line 59
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 59
       __cil_tmp20 = (void *)0;
 #line 59
       __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 59
       __cil_tmp22 = it_func_ptr->func;
 #line 59
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 59
       if (__cil_tmp23 != __cil_tmp21) {
 #line 60
         goto ldv_35795;
       } else {
 #line 62
         goto ldv_35796;
       }
       }
       ldv_35796: ;
     } else {
 
     }
     }
     {
 #line 59
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 61
   return;
 }
 }
 #line 101
 struct tracepoint __tracepoint_i915_gem_object_change_domain ;
 #line 101 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_change_domain(struct drm_i915_gem_object *obj ,
                                                          u32 old_read , u32 old_write ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp12 ;
   struct tracepoint_func **__cil_tmp13 ;
   struct tracepoint_func * volatile  *__cil_tmp14 ;
   struct tracepoint_func * volatile  __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   struct tracepoint_func *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void (*__cil_tmp21)(void * , struct drm_i915_gem_object * , u32  , u32  ) ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   void *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
 
   {
   {
 #line 79
   __cil_tmp12 = & __tracepoint_i915_gem_object_change_domain.key;
 #line 79
   tmp___1 = static_branch(__cil_tmp12);
   }
 #line 79
   if ((int )tmp___1) {
     {
 #line 79
     rcu_read_lock_sched_notrace();
 #line 79
     __cil_tmp13 = & __tracepoint_i915_gem_object_change_domain.funcs;
 #line 79
     __cil_tmp14 = (struct tracepoint_func * volatile  *)__cil_tmp13;
 #line 79
     __cil_tmp15 = *__cil_tmp14;
 #line 79
     _________p1 = (struct tracepoint_func *)__cil_tmp15;
 #line 79
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 79
     if (tmp != 0) {
 #line 79
       if (! __warned) {
         {
 #line 79
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 79
         if (tmp___0 == 0) {
           {
 #line 79
           __warned = (bool )1;
 #line 79
           __cil_tmp16 = (int const   )101;
 #line 79
           __cil_tmp17 = (int )__cil_tmp16;
 #line 79
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp17);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 79
     it_func_ptr = _________p1;
     {
 #line 79
     __cil_tmp18 = (struct tracepoint_func *)0;
 #line 79
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 79
     __cil_tmp20 = (unsigned long )it_func_ptr;
 #line 79
     if (__cil_tmp20 != __cil_tmp19) {
       ldv_35830: 
       {
 #line 79
       it_func = it_func_ptr->func;
 #line 79
       __data = it_func_ptr->data;
 #line 79
       __cil_tmp21 = (void (*)(void * , struct drm_i915_gem_object * , u32  , u32  ))it_func;
 #line 79
       (*__cil_tmp21)(__data, obj, old_read, old_write);
 #line 79
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 79
       __cil_tmp22 = (void *)0;
 #line 79
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 79
       __cil_tmp24 = it_func_ptr->func;
 #line 79
       __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 79
       if (__cil_tmp25 != __cil_tmp23) {
 #line 80
         goto ldv_35830;
       } else {
 #line 82
         goto ldv_35831;
       }
       }
       ldv_35831: ;
     } else {
 
     }
     }
     {
 #line 79
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 81
   return;
 }
 }
 #line 121
 struct tracepoint __tracepoint_i915_gem_object_pwrite ;
 #line 121 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_pwrite(struct drm_i915_gem_object *obj ,
                                                   u32 offset , u32 len ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp12 ;
   struct tracepoint_func **__cil_tmp13 ;
   struct tracepoint_func * volatile  *__cil_tmp14 ;
   struct tracepoint_func * volatile  __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   struct tracepoint_func *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void (*__cil_tmp21)(void * , struct drm_i915_gem_object * , u32  , u32  ) ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   void *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
 
   {
   {
 #line 103
   __cil_tmp12 = & __tracepoint_i915_gem_object_pwrite.key;
 #line 103
   tmp___1 = static_branch(__cil_tmp12);
   }
 #line 103
   if ((int )tmp___1) {
     {
 #line 103
     rcu_read_lock_sched_notrace();
 #line 103
     __cil_tmp13 = & __tracepoint_i915_gem_object_pwrite.funcs;
 #line 103
     __cil_tmp14 = (struct tracepoint_func * volatile  *)__cil_tmp13;
 #line 103
     __cil_tmp15 = *__cil_tmp14;
 #line 103
     _________p1 = (struct tracepoint_func *)__cil_tmp15;
 #line 103
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 103
     if (tmp != 0) {
 #line 103
       if (! __warned) {
         {
 #line 103
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 103
         if (tmp___0 == 0) {
           {
 #line 103
           __warned = (bool )1;
 #line 103
           __cil_tmp16 = (int const   )121;
 #line 103
           __cil_tmp17 = (int )__cil_tmp16;
 #line 103
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp17);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 103
     it_func_ptr = _________p1;
     {
 #line 103
     __cil_tmp18 = (struct tracepoint_func *)0;
 #line 103
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 103
     __cil_tmp20 = (unsigned long )it_func_ptr;
 #line 103
     if (__cil_tmp20 != __cil_tmp19) {
       ldv_35871: 
       {
 #line 103
       it_func = it_func_ptr->func;
 #line 103
       __data = it_func_ptr->data;
 #line 103
       __cil_tmp21 = (void (*)(void * , struct drm_i915_gem_object * , u32  , u32  ))it_func;
 #line 103
       (*__cil_tmp21)(__data, obj, offset, len);
 #line 103
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 103
       __cil_tmp22 = (void *)0;
 #line 103
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 103
       __cil_tmp24 = it_func_ptr->func;
 #line 103
       __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 103
       if (__cil_tmp25 != __cil_tmp23) {
 #line 104
         goto ldv_35871;
       } else {
 #line 106
         goto ldv_35872;
       }
       }
       ldv_35872: ;
     } else {
 
     }
     }
     {
 #line 103
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 105
   return;
 }
 }
 #line 141
 struct tracepoint __tracepoint_i915_gem_object_pread ;
 #line 141 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_pread(struct drm_i915_gem_object *obj ,
                                                  u32 offset , u32 len ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp12 ;
   struct tracepoint_func **__cil_tmp13 ;
   struct tracepoint_func * volatile  *__cil_tmp14 ;
   struct tracepoint_func * volatile  __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   struct tracepoint_func *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void (*__cil_tmp21)(void * , struct drm_i915_gem_object * , u32  , u32  ) ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   void *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
 
   {
   {
 #line 123
   __cil_tmp12 = & __tracepoint_i915_gem_object_pread.key;
 #line 123
   tmp___1 = static_branch(__cil_tmp12);
   }
 #line 123
   if ((int )tmp___1) {
     {
 #line 123
     rcu_read_lock_sched_notrace();
 #line 123
     __cil_tmp13 = & __tracepoint_i915_gem_object_pread.funcs;
 #line 123
     __cil_tmp14 = (struct tracepoint_func * volatile  *)__cil_tmp13;
 #line 123
     __cil_tmp15 = *__cil_tmp14;
 #line 123
     _________p1 = (struct tracepoint_func *)__cil_tmp15;
 #line 123
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 123
     if (tmp != 0) {
 #line 123
       if (! __warned) {
         {
 #line 123
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 123
         if (tmp___0 == 0) {
           {
 #line 123
           __warned = (bool )1;
 #line 123
           __cil_tmp16 = (int const   )141;
 #line 123
           __cil_tmp17 = (int )__cil_tmp16;
 #line 123
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp17);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 123
     it_func_ptr = _________p1;
     {
 #line 123
     __cil_tmp18 = (struct tracepoint_func *)0;
 #line 123
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 123
     __cil_tmp20 = (unsigned long )it_func_ptr;
 #line 123
     if (__cil_tmp20 != __cil_tmp19) {
       ldv_35912: 
       {
 #line 123
       it_func = it_func_ptr->func;
 #line 123
       __data = it_func_ptr->data;
 #line 123
       __cil_tmp21 = (void (*)(void * , struct drm_i915_gem_object * , u32  , u32  ))it_func;
 #line 123
       (*__cil_tmp21)(__data, obj, offset, len);
 #line 123
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 123
       __cil_tmp22 = (void *)0;
 #line 123
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 123
       __cil_tmp24 = it_func_ptr->func;
 #line 123
       __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 123
       if (__cil_tmp25 != __cil_tmp23) {
 #line 124
         goto ldv_35912;
       } else {
 #line 126
         goto ldv_35913;
       }
       }
       ldv_35913: ;
     } else {
 
     }
     }
     {
 #line 123
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 125
   return;
 }
 }
 #line 166
 struct tracepoint __tracepoint_i915_gem_object_fault ;
 #line 166 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_fault(struct drm_i915_gem_object *obj ,
                                                  u32 index , bool gtt , bool write ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp13 ;
   struct tracepoint_func **__cil_tmp14 ;
   struct tracepoint_func * volatile  *__cil_tmp15 ;
   struct tracepoint_func * volatile  __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct tracepoint_func *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void (*__cil_tmp22)(void * , struct drm_i915_gem_object * , u32  , bool  , bool  ) ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   bool __cil_tmp26 ;
   void *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   void *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
 
   {
   {
 #line 143
   __cil_tmp13 = & __tracepoint_i915_gem_object_fault.key;
 #line 143
   tmp___1 = static_branch(__cil_tmp13);
   }
 #line 143
   if ((int )tmp___1) {
     {
 #line 143
     rcu_read_lock_sched_notrace();
 #line 143
     __cil_tmp14 = & __tracepoint_i915_gem_object_fault.funcs;
 #line 143
     __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
 #line 143
     __cil_tmp16 = *__cil_tmp15;
 #line 143
     _________p1 = (struct tracepoint_func *)__cil_tmp16;
 #line 143
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 143
     if (tmp != 0) {
 #line 143
       if (! __warned) {
         {
 #line 143
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 143
         if (tmp___0 == 0) {
           {
 #line 143
           __warned = (bool )1;
 #line 143
           __cil_tmp17 = (int const   )166;
 #line 143
           __cil_tmp18 = (int )__cil_tmp17;
 #line 143
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp18);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 143
     it_func_ptr = _________p1;
     {
 #line 143
     __cil_tmp19 = (struct tracepoint_func *)0;
 #line 143
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 143
     __cil_tmp21 = (unsigned long )it_func_ptr;
 #line 143
     if (__cil_tmp21 != __cil_tmp20) {
       ldv_35955: 
       {
 #line 143
       it_func = it_func_ptr->func;
 #line 143
       __data = it_func_ptr->data;
 #line 143
       __cil_tmp22 = (void (*)(void * , struct drm_i915_gem_object * , u32  , bool  ,
                               bool  ))it_func;
 #line 143
       __cil_tmp23 = (int )gtt;
 #line 143
       __cil_tmp24 = (bool )__cil_tmp23;
 #line 143
       __cil_tmp25 = (int )write;
 #line 143
       __cil_tmp26 = (bool )__cil_tmp25;
 #line 143
       (*__cil_tmp22)(__data, obj, index, __cil_tmp24, __cil_tmp26);
 #line 143
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 143
       __cil_tmp27 = (void *)0;
 #line 143
       __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 143
       __cil_tmp29 = it_func_ptr->func;
 #line 143
       __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 143
       if (__cil_tmp30 != __cil_tmp28) {
 #line 144
         goto ldv_35955;
       } else {
 #line 146
         goto ldv_35956;
       }
       }
       ldv_35956: ;
     } else {
 
     }
     }
     {
 #line 143
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 145
   return;
 }
 }
 #line 186
 struct tracepoint __tracepoint_i915_gem_object_clflush ;
 #line 186 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_clflush(struct drm_i915_gem_object *obj ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp10 ;
   struct tracepoint_func **__cil_tmp11 ;
   struct tracepoint_func * volatile  *__cil_tmp12 ;
   struct tracepoint_func * volatile  __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   struct tracepoint_func *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   void (*__cil_tmp19)(void * , struct drm_i915_gem_object * ) ;
   void *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
 
   {
   {
 #line 183
   __cil_tmp10 = & __tracepoint_i915_gem_object_clflush.key;
 #line 183
   tmp___1 = static_branch(__cil_tmp10);
   }
 #line 183
   if ((int )tmp___1) {
     {
 #line 183
     rcu_read_lock_sched_notrace();
 #line 183
     __cil_tmp11 = & __tracepoint_i915_gem_object_clflush.funcs;
 #line 183
     __cil_tmp12 = (struct tracepoint_func * volatile  *)__cil_tmp11;
 #line 183
     __cil_tmp13 = *__cil_tmp12;
 #line 183
     _________p1 = (struct tracepoint_func *)__cil_tmp13;
 #line 183
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 183
     if (tmp != 0) {
 #line 183
       if (! __warned) {
         {
 #line 183
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 183
         if (tmp___0 == 0) {
           {
 #line 183
           __warned = (bool )1;
 #line 183
           __cil_tmp14 = (int const   )186;
 #line 183
           __cil_tmp15 = (int )__cil_tmp14;
 #line 183
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp15);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 183
     it_func_ptr = _________p1;
     {
 #line 183
     __cil_tmp16 = (struct tracepoint_func *)0;
 #line 183
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 183
     __cil_tmp18 = (unsigned long )it_func_ptr;
 #line 183
     if (__cil_tmp18 != __cil_tmp17) {
       ldv_35995: 
       {
 #line 183
       it_func = it_func_ptr->func;
 #line 183
       __data = it_func_ptr->data;
 #line 183
       __cil_tmp19 = (void (*)(void * , struct drm_i915_gem_object * ))it_func;
 #line 183
       (*__cil_tmp19)(__data, obj);
 #line 183
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 183
       __cil_tmp20 = (void *)0;
 #line 183
       __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 183
       __cil_tmp22 = it_func_ptr->func;
 #line 183
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 183
       if (__cil_tmp23 != __cil_tmp21) {
 #line 184
         goto ldv_35995;
       } else {
 #line 186
         goto ldv_35996;
       }
       }
       ldv_35996: ;
     } else {
 
     }
     }
     {
 #line 183
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 185
   return;
 }
 }
 #line 191
 struct tracepoint __tracepoint_i915_gem_object_destroy ;
 #line 191 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_object_destroy(struct drm_i915_gem_object *obj ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp10 ;
   struct tracepoint_func **__cil_tmp11 ;
   struct tracepoint_func * volatile  *__cil_tmp12 ;
   struct tracepoint_func * volatile  __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   struct tracepoint_func *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   void (*__cil_tmp19)(void * , struct drm_i915_gem_object * ) ;
   void *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
 
   {
   {
 #line 188
   __cil_tmp10 = & __tracepoint_i915_gem_object_destroy.key;
 #line 188
   tmp___1 = static_branch(__cil_tmp10);
   }
 #line 188
   if ((int )tmp___1) {
     {
 #line 188
     rcu_read_lock_sched_notrace();
 #line 188
     __cil_tmp11 = & __tracepoint_i915_gem_object_destroy.funcs;
 #line 188
     __cil_tmp12 = (struct tracepoint_func * volatile  *)__cil_tmp11;
 #line 188
     __cil_tmp13 = *__cil_tmp12;
 #line 188
     _________p1 = (struct tracepoint_func *)__cil_tmp13;
 #line 188
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 188
     if (tmp != 0) {
 #line 188
       if (! __warned) {
         {
 #line 188
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 188
         if (tmp___0 == 0) {
           {
 #line 188
           __warned = (bool )1;
 #line 188
           __cil_tmp14 = (int const   )191;
 #line 188
           __cil_tmp15 = (int )__cil_tmp14;
 #line 188
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp15);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 188
     it_func_ptr = _________p1;
     {
 #line 188
     __cil_tmp16 = (struct tracepoint_func *)0;
 #line 188
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 188
     __cil_tmp18 = (unsigned long )it_func_ptr;
 #line 188
     if (__cil_tmp18 != __cil_tmp17) {
       ldv_36026: 
       {
 #line 188
       it_func = it_func_ptr->func;
 #line 188
       __data = it_func_ptr->data;
 #line 188
       __cil_tmp19 = (void (*)(void * , struct drm_i915_gem_object * ))it_func;
 #line 188
       (*__cil_tmp19)(__data, obj);
 #line 188
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 188
       __cil_tmp20 = (void *)0;
 #line 188
       __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 188
       __cil_tmp22 = it_func_ptr->func;
 #line 188
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 188
       if (__cil_tmp23 != __cil_tmp21) {
 #line 189
         goto ldv_36026;
       } else {
 #line 191
         goto ldv_36027;
       }
       }
       ldv_36027: ;
     } else {
 
     }
     }
     {
 #line 188
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 190
   return;
 }
 }
 #line 277
 struct tracepoint __tracepoint_i915_gem_ring_flush ;
 #line 277 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_ring_flush(struct intel_ring_buffer *ring , u32 invalidate ,
                                                u32 flush ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp12 ;
   struct tracepoint_func **__cil_tmp13 ;
   struct tracepoint_func * volatile  *__cil_tmp14 ;
   struct tracepoint_func * volatile  __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   struct tracepoint_func *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void (*__cil_tmp21)(void * , struct intel_ring_buffer * , u32  , u32  ) ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   void *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
 
   {
   {
 #line 256
   __cil_tmp12 = & __tracepoint_i915_gem_ring_flush.key;
 #line 256
   tmp___1 = static_branch(__cil_tmp12);
   }
 #line 256
   if ((int )tmp___1) {
     {
 #line 256
     rcu_read_lock_sched_notrace();
 #line 256
     __cil_tmp13 = & __tracepoint_i915_gem_ring_flush.funcs;
 #line 256
     __cil_tmp14 = (struct tracepoint_func * volatile  *)__cil_tmp13;
 #line 256
     __cil_tmp15 = *__cil_tmp14;
 #line 256
     _________p1 = (struct tracepoint_func *)__cil_tmp15;
 #line 256
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 256
     if (tmp != 0) {
 #line 256
       if (! __warned) {
         {
 #line 256
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 256
         if (tmp___0 == 0) {
           {
 #line 256
           __warned = (bool )1;
 #line 256
           __cil_tmp16 = (int const   )277;
 #line 256
           __cil_tmp17 = (int )__cil_tmp16;
 #line 256
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp17);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 256
     it_func_ptr = _________p1;
     {
 #line 256
     __cil_tmp18 = (struct tracepoint_func *)0;
 #line 256
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 256
     __cil_tmp20 = (unsigned long )it_func_ptr;
 #line 256
     if (__cil_tmp20 != __cil_tmp19) {
       ldv_36179: 
       {
 #line 256
       it_func = it_func_ptr->func;
 #line 256
       __data = it_func_ptr->data;
 #line 256
       __cil_tmp21 = (void (*)(void * , struct intel_ring_buffer * , u32  , u32  ))it_func;
 #line 256
       (*__cil_tmp21)(__data, ring, invalidate, flush);
 #line 256
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 256
       __cil_tmp22 = (void *)0;
 #line 256
       __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 256
       __cil_tmp24 = it_func_ptr->func;
 #line 256
       __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 256
       if (__cil_tmp25 != __cil_tmp23) {
 #line 257
         goto ldv_36179;
       } else {
 #line 259
         goto ldv_36180;
       }
       }
       ldv_36180: ;
     } else {
 
     }
     }
     {
 #line 256
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 258
   return;
 }
 }
 #line 302
 struct tracepoint __tracepoint_i915_gem_request_add ;
 #line 302 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_request_add(struct intel_ring_buffer *ring , u32 seqno ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct intel_ring_buffer * , u32  ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 299
   __cil_tmp11 = & __tracepoint_i915_gem_request_add.key;
 #line 299
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 299
   if ((int )tmp___1) {
     {
 #line 299
     rcu_read_lock_sched_notrace();
 #line 299
     __cil_tmp12 = & __tracepoint_i915_gem_request_add.funcs;
 #line 299
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 299
     __cil_tmp14 = *__cil_tmp13;
 #line 299
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 299
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 299
     if (tmp != 0) {
 #line 299
       if (! __warned) {
         {
 #line 299
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 299
         if (tmp___0 == 0) {
           {
 #line 299
           __warned = (bool )1;
 #line 299
           __cil_tmp15 = (int const   )302;
 #line 299
           __cil_tmp16 = (int )__cil_tmp15;
 #line 299
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 299
     it_func_ptr = _________p1;
     {
 #line 299
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 299
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 299
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 299
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36218: 
       {
 #line 299
       it_func = it_func_ptr->func;
 #line 299
       __data = it_func_ptr->data;
 #line 299
       __cil_tmp20 = (void (*)(void * , struct intel_ring_buffer * , u32  ))it_func;
 #line 299
       (*__cil_tmp20)(__data, ring, seqno);
 #line 299
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 299
       __cil_tmp21 = (void *)0;
 #line 299
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 299
       __cil_tmp23 = it_func_ptr->func;
 #line 299
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 299
       if (__cil_tmp24 != __cil_tmp22) {
 #line 300
         goto ldv_36218;
       } else {
 #line 302
         goto ldv_36219;
       }
       }
       ldv_36219: ;
     } else {
 
     }
     }
     {
 #line 299
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 301
   return;
 }
 }
 #line 312
 struct tracepoint __tracepoint_i915_gem_request_retire ;
 #line 312 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_request_retire(struct intel_ring_buffer *ring ,
                                                    u32 seqno ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct intel_ring_buffer * , u32  ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 309
   __cil_tmp11 = & __tracepoint_i915_gem_request_retire.key;
 #line 309
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 309
   if ((int )tmp___1) {
     {
 #line 309
     rcu_read_lock_sched_notrace();
 #line 309
     __cil_tmp12 = & __tracepoint_i915_gem_request_retire.funcs;
 #line 309
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 309
     __cil_tmp14 = *__cil_tmp13;
 #line 309
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 309
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 309
     if (tmp != 0) {
 #line 309
       if (! __warned) {
         {
 #line 309
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 309
         if (tmp___0 == 0) {
           {
 #line 309
           __warned = (bool )1;
 #line 309
           __cil_tmp15 = (int const   )312;
 #line 309
           __cil_tmp16 = (int )__cil_tmp15;
 #line 309
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 309
     it_func_ptr = _________p1;
     {
 #line 309
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 309
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 309
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 309
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36290: 
       {
 #line 309
       it_func = it_func_ptr->func;
 #line 309
       __data = it_func_ptr->data;
 #line 309
       __cil_tmp20 = (void (*)(void * , struct intel_ring_buffer * , u32  ))it_func;
 #line 309
       (*__cil_tmp20)(__data, ring, seqno);
 #line 309
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 309
       __cil_tmp21 = (void *)0;
 #line 309
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 309
       __cil_tmp23 = it_func_ptr->func;
 #line 309
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 309
       if (__cil_tmp24 != __cil_tmp22) {
 #line 310
         goto ldv_36290;
       } else {
 #line 312
         goto ldv_36291;
       }
       }
       ldv_36291: ;
     } else {
 
     }
     }
     {
 #line 309
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 311
   return;
 }
 }
 #line 317
 struct tracepoint __tracepoint_i915_gem_request_wait_begin ;
 #line 317 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_request_wait_begin(struct intel_ring_buffer *ring ,
                                                        u32 seqno ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct intel_ring_buffer * , u32  ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 314
   __cil_tmp11 = & __tracepoint_i915_gem_request_wait_begin.key;
 #line 314
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 314
   if ((int )tmp___1) {
     {
 #line 314
     rcu_read_lock_sched_notrace();
 #line 314
     __cil_tmp12 = & __tracepoint_i915_gem_request_wait_begin.funcs;
 #line 314
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 314
     __cil_tmp14 = *__cil_tmp13;
 #line 314
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 314
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 314
     if (tmp != 0) {
 #line 314
       if (! __warned) {
         {
 #line 314
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 314
         if (tmp___0 == 0) {
           {
 #line 314
           __warned = (bool )1;
 #line 314
           __cil_tmp15 = (int const   )317;
 #line 314
           __cil_tmp16 = (int )__cil_tmp15;
 #line 314
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 314
     it_func_ptr = _________p1;
     {
 #line 314
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 314
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 314
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 314
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36326: 
       {
 #line 314
       it_func = it_func_ptr->func;
 #line 314
       __data = it_func_ptr->data;
 #line 314
       __cil_tmp20 = (void (*)(void * , struct intel_ring_buffer * , u32  ))it_func;
 #line 314
       (*__cil_tmp20)(__data, ring, seqno);
 #line 314
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 314
       __cil_tmp21 = (void *)0;
 #line 314
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 314
       __cil_tmp23 = it_func_ptr->func;
 #line 314
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 314
       if (__cil_tmp24 != __cil_tmp22) {
 #line 315
         goto ldv_36326;
       } else {
 #line 317
         goto ldv_36327;
       }
       }
       ldv_36327: ;
     } else {
 
     }
     }
     {
 #line 314
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 316
   return;
 }
 }
 #line 322
 struct tracepoint __tracepoint_i915_gem_request_wait_end ;
 #line 322 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_request_wait_end(struct intel_ring_buffer *ring ,
                                                      u32 seqno ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct intel_ring_buffer * , u32  ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 319
   __cil_tmp11 = & __tracepoint_i915_gem_request_wait_end.key;
 #line 319
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 319
   if ((int )tmp___1) {
     {
 #line 319
     rcu_read_lock_sched_notrace();
 #line 319
     __cil_tmp12 = & __tracepoint_i915_gem_request_wait_end.funcs;
 #line 319
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 319
     __cil_tmp14 = *__cil_tmp13;
 #line 319
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 319
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 319
     if (tmp != 0) {
 #line 319
       if (! __warned) {
         {
 #line 319
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 319
         if (tmp___0 == 0) {
           {
 #line 319
           __warned = (bool )1;
 #line 319
           __cil_tmp15 = (int const   )322;
 #line 319
           __cil_tmp16 = (int )__cil_tmp15;
 #line 319
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 319
     it_func_ptr = _________p1;
     {
 #line 319
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 319
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 319
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 319
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36362: 
       {
 #line 319
       it_func = it_func_ptr->func;
 #line 319
       __data = it_func_ptr->data;
 #line 319
       __cil_tmp20 = (void (*)(void * , struct intel_ring_buffer * , u32  ))it_func;
 #line 319
       (*__cil_tmp20)(__data, ring, seqno);
 #line 319
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 319
       __cil_tmp21 = (void *)0;
 #line 319
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 319
       __cil_tmp23 = it_func_ptr->func;
 #line 319
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 319
       if (__cil_tmp24 != __cil_tmp22) {
 #line 320
         goto ldv_36362;
       } else {
 #line 322
         goto ldv_36363;
       }
       }
       ldv_36363: ;
     } else {
 
     }
     }
     {
 #line 319
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 321
   return;
 }
 }
 #line 1114 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 int i915_gem_flush_ring(struct intel_ring_buffer *ring , uint32_t invalidate_domains ,
                         uint32_t flush_domains ) ;
 #line 1117
 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev , size_t size ) ;
 #line 1120
 int i915_gem_object_pin(struct drm_i915_gem_object *obj , uint32_t alignment , bool map_and_fenceable ) ;
 #line 1123
 void i915_gem_object_unpin(struct drm_i915_gem_object *obj ) ;
 #line 1124
 int i915_gem_object_unbind(struct drm_i915_gem_object *obj ) ;
 #line 1125
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj ) ;
 #line 1128
 int i915_mutex_lock_interruptible(struct drm_device *dev ) ;
 #line 1129
 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj ) ;
 #line 1130
 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj , struct intel_ring_buffer *ring ,
                                     u32 seqno ) ;
 #line 1151 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring ) 
 { drm_i915_private_t *dev_priv ;
   u32 tmp ;
   struct drm_device *__cil_tmp4 ;
   void *__cil_tmp5 ;
 
   {
 #line 1153
   __cil_tmp4 = ring->dev;
 #line 1153
   __cil_tmp5 = __cil_tmp4->dev_private;
 #line 1153
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 1154
   tmp = dev_priv->next_seqno;
 #line 1154
   ring->outstanding_lazy_request = tmp;
 #line 1154
   return (tmp);
 }
 }
 #line 1157
 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) ;
 #line 1159
 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj ) ;
 #line 1161
 void i915_gem_retire_requests(struct drm_device *dev ) ;
 #line 1163
 void i915_gem_clflush_object(struct drm_i915_gem_object *obj ) ;
 #line 1167
 int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj ) ;
 #line 1176
 int i915_add_request(struct intel_ring_buffer *ring , struct drm_file *file , struct drm_i915_gem_request *request ) ;
 #line 1179
 int i915_wait_request(struct intel_ring_buffer *ring , uint32_t seqno ) ;
 #line 1183
 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj , bool write ) ;
 #line 1186
 int i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) ;
 #line 1188
 int i915_gem_attach_phys_object(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                 int id , int align ) ;
 #line 1192
 void i915_gem_detach_phys_object(struct drm_device *dev , struct drm_i915_gem_object *obj ) ;
 #line 1198
 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev , uint32_t size ,
                                              int tiling_mode ) ;
 #line 1204
 int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj ) ;
 #line 1205
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj ) ;
 #line 1208
 int i915_gem_evict_something(struct drm_device *dev , int min_size , unsigned int alignment ,
                              bool mappable ) ;
 #line 1210
 int i915_gem_evict_everything(struct drm_device *dev , bool purgeable_only ) ;
 #line 1212
 int i915_gem_evict_inactive(struct drm_device *dev , bool purgeable_only ) ;
 #line 1216
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev ) ;
 #line 1217
 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj ) ;
 #line 1218
 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj ) ;
 #line 223 "include/linux/swap.h"
 extern void mark_page_accessed(struct page * ) ;
 #line 58 "include/linux/shmem_fs.h"
 extern struct page *shmem_read_mapping_page_gfp(struct address_space * , unsigned long  ,
                                                 gfp_t  ) ;
 #line 60
 extern void shmem_truncate_range(struct inode * , loff_t  , loff_t  ) ;
 #line 65 "include/linux/shmem_fs.h"
 __inline static struct page *shmem_read_mapping_page(struct address_space *mapping ,
                                                      unsigned long index ) 
 { gfp_t tmp ;
   struct page *tmp___0 ;
 
   {
   {
 #line 68
   tmp = mapping_gfp_mask(mapping);
 #line 68
   tmp___0 = shmem_read_mapping_page_gfp(mapping, index, tmp);
   }
 #line 68
   return (tmp___0);
 }
 }
 #line 46 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj ) ;
 #line 47
 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj ) ;
 #line 48
 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj ) ;
 #line 49
 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj , bool write ) ;
 #line 51
 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj ,
                                                      uint64_t offset , uint64_t size ) ;
 #line 54
 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj ) ;
 #line 55
 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj , unsigned int alignment ,
                                        bool map_and_fenceable ) ;
 #line 58
 static void i915_gem_clear_fence_reg(struct drm_device *dev , struct drm_i915_fence_reg *reg ) ;
 #line 60
 static int i915_gem_phys_pwrite(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                 struct drm_i915_gem_pwrite *args , struct drm_file *file_priv ) ;
 #line 64
 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj ) ;
 #line 66
 static int i915_gem_inactive_shrink(struct shrinker *shrinker , struct shrink_control *sc ) ;
 #line 70 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv , size_t size ) 
 { u32 __cil_tmp3 ;
   size_t __cil_tmp4 ;
 
   {
 #line 73
   __cil_tmp3 = dev_priv->mm.object_count;
 #line 73
   dev_priv->mm.object_count = __cil_tmp3 + 1U;
 #line 74
   __cil_tmp4 = dev_priv->mm.object_memory;
 #line 74
   dev_priv->mm.object_memory = __cil_tmp4 + size;
 #line 75
   return;
 }
 }
 #line 77 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv , size_t size ) 
 { u32 __cil_tmp3 ;
   size_t __cil_tmp4 ;
 
   {
 #line 80
   __cil_tmp3 = dev_priv->mm.object_count;
 #line 80
   dev_priv->mm.object_count = __cil_tmp3 - 1U;
 #line 81
   __cil_tmp4 = dev_priv->mm.object_memory;
 #line 81
   dev_priv->mm.object_memory = __cil_tmp4 - size;
 #line 82
   return;
 }
 }
 #line 85 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_wait_for_error(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct completion *x ;
   unsigned long flags ;
   int ret ;
   int tmp ;
   raw_spinlock_t *tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp9 ;
   atomic_t *__cil_tmp10 ;
   atomic_t const   *__cil_tmp11 ;
   atomic_t *__cil_tmp12 ;
   atomic_t const   *__cil_tmp13 ;
   spinlock_t *__cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   spinlock_t *__cil_tmp16 ;
 
   {
   {
 #line 87
   __cil_tmp9 = dev->dev_private;
 #line 87
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 88
   x = & dev_priv->error_completion;
 #line 92
   __cil_tmp10 = & dev_priv->mm.wedged;
 #line 92
   __cil_tmp11 = (atomic_t const   *)__cil_tmp10;
 #line 92
   tmp = atomic_read(__cil_tmp11);
   }
 #line 92
   if (tmp == 0) {
 #line 93
     return (0);
   } else {
 
   }
   {
 #line 95
   ret = wait_for_completion_interruptible(x);
   }
 #line 96
   if (ret != 0) {
 #line 97
     return (ret);
   } else {
 
   }
   {
 #line 99
   __cil_tmp12 = & dev_priv->mm.wedged;
 #line 99
   __cil_tmp13 = (atomic_t const   *)__cil_tmp12;
 #line 99
   tmp___1 = atomic_read(__cil_tmp13);
   }
 #line 99
   if (tmp___1 != 0) {
     {
 #line 105
     __cil_tmp14 = & x->wait.lock;
 #line 105
     tmp___0 = spinlock_check(__cil_tmp14);
 #line 105
     flags = _raw_spin_lock_irqsave(tmp___0);
 #line 106
     __cil_tmp15 = x->done;
 #line 106
     x->done = __cil_tmp15 + 1U;
 #line 107
     __cil_tmp16 = & x->wait.lock;
 #line 107
     spin_unlock_irqrestore(__cil_tmp16, flags);
     }
   } else {
 
   }
 #line 109
   return (0);
 }
 }
 #line 112 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_mutex_lock_interruptible(struct drm_device *dev ) 
 { int ret ;
   int __ret_warn_on ;
   long tmp ;
   struct mutex *__cil_tmp5 ;
   int __cil_tmp6 ;
   long __cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   long __cil_tmp11 ;
 
   {
   {
 #line 116
   ret = i915_gem_wait_for_error(dev);
   }
 #line 117
   if (ret != 0) {
 #line 118
     return (ret);
   } else {
 
   }
   {
 #line 120
   __cil_tmp5 = & dev->struct_mutex;
 #line 120
   ret = mutex_lock_interruptible_nested(__cil_tmp5, 0U);
   }
 #line 121
   if (ret != 0) {
 #line 122
     return (ret);
   } else {
 
   }
   {
 #line 124
   __ret_warn_on = 0;
 #line 124
   __cil_tmp6 = __ret_warn_on != 0;
 #line 124
   __cil_tmp7 = (long )__cil_tmp6;
 #line 124
   tmp = __builtin_expect(__cil_tmp7, 0L);
   }
 #line 124
   if (tmp != 0L) {
     {
 #line 124
     __cil_tmp8 = (int const   )124;
 #line 124
     __cil_tmp9 = (int )__cil_tmp8;
 #line 124
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp9);
     }
   } else {
 
   }
   {
 #line 124
   __cil_tmp10 = __ret_warn_on != 0;
 #line 124
   __cil_tmp11 = (long )__cil_tmp10;
 #line 124
   __builtin_expect(__cil_tmp11, 0L);
   }
 #line 125
   return (0);
 }
 }
 #line 129 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj ) 
 { int tmp ;
   struct drm_mm_node *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   struct drm_mm_node *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int *__cil_tmp11 ;
   unsigned int *__cil_tmp12 ;
   unsigned int __cil_tmp13 ;
 
   {
   {
 #line 131
   __cil_tmp3 = (struct drm_mm_node *)0;
 #line 131
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 131
   __cil_tmp5 = obj->gtt_space;
 #line 131
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 131
   if (__cil_tmp6 != __cil_tmp4) {
     {
 #line 131
     __cil_tmp7 = (unsigned char *)obj;
 #line 131
     __cil_tmp8 = __cil_tmp7 + 224UL;
 #line 131
     __cil_tmp9 = *__cil_tmp8;
 #line 131
     __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 131
     if (__cil_tmp10 == 0U) {
       {
 #line 131
       __cil_tmp11 = (unsigned int *)obj;
 #line 131
       __cil_tmp12 = __cil_tmp11 + 56UL;
 #line 131
       __cil_tmp13 = *__cil_tmp12;
 #line 131
       if (__cil_tmp13 == 0U) {
 #line 131
         tmp = 1;
       } else {
 #line 131
         tmp = 0;
       }
       }
     } else {
 #line 131
       tmp = 0;
     }
     }
   } else {
 #line 131
     tmp = 0;
   }
   }
 #line 131
   return ((bool )tmp);
 }
 }
 #line 134 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_do_init(struct drm_device *dev , unsigned long start , unsigned long mappable_end ,
                       unsigned long end ) 
 { drm_i915_private_t *dev_priv ;
   unsigned long _min1 ;
   unsigned long _min2 ;
   unsigned long tmp ;
   void *__cil_tmp9 ;
   struct drm_mm *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
 
   {
   {
 #line 139
   __cil_tmp9 = dev->dev_private;
 #line 139
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 141
   __cil_tmp10 = & dev_priv->mm.gtt_space;
 #line 141
   __cil_tmp11 = end - start;
 #line 141
   drm_mm_init(__cil_tmp10, start, __cil_tmp11);
 #line 143
   dev_priv->mm.gtt_start = start;
 #line 144
   dev_priv->mm.gtt_mappable_end = mappable_end;
 #line 145
   dev_priv->mm.gtt_end = end;
 #line 146
   dev_priv->mm.gtt_total = end - start;
 #line 147
   _min1 = end;
 #line 147
   _min2 = mappable_end;
   }
 #line 147
   if (_min1 < _min2) {
 #line 147
     tmp = _min1;
   } else {
 #line 147
     tmp = _min2;
   }
   {
 #line 147
   dev_priv->mm.mappable_gtt_total = tmp - start;
 #line 150
   __cil_tmp12 = start / 4096UL;
 #line 150
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 150
   __cil_tmp14 = end - start;
 #line 150
   __cil_tmp15 = __cil_tmp14 / 4096UL;
 #line 150
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 150
   intel_gtt_clear_range(__cil_tmp13, __cil_tmp16);
   }
 #line 151
   return;
 }
 }
 #line 154 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_init_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_init *args ;
   __u64 __cil_tmp5 ;
   __u64 __cil_tmp6 ;
   __u64 __cil_tmp7 ;
   __u64 __cil_tmp8 ;
   unsigned long long __cil_tmp9 ;
   unsigned long long __cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   __u64 __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   __u64 __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   __u64 __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct mutex *__cil_tmp18 ;
 
   {
 #line 157
   args = (struct drm_i915_gem_init *)data;
   {
 #line 159
   __cil_tmp5 = args->gtt_end;
 #line 159
   __cil_tmp6 = args->gtt_start;
 #line 159
   if (__cil_tmp6 >= __cil_tmp5) {
 #line 161
     return (-22);
   } else {
     {
 #line 159
     __cil_tmp7 = args->gtt_start;
 #line 159
     __cil_tmp8 = args->gtt_end;
 #line 159
     __cil_tmp9 = __cil_tmp8 | __cil_tmp7;
 #line 159
     __cil_tmp10 = __cil_tmp9 & 4095ULL;
 #line 159
     if (__cil_tmp10 != 0ULL) {
 #line 161
       return (-22);
     } else {
 
     }
     }
   }
   }
   {
 #line 163
   __cil_tmp11 = & dev->struct_mutex;
 #line 163
   mutex_lock_nested(__cil_tmp11, 0U);
 #line 164
   __cil_tmp12 = args->gtt_start;
 #line 164
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 164
   __cil_tmp14 = args->gtt_end;
 #line 164
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 164
   __cil_tmp16 = args->gtt_end;
 #line 164
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 164
   i915_gem_do_init(dev, __cil_tmp13, __cil_tmp15, __cil_tmp17);
 #line 165
   __cil_tmp18 = & dev->struct_mutex;
 #line 165
   mutex_unlock(__cil_tmp18);
   }
 #line 167
   return (0);
 }
 }
 #line 171 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_get_aperture_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_get_aperture *args ;
   struct drm_i915_gem_object *obj ;
   size_t pinned ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp10 ;
   struct drm_driver *__cil_tmp11 ;
   u32 __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   struct mutex *__cil_tmp14 ;
   struct list_head *__cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   struct drm_mm_node *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct list_head *__cil_tmp19 ;
   struct drm_i915_gem_object *__cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   struct list_head *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct mutex *__cil_tmp25 ;
   size_t __cil_tmp26 ;
   unsigned long long __cil_tmp27 ;
   __u64 __cil_tmp28 ;
 
   {
 #line 174
   __cil_tmp10 = dev->dev_private;
 #line 174
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 175
   args = (struct drm_i915_gem_get_aperture *)data;
   {
 #line 179
   __cil_tmp11 = dev->driver;
 #line 179
   __cil_tmp12 = __cil_tmp11->driver_features;
 #line 179
   __cil_tmp13 = __cil_tmp12 & 4096U;
 #line 179
   if (__cil_tmp13 == 0U) {
 #line 180
     return (-19);
   } else {
 
   }
   }
   {
 #line 182
   pinned = 0UL;
 #line 183
   __cil_tmp14 = & dev->struct_mutex;
 #line 183
   mutex_lock_nested(__cil_tmp14, 0U);
 #line 184
   __cil_tmp15 = dev_priv->mm.pinned_list.next;
 #line 184
   __mptr = (struct list_head  const  *)__cil_tmp15;
 #line 184
   __cil_tmp16 = (struct drm_i915_gem_object *)__mptr;
 #line 184
   obj = __cil_tmp16 + 1152921504606846800UL;
   }
 #line 184
   goto ldv_38798;
   ldv_38797: 
 #line 185
   __cil_tmp17 = obj->gtt_space;
 #line 185
   __cil_tmp18 = __cil_tmp17->size;
 #line 185
   pinned = __cil_tmp18 + pinned;
 #line 184
   __cil_tmp19 = obj->mm_list.next;
 #line 184
   __mptr___0 = (struct list_head  const  *)__cil_tmp19;
 #line 184
   __cil_tmp20 = (struct drm_i915_gem_object *)__mptr___0;
 #line 184
   obj = __cil_tmp20 + 1152921504606846800UL;
   ldv_38798: ;
   {
 #line 184
   __cil_tmp21 = & dev_priv->mm.pinned_list;
 #line 184
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 184
   __cil_tmp23 = & obj->mm_list;
 #line 184
   __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 184
   if (__cil_tmp24 != __cil_tmp22) {
 #line 185
     goto ldv_38797;
   } else {
 #line 187
     goto ldv_38799;
   }
   }
   ldv_38799: 
   {
 #line 186
   __cil_tmp25 = & dev->struct_mutex;
 #line 186
   mutex_unlock(__cil_tmp25);
 #line 188
   __cil_tmp26 = dev_priv->mm.gtt_total;
 #line 188
   args->aper_size = (__u64 )__cil_tmp26;
 #line 189
   __cil_tmp27 = (unsigned long long )pinned;
 #line 189
   __cil_tmp28 = args->aper_size;
 #line 189
   args->aper_available_size = __cil_tmp28 - __cil_tmp27;
   }
 #line 191
   return (0);
 }
 }
 #line 195 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_create(struct drm_file *file , struct drm_device *dev , uint64_t size ,
                            uint32_t *handle_p ) 
 { struct drm_i915_gem_object *obj ;
   int ret ;
   u32 handle ;
   unsigned long __y ;
   unsigned long long __cil_tmp9 ;
   unsigned long long __cil_tmp10 ;
   unsigned long long __cil_tmp11 ;
   unsigned long long __cil_tmp12 ;
   unsigned long long __cil_tmp13 ;
   unsigned long long __cil_tmp14 ;
   size_t __cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct drm_gem_object *__cil_tmp19 ;
   struct drm_gem_object *__cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   size_t __cil_tmp23 ;
   void const   *__cil_tmp24 ;
   struct drm_gem_object *__cil_tmp25 ;
 
   {
   {
 #line 204
   __y = 4096UL;
 #line 204
   __cil_tmp9 = (unsigned long long )__y;
 #line 204
   __cil_tmp10 = (unsigned long long )__y;
 #line 204
   __cil_tmp11 = (unsigned long long )__y;
 #line 204
   __cil_tmp12 = __cil_tmp11 + size;
 #line 204
   __cil_tmp13 = __cil_tmp12 - 1ULL;
 #line 204
   __cil_tmp14 = __cil_tmp13 / __cil_tmp10;
 #line 204
   size = __cil_tmp14 * __cil_tmp9;
 #line 207
   __cil_tmp15 = (size_t )size;
 #line 207
   obj = i915_gem_alloc_object(dev, __cil_tmp15);
   }
   {
 #line 208
   __cil_tmp16 = (struct drm_i915_gem_object *)0;
 #line 208
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 208
   __cil_tmp18 = (unsigned long )obj;
 #line 208
   if (__cil_tmp18 == __cil_tmp17) {
 #line 209
     return (-12);
   } else {
 
   }
   }
   {
 #line 211
   __cil_tmp19 = & obj->base;
 #line 211
   ret = drm_gem_handle_create(file, __cil_tmp19, & handle);
   }
 #line 212
   if (ret != 0) {
     {
 #line 213
     __cil_tmp20 = & obj->base;
 #line 213
     drm_gem_object_release(__cil_tmp20);
 #line 214
     __cil_tmp21 = dev->dev_private;
 #line 214
     __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 214
     __cil_tmp23 = obj->base.size;
 #line 214
     i915_gem_info_remove_obj(__cil_tmp22, __cil_tmp23);
 #line 215
     __cil_tmp24 = (void const   *)obj;
 #line 215
     kfree(__cil_tmp24);
     }
 #line 216
     return (ret);
   } else {
 
   }
   {
 #line 220
   __cil_tmp25 = & obj->base;
 #line 220
   drm_gem_object_unreference(__cil_tmp25);
 #line 221
   trace_i915_gem_object_create(obj);
 #line 223
   *handle_p = handle;
   }
 #line 224
   return (0);
 }
 }
 #line 228 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_dumb_create(struct drm_file *file , struct drm_device *dev , struct drm_mode_create_dumb *args ) 
 { int tmp ;
   uint32_t __cil_tmp5 ;
   uint32_t __cil_tmp6 ;
   uint32_t __cil_tmp7 ;
   uint32_t __cil_tmp8 ;
   uint32_t __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   uint32_t __cil_tmp12 ;
   uint32_t __cil_tmp13 ;
   uint64_t __cil_tmp14 ;
   uint32_t *__cil_tmp15 ;
 
   {
   {
 #line 233
   __cil_tmp5 = args->bpp;
 #line 233
   __cil_tmp6 = __cil_tmp5 + 7U;
 #line 233
   __cil_tmp7 = __cil_tmp6 / 8U;
 #line 233
   __cil_tmp8 = args->width;
 #line 233
   __cil_tmp9 = __cil_tmp8 * __cil_tmp7;
 #line 233
   __cil_tmp10 = __cil_tmp9 + 63U;
 #line 233
   args->pitch = __cil_tmp10 & 4294967232U;
 #line 234
   __cil_tmp11 = args->height;
 #line 234
   __cil_tmp12 = args->pitch;
 #line 234
   __cil_tmp13 = __cil_tmp12 * __cil_tmp11;
 #line 234
   args->size = (uint64_t )__cil_tmp13;
 #line 235
   __cil_tmp14 = args->size;
 #line 235
   __cil_tmp15 = & args->handle;
 #line 235
   tmp = i915_gem_create(file, dev, __cil_tmp14, __cil_tmp15);
   }
 #line 235
   return (tmp);
 }
 }
 #line 239 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_dumb_destroy(struct drm_file *file , struct drm_device *dev , uint32_t handle ) 
 { int tmp ;
 
   {
   {
 #line 243
   tmp = drm_gem_handle_delete(file, handle);
   }
 #line 243
   return (tmp);
 }
 }
 #line 250 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_create_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_create *args ;
   int tmp ;
   __u64 __cil_tmp6 ;
   __u32 *__cil_tmp7 ;
 
   {
   {
 #line 253
   args = (struct drm_i915_gem_create *)data;
 #line 254
   __cil_tmp6 = args->size;
 #line 254
   __cil_tmp7 = & args->handle;
 #line 254
   tmp = i915_gem_create(file, dev, __cil_tmp6, __cil_tmp7);
   }
 #line 254
   return (tmp);
 }
 }
 #line 258 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj ) 
 { drm_i915_private_t *dev_priv ;
   int tmp ;
   struct drm_device *__cil_tmp4 ;
   void *__cil_tmp5 ;
   uint32_t __cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
 
   {
 #line 260
   __cil_tmp4 = obj->base.dev;
 #line 260
   __cil_tmp5 = __cil_tmp4->dev_private;
 #line 260
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
   {
 #line 262
   __cil_tmp6 = dev_priv->mm.bit_6_swizzle_x;
 #line 262
   if (__cil_tmp6 == 7U) {
     {
 #line 262
     __cil_tmp7 = (unsigned char *)obj;
 #line 262
     __cil_tmp8 = __cil_tmp7 + 225UL;
 #line 262
     __cil_tmp9 = *__cil_tmp8;
 #line 262
     __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 262
     if (__cil_tmp10 != 0U) {
 #line 262
       tmp = 1;
     } else {
 #line 262
       tmp = 0;
     }
     }
   } else {
 #line 262
     tmp = 0;
   }
   }
 #line 262
   return (tmp);
 }
 }
 #line 267 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static void slow_shmem_copy(struct page *dst_page , int dst_offset , struct page *src_page ,
                                      int src_offset , int length ) 
 { char *dst_vaddr ;
   char *src_vaddr ;
   void *tmp ;
   void *tmp___0 ;
   size_t __len ;
   void *__ret ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   void const   *__cil_tmp16 ;
   void const   *__cil_tmp17 ;
 
   {
   {
 #line 275
   tmp = kmap(dst_page);
 #line 275
   dst_vaddr = (char *)tmp;
 #line 276
   tmp___0 = kmap(src_page);
 #line 276
   src_vaddr = (char *)tmp___0;
 #line 278
   __len = (size_t )length;
 #line 278
   __cil_tmp12 = (unsigned long )dst_offset;
 #line 278
   __cil_tmp13 = (void *)dst_vaddr;
 #line 278
   __cil_tmp14 = __cil_tmp13 + __cil_tmp12;
 #line 278
   __cil_tmp15 = (unsigned long )src_offset;
 #line 278
   __cil_tmp16 = (void const   *)src_vaddr;
 #line 278
   __cil_tmp17 = __cil_tmp16 + __cil_tmp15;
 #line 278
   __ret = __builtin_memcpy(__cil_tmp14, __cil_tmp17, __len);
 #line 280
   kunmap(src_page);
 #line 281
   kunmap(dst_page);
   }
 #line 282
   return;
 }
 }
 #line 285 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static void slow_shmem_bit17_copy(struct page *gpu_page , int gpu_offset ,
                                            struct page *cpu_page , int cpu_offset ,
                                            int length , int is_read ) 
 { char *gpu_vaddr ;
   char *cpu_vaddr ;
   void *tmp ;
   void *tmp___0 ;
   int cacheline_end ;
   int this_length ;
   int _min1 ;
   int _min2 ;
   int tmp___1 ;
   int swizzled_gpu_offset ;
   size_t __len ;
   void *__ret ;
   size_t __len___0 ;
   void *__ret___0 ;
   long __cil_tmp21 ;
   long __cil_tmp22 ;
   long __cil_tmp23 ;
   unsigned long long __cil_tmp24 ;
   unsigned long long __cil_tmp25 ;
   unsigned long long __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   void *__cil_tmp29 ;
   void *__cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   void const   *__cil_tmp32 ;
   void const   *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   void *__cil_tmp35 ;
   void *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   void const   *__cil_tmp38 ;
   void const   *__cil_tmp39 ;
 
   {
   {
 #line 295
   __cil_tmp21 = (long )gpu_page;
 #line 295
   __cil_tmp22 = __cil_tmp21 + 24189255811072L;
 #line 295
   __cil_tmp23 = __cil_tmp22 / 56L;
 #line 295
   __cil_tmp24 = (unsigned long long )__cil_tmp23;
 #line 295
   __cil_tmp25 = __cil_tmp24 << 12;
 #line 295
   __cil_tmp26 = __cil_tmp25 & 131072ULL;
 #line 295
   if (__cil_tmp26 == 0ULL) {
 #line 296
     if (is_read != 0) {
 #line 297
       return;
     } else {
 #line 300
       return;
     }
   } else {
 
   }
   }
   {
 #line 304
   tmp = kmap(gpu_page);
 #line 304
   gpu_vaddr = (char *)tmp;
 #line 305
   tmp___0 = kmap(cpu_page);
 #line 305
   cpu_vaddr = (char *)tmp___0;
   }
 #line 310
   goto ldv_38866;
   ldv_38865: 
 #line 311
   __cil_tmp27 = gpu_offset + 64;
 #line 311
   cacheline_end = __cil_tmp27 & -64;
 #line 312
   _min1 = cacheline_end - gpu_offset;
 #line 312
   _min2 = length;
 #line 312
   if (_min1 < _min2) {
 #line 312
     tmp___1 = _min1;
   } else {
 #line 312
     tmp___1 = _min2;
   }
 #line 312
   this_length = tmp___1;
 #line 313
   swizzled_gpu_offset = gpu_offset ^ 64;
 #line 315
   if (is_read != 0) {
     {
 #line 316
     __len = (size_t )this_length;
 #line 316
     __cil_tmp28 = (unsigned long )cpu_offset;
 #line 316
     __cil_tmp29 = (void *)cpu_vaddr;
 #line 316
     __cil_tmp30 = __cil_tmp29 + __cil_tmp28;
 #line 316
     __cil_tmp31 = (unsigned long )swizzled_gpu_offset;
 #line 316
     __cil_tmp32 = (void const   *)gpu_vaddr;
 #line 316
     __cil_tmp33 = __cil_tmp32 + __cil_tmp31;
 #line 316
     __ret = __builtin_memcpy(__cil_tmp30, __cil_tmp33, __len);
     }
   } else {
     {
 #line 320
     __len___0 = (size_t )this_length;
 #line 320
     __cil_tmp34 = (unsigned long )swizzled_gpu_offset;
 #line 320
     __cil_tmp35 = (void *)gpu_vaddr;
 #line 320
     __cil_tmp36 = __cil_tmp35 + __cil_tmp34;
 #line 320
     __cil_tmp37 = (unsigned long )cpu_offset;
 #line 320
     __cil_tmp38 = (void const   *)cpu_vaddr;
 #line 320
     __cil_tmp39 = __cil_tmp38 + __cil_tmp37;
 #line 320
     __ret___0 = __builtin_memcpy(__cil_tmp36, __cil_tmp39, __len___0);
     }
   }
 #line 324
   cpu_offset = cpu_offset + this_length;
 #line 325
   gpu_offset = gpu_offset + this_length;
 #line 326
   length = length - this_length;
   ldv_38866: ;
 #line 310
   if (length > 0) {
 #line 311
     goto ldv_38865;
   } else {
 #line 313
     goto ldv_38867;
   }
   ldv_38867: 
   {
 #line 329
   kunmap(cpu_page);
 #line 330
   kunmap(gpu_page);
   }
 #line 331
   return;
 }
 }
 #line 339 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_shmem_pread_fast(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                      struct drm_i915_gem_pread *args , struct drm_file *file ) 
 { struct address_space *mapping ;
   ssize_t remain ;
   loff_t offset ;
   char *user_data ;
   int page_offset___0 ;
   int page_length ;
   struct page *page ;
   char *vaddr ;
   int ret ;
   long tmp ;
   long tmp___0 ;
   void *tmp___1 ;
   struct file *__cil_tmp17 ;
   struct dentry *__cil_tmp18 ;
   struct inode *__cil_tmp19 ;
   __u64 __cil_tmp20 ;
   __u64 __cil_tmp21 ;
   __u64 __cil_tmp22 ;
   int __cil_tmp23 ;
   ssize_t __cil_tmp24 ;
   ssize_t __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   loff_t __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   void const   *__cil_tmp31 ;
   void const   *__cil_tmp32 ;
   void *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   void const   *__cil_tmp35 ;
   void const   *__cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   void *__cil_tmp38 ;
   ssize_t __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   loff_t __cil_tmp41 ;
 
   {
 #line 344
   __cil_tmp17 = obj->base.filp;
 #line 344
   __cil_tmp18 = __cil_tmp17->f_path.dentry;
 #line 344
   __cil_tmp19 = __cil_tmp18->d_inode;
 #line 344
   mapping = __cil_tmp19->i_mapping;
 #line 350
   __cil_tmp20 = args->data_ptr;
 #line 350
   user_data = (char *)__cil_tmp20;
 #line 351
   __cil_tmp21 = args->size;
 #line 351
   remain = (ssize_t )__cil_tmp21;
 #line 353
   __cil_tmp22 = args->offset;
 #line 353
   offset = (loff_t )__cil_tmp22;
 #line 355
   goto ldv_38884;
   ldv_38883: 
 #line 365
   __cil_tmp23 = (int )offset;
 #line 365
   page_offset___0 = __cil_tmp23 & 4095;
 #line 366
   page_length = (int )remain;
   {
 #line 367
   __cil_tmp24 = (ssize_t )page_offset___0;
 #line 367
   __cil_tmp25 = __cil_tmp24 + remain;
 #line 367
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 367
   if (__cil_tmp26 > 4096UL) {
 #line 368
     __cil_tmp27 = (unsigned int )page_offset___0;
 #line 368
     __cil_tmp28 = 4096U - __cil_tmp27;
 #line 368
     page_length = (int )__cil_tmp28;
   } else {
 
   }
   }
   {
 #line 370
   __cil_tmp29 = offset >> 12;
 #line 370
   __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 370
   page = shmem_read_mapping_page(mapping, __cil_tmp30);
 #line 371
   __cil_tmp31 = (void const   *)page;
 #line 371
   tmp___0 = IS_ERR(__cil_tmp31);
   }
 #line 371
   if (tmp___0 != 0L) {
     {
 #line 372
     __cil_tmp32 = (void const   *)page;
 #line 372
     tmp = PTR_ERR(__cil_tmp32);
     }
 #line 372
     return ((int )tmp);
   } else {
 
   }
   {
 #line 374
   tmp___1 = __kmap_atomic(page);
 #line 374
   vaddr = (char *)tmp___1;
 #line 375
   __cil_tmp33 = (void *)user_data;
 #line 375
   __cil_tmp34 = (unsigned long )page_offset___0;
 #line 375
   __cil_tmp35 = (void const   *)vaddr;
 #line 375
   __cil_tmp36 = __cil_tmp35 + __cil_tmp34;
 #line 375
   __cil_tmp37 = (unsigned int )page_length;
 #line 375
   ret = __copy_from_user_inatomic(__cil_tmp33, __cil_tmp36, __cil_tmp37);
 #line 378
   __cil_tmp38 = (void *)vaddr;
 #line 378
   __kunmap_atomic(__cil_tmp38);
 #line 380
   mark_page_accessed(page);
 #line 381
   put_page(page);
   }
 #line 382
   if (ret != 0) {
 #line 383
     return (-14);
   } else {
 
   }
 #line 385
   __cil_tmp39 = (ssize_t )page_length;
 #line 385
   remain = remain - __cil_tmp39;
 #line 386
   __cil_tmp40 = (unsigned long )page_length;
 #line 386
   user_data = user_data + __cil_tmp40;
 #line 387
   __cil_tmp41 = (loff_t )page_length;
 #line 387
   offset = __cil_tmp41 + offset;
   ldv_38884: ;
 #line 355
   if (remain > 0L) {
 #line 356
     goto ldv_38883;
   } else {
 #line 358
     goto ldv_38885;
   }
   ldv_38885: ;
 #line 390
   return (0);
 }
 }
 #line 400 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_shmem_pread_slow(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                      struct drm_i915_gem_pread *args , struct drm_file *file ) 
 { struct address_space *mapping ;
   struct mm_struct *mm ;
   struct task_struct *tmp ;
   struct page **user_pages ;
   ssize_t remain ;
   loff_t offset ;
   loff_t pinned_pages ;
   loff_t i ;
   loff_t first_data_page ;
   loff_t last_data_page ;
   loff_t num_pages ;
   int shmem_page_offset ;
   int data_page_index ;
   int data_page_offset ;
   int page_length ;
   int ret ;
   uint64_t data_ptr ;
   int do_bit17_swizzling ;
   void *tmp___0 ;
   struct task_struct *tmp___1 ;
   int tmp___2 ;
   struct page *page ;
   long tmp___3 ;
   long tmp___4 ;
   struct file *__cil_tmp29 ;
   struct dentry *__cil_tmp30 ;
   struct inode *__cil_tmp31 ;
   __u64 __cil_tmp32 ;
   uint64_t __cil_tmp33 ;
   __u64 __cil_tmp34 ;
   __u64 __cil_tmp35 ;
   __u64 __cil_tmp36 ;
   __u64 __cil_tmp37 ;
   loff_t __cil_tmp38 ;
   size_t __cil_tmp39 ;
   struct page **__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct mutex *__cil_tmp43 ;
   struct rw_semaphore *__cil_tmp44 ;
   __u64 __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   int __cil_tmp47 ;
   struct vm_area_struct **__cil_tmp48 ;
   struct rw_semaphore *__cil_tmp49 ;
   struct mutex *__cil_tmp50 ;
   __u64 __cil_tmp51 ;
   __u64 __cil_tmp52 ;
   __u64 __cil_tmp53 ;
   int __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   uint64_t __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   int __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   loff_t __cil_tmp68 ;
   unsigned long __cil_tmp69 ;
   void const   *__cil_tmp70 ;
   void const   *__cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   struct page **__cil_tmp73 ;
   struct page *__cil_tmp74 ;
   unsigned long __cil_tmp75 ;
   struct page **__cil_tmp76 ;
   struct page *__cil_tmp77 ;
   ssize_t __cil_tmp78 ;
   uint64_t __cil_tmp79 ;
   loff_t __cil_tmp80 ;
   unsigned long __cil_tmp81 ;
   struct page **__cil_tmp82 ;
   struct page *__cil_tmp83 ;
   unsigned long __cil_tmp84 ;
   struct page **__cil_tmp85 ;
   struct page *__cil_tmp86 ;
   unsigned long __cil_tmp87 ;
   struct page **__cil_tmp88 ;
   struct page *__cil_tmp89 ;
   void *__cil_tmp90 ;
 
   {
   {
 #line 405
   __cil_tmp29 = obj->base.filp;
 #line 405
   __cil_tmp30 = __cil_tmp29->f_path.dentry;
 #line 405
   __cil_tmp31 = __cil_tmp30->d_inode;
 #line 405
   mapping = __cil_tmp31->i_mapping;
 #line 406
   tmp = get_current();
 #line 406
   mm = tmp->mm;
 #line 415
   data_ptr = args->data_ptr;
 #line 418
   __cil_tmp32 = args->size;
 #line 418
   remain = (ssize_t )__cil_tmp32;
 #line 424
   __cil_tmp33 = data_ptr / 4096ULL;
 #line 424
   first_data_page = (loff_t )__cil_tmp33;
 #line 425
   __cil_tmp34 = args->size;
 #line 425
   __cil_tmp35 = __cil_tmp34 + data_ptr;
 #line 425
   __cil_tmp36 = __cil_tmp35 - 1ULL;
 #line 425
   __cil_tmp37 = __cil_tmp36 / 4096ULL;
 #line 425
   last_data_page = (loff_t )__cil_tmp37;
 #line 426
   __cil_tmp38 = last_data_page - first_data_page;
 #line 426
   num_pages = __cil_tmp38 + 1LL;
 #line 428
   __cil_tmp39 = (size_t )num_pages;
 #line 428
   tmp___0 = drm_malloc_ab(__cil_tmp39, 8UL);
 #line 428
   user_pages = (struct page **)tmp___0;
   }
   {
 #line 429
   __cil_tmp40 = (struct page **)0;
 #line 429
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 429
   __cil_tmp42 = (unsigned long )user_pages;
 #line 429
   if (__cil_tmp42 == __cil_tmp41) {
 #line 430
     return (-12);
   } else {
 
   }
   }
   {
 #line 432
   __cil_tmp43 = & dev->struct_mutex;
 #line 432
   mutex_unlock(__cil_tmp43);
 #line 433
   __cil_tmp44 = & mm->mmap_sem;
 #line 433
   down_read(__cil_tmp44);
 #line 434
   tmp___1 = get_current();
 #line 434
   __cil_tmp45 = args->data_ptr;
 #line 434
   __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 434
   __cil_tmp47 = (int )num_pages;
 #line 434
   __cil_tmp48 = (struct vm_area_struct **)0;
 #line 434
   tmp___2 = get_user_pages(tmp___1, mm, __cil_tmp46, __cil_tmp47, 1, 0, user_pages,
                            __cil_tmp48);
 #line 434
   pinned_pages = (loff_t )tmp___2;
 #line 436
   __cil_tmp49 = & mm->mmap_sem;
 #line 436
   up_read(__cil_tmp49);
 #line 437
   __cil_tmp50 = & dev->struct_mutex;
 #line 437
   mutex_lock_nested(__cil_tmp50, 0U);
   }
 #line 438
   if (pinned_pages < num_pages) {
 #line 439
     ret = -14;
 #line 440
     goto out;
   } else {
 
   }
   {
 #line 443
   __cil_tmp51 = args->offset;
 #line 443
   __cil_tmp52 = args->size;
 #line 443
   ret = i915_gem_object_set_cpu_read_domain_range(obj, __cil_tmp51, __cil_tmp52);
   }
 #line 446
   if (ret != 0) {
 #line 447
     goto out;
   } else {
 
   }
   {
 #line 449
   do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 #line 451
   __cil_tmp53 = args->offset;
 #line 451
   offset = (loff_t )__cil_tmp53;
   }
 #line 453
   goto ldv_38912;
   ldv_38911: 
 #line 463
   __cil_tmp54 = (int )offset;
 #line 463
   shmem_page_offset = __cil_tmp54 & 4095;
 #line 464
   __cil_tmp55 = (unsigned int )first_data_page;
 #line 464
   __cil_tmp56 = data_ptr / 4096ULL;
 #line 464
   __cil_tmp57 = (unsigned int )__cil_tmp56;
 #line 464
   __cil_tmp58 = __cil_tmp57 - __cil_tmp55;
 #line 464
   data_page_index = (int )__cil_tmp58;
 #line 465
   __cil_tmp59 = (int )data_ptr;
 #line 465
   data_page_offset = __cil_tmp59 & 4095;
 #line 467
   page_length = (int )remain;
   {
 #line 468
   __cil_tmp60 = shmem_page_offset + page_length;
 #line 468
   __cil_tmp61 = (unsigned int )__cil_tmp60;
 #line 468
   if (__cil_tmp61 > 4096U) {
 #line 469
     __cil_tmp62 = (unsigned int )shmem_page_offset;
 #line 469
     __cil_tmp63 = 4096U - __cil_tmp62;
 #line 469
     page_length = (int )__cil_tmp63;
   } else {
 
   }
   }
   {
 #line 470
   __cil_tmp64 = data_page_offset + page_length;
 #line 470
   __cil_tmp65 = (unsigned int )__cil_tmp64;
 #line 470
   if (__cil_tmp65 > 4096U) {
 #line 471
     __cil_tmp66 = (unsigned int )data_page_offset;
 #line 471
     __cil_tmp67 = 4096U - __cil_tmp66;
 #line 471
     page_length = (int )__cil_tmp67;
   } else {
 
   }
   }
   {
 #line 473
   __cil_tmp68 = offset >> 12;
 #line 473
   __cil_tmp69 = (unsigned long )__cil_tmp68;
 #line 473
   page = shmem_read_mapping_page(mapping, __cil_tmp69);
 #line 474
   __cil_tmp70 = (void const   *)page;
 #line 474
   tmp___4 = IS_ERR(__cil_tmp70);
   }
 #line 474
   if (tmp___4 != 0L) {
     {
 #line 475
     __cil_tmp71 = (void const   *)page;
 #line 475
     tmp___3 = PTR_ERR(__cil_tmp71);
 #line 475
     ret = (int )tmp___3;
     }
 #line 476
     goto out;
   } else {
 
   }
 #line 479
   if (do_bit17_swizzling != 0) {
     {
 #line 480
     __cil_tmp72 = (unsigned long )data_page_index;
 #line 480
     __cil_tmp73 = user_pages + __cil_tmp72;
 #line 480
     __cil_tmp74 = *__cil_tmp73;
 #line 480
     slow_shmem_bit17_copy(page, shmem_page_offset, __cil_tmp74, data_page_offset,
                           page_length, 1);
     }
   } else {
     {
 #line 487
     __cil_tmp75 = (unsigned long )data_page_index;
 #line 487
     __cil_tmp76 = user_pages + __cil_tmp75;
 #line 487
     __cil_tmp77 = *__cil_tmp76;
 #line 487
     slow_shmem_copy(__cil_tmp77, data_page_offset, page, shmem_page_offset, page_length);
     }
   }
   {
 #line 494
   mark_page_accessed(page);
 #line 495
   put_page(page);
 #line 497
   __cil_tmp78 = (ssize_t )page_length;
 #line 497
   remain = remain - __cil_tmp78;
 #line 498
   __cil_tmp79 = (uint64_t )page_length;
 #line 498
   data_ptr = __cil_tmp79 + data_ptr;
 #line 499
   __cil_tmp80 = (loff_t )page_length;
 #line 499
   offset = __cil_tmp80 + offset;
   }
   ldv_38912: ;
 #line 453
   if (remain > 0L) {
 #line 454
     goto ldv_38911;
   } else {
 #line 456
     goto ldv_38913;
   }
   ldv_38913: ;
   out: 
 #line 503
   i = 0LL;
 #line 503
   goto ldv_38915;
   ldv_38914: 
   {
 #line 504
   __cil_tmp81 = (unsigned long )i;
 #line 504
   __cil_tmp82 = user_pages + __cil_tmp81;
 #line 504
   __cil_tmp83 = *__cil_tmp82;
 #line 504
   SetPageDirty(__cil_tmp83);
 #line 505
   __cil_tmp84 = (unsigned long )i;
 #line 505
   __cil_tmp85 = user_pages + __cil_tmp84;
 #line 505
   __cil_tmp86 = *__cil_tmp85;
 #line 505
   mark_page_accessed(__cil_tmp86);
 #line 506
   __cil_tmp87 = (unsigned long )i;
 #line 506
   __cil_tmp88 = user_pages + __cil_tmp87;
 #line 506
   __cil_tmp89 = *__cil_tmp88;
 #line 506
   put_page(__cil_tmp89);
 #line 503
   i = i + 1LL;
   }
   ldv_38915: ;
 #line 503
   if (i < pinned_pages) {
 #line 504
     goto ldv_38914;
   } else {
 #line 506
     goto ldv_38916;
   }
   ldv_38916: 
   {
 #line 508
   __cil_tmp90 = (void *)user_pages;
 #line 508
   drm_free_large(__cil_tmp90);
   }
 #line 510
   return (ret);
 }
 }
 #line 519 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_pread_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_pread *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   unsigned long flag ;
   unsigned long roksum ;
   struct thread_info *tmp ;
   long tmp___0 ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp___1 ;
   int tmp___2 ;
   __u64 __cil_tmp14 ;
   __u64 __cil_tmp15 ;
   __u64 __cil_tmp16 ;
   int __cil_tmp17 ;
   long __cil_tmp18 ;
   __u64 __cil_tmp19 ;
   char *__cil_tmp20 ;
   __u64 __cil_tmp21 ;
   int __cil_tmp22 ;
   __u32 __cil_tmp23 ;
   struct drm_gem_object *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_gem_object *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   size_t __cil_tmp28 ;
   unsigned long long __cil_tmp29 ;
   __u64 __cil_tmp30 ;
   __u64 __cil_tmp31 ;
   size_t __cil_tmp32 ;
   unsigned long long __cil_tmp33 ;
   unsigned long long __cil_tmp34 ;
   __u64 __cil_tmp35 ;
   __u64 __cil_tmp36 ;
   u32 __cil_tmp37 ;
   __u64 __cil_tmp38 ;
   u32 __cil_tmp39 ;
   __u64 __cil_tmp40 ;
   __u64 __cil_tmp41 ;
   struct drm_gem_object *__cil_tmp42 ;
   struct mutex *__cil_tmp43 ;
 
   {
 #line 522
   args = (struct drm_i915_gem_pread *)data;
 #line 524
   ret = 0;
   {
 #line 526
   __cil_tmp14 = args->size;
 #line 526
   if (__cil_tmp14 == 0ULL) {
 #line 527
     return (0);
   } else {
 
   }
   }
   {
 #line 529
   tmp = current_thread_info();
 #line 529
   __cil_tmp15 = args->data_ptr;
 #line 529
   __cil_tmp16 = args->size;
 #line 529
   __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" ((char *)__cil_tmp15),
             "g" ((long )__cil_tmp16), "rm" (tmp->addr_limit.seg));
 #line 529
   __cil_tmp17 = flag == 0UL;
 #line 529
   __cil_tmp18 = (long )__cil_tmp17;
 #line 529
   tmp___0 = __builtin_expect(__cil_tmp18, 1L);
   }
 #line 529
   if (tmp___0 == 0L) {
 #line 532
     return (-14);
   } else {
 
   }
   {
 #line 534
   __cil_tmp19 = args->data_ptr;
 #line 534
   __cil_tmp20 = (char *)__cil_tmp19;
 #line 534
   __cil_tmp21 = args->size;
 #line 534
   __cil_tmp22 = (int )__cil_tmp21;
 #line 534
   ret = fault_in_pages_writeable(__cil_tmp20, __cil_tmp22);
   }
 #line 536
   if (ret != 0) {
 #line 537
     return (-14);
   } else {
 
   }
   {
 #line 539
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 540
   if (ret != 0) {
 #line 541
     return (ret);
   } else {
 
   }
   {
 #line 543
   __cil_tmp23 = args->handle;
 #line 543
   tmp___1 = drm_gem_object_lookup(dev, file, __cil_tmp23);
 #line 543
   __mptr = (struct drm_gem_object  const  *)tmp___1;
 #line 543
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 544
   __cil_tmp24 = (struct drm_gem_object *)0;
 #line 544
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 544
   __cil_tmp26 = & obj->base;
 #line 544
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 544
   if (__cil_tmp27 == __cil_tmp25) {
 #line 545
     ret = -2;
 #line 546
     goto unlock;
   } else {
 
   }
   }
   {
 #line 550
   __cil_tmp28 = obj->base.size;
 #line 550
   __cil_tmp29 = (unsigned long long )__cil_tmp28;
 #line 550
   __cil_tmp30 = args->offset;
 #line 550
   if (__cil_tmp30 > __cil_tmp29) {
 #line 552
     ret = -22;
 #line 553
     goto out;
   } else {
     {
 #line 550
     __cil_tmp31 = args->offset;
 #line 550
     __cil_tmp32 = obj->base.size;
 #line 550
     __cil_tmp33 = (unsigned long long )__cil_tmp32;
 #line 550
     __cil_tmp34 = __cil_tmp33 - __cil_tmp31;
 #line 550
     __cil_tmp35 = args->size;
 #line 550
     if (__cil_tmp35 > __cil_tmp34) {
 #line 552
       ret = -22;
 #line 553
       goto out;
     } else {
 
     }
     }
   }
   }
   {
 #line 556
   __cil_tmp36 = args->offset;
 #line 556
   __cil_tmp37 = (u32 )__cil_tmp36;
 #line 556
   __cil_tmp38 = args->size;
 #line 556
   __cil_tmp39 = (u32 )__cil_tmp38;
 #line 556
   trace_i915_gem_object_pread(obj, __cil_tmp37, __cil_tmp39);
 #line 558
   __cil_tmp40 = args->offset;
 #line 558
   __cil_tmp41 = args->size;
 #line 558
   ret = i915_gem_object_set_cpu_read_domain_range(obj, __cil_tmp40, __cil_tmp41);
   }
 #line 561
   if (ret != 0) {
 #line 562
     goto out;
   } else {
 
   }
   {
 #line 564
   ret = -14;
 #line 565
   tmp___2 = i915_gem_object_needs_bit17_swizzle(obj);
   }
 #line 565
   if (tmp___2 == 0) {
     {
 #line 566
     ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
     }
   } else {
 
   }
 #line 567
   if (ret == -14) {
     {
 #line 568
     ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
     }
   } else {
 
   }
   out: 
   {
 #line 571
   __cil_tmp42 = & obj->base;
 #line 571
   drm_gem_object_unreference(__cil_tmp42);
   }
   unlock: 
   {
 #line 573
   __cil_tmp43 = & dev->struct_mutex;
 #line 573
   mutex_unlock(__cil_tmp43);
   }
 #line 574
   return (ret);
 }
 }
 #line 582 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static int fast_user_write(struct io_mapping *mapping , loff_t page_base ,
                                     int page_offset___0 , char *user_data , int length ) 
 { char *vaddr_atomic ;
   unsigned long unwritten ;
   void *tmp ;
   int tmp___0 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   void *__cil_tmp12 ;
   void *__cil_tmp13 ;
   void const   *__cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   void *__cil_tmp16 ;
 
   {
   {
 #line 590
   __cil_tmp10 = (unsigned long )page_base;
 #line 590
   tmp = io_mapping_map_atomic_wc(mapping, __cil_tmp10);
 #line 590
   vaddr_atomic = (char *)tmp;
 #line 591
   __cil_tmp11 = (unsigned long )page_offset___0;
 #line 591
   __cil_tmp12 = (void *)vaddr_atomic;
 #line 591
   __cil_tmp13 = __cil_tmp12 + __cil_tmp11;
 #line 591
   __cil_tmp14 = (void const   *)user_data;
 #line 591
   __cil_tmp15 = (unsigned int )length;
 #line 591
   tmp___0 = __copy_from_user_inatomic_nocache(__cil_tmp13, __cil_tmp14, __cil_tmp15);
 #line 591
   unwritten = (unsigned long )tmp___0;
 #line 593
   __cil_tmp16 = (void *)vaddr_atomic;
 #line 593
   io_mapping_unmap_atomic(__cil_tmp16);
   }
 #line 594
   return ((int )unwritten);
 }
 }
 #line 602 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static void slow_kernel_write(struct io_mapping *mapping , loff_t gtt_base ,
                                        int gtt_offset , struct page *user_page , int user_offset ,
                                        int length ) 
 { char *dst_vaddr ;
   char *src_vaddr ;
   void *tmp ;
   void *tmp___0 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void volatile   *__cil_tmp13 ;
   void volatile   *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   void const   *__cil_tmp16 ;
   void const   *__cil_tmp17 ;
   size_t __cil_tmp18 ;
   void *__cil_tmp19 ;
 
   {
   {
 #line 610
   __cil_tmp11 = (unsigned long )gtt_base;
 #line 610
   tmp = io_mapping_map_atomic_wc(mapping, __cil_tmp11);
 #line 610
   dst_vaddr = (char *)tmp;
 #line 611
   tmp___0 = kmap(user_page);
 #line 611
   src_vaddr = (char *)tmp___0;
 #line 613
   __cil_tmp12 = (unsigned long )gtt_offset;
 #line 613
   __cil_tmp13 = (void volatile   *)dst_vaddr;
 #line 613
   __cil_tmp14 = __cil_tmp13 + __cil_tmp12;
 #line 613
   __cil_tmp15 = (unsigned long )user_offset;
 #line 613
   __cil_tmp16 = (void const   *)src_vaddr;
 #line 613
   __cil_tmp17 = __cil_tmp16 + __cil_tmp15;
 #line 613
   __cil_tmp18 = (size_t )length;
 #line 613
   memcpy_toio(__cil_tmp14, __cil_tmp17, __cil_tmp18);
 #line 617
   kunmap(user_page);
 #line 618
   __cil_tmp19 = (void *)dst_vaddr;
 #line 618
   io_mapping_unmap_atomic(__cil_tmp19);
   }
 #line 619
   return;
 }
 }
 #line 626 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_gtt_pwrite_fast(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                     struct drm_i915_gem_pwrite *args , struct drm_file *file ) 
 { drm_i915_private_t *dev_priv ;
   ssize_t remain ;
   loff_t offset ;
   loff_t page_base ;
   char *user_data ;
   int page_offset___0 ;
   int page_length ;
   int tmp ;
   void *__cil_tmp13 ;
   __u64 __cil_tmp14 ;
   __u64 __cil_tmp15 ;
   __u64 __cil_tmp16 ;
   uint32_t __cil_tmp17 ;
   __u64 __cil_tmp18 ;
   __u64 __cil_tmp19 ;
   int __cil_tmp20 ;
   ssize_t __cil_tmp21 ;
   ssize_t __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   struct io_mapping *__cil_tmp26 ;
   ssize_t __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   loff_t __cil_tmp29 ;
 
   {
 #line 631
   __cil_tmp13 = dev->dev_private;
 #line 631
   dev_priv = (drm_i915_private_t *)__cil_tmp13;
 #line 637
   __cil_tmp14 = args->data_ptr;
 #line 637
   user_data = (char *)__cil_tmp14;
 #line 638
   __cil_tmp15 = args->size;
 #line 638
   remain = (ssize_t )__cil_tmp15;
 #line 640
   __cil_tmp16 = args->offset;
 #line 640
   __cil_tmp17 = obj->gtt_offset;
 #line 640
   __cil_tmp18 = (__u64 )__cil_tmp17;
 #line 640
   __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 640
   offset = (loff_t )__cil_tmp19;
 #line 642
   goto ldv_38965;
   ldv_38964: 
 #line 649
   page_base = offset & -4096LL;
 #line 650
   __cil_tmp20 = (int )offset;
 #line 650
   page_offset___0 = __cil_tmp20 & 4095;
 #line 651
   page_length = (int )remain;
   {
 #line 652
   __cil_tmp21 = (ssize_t )page_offset___0;
 #line 652
   __cil_tmp22 = __cil_tmp21 + remain;
 #line 652
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 652
   if (__cil_tmp23 > 4096UL) {
 #line 653
     __cil_tmp24 = (unsigned int )page_offset___0;
 #line 653
     __cil_tmp25 = 4096U - __cil_tmp24;
 #line 653
     page_length = (int )__cil_tmp25;
   } else {
 
   }
   }
   {
 #line 659
   __cil_tmp26 = dev_priv->mm.gtt_mapping;
 #line 659
   tmp = fast_user_write(__cil_tmp26, page_base, page_offset___0, user_data, page_length);
   }
 #line 659
   if (tmp != 0) {
 #line 661
     return (-14);
   } else {
 
   }
 #line 663
   __cil_tmp27 = (ssize_t )page_length;
 #line 663
   remain = remain - __cil_tmp27;
 #line 664
   __cil_tmp28 = (unsigned long )page_length;
 #line 664
   user_data = user_data + __cil_tmp28;
 #line 665
   __cil_tmp29 = (loff_t )page_length;
 #line 665
   offset = __cil_tmp29 + offset;
   ldv_38965: ;
 #line 642
   if (remain > 0L) {
 #line 643
     goto ldv_38964;
   } else {
 #line 645
     goto ldv_38966;
   }
   ldv_38966: ;
 #line 668
   return (0);
 }
 }
 #line 679 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_gtt_pwrite_slow(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                     struct drm_i915_gem_pwrite *args , struct drm_file *file ) 
 { drm_i915_private_t *dev_priv ;
   ssize_t remain ;
   loff_t gtt_page_base ;
   loff_t offset ;
   loff_t first_data_page ;
   loff_t last_data_page ;
   loff_t num_pages ;
   loff_t pinned_pages ;
   loff_t i ;
   struct page **user_pages ;
   struct mm_struct *mm ;
   struct task_struct *tmp ;
   int gtt_page_offset ;
   int data_page_offset ;
   int data_page_index ;
   int page_length ;
   int ret ;
   uint64_t data_ptr ;
   void *tmp___0 ;
   struct task_struct *tmp___1 ;
   int tmp___2 ;
   void *__cil_tmp26 ;
   __u64 __cil_tmp27 ;
   uint64_t __cil_tmp28 ;
   __u64 __cil_tmp29 ;
   __u64 __cil_tmp30 ;
   __u64 __cil_tmp31 ;
   __u64 __cil_tmp32 ;
   loff_t __cil_tmp33 ;
   size_t __cil_tmp34 ;
   struct page **__cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct mutex *__cil_tmp38 ;
   struct rw_semaphore *__cil_tmp39 ;
   __u64 __cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   int __cil_tmp42 ;
   struct vm_area_struct **__cil_tmp43 ;
   struct rw_semaphore *__cil_tmp44 ;
   struct mutex *__cil_tmp45 ;
   bool __cil_tmp46 ;
   __u64 __cil_tmp47 ;
   uint32_t __cil_tmp48 ;
   __u64 __cil_tmp49 ;
   __u64 __cil_tmp50 ;
   int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   uint64_t __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   struct io_mapping *__cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   struct page **__cil_tmp67 ;
   struct page *__cil_tmp68 ;
   ssize_t __cil_tmp69 ;
   loff_t __cil_tmp70 ;
   uint64_t __cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   struct page **__cil_tmp73 ;
   struct page *__cil_tmp74 ;
   void *__cil_tmp75 ;
 
   {
   {
 #line 684
   __cil_tmp26 = dev->dev_private;
 #line 684
   dev_priv = (drm_i915_private_t *)__cil_tmp26;
 #line 690
   tmp = get_current();
 #line 690
   mm = tmp->mm;
 #line 693
   data_ptr = args->data_ptr;
 #line 695
   __cil_tmp27 = args->size;
 #line 695
   remain = (ssize_t )__cil_tmp27;
 #line 701
   __cil_tmp28 = data_ptr / 4096ULL;
 #line 701
   first_data_page = (loff_t )__cil_tmp28;
 #line 702
   __cil_tmp29 = args->size;
 #line 702
   __cil_tmp30 = __cil_tmp29 + data_ptr;
 #line 702
   __cil_tmp31 = __cil_tmp30 - 1ULL;
 #line 702
   __cil_tmp32 = __cil_tmp31 / 4096ULL;
 #line 702
   last_data_page = (loff_t )__cil_tmp32;
 #line 703
   __cil_tmp33 = last_data_page - first_data_page;
 #line 703
   num_pages = __cil_tmp33 + 1LL;
 #line 705
   __cil_tmp34 = (size_t )num_pages;
 #line 705
   tmp___0 = drm_malloc_ab(__cil_tmp34, 8UL);
 #line 705
   user_pages = (struct page **)tmp___0;
   }
   {
 #line 706
   __cil_tmp35 = (struct page **)0;
 #line 706
   __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 706
   __cil_tmp37 = (unsigned long )user_pages;
 #line 706
   if (__cil_tmp37 == __cil_tmp36) {
 #line 707
     return (-12);
   } else {
 
   }
   }
   {
 #line 709
   __cil_tmp38 = & dev->struct_mutex;
 #line 709
   mutex_unlock(__cil_tmp38);
 #line 710
   __cil_tmp39 = & mm->mmap_sem;
 #line 710
   down_read(__cil_tmp39);
 #line 711
   tmp___1 = get_current();
 #line 711
   __cil_tmp40 = args->data_ptr;
 #line 711
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 711
   __cil_tmp42 = (int )num_pages;
 #line 711
   __cil_tmp43 = (struct vm_area_struct **)0;
 #line 711
   tmp___2 = get_user_pages(tmp___1, mm, __cil_tmp41, __cil_tmp42, 0, 0, user_pages,
                            __cil_tmp43);
 #line 711
   pinned_pages = (loff_t )tmp___2;
 #line 713
   __cil_tmp44 = & mm->mmap_sem;
 #line 713
   up_read(__cil_tmp44);
 #line 714
   __cil_tmp45 = & dev->struct_mutex;
 #line 714
   mutex_lock_nested(__cil_tmp45, 0U);
   }
 #line 715
   if (pinned_pages < num_pages) {
 #line 716
     ret = -14;
 #line 717
     goto out_unpin_pages;
   } else {
 
   }
   {
 #line 720
   __cil_tmp46 = (bool )1;
 #line 720
   ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp46);
   }
 #line 721
   if (ret != 0) {
 #line 722
     goto out_unpin_pages;
   } else {
 
   }
   {
 #line 724
   ret = i915_gem_object_put_fence(obj);
   }
 #line 725
   if (ret != 0) {
 #line 726
     goto out_unpin_pages;
   } else {
 
   }
 #line 728
   __cil_tmp47 = args->offset;
 #line 728
   __cil_tmp48 = obj->gtt_offset;
 #line 728
   __cil_tmp49 = (__u64 )__cil_tmp48;
 #line 728
   __cil_tmp50 = __cil_tmp49 + __cil_tmp47;
 #line 728
   offset = (loff_t )__cil_tmp50;
 #line 730
   goto ldv_38992;
   ldv_38991: 
 #line 739
   gtt_page_base = offset & -4096LL;
 #line 740
   __cil_tmp51 = (int )offset;
 #line 740
   gtt_page_offset = __cil_tmp51 & 4095;
 #line 741
   __cil_tmp52 = (unsigned int )first_data_page;
 #line 741
   __cil_tmp53 = data_ptr / 4096ULL;
 #line 741
   __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 741
   __cil_tmp55 = __cil_tmp54 - __cil_tmp52;
 #line 741
   data_page_index = (int )__cil_tmp55;
 #line 742
   __cil_tmp56 = (int )data_ptr;
 #line 742
   data_page_offset = __cil_tmp56 & 4095;
 #line 744
   page_length = (int )remain;
   {
 #line 745
   __cil_tmp57 = gtt_page_offset + page_length;
 #line 745
   __cil_tmp58 = (unsigned int )__cil_tmp57;
 #line 745
   if (__cil_tmp58 > 4096U) {
 #line 746
     __cil_tmp59 = (unsigned int )gtt_page_offset;
 #line 746
     __cil_tmp60 = 4096U - __cil_tmp59;
 #line 746
     page_length = (int )__cil_tmp60;
   } else {
 
   }
   }
   {
 #line 747
   __cil_tmp61 = data_page_offset + page_length;
 #line 747
   __cil_tmp62 = (unsigned int )__cil_tmp61;
 #line 747
   if (__cil_tmp62 > 4096U) {
 #line 748
     __cil_tmp63 = (unsigned int )data_page_offset;
 #line 748
     __cil_tmp64 = 4096U - __cil_tmp63;
 #line 748
     page_length = (int )__cil_tmp64;
   } else {
 
   }
   }
   {
 #line 750
   __cil_tmp65 = dev_priv->mm.gtt_mapping;
 #line 750
   __cil_tmp66 = (unsigned long )data_page_index;
 #line 750
   __cil_tmp67 = user_pages + __cil_tmp66;
 #line 750
   __cil_tmp68 = *__cil_tmp67;
 #line 750
   slow_kernel_write(__cil_tmp65, gtt_page_base, gtt_page_offset, __cil_tmp68, data_page_offset,
                     page_length);
 #line 756
   __cil_tmp69 = (ssize_t )page_length;
 #line 756
   remain = remain - __cil_tmp69;
 #line 757
   __cil_tmp70 = (loff_t )page_length;
 #line 757
   offset = __cil_tmp70 + offset;
 #line 758
   __cil_tmp71 = (uint64_t )page_length;
 #line 758
   data_ptr = __cil_tmp71 + data_ptr;
   }
   ldv_38992: ;
 #line 730
   if (remain > 0L) {
 #line 731
     goto ldv_38991;
   } else {
 #line 733
     goto ldv_38993;
   }
   ldv_38993: ;
   out_unpin_pages: 
 #line 762
   i = 0LL;
 #line 762
   goto ldv_38995;
   ldv_38994: 
   {
 #line 763
   __cil_tmp72 = (unsigned long )i;
 #line 763
   __cil_tmp73 = user_pages + __cil_tmp72;
 #line 763
   __cil_tmp74 = *__cil_tmp73;
 #line 763
   put_page(__cil_tmp74);
 #line 762
   i = i + 1LL;
   }
   ldv_38995: ;
 #line 762
   if (i < pinned_pages) {
 #line 763
     goto ldv_38994;
   } else {
 #line 765
     goto ldv_38996;
   }
   ldv_38996: 
   {
 #line 764
   __cil_tmp75 = (void *)user_pages;
 #line 764
   drm_free_large(__cil_tmp75);
   }
 #line 766
   return (ret);
 }
 }
 #line 774 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_shmem_pwrite_fast(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                       struct drm_i915_gem_pwrite *args , struct drm_file *file ) 
 { struct address_space *mapping ;
   ssize_t remain ;
   loff_t offset ;
   char *user_data ;
   int page_offset___0 ;
   int page_length ;
   struct page *page ;
   char *vaddr ;
   int ret ;
   long tmp ;
   long tmp___0 ;
   void *tmp___1 ;
   struct file *__cil_tmp17 ;
   struct dentry *__cil_tmp18 ;
   struct inode *__cil_tmp19 ;
   __u64 __cil_tmp20 ;
   __u64 __cil_tmp21 ;
   __u64 __cil_tmp22 ;
   int __cil_tmp23 ;
   ssize_t __cil_tmp24 ;
   ssize_t __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   loff_t __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   void const   *__cil_tmp31 ;
   void const   *__cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   void *__cil_tmp34 ;
   void *__cil_tmp35 ;
   void const   *__cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   void *__cil_tmp38 ;
   ssize_t __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   loff_t __cil_tmp41 ;
 
   {
 #line 779
   __cil_tmp17 = obj->base.filp;
 #line 779
   __cil_tmp18 = __cil_tmp17->f_path.dentry;
 #line 779
   __cil_tmp19 = __cil_tmp18->d_inode;
 #line 779
   mapping = __cil_tmp19->i_mapping;
 #line 785
   __cil_tmp20 = args->data_ptr;
 #line 785
   user_data = (char *)__cil_tmp20;
 #line 786
   __cil_tmp21 = args->size;
 #line 786
   remain = (ssize_t )__cil_tmp21;
 #line 788
   __cil_tmp22 = args->offset;
 #line 788
   offset = (loff_t )__cil_tmp22;
 #line 789
   obj->dirty = (unsigned char)1;
 #line 791
   goto ldv_39013;
   ldv_39012: 
 #line 801
   __cil_tmp23 = (int )offset;
 #line 801
   page_offset___0 = __cil_tmp23 & 4095;
 #line 802
   page_length = (int )remain;
   {
 #line 803
   __cil_tmp24 = (ssize_t )page_offset___0;
 #line 803
   __cil_tmp25 = __cil_tmp24 + remain;
 #line 803
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 803
   if (__cil_tmp26 > 4096UL) {
 #line 804
     __cil_tmp27 = (unsigned int )page_offset___0;
 #line 804
     __cil_tmp28 = 4096U - __cil_tmp27;
 #line 804
     page_length = (int )__cil_tmp28;
   } else {
 
   }
   }
   {
 #line 806
   __cil_tmp29 = offset >> 12;
 #line 806
   __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 806
   page = shmem_read_mapping_page(mapping, __cil_tmp30);
 #line 807
   __cil_tmp31 = (void const   *)page;
 #line 807
   tmp___0 = IS_ERR(__cil_tmp31);
   }
 #line 807
   if (tmp___0 != 0L) {
     {
 #line 808
     __cil_tmp32 = (void const   *)page;
 #line 808
     tmp = PTR_ERR(__cil_tmp32);
     }
 #line 808
     return ((int )tmp);
   } else {
 
   }
   {
 #line 810
   tmp___1 = __kmap_atomic(page);
 #line 810
   vaddr = (char *)tmp___1;
 #line 811
   __cil_tmp33 = (unsigned long )page_offset___0;
 #line 811
   __cil_tmp34 = (void *)vaddr;
 #line 811
   __cil_tmp35 = __cil_tmp34 + __cil_tmp33;
 #line 811
   __cil_tmp36 = (void const   *)user_data;
 #line 811
   __cil_tmp37 = (unsigned int )page_length;
 #line 811
   ret = __copy_from_user_inatomic(__cil_tmp35, __cil_tmp36, __cil_tmp37);
 #line 814
   __cil_tmp38 = (void *)vaddr;
 #line 814
   __kunmap_atomic(__cil_tmp38);
 #line 816
   set_page_dirty(page);
 #line 817
   mark_page_accessed(page);
 #line 818
   put_page(page);
   }
 #line 824
   if (ret != 0) {
 #line 825
     return (-14);
   } else {
 
   }
 #line 827
   __cil_tmp39 = (ssize_t )page_length;
 #line 827
   remain = remain - __cil_tmp39;
 #line 828
   __cil_tmp40 = (unsigned long )page_length;
 #line 828
   user_data = user_data + __cil_tmp40;
 #line 829
   __cil_tmp41 = (loff_t )page_length;
 #line 829
   offset = __cil_tmp41 + offset;
   ldv_39013: ;
 #line 791
   if (remain > 0L) {
 #line 792
     goto ldv_39012;
   } else {
 #line 794
     goto ldv_39014;
   }
   ldv_39014: ;
 #line 832
   return (0);
 }
 }
 #line 843 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_shmem_pwrite_slow(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                       struct drm_i915_gem_pwrite *args , struct drm_file *file ) 
 { struct address_space *mapping ;
   struct mm_struct *mm ;
   struct task_struct *tmp ;
   struct page **user_pages ;
   ssize_t remain ;
   loff_t offset ;
   loff_t pinned_pages ;
   loff_t i ;
   loff_t first_data_page ;
   loff_t last_data_page ;
   loff_t num_pages ;
   int shmem_page_offset ;
   int data_page_index ;
   int data_page_offset ;
   int page_length ;
   int ret ;
   uint64_t data_ptr ;
   int do_bit17_swizzling ;
   void *tmp___0 ;
   struct task_struct *tmp___1 ;
   int tmp___2 ;
   struct page *page ;
   long tmp___3 ;
   long tmp___4 ;
   struct file *__cil_tmp29 ;
   struct dentry *__cil_tmp30 ;
   struct inode *__cil_tmp31 ;
   __u64 __cil_tmp32 ;
   uint64_t __cil_tmp33 ;
   __u64 __cil_tmp34 ;
   __u64 __cil_tmp35 ;
   __u64 __cil_tmp36 ;
   __u64 __cil_tmp37 ;
   loff_t __cil_tmp38 ;
   size_t __cil_tmp39 ;
   struct page **__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct mutex *__cil_tmp43 ;
   struct rw_semaphore *__cil_tmp44 ;
   __u64 __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   int __cil_tmp47 ;
   struct vm_area_struct **__cil_tmp48 ;
   struct rw_semaphore *__cil_tmp49 ;
   struct mutex *__cil_tmp50 ;
   bool __cil_tmp51 ;
   __u64 __cil_tmp52 ;
   int __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   uint64_t __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   int __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   loff_t __cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   void const   *__cil_tmp69 ;
   void const   *__cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   struct page **__cil_tmp72 ;
   struct page *__cil_tmp73 ;
   unsigned long __cil_tmp74 ;
   struct page **__cil_tmp75 ;
   struct page *__cil_tmp76 ;
   ssize_t __cil_tmp77 ;
   uint64_t __cil_tmp78 ;
   loff_t __cil_tmp79 ;
   unsigned long __cil_tmp80 ;
   struct page **__cil_tmp81 ;
   struct page *__cil_tmp82 ;
   void *__cil_tmp83 ;
 
   {
   {
 #line 848
   __cil_tmp29 = obj->base.filp;
 #line 848
   __cil_tmp30 = __cil_tmp29->f_path.dentry;
 #line 848
   __cil_tmp31 = __cil_tmp30->d_inode;
 #line 848
   mapping = __cil_tmp31->i_mapping;
 #line 849
   tmp = get_current();
 #line 849
   mm = tmp->mm;
 #line 858
   data_ptr = args->data_ptr;
 #line 861
   __cil_tmp32 = args->size;
 #line 861
   remain = (ssize_t )__cil_tmp32;
 #line 867
   __cil_tmp33 = data_ptr / 4096ULL;
 #line 867
   first_data_page = (loff_t )__cil_tmp33;
 #line 868
   __cil_tmp34 = args->size;
 #line 868
   __cil_tmp35 = __cil_tmp34 + data_ptr;
 #line 868
   __cil_tmp36 = __cil_tmp35 - 1ULL;
 #line 868
   __cil_tmp37 = __cil_tmp36 / 4096ULL;
 #line 868
   last_data_page = (loff_t )__cil_tmp37;
 #line 869
   __cil_tmp38 = last_data_page - first_data_page;
 #line 869
   num_pages = __cil_tmp38 + 1LL;
 #line 871
   __cil_tmp39 = (size_t )num_pages;
 #line 871
   tmp___0 = drm_malloc_ab(__cil_tmp39, 8UL);
 #line 871
   user_pages = (struct page **)tmp___0;
   }
   {
 #line 872
   __cil_tmp40 = (struct page **)0;
 #line 872
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 872
   __cil_tmp42 = (unsigned long )user_pages;
 #line 872
   if (__cil_tmp42 == __cil_tmp41) {
 #line 873
     return (-12);
   } else {
 
   }
   }
   {
 #line 875
   __cil_tmp43 = & dev->struct_mutex;
 #line 875
   mutex_unlock(__cil_tmp43);
 #line 876
   __cil_tmp44 = & mm->mmap_sem;
 #line 876
   down_read(__cil_tmp44);
 #line 877
   tmp___1 = get_current();
 #line 877
   __cil_tmp45 = args->data_ptr;
 #line 877
   __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 877
   __cil_tmp47 = (int )num_pages;
 #line 877
   __cil_tmp48 = (struct vm_area_struct **)0;
 #line 877
   tmp___2 = get_user_pages(tmp___1, mm, __cil_tmp46, __cil_tmp47, 0, 0, user_pages,
                            __cil_tmp48);
 #line 877
   pinned_pages = (loff_t )tmp___2;
 #line 879
   __cil_tmp49 = & mm->mmap_sem;
 #line 879
   up_read(__cil_tmp49);
 #line 880
   __cil_tmp50 = & dev->struct_mutex;
 #line 880
   mutex_lock_nested(__cil_tmp50, 0U);
   }
 #line 881
   if (pinned_pages < num_pages) {
 #line 882
     ret = -14;
 #line 883
     goto out;
   } else {
 
   }
   {
 #line 886
   __cil_tmp51 = (bool )1;
 #line 886
   ret = i915_gem_object_set_to_cpu_domain(obj, __cil_tmp51);
   }
 #line 887
   if (ret != 0) {
 #line 888
     goto out;
   } else {
 
   }
   {
 #line 890
   do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 #line 892
   __cil_tmp52 = args->offset;
 #line 892
   offset = (loff_t )__cil_tmp52;
 #line 893
   obj->dirty = (unsigned char)1;
   }
 #line 895
   goto ldv_39041;
   ldv_39040: 
 #line 905
   __cil_tmp53 = (int )offset;
 #line 905
   shmem_page_offset = __cil_tmp53 & 4095;
 #line 906
   __cil_tmp54 = (unsigned int )first_data_page;
 #line 906
   __cil_tmp55 = data_ptr / 4096ULL;
 #line 906
   __cil_tmp56 = (unsigned int )__cil_tmp55;
 #line 906
   __cil_tmp57 = __cil_tmp56 - __cil_tmp54;
 #line 906
   data_page_index = (int )__cil_tmp57;
 #line 907
   __cil_tmp58 = (int )data_ptr;
 #line 907
   data_page_offset = __cil_tmp58 & 4095;
 #line 909
   page_length = (int )remain;
   {
 #line 910
   __cil_tmp59 = shmem_page_offset + page_length;
 #line 910
   __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 910
   if (__cil_tmp60 > 4096U) {
 #line 911
     __cil_tmp61 = (unsigned int )shmem_page_offset;
 #line 911
     __cil_tmp62 = 4096U - __cil_tmp61;
 #line 911
     page_length = (int )__cil_tmp62;
   } else {
 
   }
   }
   {
 #line 912
   __cil_tmp63 = data_page_offset + page_length;
 #line 912
   __cil_tmp64 = (unsigned int )__cil_tmp63;
 #line 912
   if (__cil_tmp64 > 4096U) {
 #line 913
     __cil_tmp65 = (unsigned int )data_page_offset;
 #line 913
     __cil_tmp66 = 4096U - __cil_tmp65;
 #line 913
     page_length = (int )__cil_tmp66;
   } else {
 
   }
   }
   {
 #line 915
   __cil_tmp67 = offset >> 12;
 #line 915
   __cil_tmp68 = (unsigned long )__cil_tmp67;
 #line 915
   page = shmem_read_mapping_page(mapping, __cil_tmp68);
 #line 916
   __cil_tmp69 = (void const   *)page;
 #line 916
   tmp___4 = IS_ERR(__cil_tmp69);
   }
 #line 916
   if (tmp___4 != 0L) {
     {
 #line 917
     __cil_tmp70 = (void const   *)page;
 #line 917
     tmp___3 = PTR_ERR(__cil_tmp70);
 #line 917
     ret = (int )tmp___3;
     }
 #line 918
     goto out;
   } else {
 
   }
 #line 921
   if (do_bit17_swizzling != 0) {
     {
 #line 922
     __cil_tmp71 = (unsigned long )data_page_index;
 #line 922
     __cil_tmp72 = user_pages + __cil_tmp71;
 #line 922
     __cil_tmp73 = *__cil_tmp72;
 #line 922
     slow_shmem_bit17_copy(page, shmem_page_offset, __cil_tmp73, data_page_offset,
                           page_length, 0);
     }
   } else {
     {
 #line 929
     __cil_tmp74 = (unsigned long )data_page_index;
 #line 929
     __cil_tmp75 = user_pages + __cil_tmp74;
 #line 929
     __cil_tmp76 = *__cil_tmp75;
 #line 929
     slow_shmem_copy(page, shmem_page_offset, __cil_tmp76, data_page_offset, page_length);
     }
   }
   {
 #line 936
   set_page_dirty(page);
 #line 937
   mark_page_accessed(page);
 #line 938
   put_page(page);
 #line 940
   __cil_tmp77 = (ssize_t )page_length;
 #line 940
   remain = remain - __cil_tmp77;
 #line 941
   __cil_tmp78 = (uint64_t )page_length;
 #line 941
   data_ptr = __cil_tmp78 + data_ptr;
 #line 942
   __cil_tmp79 = (loff_t )page_length;
 #line 942
   offset = __cil_tmp79 + offset;
   }
   ldv_39041: ;
 #line 895
   if (remain > 0L) {
 #line 896
     goto ldv_39040;
   } else {
 #line 898
     goto ldv_39042;
   }
   ldv_39042: ;
   out: 
 #line 946
   i = 0LL;
 #line 946
   goto ldv_39044;
   ldv_39043: 
   {
 #line 947
   __cil_tmp80 = (unsigned long )i;
 #line 947
   __cil_tmp81 = user_pages + __cil_tmp80;
 #line 947
   __cil_tmp82 = *__cil_tmp81;
 #line 947
   put_page(__cil_tmp82);
 #line 946
   i = i + 1LL;
   }
   ldv_39044: ;
 #line 946
   if (i < pinned_pages) {
 #line 947
     goto ldv_39043;
   } else {
 #line 949
     goto ldv_39045;
   }
   ldv_39045: 
   {
 #line 948
   __cil_tmp83 = (void *)user_pages;
 #line 948
   drm_free_large(__cil_tmp83);
   }
 #line 950
   return (ret);
 }
 }
 #line 959 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_pwrite_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_pwrite *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   unsigned long flag ;
   unsigned long roksum ;
   struct thread_info *tmp ;
   long tmp___0 ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp___1 ;
   int tmp___2 ;
   __u64 __cil_tmp14 ;
   __u64 __cil_tmp15 ;
   __u64 __cil_tmp16 ;
   int __cil_tmp17 ;
   long __cil_tmp18 ;
   __u64 __cil_tmp19 ;
   char const   *__cil_tmp20 ;
   __u64 __cil_tmp21 ;
   int __cil_tmp22 ;
   __u32 __cil_tmp23 ;
   struct drm_gem_object *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_gem_object *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   size_t __cil_tmp28 ;
   unsigned long long __cil_tmp29 ;
   __u64 __cil_tmp30 ;
   __u64 __cil_tmp31 ;
   size_t __cil_tmp32 ;
   unsigned long long __cil_tmp33 ;
   unsigned long long __cil_tmp34 ;
   __u64 __cil_tmp35 ;
   __u64 __cil_tmp36 ;
   u32 __cil_tmp37 ;
   __u64 __cil_tmp38 ;
   u32 __cil_tmp39 ;
   struct drm_i915_gem_phys_object *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   struct drm_i915_gem_phys_object *__cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   struct drm_mm_node *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct drm_mm_node *__cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   uint32_t __cil_tmp48 ;
   bool __cil_tmp49 ;
   bool __cil_tmp50 ;
   bool __cil_tmp51 ;
   struct drm_gem_object *__cil_tmp52 ;
   struct mutex *__cil_tmp53 ;
 
   {
 #line 962
   args = (struct drm_i915_gem_pwrite *)data;
   {
 #line 966
   __cil_tmp14 = args->size;
 #line 966
   if (__cil_tmp14 == 0ULL) {
 #line 967
     return (0);
   } else {
 
   }
   }
   {
 #line 969
   tmp = current_thread_info();
 #line 969
   __cil_tmp15 = args->data_ptr;
 #line 969
   __cil_tmp16 = args->size;
 #line 969
   __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" ((char *)__cil_tmp15),
             "g" ((long )__cil_tmp16), "rm" (tmp->addr_limit.seg));
 #line 969
   __cil_tmp17 = flag == 0UL;
 #line 969
   __cil_tmp18 = (long )__cil_tmp17;
 #line 969
   tmp___0 = __builtin_expect(__cil_tmp18, 1L);
   }
 #line 969
   if (tmp___0 == 0L) {
 #line 972
     return (-14);
   } else {
 
   }
   {
 #line 974
   __cil_tmp19 = args->data_ptr;
 #line 974
   __cil_tmp20 = (char const   *)__cil_tmp19;
 #line 974
   __cil_tmp21 = args->size;
 #line 974
   __cil_tmp22 = (int )__cil_tmp21;
 #line 974
   ret = fault_in_pages_readable(__cil_tmp20, __cil_tmp22);
   }
 #line 976
   if (ret != 0) {
 #line 977
     return (-14);
   } else {
 
   }
   {
 #line 979
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 980
   if (ret != 0) {
 #line 981
     return (ret);
   } else {
 
   }
   {
 #line 983
   __cil_tmp23 = args->handle;
 #line 983
   tmp___1 = drm_gem_object_lookup(dev, file, __cil_tmp23);
 #line 983
   __mptr = (struct drm_gem_object  const  *)tmp___1;
 #line 983
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 984
   __cil_tmp24 = (struct drm_gem_object *)0;
 #line 984
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 984
   __cil_tmp26 = & obj->base;
 #line 984
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 984
   if (__cil_tmp27 == __cil_tmp25) {
 #line 985
     ret = -2;
 #line 986
     goto unlock;
   } else {
 
   }
   }
   {
 #line 990
   __cil_tmp28 = obj->base.size;
 #line 990
   __cil_tmp29 = (unsigned long long )__cil_tmp28;
 #line 990
   __cil_tmp30 = args->offset;
 #line 990
   if (__cil_tmp30 > __cil_tmp29) {
 #line 992
     ret = -22;
 #line 993
     goto out;
   } else {
     {
 #line 990
     __cil_tmp31 = args->offset;
 #line 990
     __cil_tmp32 = obj->base.size;
 #line 990
     __cil_tmp33 = (unsigned long long )__cil_tmp32;
 #line 990
     __cil_tmp34 = __cil_tmp33 - __cil_tmp31;
 #line 990
     __cil_tmp35 = args->size;
 #line 990
     if (__cil_tmp35 > __cil_tmp34) {
 #line 992
       ret = -22;
 #line 993
       goto out;
     } else {
 
     }
     }
   }
   }
   {
 #line 996
   __cil_tmp36 = args->offset;
 #line 996
   __cil_tmp37 = (u32 )__cil_tmp36;
 #line 996
   __cil_tmp38 = args->size;
 #line 996
   __cil_tmp39 = (u32 )__cil_tmp38;
 #line 996
   trace_i915_gem_object_pwrite(obj, __cil_tmp37, __cil_tmp39);
   }
   {
 #line 1004
   __cil_tmp40 = (struct drm_i915_gem_phys_object *)0;
 #line 1004
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 1004
   __cil_tmp42 = obj->phys_obj;
 #line 1004
   __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 1004
   if (__cil_tmp43 != __cil_tmp41) {
     {
 #line 1005
     ret = i915_gem_phys_pwrite(dev, obj, args, file);
     }
   } else {
     {
 #line 1006
     __cil_tmp44 = (struct drm_mm_node *)0;
 #line 1006
     __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 1006
     __cil_tmp46 = obj->gtt_space;
 #line 1006
     __cil_tmp47 = (unsigned long )__cil_tmp46;
 #line 1006
     if (__cil_tmp47 != __cil_tmp45) {
       {
 #line 1006
       __cil_tmp48 = obj->base.write_domain;
 #line 1006
       if (__cil_tmp48 != 1U) {
         {
 #line 1008
         __cil_tmp49 = (bool )1;
 #line 1008
         ret = i915_gem_object_pin(obj, 0U, __cil_tmp49);
         }
 #line 1009
         if (ret != 0) {
 #line 1010
           goto out;
         } else {
 
         }
         {
 #line 1012
         __cil_tmp50 = (bool )1;
 #line 1012
         ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp50);
         }
 #line 1013
         if (ret != 0) {
 #line 1014
           goto out_unpin;
         } else {
 
         }
         {
 #line 1016
         ret = i915_gem_object_put_fence(obj);
         }
 #line 1017
         if (ret != 0) {
 #line 1018
           goto out_unpin;
         } else {
 
         }
         {
 #line 1020
         ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
         }
 #line 1021
         if (ret == -14) {
           {
 #line 1022
           ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
           }
         } else {
 
         }
         out_unpin: 
         {
 #line 1025
         i915_gem_object_unpin(obj);
         }
       } else {
 #line 1006
         goto _L;
       }
       }
     } else {
       _L: 
       {
 #line 1027
       __cil_tmp51 = (bool )1;
 #line 1027
       ret = i915_gem_object_set_to_cpu_domain(obj, __cil_tmp51);
       }
 #line 1028
       if (ret != 0) {
 #line 1029
         goto out;
       } else {
 
       }
       {
 #line 1031
       ret = -14;
 #line 1032
       tmp___2 = i915_gem_object_needs_bit17_swizzle(obj);
       }
 #line 1032
       if (tmp___2 == 0) {
         {
 #line 1033
         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
         }
       } else {
 
       }
 #line 1034
       if (ret == -14) {
         {
 #line 1035
         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
         }
       } else {
 
       }
     }
     }
   }
   }
   out: 
   {
 #line 1039
   __cil_tmp52 = & obj->base;
 #line 1039
   drm_gem_object_unreference(__cil_tmp52);
   }
   unlock: 
   {
 #line 1041
   __cil_tmp53 = & dev->struct_mutex;
 #line 1041
   mutex_unlock(__cil_tmp53);
   }
 #line 1042
   return (ret);
 }
 }
 #line 1050 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_set_domain_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_set_domain *args ;
   struct drm_i915_gem_object *obj ;
   uint32_t read_domains ;
   uint32_t write_domain ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   struct drm_driver *__cil_tmp11 ;
   u32 __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   __u32 __cil_tmp16 ;
   struct drm_gem_object *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct drm_gem_object *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   int __cil_tmp22 ;
   bool __cil_tmp23 ;
   int __cil_tmp24 ;
   bool __cil_tmp25 ;
   struct drm_gem_object *__cil_tmp26 ;
   struct mutex *__cil_tmp27 ;
 
   {
 #line 1053
   args = (struct drm_i915_gem_set_domain *)data;
 #line 1055
   read_domains = args->read_domains;
 #line 1056
   write_domain = args->write_domain;
   {
 #line 1059
   __cil_tmp11 = dev->driver;
 #line 1059
   __cil_tmp12 = __cil_tmp11->driver_features;
 #line 1059
   __cil_tmp13 = __cil_tmp12 & 4096U;
 #line 1059
   if (__cil_tmp13 == 0U) {
 #line 1060
     return (-19);
   } else {
 
   }
   }
   {
 #line 1063
   __cil_tmp14 = write_domain & 4294967230U;
 #line 1063
   if (__cil_tmp14 != 0U) {
 #line 1064
     return (-22);
   } else {
 
   }
   }
   {
 #line 1066
   __cil_tmp15 = read_domains & 4294967230U;
 #line 1066
   if (__cil_tmp15 != 0U) {
 #line 1067
     return (-22);
   } else {
 
   }
   }
 #line 1072
   if (write_domain != 0U) {
 #line 1072
     if (read_domains != write_domain) {
 #line 1073
       return (-22);
     } else {
 
     }
   } else {
 
   }
   {
 #line 1075
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 1076
   if (ret != 0) {
 #line 1077
     return (ret);
   } else {
 
   }
   {
 #line 1079
   __cil_tmp16 = args->handle;
 #line 1079
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp16);
 #line 1079
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 1079
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 1080
   __cil_tmp17 = (struct drm_gem_object *)0;
 #line 1080
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 1080
   __cil_tmp19 = & obj->base;
 #line 1080
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 1080
   if (__cil_tmp20 == __cil_tmp18) {
 #line 1081
     ret = -2;
 #line 1082
     goto unlock;
   } else {
 
   }
   }
   {
 #line 1085
   __cil_tmp21 = read_domains & 64U;
 #line 1085
   if (__cil_tmp21 != 0U) {
     {
 #line 1086
     __cil_tmp22 = write_domain != 0U;
 #line 1086
     __cil_tmp23 = (bool )__cil_tmp22;
 #line 1086
     ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp23);
     }
 #line 1092
     if (ret == -22) {
 #line 1093
       ret = 0;
     } else {
 
     }
   } else {
     {
 #line 1095
     __cil_tmp24 = write_domain != 0U;
 #line 1095
     __cil_tmp25 = (bool )__cil_tmp24;
 #line 1095
     ret = i915_gem_object_set_to_cpu_domain(obj, __cil_tmp25);
     }
   }
   }
   {
 #line 1098
   __cil_tmp26 = & obj->base;
 #line 1098
   drm_gem_object_unreference(__cil_tmp26);
   }
   unlock: 
   {
 #line 1100
   __cil_tmp27 = & dev->struct_mutex;
 #line 1100
   mutex_unlock(__cil_tmp27);
   }
 #line 1101
   return (ret);
 }
 }
 #line 1108 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_sw_finish_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_sw_finish *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   struct drm_driver *__cil_tmp9 ;
   u32 __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   __u32 __cil_tmp12 ;
   struct drm_gem_object *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct drm_gem_object *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned int *__cil_tmp17 ;
   unsigned int *__cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   struct drm_gem_object *__cil_tmp20 ;
   struct mutex *__cil_tmp21 ;
 
   {
 #line 1111
   args = (struct drm_i915_gem_sw_finish *)data;
 #line 1113
   ret = 0;
   {
 #line 1115
   __cil_tmp9 = dev->driver;
 #line 1115
   __cil_tmp10 = __cil_tmp9->driver_features;
 #line 1115
   __cil_tmp11 = __cil_tmp10 & 4096U;
 #line 1115
   if (__cil_tmp11 == 0U) {
 #line 1116
     return (-19);
   } else {
 
   }
   }
   {
 #line 1118
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 1119
   if (ret != 0) {
 #line 1120
     return (ret);
   } else {
 
   }
   {
 #line 1122
   __cil_tmp12 = args->handle;
 #line 1122
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp12);
 #line 1122
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 1122
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 1123
   __cil_tmp13 = (struct drm_gem_object *)0;
 #line 1123
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 1123
   __cil_tmp15 = & obj->base;
 #line 1123
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 1123
   if (__cil_tmp16 == __cil_tmp14) {
 #line 1124
     ret = -2;
 #line 1125
     goto unlock;
   } else {
 
   }
   }
   {
 #line 1129
   __cil_tmp17 = (unsigned int *)obj;
 #line 1129
   __cil_tmp18 = __cil_tmp17 + 56UL;
 #line 1129
   __cil_tmp19 = *__cil_tmp18;
 #line 1129
   if (__cil_tmp19 != 0U) {
     {
 #line 1130
     i915_gem_object_flush_cpu_write_domain(obj);
     }
   } else {
 
   }
   }
   {
 #line 1132
   __cil_tmp20 = & obj->base;
 #line 1132
   drm_gem_object_unreference(__cil_tmp20);
   }
   unlock: 
   {
 #line 1134
   __cil_tmp21 = & dev->struct_mutex;
 #line 1134
   mutex_unlock(__cil_tmp21);
   }
 #line 1135
   return (ret);
 }
 }
 #line 1146 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_mmap_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_mmap *args ;
   struct drm_gem_object *obj ;
   unsigned long addr ;
   struct task_struct *tmp ;
   struct task_struct *tmp___0 ;
   long tmp___1 ;
   void *__cil_tmp11 ;
   struct drm_driver *__cil_tmp12 ;
   u32 __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   __u32 __cil_tmp15 ;
   struct drm_gem_object *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   size_t __cil_tmp20 ;
   struct mm_struct *__cil_tmp21 ;
   struct rw_semaphore *__cil_tmp22 ;
   struct file *__cil_tmp23 ;
   __u64 __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   __u64 __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct mm_struct *__cil_tmp28 ;
   struct rw_semaphore *__cil_tmp29 ;
   void const   *__cil_tmp30 ;
 
   {
 #line 1149
   __cil_tmp11 = dev->dev_private;
 #line 1149
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 1150
   args = (struct drm_i915_gem_mmap *)data;
   {
 #line 1154
   __cil_tmp12 = dev->driver;
 #line 1154
   __cil_tmp13 = __cil_tmp12->driver_features;
 #line 1154
   __cil_tmp14 = __cil_tmp13 & 4096U;
 #line 1154
   if (__cil_tmp14 == 0U) {
 #line 1155
     return (-19);
   } else {
 
   }
   }
   {
 #line 1157
   __cil_tmp15 = args->handle;
 #line 1157
   obj = drm_gem_object_lookup(dev, file, __cil_tmp15);
   }
   {
 #line 1158
   __cil_tmp16 = (struct drm_gem_object *)0;
 #line 1158
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 1158
   __cil_tmp18 = (unsigned long )obj;
 #line 1158
   if (__cil_tmp18 == __cil_tmp17) {
 #line 1159
     return (-2);
   } else {
 
   }
   }
   {
 #line 1161
   __cil_tmp19 = dev_priv->mm.gtt_mappable_end;
 #line 1161
   __cil_tmp20 = obj->size;
 #line 1161
   if (__cil_tmp20 > __cil_tmp19) {
     {
 #line 1162
     drm_gem_object_unreference_unlocked(obj);
     }
 #line 1163
     return (-7);
   } else {
 
   }
   }
   {
 #line 1166
   tmp = get_current();
 #line 1166
   __cil_tmp21 = tmp->mm;
 #line 1166
   __cil_tmp22 = & __cil_tmp21->mmap_sem;
 #line 1166
   down_write(__cil_tmp22);
 #line 1167
   __cil_tmp23 = obj->filp;
 #line 1167
   __cil_tmp24 = args->size;
 #line 1167
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 1167
   __cil_tmp26 = args->offset;
 #line 1167
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 1167
   addr = do_mmap(__cil_tmp23, 0UL, __cil_tmp25, 3UL, 1UL, __cil_tmp27);
 #line 1170
   tmp___0 = get_current();
 #line 1170
   __cil_tmp28 = tmp___0->mm;
 #line 1170
   __cil_tmp29 = & __cil_tmp28->mmap_sem;
 #line 1170
   up_write(__cil_tmp29);
 #line 1171
   drm_gem_object_unreference_unlocked(obj);
 #line 1172
   __cil_tmp30 = (void const   *)addr;
 #line 1172
   tmp___1 = IS_ERR(__cil_tmp30);
   }
 #line 1172
   if (tmp___1 != 0L) {
 #line 1173
     return ((int )addr);
   } else {
 
   }
 #line 1175
   args->addr_ptr = (unsigned long long )addr;
 #line 1177
   return (0);
 }
 }
 #line 1196 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_fault(struct vm_area_struct *vma , struct vm_fault *vmf ) 
 { struct drm_i915_gem_object *obj ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   unsigned long page_offset___0 ;
   unsigned long pfn ;
   int ret ;
   bool write ;
   bool tmp ;
   struct thread_info *tmp___0 ;
   void *__cil_tmp13 ;
   void *__cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   u32 __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   bool __cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   struct drm_mm_node *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   struct drm_mm_node *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   bool __cil_tmp35 ;
   int __cil_tmp36 ;
   bool __cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   struct intel_ring_buffer *__cil_tmp42 ;
   struct list_head *__cil_tmp43 ;
   struct list_head *__cil_tmp44 ;
   uint32_t __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   struct drm_agp_head *__cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   void *__cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   struct mutex *__cil_tmp53 ;
 
   {
   {
 #line 1198
   __cil_tmp13 = vma->vm_private_data;
 #line 1198
   __mptr = (struct drm_gem_object  const  *)__cil_tmp13;
 #line 1198
   obj = (struct drm_i915_gem_object *)__mptr;
 #line 1199
   dev = obj->base.dev;
 #line 1200
   __cil_tmp14 = dev->dev_private;
 #line 1200
   dev_priv = (drm_i915_private_t *)__cil_tmp14;
 #line 1203
   ret = 0;
 #line 1204
   __cil_tmp15 = vmf->flags;
 #line 1204
   __cil_tmp16 = (int )__cil_tmp15;
 #line 1204
   __cil_tmp17 = __cil_tmp16 & 1;
 #line 1204
   __cil_tmp18 = __cil_tmp17 != 0;
 #line 1204
   write = (bool )__cil_tmp18;
 #line 1207
   __cil_tmp19 = vma->vm_start;
 #line 1207
   __cil_tmp20 = vmf->virtual_address;
 #line 1207
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 1207
   __cil_tmp22 = __cil_tmp21 - __cil_tmp19;
 #line 1207
   page_offset___0 = __cil_tmp22 >> 12;
 #line 1210
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 1211
   if (ret != 0) {
 #line 1212
     goto out;
   } else {
 
   }
   {
 #line 1214
   __cil_tmp23 = (u32 )page_offset___0;
 #line 1214
   __cil_tmp24 = (bool )1;
 #line 1214
   __cil_tmp25 = (int )write;
 #line 1214
   __cil_tmp26 = (bool )__cil_tmp25;
 #line 1214
   trace_i915_gem_object_fault(obj, __cil_tmp23, __cil_tmp24, __cil_tmp26);
   }
   {
 #line 1217
   __cil_tmp27 = (unsigned char *)obj;
 #line 1217
   __cil_tmp28 = __cil_tmp27 + 226UL;
 #line 1217
   __cil_tmp29 = *__cil_tmp28;
 #line 1217
   __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 1217
   if (__cil_tmp30 == 0U) {
     {
 #line 1218
     ret = i915_gem_object_unbind(obj);
     }
 #line 1219
     if (ret != 0) {
 #line 1220
       goto unlock;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1222
   __cil_tmp31 = (struct drm_mm_node *)0;
 #line 1222
   __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 1222
   __cil_tmp33 = obj->gtt_space;
 #line 1222
   __cil_tmp34 = (unsigned long )__cil_tmp33;
 #line 1222
   if (__cil_tmp34 == __cil_tmp32) {
     {
 #line 1223
     __cil_tmp35 = (bool )1;
 #line 1223
     ret = i915_gem_object_bind_to_gtt(obj, 0U, __cil_tmp35);
     }
 #line 1224
     if (ret != 0) {
 #line 1225
       goto unlock;
     } else {
 
     }
     {
 #line 1227
     __cil_tmp36 = (int )write;
 #line 1227
     __cil_tmp37 = (bool )__cil_tmp36;
 #line 1227
     ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp37);
     }
 #line 1228
     if (ret != 0) {
 #line 1229
       goto unlock;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1232
   __cil_tmp38 = (unsigned char *)obj;
 #line 1232
   __cil_tmp39 = __cil_tmp38 + 225UL;
 #line 1232
   __cil_tmp40 = *__cil_tmp39;
 #line 1232
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 1232
   if (__cil_tmp41 == 0U) {
     {
 #line 1233
     ret = i915_gem_object_put_fence(obj);
     }
   } else {
     {
 #line 1235
     __cil_tmp42 = (struct intel_ring_buffer *)0;
 #line 1235
     ret = i915_gem_object_get_fence(obj, __cil_tmp42);
     }
   }
   }
 #line 1236
   if (ret != 0) {
 #line 1237
     goto unlock;
   } else {
 
   }
   {
 #line 1239
   tmp = i915_gem_object_is_inactive(obj);
   }
 #line 1239
   if ((int )tmp) {
     {
 #line 1240
     __cil_tmp43 = & obj->mm_list;
 #line 1240
     __cil_tmp44 = & dev_priv->mm.inactive_list;
 #line 1240
     list_move_tail(__cil_tmp43, __cil_tmp44);
     }
   } else {
 
   }
   {
 #line 1242
   obj->fault_mappable = (unsigned char)1;
 #line 1244
   __cil_tmp45 = obj->gtt_offset;
 #line 1244
   __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 1244
   __cil_tmp47 = dev->agp;
 #line 1244
   __cil_tmp48 = __cil_tmp47->base;
 #line 1244
   __cil_tmp49 = __cil_tmp48 + __cil_tmp46;
 #line 1244
   __cil_tmp50 = __cil_tmp49 >> 12;
 #line 1244
   pfn = __cil_tmp50 + page_offset___0;
 #line 1248
   __cil_tmp51 = vmf->virtual_address;
 #line 1248
   __cil_tmp52 = (unsigned long )__cil_tmp51;
 #line 1248
   ret = vm_insert_pfn(vma, __cil_tmp52, pfn);
   }
   unlock: 
   {
 #line 1250
   __cil_tmp53 = & dev->struct_mutex;
 #line 1250
   mutex_unlock(__cil_tmp53);
   }
   out: ;
 #line 1253
   if (ret == -5) {
 #line 1253
     goto case_neg_5;
   } else
 #line 1254
   if (ret == -11) {
 #line 1254
     goto case_neg_11;
   } else
 #line 1263
   if (ret == 0) {
 #line 1263
     goto case_0;
   } else
 #line 1264
   if (ret == -512) {
 #line 1264
     goto case_neg_512;
   } else
 #line 1265
   if (ret == -4) {
 #line 1265
     goto case_neg_4;
   } else
 #line 1267
   if (ret == -12) {
 #line 1267
     goto case_neg_12;
   } else {
 #line 1269
     goto switch_default;
 #line 1252
     if (0) {
       case_neg_5: ;
       case_neg_11: 
       {
 #line 1262
       tmp___0 = current_thread_info();
 #line 1262
       set_ti_thread_flag(tmp___0, 3);
       }
       case_0: ;
       case_neg_512: ;
       case_neg_4: ;
 #line 1266
       return (256);
       case_neg_12: ;
 #line 1268
       return (1);
       switch_default: ;
 #line 1270
       return (2);
     } else {
 
     }
   }
 }
 }
 #line 1286 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   struct drm_gem_mm *mm ;
   struct drm_map_list *list ;
   struct drm_local_map *map ;
   int ret ;
   void *tmp ;
   void *__cil_tmp8 ;
   struct drm_local_map *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct drm_local_map *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_mm *__cil_tmp13 ;
   struct drm_mm  const  *__cil_tmp14 ;
   size_t __cil_tmp15 ;
   size_t __cil_tmp16 ;
   struct drm_mm_node *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct drm_mm_node *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   int __cil_tmp21 ;
   struct drm_mm_node *__cil_tmp22 ;
   size_t __cil_tmp23 ;
   size_t __cil_tmp24 ;
   struct drm_mm_node *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   struct drm_mm_node *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_mm_node *__cil_tmp29 ;
   struct drm_open_hash *__cil_tmp30 ;
   struct drm_hash_item *__cil_tmp31 ;
   struct drm_mm_node *__cil_tmp32 ;
   struct drm_local_map *__cil_tmp33 ;
   void const   *__cil_tmp34 ;
 
   {
   {
 #line 1288
   dev = obj->base.dev;
 #line 1289
   __cil_tmp8 = dev->mm_private;
 #line 1289
   mm = (struct drm_gem_mm *)__cil_tmp8;
 #line 1292
   ret = 0;
 #line 1295
   list = & obj->base.map_list;
 #line 1296
   tmp = kzalloc(72UL, 208U);
 #line 1296
   list->map = (struct drm_local_map *)tmp;
   }
   {
 #line 1297
   __cil_tmp9 = (struct drm_local_map *)0;
 #line 1297
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 1297
   __cil_tmp11 = list->map;
 #line 1297
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 1297
   if (__cil_tmp12 == __cil_tmp10) {
 #line 1298
     return (-12);
   } else {
 
   }
   }
   {
 #line 1300
   map = list->map;
 #line 1301
   map->type = (enum drm_map_type )6;
 #line 1302
   map->size = obj->base.size;
 #line 1303
   map->handle = (void *)obj;
 #line 1306
   __cil_tmp13 = & mm->offset_manager;
 #line 1306
   __cil_tmp14 = (struct drm_mm  const  *)__cil_tmp13;
 #line 1306
   __cil_tmp15 = obj->base.size;
 #line 1306
   __cil_tmp16 = __cil_tmp15 / 4096UL;
 #line 1306
   list->file_offset_node = drm_mm_search_free(__cil_tmp14, __cil_tmp16, 0U, 0);
   }
   {
 #line 1309
   __cil_tmp17 = (struct drm_mm_node *)0;
 #line 1309
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 1309
   __cil_tmp19 = list->file_offset_node;
 #line 1309
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 1309
   if (__cil_tmp20 == __cil_tmp18) {
     {
 #line 1310
     __cil_tmp21 = obj->base.name;
 #line 1310
     drm_err("i915_gem_create_mmap_offset", "failed to allocate offset for bo %d\n",
             __cil_tmp21);
 #line 1312
     ret = -28;
     }
 #line 1313
     goto out_free_list;
   } else {
 
   }
   }
   {
 #line 1316
   __cil_tmp22 = list->file_offset_node;
 #line 1316
   __cil_tmp23 = obj->base.size;
 #line 1316
   __cil_tmp24 = __cil_tmp23 / 4096UL;
 #line 1316
   list->file_offset_node = drm_mm_get_block(__cil_tmp22, __cil_tmp24, 0U);
   }
   {
 #line 1319
   __cil_tmp25 = (struct drm_mm_node *)0;
 #line 1319
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 1319
   __cil_tmp27 = list->file_offset_node;
 #line 1319
   __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 1319
   if (__cil_tmp28 == __cil_tmp26) {
 #line 1320
     ret = -12;
 #line 1321
     goto out_free_list;
   } else {
 
   }
   }
   {
 #line 1324
   __cil_tmp29 = list->file_offset_node;
 #line 1324
   list->hash.key = __cil_tmp29->start;
 #line 1325
   __cil_tmp30 = & mm->offset_hash;
 #line 1325
   __cil_tmp31 = & list->hash;
 #line 1325
   ret = drm_ht_insert_item(__cil_tmp30, __cil_tmp31);
   }
 #line 1326
   if (ret != 0) {
     {
 #line 1327
     drm_err("i915_gem_create_mmap_offset", "failed to add to map hash\n");
     }
 #line 1328
     goto out_free_mm;
   } else {
 
   }
 #line 1331
   return (0);
   out_free_mm: 
   {
 #line 1334
   __cil_tmp32 = list->file_offset_node;
 #line 1334
   drm_mm_put_block(__cil_tmp32);
   }
   out_free_list: 
   {
 #line 1336
   __cil_tmp33 = list->map;
 #line 1336
   __cil_tmp34 = (void const   *)__cil_tmp33;
 #line 1336
   kfree(__cil_tmp34);
 #line 1337
   list->map = (struct drm_local_map *)0;
   }
 #line 1339
   return (ret);
 }
 }
 #line 1357 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj ) 
 { unsigned char *__cil_tmp2 ;
   unsigned char *__cil_tmp3 ;
   unsigned char __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   struct address_space *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct drm_device *__cil_tmp8 ;
   struct address_space *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct drm_device *__cil_tmp11 ;
   struct address_space *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   long long __cil_tmp14 ;
   long long __cil_tmp15 ;
   loff_t __cil_tmp16 ;
   loff_t __cil_tmp17 ;
   size_t __cil_tmp18 ;
   loff_t __cil_tmp19 ;
   loff_t __cil_tmp20 ;
 
   {
   {
 #line 1359
   __cil_tmp2 = (unsigned char *)obj;
 #line 1359
   __cil_tmp3 = __cil_tmp2 + 226UL;
 #line 1359
   __cil_tmp4 = *__cil_tmp3;
 #line 1359
   __cil_tmp5 = (unsigned int )__cil_tmp4;
 #line 1359
   if (__cil_tmp5 == 0U) {
 #line 1360
     return;
   } else {
 
   }
   }
   {
 #line 1362
   __cil_tmp6 = (struct address_space *)0;
 #line 1362
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 1362
   __cil_tmp8 = obj->base.dev;
 #line 1362
   __cil_tmp9 = __cil_tmp8->dev_mapping;
 #line 1362
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 1362
   if (__cil_tmp10 != __cil_tmp7) {
     {
 #line 1363
     __cil_tmp11 = obj->base.dev;
 #line 1363
     __cil_tmp12 = __cil_tmp11->dev_mapping;
 #line 1363
     __cil_tmp13 = obj->base.map_list.hash.key;
 #line 1363
     __cil_tmp14 = (long long )__cil_tmp13;
 #line 1363
     __cil_tmp15 = __cil_tmp14 << 12;
 #line 1363
     __cil_tmp16 = (loff_t const   )__cil_tmp15;
 #line 1363
     __cil_tmp17 = (loff_t )__cil_tmp16;
 #line 1363
     __cil_tmp18 = obj->base.size;
 #line 1363
     __cil_tmp19 = (loff_t const   )__cil_tmp18;
 #line 1363
     __cil_tmp20 = (loff_t )__cil_tmp19;
 #line 1363
     unmap_mapping_range(__cil_tmp12, __cil_tmp17, __cil_tmp20, 1);
     }
   } else {
 
   }
   }
 #line 1367
   obj->fault_mappable = (unsigned char)0;
 #line 1368
   return;
 }
 }
 #line 1371 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   struct drm_gem_mm *mm ;
   struct drm_map_list *list ;
   void *__cil_tmp5 ;
   struct drm_open_hash *__cil_tmp6 ;
   struct drm_hash_item *__cil_tmp7 ;
   struct drm_mm_node *__cil_tmp8 ;
   struct drm_local_map *__cil_tmp9 ;
   void const   *__cil_tmp10 ;
 
   {
   {
 #line 1373
   dev = obj->base.dev;
 #line 1374
   __cil_tmp5 = dev->mm_private;
 #line 1374
   mm = (struct drm_gem_mm *)__cil_tmp5;
 #line 1375
   list = & obj->base.map_list;
 #line 1377
   __cil_tmp6 = & mm->offset_hash;
 #line 1377
   __cil_tmp7 = & list->hash;
 #line 1377
   drm_ht_remove_item(__cil_tmp6, __cil_tmp7);
 #line 1378
   __cil_tmp8 = list->file_offset_node;
 #line 1378
   drm_mm_put_block(__cil_tmp8);
 #line 1379
   __cil_tmp9 = list->map;
 #line 1379
   __cil_tmp10 = (void const   *)__cil_tmp9;
 #line 1379
   kfree(__cil_tmp10);
 #line 1380
   list->map = (struct drm_local_map *)0;
   }
 #line 1381
   return;
 }
 }
 #line 1384 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev , uint32_t size , int tiling_mode ) 
 { uint32_t gtt_size ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
 
   {
   {
 #line 1388
   __cil_tmp5 = dev->dev_private;
 #line 1388
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 1388
   __cil_tmp7 = __cil_tmp6->info;
 #line 1388
   __cil_tmp8 = __cil_tmp7->gen;
 #line 1388
   __cil_tmp9 = (unsigned char )__cil_tmp8;
 #line 1388
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 1388
   if (__cil_tmp10 > 3U) {
 #line 1390
     return (size);
   } else
 #line 1388
   if (tiling_mode == 0) {
 #line 1390
     return (size);
   } else {
 
   }
   }
   {
 #line 1393
   __cil_tmp11 = dev->dev_private;
 #line 1393
   __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 1393
   __cil_tmp13 = __cil_tmp12->info;
 #line 1393
   __cil_tmp14 = __cil_tmp13->gen;
 #line 1393
   __cil_tmp15 = (unsigned char )__cil_tmp14;
 #line 1393
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 1393
   if (__cil_tmp16 == 3U) {
 #line 1394
     gtt_size = 1048576U;
   } else {
 #line 1396
     gtt_size = 524288U;
   }
   }
 #line 1398
   goto ldv_39144;
   ldv_39143: 
 #line 1399
   gtt_size = gtt_size << 1;
   ldv_39144: ;
 #line 1398
   if (gtt_size < size) {
 #line 1399
     goto ldv_39143;
   } else {
 #line 1401
     goto ldv_39145;
   }
   ldv_39145: ;
 #line 1401
   return (gtt_size);
 }
 }
 #line 1412 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev , uint32_t size ,
                                            int tiling_mode ) 
 { uint32_t tmp ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
 
   {
   {
 #line 1420
   __cil_tmp5 = dev->dev_private;
 #line 1420
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 1420
   __cil_tmp7 = __cil_tmp6->info;
 #line 1420
   __cil_tmp8 = __cil_tmp7->gen;
 #line 1420
   __cil_tmp9 = (unsigned char )__cil_tmp8;
 #line 1420
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 1420
   if (__cil_tmp10 > 3U) {
 #line 1422
     return (4096U);
   } else
 #line 1420
   if (tiling_mode == 0) {
 #line 1422
     return (4096U);
   } else {
 
   }
   }
   {
 #line 1428
   tmp = i915_gem_get_gtt_size(dev, size, tiling_mode);
   }
 #line 1428
   return (tmp);
 }
 }
 #line 1442 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev , uint32_t size ,
                                              int tiling_mode ) 
 { uint32_t tmp ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
 
   {
   {
 #line 1449
   __cil_tmp5 = dev->dev_private;
 #line 1449
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 1449
   __cil_tmp7 = __cil_tmp6->info;
 #line 1449
   __cil_tmp8 = __cil_tmp7->gen;
 #line 1449
   __cil_tmp9 = (unsigned char )__cil_tmp8;
 #line 1449
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 1449
   if (__cil_tmp10 > 3U) {
 #line 1451
     return (4096U);
   } else {
     {
 #line 1449
     __cil_tmp11 = dev->dev_private;
 #line 1449
     __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 1449
     __cil_tmp13 = __cil_tmp12->info;
 #line 1449
     __cil_tmp14 = (unsigned char *)__cil_tmp13;
 #line 1449
     __cil_tmp15 = __cil_tmp14 + 1UL;
 #line 1449
     __cil_tmp16 = *__cil_tmp15;
 #line 1449
     __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 1449
     if (__cil_tmp17 != 0U) {
 #line 1451
       return (4096U);
     } else
 #line 1449
     if (tiling_mode == 0) {
 #line 1451
       return (4096U);
     } else {
 
     }
     }
   }
   }
   {
 #line 1457
   tmp = i915_gem_get_gtt_size(dev, size, tiling_mode);
   }
 #line 1457
   return (tmp);
 }
 }
 #line 1461 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_mmap_gtt(struct drm_file *file , struct drm_device *dev , uint32_t handle ,
                       uint64_t *offset ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   void *__cil_tmp10 ;
   struct drm_driver *__cil_tmp11 ;
   u32 __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   struct drm_gem_object *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct drm_gem_object *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   size_t __cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   struct drm_local_map *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_local_map *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long long __cil_tmp29 ;
   struct drm_gem_object *__cil_tmp30 ;
   struct mutex *__cil_tmp31 ;
 
   {
 #line 1466
   __cil_tmp10 = dev->dev_private;
 #line 1466
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
   {
 #line 1470
   __cil_tmp11 = dev->driver;
 #line 1470
   __cil_tmp12 = __cil_tmp11->driver_features;
 #line 1470
   __cil_tmp13 = __cil_tmp12 & 4096U;
 #line 1470
   if (__cil_tmp13 == 0U) {
 #line 1471
     return (-19);
   } else {
 
   }
   }
   {
 #line 1473
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 1474
   if (ret != 0) {
 #line 1475
     return (ret);
   } else {
 
   }
   {
 #line 1477
   tmp = drm_gem_object_lookup(dev, file, handle);
 #line 1477
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 1477
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 1478
   __cil_tmp14 = (struct drm_gem_object *)0;
 #line 1478
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 1478
   __cil_tmp16 = & obj->base;
 #line 1478
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 1478
   if (__cil_tmp17 == __cil_tmp15) {
 #line 1479
     ret = -2;
 #line 1480
     goto unlock;
   } else {
 
   }
   }
   {
 #line 1483
   __cil_tmp18 = dev_priv->mm.gtt_mappable_end;
 #line 1483
   __cil_tmp19 = obj->base.size;
 #line 1483
   if (__cil_tmp19 > __cil_tmp18) {
 #line 1484
     ret = -7;
 #line 1485
     goto unlock;
   } else {
 
   }
   }
   {
 #line 1488
   __cil_tmp20 = (unsigned char *)obj;
 #line 1488
   __cil_tmp21 = __cil_tmp20 + 225UL;
 #line 1488
   __cil_tmp22 = *__cil_tmp21;
 #line 1488
   __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 1488
   if (__cil_tmp23 != 0U) {
     {
 #line 1489
     drm_err("i915_gem_mmap_gtt", "Attempting to mmap a purgeable buffer\n");
 #line 1490
     ret = -22;
     }
 #line 1491
     goto out;
   } else {
 
   }
   }
   {
 #line 1494
   __cil_tmp24 = (struct drm_local_map *)0;
 #line 1494
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 1494
   __cil_tmp26 = obj->base.map_list.map;
 #line 1494
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 1494
   if (__cil_tmp27 == __cil_tmp25) {
     {
 #line 1495
     ret = i915_gem_create_mmap_offset(obj);
     }
 #line 1496
     if (ret != 0) {
 #line 1497
       goto out;
     } else {
 
     }
   } else {
 
   }
   }
 #line 1500
   __cil_tmp28 = obj->base.map_list.hash.key;
 #line 1500
   __cil_tmp29 = (unsigned long long )__cil_tmp28;
 #line 1500
   *offset = __cil_tmp29 << 12;
   out: 
   {
 #line 1503
   __cil_tmp30 = & obj->base;
 #line 1503
   drm_gem_object_unreference(__cil_tmp30);
   }
   unlock: 
   {
 #line 1505
   __cil_tmp31 = & dev->struct_mutex;
 #line 1505
   mutex_unlock(__cil_tmp31);
   }
 #line 1506
   return (ret);
 }
 }
 #line 1525 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_mmap_gtt *args ;
   int tmp ;
   struct drm_driver *__cil_tmp6 ;
   u32 __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   __u32 __cil_tmp9 ;
   __u64 *__cil_tmp10 ;
 
   {
 #line 1528
   args = (struct drm_i915_gem_mmap_gtt *)data;
   {
 #line 1530
   __cil_tmp6 = dev->driver;
 #line 1530
   __cil_tmp7 = __cil_tmp6->driver_features;
 #line 1530
   __cil_tmp8 = __cil_tmp7 & 4096U;
 #line 1530
   if (__cil_tmp8 == 0U) {
 #line 1531
     return (-19);
   } else {
 
   }
   }
   {
 #line 1533
   __cil_tmp9 = args->handle;
 #line 1533
   __cil_tmp10 = & args->offset;
 #line 1533
   tmp = i915_gem_mmap_gtt(file, dev, __cil_tmp9, __cil_tmp10);
   }
 #line 1533
   return (tmp);
 }
 }
 #line 1538 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj , gfp_t gfpmask ) 
 { int page_count___0 ;
   int i ;
   struct address_space *mapping ;
   struct inode *inode ;
   struct page *page ;
   long tmp ;
   void *tmp___0 ;
   gfp_t tmp___1 ;
   long tmp___2 ;
   int tmp___3 ;
   long tmp___4 ;
   size_t __cil_tmp14 ;
   size_t __cil_tmp15 ;
   struct page **__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct page **__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   int __cil_tmp20 ;
   long __cil_tmp21 ;
   size_t __cil_tmp22 ;
   struct page **__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct page **__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   struct file *__cil_tmp27 ;
   struct dentry *__cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   void const   *__cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   struct page **__cil_tmp32 ;
   struct page **__cil_tmp33 ;
   unsigned char *__cil_tmp34 ;
   unsigned char *__cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   struct page **__cil_tmp39 ;
   struct page **__cil_tmp40 ;
   struct page *__cil_tmp41 ;
   struct page **__cil_tmp42 ;
   void *__cil_tmp43 ;
   void const   *__cil_tmp44 ;
 
   {
   {
 #line 1549
   __cil_tmp14 = obj->base.size;
 #line 1549
   __cil_tmp15 = __cil_tmp14 / 4096UL;
 #line 1549
   page_count___0 = (int )__cil_tmp15;
 #line 1550
   __cil_tmp16 = (struct page **)0;
 #line 1550
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 1550
   __cil_tmp18 = obj->pages;
 #line 1550
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 1550
   __cil_tmp20 = __cil_tmp19 != __cil_tmp17;
 #line 1550
   __cil_tmp21 = (long )__cil_tmp20;
 #line 1550
   tmp = __builtin_expect(__cil_tmp21, 0L);
   }
 #line 1550
   if (tmp != 0L) {
 #line 1550
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1550), "i" (12UL));
     ldv_39185: ;
 #line 1550
     goto ldv_39185;
   } else {
 
   }
   {
 #line 1551
   __cil_tmp22 = (size_t )page_count___0;
 #line 1551
   tmp___0 = drm_malloc_ab(__cil_tmp22, 8UL);
 #line 1551
   obj->pages = (struct page **)tmp___0;
   }
   {
 #line 1552
   __cil_tmp23 = (struct page **)0;
 #line 1552
   __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 1552
   __cil_tmp25 = obj->pages;
 #line 1552
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 1552
   if (__cil_tmp26 == __cil_tmp24) {
 #line 1553
     return (-12);
   } else {
 
   }
   }
   {
 #line 1555
   __cil_tmp27 = obj->base.filp;
 #line 1555
   __cil_tmp28 = __cil_tmp27->f_path.dentry;
 #line 1555
   inode = __cil_tmp28->d_inode;
 #line 1556
   mapping = inode->i_mapping;
 #line 1557
   tmp___1 = mapping_gfp_mask(mapping);
 #line 1557
   gfpmask = tmp___1 | gfpmask;
 #line 1559
   i = 0;
   }
 #line 1559
   goto ldv_39188;
   ldv_39187: 
   {
 #line 1560
   __cil_tmp29 = (unsigned long )i;
 #line 1560
   page = shmem_read_mapping_page_gfp(mapping, __cil_tmp29, gfpmask);
 #line 1561
   __cil_tmp30 = (void const   *)page;
 #line 1561
   tmp___2 = IS_ERR(__cil_tmp30);
   }
 #line 1561
   if (tmp___2 != 0L) {
 #line 1562
     goto err_pages;
   } else {
 
   }
 #line 1564
   __cil_tmp31 = (unsigned long )i;
 #line 1564
   __cil_tmp32 = obj->pages;
 #line 1564
   __cil_tmp33 = __cil_tmp32 + __cil_tmp31;
 #line 1564
   *__cil_tmp33 = page;
 #line 1559
   i = i + 1;
   ldv_39188: ;
 #line 1559
   if (i < page_count___0) {
 #line 1560
     goto ldv_39187;
   } else {
 #line 1562
     goto ldv_39189;
   }
   ldv_39189: ;
   {
 #line 1567
   __cil_tmp34 = (unsigned char *)obj;
 #line 1567
   __cil_tmp35 = __cil_tmp34 + 225UL;
 #line 1567
   __cil_tmp36 = *__cil_tmp35;
 #line 1567
   __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 1567
   if (__cil_tmp37 != 0U) {
     {
 #line 1568
     i915_gem_object_do_bit_17_swizzle(obj);
     }
   } else {
 
   }
   }
 #line 1570
   return (0);
   err_pages: ;
 #line 1573
   goto ldv_39191;
   ldv_39190: 
   {
 #line 1574
   __cil_tmp38 = (unsigned long )i;
 #line 1574
   __cil_tmp39 = obj->pages;
 #line 1574
   __cil_tmp40 = __cil_tmp39 + __cil_tmp38;
 #line 1574
   __cil_tmp41 = *__cil_tmp40;
 #line 1574
   put_page(__cil_tmp41);
   }
   ldv_39191: 
 #line 1573
   tmp___3 = i;
 #line 1573
   i = i - 1;
 #line 1573
   if (tmp___3 != 0) {
 #line 1574
     goto ldv_39190;
   } else {
 #line 1576
     goto ldv_39192;
   }
   ldv_39192: 
   {
 #line 1576
   __cil_tmp42 = obj->pages;
 #line 1576
   __cil_tmp43 = (void *)__cil_tmp42;
 #line 1576
   drm_free_large(__cil_tmp43);
 #line 1577
   obj->pages = (struct page **)0;
 #line 1578
   __cil_tmp44 = (void const   *)page;
 #line 1578
   tmp___4 = PTR_ERR(__cil_tmp44);
   }
 #line 1578
   return ((int )tmp___4);
 }
 }
 #line 1582 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj ) 
 { int page_count___0 ;
   int i ;
   long tmp ;
   size_t __cil_tmp5 ;
   size_t __cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   int __cil_tmp11 ;
   long __cil_tmp12 ;
   unsigned char *__cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct page **__cil_tmp26 ;
   struct page **__cil_tmp27 ;
   struct page *__cil_tmp28 ;
   unsigned char *__cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   struct page **__cil_tmp34 ;
   struct page **__cil_tmp35 ;
   struct page *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct page **__cil_tmp38 ;
   struct page **__cil_tmp39 ;
   struct page *__cil_tmp40 ;
   struct page **__cil_tmp41 ;
   void *__cil_tmp42 ;
 
   {
   {
 #line 1584
   __cil_tmp5 = obj->base.size;
 #line 1584
   __cil_tmp6 = __cil_tmp5 / 4096UL;
 #line 1584
   page_count___0 = (int )__cil_tmp6;
 #line 1587
   __cil_tmp7 = (unsigned char *)obj;
 #line 1587
   __cil_tmp8 = __cil_tmp7 + 225UL;
 #line 1587
   __cil_tmp9 = *__cil_tmp8;
 #line 1587
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 1587
   __cil_tmp11 = __cil_tmp10 == 2U;
 #line 1587
   __cil_tmp12 = (long )__cil_tmp11;
 #line 1587
   tmp = __builtin_expect(__cil_tmp12, 0L);
   }
 #line 1587
   if (tmp != 0L) {
 #line 1587
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1587), "i" (12UL));
     ldv_39198: ;
 #line 1587
     goto ldv_39198;
   } else {
 
   }
   {
 #line 1589
   __cil_tmp13 = (unsigned char *)obj;
 #line 1589
   __cil_tmp14 = __cil_tmp13 + 225UL;
 #line 1589
   __cil_tmp15 = *__cil_tmp14;
 #line 1589
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 1589
   if (__cil_tmp16 != 0U) {
     {
 #line 1590
     i915_gem_object_save_bit_17_swizzle(obj);
     }
   } else {
 
   }
   }
   {
 #line 1592
   __cil_tmp17 = (unsigned char *)obj;
 #line 1592
   __cil_tmp18 = __cil_tmp17 + 225UL;
 #line 1592
   __cil_tmp19 = *__cil_tmp18;
 #line 1592
   __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 1592
   if (__cil_tmp20 == 1U) {
 #line 1593
     obj->dirty = (unsigned char)0;
   } else {
 
   }
   }
 #line 1595
   i = 0;
 #line 1595
   goto ldv_39200;
   ldv_39199: ;
   {
 #line 1596
   __cil_tmp21 = (unsigned char *)obj;
 #line 1596
   __cil_tmp22 = __cil_tmp21 + 224UL;
 #line 1596
   __cil_tmp23 = *__cil_tmp22;
 #line 1596
   __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 1596
   if (__cil_tmp24 != 0U) {
     {
 #line 1597
     __cil_tmp25 = (unsigned long )i;
 #line 1597
     __cil_tmp26 = obj->pages;
 #line 1597
     __cil_tmp27 = __cil_tmp26 + __cil_tmp25;
 #line 1597
     __cil_tmp28 = *__cil_tmp27;
 #line 1597
     set_page_dirty(__cil_tmp28);
     }
   } else {
 
   }
   }
   {
 #line 1599
   __cil_tmp29 = (unsigned char *)obj;
 #line 1599
   __cil_tmp30 = __cil_tmp29 + 225UL;
 #line 1599
   __cil_tmp31 = *__cil_tmp30;
 #line 1599
   __cil_tmp32 = (unsigned int )__cil_tmp31;
 #line 1599
   if (__cil_tmp32 == 0U) {
     {
 #line 1600
     __cil_tmp33 = (unsigned long )i;
 #line 1600
     __cil_tmp34 = obj->pages;
 #line 1600
     __cil_tmp35 = __cil_tmp34 + __cil_tmp33;
 #line 1600
     __cil_tmp36 = *__cil_tmp35;
 #line 1600
     mark_page_accessed(__cil_tmp36);
     }
   } else {
 
   }
   }
   {
 #line 1602
   __cil_tmp37 = (unsigned long )i;
 #line 1602
   __cil_tmp38 = obj->pages;
 #line 1602
   __cil_tmp39 = __cil_tmp38 + __cil_tmp37;
 #line 1602
   __cil_tmp40 = *__cil_tmp39;
 #line 1602
   put_page(__cil_tmp40);
 #line 1595
   i = i + 1;
   }
   ldv_39200: ;
 #line 1595
   if (i < page_count___0) {
 #line 1596
     goto ldv_39199;
   } else {
 #line 1598
     goto ldv_39201;
   }
   ldv_39201: 
   {
 #line 1604
   obj->dirty = (unsigned char)0;
 #line 1606
   __cil_tmp41 = obj->pages;
 #line 1606
   __cil_tmp42 = (void *)__cil_tmp41;
 #line 1606
   drm_free_large(__cil_tmp42);
 #line 1607
   obj->pages = (struct page **)0;
   }
 #line 1608
   return;
 }
 }
 #line 1611 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj , struct intel_ring_buffer *ring ,
                                     u32 seqno ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   long tmp ;
   struct drm_i915_fence_reg *reg ;
   long tmp___0 ;
   void *__cil_tmp9 ;
   struct intel_ring_buffer *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   int __cil_tmp13 ;
   long __cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   struct drm_gem_object *__cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct list_head *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char *__cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char *__cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   int __cil_tmp32 ;
   long __cil_tmp33 ;
   signed char __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   struct drm_i915_fence_reg (*__cil_tmp36)[16U] ;
   struct drm_i915_fence_reg *__cil_tmp37 ;
   struct list_head *__cil_tmp38 ;
   struct list_head *__cil_tmp39 ;
 
   {
   {
 #line 1615
   dev = obj->base.dev;
 #line 1616
   __cil_tmp9 = dev->dev_private;
 #line 1616
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 1618
   __cil_tmp10 = (struct intel_ring_buffer *)0;
 #line 1618
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 1618
   __cil_tmp12 = (unsigned long )ring;
 #line 1618
   __cil_tmp13 = __cil_tmp12 == __cil_tmp11;
 #line 1618
   __cil_tmp14 = (long )__cil_tmp13;
 #line 1618
   tmp = __builtin_expect(__cil_tmp14, 0L);
   }
 #line 1618
   if (tmp != 0L) {
 #line 1618
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1618), "i" (12UL));
     ldv_39209: ;
 #line 1618
     goto ldv_39209;
   } else {
 
   }
 #line 1619
   obj->ring = ring;
   {
 #line 1622
   __cil_tmp15 = (unsigned char *)obj;
 #line 1622
   __cil_tmp16 = __cil_tmp15 + 224UL;
 #line 1622
   __cil_tmp17 = *__cil_tmp16;
 #line 1622
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 1622
   if (__cil_tmp18 == 0U) {
     {
 #line 1623
     __cil_tmp19 = & obj->base;
 #line 1623
     drm_gem_object_reference(__cil_tmp19);
 #line 1624
     obj->active = (unsigned char)1;
     }
   } else {
 
   }
   }
   {
 #line 1628
   __cil_tmp20 = & obj->mm_list;
 #line 1628
   __cil_tmp21 = & dev_priv->mm.active_list;
 #line 1628
   list_move_tail(__cil_tmp20, __cil_tmp21);
 #line 1629
   __cil_tmp22 = & obj->ring_list;
 #line 1629
   __cil_tmp23 = & ring->active_list;
 #line 1629
   list_move_tail(__cil_tmp22, __cil_tmp23);
 #line 1631
   obj->last_rendering_seqno = seqno;
   }
   {
 #line 1632
   __cil_tmp24 = (unsigned char *)obj;
 #line 1632
   __cil_tmp25 = __cil_tmp24 + 226UL;
 #line 1632
   __cil_tmp26 = *__cil_tmp25;
 #line 1632
   __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1632
   if (__cil_tmp27 != 0U) {
     {
 #line 1635
     __cil_tmp28 = (unsigned char *)obj;
 #line 1635
     __cil_tmp29 = __cil_tmp28 + 224UL;
 #line 1635
     __cil_tmp30 = *__cil_tmp29;
 #line 1635
     __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 1635
     __cil_tmp32 = __cil_tmp31 == 248U;
 #line 1635
     __cil_tmp33 = (long )__cil_tmp32;
 #line 1635
     tmp___0 = __builtin_expect(__cil_tmp33, 0L);
     }
 #line 1635
     if (tmp___0 != 0L) {
 #line 1635
       __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                            "i" (1635), "i" (12UL));
       ldv_39211: ;
 #line 1635
       goto ldv_39211;
     } else {
 
     }
     {
 #line 1637
     obj->last_fenced_seqno = seqno;
 #line 1638
     obj->last_fenced_ring = ring;
 #line 1640
     __cil_tmp34 = obj->fence_reg;
 #line 1640
     __cil_tmp35 = (unsigned long )__cil_tmp34;
 #line 1640
     __cil_tmp36 = & dev_priv->fence_regs;
 #line 1640
     __cil_tmp37 = (struct drm_i915_fence_reg *)__cil_tmp36;
 #line 1640
     reg = __cil_tmp37 + __cil_tmp35;
 #line 1641
     __cil_tmp38 = & reg->lru_list;
 #line 1641
     __cil_tmp39 = & dev_priv->mm.fence_list;
 #line 1641
     list_move_tail(__cil_tmp38, __cil_tmp39);
     }
   } else {
 
   }
   }
 #line 1643
   return;
 }
 }
 #line 1646 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_move_off_active(struct drm_i915_gem_object *obj ) 
 { struct list_head *__cil_tmp2 ;
 
   {
   {
 #line 1648
   __cil_tmp2 = & obj->ring_list;
 #line 1648
   list_del_init(__cil_tmp2);
 #line 1649
   obj->last_rendering_seqno = 0U;
   }
 #line 1650
   return;
 }
 }
 #line 1653 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   long tmp ;
   void *__cil_tmp5 ;
   unsigned char *__cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   long __cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
 
   {
   {
 #line 1655
   dev = obj->base.dev;
 #line 1656
   __cil_tmp5 = dev->dev_private;
 #line 1656
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 1658
   __cil_tmp6 = (unsigned char *)obj;
 #line 1658
   __cil_tmp7 = __cil_tmp6 + 224UL;
 #line 1658
   __cil_tmp8 = *__cil_tmp7;
 #line 1658
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1658
   __cil_tmp10 = __cil_tmp9 == 0U;
 #line 1658
   __cil_tmp11 = (long )__cil_tmp10;
 #line 1658
   tmp = __builtin_expect(__cil_tmp11, 0L);
   }
 #line 1658
   if (tmp != 0L) {
 #line 1658
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1658), "i" (12UL));
     ldv_39220: ;
 #line 1658
     goto ldv_39220;
   } else {
 
   }
   {
 #line 1659
   __cil_tmp12 = & obj->mm_list;
 #line 1659
   __cil_tmp13 = & dev_priv->mm.flushing_list;
 #line 1659
   list_move_tail(__cil_tmp12, __cil_tmp13);
 #line 1661
   i915_gem_object_move_off_active(obj);
   }
 #line 1662
   return;
 }
 }
 #line 1665 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   int tmp ;
   long tmp___0 ;
   long tmp___1 ;
   int __ret_warn_on ;
   long tmp___2 ;
   void *__cil_tmp9 ;
   unsigned int *__cil_tmp10 ;
   unsigned int *__cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct list_head *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct list_head  const  *__cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   int __cil_tmp25 ;
   long __cil_tmp26 ;
   struct drm_gem_object *__cil_tmp27 ;
   int __cil_tmp28 ;
   long __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   long __cil_tmp33 ;
 
   {
 #line 1667
   dev = obj->base.dev;
 #line 1668
   __cil_tmp9 = dev->dev_private;
 #line 1668
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
   {
 #line 1670
   __cil_tmp10 = (unsigned int *)obj;
 #line 1670
   __cil_tmp11 = __cil_tmp10 + 56UL;
 #line 1670
   __cil_tmp12 = *__cil_tmp11;
 #line 1670
   if (__cil_tmp12 != 0U) {
     {
 #line 1671
     __cil_tmp13 = & obj->mm_list;
 #line 1671
     __cil_tmp14 = & dev_priv->mm.pinned_list;
 #line 1671
     list_move_tail(__cil_tmp13, __cil_tmp14);
     }
   } else {
     {
 #line 1673
     __cil_tmp15 = & obj->mm_list;
 #line 1673
     __cil_tmp16 = & dev_priv->mm.inactive_list;
 #line 1673
     list_move_tail(__cil_tmp15, __cil_tmp16);
     }
   }
   }
   {
 #line 1675
   __cil_tmp17 = & obj->gpu_write_list;
 #line 1675
   __cil_tmp18 = (struct list_head  const  *)__cil_tmp17;
 #line 1675
   tmp = list_empty(__cil_tmp18);
 #line 1675
   __cil_tmp19 = tmp == 0;
 #line 1675
   __cil_tmp20 = (long )__cil_tmp19;
 #line 1675
   tmp___0 = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 1675
   if (tmp___0 != 0L) {
 #line 1675
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1675), "i" (12UL));
     ldv_39226: ;
 #line 1675
     goto ldv_39226;
   } else {
 
   }
   {
 #line 1676
   __cil_tmp21 = (unsigned char *)obj;
 #line 1676
   __cil_tmp22 = __cil_tmp21 + 224UL;
 #line 1676
   __cil_tmp23 = *__cil_tmp22;
 #line 1676
   __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 1676
   __cil_tmp25 = __cil_tmp24 == 0U;
 #line 1676
   __cil_tmp26 = (long )__cil_tmp25;
 #line 1676
   tmp___1 = __builtin_expect(__cil_tmp26, 0L);
   }
 #line 1676
   if (tmp___1 != 0L) {
 #line 1676
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1676), "i" (12UL));
     ldv_39227: ;
 #line 1676
     goto ldv_39227;
   } else {
 
   }
   {
 #line 1677
   obj->ring = (struct intel_ring_buffer *)0;
 #line 1679
   i915_gem_object_move_off_active(obj);
 #line 1680
   obj->fenced_gpu_access = (unsigned char)0;
 #line 1682
   obj->active = (unsigned char)0;
 #line 1683
   obj->pending_gpu_write = (unsigned char)0;
 #line 1684
   __cil_tmp27 = & obj->base;
 #line 1684
   drm_gem_object_unreference(__cil_tmp27);
 #line 1686
   __ret_warn_on = 0;
 #line 1686
   __cil_tmp28 = __ret_warn_on != 0;
 #line 1686
   __cil_tmp29 = (long )__cil_tmp28;
 #line 1686
   tmp___2 = __builtin_expect(__cil_tmp29, 0L);
   }
 #line 1686
   if (tmp___2 != 0L) {
     {
 #line 1686
     __cil_tmp30 = (int const   )1686;
 #line 1686
     __cil_tmp31 = (int )__cil_tmp30;
 #line 1686
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp31);
     }
   } else {
 
   }
   {
 #line 1686
   __cil_tmp32 = __ret_warn_on != 0;
 #line 1686
   __cil_tmp33 = (long )__cil_tmp32;
 #line 1686
   __builtin_expect(__cil_tmp33, 0L);
   }
 #line 1688
   return;
 }
 }
 #line 1691 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj ) 
 { struct inode *inode ;
   struct file *__cil_tmp3 ;
   struct dentry *__cil_tmp4 ;
 
   {
   {
 #line 1700
   __cil_tmp3 = obj->base.filp;
 #line 1700
   __cil_tmp4 = __cil_tmp3->f_path.dentry;
 #line 1700
   inode = __cil_tmp4->d_inode;
 #line 1701
   shmem_truncate_range(inode, 0LL, -1LL);
 #line 1703
   obj->madv = (unsigned char)2;
   }
 #line 1704
   return;
 }
 }
 #line 1707 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj ) 
 { unsigned char *__cil_tmp2 ;
   unsigned char *__cil_tmp3 ;
   unsigned char __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
 
   {
   {
 #line 1709
   __cil_tmp2 = (unsigned char *)obj;
 #line 1709
   __cil_tmp3 = __cil_tmp2 + 225UL;
 #line 1709
   __cil_tmp4 = *__cil_tmp3;
 #line 1709
   __cil_tmp5 = (unsigned int )__cil_tmp4;
 #line 1709
   return (__cil_tmp5 == 1U);
   }
 }
 }
 #line 1713 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring , uint32_t flush_domains ) 
 { struct drm_i915_gem_object *obj ;
   struct drm_i915_gem_object *next ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   uint32_t old_write_domain ;
   u32 tmp ;
   struct list_head  const  *__mptr___1 ;
   struct list_head *__cil_tmp10 ;
   struct drm_i915_gem_object *__cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct drm_i915_gem_object *__cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   uint32_t __cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   struct drm_i915_gem_object *__cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
 
   {
 #line 1718
   __cil_tmp10 = ring->gpu_write_list.next;
 #line 1718
   __mptr = (struct list_head  const  *)__cil_tmp10;
 #line 1718
   __cil_tmp11 = (struct drm_i915_gem_object *)__mptr;
 #line 1718
   obj = __cil_tmp11 + 1152921504606846784UL;
 #line 1718
   __cil_tmp12 = obj->gpu_write_list.next;
 #line 1718
   __mptr___0 = (struct list_head  const  *)__cil_tmp12;
 #line 1718
   __cil_tmp13 = (struct drm_i915_gem_object *)__mptr___0;
 #line 1718
   next = __cil_tmp13 + 1152921504606846784UL;
 #line 1718
   goto ldv_39251;
   ldv_39250: ;
   {
 #line 1721
   __cil_tmp14 = obj->base.write_domain;
 #line 1721
   __cil_tmp15 = __cil_tmp14 & flush_domains;
 #line 1721
   if (__cil_tmp15 != 0U) {
     {
 #line 1722
     old_write_domain = obj->base.write_domain;
 #line 1724
     obj->base.write_domain = 0U;
 #line 1725
     __cil_tmp16 = & obj->gpu_write_list;
 #line 1725
     list_del_init(__cil_tmp16);
 #line 1726
     tmp = i915_gem_next_request_seqno(ring);
 #line 1726
     i915_gem_object_move_to_active(obj, ring, tmp);
 #line 1729
     __cil_tmp17 = obj->base.read_domains;
 #line 1729
     trace_i915_gem_object_change_domain(obj, __cil_tmp17, old_write_domain);
     }
   } else {
 
   }
   }
 #line 1718
   obj = next;
 #line 1718
   __cil_tmp18 = next->gpu_write_list.next;
 #line 1718
   __mptr___1 = (struct list_head  const  *)__cil_tmp18;
 #line 1718
   __cil_tmp19 = (struct drm_i915_gem_object *)__mptr___1;
 #line 1718
   next = __cil_tmp19 + 1152921504606846784UL;
   ldv_39251: ;
   {
 #line 1718
   __cil_tmp20 = & ring->gpu_write_list;
 #line 1718
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 1718
   __cil_tmp22 = & obj->gpu_write_list;
 #line 1718
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 1718
   if (__cil_tmp23 != __cil_tmp21) {
 #line 1719
     goto ldv_39250;
   } else {
 #line 1721
     goto ldv_39252;
   }
   }
   ldv_39252: ;
 #line 1723
   return;
 }
 }
 #line 1737 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_add_request(struct intel_ring_buffer *ring , struct drm_file *file , struct drm_i915_gem_request *request ) 
 { drm_i915_private_t *dev_priv ;
   uint32_t seqno ;
   int was_empty ;
   int ret ;
   long tmp ;
   struct drm_i915_file_private *file_priv ;
   unsigned long tmp___0 ;
   struct drm_device *__cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_gem_request *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   int __cil_tmp16 ;
   long __cil_tmp17 ;
   int (*__cil_tmp18)(struct intel_ring_buffer * , u32 * ) ;
   struct list_head *__cil_tmp19 ;
   struct list_head  const  *__cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct drm_file *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct spinlock *__cil_tmp27 ;
   struct list_head *__cil_tmp28 ;
   struct list_head *__cil_tmp29 ;
   struct spinlock *__cil_tmp30 ;
   int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   struct timer_list *__cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   struct workqueue_struct *__cil_tmp37 ;
   struct delayed_work *__cil_tmp38 ;
 
   {
   {
 #line 1741
   __cil_tmp11 = ring->dev;
 #line 1741
   __cil_tmp12 = __cil_tmp11->dev_private;
 #line 1741
   dev_priv = (drm_i915_private_t *)__cil_tmp12;
 #line 1746
   __cil_tmp13 = (struct drm_i915_gem_request *)0;
 #line 1746
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 1746
   __cil_tmp15 = (unsigned long )request;
 #line 1746
   __cil_tmp16 = __cil_tmp15 == __cil_tmp14;
 #line 1746
   __cil_tmp17 = (long )__cil_tmp16;
 #line 1746
   tmp = __builtin_expect(__cil_tmp17, 0L);
   }
 #line 1746
   if (tmp != 0L) {
 #line 1746
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (1746), "i" (12UL));
     ldv_39262: ;
 #line 1746
     goto ldv_39262;
   } else {
 
   }
   {
 #line 1748
   __cil_tmp18 = ring->add_request;
 #line 1748
   ret = (*__cil_tmp18)(ring, & seqno);
   }
 #line 1749
   if (ret != 0) {
 #line 1750
     return (ret);
   } else {
 
   }
   {
 #line 1752
   trace_i915_gem_request_add(ring, seqno);
 #line 1754
   request->seqno = seqno;
 #line 1755
   request->ring = ring;
 #line 1756
   request->emitted_jiffies = (unsigned long )jiffies;
 #line 1757
   __cil_tmp19 = & ring->request_list;
 #line 1757
   __cil_tmp20 = (struct list_head  const  *)__cil_tmp19;
 #line 1757
   was_empty = list_empty(__cil_tmp20);
 #line 1758
   __cil_tmp21 = & request->list;
 #line 1758
   __cil_tmp22 = & ring->request_list;
 #line 1758
   list_add_tail(__cil_tmp21, __cil_tmp22);
   }
   {
 #line 1760
   __cil_tmp23 = (struct drm_file *)0;
 #line 1760
   __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 1760
   __cil_tmp25 = (unsigned long )file;
 #line 1760
   if (__cil_tmp25 != __cil_tmp24) {
     {
 #line 1761
     __cil_tmp26 = file->driver_priv;
 #line 1761
     file_priv = (struct drm_i915_file_private *)__cil_tmp26;
 #line 1763
     __cil_tmp27 = & file_priv->mm.lock;
 #line 1763
     spin_lock(__cil_tmp27);
 #line 1764
     request->file_priv = file_priv;
 #line 1765
     __cil_tmp28 = & request->client_list;
 #line 1765
     __cil_tmp29 = & file_priv->mm.request_list;
 #line 1765
     list_add_tail(__cil_tmp28, __cil_tmp29);
 #line 1767
     __cil_tmp30 = & file_priv->mm.lock;
 #line 1767
     spin_unlock(__cil_tmp30);
     }
   } else {
 
   }
   }
 #line 1770
   ring->outstanding_lazy_request = 0U;
   {
 #line 1772
   __cil_tmp31 = dev_priv->mm.suspended;
 #line 1772
   if (__cil_tmp31 == 0) {
     {
 #line 1773
     __cil_tmp32 = (unsigned int const   )1500U;
 #line 1773
     __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 1773
     tmp___0 = msecs_to_jiffies(__cil_tmp33);
 #line 1773
     __cil_tmp34 = & dev_priv->hangcheck_timer;
 #line 1773
     __cil_tmp35 = (unsigned long )jiffies;
 #line 1773
     __cil_tmp36 = tmp___0 + __cil_tmp35;
 #line 1773
     mod_timer(__cil_tmp34, __cil_tmp36);
     }
 #line 1775
     if (was_empty != 0) {
       {
 #line 1776
       __cil_tmp37 = dev_priv->wq;
 #line 1776
       __cil_tmp38 = & dev_priv->mm.retire_work;
 #line 1776
       queue_delayed_work(__cil_tmp37, __cil_tmp38, 250UL);
       }
     } else {
 
     }
   } else {
 
   }
   }
 #line 1779
   return (0);
 }
 }
 #line 1783 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 __inline static void i915_gem_request_remove_from_client(struct drm_i915_gem_request *request ) 
 { struct drm_i915_file_private *file_priv ;
   struct drm_i915_file_private *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   struct spinlock *__cil_tmp6 ;
   struct drm_i915_file_private *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_i915_file_private *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct list_head *__cil_tmp11 ;
   struct spinlock *__cil_tmp12 ;
 
   {
 #line 1785
   file_priv = request->file_priv;
   {
 #line 1787
   __cil_tmp3 = (struct drm_i915_file_private *)0;
 #line 1787
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 1787
   __cil_tmp5 = (unsigned long )file_priv;
 #line 1787
   if (__cil_tmp5 == __cil_tmp4) {
 #line 1788
     return;
   } else {
 
   }
   }
   {
 #line 1790
   __cil_tmp6 = & file_priv->mm.lock;
 #line 1790
   spin_lock(__cil_tmp6);
   }
   {
 #line 1791
   __cil_tmp7 = (struct drm_i915_file_private *)0;
 #line 1791
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 1791
   __cil_tmp9 = request->file_priv;
 #line 1791
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 1791
   if (__cil_tmp10 != __cil_tmp8) {
     {
 #line 1792
     __cil_tmp11 = & request->client_list;
 #line 1792
     list_del(__cil_tmp11);
 #line 1793
     request->file_priv = (struct drm_i915_file_private *)0;
     }
   } else {
 
   }
   }
   {
 #line 1795
   __cil_tmp12 = & file_priv->mm.lock;
 #line 1795
   spin_unlock(__cil_tmp12);
   }
 #line 1796
   return;
 }
 }
 #line 1798 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv , struct intel_ring_buffer *ring ) 
 { struct drm_i915_gem_request *request ;
   struct list_head  const  *__mptr ;
   int tmp ;
   struct drm_i915_gem_object *obj ;
   struct list_head  const  *__mptr___0 ;
   int tmp___0 ;
   struct list_head *__cil_tmp9 ;
   struct drm_i915_gem_request *__cil_tmp10 ;
   struct list_head *__cil_tmp11 ;
   void const   *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct list_head  const  *__cil_tmp14 ;
   struct list_head *__cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   struct list_head  const  *__cil_tmp19 ;
 
   {
 #line 1801
   goto ldv_39276;
   ldv_39275: 
   {
 #line 1804
   __cil_tmp9 = ring->request_list.next;
 #line 1804
   __mptr = (struct list_head  const  *)__cil_tmp9;
 #line 1804
   __cil_tmp10 = (struct drm_i915_gem_request *)__mptr;
 #line 1804
   request = __cil_tmp10 + 1152921504606846952UL;
 #line 1808
   __cil_tmp11 = & request->list;
 #line 1808
   list_del(__cil_tmp11);
 #line 1809
   i915_gem_request_remove_from_client(request);
 #line 1810
   __cil_tmp12 = (void const   *)request;
 #line 1810
   kfree(__cil_tmp12);
   }
   ldv_39276: 
   {
 #line 1801
   __cil_tmp13 = & ring->request_list;
 #line 1801
   __cil_tmp14 = (struct list_head  const  *)__cil_tmp13;
 #line 1801
   tmp = list_empty(__cil_tmp14);
   }
 #line 1801
   if (tmp == 0) {
 #line 1802
     goto ldv_39275;
   } else {
 #line 1804
     goto ldv_39277;
   }
   ldv_39277: ;
 #line 1813
   goto ldv_39282;
   ldv_39281: 
   {
 #line 1816
   __cil_tmp15 = ring->active_list.next;
 #line 1816
   __mptr___0 = (struct list_head  const  *)__cil_tmp15;
 #line 1816
   __cil_tmp16 = (struct drm_i915_gem_object *)__mptr___0;
 #line 1816
   obj = __cil_tmp16 + 1152921504606846816UL;
 #line 1820
   obj->base.write_domain = 0U;
 #line 1821
   __cil_tmp17 = & obj->gpu_write_list;
 #line 1821
   list_del_init(__cil_tmp17);
 #line 1822
   i915_gem_object_move_to_inactive(obj);
   }
   ldv_39282: 
   {
 #line 1813
   __cil_tmp18 = & ring->active_list;
 #line 1813
   __cil_tmp19 = (struct list_head  const  *)__cil_tmp18;
 #line 1813
   tmp___0 = list_empty(__cil_tmp19);
   }
 #line 1813
   if (tmp___0 == 0) {
 #line 1814
     goto ldv_39281;
   } else {
 #line 1816
     goto ldv_39283;
   }
   ldv_39283: ;
 #line 1818
   return;
 }
 }
 #line 1826 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_reset_fences(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int i ;
   struct drm_i915_fence_reg *reg ;
   struct drm_i915_gem_object *obj ;
   void *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct drm_i915_fence_reg (*__cil_tmp8)[16U] ;
   struct drm_i915_fence_reg *__cil_tmp9 ;
   struct drm_i915_gem_object *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned char *__cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   struct drm_i915_gem_object *__cil_tmp17 ;
   struct drm_i915_gem_object *__cil_tmp18 ;
   struct drm_i915_gem_object *__cil_tmp19 ;
   struct drm_i915_gem_object *__cil_tmp20 ;
 
   {
 #line 1828
   __cil_tmp6 = dev->dev_private;
 #line 1828
   dev_priv = (struct drm_i915_private *)__cil_tmp6;
 #line 1831
   i = 0;
 #line 1831
   goto ldv_39293;
   ldv_39292: 
 #line 1832
   __cil_tmp7 = (unsigned long )i;
 #line 1832
   __cil_tmp8 = & dev_priv->fence_regs;
 #line 1832
   __cil_tmp9 = (struct drm_i915_fence_reg *)__cil_tmp8;
 #line 1832
   reg = __cil_tmp9 + __cil_tmp7;
 #line 1833
   obj = reg->obj;
   {
 #line 1835
   __cil_tmp10 = (struct drm_i915_gem_object *)0;
 #line 1835
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 1835
   __cil_tmp12 = (unsigned long )obj;
 #line 1835
   if (__cil_tmp12 == __cil_tmp11) {
 #line 1836
     goto ldv_39291;
   } else {
 
   }
   }
   {
 #line 1838
   __cil_tmp13 = (unsigned char *)obj;
 #line 1838
   __cil_tmp14 = __cil_tmp13 + 225UL;
 #line 1838
   __cil_tmp15 = *__cil_tmp14;
 #line 1838
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 1838
   if (__cil_tmp16 != 0U) {
     {
 #line 1839
     i915_gem_release_mmap(obj);
     }
   } else {
 
   }
   }
   {
 #line 1841
   __cil_tmp17 = reg->obj;
 #line 1841
   __cil_tmp17->fence_reg = (signed char)-1;
 #line 1842
   __cil_tmp18 = reg->obj;
 #line 1842
   __cil_tmp18->fenced_gpu_access = (unsigned char)0;
 #line 1843
   __cil_tmp19 = reg->obj;
 #line 1843
   __cil_tmp19->last_fenced_seqno = 0U;
 #line 1844
   __cil_tmp20 = reg->obj;
 #line 1844
   __cil_tmp20->last_fenced_ring = (struct intel_ring_buffer *)0;
 #line 1845
   i915_gem_clear_fence_reg(dev, reg);
   }
   ldv_39291: 
 #line 1831
   i = i + 1;
   ldv_39293: ;
 #line 1831
   if (i <= 15) {
 #line 1832
     goto ldv_39292;
   } else {
 #line 1834
     goto ldv_39294;
   }
   ldv_39294: ;
 #line 1836
   return;
 }
 }
 #line 1849 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_reset(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   int i ;
   struct list_head  const  *__mptr ;
   int tmp ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   void *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct intel_ring_buffer (*__cil_tmp11)[3U] ;
   struct intel_ring_buffer *__cil_tmp12 ;
   struct intel_ring_buffer *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct drm_i915_gem_object *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct list_head  const  *__cil_tmp18 ;
   struct list_head *__cil_tmp19 ;
   struct drm_i915_gem_object *__cil_tmp20 ;
   uint32_t __cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct drm_i915_gem_object *__cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct list_head *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
 
   {
 #line 1851
   __cil_tmp9 = dev->dev_private;
 #line 1851
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 1855
   i = 0;
 #line 1855
   goto ldv_39302;
   ldv_39301: 
   {
 #line 1856
   __cil_tmp10 = (unsigned long )i;
 #line 1856
   __cil_tmp11 = & dev_priv->ring;
 #line 1856
   __cil_tmp12 = (struct intel_ring_buffer *)__cil_tmp11;
 #line 1856
   __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
 #line 1856
   i915_gem_reset_ring_lists(dev_priv, __cil_tmp13);
 #line 1855
   i = i + 1;
   }
   ldv_39302: ;
 #line 1855
   if (i <= 2) {
 #line 1856
     goto ldv_39301;
   } else {
 #line 1858
     goto ldv_39303;
   }
   ldv_39303: ;
 #line 1862
   goto ldv_39307;
   ldv_39306: 
   {
 #line 1863
   __cil_tmp14 = dev_priv->mm.flushing_list.next;
 #line 1863
   __mptr = (struct list_head  const  *)__cil_tmp14;
 #line 1863
   __cil_tmp15 = (struct drm_i915_gem_object *)__mptr;
 #line 1863
   obj = __cil_tmp15 + 1152921504606846800UL;
 #line 1867
   obj->base.write_domain = 0U;
 #line 1868
   __cil_tmp16 = & obj->gpu_write_list;
 #line 1868
   list_del_init(__cil_tmp16);
 #line 1869
   i915_gem_object_move_to_inactive(obj);
   }
   ldv_39307: 
   {
 #line 1862
   __cil_tmp17 = & dev_priv->mm.flushing_list;
 #line 1862
   __cil_tmp18 = (struct list_head  const  *)__cil_tmp17;
 #line 1862
   tmp = list_empty(__cil_tmp18);
   }
 #line 1862
   if (tmp == 0) {
 #line 1863
     goto ldv_39306;
   } else {
 #line 1865
     goto ldv_39308;
   }
   ldv_39308: 
 #line 1875
   __cil_tmp19 = dev_priv->mm.inactive_list.next;
 #line 1875
   __mptr___0 = (struct list_head  const  *)__cil_tmp19;
 #line 1875
   __cil_tmp20 = (struct drm_i915_gem_object *)__mptr___0;
 #line 1875
   obj = __cil_tmp20 + 1152921504606846800UL;
 #line 1875
   goto ldv_39314;
   ldv_39313: 
 #line 1879
   __cil_tmp21 = obj->base.read_domains;
 #line 1879
   obj->base.read_domains = __cil_tmp21 & 65U;
 #line 1875
   __cil_tmp22 = obj->mm_list.next;
 #line 1875
   __mptr___1 = (struct list_head  const  *)__cil_tmp22;
 #line 1875
   __cil_tmp23 = (struct drm_i915_gem_object *)__mptr___1;
 #line 1875
   obj = __cil_tmp23 + 1152921504606846800UL;
   ldv_39314: ;
   {
 #line 1875
   __cil_tmp24 = & dev_priv->mm.inactive_list;
 #line 1875
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 1875
   __cil_tmp26 = & obj->mm_list;
 #line 1875
   __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 1875
   if (__cil_tmp27 != __cil_tmp25) {
 #line 1876
     goto ldv_39313;
   } else {
 #line 1878
     goto ldv_39315;
   }
   }
   ldv_39315: 
   {
 #line 1883
   i915_gem_reset_fences(dev);
   }
 #line 1884
   return;
 }
 }
 #line 1890 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring ) 
 { uint32_t seqno ;
   int i ;
   int tmp ;
   int __ret_warn_on ;
   long tmp___0 ;
   struct drm_i915_gem_request *request ;
   struct list_head  const  *__mptr ;
   bool tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   struct drm_i915_gem_object *obj ;
   struct list_head  const  *__mptr___0 ;
   bool tmp___4 ;
   int tmp___5 ;
   int tmp___6 ;
   long tmp___7 ;
   bool tmp___8 ;
   long tmp___9 ;
   int __ret_warn_on___0 ;
   long tmp___10 ;
   struct list_head *__cil_tmp22 ;
   struct list_head  const  *__cil_tmp23 ;
   int __cil_tmp24 ;
   long __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   long __cil_tmp29 ;
   u32 (*__cil_tmp30)(struct intel_ring_buffer * ) ;
   u32 __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   struct list_head *__cil_tmp33 ;
   struct drm_i915_gem_request *__cil_tmp34 ;
   uint32_t __cil_tmp35 ;
   uint32_t __cil_tmp36 ;
   struct list_head *__cil_tmp37 ;
   void const   *__cil_tmp38 ;
   struct list_head *__cil_tmp39 ;
   struct list_head  const  *__cil_tmp40 ;
   struct list_head *__cil_tmp41 ;
   struct drm_i915_gem_object *__cil_tmp42 ;
   uint32_t __cil_tmp43 ;
   uint32_t __cil_tmp44 ;
   struct list_head *__cil_tmp45 ;
   struct list_head  const  *__cil_tmp46 ;
   u32 __cil_tmp47 ;
   int __cil_tmp48 ;
   long __cil_tmp49 ;
   u32 __cil_tmp50 ;
   long __cil_tmp51 ;
   void (*__cil_tmp52)(struct intel_ring_buffer * ) ;
   int __cil_tmp53 ;
   long __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   long __cil_tmp58 ;
 
   {
   {
 #line 1895
   __cil_tmp22 = & ring->request_list;
 #line 1895
   __cil_tmp23 = (struct list_head  const  *)__cil_tmp22;
 #line 1895
   tmp = list_empty(__cil_tmp23);
   }
 #line 1895
   if (tmp != 0) {
 #line 1896
     return;
   } else {
 
   }
   {
 #line 1898
   __ret_warn_on = 0;
 #line 1898
   __cil_tmp24 = __ret_warn_on != 0;
 #line 1898
   __cil_tmp25 = (long )__cil_tmp24;
 #line 1898
   tmp___0 = __builtin_expect(__cil_tmp25, 0L);
   }
 #line 1898
   if (tmp___0 != 0L) {
     {
 #line 1898
     __cil_tmp26 = (int const   )1898;
 #line 1898
     __cil_tmp27 = (int )__cil_tmp26;
 #line 1898
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp27);
     }
   } else {
 
   }
   {
 #line 1898
   __cil_tmp28 = __ret_warn_on != 0;
 #line 1898
   __cil_tmp29 = (long )__cil_tmp28;
 #line 1898
   __builtin_expect(__cil_tmp29, 0L);
 #line 1900
   __cil_tmp30 = ring->get_seqno;
 #line 1900
   seqno = (*__cil_tmp30)(ring);
 #line 1902
   i = 0;
   }
 #line 1902
   goto ldv_39326;
   ldv_39325: ;
   {
 #line 1903
   __cil_tmp31 = ring->sync_seqno[i];
 #line 1903
   if (__cil_tmp31 <= seqno) {
 #line 1904
     ring->sync_seqno[i] = 0U;
   } else {
 
   }
   }
 #line 1902
   i = i + 1;
   ldv_39326: ;
   {
 #line 1902
   __cil_tmp32 = (unsigned int )i;
 #line 1902
   if (__cil_tmp32 <= 1U) {
 #line 1903
     goto ldv_39325;
   } else {
 #line 1905
     goto ldv_39327;
   }
   }
   ldv_39327: ;
 #line 1906
   goto ldv_39333;
   ldv_39332: 
   {
 #line 1909
   __cil_tmp33 = ring->request_list.next;
 #line 1909
   __mptr = (struct list_head  const  *)__cil_tmp33;
 #line 1909
   __cil_tmp34 = (struct drm_i915_gem_request *)__mptr;
 #line 1909
   request = __cil_tmp34 + 1152921504606846952UL;
 #line 1913
   __cil_tmp35 = request->seqno;
 #line 1913
   tmp___1 = i915_seqno_passed(seqno, __cil_tmp35);
   }
 #line 1913
   if (tmp___1) {
 #line 1913
     tmp___2 = 0;
   } else {
 #line 1913
     tmp___2 = 1;
   }
 #line 1913
   if (tmp___2) {
 #line 1914
     goto ldv_39331;
   } else {
 
   }
   {
 #line 1916
   __cil_tmp36 = request->seqno;
 #line 1916
   trace_i915_gem_request_retire(ring, __cil_tmp36);
 #line 1918
   __cil_tmp37 = & request->list;
 #line 1918
   list_del(__cil_tmp37);
 #line 1919
   i915_gem_request_remove_from_client(request);
 #line 1920
   __cil_tmp38 = (void const   *)request;
 #line 1920
   kfree(__cil_tmp38);
   }
   ldv_39333: 
   {
 #line 1906
   __cil_tmp39 = & ring->request_list;
 #line 1906
   __cil_tmp40 = (struct list_head  const  *)__cil_tmp39;
 #line 1906
   tmp___3 = list_empty(__cil_tmp40);
   }
 #line 1906
   if (tmp___3 == 0) {
 #line 1907
     goto ldv_39332;
   } else {
 #line 1909
     goto ldv_39331;
   }
   ldv_39331: ;
 #line 1926
   goto ldv_39339;
   ldv_39338: 
   {
 #line 1929
   __cil_tmp41 = ring->active_list.next;
 #line 1929
   __mptr___0 = (struct list_head  const  *)__cil_tmp41;
 #line 1929
   __cil_tmp42 = (struct drm_i915_gem_object *)__mptr___0;
 #line 1929
   obj = __cil_tmp42 + 1152921504606846816UL;
 #line 1933
   __cil_tmp43 = obj->last_rendering_seqno;
 #line 1933
   tmp___4 = i915_seqno_passed(seqno, __cil_tmp43);
   }
 #line 1933
   if (tmp___4) {
 #line 1933
     tmp___5 = 0;
   } else {
 #line 1933
     tmp___5 = 1;
   }
 #line 1933
   if (tmp___5) {
 #line 1934
     goto ldv_39337;
   } else {
 
   }
   {
 #line 1936
   __cil_tmp44 = obj->base.write_domain;
 #line 1936
   if (__cil_tmp44 != 0U) {
     {
 #line 1937
     i915_gem_object_move_to_flushing(obj);
     }
   } else {
     {
 #line 1939
     i915_gem_object_move_to_inactive(obj);
     }
   }
   }
   ldv_39339: 
   {
 #line 1926
   __cil_tmp45 = & ring->active_list;
 #line 1926
   __cil_tmp46 = (struct list_head  const  *)__cil_tmp45;
 #line 1926
   tmp___6 = list_empty(__cil_tmp46);
   }
 #line 1926
   if (tmp___6 == 0) {
 #line 1927
     goto ldv_39338;
   } else {
 #line 1929
     goto ldv_39337;
   }
   ldv_39337: 
   {
 #line 1942
   __cil_tmp47 = ring->trace_irq_seqno;
 #line 1942
   __cil_tmp48 = __cil_tmp47 != 0U;
 #line 1942
   __cil_tmp49 = (long )__cil_tmp48;
 #line 1942
   tmp___7 = __builtin_expect(__cil_tmp49, 0L);
   }
 #line 1942
   if (tmp___7 != 0L) {
     {
 #line 1942
     __cil_tmp50 = ring->trace_irq_seqno;
 #line 1942
     tmp___8 = i915_seqno_passed(seqno, __cil_tmp50);
 #line 1942
     __cil_tmp51 = (long )tmp___8;
 #line 1942
     tmp___9 = __builtin_expect(__cil_tmp51, 0L);
     }
 #line 1942
     if (tmp___9 != 0L) {
       {
 #line 1944
       __cil_tmp52 = ring->irq_put;
 #line 1944
       (*__cil_tmp52)(ring);
 #line 1945
       ring->trace_irq_seqno = 0U;
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 1948
   __ret_warn_on___0 = 0;
 #line 1948
   __cil_tmp53 = __ret_warn_on___0 != 0;
 #line 1948
   __cil_tmp54 = (long )__cil_tmp53;
 #line 1948
   tmp___10 = __builtin_expect(__cil_tmp54, 0L);
   }
 #line 1948
   if (tmp___10 != 0L) {
     {
 #line 1948
     __cil_tmp55 = (int const   )1948;
 #line 1948
     __cil_tmp56 = (int )__cil_tmp55;
 #line 1948
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp56);
     }
   } else {
 
   }
   {
 #line 1948
   __cil_tmp57 = __ret_warn_on___0 != 0;
 #line 1948
   __cil_tmp58 = (long )__cil_tmp57;
 #line 1948
   __builtin_expect(__cil_tmp58, 0L);
   }
 #line 1950
   return;
 }
 }
 #line 1952 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_retire_requests(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int i ;
   struct drm_i915_gem_object *obj ;
   struct drm_i915_gem_object *next ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   int tmp ;
   void *__cil_tmp10 ;
   struct list_head *__cil_tmp11 ;
   struct list_head  const  *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct drm_i915_gem_object *__cil_tmp14 ;
   struct list_head *__cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct drm_i915_gem_object *__cil_tmp18 ;
   struct list_head *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct intel_ring_buffer (*__cil_tmp24)[3U] ;
   struct intel_ring_buffer *__cil_tmp25 ;
   struct intel_ring_buffer *__cil_tmp26 ;
 
   {
   {
 #line 1954
   __cil_tmp10 = dev->dev_private;
 #line 1954
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 1957
   __cil_tmp11 = & dev_priv->mm.deferred_free_list;
 #line 1957
   __cil_tmp12 = (struct list_head  const  *)__cil_tmp11;
 #line 1957
   tmp = list_empty(__cil_tmp12);
   }
 #line 1957
   if (tmp == 0) {
 #line 1965
     __cil_tmp13 = dev_priv->mm.deferred_free_list.next;
 #line 1965
     __mptr = (struct list_head  const  *)__cil_tmp13;
 #line 1965
     __cil_tmp14 = (struct drm_i915_gem_object *)__mptr;
 #line 1965
     obj = __cil_tmp14 + 1152921504606846800UL;
 #line 1965
     __cil_tmp15 = obj->mm_list.next;
 #line 1965
     __mptr___0 = (struct list_head  const  *)__cil_tmp15;
 #line 1965
     __cil_tmp16 = (struct drm_i915_gem_object *)__mptr___0;
 #line 1965
     next = __cil_tmp16 + 1152921504606846800UL;
 #line 1965
     goto ldv_39356;
     ldv_39355: 
     {
 #line 1968
     i915_gem_free_object_tail(obj);
 #line 1965
     obj = next;
 #line 1965
     __cil_tmp17 = next->mm_list.next;
 #line 1965
     __mptr___1 = (struct list_head  const  *)__cil_tmp17;
 #line 1965
     __cil_tmp18 = (struct drm_i915_gem_object *)__mptr___1;
 #line 1965
     next = __cil_tmp18 + 1152921504606846800UL;
     }
     ldv_39356: ;
     {
 #line 1965
     __cil_tmp19 = & dev_priv->mm.deferred_free_list;
 #line 1965
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 1965
     __cil_tmp21 = & obj->mm_list;
 #line 1965
     __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 1965
     if (__cil_tmp22 != __cil_tmp20) {
 #line 1966
       goto ldv_39355;
     } else {
 #line 1968
       goto ldv_39357;
     }
     }
     ldv_39357: ;
   } else {
 
   }
 #line 1971
   i = 0;
 #line 1971
   goto ldv_39359;
   ldv_39358: 
   {
 #line 1972
   __cil_tmp23 = (unsigned long )i;
 #line 1972
   __cil_tmp24 = & dev_priv->ring;
 #line 1972
   __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
 #line 1972
   __cil_tmp26 = __cil_tmp25 + __cil_tmp23;
 #line 1972
   i915_gem_retire_requests_ring(__cil_tmp26);
 #line 1971
   i = i + 1;
   }
   ldv_39359: ;
 #line 1971
   if (i <= 2) {
 #line 1972
     goto ldv_39358;
   } else {
 #line 1974
     goto ldv_39360;
   }
   ldv_39360: ;
 #line 1976
   return;
 }
 }
 #line 1976 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_retire_work_handler(struct work_struct *work ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_device *dev ;
   bool idle ;
   int i ;
   struct work_struct  const  *__mptr ;
   int tmp ;
   struct intel_ring_buffer *ring ;
   struct drm_i915_gem_request *request ;
   int ret ;
   void *tmp___0 ;
   int tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   drm_i915_private_t *__cil_tmp15 ;
   struct mutex *__cil_tmp16 ;
   struct workqueue_struct *__cil_tmp17 ;
   struct delayed_work *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct intel_ring_buffer (*__cil_tmp20)[3U] ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct list_head  const  *__cil_tmp23 ;
   void const   *__cil_tmp24 ;
   struct drm_i915_gem_request *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   void const   *__cil_tmp28 ;
   struct drm_file *__cil_tmp29 ;
   void const   *__cil_tmp30 ;
   struct list_head *__cil_tmp31 ;
   struct list_head  const  *__cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   struct workqueue_struct *__cil_tmp37 ;
   struct delayed_work *__cil_tmp38 ;
   struct mutex *__cil_tmp39 ;
 
   {
   {
 #line 1983
   __mptr = (struct work_struct  const  *)work;
 #line 1983
   __cil_tmp15 = (drm_i915_private_t *)__mptr;
 #line 1983
   dev_priv = __cil_tmp15 + 1152921504606840288UL;
 #line 1985
   dev = dev_priv->dev;
 #line 1988
   __cil_tmp16 = & dev->struct_mutex;
 #line 1988
   tmp = mutex_trylock(__cil_tmp16);
   }
 #line 1988
   if (tmp == 0) {
     {
 #line 1989
     __cil_tmp17 = dev_priv->wq;
 #line 1989
     __cil_tmp18 = & dev_priv->mm.retire_work;
 #line 1989
     queue_delayed_work(__cil_tmp17, __cil_tmp18, 250UL);
     }
 #line 1990
     return;
   } else {
 
   }
   {
 #line 1993
   i915_gem_retire_requests(dev);
 #line 1998
   idle = (bool )1;
 #line 1999
   i = 0;
   }
 #line 1999
   goto ldv_39374;
   ldv_39373: 
   {
 #line 2000
   __cil_tmp19 = (unsigned long )i;
 #line 2000
   __cil_tmp20 = & dev_priv->ring;
 #line 2000
   __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
 #line 2000
   ring = __cil_tmp21 + __cil_tmp19;
 #line 2002
   __cil_tmp22 = & ring->gpu_write_list;
 #line 2002
   __cil_tmp23 = (struct list_head  const  *)__cil_tmp22;
 #line 2002
   tmp___2 = list_empty(__cil_tmp23);
   }
 #line 2002
   if (tmp___2 == 0) {
     {
 #line 2006
     ret = i915_gem_flush_ring(ring, 0U, 4294967230U);
 #line 2008
     tmp___0 = kzalloc(64UL, 208U);
 #line 2008
     request = (struct drm_i915_gem_request *)tmp___0;
     }
 #line 2009
     if (ret != 0) {
       {
 #line 2011
       __cil_tmp24 = (void const   *)request;
 #line 2011
       kfree(__cil_tmp24);
       }
     } else {
       {
 #line 2009
       __cil_tmp25 = (struct drm_i915_gem_request *)0;
 #line 2009
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 2009
       __cil_tmp27 = (unsigned long )request;
 #line 2009
       if (__cil_tmp27 == __cil_tmp26) {
         {
 #line 2011
         __cil_tmp28 = (void const   *)request;
 #line 2011
         kfree(__cil_tmp28);
         }
       } else {
         {
 #line 2009
         __cil_tmp29 = (struct drm_file *)0;
 #line 2009
         tmp___1 = i915_add_request(ring, __cil_tmp29, request);
         }
 #line 2009
         if (tmp___1 != 0) {
           {
 #line 2011
           __cil_tmp30 = (void const   *)request;
 #line 2011
           kfree(__cil_tmp30);
           }
         } else {
 
         }
       }
       }
     }
   } else {
 
   }
   {
 #line 2014
   __cil_tmp31 = & ring->request_list;
 #line 2014
   __cil_tmp32 = (struct list_head  const  *)__cil_tmp31;
 #line 2014
   tmp___3 = list_empty(__cil_tmp32);
 #line 2014
   __cil_tmp33 = (int )idle;
 #line 2014
   __cil_tmp34 = __cil_tmp33 & tmp___3;
 #line 2014
   __cil_tmp35 = __cil_tmp34 != 0;
 #line 2014
   idle = (bool )__cil_tmp35;
 #line 1999
   i = i + 1;
   }
   ldv_39374: ;
 #line 1999
   if (i <= 2) {
 #line 2000
     goto ldv_39373;
   } else {
 #line 2002
     goto ldv_39375;
   }
   ldv_39375: ;
   {
 #line 2017
   __cil_tmp36 = dev_priv->mm.suspended;
 #line 2017
   if (__cil_tmp36 == 0) {
 #line 2017
     if (! idle) {
       {
 #line 2018
       __cil_tmp37 = dev_priv->wq;
 #line 2018
       __cil_tmp38 = & dev_priv->mm.retire_work;
 #line 2018
       queue_delayed_work(__cil_tmp37, __cil_tmp38, 250UL);
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 2020
   __cil_tmp39 = & dev->struct_mutex;
 #line 2020
   mutex_unlock(__cil_tmp39);
   }
 #line 2021
   return;
 }
 }
 #line 2028 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_wait_request(struct intel_ring_buffer *ring , uint32_t seqno ) 
 { drm_i915_private_t *dev_priv ;
   u32 ier ;
   int ret ;
   long tmp ;
   struct completion *x ;
   bool recovery_complete ;
   unsigned long flags ;
   raw_spinlock_t *tmp___0 ;
   int tmp___1 ;
   int tmp___2 ;
   struct drm_i915_gem_request *request ;
   void *tmp___3 ;
   u32 tmp___4 ;
   u32 tmp___5 ;
   int __ret ;
   wait_queue_t __wait ;
   struct task_struct *tmp___6 ;
   u32 tmp___7 ;
   bool tmp___8 ;
   int tmp___9 ;
   struct task_struct *tmp___10 ;
   int tmp___11 ;
   u32 tmp___12 ;
   bool tmp___13 ;
   int tmp___14 ;
   int tmp___15 ;
   u32 tmp___16 ;
   bool tmp___17 ;
   int tmp___18 ;
   wait_queue_t __wait___0 ;
   struct task_struct *tmp___19 ;
   u32 tmp___20 ;
   bool tmp___21 ;
   int tmp___22 ;
   unsigned long timeout__ ;
   unsigned long tmp___23 ;
   int ret__ ;
   struct thread_info *tmp___24 ;
   int pfo_ret__ ;
   int tmp___25 ;
   u32 tmp___26 ;
   bool tmp___27 ;
   int tmp___28 ;
   int tmp___29 ;
   bool tmp___30 ;
   u32 tmp___31 ;
   bool tmp___32 ;
   int tmp___33 ;
   int tmp___34 ;
   u32 tmp___35 ;
   struct drm_device *__cil_tmp53 ;
   void *__cil_tmp54 ;
   int __cil_tmp55 ;
   long __cil_tmp56 ;
   atomic_t *__cil_tmp57 ;
   atomic_t const   *__cil_tmp58 ;
   spinlock_t *__cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   int __cil_tmp61 ;
   spinlock_t *__cil_tmp62 ;
   u32 __cil_tmp63 ;
   struct drm_i915_gem_request *__cil_tmp64 ;
   unsigned long __cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   struct drm_file *__cil_tmp67 ;
   void const   *__cil_tmp68 ;
   u32 (*__cil_tmp69)(struct intel_ring_buffer * ) ;
   struct drm_device *__cil_tmp70 ;
   void *__cil_tmp71 ;
   struct drm_i915_private *__cil_tmp72 ;
   struct intel_device_info  const  *__cil_tmp73 ;
   u8 __cil_tmp74 ;
   unsigned char __cil_tmp75 ;
   unsigned int __cil_tmp76 ;
   struct drm_device *__cil_tmp77 ;
   void *__cil_tmp78 ;
   struct drm_i915_private *__cil_tmp79 ;
   struct intel_device_info  const  *__cil_tmp80 ;
   u8 __cil_tmp81 ;
   unsigned char __cil_tmp82 ;
   unsigned int __cil_tmp83 ;
   struct drm_device *__cil_tmp84 ;
   void *__cil_tmp85 ;
   struct drm_i915_private *__cil_tmp86 ;
   struct intel_device_info  const  *__cil_tmp87 ;
   unsigned char *__cil_tmp88 ;
   unsigned char *__cil_tmp89 ;
   unsigned char __cil_tmp90 ;
   unsigned int __cil_tmp91 ;
   struct drm_device *__cil_tmp92 ;
   struct drm_driver *__cil_tmp93 ;
   void (*__cil_tmp94)(struct drm_device * ) ;
   struct drm_device *__cil_tmp95 ;
   struct drm_device *__cil_tmp96 ;
   struct drm_driver *__cil_tmp97 ;
   int (*__cil_tmp98)(struct drm_device * ) ;
   struct drm_device *__cil_tmp99 ;
   bool (*__cil_tmp100)(struct intel_ring_buffer * ) ;
   bool __cil_tmp101 ;
   u32 (*__cil_tmp102)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp103 ;
   atomic_t const   *__cil_tmp104 ;
   wait_queue_head_t *__cil_tmp105 ;
   u32 (*__cil_tmp106)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp107 ;
   atomic_t const   *__cil_tmp108 ;
   wait_queue_head_t *__cil_tmp109 ;
   u32 (*__cil_tmp110)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp111 ;
   atomic_t const   *__cil_tmp112 ;
   wait_queue_head_t *__cil_tmp113 ;
   u32 (*__cil_tmp114)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp115 ;
   atomic_t const   *__cil_tmp116 ;
   wait_queue_head_t *__cil_tmp117 ;
   void (*__cil_tmp118)(struct intel_ring_buffer * ) ;
   unsigned int __cil_tmp119 ;
   unsigned int __cil_tmp120 ;
   unsigned long __cil_tmp121 ;
   long __cil_tmp122 ;
   long __cil_tmp123 ;
   long __cil_tmp124 ;
   int __cil_tmp125 ;
   int __cil_tmp126 ;
   atomic_t const   *__cil_tmp127 ;
   u32 (*__cil_tmp128)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp129 ;
   atomic_t const   *__cil_tmp130 ;
   atomic_t *__cil_tmp131 ;
   atomic_t const   *__cil_tmp132 ;
   u32 (*__cil_tmp133)(struct intel_ring_buffer * ) ;
   uint32_t __cil_tmp134 ;
 
   {
   {
 #line 2031
   __cil_tmp53 = ring->dev;
 #line 2031
   __cil_tmp54 = __cil_tmp53->dev_private;
 #line 2031
   dev_priv = (drm_i915_private_t *)__cil_tmp54;
 #line 2033
   ret = 0;
 #line 2035
   __cil_tmp55 = seqno == 0U;
 #line 2035
   __cil_tmp56 = (long )__cil_tmp55;
 #line 2035
   tmp = __builtin_expect(__cil_tmp56, 0L);
   }
 #line 2035
   if (tmp != 0L) {
 #line 2035
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (2035), "i" (12UL));
     ldv_39383: ;
 #line 2035
     goto ldv_39383;
   } else {
 
   }
   {
 #line 2037
   __cil_tmp57 = & dev_priv->mm.wedged;
 #line 2037
   __cil_tmp58 = (atomic_t const   *)__cil_tmp57;
 #line 2037
   tmp___2 = atomic_read(__cil_tmp58);
   }
 #line 2037
   if (tmp___2 != 0) {
     {
 #line 2038
     x = & dev_priv->error_completion;
 #line 2043
     __cil_tmp59 = & x->wait.lock;
 #line 2043
     tmp___0 = spinlock_check(__cil_tmp59);
 #line 2043
     flags = _raw_spin_lock_irqsave(tmp___0);
 #line 2044
     __cil_tmp60 = x->done;
 #line 2044
     __cil_tmp61 = __cil_tmp60 != 0U;
 #line 2044
     recovery_complete = (bool )__cil_tmp61;
 #line 2045
     __cil_tmp62 = & x->wait.lock;
 #line 2045
     spin_unlock_irqrestore(__cil_tmp62, flags);
     }
 #line 2047
     if ((int )recovery_complete) {
 #line 2047
       tmp___1 = -5;
     } else {
 #line 2047
       tmp___1 = -11;
     }
 #line 2047
     return (tmp___1);
   } else {
 
   }
   {
 #line 2050
   __cil_tmp63 = ring->outstanding_lazy_request;
 #line 2050
   if (__cil_tmp63 == seqno) {
     {
 #line 2053
     tmp___3 = kzalloc(64UL, 208U);
 #line 2053
     request = (struct drm_i915_gem_request *)tmp___3;
     }
     {
 #line 2054
     __cil_tmp64 = (struct drm_i915_gem_request *)0;
 #line 2054
     __cil_tmp65 = (unsigned long )__cil_tmp64;
 #line 2054
     __cil_tmp66 = (unsigned long )request;
 #line 2054
     if (__cil_tmp66 == __cil_tmp65) {
 #line 2055
       return (-12);
     } else {
 
     }
     }
     {
 #line 2057
     __cil_tmp67 = (struct drm_file *)0;
 #line 2057
     ret = i915_add_request(ring, __cil_tmp67, request);
     }
 #line 2058
     if (ret != 0) {
       {
 #line 2059
       __cil_tmp68 = (void const   *)request;
 #line 2059
       kfree(__cil_tmp68);
       }
 #line 2060
       return (ret);
     } else {
 
     }
 #line 2063
     seqno = request->seqno;
   } else {
 
   }
   }
   {
 #line 2066
   __cil_tmp69 = ring->get_seqno;
 #line 2066
   tmp___31 = (*__cil_tmp69)(ring);
 #line 2066
   tmp___32 = i915_seqno_passed(tmp___31, seqno);
   }
 #line 2066
   if (tmp___32) {
 #line 2066
     tmp___33 = 0;
   } else {
 #line 2066
     tmp___33 = 1;
   }
 #line 2066
   if (tmp___33) {
     {
 #line 2067
     __cil_tmp70 = ring->dev;
 #line 2067
     __cil_tmp71 = __cil_tmp70->dev_private;
 #line 2067
     __cil_tmp72 = (struct drm_i915_private *)__cil_tmp71;
 #line 2067
     __cil_tmp73 = __cil_tmp72->info;
 #line 2067
     __cil_tmp74 = __cil_tmp73->gen;
 #line 2067
     __cil_tmp75 = (unsigned char )__cil_tmp74;
 #line 2067
     __cil_tmp76 = (unsigned int )__cil_tmp75;
 #line 2067
     if (__cil_tmp76 == 5U) {
       {
 #line 2068
       tmp___4 = i915_read32(dev_priv, 278540U);
 #line 2068
       tmp___5 = i915_read32(dev_priv, 278556U);
 #line 2068
       ier = tmp___4 | tmp___5;
       }
     } else {
       {
 #line 2067
       __cil_tmp77 = ring->dev;
 #line 2067
       __cil_tmp78 = __cil_tmp77->dev_private;
 #line 2067
       __cil_tmp79 = (struct drm_i915_private *)__cil_tmp78;
 #line 2067
       __cil_tmp80 = __cil_tmp79->info;
 #line 2067
       __cil_tmp81 = __cil_tmp80->gen;
 #line 2067
       __cil_tmp82 = (unsigned char )__cil_tmp81;
 #line 2067
       __cil_tmp83 = (unsigned int )__cil_tmp82;
 #line 2067
       if (__cil_tmp83 == 6U) {
         {
 #line 2068
         tmp___4 = i915_read32(dev_priv, 278540U);
 #line 2068
         tmp___5 = i915_read32(dev_priv, 278556U);
 #line 2068
         ier = tmp___4 | tmp___5;
         }
       } else {
         {
 #line 2067
         __cil_tmp84 = ring->dev;
 #line 2067
         __cil_tmp85 = __cil_tmp84->dev_private;
 #line 2067
         __cil_tmp86 = (struct drm_i915_private *)__cil_tmp85;
 #line 2067
         __cil_tmp87 = __cil_tmp86->info;
 #line 2067
         __cil_tmp88 = (unsigned char *)__cil_tmp87;
 #line 2067
         __cil_tmp89 = __cil_tmp88 + 2UL;
 #line 2067
         __cil_tmp90 = *__cil_tmp89;
 #line 2067
         __cil_tmp91 = (unsigned int )__cil_tmp90;
 #line 2067
         if (__cil_tmp91 != 0U) {
           {
 #line 2068
           tmp___4 = i915_read32(dev_priv, 278540U);
 #line 2068
           tmp___5 = i915_read32(dev_priv, 278556U);
 #line 2068
           ier = tmp___4 | tmp___5;
           }
         } else {
           {
 #line 2070
           ier = i915_read32(dev_priv, 8352U);
           }
         }
         }
       }
       }
     }
     }
 #line 2071
     if (ier == 0U) {
       {
 #line 2072
       drm_err("i915_wait_request", "something (likely vbetool) disabled interrupts, re-enabling\n");
 #line 2074
       __cil_tmp92 = ring->dev;
 #line 2074
       __cil_tmp93 = __cil_tmp92->driver;
 #line 2074
       __cil_tmp94 = __cil_tmp93->irq_preinstall;
 #line 2074
       __cil_tmp95 = ring->dev;
 #line 2074
       (*__cil_tmp94)(__cil_tmp95);
 #line 2075
       __cil_tmp96 = ring->dev;
 #line 2075
       __cil_tmp97 = __cil_tmp96->driver;
 #line 2075
       __cil_tmp98 = __cil_tmp97->irq_postinstall;
 #line 2075
       __cil_tmp99 = ring->dev;
 #line 2075
       (*__cil_tmp98)(__cil_tmp99);
       }
     } else {
 
     }
     {
 #line 2078
     trace_i915_gem_request_wait_begin(ring, seqno);
 #line 2080
     ring->waiting_seqno = seqno;
 #line 2081
     __cil_tmp100 = ring->irq_get;
 #line 2081
     tmp___30 = (*__cil_tmp100)(ring);
     }
 #line 2081
     if ((int )tmp___30) {
       {
 #line 2082
       __cil_tmp101 = dev_priv->mm.interruptible;
 #line 2082
       if ((int )__cil_tmp101) {
         {
 #line 2083
         __ret = 0;
 #line 2083
         __cil_tmp102 = ring->get_seqno;
 #line 2083
         tmp___12 = (*__cil_tmp102)(ring);
 #line 2083
         tmp___13 = i915_seqno_passed(tmp___12, seqno);
         }
 #line 2083
         if (tmp___13) {
 #line 2083
           tmp___14 = 0;
         } else {
 #line 2083
           tmp___14 = 1;
         }
 #line 2083
         if (tmp___14) {
           {
 #line 2083
           __cil_tmp103 = & dev_priv->mm.wedged;
 #line 2083
           __cil_tmp104 = (atomic_t const   *)__cil_tmp103;
 #line 2083
           tmp___15 = atomic_read(__cil_tmp104);
           }
 #line 2083
           if (tmp___15 == 0) {
             {
 #line 2083
             tmp___6 = get_current();
 #line 2083
             __wait.flags = 0U;
 #line 2083
             __wait.private = (void *)tmp___6;
 #line 2083
             __wait.func = & autoremove_wake_function;
 #line 2083
             __wait.task_list.next = & __wait.task_list;
 #line 2083
             __wait.task_list.prev = & __wait.task_list;
             }
             ldv_39396: 
             {
 #line 2083
             __cil_tmp105 = & ring->irq_queue;
 #line 2083
             prepare_to_wait(__cil_tmp105, & __wait, 1);
 #line 2083
             __cil_tmp106 = ring->get_seqno;
 #line 2083
             tmp___7 = (*__cil_tmp106)(ring);
 #line 2083
             tmp___8 = i915_seqno_passed(tmp___7, seqno);
             }
 #line 2083
             if ((int )tmp___8) {
 #line 2083
               goto ldv_39394;
             } else {
               {
 #line 2083
               __cil_tmp107 = & dev_priv->mm.wedged;
 #line 2083
               __cil_tmp108 = (atomic_t const   *)__cil_tmp107;
 #line 2083
               tmp___9 = atomic_read(__cil_tmp108);
               }
 #line 2083
               if (tmp___9 != 0) {
 #line 2083
                 goto ldv_39394;
               } else {
 
               }
             }
             {
 #line 2083
             tmp___10 = get_current();
 #line 2083
             tmp___11 = signal_pending(tmp___10);
             }
 #line 2083
             if (tmp___11 == 0) {
               {
 #line 2083
               schedule();
               }
 #line 2083
               goto ldv_39395;
             } else {
 
             }
 #line 2083
             __ret = -512;
 #line 2083
             goto ldv_39394;
             ldv_39395: ;
 #line 2083
             goto ldv_39396;
             ldv_39394: 
             {
 #line 2083
             __cil_tmp109 = & ring->irq_queue;
 #line 2083
             finish_wait(__cil_tmp109, & __wait);
             }
           } else {
 
           }
         } else {
 
         }
 #line 2083
         ret = __ret;
       } else {
         {
 #line 2087
         __cil_tmp110 = ring->get_seqno;
 #line 2087
         tmp___16 = (*__cil_tmp110)(ring);
 #line 2087
         tmp___17 = i915_seqno_passed(tmp___16, seqno);
         }
 #line 2087
         if ((int )tmp___17) {
 #line 2087
           goto ldv_39398;
         } else {
           {
 #line 2087
           __cil_tmp111 = & dev_priv->mm.wedged;
 #line 2087
           __cil_tmp112 = (atomic_t const   *)__cil_tmp111;
 #line 2087
           tmp___18 = atomic_read(__cil_tmp112);
           }
 #line 2087
           if (tmp___18 != 0) {
 #line 2087
             goto ldv_39398;
           } else {
 
           }
         }
         {
 #line 2087
         tmp___19 = get_current();
 #line 2087
         __wait___0.flags = 0U;
 #line 2087
         __wait___0.private = (void *)tmp___19;
 #line 2087
         __wait___0.func = & autoremove_wake_function;
 #line 2087
         __wait___0.task_list.next = & __wait___0.task_list;
 #line 2087
         __wait___0.task_list.prev = & __wait___0.task_list;
         }
         ldv_39401: 
         {
 #line 2087
         __cil_tmp113 = & ring->irq_queue;
 #line 2087
         prepare_to_wait(__cil_tmp113, & __wait___0, 2);
 #line 2087
         __cil_tmp114 = ring->get_seqno;
 #line 2087
         tmp___20 = (*__cil_tmp114)(ring);
 #line 2087
         tmp___21 = i915_seqno_passed(tmp___20, seqno);
         }
 #line 2087
         if ((int )tmp___21) {
 #line 2087
           goto ldv_39400;
         } else {
           {
 #line 2087
           __cil_tmp115 = & dev_priv->mm.wedged;
 #line 2087
           __cil_tmp116 = (atomic_t const   *)__cil_tmp115;
 #line 2087
           tmp___22 = atomic_read(__cil_tmp116);
           }
 #line 2087
           if (tmp___22 != 0) {
 #line 2087
             goto ldv_39400;
           } else {
 
           }
         }
         {
 #line 2087
         schedule();
         }
 #line 2087
         goto ldv_39401;
         ldv_39400: 
         {
 #line 2087
         __cil_tmp117 = & ring->irq_queue;
 #line 2087
         finish_wait(__cil_tmp117, & __wait___0);
         }
         ldv_39398: ;
       }
       }
       {
 #line 2091
       __cil_tmp118 = ring->irq_put;
 #line 2091
       (*__cil_tmp118)(ring);
       }
     } else {
       {
 #line 2092
       __cil_tmp119 = (unsigned int const   )3000U;
 #line 2092
       __cil_tmp120 = (unsigned int )__cil_tmp119;
 #line 2092
       tmp___23 = msecs_to_jiffies(__cil_tmp120);
 #line 2092
       __cil_tmp121 = (unsigned long )jiffies;
 #line 2092
       timeout__ = tmp___23 + __cil_tmp121;
 #line 2092
       ret__ = 0;
       }
 #line 2092
       goto ldv_39420;
       ldv_39419: ;
       {
 #line 2092
       __cil_tmp122 = (long )jiffies;
 #line 2092
       __cil_tmp123 = (long )timeout__;
 #line 2092
       __cil_tmp124 = __cil_tmp123 - __cil_tmp122;
 #line 2092
       if (__cil_tmp124 < 0L) {
 #line 2092
         ret__ = -110;
 #line 2092
         goto ldv_39410;
       } else {
 
       }
       }
       {
 #line 2092
       tmp___24 = current_thread_info();
       }
       {
 #line 2092
       __cil_tmp125 = tmp___24->preempt_count;
 #line 2092
       __cil_tmp126 = __cil_tmp125 & -268435457;
 #line 2092
       if (__cil_tmp126 == 0) {
 #line 2092
         if (1) {
 #line 2092
           goto case_4;
         } else {
 #line 2092
           goto switch_default;
 #line 2092
           if (0) {
 #line 2092
             __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 2092
             goto ldv_39413;
 #line 2092
             __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 2092
             goto ldv_39413;
             case_4: 
 #line 2092
             __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 2092
             goto ldv_39413;
 #line 2092
             __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 2092
             goto ldv_39413;
             switch_default: 
             {
 #line 2092
             __bad_percpu_size();
             }
           } else {
 
           }
         }
         ldv_39413: 
         {
 #line 2092
         __cil_tmp127 = (atomic_t const   *)(& kgdb_active);
 #line 2092
         tmp___25 = atomic_read(__cil_tmp127);
         }
 #line 2092
         if (pfo_ret__ != tmp___25) {
           {
 #line 2092
           msleep(1U);
           }
         } else {
 
         }
       } else {
 
       }
       }
       ldv_39420: 
       {
 #line 2092
       __cil_tmp128 = ring->get_seqno;
 #line 2092
       tmp___26 = (*__cil_tmp128)(ring);
 #line 2092
       tmp___27 = i915_seqno_passed(tmp___26, seqno);
       }
 #line 2092
       if (tmp___27) {
 #line 2092
         tmp___28 = 0;
       } else {
 #line 2092
         tmp___28 = 1;
       }
 #line 2092
       if (tmp___28) {
         {
 #line 2092
         __cil_tmp129 = & dev_priv->mm.wedged;
 #line 2092
         __cil_tmp130 = (atomic_t const   *)__cil_tmp129;
 #line 2092
         tmp___29 = atomic_read(__cil_tmp130);
         }
 #line 2092
         if (tmp___29 == 0) {
 #line 2093
           goto ldv_39419;
         } else {
 #line 2095
           goto ldv_39410;
         }
       } else {
 #line 2095
         goto ldv_39410;
       }
       ldv_39410: ;
 #line 2092
       if (ret__ != 0) {
 #line 2095
         ret = -16;
       } else {
 
       }
     }
     {
 #line 2096
     ring->waiting_seqno = 0U;
 #line 2098
     trace_i915_gem_request_wait_end(ring, seqno);
     }
   } else {
 
   }
   {
 #line 2100
   __cil_tmp131 = & dev_priv->mm.wedged;
 #line 2100
   __cil_tmp132 = (atomic_t const   *)__cil_tmp131;
 #line 2100
   tmp___34 = atomic_read(__cil_tmp132);
   }
 #line 2100
   if (tmp___34 != 0) {
 #line 2101
     ret = -11;
   } else {
 
   }
 #line 2103
   if (ret != 0) {
 #line 2103
     if (ret != -512) {
       {
 #line 2104
       __cil_tmp133 = ring->get_seqno;
 #line 2104
       tmp___35 = (*__cil_tmp133)(ring);
 #line 2104
       __cil_tmp134 = dev_priv->next_seqno;
 #line 2104
       drm_err("i915_wait_request", "%s returns %d (awaiting %d at %d, next %d)\n",
               "i915_wait_request", ret, seqno, tmp___35, __cil_tmp134);
       }
     } else {
 
     }
   } else {
 
   }
 #line 2113
   if (ret == 0) {
     {
 #line 2114
     i915_gem_retire_requests_ring(ring);
     }
   } else {
 
   }
 #line 2116
   return (ret);
 }
 }
 #line 2124 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj ) 
 { int ret ;
   long tmp ;
   uint32_t __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
   long __cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char *__cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   struct intel_ring_buffer *__cil_tmp12 ;
   uint32_t __cil_tmp13 ;
 
   {
   {
 #line 2131
   __cil_tmp4 = obj->base.write_domain;
 #line 2131
   __cil_tmp5 = __cil_tmp4 & 4294967230U;
 #line 2131
   __cil_tmp6 = __cil_tmp5 != 0U;
 #line 2131
   __cil_tmp7 = (long )__cil_tmp6;
 #line 2131
   tmp = __builtin_expect(__cil_tmp7, 0L);
   }
 #line 2131
   if (tmp != 0L) {
 #line 2131
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (2131), "i" (12UL));
     ldv_39426: ;
 #line 2131
     goto ldv_39426;
   } else {
 
   }
   {
 #line 2136
   __cil_tmp8 = (unsigned char *)obj;
 #line 2136
   __cil_tmp9 = __cil_tmp8 + 224UL;
 #line 2136
   __cil_tmp10 = *__cil_tmp9;
 #line 2136
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 2136
   if (__cil_tmp11 != 0U) {
     {
 #line 2137
     __cil_tmp12 = obj->ring;
 #line 2137
     __cil_tmp13 = obj->last_rendering_seqno;
 #line 2137
     ret = i915_wait_request(__cil_tmp12, __cil_tmp13);
     }
 #line 2138
     if (ret != 0) {
 #line 2139
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
 #line 2142
   return (0);
 }
 }
 #line 2149 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_unbind(struct drm_i915_gem_object *obj ) 
 { int ret ;
   uint32_t tmp ;
   int tmp___0 ;
   struct drm_mm_node *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   struct drm_mm_node *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned int *__cil_tmp9 ;
   unsigned int *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   bool __cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct drm_mm_node *__cil_tmp15 ;
 
   {
 #line 2151
   ret = 0;
   {
 #line 2153
   __cil_tmp5 = (struct drm_mm_node *)0;
 #line 2153
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 2153
   __cil_tmp7 = obj->gtt_space;
 #line 2153
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 2153
   if (__cil_tmp8 == __cil_tmp6) {
 #line 2154
     return (0);
   } else {
 
   }
   }
   {
 #line 2156
   __cil_tmp9 = (unsigned int *)obj;
 #line 2156
   __cil_tmp10 = __cil_tmp9 + 56UL;
 #line 2156
   __cil_tmp11 = *__cil_tmp10;
 #line 2156
   if (__cil_tmp11 != 0U) {
     {
 #line 2157
     drm_err("i915_gem_object_unbind", "Attempting to unbind pinned buffer\n");
     }
 #line 2158
     return (-22);
   } else {
 
   }
   }
   {
 #line 2162
   i915_gem_release_mmap(obj);
 #line 2170
   __cil_tmp12 = (bool )1;
 #line 2170
   ret = i915_gem_object_set_to_cpu_domain(obj, __cil_tmp12);
   }
 #line 2171
   if (ret == -512) {
 #line 2172
     return (ret);
   } else {
 
   }
 #line 2177
   if (ret != 0) {
     {
 #line 2178
     i915_gem_clflush_object(obj);
 #line 2179
     tmp = 1U;
 #line 2179
     obj->base.write_domain = tmp;
 #line 2179
     obj->base.read_domains = tmp;
     }
   } else {
 
   }
   {
 #line 2183
   ret = i915_gem_object_put_fence(obj);
   }
 #line 2184
   if (ret == -512) {
 #line 2185
     return (ret);
   } else {
 
   }
   {
 #line 2187
   trace_i915_gem_object_unbind(obj);
 #line 2189
   i915_gem_gtt_unbind_object(obj);
 #line 2190
   i915_gem_object_put_pages_gtt(obj);
 #line 2192
   __cil_tmp13 = & obj->gtt_list;
 #line 2192
   list_del_init(__cil_tmp13);
 #line 2193
   __cil_tmp14 = & obj->mm_list;
 #line 2193
   list_del_init(__cil_tmp14);
 #line 2195
   obj->map_and_fenceable = (unsigned char)1;
 #line 2197
   __cil_tmp15 = obj->gtt_space;
 #line 2197
   drm_mm_put_block(__cil_tmp15);
 #line 2198
   obj->gtt_space = (struct drm_mm_node *)0;
 #line 2199
   obj->gtt_offset = 0U;
 #line 2201
   tmp___0 = i915_gem_object_is_purgeable(obj);
   }
 #line 2201
   if (tmp___0 != 0) {
     {
 #line 2202
     i915_gem_object_truncate(obj);
     }
   } else {
 
   }
 #line 2204
   return (ret);
 }
 }
 #line 2208 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_flush_ring(struct intel_ring_buffer *ring , uint32_t invalidate_domains ,
                         uint32_t flush_domains ) 
 { int ret ;
   unsigned int __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   int (*__cil_tmp7)(struct intel_ring_buffer * , u32  , u32  ) ;
   unsigned int __cil_tmp8 ;
 
   {
   {
 #line 2214
   __cil_tmp5 = invalidate_domains | flush_domains;
 #line 2214
   __cil_tmp6 = __cil_tmp5 & 4294967230U;
 #line 2214
   if (__cil_tmp6 == 0U) {
 #line 2215
     return (0);
   } else {
 
   }
   }
   {
 #line 2217
   trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
 #line 2219
   __cil_tmp7 = ring->flush;
 #line 2219
   ret = (*__cil_tmp7)(ring, invalidate_domains, flush_domains);
   }
 #line 2220
   if (ret != 0) {
 #line 2221
     return (ret);
   } else {
 
   }
   {
 #line 2223
   __cil_tmp8 = flush_domains & 4294967230U;
 #line 2223
   if (__cil_tmp8 != 0U) {
     {
 #line 2224
     i915_gem_process_flushing_list(ring, flush_domains);
     }
   } else {
 
   }
   }
 #line 2226
   return (0);
 }
 }
 #line 2229 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_ring_idle(struct intel_ring_buffer *ring ) 
 { int ret ;
   int tmp ;
   int tmp___0 ;
   int tmp___1 ;
   u32 tmp___2 ;
   int tmp___3 ;
   struct list_head *__cil_tmp8 ;
   struct list_head  const  *__cil_tmp9 ;
   struct list_head *__cil_tmp10 ;
   struct list_head  const  *__cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct list_head  const  *__cil_tmp13 ;
 
   {
   {
 #line 2233
   __cil_tmp8 = & ring->gpu_write_list;
 #line 2233
   __cil_tmp9 = (struct list_head  const  *)__cil_tmp8;
 #line 2233
   tmp = list_empty(__cil_tmp9);
   }
 #line 2233
   if (tmp != 0) {
     {
 #line 2233
     __cil_tmp10 = & ring->active_list;
 #line 2233
     __cil_tmp11 = (struct list_head  const  *)__cil_tmp10;
 #line 2233
     tmp___0 = list_empty(__cil_tmp11);
     }
 #line 2233
     if (tmp___0 != 0) {
 #line 2234
       return (0);
     } else {
 
     }
   } else {
 
   }
   {
 #line 2236
   __cil_tmp12 = & ring->gpu_write_list;
 #line 2236
   __cil_tmp13 = (struct list_head  const  *)__cil_tmp12;
 #line 2236
   tmp___1 = list_empty(__cil_tmp13);
   }
 #line 2236
   if (tmp___1 == 0) {
     {
 #line 2237
     ret = i915_gem_flush_ring(ring, 4294967230U, 4294967230U);
     }
 #line 2239
     if (ret != 0) {
 #line 2240
       return (ret);
     } else {
 
     }
   } else {
 
   }
   {
 #line 2243
   tmp___2 = i915_gem_next_request_seqno(ring);
 #line 2243
   tmp___3 = i915_wait_request(ring, tmp___2);
   }
 #line 2243
   return (tmp___3);
 }
 }
 #line 2247 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gpu_idle(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   bool lists_empty ;
   int ret ;
   int i ;
   int tmp ;
   int tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp9 ;
   struct list_head *__cil_tmp10 ;
   struct list_head  const  *__cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct list_head  const  *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct intel_ring_buffer (*__cil_tmp15)[3U] ;
   struct intel_ring_buffer *__cil_tmp16 ;
   struct intel_ring_buffer *__cil_tmp17 ;
 
   {
   {
 #line 2249
   __cil_tmp9 = dev->dev_private;
 #line 2249
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 2253
   __cil_tmp10 = & dev_priv->mm.flushing_list;
 #line 2253
   __cil_tmp11 = (struct list_head  const  *)__cil_tmp10;
 #line 2253
   tmp = list_empty(__cil_tmp11);
   }
 #line 2253
   if (tmp != 0) {
     {
 #line 2253
     __cil_tmp12 = & dev_priv->mm.active_list;
 #line 2253
     __cil_tmp13 = (struct list_head  const  *)__cil_tmp12;
 #line 2253
     tmp___0 = list_empty(__cil_tmp13);
     }
 #line 2253
     if (tmp___0 != 0) {
 #line 2253
       tmp___1 = 1;
     } else {
 #line 2253
       tmp___1 = 0;
     }
   } else {
 #line 2253
     tmp___1 = 0;
   }
 #line 2253
   lists_empty = (bool )tmp___1;
 #line 2255
   if ((int )lists_empty) {
 #line 2256
     return (0);
   } else {
 
   }
 #line 2259
   i = 0;
 #line 2259
   goto ldv_39450;
   ldv_39449: 
   {
 #line 2260
   __cil_tmp14 = (unsigned long )i;
 #line 2260
   __cil_tmp15 = & dev_priv->ring;
 #line 2260
   __cil_tmp16 = (struct intel_ring_buffer *)__cil_tmp15;
 #line 2260
   __cil_tmp17 = __cil_tmp16 + __cil_tmp14;
 #line 2260
   ret = i915_ring_idle(__cil_tmp17);
   }
 #line 2261
   if (ret != 0) {
 #line 2262
     return (ret);
   } else {
 
   }
 #line 2259
   i = i + 1;
   ldv_39450: ;
 #line 2259
   if (i <= 2) {
 #line 2260
     goto ldv_39449;
   } else {
 #line 2262
     goto ldv_39451;
   }
   ldv_39451: ;
 #line 2265
   return (0);
 }
 }
 #line 2268 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 size ;
   int regnum ;
   uint64_t val ;
   int ret ;
   int tmp ;
   void *__cil_tmp10 ;
   struct drm_mm_node *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   signed char __cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   uint32_t __cil_tmp15 ;
   uint32_t __cil_tmp16 ;
   unsigned long long __cil_tmp17 ;
   unsigned long long __cil_tmp18 ;
   uint32_t __cil_tmp19 ;
   uint64_t __cil_tmp20 ;
   unsigned long long __cil_tmp21 ;
   uint32_t __cil_tmp22 ;
   uint32_t __cil_tmp23 ;
   uint32_t __cil_tmp24 ;
   unsigned long long __cil_tmp25 ;
   unsigned long long __cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   struct intel_ring_buffer *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   u32 __cil_tmp41 ;
   uint64_t __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   int __cil_tmp44 ;
   int __cil_tmp45 ;
   u32 __cil_tmp46 ;
 
   {
 #line 2271
   dev = obj->base.dev;
 #line 2272
   __cil_tmp10 = dev->dev_private;
 #line 2272
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 2273
   __cil_tmp11 = obj->gtt_space;
 #line 2273
   __cil_tmp12 = __cil_tmp11->size;
 #line 2273
   size = (u32 )__cil_tmp12;
 #line 2274
   __cil_tmp13 = obj->fence_reg;
 #line 2274
   regnum = (int )__cil_tmp13;
 #line 2277
   __cil_tmp14 = obj->gtt_offset;
 #line 2277
   __cil_tmp15 = __cil_tmp14 + size;
 #line 2277
   __cil_tmp16 = __cil_tmp15 - 4096U;
 #line 2277
   __cil_tmp17 = (unsigned long long )__cil_tmp16;
 #line 2277
   __cil_tmp18 = __cil_tmp17 & 4294963200ULL;
 #line 2277
   val = __cil_tmp18 << 32;
 #line 2279
   __cil_tmp19 = obj->gtt_offset;
 #line 2279
   __cil_tmp20 = (uint64_t )__cil_tmp19;
 #line 2279
   __cil_tmp21 = __cil_tmp20 & 4294963200ULL;
 #line 2279
   val = __cil_tmp21 | val;
 #line 2280
   __cil_tmp22 = obj->stride;
 #line 2280
   __cil_tmp23 = __cil_tmp22 / 128U;
 #line 2280
   __cil_tmp24 = __cil_tmp23 - 1U;
 #line 2280
   __cil_tmp25 = (unsigned long long )__cil_tmp24;
 #line 2280
   __cil_tmp26 = __cil_tmp25 << 32;
 #line 2280
   val = __cil_tmp26 | val;
   {
 #line 2283
   __cil_tmp27 = (unsigned char *)obj;
 #line 2283
   __cil_tmp28 = __cil_tmp27 + 225UL;
 #line 2283
   __cil_tmp29 = *__cil_tmp28;
 #line 2283
   __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 2283
   if (__cil_tmp30 == 8U) {
 #line 2284
     val = val | 2ULL;
   } else {
 
   }
   }
 #line 2285
   val = val | 1ULL;
   {
 #line 2287
   __cil_tmp31 = (struct intel_ring_buffer *)0;
 #line 2287
   __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 2287
   __cil_tmp33 = (unsigned long )pipelined;
 #line 2287
   if (__cil_tmp33 != __cil_tmp32) {
     {
 #line 2288
     tmp = intel_ring_begin(pipelined, 6);
 #line 2288
     ret = tmp;
     }
 #line 2289
     if (ret != 0) {
 #line 2290
       return (ret);
     } else {
 
     }
     {
 #line 2292
     intel_ring_emit(pipelined, 0U);
 #line 2293
     intel_ring_emit(pipelined, 285212675U);
 #line 2294
     __cil_tmp34 = regnum + 131072;
 #line 2294
     __cil_tmp35 = __cil_tmp34 * 8;
 #line 2294
     __cil_tmp36 = (u32 )__cil_tmp35;
 #line 2294
     intel_ring_emit(pipelined, __cil_tmp36);
 #line 2295
     __cil_tmp37 = (unsigned int )val;
 #line 2295
     intel_ring_emit(pipelined, __cil_tmp37);
 #line 2296
     __cil_tmp38 = regnum + 131072;
 #line 2296
     __cil_tmp39 = __cil_tmp38 * 8;
 #line 2296
     __cil_tmp40 = __cil_tmp39 + 4;
 #line 2296
     __cil_tmp41 = (u32 )__cil_tmp40;
 #line 2296
     intel_ring_emit(pipelined, __cil_tmp41);
 #line 2297
     __cil_tmp42 = val >> 32;
 #line 2297
     __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 2297
     intel_ring_emit(pipelined, __cil_tmp43);
 #line 2298
     intel_ring_advance(pipelined);
     }
   } else {
     {
 #line 2300
     __cil_tmp44 = regnum + 131072;
 #line 2300
     __cil_tmp45 = __cil_tmp44 * 8;
 #line 2300
     __cil_tmp46 = (u32 )__cil_tmp45;
 #line 2300
     i915_write64(dev_priv, __cil_tmp46, val);
     }
   }
   }
 #line 2302
   return (0);
 }
 }
 #line 2305 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i965_write_fence_reg(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 size ;
   int regnum ;
   uint64_t val ;
   int ret ;
   int tmp ;
   void *__cil_tmp10 ;
   struct drm_mm_node *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   signed char __cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   uint32_t __cil_tmp15 ;
   uint32_t __cil_tmp16 ;
   unsigned long long __cil_tmp17 ;
   unsigned long long __cil_tmp18 ;
   uint32_t __cil_tmp19 ;
   uint64_t __cil_tmp20 ;
   unsigned long long __cil_tmp21 ;
   uint32_t __cil_tmp22 ;
   uint32_t __cil_tmp23 ;
   uint32_t __cil_tmp24 ;
   uint32_t __cil_tmp25 ;
   uint64_t __cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   struct intel_ring_buffer *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   u32 __cil_tmp41 ;
   uint64_t __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   int __cil_tmp44 ;
   int __cil_tmp45 ;
   u32 __cil_tmp46 ;
 
   {
 #line 2308
   dev = obj->base.dev;
 #line 2309
   __cil_tmp10 = dev->dev_private;
 #line 2309
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 2310
   __cil_tmp11 = obj->gtt_space;
 #line 2310
   __cil_tmp12 = __cil_tmp11->size;
 #line 2310
   size = (u32 )__cil_tmp12;
 #line 2311
   __cil_tmp13 = obj->fence_reg;
 #line 2311
   regnum = (int )__cil_tmp13;
 #line 2314
   __cil_tmp14 = obj->gtt_offset;
 #line 2314
   __cil_tmp15 = __cil_tmp14 + size;
 #line 2314
   __cil_tmp16 = __cil_tmp15 - 4096U;
 #line 2314
   __cil_tmp17 = (unsigned long long )__cil_tmp16;
 #line 2314
   __cil_tmp18 = __cil_tmp17 & 4294963200ULL;
 #line 2314
   val = __cil_tmp18 << 32;
 #line 2316
   __cil_tmp19 = obj->gtt_offset;
 #line 2316
   __cil_tmp20 = (uint64_t )__cil_tmp19;
 #line 2316
   __cil_tmp21 = __cil_tmp20 & 4294963200ULL;
 #line 2316
   val = __cil_tmp21 | val;
 #line 2317
   __cil_tmp22 = obj->stride;
 #line 2317
   __cil_tmp23 = __cil_tmp22 / 128U;
 #line 2317
   __cil_tmp24 = __cil_tmp23 - 1U;
 #line 2317
   __cil_tmp25 = __cil_tmp24 << 2;
 #line 2317
   __cil_tmp26 = (uint64_t )__cil_tmp25;
 #line 2317
   val = __cil_tmp26 | val;
   {
 #line 2318
   __cil_tmp27 = (unsigned char *)obj;
 #line 2318
   __cil_tmp28 = __cil_tmp27 + 225UL;
 #line 2318
   __cil_tmp29 = *__cil_tmp28;
 #line 2318
   __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 2318
   if (__cil_tmp30 == 8U) {
 #line 2319
     val = val | 2ULL;
   } else {
 
   }
   }
 #line 2320
   val = val | 1ULL;
   {
 #line 2322
   __cil_tmp31 = (struct intel_ring_buffer *)0;
 #line 2322
   __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 2322
   __cil_tmp33 = (unsigned long )pipelined;
 #line 2322
   if (__cil_tmp33 != __cil_tmp32) {
     {
 #line 2323
     tmp = intel_ring_begin(pipelined, 6);
 #line 2323
     ret = tmp;
     }
 #line 2324
     if (ret != 0) {
 #line 2325
       return (ret);
     } else {
 
     }
     {
 #line 2327
     intel_ring_emit(pipelined, 0U);
 #line 2328
     intel_ring_emit(pipelined, 285212675U);
 #line 2329
     __cil_tmp34 = regnum + 1536;
 #line 2329
     __cil_tmp35 = __cil_tmp34 * 8;
 #line 2329
     __cil_tmp36 = (u32 )__cil_tmp35;
 #line 2329
     intel_ring_emit(pipelined, __cil_tmp36);
 #line 2330
     __cil_tmp37 = (unsigned int )val;
 #line 2330
     intel_ring_emit(pipelined, __cil_tmp37);
 #line 2331
     __cil_tmp38 = regnum + 1536;
 #line 2331
     __cil_tmp39 = __cil_tmp38 * 8;
 #line 2331
     __cil_tmp40 = __cil_tmp39 + 4;
 #line 2331
     __cil_tmp41 = (u32 )__cil_tmp40;
 #line 2331
     intel_ring_emit(pipelined, __cil_tmp41);
 #line 2332
     __cil_tmp42 = val >> 32;
 #line 2332
     __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 2332
     intel_ring_emit(pipelined, __cil_tmp43);
 #line 2333
     intel_ring_advance(pipelined);
     }
   } else {
     {
 #line 2335
     __cil_tmp44 = regnum + 1536;
 #line 2335
     __cil_tmp45 = __cil_tmp44 * 8;
 #line 2335
     __cil_tmp46 = (u32 )__cil_tmp45;
 #line 2335
     i915_write64(dev_priv, __cil_tmp46, val);
     }
   }
   }
 #line 2337
   return (0);
 }
 }
 #line 2340 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_write_fence_reg(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 size ;
   u32 fence_reg ;
   u32 val ;
   u32 pitch_val ;
   int tile_width ;
   int __ret_warn_on ;
   int tmp ;
   long tmp___0 ;
   long tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   int ret ;
   int tmp___4 ;
   void *__cil_tmp18 ;
   struct drm_mm_node *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   uint32_t __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   u32 __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   u32 __cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   long __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   uint32_t __cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   long __cil_tmp36 ;
   unsigned char *__cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   void *__cil_tmp41 ;
   struct drm_i915_private *__cil_tmp42 ;
   struct intel_device_info  const  *__cil_tmp43 ;
   u8 __cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   void *__cil_tmp47 ;
   struct drm_i915_private *__cil_tmp48 ;
   struct intel_device_info  const  *__cil_tmp49 ;
   unsigned char *__cil_tmp50 ;
   unsigned char *__cil_tmp51 ;
   unsigned char __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   int __cil_tmp54 ;
   uint32_t __cil_tmp55 ;
   uint32_t __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   unsigned char *__cil_tmp59 ;
   unsigned char *__cil_tmp60 ;
   unsigned char __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   u32 __cil_tmp63 ;
   int __cil_tmp64 ;
   int __cil_tmp65 ;
   int __cil_tmp66 ;
   u32 __cil_tmp67 ;
   u32 __cil_tmp68 ;
   signed char __cil_tmp69 ;
   u32 __cil_tmp70 ;
   u32 __cil_tmp71 ;
   struct intel_ring_buffer *__cil_tmp72 ;
   unsigned long __cil_tmp73 ;
   unsigned long __cil_tmp74 ;
 
   {
 #line 2343
   dev = obj->base.dev;
 #line 2344
   __cil_tmp18 = dev->dev_private;
 #line 2344
   dev_priv = (drm_i915_private_t *)__cil_tmp18;
 #line 2345
   __cil_tmp19 = obj->gtt_space;
 #line 2345
   __cil_tmp20 = __cil_tmp19->size;
 #line 2345
   size = (u32 )__cil_tmp20;
   {
 #line 2349
   __cil_tmp21 = obj->gtt_offset;
 #line 2349
   __cil_tmp22 = __cil_tmp21 & 4027580415U;
 #line 2349
   if (__cil_tmp22 != 0U) {
 #line 2349
     tmp = 1;
   } else {
     {
 #line 2349
     __cil_tmp23 = - size;
 #line 2349
     __cil_tmp24 = __cil_tmp23 & size;
 #line 2349
     if (__cil_tmp24 != size) {
 #line 2349
       tmp = 1;
     } else {
       {
 #line 2349
       __cil_tmp25 = size - 1U;
 #line 2349
       __cil_tmp26 = obj->gtt_offset;
 #line 2349
       __cil_tmp27 = __cil_tmp26 & __cil_tmp25;
 #line 2349
       if (__cil_tmp27 != 0U) {
 #line 2349
         tmp = 1;
       } else {
 #line 2349
         tmp = 0;
       }
       }
     }
     }
   }
   }
   {
 #line 2349
   __ret_warn_on = tmp;
 #line 2349
   __cil_tmp28 = __ret_warn_on != 0;
 #line 2349
   __cil_tmp29 = (long )__cil_tmp28;
 #line 2349
   tmp___0 = __builtin_expect(__cil_tmp29, 0L);
   }
 #line 2349
   if (tmp___0 != 0L) {
     {
 #line 2349
     __cil_tmp30 = (int const   )2353;
 #line 2349
     __cil_tmp31 = (int )__cil_tmp30;
 #line 2349
     __cil_tmp32 = obj->gtt_offset;
 #line 2349
     __cil_tmp33 = obj->map_and_fenceable;
 #line 2349
     __cil_tmp34 = (int )__cil_tmp33;
 #line 2349
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                       __cil_tmp31, "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
                       __cil_tmp32, __cil_tmp34, size);
     }
   } else {
 
   }
   {
 #line 2349
   __cil_tmp35 = __ret_warn_on != 0;
 #line 2349
   __cil_tmp36 = (long )__cil_tmp35;
 #line 2349
   tmp___1 = __builtin_expect(__cil_tmp36, 0L);
   }
 #line 2349
   if (tmp___1 != 0L) {
 #line 2354
     return (-22);
   } else {
 
   }
   {
 #line 2356
   __cil_tmp37 = (unsigned char *)obj;
 #line 2356
   __cil_tmp38 = __cil_tmp37 + 225UL;
 #line 2356
   __cil_tmp39 = *__cil_tmp38;
 #line 2356
   __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 2356
   if (__cil_tmp40 == 8U) {
     {
 #line 2356
     __cil_tmp41 = dev->dev_private;
 #line 2356
     __cil_tmp42 = (struct drm_i915_private *)__cil_tmp41;
 #line 2356
     __cil_tmp43 = __cil_tmp42->info;
 #line 2356
     __cil_tmp44 = __cil_tmp43->gen;
 #line 2356
     __cil_tmp45 = (unsigned char )__cil_tmp44;
 #line 2356
     __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 2356
     if (__cil_tmp46 != 2U) {
       {
 #line 2356
       __cil_tmp47 = dev->dev_private;
 #line 2356
       __cil_tmp48 = (struct drm_i915_private *)__cil_tmp47;
 #line 2356
       __cil_tmp49 = __cil_tmp48->info;
 #line 2356
       __cil_tmp50 = (unsigned char *)__cil_tmp49;
 #line 2356
       __cil_tmp51 = __cil_tmp50 + 1UL;
 #line 2356
       __cil_tmp52 = *__cil_tmp51;
 #line 2356
       __cil_tmp53 = (unsigned int )__cil_tmp52;
 #line 2356
       if (__cil_tmp53 == 0U) {
         {
 #line 2356
         __cil_tmp54 = dev->pci_device;
 #line 2356
         if (__cil_tmp54 != 9618) {
 #line 2357
           tile_width = 128;
         } else {
 #line 2359
           tile_width = 512;
         }
         }
       } else {
 #line 2359
         tile_width = 512;
       }
       }
     } else {
 #line 2359
       tile_width = 512;
     }
     }
   } else {
 #line 2359
     tile_width = 512;
   }
   }
   {
 #line 2362
   __cil_tmp55 = (uint32_t )tile_width;
 #line 2362
   __cil_tmp56 = obj->stride;
 #line 2362
   pitch_val = __cil_tmp56 / __cil_tmp55;
 #line 2363
   __cil_tmp57 = (int )pitch_val;
 #line 2363
   tmp___2 = ffs(__cil_tmp57);
 #line 2363
   __cil_tmp58 = tmp___2 + -1;
 #line 2363
   pitch_val = (u32 )__cil_tmp58;
 #line 2365
   val = obj->gtt_offset;
   }
   {
 #line 2366
   __cil_tmp59 = (unsigned char *)obj;
 #line 2366
   __cil_tmp60 = __cil_tmp59 + 225UL;
 #line 2366
   __cil_tmp61 = *__cil_tmp60;
 #line 2366
   __cil_tmp62 = (unsigned int )__cil_tmp61;
 #line 2366
   if (__cil_tmp62 == 8U) {
 #line 2367
     val = val | 4096U;
   } else {
 
   }
   }
   {
 #line 2368
   __cil_tmp63 = size >> 20;
 #line 2368
   __cil_tmp64 = (int )__cil_tmp63;
 #line 2368
   tmp___3 = ffs(__cil_tmp64);
 #line 2368
   __cil_tmp65 = tmp___3 + -1;
 #line 2368
   __cil_tmp66 = __cil_tmp65 << 8;
 #line 2368
   __cil_tmp67 = (u32 )__cil_tmp66;
 #line 2368
   val = __cil_tmp67 | val;
 #line 2369
   __cil_tmp68 = pitch_val << 4;
 #line 2369
   val = __cil_tmp68 | val;
 #line 2370
   val = val | 1U;
 #line 2372
   __cil_tmp69 = obj->fence_reg;
 #line 2372
   fence_reg = (u32 )__cil_tmp69;
   }
 #line 2373
   if (fence_reg <= 7U) {
 #line 2374
     __cil_tmp70 = fence_reg + 2048U;
 #line 2374
     fence_reg = __cil_tmp70 * 4U;
   } else {
 #line 2376
     __cil_tmp71 = fence_reg + 3064U;
 #line 2376
     fence_reg = __cil_tmp71 * 4U;
   }
   {
 #line 2378
   __cil_tmp72 = (struct intel_ring_buffer *)0;
 #line 2378
   __cil_tmp73 = (unsigned long )__cil_tmp72;
 #line 2378
   __cil_tmp74 = (unsigned long )pipelined;
 #line 2378
   if (__cil_tmp74 != __cil_tmp73) {
     {
 #line 2379
     tmp___4 = intel_ring_begin(pipelined, 4);
 #line 2379
     ret = tmp___4;
     }
 #line 2380
     if (ret != 0) {
 #line 2381
       return (ret);
     } else {
 
     }
     {
 #line 2383
     intel_ring_emit(pipelined, 0U);
 #line 2384
     intel_ring_emit(pipelined, 285212673U);
 #line 2385
     intel_ring_emit(pipelined, fence_reg);
 #line 2386
     intel_ring_emit(pipelined, val);
 #line 2387
     intel_ring_advance(pipelined);
     }
   } else {
     {
 #line 2389
     i915_write32(dev_priv, fence_reg, val);
     }
   }
   }
 #line 2391
   return (0);
 }
 }
 #line 2394 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i830_write_fence_reg(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   u32 size ;
   int regnum ;
   uint32_t val ;
   uint32_t pitch_val ;
   int __ret_warn_on ;
   int tmp ;
   long tmp___0 ;
   long tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   int ret ;
   int tmp___4 ;
   void *__cil_tmp17 ;
   struct drm_mm_node *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   signed char __cil_tmp20 ;
   uint32_t __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   u32 __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   u32 __cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   long __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   uint32_t __cil_tmp32 ;
   int __cil_tmp33 ;
   long __cil_tmp34 ;
   uint32_t __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   u32 __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   int __cil_tmp45 ;
   uint32_t __cil_tmp46 ;
   uint32_t __cil_tmp47 ;
   struct intel_ring_buffer *__cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   int __cil_tmp51 ;
   int __cil_tmp52 ;
   u32 __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   u32 __cil_tmp56 ;
 
   {
 #line 2397
   dev = obj->base.dev;
 #line 2398
   __cil_tmp17 = dev->dev_private;
 #line 2398
   dev_priv = (drm_i915_private_t *)__cil_tmp17;
 #line 2399
   __cil_tmp18 = obj->gtt_space;
 #line 2399
   __cil_tmp19 = __cil_tmp18->size;
 #line 2399
   size = (u32 )__cil_tmp19;
 #line 2400
   __cil_tmp20 = obj->fence_reg;
 #line 2400
   regnum = (int )__cil_tmp20;
   {
 #line 2404
   __cil_tmp21 = obj->gtt_offset;
 #line 2404
   __cil_tmp22 = __cil_tmp21 & 4161273855U;
 #line 2404
   if (__cil_tmp22 != 0U) {
 #line 2404
     tmp = 1;
   } else {
     {
 #line 2404
     __cil_tmp23 = - size;
 #line 2404
     __cil_tmp24 = __cil_tmp23 & size;
 #line 2404
     if (__cil_tmp24 != size) {
 #line 2404
       tmp = 1;
     } else {
       {
 #line 2404
       __cil_tmp25 = size - 1U;
 #line 2404
       __cil_tmp26 = obj->gtt_offset;
 #line 2404
       __cil_tmp27 = __cil_tmp26 & __cil_tmp25;
 #line 2404
       if (__cil_tmp27 != 0U) {
 #line 2404
         tmp = 1;
       } else {
 #line 2404
         tmp = 0;
       }
       }
     }
     }
   }
   }
   {
 #line 2404
   __ret_warn_on = tmp;
 #line 2404
   __cil_tmp28 = __ret_warn_on != 0;
 #line 2404
   __cil_tmp29 = (long )__cil_tmp28;
 #line 2404
   tmp___0 = __builtin_expect(__cil_tmp29, 0L);
   }
 #line 2404
   if (tmp___0 != 0L) {
     {
 #line 2404
     __cil_tmp30 = (int const   )2408;
 #line 2404
     __cil_tmp31 = (int )__cil_tmp30;
 #line 2404
     __cil_tmp32 = obj->gtt_offset;
 #line 2404
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                       __cil_tmp31, "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
                       __cil_tmp32, size);
     }
   } else {
 
   }
   {
 #line 2404
   __cil_tmp33 = __ret_warn_on != 0;
 #line 2404
   __cil_tmp34 = (long )__cil_tmp33;
 #line 2404
   tmp___1 = __builtin_expect(__cil_tmp34, 0L);
   }
 #line 2404
   if (tmp___1 != 0L) {
 #line 2409
     return (-22);
   } else {
 
   }
   {
 #line 2411
   __cil_tmp35 = obj->stride;
 #line 2411
   pitch_val = __cil_tmp35 / 128U;
 #line 2412
   __cil_tmp36 = (int )pitch_val;
 #line 2412
   tmp___2 = ffs(__cil_tmp36);
 #line 2412
   __cil_tmp37 = tmp___2 + -1;
 #line 2412
   pitch_val = (uint32_t )__cil_tmp37;
 #line 2414
   val = obj->gtt_offset;
   }
   {
 #line 2415
   __cil_tmp38 = (unsigned char *)obj;
 #line 2415
   __cil_tmp39 = __cil_tmp38 + 225UL;
 #line 2415
   __cil_tmp40 = *__cil_tmp39;
 #line 2415
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 2415
   if (__cil_tmp41 == 8U) {
 #line 2416
     val = val | 4096U;
   } else {
 
   }
   }
   {
 #line 2417
   __cil_tmp42 = size >> 19;
 #line 2417
   __cil_tmp43 = (int )__cil_tmp42;
 #line 2417
   tmp___3 = ffs(__cil_tmp43);
 #line 2417
   __cil_tmp44 = tmp___3 + -1;
 #line 2417
   __cil_tmp45 = __cil_tmp44 << 8;
 #line 2417
   __cil_tmp46 = (uint32_t )__cil_tmp45;
 #line 2417
   val = __cil_tmp46 | val;
 #line 2418
   __cil_tmp47 = pitch_val << 4;
 #line 2418
   val = __cil_tmp47 | val;
 #line 2419
   val = val | 1U;
   }
   {
 #line 2421
   __cil_tmp48 = (struct intel_ring_buffer *)0;
 #line 2421
   __cil_tmp49 = (unsigned long )__cil_tmp48;
 #line 2421
   __cil_tmp50 = (unsigned long )pipelined;
 #line 2421
   if (__cil_tmp50 != __cil_tmp49) {
     {
 #line 2422
     tmp___4 = intel_ring_begin(pipelined, 4);
 #line 2422
     ret = tmp___4;
     }
 #line 2423
     if (ret != 0) {
 #line 2424
       return (ret);
     } else {
 
     }
     {
 #line 2426
     intel_ring_emit(pipelined, 0U);
 #line 2427
     intel_ring_emit(pipelined, 285212673U);
 #line 2428
     __cil_tmp51 = regnum + 2048;
 #line 2428
     __cil_tmp52 = __cil_tmp51 * 4;
 #line 2428
     __cil_tmp53 = (u32 )__cil_tmp52;
 #line 2428
     intel_ring_emit(pipelined, __cil_tmp53);
 #line 2429
     intel_ring_emit(pipelined, val);
 #line 2430
     intel_ring_advance(pipelined);
     }
   } else {
     {
 #line 2432
     __cil_tmp54 = regnum + 2048;
 #line 2432
     __cil_tmp55 = __cil_tmp54 * 4;
 #line 2432
     __cil_tmp56 = (u32 )__cil_tmp55;
 #line 2432
     i915_write32(dev_priv, __cil_tmp56, val);
     }
   }
   }
 #line 2434
   return (0);
 }
 }
 #line 2437 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static bool ring_passed_seqno(struct intel_ring_buffer *ring , u32 seqno ) 
 { u32 tmp ;
   bool tmp___0 ;
   u32 (*__cil_tmp5)(struct intel_ring_buffer * ) ;
 
   {
   {
 #line 2439
   __cil_tmp5 = ring->get_seqno;
 #line 2439
   tmp = (*__cil_tmp5)(ring);
 #line 2439
   tmp___0 = i915_seqno_passed(tmp, seqno);
   }
 #line 2439
   return (tmp___0);
 }
 }
 #line 2443 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_flush_fence(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { int ret ;
   bool tmp ;
   int tmp___0 ;
   unsigned char *__cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   struct intel_ring_buffer *__cil_tmp12 ;
   uint32_t __cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct intel_ring_buffer *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct intel_ring_buffer *__cil_tmp18 ;
   uint32_t __cil_tmp19 ;
   struct intel_ring_buffer *__cil_tmp20 ;
   uint32_t __cil_tmp21 ;
   uint32_t __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
 
   {
   {
 #line 2448
   __cil_tmp6 = (unsigned char *)obj;
 #line 2448
   __cil_tmp7 = __cil_tmp6 + 226UL;
 #line 2448
   __cil_tmp8 = *__cil_tmp7;
 #line 2448
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 2448
   if (__cil_tmp9 != 0U) {
     {
 #line 2449
     __cil_tmp10 = obj->base.write_domain;
 #line 2449
     __cil_tmp11 = __cil_tmp10 & 4294967230U;
 #line 2449
     if (__cil_tmp11 != 0U) {
       {
 #line 2450
       __cil_tmp12 = obj->last_fenced_ring;
 #line 2450
       __cil_tmp13 = obj->base.write_domain;
 #line 2450
       ret = i915_gem_flush_ring(__cil_tmp12, 0U, __cil_tmp13);
       }
 #line 2452
       if (ret != 0) {
 #line 2453
         return (ret);
       } else {
 
       }
     } else {
 
     }
     }
 #line 2456
     obj->fenced_gpu_access = (unsigned char)0;
   } else {
 
   }
   }
   {
 #line 2459
   __cil_tmp14 = obj->last_fenced_seqno;
 #line 2459
   if (__cil_tmp14 != 0U) {
     {
 #line 2459
     __cil_tmp15 = (unsigned long )pipelined;
 #line 2459
     __cil_tmp16 = obj->last_fenced_ring;
 #line 2459
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 2459
     if (__cil_tmp17 != __cil_tmp15) {
       {
 #line 2460
       __cil_tmp18 = obj->last_fenced_ring;
 #line 2460
       __cil_tmp19 = obj->last_fenced_seqno;
 #line 2460
       tmp = ring_passed_seqno(__cil_tmp18, __cil_tmp19);
       }
 #line 2460
       if (tmp) {
 #line 2460
         tmp___0 = 0;
       } else {
 #line 2460
         tmp___0 = 1;
       }
 #line 2460
       if (tmp___0) {
         {
 #line 2462
         __cil_tmp20 = obj->last_fenced_ring;
 #line 2462
         __cil_tmp21 = obj->last_fenced_seqno;
 #line 2462
         ret = i915_wait_request(__cil_tmp20, __cil_tmp21);
         }
 #line 2464
         if (ret != 0) {
 #line 2465
           return (ret);
         } else {
 
         }
       } else {
 
       }
 #line 2468
       obj->last_fenced_seqno = 0U;
 #line 2469
       obj->last_fenced_ring = (struct intel_ring_buffer *)0;
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 2475
   __cil_tmp22 = obj->base.read_domains;
 #line 2475
   __cil_tmp23 = __cil_tmp22 & 64U;
 #line 2475
   if (__cil_tmp23 != 0U) {
 #line 2476
     __asm__  volatile   ("mfence": : : "memory");
   } else {
 
   }
   }
 #line 2478
   return (0);
 }
 }
 #line 2482 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj ) 
 { int ret ;
   struct drm_i915_private *dev_priv ;
   unsigned char *__cil_tmp4 ;
   unsigned char *__cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   struct intel_ring_buffer *__cil_tmp8 ;
   unsigned char *__cil_tmp9 ;
   unsigned char *__cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   struct drm_device *__cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_device *__cil_tmp15 ;
   signed char __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct drm_i915_fence_reg (*__cil_tmp18)[16U] ;
   struct drm_i915_fence_reg *__cil_tmp19 ;
   struct drm_i915_fence_reg *__cil_tmp20 ;
 
   {
   {
 #line 2486
   __cil_tmp4 = (unsigned char *)obj;
 #line 2486
   __cil_tmp5 = __cil_tmp4 + 225UL;
 #line 2486
   __cil_tmp6 = *__cil_tmp5;
 #line 2486
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 2486
   if (__cil_tmp7 != 0U) {
     {
 #line 2487
     i915_gem_release_mmap(obj);
     }
   } else {
 
   }
   }
   {
 #line 2489
   __cil_tmp8 = (struct intel_ring_buffer *)0;
 #line 2489
   ret = i915_gem_object_flush_fence(obj, __cil_tmp8);
   }
 #line 2490
   if (ret != 0) {
 #line 2491
     return (ret);
   } else {
 
   }
   {
 #line 2493
   __cil_tmp9 = (unsigned char *)obj;
 #line 2493
   __cil_tmp10 = __cil_tmp9 + 224UL;
 #line 2493
   __cil_tmp11 = *__cil_tmp10;
 #line 2493
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 2493
   if (__cil_tmp12 != 248U) {
     {
 #line 2494
     __cil_tmp13 = obj->base.dev;
 #line 2494
     __cil_tmp14 = __cil_tmp13->dev_private;
 #line 2494
     dev_priv = (struct drm_i915_private *)__cil_tmp14;
 #line 2495
     __cil_tmp15 = obj->base.dev;
 #line 2495
     __cil_tmp16 = obj->fence_reg;
 #line 2495
     __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 2495
     __cil_tmp18 = & dev_priv->fence_regs;
 #line 2495
     __cil_tmp19 = (struct drm_i915_fence_reg *)__cil_tmp18;
 #line 2495
     __cil_tmp20 = __cil_tmp19 + __cil_tmp17;
 #line 2495
     i915_gem_clear_fence_reg(__cil_tmp15, __cil_tmp20);
 #line 2498
     obj->fence_reg = (signed char)-1;
     }
   } else {
 
   }
   }
 #line 2501
   return (0);
 }
 }
 #line 2505 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static struct drm_i915_fence_reg *i915_find_fence_reg(struct drm_device *dev , struct intel_ring_buffer *pipelined ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_fence_reg *reg ;
   struct drm_i915_fence_reg *first ;
   struct drm_i915_fence_reg *avail ;
   int i ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_i915_fence_reg (*__cil_tmp12)[16U] ;
   struct drm_i915_fence_reg *__cil_tmp13 ;
   struct drm_i915_gem_object *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct drm_i915_gem_object *__cil_tmp18 ;
   unsigned int *__cil_tmp19 ;
   unsigned int *__cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   int __cil_tmp22 ;
   struct drm_i915_fence_reg *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct list_head *__cil_tmp26 ;
   struct drm_i915_gem_object *__cil_tmp27 ;
   unsigned int *__cil_tmp28 ;
   unsigned int *__cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   struct drm_i915_fence_reg *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   struct intel_ring_buffer *__cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   struct intel_ring_buffer *__cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   struct drm_i915_gem_object *__cil_tmp39 ;
   struct intel_ring_buffer *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct drm_i915_gem_object *__cil_tmp43 ;
   struct intel_ring_buffer *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct list_head *__cil_tmp46 ;
   struct list_head *__cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   struct list_head *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   struct drm_i915_fence_reg *__cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   unsigned long __cil_tmp53 ;
 
   {
 #line 2508
   __cil_tmp10 = dev->dev_private;
 #line 2508
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 2513
   avail = (struct drm_i915_fence_reg *)0;
 #line 2514
   i = dev_priv->fence_reg_start;
 #line 2514
   goto ldv_39523;
   ldv_39522: 
 #line 2515
   __cil_tmp11 = (unsigned long )i;
 #line 2515
   __cil_tmp12 = & dev_priv->fence_regs;
 #line 2515
   __cil_tmp13 = (struct drm_i915_fence_reg *)__cil_tmp12;
 #line 2515
   reg = __cil_tmp13 + __cil_tmp11;
   {
 #line 2516
   __cil_tmp14 = (struct drm_i915_gem_object *)0;
 #line 2516
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 2516
   __cil_tmp16 = reg->obj;
 #line 2516
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 2516
   if (__cil_tmp17 == __cil_tmp15) {
 #line 2517
     return (reg);
   } else {
 
   }
   }
   {
 #line 2519
   __cil_tmp18 = reg->obj;
 #line 2519
   __cil_tmp19 = (unsigned int *)__cil_tmp18;
 #line 2519
   __cil_tmp20 = __cil_tmp19 + 56UL;
 #line 2519
   __cil_tmp21 = *__cil_tmp20;
 #line 2519
   if (__cil_tmp21 == 0U) {
 #line 2520
     avail = reg;
   } else {
 
   }
   }
 #line 2514
   i = i + 1;
   ldv_39523: ;
   {
 #line 2514
   __cil_tmp22 = dev_priv->num_fence_regs;
 #line 2514
   if (__cil_tmp22 > i) {
 #line 2515
     goto ldv_39522;
   } else {
 #line 2517
     goto ldv_39524;
   }
   }
   ldv_39524: ;
   {
 #line 2523
   __cil_tmp23 = (struct drm_i915_fence_reg *)0;
 #line 2523
   __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 2523
   __cil_tmp25 = (unsigned long )avail;
 #line 2523
   if (__cil_tmp25 == __cil_tmp24) {
 #line 2524
     return ((struct drm_i915_fence_reg *)0);
   } else {
 
   }
   }
 #line 2527
   first = (struct drm_i915_fence_reg *)0;
 #line 2527
   avail = first;
 #line 2528
   __cil_tmp26 = dev_priv->mm.fence_list.next;
 #line 2528
   __mptr = (struct list_head  const  *)__cil_tmp26;
 #line 2528
   reg = (struct drm_i915_fence_reg *)__mptr;
 #line 2528
   goto ldv_39532;
   ldv_39531: ;
   {
 #line 2529
   __cil_tmp27 = reg->obj;
 #line 2529
   __cil_tmp28 = (unsigned int *)__cil_tmp27;
 #line 2529
   __cil_tmp29 = __cil_tmp28 + 56UL;
 #line 2529
   __cil_tmp30 = *__cil_tmp29;
 #line 2529
   if (__cil_tmp30 != 0U) {
 #line 2530
     goto ldv_39529;
   } else {
 
   }
   }
   {
 #line 2532
   __cil_tmp31 = (struct drm_i915_fence_reg *)0;
 #line 2532
   __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 2532
   __cil_tmp33 = (unsigned long )first;
 #line 2532
   if (__cil_tmp33 == __cil_tmp32) {
 #line 2533
     first = reg;
   } else {
 
   }
   }
   {
 #line 2535
   __cil_tmp34 = (struct intel_ring_buffer *)0;
 #line 2535
   __cil_tmp35 = (unsigned long )__cil_tmp34;
 #line 2535
   __cil_tmp36 = (unsigned long )pipelined;
 #line 2535
   if (__cil_tmp36 == __cil_tmp35) {
 #line 2538
     avail = reg;
 #line 2539
     goto ldv_39530;
   } else {
     {
 #line 2535
     __cil_tmp37 = (struct intel_ring_buffer *)0;
 #line 2535
     __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 2535
     __cil_tmp39 = reg->obj;
 #line 2535
     __cil_tmp40 = __cil_tmp39->last_fenced_ring;
 #line 2535
     __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 2535
     if (__cil_tmp41 == __cil_tmp38) {
 #line 2538
       avail = reg;
 #line 2539
       goto ldv_39530;
     } else {
       {
 #line 2535
       __cil_tmp42 = (unsigned long )pipelined;
 #line 2535
       __cil_tmp43 = reg->obj;
 #line 2535
       __cil_tmp44 = __cil_tmp43->last_fenced_ring;
 #line 2535
       __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 2535
       if (__cil_tmp45 == __cil_tmp42) {
 #line 2538
         avail = reg;
 #line 2539
         goto ldv_39530;
       } else {
 
       }
       }
     }
     }
   }
   }
   ldv_39529: 
 #line 2528
   __cil_tmp46 = reg->lru_list.next;
 #line 2528
   __mptr___0 = (struct list_head  const  *)__cil_tmp46;
 #line 2528
   reg = (struct drm_i915_fence_reg *)__mptr___0;
   ldv_39532: ;
   {
 #line 2528
   __cil_tmp47 = & dev_priv->mm.fence_list;
 #line 2528
   __cil_tmp48 = (unsigned long )__cil_tmp47;
 #line 2528
   __cil_tmp49 = & reg->lru_list;
 #line 2528
   __cil_tmp50 = (unsigned long )__cil_tmp49;
 #line 2528
   if (__cil_tmp50 != __cil_tmp48) {
 #line 2529
     goto ldv_39531;
   } else {
 #line 2531
     goto ldv_39530;
   }
   }
   ldv_39530: ;
   {
 #line 2543
   __cil_tmp51 = (struct drm_i915_fence_reg *)0;
 #line 2543
   __cil_tmp52 = (unsigned long )__cil_tmp51;
 #line 2543
   __cil_tmp53 = (unsigned long )avail;
 #line 2543
   if (__cil_tmp53 == __cil_tmp52) {
 #line 2544
     avail = first;
   } else {
 
   }
   }
 #line 2546
   return (avail);
 }
 }
 #line 2565 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct drm_i915_fence_reg *reg ;
   int ret ;
   bool tmp ;
   int tmp___0 ;
   struct drm_i915_gem_object *old ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp12 ;
   unsigned char *__cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   signed char __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct drm_i915_fence_reg (*__cil_tmp19)[16U] ;
   struct drm_i915_fence_reg *__cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   uint32_t __cil_tmp31 ;
   struct intel_ring_buffer *__cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   struct intel_ring_buffer *__cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   uint32_t __cil_tmp38 ;
   struct intel_ring_buffer *__cil_tmp39 ;
   uint32_t __cil_tmp40 ;
   struct intel_ring_buffer *__cil_tmp41 ;
   uint32_t __cil_tmp42 ;
   struct intel_ring_buffer *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   struct intel_ring_buffer *__cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   struct intel_ring_buffer *__cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   struct drm_i915_fence_reg *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   struct drm_i915_gem_object *__cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   struct drm_i915_gem_object *__cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   struct drm_gem_object *__cil_tmp57 ;
   unsigned char *__cil_tmp58 ;
   unsigned char *__cil_tmp59 ;
   unsigned char __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   struct drm_gem_object *__cil_tmp62 ;
   uint32_t __cil_tmp63 ;
   uint32_t __cil_tmp64 ;
   struct intel_ring_buffer *__cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   struct drm_gem_object *__cil_tmp68 ;
   uint32_t __cil_tmp69 ;
   struct list_head *__cil_tmp70 ;
   struct list_head *__cil_tmp71 ;
   struct drm_i915_fence_reg (*__cil_tmp72)[16U] ;
   long __cil_tmp73 ;
   long __cil_tmp74 ;
   long __cil_tmp75 ;
   long __cil_tmp76 ;
   struct intel_ring_buffer *__cil_tmp77 ;
   unsigned long __cil_tmp78 ;
   unsigned long __cil_tmp79 ;
   void *__cil_tmp80 ;
   struct drm_i915_private *__cil_tmp81 ;
   struct intel_device_info  const  *__cil_tmp82 ;
   u8 __cil_tmp83 ;
   int __cil_tmp84 ;
   void *__cil_tmp85 ;
   struct drm_i915_private *__cil_tmp86 ;
   struct intel_device_info  const  *__cil_tmp87 ;
   u8 __cil_tmp88 ;
   int __cil_tmp89 ;
   void *__cil_tmp90 ;
   struct drm_i915_private *__cil_tmp91 ;
   struct intel_device_info  const  *__cil_tmp92 ;
   u8 __cil_tmp93 ;
   int __cil_tmp94 ;
   void *__cil_tmp95 ;
   struct drm_i915_private *__cil_tmp96 ;
   struct intel_device_info  const  *__cil_tmp97 ;
   u8 __cil_tmp98 ;
   int __cil_tmp99 ;
   void *__cil_tmp100 ;
   struct drm_i915_private *__cil_tmp101 ;
   struct intel_device_info  const  *__cil_tmp102 ;
   u8 __cil_tmp103 ;
   int __cil_tmp104 ;
   void *__cil_tmp105 ;
   struct drm_i915_private *__cil_tmp106 ;
   struct intel_device_info  const  *__cil_tmp107 ;
   u8 __cil_tmp108 ;
   int __cil_tmp109 ;
 
   {
 #line 2568
   dev = obj->base.dev;
 #line 2569
   __cil_tmp12 = dev->dev_private;
 #line 2569
   dev_priv = (struct drm_i915_private *)__cil_tmp12;
 #line 2574
   pipelined = (struct intel_ring_buffer *)0;
   {
 #line 2577
   __cil_tmp13 = (unsigned char *)obj;
 #line 2577
   __cil_tmp14 = __cil_tmp13 + 224UL;
 #line 2577
   __cil_tmp15 = *__cil_tmp14;
 #line 2577
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 2577
   if (__cil_tmp16 != 248U) {
     {
 #line 2578
     __cil_tmp17 = obj->fence_reg;
 #line 2578
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 2578
     __cil_tmp19 = & dev_priv->fence_regs;
 #line 2578
     __cil_tmp20 = (struct drm_i915_fence_reg *)__cil_tmp19;
 #line 2578
     reg = __cil_tmp20 + __cil_tmp18;
 #line 2579
     __cil_tmp21 = & reg->lru_list;
 #line 2579
     __cil_tmp22 = & dev_priv->mm.fence_list;
 #line 2579
     list_move_tail(__cil_tmp21, __cil_tmp22);
     }
     {
 #line 2581
     __cil_tmp23 = (unsigned char *)obj;
 #line 2581
     __cil_tmp24 = __cil_tmp23 + 225UL;
 #line 2581
     __cil_tmp25 = *__cil_tmp24;
 #line 2581
     __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 2581
     if (__cil_tmp26 != 0U) {
       {
 #line 2582
       ret = i915_gem_object_flush_fence(obj, pipelined);
       }
 #line 2583
       if (ret != 0) {
 #line 2584
         return (ret);
       } else {
 
       }
       {
 #line 2586
       __cil_tmp27 = (unsigned char *)obj;
 #line 2586
       __cil_tmp28 = __cil_tmp27 + 226UL;
 #line 2586
       __cil_tmp29 = *__cil_tmp28;
 #line 2586
       __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 2586
       if (__cil_tmp30 == 0U) {
         {
 #line 2586
         __cil_tmp31 = obj->last_fenced_seqno;
 #line 2586
         if (__cil_tmp31 == 0U) {
 #line 2587
           pipelined = (struct intel_ring_buffer *)0;
         } else {
 
         }
         }
       } else {
 
       }
       }
       {
 #line 2589
       __cil_tmp32 = (struct intel_ring_buffer *)0;
 #line 2589
       __cil_tmp33 = (unsigned long )__cil_tmp32;
 #line 2589
       __cil_tmp34 = (unsigned long )pipelined;
 #line 2589
       if (__cil_tmp34 != __cil_tmp33) {
         {
 #line 2590
         reg->setup_seqno = i915_gem_next_request_seqno(pipelined);
 #line 2592
         obj->last_fenced_seqno = reg->setup_seqno;
 #line 2593
         obj->last_fenced_ring = pipelined;
         }
       } else {
 
       }
       }
 #line 2596
       goto update;
     } else {
 
     }
     }
     {
 #line 2599
     __cil_tmp35 = (struct intel_ring_buffer *)0;
 #line 2599
     __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 2599
     __cil_tmp37 = (unsigned long )pipelined;
 #line 2599
     if (__cil_tmp37 == __cil_tmp36) {
       {
 #line 2600
       __cil_tmp38 = reg->setup_seqno;
 #line 2600
       if (__cil_tmp38 != 0U) {
         {
 #line 2601
         __cil_tmp39 = obj->last_fenced_ring;
 #line 2601
         __cil_tmp40 = reg->setup_seqno;
 #line 2601
         tmp = ring_passed_seqno(__cil_tmp39, __cil_tmp40);
         }
 #line 2601
         if (tmp) {
 #line 2601
           tmp___0 = 0;
         } else {
 #line 2601
           tmp___0 = 1;
         }
 #line 2601
         if (tmp___0) {
           {
 #line 2603
           __cil_tmp41 = obj->last_fenced_ring;
 #line 2603
           __cil_tmp42 = reg->setup_seqno;
 #line 2603
           ret = i915_wait_request(__cil_tmp41, __cil_tmp42);
           }
 #line 2605
           if (ret != 0) {
 #line 2606
             return (ret);
           } else {
 
           }
         } else {
 
         }
 #line 2609
         reg->setup_seqno = 0U;
       } else {
         {
 #line 2611
         __cil_tmp43 = (struct intel_ring_buffer *)0;
 #line 2611
         __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 2611
         __cil_tmp45 = obj->last_fenced_ring;
 #line 2611
         __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 2611
         if (__cil_tmp46 != __cil_tmp44) {
           {
 #line 2611
           __cil_tmp47 = (unsigned long )pipelined;
 #line 2611
           __cil_tmp48 = obj->last_fenced_ring;
 #line 2611
           __cil_tmp49 = (unsigned long )__cil_tmp48;
 #line 2611
           if (__cil_tmp49 != __cil_tmp47) {
             {
 #line 2613
             ret = i915_gem_object_flush_fence(obj, pipelined);
             }
 #line 2614
             if (ret != 0) {
 #line 2615
               return (ret);
             } else {
 
             }
           } else {
 
           }
           }
         } else {
 
         }
         }
       }
       }
     } else {
 
     }
     }
 #line 2618
     return (0);
   } else {
 
   }
   }
   {
 #line 2621
   reg = i915_find_fence_reg(dev, pipelined);
   }
   {
 #line 2622
   __cil_tmp50 = (struct drm_i915_fence_reg *)0;
 #line 2622
   __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 2622
   __cil_tmp52 = (unsigned long )reg;
 #line 2622
   if (__cil_tmp52 == __cil_tmp51) {
 #line 2623
     return (-28);
   } else {
 
   }
   }
   {
 #line 2625
   ret = i915_gem_object_flush_fence(obj, pipelined);
   }
 #line 2626
   if (ret != 0) {
 #line 2627
     return (ret);
   } else {
 
   }
   {
 #line 2629
   __cil_tmp53 = (struct drm_i915_gem_object *)0;
 #line 2629
   __cil_tmp54 = (unsigned long )__cil_tmp53;
 #line 2629
   __cil_tmp55 = reg->obj;
 #line 2629
   __cil_tmp56 = (unsigned long )__cil_tmp55;
 #line 2629
   if (__cil_tmp56 != __cil_tmp54) {
     {
 #line 2630
     old = reg->obj;
 #line 2632
     __cil_tmp57 = & old->base;
 #line 2632
     drm_gem_object_reference(__cil_tmp57);
     }
     {
 #line 2634
     __cil_tmp58 = (unsigned char *)old;
 #line 2634
     __cil_tmp59 = __cil_tmp58 + 225UL;
 #line 2634
     __cil_tmp60 = *__cil_tmp59;
 #line 2634
     __cil_tmp61 = (unsigned int )__cil_tmp60;
 #line 2634
     if (__cil_tmp61 != 0U) {
       {
 #line 2635
       i915_gem_release_mmap(old);
       }
     } else {
 
     }
     }
     {
 #line 2637
     ret = i915_gem_object_flush_fence(old, pipelined);
     }
 #line 2638
     if (ret != 0) {
       {
 #line 2639
       __cil_tmp62 = & old->base;
 #line 2639
       drm_gem_object_unreference(__cil_tmp62);
       }
 #line 2640
       return (ret);
     } else {
 
     }
     {
 #line 2643
     __cil_tmp63 = old->last_fenced_seqno;
 #line 2643
     if (__cil_tmp63 == 0U) {
       {
 #line 2643
       __cil_tmp64 = obj->last_fenced_seqno;
 #line 2643
       if (__cil_tmp64 == 0U) {
 #line 2644
         pipelined = (struct intel_ring_buffer *)0;
       } else {
 
       }
       }
     } else {
 
     }
     }
 #line 2646
     old->fence_reg = (signed char)-1;
 #line 2647
     old->last_fenced_ring = pipelined;
     {
 #line 2648
     __cil_tmp65 = (struct intel_ring_buffer *)0;
 #line 2648
     __cil_tmp66 = (unsigned long )__cil_tmp65;
 #line 2648
     __cil_tmp67 = (unsigned long )pipelined;
 #line 2648
     if (__cil_tmp67 != __cil_tmp66) {
       {
 #line 2648
       tmp___1 = i915_gem_next_request_seqno(pipelined);
 #line 2648
       old->last_fenced_seqno = tmp___1;
       }
     } else {
 #line 2648
       old->last_fenced_seqno = 0U;
     }
     }
     {
 #line 2651
     __cil_tmp68 = & old->base;
 #line 2651
     drm_gem_object_unreference(__cil_tmp68);
     }
   } else {
     {
 #line 2652
     __cil_tmp69 = obj->last_fenced_seqno;
 #line 2652
     if (__cil_tmp69 == 0U) {
 #line 2653
       pipelined = (struct intel_ring_buffer *)0;
     } else {
 
     }
     }
   }
   }
   {
 #line 2655
   reg->obj = obj;
 #line 2656
   __cil_tmp70 = & reg->lru_list;
 #line 2656
   __cil_tmp71 = & dev_priv->mm.fence_list;
 #line 2656
   list_move_tail(__cil_tmp70, __cil_tmp71);
 #line 2657
   __cil_tmp72 = & dev_priv->fence_regs;
 #line 2657
   __cil_tmp73 = (long )__cil_tmp72;
 #line 2657
   __cil_tmp74 = (long )reg;
 #line 2657
   __cil_tmp75 = __cil_tmp74 - __cil_tmp73;
 #line 2657
   __cil_tmp76 = __cil_tmp75 / 32L;
 #line 2657
   obj->fence_reg = (signed char )__cil_tmp76;
 #line 2658
   obj->last_fenced_ring = pipelined;
   }
   {
 #line 2660
   __cil_tmp77 = (struct intel_ring_buffer *)0;
 #line 2660
   __cil_tmp78 = (unsigned long )__cil_tmp77;
 #line 2660
   __cil_tmp79 = (unsigned long )pipelined;
 #line 2660
   if (__cil_tmp79 != __cil_tmp78) {
     {
 #line 2660
     tmp___2 = i915_gem_next_request_seqno(pipelined);
 #line 2660
     reg->setup_seqno = tmp___2;
     }
   } else {
 #line 2660
     reg->setup_seqno = 0U;
   }
   }
 #line 2662
   obj->last_fenced_seqno = reg->setup_seqno;
   update: 
 #line 2665
   obj->tiling_changed = (unsigned char)0;
   {
 #line 2667
   __cil_tmp80 = dev->dev_private;
 #line 2667
   __cil_tmp81 = (struct drm_i915_private *)__cil_tmp80;
 #line 2667
   __cil_tmp82 = __cil_tmp81->info;
 #line 2667
   __cil_tmp83 = __cil_tmp82->gen;
 #line 2667
   __cil_tmp84 = (int )__cil_tmp83;
 #line 2667
   if (__cil_tmp84 == 7) {
 #line 2667
     goto case_7;
   } else {
     {
 #line 2668
     __cil_tmp85 = dev->dev_private;
 #line 2668
     __cil_tmp86 = (struct drm_i915_private *)__cil_tmp85;
 #line 2668
     __cil_tmp87 = __cil_tmp86->info;
 #line 2668
     __cil_tmp88 = __cil_tmp87->gen;
 #line 2668
     __cil_tmp89 = (int )__cil_tmp88;
 #line 2668
     if (__cil_tmp89 == 6) {
 #line 2668
       goto case_6;
     } else {
       {
 #line 2671
       __cil_tmp90 = dev->dev_private;
 #line 2671
       __cil_tmp91 = (struct drm_i915_private *)__cil_tmp90;
 #line 2671
       __cil_tmp92 = __cil_tmp91->info;
 #line 2671
       __cil_tmp93 = __cil_tmp92->gen;
 #line 2671
       __cil_tmp94 = (int )__cil_tmp93;
 #line 2671
       if (__cil_tmp94 == 5) {
 #line 2671
         goto case_5;
       } else {
         {
 #line 2672
         __cil_tmp95 = dev->dev_private;
 #line 2672
         __cil_tmp96 = (struct drm_i915_private *)__cil_tmp95;
 #line 2672
         __cil_tmp97 = __cil_tmp96->info;
 #line 2672
         __cil_tmp98 = __cil_tmp97->gen;
 #line 2672
         __cil_tmp99 = (int )__cil_tmp98;
 #line 2672
         if (__cil_tmp99 == 4) {
 #line 2672
           goto case_4;
         } else {
           {
 #line 2675
           __cil_tmp100 = dev->dev_private;
 #line 2675
           __cil_tmp101 = (struct drm_i915_private *)__cil_tmp100;
 #line 2675
           __cil_tmp102 = __cil_tmp101->info;
 #line 2675
           __cil_tmp103 = __cil_tmp102->gen;
 #line 2675
           __cil_tmp104 = (int )__cil_tmp103;
 #line 2675
           if (__cil_tmp104 == 3) {
 #line 2675
             goto case_3;
           } else {
             {
 #line 2678
             __cil_tmp105 = dev->dev_private;
 #line 2678
             __cil_tmp106 = (struct drm_i915_private *)__cil_tmp105;
 #line 2678
             __cil_tmp107 = __cil_tmp106->info;
 #line 2678
             __cil_tmp108 = __cil_tmp107->gen;
 #line 2678
             __cil_tmp109 = (int )__cil_tmp108;
 #line 2678
             if (__cil_tmp109 == 2) {
 #line 2678
               goto case_2;
             } else
 #line 2666
             if (0) {
               case_7: ;
               case_6: 
               {
 #line 2669
               ret = sandybridge_write_fence_reg(obj, pipelined);
               }
 #line 2670
               goto ldv_39545;
               case_5: ;
               case_4: 
               {
 #line 2673
               ret = i965_write_fence_reg(obj, pipelined);
               }
 #line 2674
               goto ldv_39545;
               case_3: 
               {
 #line 2676
               ret = i915_write_fence_reg(obj, pipelined);
               }
 #line 2677
               goto ldv_39545;
               case_2: 
               {
 #line 2679
               ret = i830_write_fence_reg(obj, pipelined);
               }
 #line 2680
               goto ldv_39545;
             } else {
 
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_39545: ;
 #line 2683
   return (ret);
 }
 }
 #line 2694 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_clear_fence_reg(struct drm_device *dev , struct drm_i915_fence_reg *reg ) 
 { drm_i915_private_t *dev_priv ;
   uint32_t fence_reg ;
   void *__cil_tmp5 ;
   struct drm_i915_fence_reg (*__cil_tmp6)[16U] ;
   long __cil_tmp7 ;
   long __cil_tmp8 ;
   long __cil_tmp9 ;
   long __cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   int __cil_tmp15 ;
   void *__cil_tmp16 ;
   struct drm_i915_private *__cil_tmp17 ;
   struct intel_device_info  const  *__cil_tmp18 ;
   u8 __cil_tmp19 ;
   int __cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   u8 __cil_tmp24 ;
   int __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct drm_i915_private *__cil_tmp27 ;
   struct intel_device_info  const  *__cil_tmp28 ;
   u8 __cil_tmp29 ;
   int __cil_tmp30 ;
   void *__cil_tmp31 ;
   struct drm_i915_private *__cil_tmp32 ;
   struct intel_device_info  const  *__cil_tmp33 ;
   u8 __cil_tmp34 ;
   int __cil_tmp35 ;
   void *__cil_tmp36 ;
   struct drm_i915_private *__cil_tmp37 ;
   struct intel_device_info  const  *__cil_tmp38 ;
   u8 __cil_tmp39 ;
   int __cil_tmp40 ;
   uint32_t __cil_tmp41 ;
   uint32_t __cil_tmp42 ;
   uint32_t __cil_tmp43 ;
   uint32_t __cil_tmp44 ;
   uint32_t __cil_tmp45 ;
   uint32_t __cil_tmp46 ;
   struct list_head *__cil_tmp47 ;
 
   {
 #line 2697
   __cil_tmp5 = dev->dev_private;
 #line 2697
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 2698
   __cil_tmp6 = & dev_priv->fence_regs;
 #line 2698
   __cil_tmp7 = (long )__cil_tmp6;
 #line 2698
   __cil_tmp8 = (long )reg;
 #line 2698
   __cil_tmp9 = __cil_tmp8 - __cil_tmp7;
 #line 2698
   __cil_tmp10 = __cil_tmp9 / 32L;
 #line 2698
   fence_reg = (uint32_t )__cil_tmp10;
   {
 #line 2701
   __cil_tmp11 = dev->dev_private;
 #line 2701
   __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 2701
   __cil_tmp13 = __cil_tmp12->info;
 #line 2701
   __cil_tmp14 = __cil_tmp13->gen;
 #line 2701
   __cil_tmp15 = (int )__cil_tmp14;
 #line 2701
   if (__cil_tmp15 == 7) {
 #line 2701
     goto case_7;
   } else {
     {
 #line 2702
     __cil_tmp16 = dev->dev_private;
 #line 2702
     __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
 #line 2702
     __cil_tmp18 = __cil_tmp17->info;
 #line 2702
     __cil_tmp19 = __cil_tmp18->gen;
 #line 2702
     __cil_tmp20 = (int )__cil_tmp19;
 #line 2702
     if (__cil_tmp20 == 6) {
 #line 2702
       goto case_6;
     } else {
       {
 #line 2705
       __cil_tmp21 = dev->dev_private;
 #line 2705
       __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 2705
       __cil_tmp23 = __cil_tmp22->info;
 #line 2705
       __cil_tmp24 = __cil_tmp23->gen;
 #line 2705
       __cil_tmp25 = (int )__cil_tmp24;
 #line 2705
       if (__cil_tmp25 == 5) {
 #line 2705
         goto case_5;
       } else {
         {
 #line 2706
         __cil_tmp26 = dev->dev_private;
 #line 2706
         __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
 #line 2706
         __cil_tmp28 = __cil_tmp27->info;
 #line 2706
         __cil_tmp29 = __cil_tmp28->gen;
 #line 2706
         __cil_tmp30 = (int )__cil_tmp29;
 #line 2706
         if (__cil_tmp30 == 4) {
 #line 2706
           goto case_4;
         } else {
           {
 #line 2709
           __cil_tmp31 = dev->dev_private;
 #line 2709
           __cil_tmp32 = (struct drm_i915_private *)__cil_tmp31;
 #line 2709
           __cil_tmp33 = __cil_tmp32->info;
 #line 2709
           __cil_tmp34 = __cil_tmp33->gen;
 #line 2709
           __cil_tmp35 = (int )__cil_tmp34;
 #line 2709
           if (__cil_tmp35 == 3) {
 #line 2709
             goto case_3;
           } else {
             {
 #line 2713
             __cil_tmp36 = dev->dev_private;
 #line 2713
             __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
 #line 2713
             __cil_tmp38 = __cil_tmp37->info;
 #line 2713
             __cil_tmp39 = __cil_tmp38->gen;
 #line 2713
             __cil_tmp40 = (int )__cil_tmp39;
 #line 2713
             if (__cil_tmp40 == 2) {
 #line 2713
               goto case_2;
             } else
 #line 2700
             if (0) {
               case_7: ;
               case_6: 
               {
 #line 2703
               __cil_tmp41 = fence_reg + 131072U;
 #line 2703
               __cil_tmp42 = __cil_tmp41 * 8U;
 #line 2703
               i915_write64(dev_priv, __cil_tmp42, 0ULL);
               }
 #line 2704
               goto ldv_39558;
               case_5: ;
               case_4: 
               {
 #line 2707
               __cil_tmp43 = fence_reg + 1536U;
 #line 2707
               __cil_tmp44 = __cil_tmp43 * 8U;
 #line 2707
               i915_write64(dev_priv, __cil_tmp44, 0ULL);
               }
 #line 2708
               goto ldv_39558;
               case_3: ;
 #line 2710
               if (fence_reg > 7U) {
 #line 2711
                 __cil_tmp45 = fence_reg + 3064U;
 #line 2711
                 fence_reg = __cil_tmp45 * 4U;
               } else {
                 case_2: 
 #line 2714
                 __cil_tmp46 = fence_reg + 2048U;
 #line 2714
                 fence_reg = __cil_tmp46 * 4U;
               }
               {
 #line 2716
               i915_write32(dev_priv, fence_reg, 0U);
               }
 #line 2717
               goto ldv_39558;
             } else {
 
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_39558: 
   {
 #line 2720
   __cil_tmp47 = & reg->lru_list;
 #line 2720
   list_del_init(__cil_tmp47);
 #line 2721
   reg->obj = (struct drm_i915_gem_object *)0;
 #line 2722
   reg->setup_seqno = 0U;
   }
 #line 2723
   return;
 }
 }
 #line 2729 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj , unsigned int alignment ,
                                        bool map_and_fenceable ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   struct drm_mm_node *free_space ;
   gfp_t gfpmask ;
   u32 size ;
   u32 fence_size ;
   u32 fence_alignment ;
   u32 unfenced_alignment ;
   bool mappable ;
   bool fenceable ;
   int ret ;
   unsigned long tmp ;
   int tmp___0 ;
   long tmp___1 ;
   long tmp___2 ;
   int tmp___3 ;
   int tmp___4 ;
   void *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   size_t __cil_tmp26 ;
   uint32_t __cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   int __cil_tmp29 ;
   size_t __cil_tmp30 ;
   uint32_t __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   int __cil_tmp33 ;
   size_t __cil_tmp34 ;
   uint32_t __cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   size_t __cil_tmp40 ;
   size_t __cil_tmp41 ;
   struct drm_mm *__cil_tmp42 ;
   struct drm_mm  const  *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct drm_mm *__cil_tmp46 ;
   struct drm_mm  const  *__cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   struct drm_mm_node *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   struct drm_mm_node *__cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   struct drm_mm_node *__cil_tmp57 ;
   unsigned long __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   bool __cil_tmp61 ;
   struct drm_mm_node *__cil_tmp62 ;
   bool __cil_tmp63 ;
   struct drm_mm_node *__cil_tmp64 ;
   bool __cil_tmp65 ;
   struct list_head *__cil_tmp66 ;
   struct list_head *__cil_tmp67 ;
   struct list_head *__cil_tmp68 ;
   struct list_head *__cil_tmp69 ;
   uint32_t __cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   int __cil_tmp72 ;
   long __cil_tmp73 ;
   uint32_t __cil_tmp74 ;
   unsigned int __cil_tmp75 ;
   int __cil_tmp76 ;
   long __cil_tmp77 ;
   struct drm_mm_node *__cil_tmp78 ;
   unsigned long __cil_tmp79 ;
   unsigned long __cil_tmp80 ;
   struct drm_mm_node *__cil_tmp81 ;
   unsigned long __cil_tmp82 ;
   u32 __cil_tmp83 ;
   unsigned long __cil_tmp84 ;
   struct drm_mm_node *__cil_tmp85 ;
   unsigned long __cil_tmp86 ;
   unsigned long __cil_tmp87 ;
   unsigned long __cil_tmp88 ;
   size_t __cil_tmp89 ;
   uint32_t __cil_tmp90 ;
   size_t __cil_tmp91 ;
   size_t __cil_tmp92 ;
   int __cil_tmp93 ;
   int __cil_tmp94 ;
   bool __cil_tmp95 ;
 
   {
 #line 2733
   dev = obj->base.dev;
 #line 2734
   __cil_tmp21 = dev->dev_private;
 #line 2734
   dev_priv = (drm_i915_private_t *)__cil_tmp21;
 #line 2736
   gfpmask = 4608U;
   {
 #line 2741
   __cil_tmp22 = (unsigned char *)obj;
 #line 2741
   __cil_tmp23 = __cil_tmp22 + 225UL;
 #line 2741
   __cil_tmp24 = *__cil_tmp23;
 #line 2741
   __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 2741
   if (__cil_tmp25 != 0U) {
     {
 #line 2742
     drm_err("i915_gem_object_bind_to_gtt", "Attempting to bind a purgeable object\n");
     }
 #line 2743
     return (-22);
   } else {
 
   }
   }
   {
 #line 2746
   __cil_tmp26 = obj->base.size;
 #line 2746
   __cil_tmp27 = (uint32_t )__cil_tmp26;
 #line 2746
   __cil_tmp28 = obj->tiling_mode;
 #line 2746
   __cil_tmp29 = (int )__cil_tmp28;
 #line 2746
   fence_size = i915_gem_get_gtt_size(dev, __cil_tmp27, __cil_tmp29);
 #line 2749
   __cil_tmp30 = obj->base.size;
 #line 2749
   __cil_tmp31 = (uint32_t )__cil_tmp30;
 #line 2749
   __cil_tmp32 = obj->tiling_mode;
 #line 2749
   __cil_tmp33 = (int )__cil_tmp32;
 #line 2749
   fence_alignment = i915_gem_get_gtt_alignment(dev, __cil_tmp31, __cil_tmp33);
 #line 2752
   __cil_tmp34 = obj->base.size;
 #line 2752
   __cil_tmp35 = (uint32_t )__cil_tmp34;
 #line 2752
   __cil_tmp36 = obj->tiling_mode;
 #line 2752
   __cil_tmp37 = (int )__cil_tmp36;
 #line 2752
   unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev, __cil_tmp35, __cil_tmp37);
   }
 #line 2757
   if (alignment == 0U) {
 #line 2758
     if ((int )map_and_fenceable) {
 #line 2758
       alignment = fence_alignment;
     } else {
 #line 2758
       alignment = unfenced_alignment;
     }
   } else {
 
   }
 #line 2760
   if ((int )map_and_fenceable) {
     {
 #line 2760
     __cil_tmp38 = fence_alignment - 1U;
 #line 2760
     __cil_tmp39 = __cil_tmp38 & alignment;
 #line 2760
     if (__cil_tmp39 != 0U) {
       {
 #line 2761
       drm_err("i915_gem_object_bind_to_gtt", "Invalid object alignment requested %u\n",
               alignment);
       }
 #line 2762
       return (-22);
     } else {
 
     }
     }
   } else {
 
   }
 #line 2765
   if ((int )map_and_fenceable) {
 #line 2765
     size = fence_size;
   } else {
 #line 2765
     __cil_tmp40 = obj->base.size;
 #line 2765
     size = (u32 )__cil_tmp40;
   }
 #line 2770
   if ((int )map_and_fenceable) {
 #line 2770
     tmp = dev_priv->mm.gtt_mappable_end;
   } else {
 #line 2770
     tmp = dev_priv->mm.gtt_total;
   }
   {
 #line 2770
   __cil_tmp41 = obj->base.size;
 #line 2770
   if (__cil_tmp41 > tmp) {
     {
 #line 2772
     drm_err("i915_gem_object_bind_to_gtt", "Attempting to bind an object larger than the aperture\n");
     }
 #line 2773
     return (-7);
   } else {
 
   }
   }
   search_free: ;
 #line 2777
   if ((int )map_and_fenceable) {
     {
 #line 2778
     __cil_tmp42 = & dev_priv->mm.gtt_space;
 #line 2778
     __cil_tmp43 = (struct drm_mm  const  *)__cil_tmp42;
 #line 2778
     __cil_tmp44 = (unsigned long )size;
 #line 2778
     __cil_tmp45 = dev_priv->mm.gtt_mappable_end;
 #line 2778
     free_space = drm_mm_search_free_in_range(__cil_tmp43, __cil_tmp44, alignment,
                                              0UL, __cil_tmp45, 0);
     }
   } else {
     {
 #line 2784
     __cil_tmp46 = & dev_priv->mm.gtt_space;
 #line 2784
     __cil_tmp47 = (struct drm_mm  const  *)__cil_tmp46;
 #line 2784
     __cil_tmp48 = (unsigned long )size;
 #line 2784
     free_space = drm_mm_search_free(__cil_tmp47, __cil_tmp48, alignment, 0);
     }
   }
   {
 #line 2787
   __cil_tmp49 = (struct drm_mm_node *)0;
 #line 2787
   __cil_tmp50 = (unsigned long )__cil_tmp49;
 #line 2787
   __cil_tmp51 = (unsigned long )free_space;
 #line 2787
   if (__cil_tmp51 != __cil_tmp50) {
 #line 2788
     if ((int )map_and_fenceable) {
       {
 #line 2789
       __cil_tmp52 = (unsigned long )size;
 #line 2789
       __cil_tmp53 = dev_priv->mm.gtt_mappable_end;
 #line 2789
       obj->gtt_space = drm_mm_get_block_range_generic(free_space, __cil_tmp52, alignment,
                                                       0UL, __cil_tmp53, 0);
       }
     } else {
       {
 #line 2795
       __cil_tmp54 = (unsigned long )size;
 #line 2795
       obj->gtt_space = drm_mm_get_block(free_space, __cil_tmp54, alignment);
       }
     }
   } else {
 
   }
   }
   {
 #line 2798
   __cil_tmp55 = (struct drm_mm_node *)0;
 #line 2798
   __cil_tmp56 = (unsigned long )__cil_tmp55;
 #line 2798
   __cil_tmp57 = obj->gtt_space;
 #line 2798
   __cil_tmp58 = (unsigned long )__cil_tmp57;
 #line 2798
   if (__cil_tmp58 == __cil_tmp56) {
     {
 #line 2802
     __cil_tmp59 = (int )size;
 #line 2802
     __cil_tmp60 = (int )map_and_fenceable;
 #line 2802
     __cil_tmp61 = (bool )__cil_tmp60;
 #line 2802
     ret = i915_gem_evict_something(dev, __cil_tmp59, alignment, __cil_tmp61);
     }
 #line 2804
     if (ret != 0) {
 #line 2805
       return (ret);
     } else {
 
     }
 #line 2807
     goto search_free;
   } else {
 
   }
   }
   {
 #line 2810
   ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
   }
 #line 2811
   if (ret != 0) {
     {
 #line 2812
     __cil_tmp62 = obj->gtt_space;
 #line 2812
     drm_mm_put_block(__cil_tmp62);
 #line 2813
     obj->gtt_space = (struct drm_mm_node *)0;
     }
 #line 2815
     if (ret == -12) {
       {
 #line 2817
       __cil_tmp63 = (bool )0;
 #line 2817
       ret = i915_gem_evict_everything(dev, __cil_tmp63);
       }
 #line 2818
       if (ret != 0) {
 #line 2820
         if (gfpmask != 0U) {
 #line 2821
           gfpmask = 0U;
 #line 2822
           goto search_free;
         } else {
 
         }
 #line 2825
         return (-12);
       } else {
 
       }
 #line 2828
       goto search_free;
     } else {
 
     }
 #line 2831
     return (ret);
   } else {
 
   }
   {
 #line 2834
   ret = i915_gem_gtt_bind_object(obj);
   }
 #line 2835
   if (ret != 0) {
     {
 #line 2836
     i915_gem_object_put_pages_gtt(obj);
 #line 2837
     __cil_tmp64 = obj->gtt_space;
 #line 2837
     drm_mm_put_block(__cil_tmp64);
 #line 2838
     obj->gtt_space = (struct drm_mm_node *)0;
 #line 2840
     __cil_tmp65 = (bool )0;
 #line 2840
     tmp___0 = i915_gem_evict_everything(dev, __cil_tmp65);
     }
 #line 2840
     if (tmp___0 != 0) {
 #line 2841
       return (ret);
     } else {
 
     }
 #line 2843
     goto search_free;
   } else {
 
   }
   {
 #line 2846
   __cil_tmp66 = & obj->gtt_list;
 #line 2846
   __cil_tmp67 = & dev_priv->mm.gtt_list;
 #line 2846
   list_add_tail(__cil_tmp66, __cil_tmp67);
 #line 2847
   __cil_tmp68 = & obj->mm_list;
 #line 2847
   __cil_tmp69 = & dev_priv->mm.inactive_list;
 #line 2847
   list_add_tail(__cil_tmp68, __cil_tmp69);
 #line 2853
   __cil_tmp70 = obj->base.read_domains;
 #line 2853
   __cil_tmp71 = __cil_tmp70 & 4294967230U;
 #line 2853
   __cil_tmp72 = __cil_tmp71 != 0U;
 #line 2853
   __cil_tmp73 = (long )__cil_tmp72;
 #line 2853
   tmp___1 = __builtin_expect(__cil_tmp73, 0L);
   }
 #line 2853
   if (tmp___1 != 0L) {
 #line 2853
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (2853), "i" (12UL));
     ldv_39581: ;
 #line 2853
     goto ldv_39581;
   } else {
 
   }
   {
 #line 2854
   __cil_tmp74 = obj->base.write_domain;
 #line 2854
   __cil_tmp75 = __cil_tmp74 & 4294967230U;
 #line 2854
   __cil_tmp76 = __cil_tmp75 != 0U;
 #line 2854
   __cil_tmp77 = (long )__cil_tmp76;
 #line 2854
   tmp___2 = __builtin_expect(__cil_tmp77, 0L);
   }
 #line 2854
   if (tmp___2 != 0L) {
 #line 2854
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (2854), "i" (12UL));
     ldv_39582: ;
 #line 2854
     goto ldv_39582;
   } else {
 
   }
 #line 2856
   __cil_tmp78 = obj->gtt_space;
 #line 2856
   __cil_tmp79 = __cil_tmp78->start;
 #line 2856
   obj->gtt_offset = (uint32_t )__cil_tmp79;
   {
 #line 2858
   __cil_tmp80 = (unsigned long )fence_size;
 #line 2858
   __cil_tmp81 = obj->gtt_space;
 #line 2858
   __cil_tmp82 = __cil_tmp81->size;
 #line 2858
   if (__cil_tmp82 == __cil_tmp80) {
     {
 #line 2858
     __cil_tmp83 = fence_alignment - 1U;
 #line 2858
     __cil_tmp84 = (unsigned long )__cil_tmp83;
 #line 2858
     __cil_tmp85 = obj->gtt_space;
 #line 2858
     __cil_tmp86 = __cil_tmp85->start;
 #line 2858
     __cil_tmp87 = __cil_tmp86 & __cil_tmp84;
 #line 2858
     if (__cil_tmp87 == 0UL) {
 #line 2858
       tmp___3 = 1;
     } else {
 #line 2858
       tmp___3 = 0;
     }
     }
   } else {
 #line 2858
     tmp___3 = 0;
   }
   }
 #line 2858
   fenceable = (bool )tmp___3;
 #line 2862
   __cil_tmp88 = dev_priv->mm.gtt_mappable_end;
 #line 2862
   __cil_tmp89 = obj->base.size;
 #line 2862
   __cil_tmp90 = obj->gtt_offset;
 #line 2862
   __cil_tmp91 = (size_t )__cil_tmp90;
 #line 2862
   __cil_tmp92 = __cil_tmp91 + __cil_tmp89;
 #line 2862
   __cil_tmp93 = __cil_tmp92 <= __cil_tmp88;
 #line 2862
   mappable = (bool )__cil_tmp93;
 #line 2865
   if ((int )mappable) {
 #line 2865
     if ((int )fenceable) {
 #line 2865
       tmp___4 = 1;
     } else {
 #line 2865
       tmp___4 = 0;
     }
   } else {
 #line 2865
     tmp___4 = 0;
   }
   {
 #line 2865
   obj->map_and_fenceable = (unsigned char )tmp___4;
 #line 2867
   __cil_tmp94 = (int )map_and_fenceable;
 #line 2867
   __cil_tmp95 = (bool )__cil_tmp94;
 #line 2867
   trace_i915_gem_object_bind(obj, __cil_tmp95);
   }
 #line 2868
   return (0);
 }
 }
 #line 2872 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_clflush_object(struct drm_i915_gem_object *obj ) 
 { struct page **__cil_tmp2 ;
   unsigned long __cil_tmp3 ;
   struct page **__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   unsigned char *__cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   struct page **__cil_tmp10 ;
   size_t __cil_tmp11 ;
   size_t __cil_tmp12 ;
 
   {
   {
 #line 2878
   __cil_tmp2 = (struct page **)0;
 #line 2878
   __cil_tmp3 = (unsigned long )__cil_tmp2;
 #line 2878
   __cil_tmp4 = obj->pages;
 #line 2878
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 2878
   if (__cil_tmp5 == __cil_tmp3) {
 #line 2879
     return;
   } else {
 
   }
   }
   {
 #line 2889
   __cil_tmp6 = (unsigned char *)obj;
 #line 2889
   __cil_tmp7 = __cil_tmp6 + 226UL;
 #line 2889
   __cil_tmp8 = *__cil_tmp7;
 #line 2889
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 2889
   if (__cil_tmp9 != 0U) {
 #line 2890
     return;
   } else {
 
   }
   }
   {
 #line 2892
   trace_i915_gem_object_clflush(obj);
 #line 2894
   __cil_tmp10 = obj->pages;
 #line 2894
   __cil_tmp11 = obj->base.size;
 #line 2894
   __cil_tmp12 = __cil_tmp11 / 4096UL;
 #line 2894
   drm_clflush_pages(__cil_tmp10, __cil_tmp12);
   }
 #line 2895
   return;
 }
 }
 #line 2899 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj ) 
 { int tmp ;
   uint32_t __cil_tmp3 ;
   unsigned int __cil_tmp4 ;
   struct intel_ring_buffer *__cil_tmp5 ;
   uint32_t __cil_tmp6 ;
 
   {
   {
 #line 2901
   __cil_tmp3 = obj->base.write_domain;
 #line 2901
   __cil_tmp4 = __cil_tmp3 & 4294967230U;
 #line 2901
   if (__cil_tmp4 == 0U) {
 #line 2902
     return (0);
   } else {
 
   }
   }
   {
 #line 2905
   __cil_tmp5 = obj->ring;
 #line 2905
   __cil_tmp6 = obj->base.write_domain;
 #line 2905
   tmp = i915_gem_flush_ring(__cil_tmp5, 0U, __cil_tmp6);
   }
 #line 2905
   return (tmp);
 }
 }
 #line 2910 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj ) 
 { uint32_t old_write_domain ;
   uint32_t __cil_tmp3 ;
   uint32_t __cil_tmp4 ;
 
   {
   {
 #line 2914
   __cil_tmp3 = obj->base.write_domain;
 #line 2914
   if (__cil_tmp3 != 64U) {
 #line 2915
     return;
   } else {
 
   }
   }
   {
 #line 2925
   __asm__  volatile   ("sfence": : : "memory");
 #line 2927
   old_write_domain = obj->base.write_domain;
 #line 2928
   obj->base.write_domain = 0U;
 #line 2930
   __cil_tmp4 = obj->base.read_domains;
 #line 2930
   trace_i915_gem_object_change_domain(obj, __cil_tmp4, old_write_domain);
   }
 #line 2932
   return;
 }
 }
 #line 2937 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj ) 
 { uint32_t old_write_domain ;
   uint32_t __cil_tmp3 ;
   uint32_t __cil_tmp4 ;
 
   {
   {
 #line 2941
   __cil_tmp3 = obj->base.write_domain;
 #line 2941
   if (__cil_tmp3 != 1U) {
 #line 2942
     return;
   } else {
 
   }
   }
   {
 #line 2944
   i915_gem_clflush_object(obj);
 #line 2945
   intel_gtt_chipset_flush();
 #line 2946
   old_write_domain = obj->base.write_domain;
 #line 2947
   obj->base.write_domain = 0U;
 #line 2949
   __cil_tmp4 = obj->base.read_domains;
 #line 2949
   trace_i915_gem_object_change_domain(obj, __cil_tmp4, old_write_domain);
   }
 #line 2951
   return;
 }
 }
 #line 2961 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj , bool write ) 
 { uint32_t old_write_domain ;
   uint32_t old_read_domains ;
   int ret ;
   long tmp ;
   struct drm_mm_node *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_mm_node *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   unsigned char *__cil_tmp12 ;
   unsigned char *__cil_tmp13 ;
   unsigned char __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   uint32_t __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   long __cil_tmp19 ;
   uint32_t __cil_tmp20 ;
 
   {
   {
 #line 2967
   __cil_tmp7 = (struct drm_mm_node *)0;
 #line 2967
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 2967
   __cil_tmp9 = obj->gtt_space;
 #line 2967
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 2967
   if (__cil_tmp10 == __cil_tmp8) {
 #line 2968
     return (-22);
   } else {
 
   }
   }
   {
 #line 2970
   __cil_tmp11 = obj->base.write_domain;
 #line 2970
   if (__cil_tmp11 == 64U) {
 #line 2971
     return (0);
   } else {
 
   }
   }
   {
 #line 2973
   ret = i915_gem_object_flush_gpu_write_domain(obj);
   }
 #line 2974
   if (ret != 0) {
 #line 2975
     return (ret);
   } else {
 
   }
   {
 #line 2977
   __cil_tmp12 = (unsigned char *)obj;
 #line 2977
   __cil_tmp13 = __cil_tmp12 + 224UL;
 #line 2977
   __cil_tmp14 = *__cil_tmp13;
 #line 2977
   __cil_tmp15 = (unsigned int )__cil_tmp14;
 #line 2977
   if (__cil_tmp15 != 0U) {
 #line 2977
     goto _L;
   } else
 #line 2977
   if ((int )write) {
     _L: 
     {
 #line 2978
     ret = i915_gem_object_wait_rendering(obj);
     }
 #line 2979
     if (ret != 0) {
 #line 2980
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 2983
   i915_gem_object_flush_cpu_write_domain(obj);
 #line 2985
   old_write_domain = obj->base.write_domain;
 #line 2986
   old_read_domains = obj->base.read_domains;
 #line 2991
   __cil_tmp16 = obj->base.write_domain;
 #line 2991
   __cil_tmp17 = __cil_tmp16 & 4294967231U;
 #line 2991
   __cil_tmp18 = __cil_tmp17 != 0U;
 #line 2991
   __cil_tmp19 = (long )__cil_tmp18;
 #line 2991
   tmp = __builtin_expect(__cil_tmp19, 0L);
   }
 #line 2991
   if (tmp != 0L) {
 #line 2991
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (2991), "i" (12UL));
     ldv_39604: ;
 #line 2991
     goto ldv_39604;
   } else {
 
   }
 #line 2992
   __cil_tmp20 = obj->base.read_domains;
 #line 2992
   obj->base.read_domains = __cil_tmp20 | 64U;
 #line 2993
   if ((int )write) {
 #line 2994
     obj->base.read_domains = 64U;
 #line 2995
     obj->base.write_domain = 64U;
 #line 2996
     obj->dirty = (unsigned char)1;
   } else {
 
   }
   {
 #line 2999
   trace_i915_gem_object_change_domain(obj, old_read_domains, old_write_domain);
   }
 #line 3003
   return (0);
 }
 }
 #line 3011 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj , struct intel_ring_buffer *pipelined ) 
 { uint32_t old_read_domains ;
   int ret ;
   struct drm_mm_node *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   struct drm_mm_node *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   struct intel_ring_buffer *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   uint32_t __cil_tmp12 ;
   uint32_t __cil_tmp13 ;
 
   {
   {
 #line 3018
   __cil_tmp5 = (struct drm_mm_node *)0;
 #line 3018
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 3018
   __cil_tmp7 = obj->gtt_space;
 #line 3018
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 3018
   if (__cil_tmp8 == __cil_tmp6) {
 #line 3019
     return (-22);
   } else {
 
   }
   }
   {
 #line 3021
   ret = i915_gem_object_flush_gpu_write_domain(obj);
   }
 #line 3022
   if (ret != 0) {
 #line 3023
     return (ret);
   } else {
 
   }
   {
 #line 3027
   __cil_tmp9 = (unsigned long )pipelined;
 #line 3027
   __cil_tmp10 = obj->ring;
 #line 3027
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3027
   if (__cil_tmp11 != __cil_tmp9) {
     {
 #line 3028
     ret = i915_gem_object_wait_rendering(obj);
     }
 #line 3029
     if (ret != 0) {
 #line 3030
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 3033
   i915_gem_object_flush_cpu_write_domain(obj);
 #line 3035
   old_read_domains = obj->base.read_domains;
 #line 3036
   __cil_tmp12 = obj->base.read_domains;
 #line 3036
   obj->base.read_domains = __cil_tmp12 | 64U;
 #line 3038
   __cil_tmp13 = obj->base.write_domain;
 #line 3038
   trace_i915_gem_object_change_domain(obj, old_read_domains, __cil_tmp13);
   }
 #line 3042
   return (0);
 }
 }
 #line 3046 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj ) 
 { int ret ;
   int tmp ;
   unsigned char *__cil_tmp4 ;
   unsigned char *__cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   uint32_t __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   struct intel_ring_buffer *__cil_tmp10 ;
   uint32_t __cil_tmp11 ;
 
   {
   {
 #line 3050
   __cil_tmp4 = (unsigned char *)obj;
 #line 3050
   __cil_tmp5 = __cil_tmp4 + 224UL;
 #line 3050
   __cil_tmp6 = *__cil_tmp5;
 #line 3050
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 3050
   if (__cil_tmp7 == 0U) {
 #line 3051
     return (0);
   } else {
 
   }
   }
   {
 #line 3053
   __cil_tmp8 = obj->base.write_domain;
 #line 3053
   __cil_tmp9 = __cil_tmp8 & 4294967230U;
 #line 3053
   if (__cil_tmp9 != 0U) {
     {
 #line 3054
     __cil_tmp10 = obj->ring;
 #line 3054
     __cil_tmp11 = obj->base.write_domain;
 #line 3054
     ret = i915_gem_flush_ring(__cil_tmp10, 0U, __cil_tmp11);
     }
 #line 3055
     if (ret != 0) {
 #line 3056
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 3059
   tmp = i915_gem_object_wait_rendering(obj);
   }
 #line 3059
   return (tmp);
 }
 }
 #line 3069 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj , bool write ) 
 { uint32_t old_write_domain ;
   uint32_t old_read_domains ;
   int ret ;
   long tmp ;
   uint32_t __cil_tmp7 ;
   uint32_t __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   int __cil_tmp13 ;
   long __cil_tmp14 ;
 
   {
   {
 #line 3074
   __cil_tmp7 = obj->base.write_domain;
 #line 3074
   if (__cil_tmp7 == 1U) {
 #line 3075
     return (0);
   } else {
 
   }
   }
   {
 #line 3077
   ret = i915_gem_object_flush_gpu_write_domain(obj);
   }
 #line 3078
   if (ret != 0) {
 #line 3079
     return (ret);
   } else {
 
   }
   {
 #line 3081
   ret = i915_gem_object_wait_rendering(obj);
   }
 #line 3082
   if (ret != 0) {
 #line 3083
     return (ret);
   } else {
 
   }
   {
 #line 3085
   i915_gem_object_flush_gtt_write_domain(obj);
 #line 3090
   i915_gem_object_set_to_full_cpu_read_domain(obj);
 #line 3092
   old_write_domain = obj->base.write_domain;
 #line 3093
   old_read_domains = obj->base.read_domains;
   }
   {
 #line 3096
   __cil_tmp8 = obj->base.read_domains;
 #line 3096
   __cil_tmp9 = __cil_tmp8 & 1U;
 #line 3096
   if (__cil_tmp9 == 0U) {
     {
 #line 3097
     i915_gem_clflush_object(obj);
 #line 3099
     __cil_tmp10 = obj->base.read_domains;
 #line 3099
     obj->base.read_domains = __cil_tmp10 | 1U;
     }
   } else {
 
   }
   }
   {
 #line 3105
   __cil_tmp11 = obj->base.write_domain;
 #line 3105
   __cil_tmp12 = __cil_tmp11 & 4294967294U;
 #line 3105
   __cil_tmp13 = __cil_tmp12 != 0U;
 #line 3105
   __cil_tmp14 = (long )__cil_tmp13;
 #line 3105
   tmp = __builtin_expect(__cil_tmp14, 0L);
   }
 #line 3105
   if (tmp != 0L) {
 #line 3105
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3105), "i" (12UL));
     ldv_39622: ;
 #line 3105
     goto ldv_39622;
   } else {
 
   }
 #line 3110
   if ((int )write) {
 #line 3111
     obj->base.read_domains = 1U;
 #line 3112
     obj->base.write_domain = 1U;
   } else {
 
   }
   {
 #line 3115
   trace_i915_gem_object_change_domain(obj, old_read_domains, old_write_domain);
   }
 #line 3119
   return (0);
 }
 }
 #line 3129 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj ) 
 { int i ;
   uint8_t *__cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   uint8_t *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   uint32_t __cil_tmp7 ;
   int __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   uint8_t *__cil_tmp10 ;
   uint8_t *__cil_tmp11 ;
   uint8_t __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct page **__cil_tmp15 ;
   struct page **__cil_tmp16 ;
   size_t __cil_tmp17 ;
   size_t __cil_tmp18 ;
   size_t __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   uint8_t *__cil_tmp21 ;
   void const   *__cil_tmp22 ;
 
   {
   {
 #line 3131
   __cil_tmp3 = (uint8_t *)0;
 #line 3131
   __cil_tmp4 = (unsigned long )__cil_tmp3;
 #line 3131
   __cil_tmp5 = obj->page_cpu_valid;
 #line 3131
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 3131
   if (__cil_tmp6 == __cil_tmp4) {
 #line 3132
     return;
   } else {
 
   }
   }
   {
 #line 3136
   __cil_tmp7 = obj->base.read_domains;
 #line 3136
   __cil_tmp8 = (int )__cil_tmp7;
 #line 3136
   if (__cil_tmp8 & 1) {
 #line 3139
     i = 0;
 #line 3139
     goto ldv_39629;
     ldv_39628: ;
     {
 #line 3140
     __cil_tmp9 = (unsigned long )i;
 #line 3140
     __cil_tmp10 = obj->page_cpu_valid;
 #line 3140
     __cil_tmp11 = __cil_tmp10 + __cil_tmp9;
 #line 3140
     __cil_tmp12 = *__cil_tmp11;
 #line 3140
     __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 3140
     if (__cil_tmp13 != 0U) {
 #line 3141
       goto ldv_39627;
     } else {
 
     }
     }
     {
 #line 3142
     __cil_tmp14 = (unsigned long )i;
 #line 3142
     __cil_tmp15 = obj->pages;
 #line 3142
     __cil_tmp16 = __cil_tmp15 + __cil_tmp14;
 #line 3142
     drm_clflush_pages(__cil_tmp16, 1UL);
     }
     ldv_39627: 
 #line 3139
     i = i + 1;
     ldv_39629: ;
     {
 #line 3139
     __cil_tmp17 = obj->base.size;
 #line 3139
     __cil_tmp18 = __cil_tmp17 - 1UL;
 #line 3139
     __cil_tmp19 = __cil_tmp18 / 4096UL;
 #line 3139
     __cil_tmp20 = (unsigned long )i;
 #line 3139
     if (__cil_tmp20 <= __cil_tmp19) {
 #line 3140
       goto ldv_39628;
     } else {
 #line 3142
       goto ldv_39630;
     }
     }
     ldv_39630: ;
   } else {
 
   }
   }
   {
 #line 3149
   __cil_tmp21 = obj->page_cpu_valid;
 #line 3149
   __cil_tmp22 = (void const   *)__cil_tmp21;
 #line 3149
   kfree(__cil_tmp22);
 #line 3150
   obj->page_cpu_valid = (uint8_t *)0;
   }
 #line 3151
   return;
 }
 }
 #line 3166 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj ,
                                                      uint64_t offset , uint64_t size ) 
 { uint32_t old_read_domains ;
   int i ;
   int ret ;
   int tmp ;
   void *tmp___0 ;
   long tmp___1 ;
   size_t __cil_tmp10 ;
   unsigned long long __cil_tmp11 ;
   bool __cil_tmp12 ;
   uint8_t *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   uint8_t *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   uint32_t __cil_tmp17 ;
   int __cil_tmp18 ;
   uint8_t *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   uint8_t *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   size_t __cil_tmp23 ;
   size_t __cil_tmp24 ;
   uint8_t *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   uint8_t *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   uint32_t __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   uint8_t *__cil_tmp31 ;
   void *__cil_tmp32 ;
   size_t __cil_tmp33 ;
   size_t __cil_tmp34 ;
   uint64_t __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   uint8_t *__cil_tmp37 ;
   uint8_t *__cil_tmp38 ;
   uint8_t __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   struct page **__cil_tmp42 ;
   struct page **__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   uint8_t *__cil_tmp45 ;
   uint8_t *__cil_tmp46 ;
   uint64_t __cil_tmp47 ;
   uint64_t __cil_tmp48 ;
   uint64_t __cil_tmp49 ;
   unsigned long long __cil_tmp50 ;
   uint32_t __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   int __cil_tmp53 ;
   long __cil_tmp54 ;
   uint32_t __cil_tmp55 ;
   uint32_t __cil_tmp56 ;
 
   {
 #line 3172
   if (offset == 0ULL) {
     {
 #line 3172
     __cil_tmp10 = obj->base.size;
 #line 3172
     __cil_tmp11 = (unsigned long long )__cil_tmp10;
 #line 3172
     if (__cil_tmp11 == size) {
       {
 #line 3173
       __cil_tmp12 = (bool )0;
 #line 3173
       tmp = i915_gem_object_set_to_cpu_domain(obj, __cil_tmp12);
       }
 #line 3173
       return (tmp);
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 3175
   ret = i915_gem_object_flush_gpu_write_domain(obj);
   }
 #line 3176
   if (ret != 0) {
 #line 3177
     return (ret);
   } else {
 
   }
   {
 #line 3179
   ret = i915_gem_object_wait_rendering(obj);
   }
 #line 3180
   if (ret != 0) {
 #line 3181
     return (ret);
   } else {
 
   }
   {
 #line 3183
   i915_gem_object_flush_gtt_write_domain(obj);
   }
   {
 #line 3186
   __cil_tmp13 = (uint8_t *)0;
 #line 3186
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 3186
   __cil_tmp15 = obj->page_cpu_valid;
 #line 3186
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 3186
   if (__cil_tmp16 == __cil_tmp14) {
     {
 #line 3186
     __cil_tmp17 = obj->base.read_domains;
 #line 3186
     __cil_tmp18 = (int )__cil_tmp17;
 #line 3186
     if (__cil_tmp18 & 1) {
 #line 3188
       return (0);
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 3193
   __cil_tmp19 = (uint8_t *)0;
 #line 3193
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 3193
   __cil_tmp21 = obj->page_cpu_valid;
 #line 3193
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 3193
   if (__cil_tmp22 == __cil_tmp20) {
     {
 #line 3194
     __cil_tmp23 = obj->base.size;
 #line 3194
     __cil_tmp24 = __cil_tmp23 / 4096UL;
 #line 3194
     tmp___0 = kzalloc(__cil_tmp24, 208U);
 #line 3194
     obj->page_cpu_valid = (uint8_t *)tmp___0;
     }
     {
 #line 3196
     __cil_tmp25 = (uint8_t *)0;
 #line 3196
     __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 3196
     __cil_tmp27 = obj->page_cpu_valid;
 #line 3196
     __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 3196
     if (__cil_tmp28 == __cil_tmp26) {
 #line 3197
       return (-12);
     } else {
 
     }
     }
   } else {
     {
 #line 3198
     __cil_tmp29 = obj->base.read_domains;
 #line 3198
     __cil_tmp30 = __cil_tmp29 & 1U;
 #line 3198
     if (__cil_tmp30 == 0U) {
       {
 #line 3199
       __cil_tmp31 = obj->page_cpu_valid;
 #line 3199
       __cil_tmp32 = (void *)__cil_tmp31;
 #line 3199
       __cil_tmp33 = obj->base.size;
 #line 3199
       __cil_tmp34 = __cil_tmp33 / 4096UL;
 #line 3199
       memset(__cil_tmp32, 0, __cil_tmp34);
       }
     } else {
 
     }
     }
   }
   }
 #line 3204
   __cil_tmp35 = offset / 4096ULL;
 #line 3204
   i = (int )__cil_tmp35;
 #line 3204
   goto ldv_39641;
   ldv_39640: ;
   {
 #line 3206
   __cil_tmp36 = (unsigned long )i;
 #line 3206
   __cil_tmp37 = obj->page_cpu_valid;
 #line 3206
   __cil_tmp38 = __cil_tmp37 + __cil_tmp36;
 #line 3206
   __cil_tmp39 = *__cil_tmp38;
 #line 3206
   __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 3206
   if (__cil_tmp40 != 0U) {
 #line 3207
     goto ldv_39639;
   } else {
 
   }
   }
   {
 #line 3209
   __cil_tmp41 = (unsigned long )i;
 #line 3209
   __cil_tmp42 = obj->pages;
 #line 3209
   __cil_tmp43 = __cil_tmp42 + __cil_tmp41;
 #line 3209
   drm_clflush_pages(__cil_tmp43, 1UL);
 #line 3211
   __cil_tmp44 = (unsigned long )i;
 #line 3211
   __cil_tmp45 = obj->page_cpu_valid;
 #line 3211
   __cil_tmp46 = __cil_tmp45 + __cil_tmp44;
 #line 3211
   *__cil_tmp46 = (uint8_t )1U;
   }
   ldv_39639: 
 #line 3205
   i = i + 1;
   ldv_39641: ;
   {
 #line 3204
   __cil_tmp47 = offset + size;
 #line 3204
   __cil_tmp48 = __cil_tmp47 - 1ULL;
 #line 3204
   __cil_tmp49 = __cil_tmp48 / 4096ULL;
 #line 3204
   __cil_tmp50 = (unsigned long long )i;
 #line 3204
   if (__cil_tmp50 <= __cil_tmp49) {
 #line 3205
     goto ldv_39640;
   } else {
 #line 3207
     goto ldv_39642;
   }
   }
   ldv_39642: 
   {
 #line 3217
   __cil_tmp51 = obj->base.write_domain;
 #line 3217
   __cil_tmp52 = __cil_tmp51 & 4294967294U;
 #line 3217
   __cil_tmp53 = __cil_tmp52 != 0U;
 #line 3217
   __cil_tmp54 = (long )__cil_tmp53;
 #line 3217
   tmp___1 = __builtin_expect(__cil_tmp54, 0L);
   }
 #line 3217
   if (tmp___1 != 0L) {
 #line 3217
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3217), "i" (12UL));
     ldv_39643: ;
 #line 3217
     goto ldv_39643;
   } else {
 
   }
   {
 #line 3219
   old_read_domains = obj->base.read_domains;
 #line 3220
   __cil_tmp55 = obj->base.read_domains;
 #line 3220
   obj->base.read_domains = __cil_tmp55 | 1U;
 #line 3222
   __cil_tmp56 = obj->base.write_domain;
 #line 3222
   trace_i915_gem_object_change_domain(obj, old_read_domains, __cil_tmp56);
   }
 #line 3226
   return (0);
 }
 }
 #line 3240 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_ring_throttle(struct drm_device *dev , struct drm_file *file ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_file_private *file_priv ;
   unsigned long recent_enough ;
   unsigned long tmp ;
   struct drm_i915_gem_request *request ;
   struct intel_ring_buffer *ring ;
   u32 seqno ;
   int ret ;
   int tmp___0 ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   int __ret ;
   wait_queue_t __wait ;
   struct task_struct *tmp___1 ;
   u32 tmp___2 ;
   bool tmp___3 ;
   int tmp___4 ;
   struct task_struct *tmp___5 ;
   int tmp___6 ;
   u32 tmp___7 ;
   bool tmp___8 ;
   int tmp___9 ;
   int tmp___10 ;
   int tmp___11 ;
   bool tmp___12 ;
   u32 tmp___13 ;
   bool tmp___14 ;
   int tmp___15 ;
   void *__cil_tmp31 ;
   void *__cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   atomic_t *__cil_tmp36 ;
   atomic_t const   *__cil_tmp37 ;
   struct spinlock *__cil_tmp38 ;
   struct list_head *__cil_tmp39 ;
   struct drm_i915_gem_request *__cil_tmp40 ;
   long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   long __cil_tmp43 ;
   long __cil_tmp44 ;
   struct list_head *__cil_tmp45 ;
   struct drm_i915_gem_request *__cil_tmp46 ;
   struct list_head *__cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   struct list_head *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   struct spinlock *__cil_tmp51 ;
   u32 (*__cil_tmp52)(struct intel_ring_buffer * ) ;
   bool (*__cil_tmp53)(struct intel_ring_buffer * ) ;
   u32 (*__cil_tmp54)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp55 ;
   atomic_t const   *__cil_tmp56 ;
   wait_queue_head_t *__cil_tmp57 ;
   u32 (*__cil_tmp58)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp59 ;
   atomic_t const   *__cil_tmp60 ;
   wait_queue_head_t *__cil_tmp61 ;
   void (*__cil_tmp62)(struct intel_ring_buffer * ) ;
   atomic_t *__cil_tmp63 ;
   atomic_t const   *__cil_tmp64 ;
   struct workqueue_struct *__cil_tmp65 ;
   struct delayed_work *__cil_tmp66 ;
 
   {
   {
 #line 3242
   __cil_tmp31 = dev->dev_private;
 #line 3242
   dev_priv = (struct drm_i915_private *)__cil_tmp31;
 #line 3243
   __cil_tmp32 = file->driver_priv;
 #line 3243
   file_priv = (struct drm_i915_file_private *)__cil_tmp32;
 #line 3244
   __cil_tmp33 = (unsigned int const   )20U;
 #line 3244
   __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 3244
   tmp = msecs_to_jiffies(__cil_tmp34);
 #line 3244
   __cil_tmp35 = (unsigned long )jiffies;
 #line 3244
   recent_enough = __cil_tmp35 - tmp;
 #line 3246
   ring = (struct intel_ring_buffer *)0;
 #line 3247
   seqno = 0U;
 #line 3250
   __cil_tmp36 = & dev_priv->mm.wedged;
 #line 3250
   __cil_tmp37 = (atomic_t const   *)__cil_tmp36;
 #line 3250
   tmp___0 = atomic_read(__cil_tmp37);
   }
 #line 3250
   if (tmp___0 != 0) {
 #line 3251
     return (-5);
   } else {
 
   }
   {
 #line 3253
   __cil_tmp38 = & file_priv->mm.lock;
 #line 3253
   spin_lock(__cil_tmp38);
 #line 3254
   __cil_tmp39 = file_priv->mm.request_list.next;
 #line 3254
   __mptr = (struct list_head  const  *)__cil_tmp39;
 #line 3254
   __cil_tmp40 = (struct drm_i915_gem_request *)__mptr;
 #line 3254
   request = __cil_tmp40 + 1152921504606846928UL;
   }
 #line 3254
   goto ldv_39667;
   ldv_39666: ;
   {
 #line 3255
   __cil_tmp41 = (long )recent_enough;
 #line 3255
   __cil_tmp42 = request->emitted_jiffies;
 #line 3255
   __cil_tmp43 = (long )__cil_tmp42;
 #line 3255
   __cil_tmp44 = __cil_tmp43 - __cil_tmp41;
 #line 3255
   if (__cil_tmp44 >= 0L) {
 #line 3256
     goto ldv_39665;
   } else {
 
   }
   }
 #line 3258
   ring = request->ring;
 #line 3259
   seqno = request->seqno;
 #line 3254
   __cil_tmp45 = request->client_list.next;
 #line 3254
   __mptr___0 = (struct list_head  const  *)__cil_tmp45;
 #line 3254
   __cil_tmp46 = (struct drm_i915_gem_request *)__mptr___0;
 #line 3254
   request = __cil_tmp46 + 1152921504606846928UL;
   ldv_39667: ;
   {
 #line 3254
   __cil_tmp47 = & file_priv->mm.request_list;
 #line 3254
   __cil_tmp48 = (unsigned long )__cil_tmp47;
 #line 3254
   __cil_tmp49 = & request->client_list;
 #line 3254
   __cil_tmp50 = (unsigned long )__cil_tmp49;
 #line 3254
   if (__cil_tmp50 != __cil_tmp48) {
 #line 3255
     goto ldv_39666;
   } else {
 #line 3257
     goto ldv_39665;
   }
   }
   ldv_39665: 
   {
 #line 3261
   __cil_tmp51 = & file_priv->mm.lock;
 #line 3261
   spin_unlock(__cil_tmp51);
   }
 #line 3263
   if (seqno == 0U) {
 #line 3264
     return (0);
   } else {
 
   }
   {
 #line 3266
   ret = 0;
 #line 3267
   __cil_tmp52 = ring->get_seqno;
 #line 3267
   tmp___13 = (*__cil_tmp52)(ring);
 #line 3267
   tmp___14 = i915_seqno_passed(tmp___13, seqno);
   }
 #line 3267
   if (tmp___14) {
 #line 3267
     tmp___15 = 0;
   } else {
 #line 3267
     tmp___15 = 1;
   }
 #line 3267
   if (tmp___15) {
     {
 #line 3273
     __cil_tmp53 = ring->irq_get;
 #line 3273
     tmp___12 = (*__cil_tmp53)(ring);
     }
 #line 3273
     if ((int )tmp___12) {
       {
 #line 3274
       __ret = 0;
 #line 3274
       __cil_tmp54 = ring->get_seqno;
 #line 3274
       tmp___7 = (*__cil_tmp54)(ring);
 #line 3274
       tmp___8 = i915_seqno_passed(tmp___7, seqno);
       }
 #line 3274
       if (tmp___8) {
 #line 3274
         tmp___9 = 0;
       } else {
 #line 3274
         tmp___9 = 1;
       }
 #line 3274
       if (tmp___9) {
         {
 #line 3274
         __cil_tmp55 = & dev_priv->mm.wedged;
 #line 3274
         __cil_tmp56 = (atomic_t const   *)__cil_tmp55;
 #line 3274
         tmp___10 = atomic_read(__cil_tmp56);
         }
 #line 3274
         if (tmp___10 == 0) {
           {
 #line 3274
           tmp___1 = get_current();
 #line 3274
           __wait.flags = 0U;
 #line 3274
           __wait.private = (void *)tmp___1;
 #line 3274
           __wait.func = & autoremove_wake_function;
 #line 3274
           __wait.task_list.next = & __wait.task_list;
 #line 3274
           __wait.task_list.prev = & __wait.task_list;
           }
           ldv_39672: 
           {
 #line 3274
           __cil_tmp57 = & ring->irq_queue;
 #line 3274
           prepare_to_wait(__cil_tmp57, & __wait, 1);
 #line 3274
           __cil_tmp58 = ring->get_seqno;
 #line 3274
           tmp___2 = (*__cil_tmp58)(ring);
 #line 3274
           tmp___3 = i915_seqno_passed(tmp___2, seqno);
           }
 #line 3274
           if ((int )tmp___3) {
 #line 3274
             goto ldv_39670;
           } else {
             {
 #line 3274
             __cil_tmp59 = & dev_priv->mm.wedged;
 #line 3274
             __cil_tmp60 = (atomic_t const   *)__cil_tmp59;
 #line 3274
             tmp___4 = atomic_read(__cil_tmp60);
             }
 #line 3274
             if (tmp___4 != 0) {
 #line 3274
               goto ldv_39670;
             } else {
 
             }
           }
           {
 #line 3274
           tmp___5 = get_current();
 #line 3274
           tmp___6 = signal_pending(tmp___5);
           }
 #line 3274
           if (tmp___6 == 0) {
             {
 #line 3274
             schedule();
             }
 #line 3274
             goto ldv_39671;
           } else {
 
           }
 #line 3274
           __ret = -512;
 #line 3274
           goto ldv_39670;
           ldv_39671: ;
 #line 3274
           goto ldv_39672;
           ldv_39670: 
           {
 #line 3274
           __cil_tmp61 = & ring->irq_queue;
 #line 3274
           finish_wait(__cil_tmp61, & __wait);
           }
         } else {
 
         }
       } else {
 
       }
       {
 #line 3274
       ret = __ret;
 #line 3277
       __cil_tmp62 = ring->irq_put;
 #line 3277
       (*__cil_tmp62)(ring);
       }
 #line 3279
       if (ret == 0) {
         {
 #line 3279
         __cil_tmp63 = & dev_priv->mm.wedged;
 #line 3279
         __cil_tmp64 = (atomic_t const   *)__cil_tmp63;
 #line 3279
         tmp___11 = atomic_read(__cil_tmp64);
         }
 #line 3279
         if (tmp___11 != 0) {
 #line 3280
           ret = -5;
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
 #line 3284
   if (ret == 0) {
     {
 #line 3285
     __cil_tmp65 = dev_priv->wq;
 #line 3285
     __cil_tmp66 = & dev_priv->mm.retire_work;
 #line 3285
     queue_delayed_work(__cil_tmp65, __cil_tmp66, 0UL);
     }
   } else {
 
   }
 #line 3287
   return (ret);
 }
 }
 #line 3291 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_object_pin(struct drm_i915_gem_object *obj , uint32_t alignment , bool map_and_fenceable ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   int ret ;
   long tmp ;
   int __ret_warn_on ;
   long tmp___0 ;
   int __ret_warn_on___0 ;
   long tmp___1 ;
   unsigned char tmp___2 ;
   int __ret_warn_on___1 ;
   long tmp___3 ;
   void *__cil_tmp15 ;
   unsigned int *__cil_tmp16 ;
   unsigned int *__cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   long __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   long __cil_tmp26 ;
   struct drm_mm_node *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_mm_node *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   uint32_t __cil_tmp31 ;
   uint32_t __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned char *__cil_tmp34 ;
   unsigned char *__cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned int *__cil_tmp38 ;
   unsigned int *__cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   int __cil_tmp41 ;
   long __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   uint32_t __cil_tmp45 ;
   int __cil_tmp46 ;
   unsigned char __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   long __cil_tmp50 ;
   struct drm_mm_node *__cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   struct drm_mm_node *__cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   int __cil_tmp55 ;
   bool __cil_tmp56 ;
   unsigned char __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned char *__cil_tmp61 ;
   unsigned char *__cil_tmp62 ;
   unsigned char __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   struct list_head *__cil_tmp65 ;
   struct list_head *__cil_tmp66 ;
   unsigned char __cil_tmp67 ;
   int __cil_tmp68 ;
   unsigned char __cil_tmp69 ;
   int __cil_tmp70 ;
   int __cil_tmp71 ;
   int __cil_tmp72 ;
   long __cil_tmp73 ;
   int __cil_tmp74 ;
   int __cil_tmp75 ;
   int __cil_tmp76 ;
   long __cil_tmp77 ;
 
   {
   {
 #line 3295
   dev = obj->base.dev;
 #line 3296
   __cil_tmp15 = dev->dev_private;
 #line 3296
   dev_priv = (struct drm_i915_private *)__cil_tmp15;
 #line 3299
   __cil_tmp16 = (unsigned int *)obj;
 #line 3299
   __cil_tmp17 = __cil_tmp16 + 56UL;
 #line 3299
   __cil_tmp18 = *__cil_tmp17;
 #line 3299
   __cil_tmp19 = __cil_tmp18 == 122880U;
 #line 3299
   __cil_tmp20 = (long )__cil_tmp19;
 #line 3299
   tmp = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 3299
   if (tmp != 0L) {
 #line 3299
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3299), "i" (12UL));
     ldv_39682: ;
 #line 3299
     goto ldv_39682;
   } else {
 
   }
   {
 #line 3300
   __ret_warn_on = 0;
 #line 3300
   __cil_tmp21 = __ret_warn_on != 0;
 #line 3300
   __cil_tmp22 = (long )__cil_tmp21;
 #line 3300
   tmp___0 = __builtin_expect(__cil_tmp22, 0L);
   }
 #line 3300
   if (tmp___0 != 0L) {
     {
 #line 3300
     __cil_tmp23 = (int const   )3300;
 #line 3300
     __cil_tmp24 = (int )__cil_tmp23;
 #line 3300
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp24);
     }
   } else {
 
   }
   {
 #line 3300
   __cil_tmp25 = __ret_warn_on != 0;
 #line 3300
   __cil_tmp26 = (long )__cil_tmp25;
 #line 3300
   __builtin_expect(__cil_tmp26, 0L);
   }
   {
 #line 3302
   __cil_tmp27 = (struct drm_mm_node *)0;
 #line 3302
   __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 3302
   __cil_tmp29 = obj->gtt_space;
 #line 3302
   __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 3302
   if (__cil_tmp30 != __cil_tmp28) {
 #line 3303
     if (alignment != 0U) {
       {
 #line 3303
       __cil_tmp31 = alignment - 1U;
 #line 3303
       __cil_tmp32 = obj->gtt_offset;
 #line 3303
       __cil_tmp33 = __cil_tmp32 & __cil_tmp31;
 #line 3303
       if (__cil_tmp33 != 0U) {
 #line 3303
         goto _L;
       } else {
 #line 3303
         goto _L___0;
       }
       }
     } else
     _L___0: 
 #line 3303
     if ((int )map_and_fenceable) {
       {
 #line 3303
       __cil_tmp34 = (unsigned char *)obj;
 #line 3303
       __cil_tmp35 = __cil_tmp34 + 226UL;
 #line 3303
       __cil_tmp36 = *__cil_tmp35;
 #line 3303
       __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 3303
       if (__cil_tmp37 == 0U) {
         _L: 
         {
 #line 3305
         __cil_tmp38 = (unsigned int *)obj;
 #line 3305
         __cil_tmp39 = __cil_tmp38 + 56UL;
 #line 3305
         __cil_tmp40 = *__cil_tmp39;
 #line 3305
         __ret_warn_on___0 = __cil_tmp40 != 0U;
 #line 3305
         __cil_tmp41 = __ret_warn_on___0 != 0;
 #line 3305
         __cil_tmp42 = (long )__cil_tmp41;
 #line 3305
         tmp___1 = __builtin_expect(__cil_tmp42, 0L);
         }
 #line 3305
         if (tmp___1 != 0L) {
           {
 #line 3305
           __cil_tmp43 = (int const   )3311;
 #line 3305
           __cil_tmp44 = (int )__cil_tmp43;
 #line 3305
           __cil_tmp45 = obj->gtt_offset;
 #line 3305
           __cil_tmp46 = (int )map_and_fenceable;
 #line 3305
           __cil_tmp47 = obj->map_and_fenceable;
 #line 3305
           __cil_tmp48 = (int )__cil_tmp47;
 #line 3305
           warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                             __cil_tmp44, "bo is already pinned with incorrect alignment: offset=%x, req.alignment=%x, req.map_and_fenceable=%d, obj->map_and_fenceable=%d\n",
                             __cil_tmp45, alignment, __cil_tmp46, __cil_tmp48);
           }
         } else {
 
         }
         {
 #line 3305
         __cil_tmp49 = __ret_warn_on___0 != 0;
 #line 3305
         __cil_tmp50 = (long )__cil_tmp49;
 #line 3305
         __builtin_expect(__cil_tmp50, 0L);
 #line 3312
         ret = i915_gem_object_unbind(obj);
         }
 #line 3313
         if (ret != 0) {
 #line 3314
           return (ret);
         } else {
 
         }
       } else {
 
       }
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 3318
   __cil_tmp51 = (struct drm_mm_node *)0;
 #line 3318
   __cil_tmp52 = (unsigned long )__cil_tmp51;
 #line 3318
   __cil_tmp53 = obj->gtt_space;
 #line 3318
   __cil_tmp54 = (unsigned long )__cil_tmp53;
 #line 3318
   if (__cil_tmp54 == __cil_tmp52) {
     {
 #line 3319
     __cil_tmp55 = (int )map_and_fenceable;
 #line 3319
     __cil_tmp56 = (bool )__cil_tmp55;
 #line 3319
     ret = i915_gem_object_bind_to_gtt(obj, alignment, __cil_tmp56);
     }
 #line 3321
     if (ret != 0) {
 #line 3322
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
 #line 3325
   tmp___2 = obj->pin_count;
 #line 3325
   __cil_tmp57 = obj->pin_count;
 #line 3325
   __cil_tmp58 = (int )__cil_tmp57;
 #line 3325
   __cil_tmp59 = __cil_tmp58 + 1;
 #line 3325
   obj->pin_count = (unsigned char )__cil_tmp59;
   {
 #line 3325
   __cil_tmp60 = (unsigned int )tmp___2;
 #line 3325
   if (__cil_tmp60 == 0U) {
     {
 #line 3326
     __cil_tmp61 = (unsigned char *)obj;
 #line 3326
     __cil_tmp62 = __cil_tmp61 + 224UL;
 #line 3326
     __cil_tmp63 = *__cil_tmp62;
 #line 3326
     __cil_tmp64 = (unsigned int )__cil_tmp63;
 #line 3326
     if (__cil_tmp64 == 0U) {
       {
 #line 3327
       __cil_tmp65 = & obj->mm_list;
 #line 3327
       __cil_tmp66 = & dev_priv->mm.pinned_list;
 #line 3327
       list_move_tail(__cil_tmp65, __cil_tmp66);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 3330
   __cil_tmp67 = (unsigned char )map_and_fenceable;
 #line 3330
   __cil_tmp68 = (int )__cil_tmp67;
 #line 3330
   __cil_tmp69 = obj->pin_mappable;
 #line 3330
   __cil_tmp70 = (int )__cil_tmp69;
 #line 3330
   __cil_tmp71 = __cil_tmp70 | __cil_tmp68;
 #line 3330
   obj->pin_mappable = (unsigned char )__cil_tmp71;
 #line 3332
   __ret_warn_on___1 = 0;
 #line 3332
   __cil_tmp72 = __ret_warn_on___1 != 0;
 #line 3332
   __cil_tmp73 = (long )__cil_tmp72;
 #line 3332
   tmp___3 = __builtin_expect(__cil_tmp73, 0L);
   }
 #line 3332
   if (tmp___3 != 0L) {
     {
 #line 3332
     __cil_tmp74 = (int const   )3332;
 #line 3332
     __cil_tmp75 = (int )__cil_tmp74;
 #line 3332
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp75);
     }
   } else {
 
   }
   {
 #line 3332
   __cil_tmp76 = __ret_warn_on___1 != 0;
 #line 3332
   __cil_tmp77 = (long )__cil_tmp76;
 #line 3332
   __builtin_expect(__cil_tmp77, 0L);
   }
 #line 3333
   return (0);
 }
 }
 #line 3337 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_object_unpin(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int __ret_warn_on ;
   long tmp ;
   long tmp___0 ;
   long tmp___1 ;
   int __ret_warn_on___0 ;
   long tmp___2 ;
   void *__cil_tmp10 ;
   int __cil_tmp11 ;
   long __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   long __cil_tmp16 ;
   unsigned int *__cil_tmp17 ;
   unsigned int *__cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   int __cil_tmp20 ;
   long __cil_tmp21 ;
   struct drm_mm_node *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct drm_mm_node *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   int __cil_tmp26 ;
   long __cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   unsigned char __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned char *__cil_tmp33 ;
   unsigned char *__cil_tmp34 ;
   unsigned char __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   struct list_head *__cil_tmp37 ;
   struct list_head *__cil_tmp38 ;
   int __cil_tmp39 ;
   long __cil_tmp40 ;
   int __cil_tmp41 ;
   int __cil_tmp42 ;
   int __cil_tmp43 ;
   long __cil_tmp44 ;
 
   {
   {
 #line 3339
   dev = obj->base.dev;
 #line 3340
   __cil_tmp10 = dev->dev_private;
 #line 3340
   dev_priv = (drm_i915_private_t *)__cil_tmp10;
 #line 3342
   __ret_warn_on = 0;
 #line 3342
   __cil_tmp11 = __ret_warn_on != 0;
 #line 3342
   __cil_tmp12 = (long )__cil_tmp11;
 #line 3342
   tmp = __builtin_expect(__cil_tmp12, 0L);
   }
 #line 3342
   if (tmp != 0L) {
     {
 #line 3342
     __cil_tmp13 = (int const   )3342;
 #line 3342
     __cil_tmp14 = (int )__cil_tmp13;
 #line 3342
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp14);
     }
   } else {
 
   }
   {
 #line 3342
   __cil_tmp15 = __ret_warn_on != 0;
 #line 3342
   __cil_tmp16 = (long )__cil_tmp15;
 #line 3342
   __builtin_expect(__cil_tmp16, 0L);
 #line 3343
   __cil_tmp17 = (unsigned int *)obj;
 #line 3343
   __cil_tmp18 = __cil_tmp17 + 56UL;
 #line 3343
   __cil_tmp19 = *__cil_tmp18;
 #line 3343
   __cil_tmp20 = __cil_tmp19 == 0U;
 #line 3343
   __cil_tmp21 = (long )__cil_tmp20;
 #line 3343
   tmp___0 = __builtin_expect(__cil_tmp21, 0L);
   }
 #line 3343
   if (tmp___0 != 0L) {
 #line 3343
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3343), "i" (12UL));
     ldv_39696: ;
 #line 3343
     goto ldv_39696;
   } else {
 
   }
   {
 #line 3344
   __cil_tmp22 = (struct drm_mm_node *)0;
 #line 3344
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 3344
   __cil_tmp24 = obj->gtt_space;
 #line 3344
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 3344
   __cil_tmp26 = __cil_tmp25 == __cil_tmp23;
 #line 3344
   __cil_tmp27 = (long )__cil_tmp26;
 #line 3344
   tmp___1 = __builtin_expect(__cil_tmp27, 0L);
   }
 #line 3344
   if (tmp___1 != 0L) {
 #line 3344
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3344), "i" (12UL));
     ldv_39697: ;
 #line 3344
     goto ldv_39697;
   } else {
 
   }
 #line 3346
   __cil_tmp28 = obj->pin_count;
 #line 3346
   __cil_tmp29 = (int )__cil_tmp28;
 #line 3346
   __cil_tmp30 = __cil_tmp29 - 1;
 #line 3346
   obj->pin_count = (unsigned char )__cil_tmp30;
   {
 #line 3346
   __cil_tmp31 = obj->pin_count;
 #line 3346
   __cil_tmp32 = (unsigned int )__cil_tmp31;
 #line 3346
   if (__cil_tmp32 == 0U) {
     {
 #line 3347
     __cil_tmp33 = (unsigned char *)obj;
 #line 3347
     __cil_tmp34 = __cil_tmp33 + 224UL;
 #line 3347
     __cil_tmp35 = *__cil_tmp34;
 #line 3347
     __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 3347
     if (__cil_tmp36 == 0U) {
       {
 #line 3348
       __cil_tmp37 = & obj->mm_list;
 #line 3348
       __cil_tmp38 = & dev_priv->mm.inactive_list;
 #line 3348
       list_move_tail(__cil_tmp37, __cil_tmp38);
       }
     } else {
 
     }
     }
 #line 3350
     obj->pin_mappable = (unsigned char)0;
   } else {
 
   }
   }
   {
 #line 3352
   __ret_warn_on___0 = 0;
 #line 3352
   __cil_tmp39 = __ret_warn_on___0 != 0;
 #line 3352
   __cil_tmp40 = (long )__cil_tmp39;
 #line 3352
   tmp___2 = __builtin_expect(__cil_tmp40, 0L);
   }
 #line 3352
   if (tmp___2 != 0L) {
     {
 #line 3352
     __cil_tmp41 = (int const   )3352;
 #line 3352
     __cil_tmp42 = (int )__cil_tmp41;
 #line 3352
     warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p",
                        __cil_tmp42);
     }
   } else {
 
   }
   {
 #line 3352
   __cil_tmp43 = __ret_warn_on___0 != 0;
 #line 3352
   __cil_tmp44 = (long )__cil_tmp43;
 #line 3352
   __builtin_expect(__cil_tmp44, 0L);
   }
 #line 3354
   return;
 }
 }
 #line 3356 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_pin_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_pin *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   __u32 __cil_tmp9 ;
   struct drm_gem_object *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_gem_object *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned char *__cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   struct drm_file *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct drm_file *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   struct drm_file *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   __u32 __cil_tmp25 ;
   uint32_t __cil_tmp26 ;
   uint32_t __cil_tmp27 ;
   __u64 __cil_tmp28 ;
   uint32_t __cil_tmp29 ;
   bool __cil_tmp30 ;
   uint32_t __cil_tmp31 ;
   struct drm_gem_object *__cil_tmp32 ;
   struct mutex *__cil_tmp33 ;
 
   {
   {
 #line 3359
   args = (struct drm_i915_gem_pin *)data;
 #line 3363
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 3364
   if (ret != 0) {
 #line 3365
     return (ret);
   } else {
 
   }
   {
 #line 3367
   __cil_tmp9 = args->handle;
 #line 3367
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp9);
 #line 3367
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 3367
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 3368
   __cil_tmp10 = (struct drm_gem_object *)0;
 #line 3368
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3368
   __cil_tmp12 = & obj->base;
 #line 3368
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 3368
   if (__cil_tmp13 == __cil_tmp11) {
 #line 3369
     ret = -2;
 #line 3370
     goto unlock;
   } else {
 
   }
   }
   {
 #line 3373
   __cil_tmp14 = (unsigned char *)obj;
 #line 3373
   __cil_tmp15 = __cil_tmp14 + 225UL;
 #line 3373
   __cil_tmp16 = *__cil_tmp15;
 #line 3373
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 3373
   if (__cil_tmp17 != 0U) {
     {
 #line 3374
     drm_err("i915_gem_pin_ioctl", "Attempting to pin a purgeable buffer\n");
 #line 3375
     ret = -22;
     }
 #line 3376
     goto out;
   } else {
 
   }
   }
   {
 #line 3379
   __cil_tmp18 = (struct drm_file *)0;
 #line 3379
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 3379
   __cil_tmp20 = obj->pin_filp;
 #line 3379
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 3379
   if (__cil_tmp21 != __cil_tmp19) {
     {
 #line 3379
     __cil_tmp22 = (unsigned long )file;
 #line 3379
     __cil_tmp23 = obj->pin_filp;
 #line 3379
     __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 3379
     if (__cil_tmp24 != __cil_tmp22) {
       {
 #line 3380
       __cil_tmp25 = args->handle;
 #line 3380
       drm_err("i915_gem_pin_ioctl", "Already pinned in i915_gem_pin_ioctl(): %d\n",
               __cil_tmp25);
 #line 3382
       ret = -22;
       }
 #line 3383
       goto out;
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 3386
   __cil_tmp26 = obj->user_pin_count;
 #line 3386
   obj->user_pin_count = __cil_tmp26 + 1U;
 #line 3387
   obj->pin_filp = file;
   {
 #line 3388
   __cil_tmp27 = obj->user_pin_count;
 #line 3388
   if (__cil_tmp27 == 1U) {
     {
 #line 3389
     __cil_tmp28 = args->alignment;
 #line 3389
     __cil_tmp29 = (uint32_t )__cil_tmp28;
 #line 3389
     __cil_tmp30 = (bool )1;
 #line 3389
     ret = i915_gem_object_pin(obj, __cil_tmp29, __cil_tmp30);
     }
 #line 3390
     if (ret != 0) {
 #line 3391
       goto out;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 3397
   i915_gem_object_flush_cpu_write_domain(obj);
 #line 3398
   __cil_tmp31 = obj->gtt_offset;
 #line 3398
   args->offset = (__u64 )__cil_tmp31;
   }
   out: 
   {
 #line 3400
   __cil_tmp32 = & obj->base;
 #line 3400
   drm_gem_object_unreference(__cil_tmp32);
   }
   unlock: 
   {
 #line 3402
   __cil_tmp33 = & dev->struct_mutex;
 #line 3402
   mutex_unlock(__cil_tmp33);
   }
 #line 3403
   return (ret);
 }
 }
 #line 3407 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_unpin_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_pin *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   __u32 __cil_tmp9 ;
   struct drm_gem_object *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_gem_object *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct drm_file *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   __u32 __cil_tmp17 ;
   uint32_t __cil_tmp18 ;
   uint32_t __cil_tmp19 ;
   struct drm_gem_object *__cil_tmp20 ;
   struct mutex *__cil_tmp21 ;
 
   {
   {
 #line 3410
   args = (struct drm_i915_gem_pin *)data;
 #line 3414
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 3415
   if (ret != 0) {
 #line 3416
     return (ret);
   } else {
 
   }
   {
 #line 3418
   __cil_tmp9 = args->handle;
 #line 3418
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp9);
 #line 3418
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 3418
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 3419
   __cil_tmp10 = (struct drm_gem_object *)0;
 #line 3419
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3419
   __cil_tmp12 = & obj->base;
 #line 3419
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 3419
   if (__cil_tmp13 == __cil_tmp11) {
 #line 3420
     ret = -2;
 #line 3421
     goto unlock;
   } else {
 
   }
   }
   {
 #line 3424
   __cil_tmp14 = (unsigned long )file;
 #line 3424
   __cil_tmp15 = obj->pin_filp;
 #line 3424
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 3424
   if (__cil_tmp16 != __cil_tmp14) {
     {
 #line 3425
     __cil_tmp17 = args->handle;
 #line 3425
     drm_err("i915_gem_unpin_ioctl", "Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
             __cil_tmp17);
 #line 3427
     ret = -22;
     }
 #line 3428
     goto out;
   } else {
 
   }
   }
 #line 3430
   __cil_tmp18 = obj->user_pin_count;
 #line 3430
   obj->user_pin_count = __cil_tmp18 - 1U;
   {
 #line 3431
   __cil_tmp19 = obj->user_pin_count;
 #line 3431
   if (__cil_tmp19 == 0U) {
     {
 #line 3432
     obj->pin_filp = (struct drm_file *)0;
 #line 3433
     i915_gem_object_unpin(obj);
     }
   } else {
 
   }
   }
   out: 
   {
 #line 3437
   __cil_tmp20 = & obj->base;
 #line 3437
   drm_gem_object_unreference(__cil_tmp20);
   }
   unlock: 
   {
 #line 3439
   __cil_tmp21 = & dev->struct_mutex;
 #line 3439
   mutex_unlock(__cil_tmp21);
   }
 #line 3440
   return (ret);
 }
 }
 #line 3444 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_busy_ioctl(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_busy *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   struct drm_i915_gem_request *request ;
   void *tmp___0 ;
   __u32 __cil_tmp11 ;
   struct drm_gem_object *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct drm_gem_object *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   __u32 __cil_tmp17 ;
   uint32_t __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   struct intel_ring_buffer *__cil_tmp20 ;
   uint32_t __cil_tmp21 ;
   uint32_t __cil_tmp22 ;
   struct intel_ring_buffer *__cil_tmp23 ;
   u32 __cil_tmp24 ;
   struct drm_i915_gem_request *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   struct intel_ring_buffer *__cil_tmp28 ;
   struct drm_file *__cil_tmp29 ;
   struct intel_ring_buffer *__cil_tmp30 ;
   unsigned char __cil_tmp31 ;
   struct drm_gem_object *__cil_tmp32 ;
   struct mutex *__cil_tmp33 ;
 
   {
   {
 #line 3447
   args = (struct drm_i915_gem_busy *)data;
 #line 3451
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 3452
   if (ret != 0) {
 #line 3453
     return (ret);
   } else {
 
   }
   {
 #line 3455
   __cil_tmp11 = args->handle;
 #line 3455
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp11);
 #line 3455
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 3455
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 3456
   __cil_tmp12 = (struct drm_gem_object *)0;
 #line 3456
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 3456
   __cil_tmp14 = & obj->base;
 #line 3456
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 3456
   if (__cil_tmp15 == __cil_tmp13) {
 #line 3457
     ret = -2;
 #line 3458
     goto unlock;
   } else {
 
   }
   }
 #line 3466
   __cil_tmp16 = obj->active;
 #line 3466
   args->busy = (__u32 )__cil_tmp16;
   {
 #line 3467
   __cil_tmp17 = args->busy;
 #line 3467
   if (__cil_tmp17 != 0U) {
     {
 #line 3473
     __cil_tmp18 = obj->base.write_domain;
 #line 3473
     __cil_tmp19 = __cil_tmp18 & 4294967230U;
 #line 3473
     if (__cil_tmp19 != 0U) {
       {
 #line 3474
       __cil_tmp20 = obj->ring;
 #line 3474
       __cil_tmp21 = obj->base.write_domain;
 #line 3474
       ret = i915_gem_flush_ring(__cil_tmp20, 0U, __cil_tmp21);
       }
     } else {
       {
 #line 3476
       __cil_tmp22 = obj->last_rendering_seqno;
 #line 3476
       __cil_tmp23 = obj->ring;
 #line 3476
       __cil_tmp24 = __cil_tmp23->outstanding_lazy_request;
 #line 3476
       if (__cil_tmp24 == __cil_tmp22) {
         {
 #line 3483
         tmp___0 = kzalloc(64UL, 208U);
 #line 3483
         request = (struct drm_i915_gem_request *)tmp___0;
         }
         {
 #line 3484
         __cil_tmp25 = (struct drm_i915_gem_request *)0;
 #line 3484
         __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 3484
         __cil_tmp27 = (unsigned long )request;
 #line 3484
         if (__cil_tmp27 != __cil_tmp26) {
           {
 #line 3485
           __cil_tmp28 = obj->ring;
 #line 3485
           __cil_tmp29 = (struct drm_file *)0;
 #line 3485
           ret = i915_add_request(__cil_tmp28, __cil_tmp29, request);
           }
         } else {
 #line 3487
           ret = -12;
         }
         }
       } else {
 
       }
       }
     }
     }
     {
 #line 3495
     __cil_tmp30 = obj->ring;
 #line 3495
     i915_gem_retire_requests_ring(__cil_tmp30);
 #line 3497
     __cil_tmp31 = obj->active;
 #line 3497
     args->busy = (__u32 )__cil_tmp31;
     }
   } else {
 
   }
   }
   {
 #line 3500
   __cil_tmp32 = & obj->base;
 #line 3500
   drm_gem_object_unreference(__cil_tmp32);
   }
   unlock: 
   {
 #line 3502
   __cil_tmp33 = & dev->struct_mutex;
 #line 3502
   mutex_unlock(__cil_tmp33);
   }
 #line 3503
   return (ret);
 }
 }
 #line 3507 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_throttle_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { int tmp ;
 
   {
   {
 #line 3510
   tmp = i915_gem_ring_throttle(dev, file_priv);
   }
 #line 3510
   return (tmp);
 }
 }
 #line 3514 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_madvise_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { struct drm_i915_gem_madvise *args ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   int tmp___0 ;
   __u32 __cil_tmp10 ;
   int __cil_tmp11 ;
   __u32 __cil_tmp12 ;
   int __cil_tmp13 ;
   __u32 __cil_tmp14 ;
   struct drm_gem_object *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct drm_gem_object *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned int *__cil_tmp19 ;
   unsigned int *__cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   __u32 __cil_tmp26 ;
   struct drm_mm_node *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_mm_node *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char *__cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   int __cil_tmp35 ;
   struct drm_gem_object *__cil_tmp36 ;
   struct mutex *__cil_tmp37 ;
 
   {
 #line 3517
   args = (struct drm_i915_gem_madvise *)data;
   {
 #line 3522
   __cil_tmp10 = args->madv;
 #line 3522
   __cil_tmp11 = (int )__cil_tmp10;
 #line 3522
   if (__cil_tmp11 == 1) {
 #line 3522
     goto case_1;
   } else {
     {
 #line 3523
     __cil_tmp12 = args->madv;
 #line 3523
     __cil_tmp13 = (int )__cil_tmp12;
 #line 3523
     if (__cil_tmp13 == 0) {
 #line 3523
       goto case_0;
     } else {
 #line 3525
       goto switch_default;
 #line 3521
       if (0) {
         case_1: ;
         case_0: ;
 #line 3524
         goto ldv_39753;
         switch_default: ;
 #line 3526
         return (-22);
       } else {
 
       }
     }
     }
   }
   }
   ldv_39753: 
   {
 #line 3529
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 3530
   if (ret != 0) {
 #line 3531
     return (ret);
   } else {
 
   }
   {
 #line 3533
   __cil_tmp14 = args->handle;
 #line 3533
   tmp = drm_gem_object_lookup(dev, file_priv, __cil_tmp14);
 #line 3533
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 3533
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 3534
   __cil_tmp15 = (struct drm_gem_object *)0;
 #line 3534
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 3534
   __cil_tmp17 = & obj->base;
 #line 3534
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 3534
   if (__cil_tmp18 == __cil_tmp16) {
 #line 3535
     ret = -2;
 #line 3536
     goto unlock;
   } else {
 
   }
   }
   {
 #line 3539
   __cil_tmp19 = (unsigned int *)obj;
 #line 3539
   __cil_tmp20 = __cil_tmp19 + 56UL;
 #line 3539
   __cil_tmp21 = *__cil_tmp20;
 #line 3539
   if (__cil_tmp21 != 0U) {
 #line 3540
     ret = -22;
 #line 3541
     goto out;
   } else {
 
   }
   }
   {
 #line 3544
   __cil_tmp22 = (unsigned char *)obj;
 #line 3544
   __cil_tmp23 = __cil_tmp22 + 225UL;
 #line 3544
   __cil_tmp24 = *__cil_tmp23;
 #line 3544
   __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 3544
   if (__cil_tmp25 != 2U) {
 #line 3545
     __cil_tmp26 = args->madv;
 #line 3545
     obj->madv = (unsigned char )__cil_tmp26;
   } else {
 
   }
   }
   {
 #line 3548
   tmp___0 = i915_gem_object_is_purgeable(obj);
   }
 #line 3548
   if (tmp___0 != 0) {
     {
 #line 3548
     __cil_tmp27 = (struct drm_mm_node *)0;
 #line 3548
     __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 3548
     __cil_tmp29 = obj->gtt_space;
 #line 3548
     __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 3548
     if (__cil_tmp30 == __cil_tmp28) {
       {
 #line 3550
       i915_gem_object_truncate(obj);
       }
     } else {
 
     }
     }
   } else {
 
   }
 #line 3552
   __cil_tmp31 = (unsigned char *)obj;
 #line 3552
   __cil_tmp32 = __cil_tmp31 + 225UL;
 #line 3552
   __cil_tmp33 = *__cil_tmp32;
 #line 3552
   __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 3552
   __cil_tmp35 = __cil_tmp34 != 2U;
 #line 3552
   args->retained = (__u32 )__cil_tmp35;
   out: 
   {
 #line 3555
   __cil_tmp36 = & obj->base;
 #line 3555
   drm_gem_object_unreference(__cil_tmp36);
   }
   unlock: 
   {
 #line 3557
   __cil_tmp37 = & dev->struct_mutex;
 #line 3557
   mutex_unlock(__cil_tmp37);
   }
 #line 3558
   return (ret);
 }
 }
 #line 3561 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev , size_t size ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   struct address_space *mapping ;
   void *tmp ;
   int tmp___0 ;
   void *__cil_tmp8 ;
   struct drm_i915_gem_object *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_gem_object *__cil_tmp12 ;
   void const   *__cil_tmp13 ;
   struct file *__cil_tmp14 ;
   struct dentry *__cil_tmp15 ;
   struct inode *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   struct list_head *__cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   struct list_head *__cil_tmp21 ;
 
   {
   {
 #line 3564
   __cil_tmp8 = dev->dev_private;
 #line 3564
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 3568
   tmp = kzalloc(376UL, 208U);
 #line 3568
   obj = (struct drm_i915_gem_object *)tmp;
   }
   {
 #line 3569
   __cil_tmp9 = (struct drm_i915_gem_object *)0;
 #line 3569
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 3569
   __cil_tmp11 = (unsigned long )obj;
 #line 3569
   if (__cil_tmp11 == __cil_tmp10) {
 #line 3570
     return ((struct drm_i915_gem_object *)0);
   } else {
 
   }
   }
   {
 #line 3572
   __cil_tmp12 = & obj->base;
 #line 3572
   tmp___0 = drm_gem_object_init(dev, __cil_tmp12, size);
   }
 #line 3572
   if (tmp___0 != 0) {
     {
 #line 3573
     __cil_tmp13 = (void const   *)obj;
 #line 3573
     kfree(__cil_tmp13);
     }
 #line 3574
     return ((struct drm_i915_gem_object *)0);
   } else {
 
   }
   {
 #line 3577
   __cil_tmp14 = obj->base.filp;
 #line 3577
   __cil_tmp15 = __cil_tmp14->f_path.dentry;
 #line 3577
   __cil_tmp16 = __cil_tmp15->d_inode;
 #line 3577
   mapping = __cil_tmp16->i_mapping;
 #line 3578
   mapping_set_gfp_mask(mapping, 655570U);
 #line 3580
   i915_gem_info_add_obj(dev_priv, size);
 #line 3582
   obj->base.write_domain = 1U;
 #line 3583
   obj->base.read_domains = 1U;
 #line 3585
   obj->cache_level = (unsigned char)0;
 #line 3586
   obj->base.driver_private = (void *)0;
 #line 3587
   obj->fence_reg = (signed char)-1;
 #line 3588
   __cil_tmp17 = & obj->mm_list;
 #line 3588
   INIT_LIST_HEAD(__cil_tmp17);
 #line 3589
   __cil_tmp18 = & obj->gtt_list;
 #line 3589
   INIT_LIST_HEAD(__cil_tmp18);
 #line 3590
   __cil_tmp19 = & obj->ring_list;
 #line 3590
   INIT_LIST_HEAD(__cil_tmp19);
 #line 3591
   __cil_tmp20 = & obj->exec_list;
 #line 3591
   INIT_LIST_HEAD(__cil_tmp20);
 #line 3592
   __cil_tmp21 = & obj->gpu_write_list;
 #line 3592
   INIT_LIST_HEAD(__cil_tmp21);
 #line 3593
   obj->madv = (unsigned char)0;
 #line 3595
   obj->map_and_fenceable = (unsigned char)1;
   }
 #line 3597
   return (obj);
 }
 }
 #line 3600 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_init_object(struct drm_gem_object *obj ) 
 { 
 
   {
 #line 3602
   __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                        "i" (3602), "i" (12UL));
   ldv_39769: ;
 #line 3602
   goto ldv_39769;
 #line 3604
   return (0);
 }
 }
 #line 3607 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   void *__cil_tmp5 ;
   struct list_head *__cil_tmp6 ;
   struct list_head *__cil_tmp7 ;
   struct drm_local_map *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   struct drm_local_map *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_gem_object *__cil_tmp12 ;
   size_t __cil_tmp13 ;
   uint8_t *__cil_tmp14 ;
   void const   *__cil_tmp15 ;
   unsigned long *__cil_tmp16 ;
   void const   *__cil_tmp17 ;
   void const   *__cil_tmp18 ;
 
   {
   {
 #line 3609
   dev = obj->base.dev;
 #line 3610
   __cil_tmp5 = dev->dev_private;
 #line 3610
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 3613
   ret = i915_gem_object_unbind(obj);
   }
 #line 3614
   if (ret == -512) {
     {
 #line 3615
     __cil_tmp6 = & obj->mm_list;
 #line 3615
     __cil_tmp7 = & dev_priv->mm.deferred_free_list;
 #line 3615
     list_move(__cil_tmp6, __cil_tmp7);
     }
 #line 3617
     return;
   } else {
 
   }
   {
 #line 3620
   trace_i915_gem_object_destroy(obj);
   }
   {
 #line 3622
   __cil_tmp8 = (struct drm_local_map *)0;
 #line 3622
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 3622
   __cil_tmp10 = obj->base.map_list.map;
 #line 3622
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3622
   if (__cil_tmp11 != __cil_tmp9) {
     {
 #line 3623
     i915_gem_free_mmap_offset(obj);
     }
   } else {
 
   }
   }
   {
 #line 3625
   __cil_tmp12 = & obj->base;
 #line 3625
   drm_gem_object_release(__cil_tmp12);
 #line 3626
   __cil_tmp13 = obj->base.size;
 #line 3626
   i915_gem_info_remove_obj(dev_priv, __cil_tmp13);
 #line 3628
   __cil_tmp14 = obj->page_cpu_valid;
 #line 3628
   __cil_tmp15 = (void const   *)__cil_tmp14;
 #line 3628
   kfree(__cil_tmp15);
 #line 3629
   __cil_tmp16 = obj->bit_17;
 #line 3629
   __cil_tmp17 = (void const   *)__cil_tmp16;
 #line 3629
   kfree(__cil_tmp17);
 #line 3630
   __cil_tmp18 = (void const   *)obj;
 #line 3630
   kfree(__cil_tmp18);
   }
 #line 3631
   return;
 }
 }
 #line 3633 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_free_object(struct drm_gem_object *gem_obj ) 
 { struct drm_i915_gem_object *obj ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_device *dev ;
   unsigned char __cil_tmp5 ;
   int __cil_tmp6 ;
   struct drm_i915_gem_phys_object *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_i915_gem_phys_object *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
 
   {
 #line 3635
   __mptr = (struct drm_gem_object  const  *)gem_obj;
 #line 3635
   obj = (struct drm_i915_gem_object *)__mptr;
 #line 3636
   dev = obj->base.dev;
 #line 3638
   goto ldv_39784;
   ldv_39783: 
   {
 #line 3639
   i915_gem_object_unpin(obj);
   }
   ldv_39784: ;
   {
 #line 3638
   __cil_tmp5 = obj->pin_count;
 #line 3638
   __cil_tmp6 = (int )__cil_tmp5;
 #line 3638
   if (__cil_tmp6 > 0) {
 #line 3639
     goto ldv_39783;
   } else {
 #line 3641
     goto ldv_39785;
   }
   }
   ldv_39785: ;
   {
 #line 3641
   __cil_tmp7 = (struct drm_i915_gem_phys_object *)0;
 #line 3641
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 3641
   __cil_tmp9 = obj->phys_obj;
 #line 3641
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 3641
   if (__cil_tmp10 != __cil_tmp8) {
     {
 #line 3642
     i915_gem_detach_phys_object(dev, obj);
     }
   } else {
 
   }
   }
   {
 #line 3644
   i915_gem_free_object_tail(obj);
   }
 #line 3645
   return;
 }
 }
 #line 3648 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_idle(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int ret ;
   int tmp ;
   void *__cil_tmp5 ;
   struct mutex *__cil_tmp6 ;
   int __cil_tmp7 ;
   struct mutex *__cil_tmp8 ;
   struct mutex *__cil_tmp9 ;
   bool __cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   struct timer_list *__cil_tmp12 ;
   struct mutex *__cil_tmp13 ;
   struct delayed_work *__cil_tmp14 ;
 
   {
   {
 #line 3650
   __cil_tmp5 = dev->dev_private;
 #line 3650
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
 #line 3653
   __cil_tmp6 = & dev->struct_mutex;
 #line 3653
   mutex_lock_nested(__cil_tmp6, 0U);
   }
   {
 #line 3655
   __cil_tmp7 = dev_priv->mm.suspended;
 #line 3655
   if (__cil_tmp7 != 0) {
     {
 #line 3656
     __cil_tmp8 = & dev->struct_mutex;
 #line 3656
     mutex_unlock(__cil_tmp8);
     }
 #line 3657
     return (0);
   } else {
 
   }
   }
   {
 #line 3660
   ret = i915_gpu_idle(dev);
   }
 #line 3661
   if (ret != 0) {
     {
 #line 3662
     __cil_tmp9 = & dev->struct_mutex;
 #line 3662
     mutex_unlock(__cil_tmp9);
     }
 #line 3663
     return (ret);
   } else {
 
   }
   {
 #line 3667
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 3667
   if (tmp == 0) {
     {
 #line 3668
     __cil_tmp10 = (bool )0;
 #line 3668
     ret = i915_gem_evict_inactive(dev, __cil_tmp10);
     }
 #line 3669
     if (ret != 0) {
       {
 #line 3670
       __cil_tmp11 = & dev->struct_mutex;
 #line 3670
       mutex_unlock(__cil_tmp11);
       }
 #line 3671
       return (ret);
     } else {
 
     }
   } else {
 
   }
   {
 #line 3675
   i915_gem_reset_fences(dev);
 #line 3681
   dev_priv->mm.suspended = 1;
 #line 3682
   __cil_tmp12 = & dev_priv->hangcheck_timer;
 #line 3682
   del_timer_sync(__cil_tmp12);
 #line 3684
   i915_kernel_lost_context(dev);
 #line 3685
   i915_gem_cleanup_ringbuffer(dev);
 #line 3687
   __cil_tmp13 = & dev->struct_mutex;
 #line 3687
   mutex_unlock(__cil_tmp13);
 #line 3690
   __cil_tmp14 = & dev_priv->mm.retire_work;
 #line 3690
   cancel_delayed_work_sync(__cil_tmp14);
   }
 #line 3692
   return (0);
 }
 }
 #line 3696 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_init_ringbuffer(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int ret ;
   void *__cil_tmp4 ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char *__cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   unsigned char *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   struct intel_ring_buffer (*__cil_tmp19)[3U] ;
   struct intel_ring_buffer *__cil_tmp20 ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct intel_ring_buffer (*__cil_tmp22)[3U] ;
   struct intel_ring_buffer *__cil_tmp23 ;
 
   {
   {
 #line 3698
   __cil_tmp4 = dev->dev_private;
 #line 3698
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 3701
   ret = intel_init_render_ring_buffer(dev);
   }
 #line 3702
   if (ret != 0) {
 #line 3703
     return (ret);
   } else {
 
   }
   {
 #line 3705
   __cil_tmp5 = dev->dev_private;
 #line 3705
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 3705
   __cil_tmp7 = __cil_tmp6->info;
 #line 3705
   __cil_tmp8 = (unsigned char *)__cil_tmp7;
 #line 3705
   __cil_tmp9 = __cil_tmp8 + 3UL;
 #line 3705
   __cil_tmp10 = *__cil_tmp9;
 #line 3705
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 3705
   if (__cil_tmp11 != 0U) {
     {
 #line 3706
     ret = intel_init_bsd_ring_buffer(dev);
     }
 #line 3707
     if (ret != 0) {
 #line 3708
       goto cleanup_render_ring;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 3711
   __cil_tmp12 = dev->dev_private;
 #line 3711
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 3711
   __cil_tmp14 = __cil_tmp13->info;
 #line 3711
   __cil_tmp15 = (unsigned char *)__cil_tmp14;
 #line 3711
   __cil_tmp16 = __cil_tmp15 + 3UL;
 #line 3711
   __cil_tmp17 = *__cil_tmp16;
 #line 3711
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 3711
   if (__cil_tmp18 != 0U) {
     {
 #line 3712
     ret = intel_init_blt_ring_buffer(dev);
     }
 #line 3713
     if (ret != 0) {
 #line 3714
       goto cleanup_bsd_ring;
     } else {
 
     }
   } else {
 
   }
   }
 #line 3717
   dev_priv->next_seqno = 1U;
 #line 3719
   return (0);
   cleanup_bsd_ring: 
   {
 #line 3722
   __cil_tmp19 = & dev_priv->ring;
 #line 3722
   __cil_tmp20 = (struct intel_ring_buffer *)__cil_tmp19;
 #line 3722
   __cil_tmp21 = __cil_tmp20 + 1UL;
 #line 3722
   intel_cleanup_ring_buffer(__cil_tmp21);
   }
   cleanup_render_ring: 
   {
 #line 3724
   __cil_tmp22 = & dev_priv->ring;
 #line 3724
   __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
 #line 3724
   intel_cleanup_ring_buffer(__cil_tmp23);
   }
 #line 3725
   return (ret);
 }
 }
 #line 3729 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int i ;
   void *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   struct intel_ring_buffer (*__cil_tmp6)[3U] ;
   struct intel_ring_buffer *__cil_tmp7 ;
   struct intel_ring_buffer *__cil_tmp8 ;
 
   {
 #line 3731
   __cil_tmp4 = dev->dev_private;
 #line 3731
   dev_priv = (drm_i915_private_t *)__cil_tmp4;
 #line 3734
   i = 0;
 #line 3734
   goto ldv_39804;
   ldv_39803: 
   {
 #line 3735
   __cil_tmp5 = (unsigned long )i;
 #line 3735
   __cil_tmp6 = & dev_priv->ring;
 #line 3735
   __cil_tmp7 = (struct intel_ring_buffer *)__cil_tmp6;
 #line 3735
   __cil_tmp8 = __cil_tmp7 + __cil_tmp5;
 #line 3735
   intel_cleanup_ring_buffer(__cil_tmp8);
 #line 3734
   i = i + 1;
   }
   ldv_39804: ;
 #line 3734
   if (i <= 2) {
 #line 3735
     goto ldv_39803;
   } else {
 #line 3737
     goto ldv_39805;
   }
   ldv_39805: ;
 #line 3739
   return;
 }
 }
 #line 3739 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_entervt_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { drm_i915_private_t *dev_priv ;
   int ret ;
   int i ;
   int tmp ;
   int tmp___0 ;
   int tmp___1 ;
   long tmp___2 ;
   int tmp___3 ;
   long tmp___4 ;
   int tmp___5 ;
   long tmp___6 ;
   int tmp___7 ;
   long tmp___8 ;
   int tmp___9 ;
   long tmp___10 ;
   void *__cil_tmp19 ;
   atomic_t *__cil_tmp20 ;
   atomic_t const   *__cil_tmp21 ;
   atomic_t *__cil_tmp22 ;
   struct mutex *__cil_tmp23 ;
   struct mutex *__cil_tmp24 ;
   struct list_head *__cil_tmp25 ;
   struct list_head  const  *__cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
   struct list_head *__cil_tmp29 ;
   struct list_head  const  *__cil_tmp30 ;
   int __cil_tmp31 ;
   long __cil_tmp32 ;
   struct list_head *__cil_tmp33 ;
   struct list_head  const  *__cil_tmp34 ;
   int __cil_tmp35 ;
   long __cil_tmp36 ;
   struct list_head *__cil_tmp37 ;
   struct list_head  const  *__cil_tmp38 ;
   int __cil_tmp39 ;
   long __cil_tmp40 ;
   struct list_head *__cil_tmp41 ;
   struct list_head  const  *__cil_tmp42 ;
   int __cil_tmp43 ;
   long __cil_tmp44 ;
   struct mutex *__cil_tmp45 ;
   struct mutex *__cil_tmp46 ;
   struct mutex *__cil_tmp47 ;
 
   {
   {
 #line 3742
   __cil_tmp19 = dev->dev_private;
 #line 3742
   dev_priv = (drm_i915_private_t *)__cil_tmp19;
 #line 3745
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 3745
   if (tmp != 0) {
 #line 3746
     return (0);
   } else {
 
   }
   {
 #line 3748
   __cil_tmp20 = & dev_priv->mm.wedged;
 #line 3748
   __cil_tmp21 = (atomic_t const   *)__cil_tmp20;
 #line 3748
   tmp___0 = atomic_read(__cil_tmp21);
   }
 #line 3748
   if (tmp___0 != 0) {
     {
 #line 3749
     drm_err("i915_gem_entervt_ioctl", "Reenabling wedged hardware, good luck\n");
 #line 3750
     __cil_tmp22 = & dev_priv->mm.wedged;
 #line 3750
     atomic_set(__cil_tmp22, 0);
     }
   } else {
 
   }
   {
 #line 3753
   __cil_tmp23 = & dev->struct_mutex;
 #line 3753
   mutex_lock_nested(__cil_tmp23, 0U);
 #line 3754
   dev_priv->mm.suspended = 0;
 #line 3756
   ret = i915_gem_init_ringbuffer(dev);
   }
 #line 3757
   if (ret != 0) {
     {
 #line 3758
     __cil_tmp24 = & dev->struct_mutex;
 #line 3758
     mutex_unlock(__cil_tmp24);
     }
 #line 3759
     return (ret);
   } else {
 
   }
   {
 #line 3762
   __cil_tmp25 = & dev_priv->mm.active_list;
 #line 3762
   __cil_tmp26 = (struct list_head  const  *)__cil_tmp25;
 #line 3762
   tmp___1 = list_empty(__cil_tmp26);
 #line 3762
   __cil_tmp27 = tmp___1 == 0;
 #line 3762
   __cil_tmp28 = (long )__cil_tmp27;
 #line 3762
   tmp___2 = __builtin_expect(__cil_tmp28, 0L);
   }
 #line 3762
   if (tmp___2 != 0L) {
 #line 3762
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3762), "i" (12UL));
     ldv_39815: ;
 #line 3762
     goto ldv_39815;
   } else {
 
   }
   {
 #line 3763
   __cil_tmp29 = & dev_priv->mm.flushing_list;
 #line 3763
   __cil_tmp30 = (struct list_head  const  *)__cil_tmp29;
 #line 3763
   tmp___3 = list_empty(__cil_tmp30);
 #line 3763
   __cil_tmp31 = tmp___3 == 0;
 #line 3763
   __cil_tmp32 = (long )__cil_tmp31;
 #line 3763
   tmp___4 = __builtin_expect(__cil_tmp32, 0L);
   }
 #line 3763
   if (tmp___4 != 0L) {
 #line 3763
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3763), "i" (12UL));
     ldv_39816: ;
 #line 3763
     goto ldv_39816;
   } else {
 
   }
   {
 #line 3764
   __cil_tmp33 = & dev_priv->mm.inactive_list;
 #line 3764
   __cil_tmp34 = (struct list_head  const  *)__cil_tmp33;
 #line 3764
   tmp___5 = list_empty(__cil_tmp34);
 #line 3764
   __cil_tmp35 = tmp___5 == 0;
 #line 3764
   __cil_tmp36 = (long )__cil_tmp35;
 #line 3764
   tmp___6 = __builtin_expect(__cil_tmp36, 0L);
   }
 #line 3764
   if (tmp___6 != 0L) {
 #line 3764
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3764), "i" (12UL));
     ldv_39817: ;
 #line 3764
     goto ldv_39817;
   } else {
 
   }
 #line 3765
   i = 0;
 #line 3765
   goto ldv_39821;
   ldv_39820: 
   {
 #line 3766
   __cil_tmp37 = & dev_priv->ring[i].active_list;
 #line 3766
   __cil_tmp38 = (struct list_head  const  *)__cil_tmp37;
 #line 3766
   tmp___7 = list_empty(__cil_tmp38);
 #line 3766
   __cil_tmp39 = tmp___7 == 0;
 #line 3766
   __cil_tmp40 = (long )__cil_tmp39;
 #line 3766
   tmp___8 = __builtin_expect(__cil_tmp40, 0L);
   }
 #line 3766
   if (tmp___8 != 0L) {
 #line 3766
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3766), "i" (12UL));
     ldv_39818: ;
 #line 3766
     goto ldv_39818;
   } else {
 
   }
   {
 #line 3767
   __cil_tmp41 = & dev_priv->ring[i].request_list;
 #line 3767
   __cil_tmp42 = (struct list_head  const  *)__cil_tmp41;
 #line 3767
   tmp___9 = list_empty(__cil_tmp42);
 #line 3767
   __cil_tmp43 = tmp___9 == 0;
 #line 3767
   __cil_tmp44 = (long )__cil_tmp43;
 #line 3767
   tmp___10 = __builtin_expect(__cil_tmp44, 0L);
   }
 #line 3767
   if (tmp___10 != 0L) {
 #line 3767
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"),
                          "i" (3767), "i" (12UL));
     ldv_39819: ;
 #line 3767
     goto ldv_39819;
   } else {
 
   }
 #line 3765
   i = i + 1;
   ldv_39821: ;
 #line 3765
   if (i <= 2) {
 #line 3766
     goto ldv_39820;
   } else {
 #line 3768
     goto ldv_39822;
   }
   ldv_39822: 
   {
 #line 3769
   __cil_tmp45 = & dev->struct_mutex;
 #line 3769
   mutex_unlock(__cil_tmp45);
 #line 3771
   ret = drm_irq_install(dev);
   }
 #line 3772
   if (ret != 0) {
 #line 3773
     goto cleanup_ringbuffer;
   } else {
 
   }
 #line 3775
   return (0);
   cleanup_ringbuffer: 
   {
 #line 3778
   __cil_tmp46 = & dev->struct_mutex;
 #line 3778
   mutex_lock_nested(__cil_tmp46, 0U);
 #line 3779
   i915_gem_cleanup_ringbuffer(dev);
 #line 3780
   dev_priv->mm.suspended = 1;
 #line 3781
   __cil_tmp47 = & dev->struct_mutex;
 #line 3781
   mutex_unlock(__cil_tmp47);
   }
 #line 3783
   return (ret);
 }
 }
 #line 3787 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_leavevt_ioctl(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
 { int tmp ;
   int tmp___0 ;
 
   {
   {
 #line 3790
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 3790
   if (tmp != 0) {
 #line 3791
     return (0);
   } else {
 
   }
   {
 #line 3793
   drm_irq_uninstall(dev);
 #line 3794
   tmp___0 = i915_gem_idle(dev);
   }
 #line 3794
   return (tmp___0);
 }
 }
 #line 3798 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_lastclose(struct drm_device *dev ) 
 { int ret ;
   int tmp ;
 
   {
   {
 #line 3802
   tmp = drm_core_check_feature(dev, 8192);
   }
 #line 3802
   if (tmp != 0) {
 #line 3803
     return;
   } else {
 
   }
   {
 #line 3805
   ret = i915_gem_idle(dev);
   }
 #line 3806
   if (ret != 0) {
     {
 #line 3807
     drm_err("i915_gem_lastclose", "failed to idle hardware: %d\n", ret);
     }
   } else {
 
   }
 #line 3808
   return;
 }
 }
 #line 3811 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void init_ring_lists(struct intel_ring_buffer *ring ) 
 { struct list_head *__cil_tmp2 ;
   struct list_head *__cil_tmp3 ;
   struct list_head *__cil_tmp4 ;
 
   {
   {
 #line 3813
   __cil_tmp2 = & ring->active_list;
 #line 3813
   INIT_LIST_HEAD(__cil_tmp2);
 #line 3814
   __cil_tmp3 = & ring->request_list;
 #line 3814
   INIT_LIST_HEAD(__cil_tmp3);
 #line 3815
   __cil_tmp4 = & ring->gpu_write_list;
 #line 3815
   INIT_LIST_HEAD(__cil_tmp4);
   }
 #line 3816
   return;
 }
 }
 #line 3819 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_load(struct drm_device *dev ) 
 { int i ;
   drm_i915_private_t *dev_priv ;
   struct lock_class_key __key ;
   atomic_long_t __constr_expr_0 ;
   struct lock_class_key __key___0 ;
   u32 tmp ;
   u32 tmp___0 ;
   int tmp___1 ;
   struct lock_class_key __key___1 ;
   void *__cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct list_head *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   struct list_head *__cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct intel_ring_buffer (*__cil_tmp20)[3U] ;
   struct intel_ring_buffer *__cil_tmp21 ;
   struct intel_ring_buffer *__cil_tmp22 ;
   struct list_head *__cil_tmp23 ;
   struct work_struct *__cil_tmp24 ;
   struct lockdep_map *__cil_tmp25 ;
   struct list_head *__cil_tmp26 ;
   struct timer_list *__cil_tmp27 ;
   struct completion *__cil_tmp28 ;
   void *__cil_tmp29 ;
   struct drm_i915_private *__cil_tmp30 ;
   struct intel_device_info  const  *__cil_tmp31 ;
   u8 __cil_tmp32 ;
   unsigned char __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   void *__cil_tmp36 ;
   struct drm_i915_private *__cil_tmp37 ;
   struct intel_device_info  const  *__cil_tmp38 ;
   u8 __cil_tmp39 ;
   unsigned char __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   int __cil_tmp42 ;
   void *__cil_tmp43 ;
   struct drm_i915_private *__cil_tmp44 ;
   struct intel_device_info  const  *__cil_tmp45 ;
   unsigned char *__cil_tmp46 ;
   unsigned char *__cil_tmp47 ;
   unsigned char __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   void *__cil_tmp50 ;
   struct drm_i915_private *__cil_tmp51 ;
   struct intel_device_info  const  *__cil_tmp52 ;
   unsigned char *__cil_tmp53 ;
   unsigned char *__cil_tmp54 ;
   unsigned char __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   struct drm_i915_fence_reg (*__cil_tmp58)[16U] ;
   struct drm_i915_fence_reg *__cil_tmp59 ;
   struct drm_i915_fence_reg *__cil_tmp60 ;
   int __cil_tmp61 ;
   wait_queue_head_t *__cil_tmp62 ;
   struct shrinker *__cil_tmp63 ;
 
   {
   {
 #line 3822
   __cil_tmp11 = dev->dev_private;
 #line 3822
   dev_priv = (drm_i915_private_t *)__cil_tmp11;
 #line 3824
   __cil_tmp12 = & dev_priv->mm.active_list;
 #line 3824
   INIT_LIST_HEAD(__cil_tmp12);
 #line 3825
   __cil_tmp13 = & dev_priv->mm.flushing_list;
 #line 3825
   INIT_LIST_HEAD(__cil_tmp13);
 #line 3826
   __cil_tmp14 = & dev_priv->mm.inactive_list;
 #line 3826
   INIT_LIST_HEAD(__cil_tmp14);
 #line 3827
   __cil_tmp15 = & dev_priv->mm.pinned_list;
 #line 3827
   INIT_LIST_HEAD(__cil_tmp15);
 #line 3828
   __cil_tmp16 = & dev_priv->mm.fence_list;
 #line 3828
   INIT_LIST_HEAD(__cil_tmp16);
 #line 3829
   __cil_tmp17 = & dev_priv->mm.deferred_free_list;
 #line 3829
   INIT_LIST_HEAD(__cil_tmp17);
 #line 3830
   __cil_tmp18 = & dev_priv->mm.gtt_list;
 #line 3830
   INIT_LIST_HEAD(__cil_tmp18);
 #line 3831
   i = 0;
   }
 #line 3831
   goto ldv_39843;
   ldv_39842: 
   {
 #line 3832
   __cil_tmp19 = (unsigned long )i;
 #line 3832
   __cil_tmp20 = & dev_priv->ring;
 #line 3832
   __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
 #line 3832
   __cil_tmp22 = __cil_tmp21 + __cil_tmp19;
 #line 3832
   init_ring_lists(__cil_tmp22);
 #line 3831
   i = i + 1;
   }
   ldv_39843: ;
 #line 3831
   if (i <= 2) {
 #line 3832
     goto ldv_39842;
   } else {
 #line 3834
     goto ldv_39844;
   }
   ldv_39844: 
 #line 3833
   i = 0;
 #line 3833
   goto ldv_39846;
   ldv_39845: 
   {
 #line 3834
   __cil_tmp23 = & dev_priv->fence_regs[i].lru_list;
 #line 3834
   INIT_LIST_HEAD(__cil_tmp23);
 #line 3833
   i = i + 1;
   }
   ldv_39846: ;
 #line 3833
   if (i <= 15) {
 #line 3834
     goto ldv_39845;
   } else {
 #line 3836
     goto ldv_39847;
   }
   ldv_39847: 
   {
 #line 3835
   __cil_tmp24 = & dev_priv->mm.retire_work.work;
 #line 3835
   __init_work(__cil_tmp24, 0);
 #line 3835
   __constr_expr_0.counter = 2097664L;
 #line 3835
   dev_priv->mm.retire_work.work.data = __constr_expr_0;
 #line 3835
   __cil_tmp25 = & dev_priv->mm.retire_work.work.lockdep_map;
 #line 3835
   lockdep_init_map(__cil_tmp25, "(&(&dev_priv->mm.retire_work)->work)", & __key, 0);
 #line 3835
   __cil_tmp26 = & dev_priv->mm.retire_work.work.entry;
 #line 3835
   INIT_LIST_HEAD(__cil_tmp26);
 #line 3835
   dev_priv->mm.retire_work.work.func = & i915_gem_retire_work_handler;
 #line 3835
   __cil_tmp27 = & dev_priv->mm.retire_work.timer;
 #line 3835
   init_timer_key(__cil_tmp27, "&(&dev_priv->mm.retire_work)->timer", & __key___0);
 #line 3837
   __cil_tmp28 = & dev_priv->error_completion;
 #line 3837
   init_completion(__cil_tmp28);
   }
   {
 #line 3840
   __cil_tmp29 = dev->dev_private;
 #line 3840
   __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
 #line 3840
   __cil_tmp31 = __cil_tmp30->info;
 #line 3840
   __cil_tmp32 = __cil_tmp31->gen;
 #line 3840
   __cil_tmp33 = (unsigned char )__cil_tmp32;
 #line 3840
   __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 3840
   if (__cil_tmp34 == 3U) {
     {
 #line 3841
     tmp___0 = i915_read32(dev_priv, 8420U);
 #line 3841
     tmp = tmp___0;
     }
     {
 #line 3842
     __cil_tmp35 = tmp & 2048U;
 #line 3842
     if (__cil_tmp35 == 0U) {
       {
 #line 3844
       tmp = 134219776U;
 #line 3845
       i915_write32(dev_priv, 8420U, tmp);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 3849
   dev_priv->relative_constants_mode = 0;
 #line 3852
   tmp___1 = drm_core_check_feature(dev, 8192);
   }
 #line 3852
   if (tmp___1 == 0) {
 #line 3853
     dev_priv->fence_reg_start = 3;
   } else {
 
   }
   {
 #line 3855
   __cil_tmp36 = dev->dev_private;
 #line 3855
   __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
 #line 3855
   __cil_tmp38 = __cil_tmp37->info;
 #line 3855
   __cil_tmp39 = __cil_tmp38->gen;
 #line 3855
   __cil_tmp40 = (unsigned char )__cil_tmp39;
 #line 3855
   __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 3855
   if (__cil_tmp41 > 3U) {
 #line 3856
     dev_priv->num_fence_regs = 16;
   } else {
     {
 #line 3855
     __cil_tmp42 = dev->pci_device;
 #line 3855
     if (__cil_tmp42 == 10098) {
 #line 3856
       dev_priv->num_fence_regs = 16;
     } else {
       {
 #line 3855
       __cil_tmp43 = dev->dev_private;
 #line 3855
       __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
 #line 3855
       __cil_tmp45 = __cil_tmp44->info;
 #line 3855
       __cil_tmp46 = (unsigned char *)__cil_tmp45;
 #line 3855
       __cil_tmp47 = __cil_tmp46 + 1UL;
 #line 3855
       __cil_tmp48 = *__cil_tmp47;
 #line 3855
       __cil_tmp49 = (unsigned int )__cil_tmp48;
 #line 3855
       if (__cil_tmp49 != 0U) {
 #line 3856
         dev_priv->num_fence_regs = 16;
       } else {
         {
 #line 3855
         __cil_tmp50 = dev->dev_private;
 #line 3855
         __cil_tmp51 = (struct drm_i915_private *)__cil_tmp50;
 #line 3855
         __cil_tmp52 = __cil_tmp51->info;
 #line 3855
         __cil_tmp53 = (unsigned char *)__cil_tmp52;
 #line 3855
         __cil_tmp54 = __cil_tmp53 + 1UL;
 #line 3855
         __cil_tmp55 = *__cil_tmp54;
 #line 3855
         __cil_tmp56 = (unsigned int )__cil_tmp55;
 #line 3855
         if (__cil_tmp56 != 0U) {
 #line 3856
           dev_priv->num_fence_regs = 16;
         } else {
 #line 3858
           dev_priv->num_fence_regs = 8;
         }
         }
       }
       }
     }
     }
   }
   }
 #line 3861
   i = 0;
 #line 3861
   goto ldv_39853;
   ldv_39852: 
   {
 #line 3862
   __cil_tmp57 = (unsigned long )i;
 #line 3862
   __cil_tmp58 = & dev_priv->fence_regs;
 #line 3862
   __cil_tmp59 = (struct drm_i915_fence_reg *)__cil_tmp58;
 #line 3862
   __cil_tmp60 = __cil_tmp59 + __cil_tmp57;
 #line 3862
   i915_gem_clear_fence_reg(dev, __cil_tmp60);
 #line 3861
   i = i + 1;
   }
   ldv_39853: ;
   {
 #line 3861
   __cil_tmp61 = dev_priv->num_fence_regs;
 #line 3861
   if (__cil_tmp61 > i) {
 #line 3862
     goto ldv_39852;
   } else {
 #line 3864
     goto ldv_39854;
   }
   }
   ldv_39854: 
   {
 #line 3865
   i915_gem_detect_bit_6_swizzle(dev);
 #line 3866
   __cil_tmp62 = & dev_priv->pending_flip_queue;
 #line 3866
   __init_waitqueue_head(__cil_tmp62, & __key___1);
 #line 3868
   dev_priv->mm.interruptible = (bool )1;
 #line 3870
   dev_priv->mm.inactive_shrinker.shrink = & i915_gem_inactive_shrink;
 #line 3871
   dev_priv->mm.inactive_shrinker.seeks = 2;
 #line 3872
   __cil_tmp63 = & dev_priv->mm.inactive_shrinker;
 #line 3872
   register_shrinker(__cil_tmp63);
   }
 #line 3873
   return;
 }
 }
 #line 3879 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_init_phys_object(struct drm_device *dev , int id , int size ,
                                      int align ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_phys_object *phys_obj ;
   int ret ;
   void *tmp ;
   void *__cil_tmp9 ;
   struct drm_i915_gem_phys_object *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_i915_gem_phys_object *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct drm_i915_gem_phys_object *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   size_t __cil_tmp17 ;
   size_t __cil_tmp18 ;
   drm_dma_handle_t *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   drm_dma_handle_t *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   drm_dma_handle_t *__cil_tmp23 ;
   void *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   drm_dma_handle_t *__cil_tmp26 ;
   size_t __cil_tmp27 ;
   size_t __cil_tmp28 ;
   int __cil_tmp29 ;
   void const   *__cil_tmp30 ;
 
   {
 #line 3882
   __cil_tmp9 = dev->dev_private;
 #line 3882
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
   {
 #line 3886
   __cil_tmp10 = (struct drm_i915_gem_phys_object *)0;
 #line 3886
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3886
   __cil_tmp12 = dev_priv->mm.phys_objs[id + -1];
 #line 3886
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 3886
   if (__cil_tmp13 != __cil_tmp11) {
 #line 3887
     return (0);
   } else
 #line 3886
   if (size == 0) {
 #line 3887
     return (0);
   } else {
 
   }
   }
   {
 #line 3889
   tmp = kzalloc(32UL, 208U);
 #line 3889
   phys_obj = (struct drm_i915_gem_phys_object *)tmp;
   }
   {
 #line 3890
   __cil_tmp14 = (struct drm_i915_gem_phys_object *)0;
 #line 3890
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 3890
   __cil_tmp16 = (unsigned long )phys_obj;
 #line 3890
   if (__cil_tmp16 == __cil_tmp15) {
 #line 3891
     return (-12);
   } else {
 
   }
   }
   {
 #line 3893
   phys_obj->id = id;
 #line 3895
   __cil_tmp17 = (size_t )size;
 #line 3895
   __cil_tmp18 = (size_t )align;
 #line 3895
   phys_obj->handle = drm_pci_alloc(dev, __cil_tmp17, __cil_tmp18);
   }
   {
 #line 3896
   __cil_tmp19 = (drm_dma_handle_t *)0;
 #line 3896
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 3896
   __cil_tmp21 = phys_obj->handle;
 #line 3896
   __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 3896
   if (__cil_tmp22 == __cil_tmp20) {
 #line 3897
     ret = -12;
 #line 3898
     goto kfree_obj;
   } else {
 
   }
   }
   {
 #line 3901
   __cil_tmp23 = phys_obj->handle;
 #line 3901
   __cil_tmp24 = __cil_tmp23->vaddr;
 #line 3901
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 3901
   __cil_tmp26 = phys_obj->handle;
 #line 3901
   __cil_tmp27 = __cil_tmp26->size;
 #line 3901
   __cil_tmp28 = __cil_tmp27 / 4096UL;
 #line 3901
   __cil_tmp29 = (int )__cil_tmp28;
 #line 3901
   set_memory_wc(__cil_tmp25, __cil_tmp29);
 #line 3904
   dev_priv->mm.phys_objs[id + -1] = phys_obj;
   }
 #line 3906
   return (0);
   kfree_obj: 
   {
 #line 3908
   __cil_tmp30 = (void const   *)phys_obj;
 #line 3908
   kfree(__cil_tmp30);
   }
 #line 3909
   return (ret);
 }
 }
 #line 3912 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static void i915_gem_free_phys_object(struct drm_device *dev , int id ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_phys_object *phys_obj ;
   void *__cil_tmp5 ;
   struct drm_i915_gem_phys_object *__cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct drm_i915_gem_phys_object *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   struct drm_i915_gem_object *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_i915_gem_object *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct drm_i915_gem_object *__cil_tmp14 ;
   drm_dma_handle_t *__cil_tmp15 ;
   void *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   drm_dma_handle_t *__cil_tmp18 ;
   size_t __cil_tmp19 ;
   size_t __cil_tmp20 ;
   int __cil_tmp21 ;
   drm_dma_handle_t *__cil_tmp22 ;
   void const   *__cil_tmp23 ;
 
   {
 #line 3914
   __cil_tmp5 = dev->dev_private;
 #line 3914
   dev_priv = (drm_i915_private_t *)__cil_tmp5;
   {
 #line 3917
   __cil_tmp6 = (struct drm_i915_gem_phys_object *)0;
 #line 3917
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 3917
   __cil_tmp8 = dev_priv->mm.phys_objs[id + -1];
 #line 3917
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 3917
   if (__cil_tmp9 == __cil_tmp7) {
 #line 3918
     return;
   } else {
 
   }
   }
 #line 3920
   phys_obj = dev_priv->mm.phys_objs[id + -1];
   {
 #line 3921
   __cil_tmp10 = (struct drm_i915_gem_object *)0;
 #line 3921
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3921
   __cil_tmp12 = phys_obj->cur_obj;
 #line 3921
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 3921
   if (__cil_tmp13 != __cil_tmp11) {
     {
 #line 3922
     __cil_tmp14 = phys_obj->cur_obj;
 #line 3922
     i915_gem_detach_phys_object(dev, __cil_tmp14);
     }
   } else {
 
   }
   }
   {
 #line 3926
   __cil_tmp15 = phys_obj->handle;
 #line 3926
   __cil_tmp16 = __cil_tmp15->vaddr;
 #line 3926
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 3926
   __cil_tmp18 = phys_obj->handle;
 #line 3926
   __cil_tmp19 = __cil_tmp18->size;
 #line 3926
   __cil_tmp20 = __cil_tmp19 / 4096UL;
 #line 3926
   __cil_tmp21 = (int )__cil_tmp20;
 #line 3926
   set_memory_wb(__cil_tmp17, __cil_tmp21);
 #line 3928
   __cil_tmp22 = phys_obj->handle;
 #line 3928
   drm_pci_free(dev, __cil_tmp22);
 #line 3929
   __cil_tmp23 = (void const   *)phys_obj;
 #line 3929
   kfree(__cil_tmp23);
 #line 3930
   dev_priv->mm.phys_objs[id + -1] = (struct drm_i915_gem_phys_object *)0;
   }
 #line 3931
   return;
 }
 }
 #line 3933 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_free_all_phys_object(struct drm_device *dev ) 
 { int i ;
 
   {
 #line 3937
   i = 1;
 #line 3937
   goto ldv_39877;
   ldv_39876: 
   {
 #line 3938
   i915_gem_free_phys_object(dev, i);
 #line 3937
   i = i + 1;
   }
   ldv_39877: ;
 #line 3937
   if (i <= 3) {
 #line 3938
     goto ldv_39876;
   } else {
 #line 3940
     goto ldv_39878;
   }
   ldv_39878: ;
 #line 3942
   return;
 }
 }
 #line 3941 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_detach_phys_object(struct drm_device *dev , struct drm_i915_gem_object *obj ) 
 { struct address_space *mapping ;
   char *vaddr ;
   int i ;
   int page_count___0 ;
   struct page *page ;
   struct page *tmp ;
   char *dst ;
   void *tmp___0 ;
   size_t __len ;
   void *__ret ;
   long tmp___1 ;
   struct file *__cil_tmp14 ;
   struct dentry *__cil_tmp15 ;
   struct inode *__cil_tmp16 ;
   struct drm_i915_gem_phys_object *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct drm_i915_gem_phys_object *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   struct drm_i915_gem_phys_object *__cil_tmp21 ;
   drm_dma_handle_t *__cil_tmp22 ;
   void *__cil_tmp23 ;
   size_t __cil_tmp24 ;
   size_t __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   void const   *__cil_tmp27 ;
   void *__cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   char *__cil_tmp31 ;
   void const   *__cil_tmp32 ;
   void *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   char *__cil_tmp36 ;
   void const   *__cil_tmp37 ;
   void *__cil_tmp38 ;
   struct drm_i915_gem_phys_object *__cil_tmp39 ;
 
   {
 #line 3944
   __cil_tmp14 = obj->base.filp;
 #line 3944
   __cil_tmp15 = __cil_tmp14->f_path.dentry;
 #line 3944
   __cil_tmp16 = __cil_tmp15->d_inode;
 #line 3944
   mapping = __cil_tmp16->i_mapping;
   {
 #line 3949
   __cil_tmp17 = (struct drm_i915_gem_phys_object *)0;
 #line 3949
   __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 3949
   __cil_tmp19 = obj->phys_obj;
 #line 3949
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 3949
   if (__cil_tmp20 == __cil_tmp18) {
 #line 3950
     return;
   } else {
 
   }
   }
 #line 3951
   __cil_tmp21 = obj->phys_obj;
 #line 3951
   __cil_tmp22 = __cil_tmp21->handle;
 #line 3951
   __cil_tmp23 = __cil_tmp22->vaddr;
 #line 3951
   vaddr = (char *)__cil_tmp23;
 #line 3953
   __cil_tmp24 = obj->base.size;
 #line 3953
   __cil_tmp25 = __cil_tmp24 / 4096UL;
 #line 3953
   page_count___0 = (int )__cil_tmp25;
 #line 3954
   i = 0;
 #line 3954
   goto ldv_39893;
   ldv_39892: 
   {
 #line 3955
   __cil_tmp26 = (unsigned long )i;
 #line 3955
   tmp = shmem_read_mapping_page(mapping, __cil_tmp26);
 #line 3955
   page = tmp;
 #line 3956
   __cil_tmp27 = (void const   *)page;
 #line 3956
   tmp___1 = IS_ERR(__cil_tmp27);
   }
 #line 3956
   if (tmp___1 == 0L) {
     {
 #line 3957
     tmp___0 = __kmap_atomic(page);
 #line 3957
     dst = (char *)tmp___0;
 #line 3958
     __len = 4096UL;
     }
 #line 3958
     if (__len > 63UL) {
       {
 #line 3958
       __cil_tmp28 = (void *)dst;
 #line 3958
       __cil_tmp29 = (unsigned long )i;
 #line 3958
       __cil_tmp30 = __cil_tmp29 * 4096UL;
 #line 3958
       __cil_tmp31 = vaddr + __cil_tmp30;
 #line 3958
       __cil_tmp32 = (void const   *)__cil_tmp31;
 #line 3958
       __ret = __memcpy(__cil_tmp28, __cil_tmp32, __len);
       }
     } else {
       {
 #line 3958
       __cil_tmp33 = (void *)dst;
 #line 3958
       __cil_tmp34 = (unsigned long )i;
 #line 3958
       __cil_tmp35 = __cil_tmp34 * 4096UL;
 #line 3958
       __cil_tmp36 = vaddr + __cil_tmp35;
 #line 3958
       __cil_tmp37 = (void const   *)__cil_tmp36;
 #line 3958
       __ret = __builtin_memcpy(__cil_tmp33, __cil_tmp37, __len);
       }
     }
     {
 #line 3959
     __cil_tmp38 = (void *)dst;
 #line 3959
     __kunmap_atomic(__cil_tmp38);
 #line 3961
     drm_clflush_pages(& page, 1UL);
 #line 3963
     set_page_dirty(page);
 #line 3964
     mark_page_accessed(page);
 #line 3965
     put_page(page);
     }
   } else {
 
   }
 #line 3954
   i = i + 1;
   ldv_39893: ;
 #line 3954
   if (i < page_count___0) {
 #line 3955
     goto ldv_39892;
   } else {
 #line 3957
     goto ldv_39894;
   }
   ldv_39894: 
   {
 #line 3968
   intel_gtt_chipset_flush();
 #line 3970
   __cil_tmp39 = obj->phys_obj;
 #line 3970
   __cil_tmp39->cur_obj = (struct drm_i915_gem_object *)0;
 #line 3971
   obj->phys_obj = (struct drm_i915_gem_phys_object *)0;
   }
 #line 3972
   return;
 }
 }
 #line 3975 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 int i915_gem_attach_phys_object(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                 int id , int align ) 
 { struct address_space *mapping ;
   drm_i915_private_t *dev_priv ;
   int ret ;
   int page_count___0 ;
   int i ;
   struct page *page ;
   char *dst ;
   char *src ;
   long tmp ;
   long tmp___0 ;
   void *tmp___1 ;
   size_t __len ;
   void *__ret ;
   struct file *__cil_tmp18 ;
   struct dentry *__cil_tmp19 ;
   struct inode *__cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_gem_phys_object *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct drm_i915_gem_phys_object *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct drm_i915_gem_phys_object *__cil_tmp26 ;
   int __cil_tmp27 ;
   struct drm_i915_gem_phys_object *__cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   struct drm_i915_gem_phys_object *__cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   size_t __cil_tmp32 ;
   int __cil_tmp33 ;
   size_t __cil_tmp34 ;
   struct drm_i915_gem_phys_object *__cil_tmp35 ;
   size_t __cil_tmp36 ;
   size_t __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   void const   *__cil_tmp39 ;
   void const   *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct drm_i915_gem_phys_object *__cil_tmp43 ;
   drm_dma_handle_t *__cil_tmp44 ;
   void *__cil_tmp45 ;
   void *__cil_tmp46 ;
   void *__cil_tmp47 ;
   void const   *__cil_tmp48 ;
   void *__cil_tmp49 ;
   void const   *__cil_tmp50 ;
   void *__cil_tmp51 ;
 
   {
 #line 3980
   __cil_tmp18 = obj->base.filp;
 #line 3980
   __cil_tmp19 = __cil_tmp18->f_path.dentry;
 #line 3980
   __cil_tmp20 = __cil_tmp19->d_inode;
 #line 3980
   mapping = __cil_tmp20->i_mapping;
 #line 3981
   __cil_tmp21 = dev->dev_private;
 #line 3981
   dev_priv = (drm_i915_private_t *)__cil_tmp21;
 #line 3982
   ret = 0;
 #line 3986
   if (id > 3) {
 #line 3987
     return (-22);
   } else {
 
   }
   {
 #line 3989
   __cil_tmp22 = (struct drm_i915_gem_phys_object *)0;
 #line 3989
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 3989
   __cil_tmp24 = obj->phys_obj;
 #line 3989
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 3989
   if (__cil_tmp25 != __cil_tmp23) {
     {
 #line 3990
     __cil_tmp26 = obj->phys_obj;
 #line 3990
     __cil_tmp27 = __cil_tmp26->id;
 #line 3990
     if (__cil_tmp27 == id) {
 #line 3991
       return (0);
     } else {
 
     }
     }
     {
 #line 3992
     i915_gem_detach_phys_object(dev, obj);
     }
   } else {
 
   }
   }
   {
 #line 3996
   __cil_tmp28 = (struct drm_i915_gem_phys_object *)0;
 #line 3996
   __cil_tmp29 = (unsigned long )__cil_tmp28;
 #line 3996
   __cil_tmp30 = dev_priv->mm.phys_objs[id + -1];
 #line 3996
   __cil_tmp31 = (unsigned long )__cil_tmp30;
 #line 3996
   if (__cil_tmp31 == __cil_tmp29) {
     {
 #line 3997
     __cil_tmp32 = obj->base.size;
 #line 3997
     __cil_tmp33 = (int )__cil_tmp32;
 #line 3997
     ret = i915_gem_init_phys_object(dev, id, __cil_tmp33, align);
     }
 #line 3999
     if (ret != 0) {
       {
 #line 4000
       __cil_tmp34 = obj->base.size;
 #line 4000
       drm_err("i915_gem_attach_phys_object", "failed to init phys object %d size: %zu\n",
               id, __cil_tmp34);
       }
 #line 4002
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
 #line 4007
   obj->phys_obj = dev_priv->mm.phys_objs[id + -1];
 #line 4008
   __cil_tmp35 = obj->phys_obj;
 #line 4008
   __cil_tmp35->cur_obj = obj;
 #line 4010
   __cil_tmp36 = obj->base.size;
 #line 4010
   __cil_tmp37 = __cil_tmp36 / 4096UL;
 #line 4010
   page_count___0 = (int )__cil_tmp37;
 #line 4012
   i = 0;
 #line 4012
   goto ldv_39914;
   ldv_39913: 
   {
 #line 4016
   __cil_tmp38 = (unsigned long )i;
 #line 4016
   page = shmem_read_mapping_page(mapping, __cil_tmp38);
 #line 4017
   __cil_tmp39 = (void const   *)page;
 #line 4017
   tmp___0 = IS_ERR(__cil_tmp39);
   }
 #line 4017
   if (tmp___0 != 0L) {
     {
 #line 4018
     __cil_tmp40 = (void const   *)page;
 #line 4018
     tmp = PTR_ERR(__cil_tmp40);
     }
 #line 4018
     return ((int )tmp);
   } else {
 
   }
   {
 #line 4020
   tmp___1 = __kmap_atomic(page);
 #line 4020
   src = (char *)tmp___1;
 #line 4021
   __cil_tmp41 = (unsigned long )i;
 #line 4021
   __cil_tmp42 = __cil_tmp41 * 4096UL;
 #line 4021
   __cil_tmp43 = obj->phys_obj;
 #line 4021
   __cil_tmp44 = __cil_tmp43->handle;
 #line 4021
   __cil_tmp45 = __cil_tmp44->vaddr;
 #line 4021
   __cil_tmp46 = __cil_tmp45 + __cil_tmp42;
 #line 4021
   dst = (char *)__cil_tmp46;
 #line 4022
   __len = 4096UL;
   }
 #line 4022
   if (__len > 63UL) {
     {
 #line 4022
     __cil_tmp47 = (void *)dst;
 #line 4022
     __cil_tmp48 = (void const   *)src;
 #line 4022
     __ret = __memcpy(__cil_tmp47, __cil_tmp48, __len);
     }
   } else {
     {
 #line 4022
     __cil_tmp49 = (void *)dst;
 #line 4022
     __cil_tmp50 = (void const   *)src;
 #line 4022
     __ret = __builtin_memcpy(__cil_tmp49, __cil_tmp50, __len);
     }
   }
   {
 #line 4023
   __cil_tmp51 = (void *)src;
 #line 4023
   __kunmap_atomic(__cil_tmp51);
 #line 4025
   mark_page_accessed(page);
 #line 4026
   put_page(page);
 #line 4012
   i = i + 1;
   }
   ldv_39914: ;
 #line 4012
   if (i < page_count___0) {
 #line 4013
     goto ldv_39913;
   } else {
 #line 4015
     goto ldv_39915;
   }
   ldv_39915: ;
 #line 4029
   return (0);
 }
 }
 #line 4033 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_phys_pwrite(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                 struct drm_i915_gem_pwrite *args , struct drm_file *file_priv ) 
 { void *vaddr ;
   char *user_data ;
   unsigned long unwritten ;
   int tmp ;
   __u64 __cil_tmp9 ;
   struct drm_i915_gem_phys_object *__cil_tmp10 ;
   drm_dma_handle_t *__cil_tmp11 ;
   void *__cil_tmp12 ;
   __u64 __cil_tmp13 ;
   void const   *__cil_tmp14 ;
   __u64 __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   struct mutex *__cil_tmp17 ;
   void const   *__cil_tmp18 ;
   __u64 __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   struct mutex *__cil_tmp21 ;
 
   {
   {
 #line 4038
   __cil_tmp9 = args->offset;
 #line 4038
   __cil_tmp10 = obj->phys_obj;
 #line 4038
   __cil_tmp11 = __cil_tmp10->handle;
 #line 4038
   __cil_tmp12 = __cil_tmp11->vaddr;
 #line 4038
   vaddr = __cil_tmp12 + __cil_tmp9;
 #line 4039
   __cil_tmp13 = args->data_ptr;
 #line 4039
   user_data = (char *)__cil_tmp13;
 #line 4041
   __cil_tmp14 = (void const   *)user_data;
 #line 4041
   __cil_tmp15 = args->size;
 #line 4041
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 4041
   tmp = __copy_from_user_inatomic_nocache(vaddr, __cil_tmp14, __cil_tmp16);
   }
 #line 4041
   if (tmp != 0) {
     {
 #line 4048
     __cil_tmp17 = & dev->struct_mutex;
 #line 4048
     mutex_unlock(__cil_tmp17);
 #line 4049
     __cil_tmp18 = (void const   *)user_data;
 #line 4049
     __cil_tmp19 = args->size;
 #line 4049
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 4049
     unwritten = copy_from_user(vaddr, __cil_tmp18, __cil_tmp20);
 #line 4050
     __cil_tmp21 = & dev->struct_mutex;
 #line 4050
     mutex_lock_nested(__cil_tmp21, 0U);
     }
 #line 4051
     if (unwritten != 0UL) {
 #line 4052
       return (-14);
     } else {
 
     }
   } else {
 
   }
   {
 #line 4055
   intel_gtt_chipset_flush();
   }
 #line 4056
   return (0);
 }
 }
 #line 4059 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 void i915_gem_release(struct drm_device *dev , struct drm_file *file ) 
 { struct drm_i915_file_private *file_priv ;
   struct drm_i915_gem_request *request ;
   struct list_head  const  *__mptr ;
   int tmp ;
   void *__cil_tmp7 ;
   struct spinlock *__cil_tmp8 ;
   struct list_head *__cil_tmp9 ;
   struct drm_i915_gem_request *__cil_tmp10 ;
   struct list_head *__cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct list_head  const  *__cil_tmp13 ;
   struct spinlock *__cil_tmp14 ;
 
   {
   {
 #line 4061
   __cil_tmp7 = file->driver_priv;
 #line 4061
   file_priv = (struct drm_i915_file_private *)__cil_tmp7;
 #line 4067
   __cil_tmp8 = & file_priv->mm.lock;
 #line 4067
   spin_lock(__cil_tmp8);
   }
 #line 4068
   goto ldv_39934;
   ldv_39933: 
   {
 #line 4071
   __cil_tmp9 = file_priv->mm.request_list.next;
 #line 4071
   __mptr = (struct list_head  const  *)__cil_tmp9;
 #line 4071
   __cil_tmp10 = (struct drm_i915_gem_request *)__mptr;
 #line 4071
   request = __cil_tmp10 + 1152921504606846928UL;
 #line 4074
   __cil_tmp11 = & request->client_list;
 #line 4074
   list_del(__cil_tmp11);
 #line 4075
   request->file_priv = (struct drm_i915_file_private *)0;
   }
   ldv_39934: 
   {
 #line 4068
   __cil_tmp12 = & file_priv->mm.request_list;
 #line 4068
   __cil_tmp13 = (struct list_head  const  *)__cil_tmp12;
 #line 4068
   tmp = list_empty(__cil_tmp13);
   }
 #line 4068
   if (tmp == 0) {
 #line 4069
     goto ldv_39933;
   } else {
 #line 4071
     goto ldv_39935;
   }
   ldv_39935: 
   {
 #line 4077
   __cil_tmp14 = & file_priv->mm.lock;
 #line 4077
   spin_unlock(__cil_tmp14);
   }
 #line 4078
   return;
 }
 }
 #line 4081 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gpu_is_active(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   int lists_empty ;
   int tmp ;
   int tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp7 ;
   struct list_head *__cil_tmp8 ;
   struct list_head  const  *__cil_tmp9 ;
   struct list_head *__cil_tmp10 ;
   struct list_head  const  *__cil_tmp11 ;
 
   {
   {
 #line 4083
   __cil_tmp7 = dev->dev_private;
 #line 4083
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 4086
   __cil_tmp8 = & dev_priv->mm.flushing_list;
 #line 4086
   __cil_tmp9 = (struct list_head  const  *)__cil_tmp8;
 #line 4086
   tmp = list_empty(__cil_tmp9);
   }
 #line 4086
   if (tmp != 0) {
     {
 #line 4086
     __cil_tmp10 = & dev_priv->mm.active_list;
 #line 4086
     __cil_tmp11 = (struct list_head  const  *)__cil_tmp10;
 #line 4086
     tmp___0 = list_empty(__cil_tmp11);
     }
 #line 4086
     if (tmp___0 != 0) {
 #line 4086
       tmp___1 = 1;
     } else {
 #line 4086
       tmp___1 = 0;
     }
   } else {
 #line 4086
     tmp___1 = 0;
   }
 #line 4086
   lists_empty = tmp___1;
 #line 4089
   return (lists_empty == 0);
 }
 }
 #line 4093 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem.c.p"
 static int i915_gem_inactive_shrink(struct shrinker *shrinker , struct shrink_control *sc ) 
 { struct drm_i915_private *dev_priv ;
   struct shrinker  const  *__mptr ;
   struct drm_device *dev ;
   struct drm_i915_gem_object *obj ;
   struct drm_i915_gem_object *next ;
   int nr_to_scan ;
   int cnt ;
   int tmp ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   struct list_head  const  *__mptr___2 ;
   struct list_head  const  *__mptr___3 ;
   int tmp___0 ;
   int tmp___1 ;
   struct list_head  const  *__mptr___4 ;
   struct list_head  const  *__mptr___5 ;
   struct list_head  const  *__mptr___6 ;
   int tmp___2 ;
   struct list_head  const  *__mptr___7 ;
   int tmp___3 ;
   int tmp___4 ;
   struct drm_i915_private *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   struct mutex *__cil_tmp26 ;
   struct list_head *__cil_tmp27 ;
   struct drm_i915_gem_object *__cil_tmp28 ;
   struct list_head *__cil_tmp29 ;
   struct drm_i915_gem_object *__cil_tmp30 ;
   struct list_head *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   struct list_head *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   struct mutex *__cil_tmp35 ;
   int __cil_tmp36 ;
   struct list_head *__cil_tmp37 ;
   struct drm_i915_gem_object *__cil_tmp38 ;
   struct list_head *__cil_tmp39 ;
   struct drm_i915_gem_object *__cil_tmp40 ;
   struct list_head *__cil_tmp41 ;
   struct drm_i915_gem_object *__cil_tmp42 ;
   struct list_head *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   struct list_head *__cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   struct list_head *__cil_tmp47 ;
   struct drm_i915_gem_object *__cil_tmp48 ;
   struct list_head *__cil_tmp49 ;
   struct drm_i915_gem_object *__cil_tmp50 ;
   struct list_head *__cil_tmp51 ;
   struct drm_i915_gem_object *__cil_tmp52 ;
   struct list_head *__cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   struct list_head *__cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   struct mutex *__cil_tmp57 ;
   int __cil_tmp58 ;
 
   {
   {
 #line 4096
   __mptr = (struct shrinker  const  *)shrinker;
 #line 4096
   __cil_tmp24 = (struct drm_i915_private *)__mptr;
 #line 4096
   dev_priv = __cil_tmp24 + 1152921504606840424UL;
 #line 4099
   dev = dev_priv->dev;
 #line 4101
   __cil_tmp25 = sc->nr_to_scan;
 #line 4101
   nr_to_scan = (int )__cil_tmp25;
 #line 4104
   __cil_tmp26 = & dev->struct_mutex;
 #line 4104
   tmp = mutex_trylock(__cil_tmp26);
   }
 #line 4104
   if (tmp == 0) {
 #line 4105
     return (0);
   } else {
 
   }
 #line 4108
   if (nr_to_scan == 0) {
 #line 4109
     cnt = 0;
 #line 4110
     __cil_tmp27 = dev_priv->mm.inactive_list.next;
 #line 4110
     __mptr___0 = (struct list_head  const  *)__cil_tmp27;
 #line 4110
     __cil_tmp28 = (struct drm_i915_gem_object *)__mptr___0;
 #line 4110
     obj = __cil_tmp28 + 1152921504606846800UL;
 #line 4110
     goto ldv_39958;
     ldv_39957: 
 #line 4113
     cnt = cnt + 1;
 #line 4110
     __cil_tmp29 = obj->mm_list.next;
 #line 4110
     __mptr___1 = (struct list_head  const  *)__cil_tmp29;
 #line 4110
     __cil_tmp30 = (struct drm_i915_gem_object *)__mptr___1;
 #line 4110
     obj = __cil_tmp30 + 1152921504606846800UL;
     ldv_39958: ;
     {
 #line 4110
     __cil_tmp31 = & dev_priv->mm.inactive_list;
 #line 4110
     __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 4110
     __cil_tmp33 = & obj->mm_list;
 #line 4110
     __cil_tmp34 = (unsigned long )__cil_tmp33;
 #line 4110
     if (__cil_tmp34 != __cil_tmp32) {
 #line 4111
       goto ldv_39957;
     } else {
 #line 4113
       goto ldv_39959;
     }
     }
     ldv_39959: 
     {
 #line 4114
     __cil_tmp35 = & dev->struct_mutex;
 #line 4114
     mutex_unlock(__cil_tmp35);
     }
     {
 #line 4115
     __cil_tmp36 = cnt / 100;
 #line 4115
     return (__cil_tmp36 * sysctl_vfs_cache_pressure);
     }
   } else {
 
   }
   rescan: 
   {
 #line 4120
   i915_gem_retire_requests(dev);
 #line 4122
   __cil_tmp37 = dev_priv->mm.inactive_list.next;
 #line 4122
   __mptr___2 = (struct list_head  const  *)__cil_tmp37;
 #line 4122
   __cil_tmp38 = (struct drm_i915_gem_object *)__mptr___2;
 #line 4122
   obj = __cil_tmp38 + 1152921504606846800UL;
 #line 4122
   __cil_tmp39 = obj->mm_list.next;
 #line 4122
   __mptr___3 = (struct list_head  const  *)__cil_tmp39;
 #line 4122
   __cil_tmp40 = (struct drm_i915_gem_object *)__mptr___3;
 #line 4122
   next = __cil_tmp40 + 1152921504606846800UL;
   }
 #line 4122
   goto ldv_39969;
   ldv_39968: 
   {
 #line 4125
   tmp___1 = i915_gem_object_is_purgeable(obj);
   }
 #line 4125
   if (tmp___1 != 0) {
     {
 #line 4126
     tmp___0 = i915_gem_object_unbind(obj);
     }
 #line 4126
     if (tmp___0 == 0) {
 #line 4126
       nr_to_scan = nr_to_scan - 1;
 #line 4126
       if (nr_to_scan == 0) {
 #line 4128
         goto ldv_39967;
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
 #line 4122
   obj = next;
 #line 4122
   __cil_tmp41 = next->mm_list.next;
 #line 4122
   __mptr___4 = (struct list_head  const  *)__cil_tmp41;
 #line 4122
   __cil_tmp42 = (struct drm_i915_gem_object *)__mptr___4;
 #line 4122
   next = __cil_tmp42 + 1152921504606846800UL;
   ldv_39969: ;
   {
 #line 4122
   __cil_tmp43 = & dev_priv->mm.inactive_list;
 #line 4122
   __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 4122
   __cil_tmp45 = & obj->mm_list;
 #line 4122
   __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 4122
   if (__cil_tmp46 != __cil_tmp44) {
 #line 4123
     goto ldv_39968;
   } else {
 #line 4125
     goto ldv_39967;
   }
   }
   ldv_39967: 
 #line 4133
   cnt = 0;
 #line 4134
   __cil_tmp47 = dev_priv->mm.inactive_list.next;
 #line 4134
   __mptr___5 = (struct list_head  const  *)__cil_tmp47;
 #line 4134
   __cil_tmp48 = (struct drm_i915_gem_object *)__mptr___5;
 #line 4134
   obj = __cil_tmp48 + 1152921504606846800UL;
 #line 4134
   __cil_tmp49 = obj->mm_list.next;
 #line 4134
   __mptr___6 = (struct list_head  const  *)__cil_tmp49;
 #line 4134
   __cil_tmp50 = (struct drm_i915_gem_object *)__mptr___6;
 #line 4134
   next = __cil_tmp50 + 1152921504606846800UL;
 #line 4134
   goto ldv_39977;
   ldv_39976: ;
 #line 4137
   if (nr_to_scan != 0) {
     {
 #line 4137
     tmp___2 = i915_gem_object_unbind(obj);
     }
 #line 4137
     if (tmp___2 == 0) {
 #line 4139
       nr_to_scan = nr_to_scan - 1;
     } else {
 #line 4141
       cnt = cnt + 1;
     }
   } else {
 #line 4141
     cnt = cnt + 1;
   }
 #line 4134
   obj = next;
 #line 4134
   __cil_tmp51 = next->mm_list.next;
 #line 4134
   __mptr___7 = (struct list_head  const  *)__cil_tmp51;
 #line 4134
   __cil_tmp52 = (struct drm_i915_gem_object *)__mptr___7;
 #line 4134
   next = __cil_tmp52 + 1152921504606846800UL;
   ldv_39977: ;
   {
 #line 4134
   __cil_tmp53 = & dev_priv->mm.inactive_list;
 #line 4134
   __cil_tmp54 = (unsigned long )__cil_tmp53;
 #line 4134
   __cil_tmp55 = & obj->mm_list;
 #line 4134
   __cil_tmp56 = (unsigned long )__cil_tmp55;
 #line 4134
   if (__cil_tmp56 != __cil_tmp54) {
 #line 4135
     goto ldv_39976;
   } else {
 #line 4137
     goto ldv_39978;
   }
   }
   ldv_39978: ;
 #line 4144
   if (nr_to_scan != 0) {
     {
 #line 4144
     tmp___4 = i915_gpu_is_active(dev);
     }
 #line 4144
     if (tmp___4 != 0) {
       {
 #line 4151
       tmp___3 = i915_gpu_idle(dev);
       }
 #line 4151
       if (tmp___3 == 0) {
 #line 4152
         goto rescan;
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 4154
   __cil_tmp57 = & dev->struct_mutex;
 #line 4154
   mutex_unlock(__cil_tmp57);
   }
   {
 #line 4155
   __cil_tmp58 = cnt / 100;
 #line 4155
   return (__cil_tmp58 * sysctl_vfs_cache_pressure);
   }
 }
 }
 #line 174 "include/drm/drm_mm.h"
 extern void drm_mm_init_scan(struct drm_mm * , unsigned long  , unsigned int  ) ;
 #line 176
 extern void drm_mm_init_scan_with_range(struct drm_mm * , unsigned long  , unsigned int  ,
                                         unsigned long  , unsigned long  ) ;
 #line 180
 extern int drm_mm_scan_add_block(struct drm_mm_node * ) ;
 #line 181
 extern int drm_mm_scan_remove_block(struct drm_mm_node * ) ;
 #line 214 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_evict ;
 #line 214 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_evict(struct drm_device *dev , u32 size , u32 align ,
                                           bool mappable ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp13 ;
   struct tracepoint_func **__cil_tmp14 ;
   struct tracepoint_func * volatile  *__cil_tmp15 ;
   struct tracepoint_func * volatile  __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct tracepoint_func *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void (*__cil_tmp22)(void * , struct drm_device * , u32  , u32  , bool  ) ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   void *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   void *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
 
   {
   {
 #line 193
   __cil_tmp13 = & __tracepoint_i915_gem_evict.key;
 #line 193
   tmp___1 = static_branch(__cil_tmp13);
   }
 #line 193
   if ((int )tmp___1) {
     {
 #line 193
     rcu_read_lock_sched_notrace();
 #line 193
     __cil_tmp14 = & __tracepoint_i915_gem_evict.funcs;
 #line 193
     __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
 #line 193
     __cil_tmp16 = *__cil_tmp15;
 #line 193
     _________p1 = (struct tracepoint_func *)__cil_tmp16;
 #line 193
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 193
     if (tmp != 0) {
 #line 193
       if (! __warned) {
         {
 #line 193
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 193
         if (tmp___0 == 0) {
           {
 #line 193
           __warned = (bool )1;
 #line 193
           __cil_tmp17 = (int const   )214;
 #line 193
           __cil_tmp18 = (int )__cil_tmp17;
 #line 193
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp18);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 193
     it_func_ptr = _________p1;
     {
 #line 193
     __cil_tmp19 = (struct tracepoint_func *)0;
 #line 193
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 193
     __cil_tmp21 = (unsigned long )it_func_ptr;
 #line 193
     if (__cil_tmp21 != __cil_tmp20) {
       ldv_35781: 
       {
 #line 193
       it_func = it_func_ptr->func;
 #line 193
       __data = it_func_ptr->data;
 #line 193
       __cil_tmp22 = (void (*)(void * , struct drm_device * , u32  , u32  , bool  ))it_func;
 #line 193
       __cil_tmp23 = (int )mappable;
 #line 193
       __cil_tmp24 = (bool )__cil_tmp23;
 #line 193
       (*__cil_tmp22)(__data, dev, size, align, __cil_tmp24);
 #line 193
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 193
       __cil_tmp25 = (void *)0;
 #line 193
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 193
       __cil_tmp27 = it_func_ptr->func;
 #line 193
       __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 193
       if (__cil_tmp28 != __cil_tmp26) {
 #line 194
         goto ldv_35781;
       } else {
 #line 196
         goto ldv_35782;
       }
       }
       ldv_35782: ;
     } else {
 
     }
     }
     {
 #line 193
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 195
   return;
 }
 }
 #line 233
 struct tracepoint __tracepoint_i915_gem_evict_everything ;
 #line 233 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_evict_everything(struct drm_device *dev , bool purgeable ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct drm_device * , bool  ) ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   void *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
 
   {
   {
 #line 216
   __cil_tmp11 = & __tracepoint_i915_gem_evict_everything.key;
 #line 216
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 216
   if ((int )tmp___1) {
     {
 #line 216
     rcu_read_lock_sched_notrace();
 #line 216
     __cil_tmp12 = & __tracepoint_i915_gem_evict_everything.funcs;
 #line 216
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 216
     __cil_tmp14 = *__cil_tmp13;
 #line 216
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 216
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 216
     if (tmp != 0) {
 #line 216
       if (! __warned) {
         {
 #line 216
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 216
         if (tmp___0 == 0) {
           {
 #line 216
           __warned = (bool )1;
 #line 216
           __cil_tmp15 = (int const   )233;
 #line 216
           __cil_tmp16 = (int )__cil_tmp15;
 #line 216
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 216
     it_func_ptr = _________p1;
     {
 #line 216
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 216
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 216
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 216
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_35823: 
       {
 #line 216
       it_func = it_func_ptr->func;
 #line 216
       __data = it_func_ptr->data;
 #line 216
       __cil_tmp20 = (void (*)(void * , struct drm_device * , bool  ))it_func;
 #line 216
       __cil_tmp21 = (int )purgeable;
 #line 216
       __cil_tmp22 = (bool )__cil_tmp21;
 #line 216
       (*__cil_tmp20)(__data, dev, __cil_tmp22);
 #line 216
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 216
       __cil_tmp23 = (void *)0;
 #line 216
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 216
       __cil_tmp25 = it_func_ptr->func;
 #line 216
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 216
       if (__cil_tmp26 != __cil_tmp24) {
 #line 217
         goto ldv_35823;
       } else {
 #line 219
         goto ldv_35824;
       }
       }
       ldv_35824: ;
     } else {
 
     }
     }
     {
 #line 216
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 218
   return;
 }
 }
 #line 43 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_evict.c.p"
 static bool mark_free(struct drm_i915_gem_object *obj , struct list_head *unwind ) 
 { int tmp ;
   struct list_head *__cil_tmp4 ;
   struct drm_gem_object *__cil_tmp5 ;
   struct drm_mm_node *__cil_tmp6 ;
   int __cil_tmp7 ;
 
   {
   {
 #line 45
   __cil_tmp4 = & obj->exec_list;
 #line 45
   list_add(__cil_tmp4, unwind);
 #line 46
   __cil_tmp5 = & obj->base;
 #line 46
   drm_gem_object_reference(__cil_tmp5);
 #line 47
   __cil_tmp6 = obj->gtt_space;
 #line 47
   tmp = drm_mm_scan_add_block(__cil_tmp6);
   }
   {
 #line 47
   __cil_tmp7 = tmp != 0;
 #line 47
   return ((bool )__cil_tmp7);
   }
 }
 }
 #line 51 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_evict.c.p"
 int i915_gem_evict_something(struct drm_device *dev , int min_size , unsigned int alignment ,
                              bool mappable ) 
 { drm_i915_private_t *dev_priv ;
   struct list_head eviction_list ;
   struct list_head unwind_list ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_mm_node *tmp ;
   struct drm_mm_node *tmp___0 ;
   struct list_head  const  *__mptr ;
   bool tmp___1 ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   bool tmp___2 ;
   struct list_head  const  *__mptr___2 ;
   struct list_head  const  *__mptr___3 ;
   bool tmp___3 ;
   struct list_head  const  *__mptr___4 ;
   struct list_head  const  *__mptr___5 ;
   bool tmp___4 ;
   struct list_head  const  *__mptr___6 ;
   struct list_head  const  *__mptr___7 ;
   long tmp___5 ;
   int tmp___6 ;
   struct list_head  const  *__mptr___8 ;
   int tmp___7 ;
   int tmp___8 ;
   struct list_head  const  *__mptr___9 ;
   int tmp___9 ;
   void *__cil_tmp32 ;
   struct drm_mm *__cil_tmp33 ;
   struct drm_mm  const  *__cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   struct drm_mm_node *__cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   struct drm_mm *__cil_tmp40 ;
   struct drm_mm  const  *__cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct drm_mm_node *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   u32 __cil_tmp46 ;
   int __cil_tmp47 ;
   bool __cil_tmp48 ;
   struct drm_mm *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   struct drm_mm *__cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   struct list_head *__cil_tmp54 ;
   struct drm_i915_gem_object *__cil_tmp55 ;
   struct list_head *__cil_tmp56 ;
   struct drm_i915_gem_object *__cil_tmp57 ;
   struct list_head *__cil_tmp58 ;
   unsigned long __cil_tmp59 ;
   struct list_head *__cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   struct list_head *__cil_tmp62 ;
   struct drm_i915_gem_object *__cil_tmp63 ;
   uint32_t __cil_tmp64 ;
   unsigned int *__cil_tmp65 ;
   unsigned int *__cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   struct list_head *__cil_tmp68 ;
   struct drm_i915_gem_object *__cil_tmp69 ;
   struct list_head *__cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   struct list_head *__cil_tmp72 ;
   unsigned long __cil_tmp73 ;
   struct list_head *__cil_tmp74 ;
   struct drm_i915_gem_object *__cil_tmp75 ;
   unsigned int *__cil_tmp76 ;
   unsigned int *__cil_tmp77 ;
   unsigned int __cil_tmp78 ;
   struct list_head *__cil_tmp79 ;
   struct drm_i915_gem_object *__cil_tmp80 ;
   struct list_head *__cil_tmp81 ;
   unsigned long __cil_tmp82 ;
   struct list_head *__cil_tmp83 ;
   unsigned long __cil_tmp84 ;
   struct list_head *__cil_tmp85 ;
   struct drm_i915_gem_object *__cil_tmp86 ;
   uint32_t __cil_tmp87 ;
   unsigned int *__cil_tmp88 ;
   unsigned int *__cil_tmp89 ;
   unsigned int __cil_tmp90 ;
   struct list_head *__cil_tmp91 ;
   struct drm_i915_gem_object *__cil_tmp92 ;
   struct list_head *__cil_tmp93 ;
   unsigned long __cil_tmp94 ;
   struct list_head *__cil_tmp95 ;
   unsigned long __cil_tmp96 ;
   struct drm_i915_gem_object *__cil_tmp97 ;
   struct drm_mm_node *__cil_tmp98 ;
   int __cil_tmp99 ;
   long __cil_tmp100 ;
   struct list_head *__cil_tmp101 ;
   struct drm_gem_object *__cil_tmp102 ;
   struct list_head  const  *__cil_tmp103 ;
   struct drm_i915_gem_object *__cil_tmp104 ;
   struct drm_mm_node *__cil_tmp105 ;
   struct list_head *__cil_tmp106 ;
   struct list_head *__cil_tmp107 ;
   struct drm_gem_object *__cil_tmp108 ;
   struct list_head  const  *__cil_tmp109 ;
   struct drm_i915_gem_object *__cil_tmp110 ;
   struct list_head *__cil_tmp111 ;
   struct drm_gem_object *__cil_tmp112 ;
   struct list_head  const  *__cil_tmp113 ;
 
   {
   {
 #line 54
   __cil_tmp32 = dev->dev_private;
 #line 54
   dev_priv = (drm_i915_private_t *)__cil_tmp32;
 #line 57
   ret = 0;
 #line 59
   i915_gem_retire_requests(dev);
   }
 #line 62
   if ((int )mappable) {
     {
 #line 63
     __cil_tmp33 = & dev_priv->mm.gtt_space;
 #line 63
     __cil_tmp34 = (struct drm_mm  const  *)__cil_tmp33;
 #line 63
     __cil_tmp35 = (unsigned long )min_size;
 #line 63
     __cil_tmp36 = dev_priv->mm.gtt_mappable_end;
 #line 63
     tmp___0 = drm_mm_search_free_in_range(__cil_tmp34, __cil_tmp35, alignment, 0UL,
                                           __cil_tmp36, 0);
     }
     {
 #line 63
     __cil_tmp37 = (struct drm_mm_node *)0;
 #line 63
     __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 63
     __cil_tmp39 = (unsigned long )tmp___0;
 #line 63
     if (__cil_tmp39 != __cil_tmp38) {
 #line 67
       return (0);
     } else {
       {
 #line 69
       __cil_tmp40 = & dev_priv->mm.gtt_space;
 #line 69
       __cil_tmp41 = (struct drm_mm  const  *)__cil_tmp40;
 #line 69
       __cil_tmp42 = (unsigned long )min_size;
 #line 69
       tmp = drm_mm_search_free(__cil_tmp41, __cil_tmp42, alignment, 0);
       }
       {
 #line 69
       __cil_tmp43 = (struct drm_mm_node *)0;
 #line 69
       __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 69
       __cil_tmp45 = (unsigned long )tmp;
 #line 69
       if (__cil_tmp45 != __cil_tmp44) {
 #line 71
         return (0);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   {
 #line 74
   __cil_tmp46 = (u32 )min_size;
 #line 74
   __cil_tmp47 = (int )mappable;
 #line 74
   __cil_tmp48 = (bool )__cil_tmp47;
 #line 74
   trace_i915_gem_evict(dev, __cil_tmp46, alignment, __cil_tmp48);
 #line 99
   INIT_LIST_HEAD(& unwind_list);
   }
 #line 100
   if ((int )mappable) {
     {
 #line 101
     __cil_tmp49 = & dev_priv->mm.gtt_space;
 #line 101
     __cil_tmp50 = (unsigned long )min_size;
 #line 101
     __cil_tmp51 = dev_priv->mm.gtt_mappable_end;
 #line 101
     drm_mm_init_scan_with_range(__cil_tmp49, __cil_tmp50, alignment, 0UL, __cil_tmp51);
     }
   } else {
     {
 #line 105
     __cil_tmp52 = & dev_priv->mm.gtt_space;
 #line 105
     __cil_tmp53 = (unsigned long )min_size;
 #line 105
     drm_mm_init_scan(__cil_tmp52, __cil_tmp53, alignment);
     }
   }
 #line 108
   __cil_tmp54 = dev_priv->mm.inactive_list.next;
 #line 108
   __mptr = (struct list_head  const  *)__cil_tmp54;
 #line 108
   __cil_tmp55 = (struct drm_i915_gem_object *)__mptr;
 #line 108
   obj = __cil_tmp55 + 1152921504606846800UL;
 #line 108
   goto ldv_37077;
   ldv_37076: 
   {
 #line 109
   tmp___1 = mark_free(obj, & unwind_list);
   }
 #line 109
   if ((int )tmp___1) {
 #line 110
     goto found;
   } else {
 
   }
 #line 108
   __cil_tmp56 = obj->mm_list.next;
 #line 108
   __mptr___0 = (struct list_head  const  *)__cil_tmp56;
 #line 108
   __cil_tmp57 = (struct drm_i915_gem_object *)__mptr___0;
 #line 108
   obj = __cil_tmp57 + 1152921504606846800UL;
   ldv_37077: ;
   {
 #line 108
   __cil_tmp58 = & dev_priv->mm.inactive_list;
 #line 108
   __cil_tmp59 = (unsigned long )__cil_tmp58;
 #line 108
   __cil_tmp60 = & obj->mm_list;
 #line 108
   __cil_tmp61 = (unsigned long )__cil_tmp60;
 #line 108
   if (__cil_tmp61 != __cil_tmp59) {
 #line 109
     goto ldv_37076;
   } else {
 #line 111
     goto ldv_37078;
   }
   }
   ldv_37078: 
 #line 114
   __cil_tmp62 = dev_priv->mm.active_list.next;
 #line 114
   __mptr___1 = (struct list_head  const  *)__cil_tmp62;
 #line 114
   __cil_tmp63 = (struct drm_i915_gem_object *)__mptr___1;
 #line 114
   obj = __cil_tmp63 + 1152921504606846800UL;
 #line 114
   goto ldv_37085;
   ldv_37084: ;
   {
 #line 116
   __cil_tmp64 = obj->base.write_domain;
 #line 116
   if (__cil_tmp64 != 0U) {
 #line 117
     goto ldv_37083;
   } else {
     {
 #line 116
     __cil_tmp65 = (unsigned int *)obj;
 #line 116
     __cil_tmp66 = __cil_tmp65 + 56UL;
 #line 116
     __cil_tmp67 = *__cil_tmp66;
 #line 116
     if (__cil_tmp67 != 0U) {
 #line 117
       goto ldv_37083;
     } else {
 
     }
     }
   }
   }
   {
 #line 119
   tmp___2 = mark_free(obj, & unwind_list);
   }
 #line 119
   if ((int )tmp___2) {
 #line 120
     goto found;
   } else {
 
   }
   ldv_37083: 
 #line 114
   __cil_tmp68 = obj->mm_list.next;
 #line 114
   __mptr___2 = (struct list_head  const  *)__cil_tmp68;
 #line 114
   __cil_tmp69 = (struct drm_i915_gem_object *)__mptr___2;
 #line 114
   obj = __cil_tmp69 + 1152921504606846800UL;
   ldv_37085: ;
   {
 #line 114
   __cil_tmp70 = & dev_priv->mm.active_list;
 #line 114
   __cil_tmp71 = (unsigned long )__cil_tmp70;
 #line 114
   __cil_tmp72 = & obj->mm_list;
 #line 114
   __cil_tmp73 = (unsigned long )__cil_tmp72;
 #line 114
   if (__cil_tmp73 != __cil_tmp71) {
 #line 115
     goto ldv_37084;
   } else {
 #line 117
     goto ldv_37086;
   }
   }
   ldv_37086: 
 #line 124
   __cil_tmp74 = dev_priv->mm.flushing_list.next;
 #line 124
   __mptr___3 = (struct list_head  const  *)__cil_tmp74;
 #line 124
   __cil_tmp75 = (struct drm_i915_gem_object *)__mptr___3;
 #line 124
   obj = __cil_tmp75 + 1152921504606846800UL;
 #line 124
   goto ldv_37093;
   ldv_37092: ;
   {
 #line 125
   __cil_tmp76 = (unsigned int *)obj;
 #line 125
   __cil_tmp77 = __cil_tmp76 + 56UL;
 #line 125
   __cil_tmp78 = *__cil_tmp77;
 #line 125
   if (__cil_tmp78 != 0U) {
 #line 126
     goto ldv_37091;
   } else {
 
   }
   }
   {
 #line 128
   tmp___3 = mark_free(obj, & unwind_list);
   }
 #line 128
   if ((int )tmp___3) {
 #line 129
     goto found;
   } else {
 
   }
   ldv_37091: 
 #line 124
   __cil_tmp79 = obj->mm_list.next;
 #line 124
   __mptr___4 = (struct list_head  const  *)__cil_tmp79;
 #line 124
   __cil_tmp80 = (struct drm_i915_gem_object *)__mptr___4;
 #line 124
   obj = __cil_tmp80 + 1152921504606846800UL;
   ldv_37093: ;
   {
 #line 124
   __cil_tmp81 = & dev_priv->mm.flushing_list;
 #line 124
   __cil_tmp82 = (unsigned long )__cil_tmp81;
 #line 124
   __cil_tmp83 = & obj->mm_list;
 #line 124
   __cil_tmp84 = (unsigned long )__cil_tmp83;
 #line 124
   if (__cil_tmp84 != __cil_tmp82) {
 #line 125
     goto ldv_37092;
   } else {
 #line 127
     goto ldv_37094;
   }
   }
   ldv_37094: 
 #line 131
   __cil_tmp85 = dev_priv->mm.active_list.next;
 #line 131
   __mptr___5 = (struct list_head  const  *)__cil_tmp85;
 #line 131
   __cil_tmp86 = (struct drm_i915_gem_object *)__mptr___5;
 #line 131
   obj = __cil_tmp86 + 1152921504606846800UL;
 #line 131
   goto ldv_37101;
   ldv_37100: ;
   {
 #line 132
   __cil_tmp87 = obj->base.write_domain;
 #line 132
   if (__cil_tmp87 == 0U) {
 #line 133
     goto ldv_37099;
   } else {
     {
 #line 132
     __cil_tmp88 = (unsigned int *)obj;
 #line 132
     __cil_tmp89 = __cil_tmp88 + 56UL;
 #line 132
     __cil_tmp90 = *__cil_tmp89;
 #line 132
     if (__cil_tmp90 != 0U) {
 #line 133
       goto ldv_37099;
     } else {
 
     }
     }
   }
   }
   {
 #line 135
   tmp___4 = mark_free(obj, & unwind_list);
   }
 #line 135
   if ((int )tmp___4) {
 #line 136
     goto found;
   } else {
 
   }
   ldv_37099: 
 #line 131
   __cil_tmp91 = obj->mm_list.next;
 #line 131
   __mptr___6 = (struct list_head  const  *)__cil_tmp91;
 #line 131
   __cil_tmp92 = (struct drm_i915_gem_object *)__mptr___6;
 #line 131
   obj = __cil_tmp92 + 1152921504606846800UL;
   ldv_37101: ;
   {
 #line 131
   __cil_tmp93 = & dev_priv->mm.active_list;
 #line 131
   __cil_tmp94 = (unsigned long )__cil_tmp93;
 #line 131
   __cil_tmp95 = & obj->mm_list;
 #line 131
   __cil_tmp96 = (unsigned long )__cil_tmp95;
 #line 131
   if (__cil_tmp96 != __cil_tmp94) {
 #line 132
     goto ldv_37100;
   } else {
 #line 134
     goto ldv_37102;
   }
   }
   ldv_37102: ;
 #line 140
   goto ldv_37107;
   ldv_37106: 
   {
 #line 141
   __mptr___7 = (struct list_head  const  *)unwind_list.next;
 #line 141
   __cil_tmp97 = (struct drm_i915_gem_object *)__mptr___7;
 #line 141
   obj = __cil_tmp97 + 1152921504606846768UL;
 #line 145
   __cil_tmp98 = obj->gtt_space;
 #line 145
   ret = drm_mm_scan_remove_block(__cil_tmp98);
 #line 146
   __cil_tmp99 = ret != 0;
 #line 146
   __cil_tmp100 = (long )__cil_tmp99;
 #line 146
   tmp___5 = __builtin_expect(__cil_tmp100, 0L);
   }
 #line 146
   if (tmp___5 != 0L) {
 #line 146
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_evict.c.p"),
                          "i" (146), "i" (12UL));
     ldv_37105: ;
 #line 146
     goto ldv_37105;
   } else {
 
   }
   {
 #line 148
   __cil_tmp101 = & obj->exec_list;
 #line 148
   list_del_init(__cil_tmp101);
 #line 149
   __cil_tmp102 = & obj->base;
 #line 149
   drm_gem_object_unreference(__cil_tmp102);
   }
   ldv_37107: 
   {
 #line 140
   __cil_tmp103 = (struct list_head  const  *)(& unwind_list);
 #line 140
   tmp___6 = list_empty(__cil_tmp103);
   }
 #line 140
   if (tmp___6 == 0) {
 #line 141
     goto ldv_37106;
   } else {
 #line 143
     goto ldv_37108;
   }
   ldv_37108: ;
 #line 155
   return (-28);
   found: 
   {
 #line 161
   INIT_LIST_HEAD(& eviction_list);
   }
 #line 162
   goto ldv_37111;
   ldv_37112: 
   {
 #line 163
   __mptr___8 = (struct list_head  const  *)unwind_list.next;
 #line 163
   __cil_tmp104 = (struct drm_i915_gem_object *)__mptr___8;
 #line 163
   obj = __cil_tmp104 + 1152921504606846768UL;
 #line 166
   __cil_tmp105 = obj->gtt_space;
 #line 166
   tmp___7 = drm_mm_scan_remove_block(__cil_tmp105);
   }
 #line 166
   if (tmp___7 != 0) {
     {
 #line 167
     __cil_tmp106 = & obj->exec_list;
 #line 167
     list_move(__cil_tmp106, & eviction_list);
     }
 #line 168
     goto ldv_37111;
   } else {
 
   }
   {
 #line 170
   __cil_tmp107 = & obj->exec_list;
 #line 170
   list_del_init(__cil_tmp107);
 #line 171
   __cil_tmp108 = & obj->base;
 #line 171
   drm_gem_object_unreference(__cil_tmp108);
   }
   ldv_37111: 
   {
 #line 162
   __cil_tmp109 = (struct list_head  const  *)(& unwind_list);
 #line 162
   tmp___8 = list_empty(__cil_tmp109);
   }
 #line 162
   if (tmp___8 == 0) {
 #line 163
     goto ldv_37112;
   } else {
 #line 165
     goto ldv_37113;
   }
   ldv_37113: ;
 #line 175
   goto ldv_37117;
   ldv_37116: 
 #line 176
   __mptr___9 = (struct list_head  const  *)eviction_list.next;
 #line 176
   __cil_tmp110 = (struct drm_i915_gem_object *)__mptr___9;
 #line 176
   obj = __cil_tmp110 + 1152921504606846768UL;
 #line 179
   if (ret == 0) {
     {
 #line 180
     ret = i915_gem_object_unbind(obj);
     }
   } else {
 
   }
   {
 #line 182
   __cil_tmp111 = & obj->exec_list;
 #line 182
   list_del_init(__cil_tmp111);
 #line 183
   __cil_tmp112 = & obj->base;
 #line 183
   drm_gem_object_unreference(__cil_tmp112);
   }
   ldv_37117: 
   {
 #line 175
   __cil_tmp113 = (struct list_head  const  *)(& eviction_list);
 #line 175
   tmp___9 = list_empty(__cil_tmp113);
   }
 #line 175
   if (tmp___9 == 0) {
 #line 176
     goto ldv_37116;
   } else {
 #line 178
     goto ldv_37118;
   }
   ldv_37118: ;
 #line 186
   return (ret);
 }
 }
 #line 190 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_evict.c.p"
 int i915_gem_evict_everything(struct drm_device *dev , bool purgeable_only ) 
 { drm_i915_private_t *dev_priv ;
   int ret ;
   bool lists_empty ;
   int tmp ;
   int tmp___0 ;
   int tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   long tmp___4 ;
   int tmp___5 ;
   void *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct list_head  const  *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   struct list_head  const  *__cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   struct list_head  const  *__cil_tmp19 ;
   int __cil_tmp20 ;
   bool __cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct list_head  const  *__cil_tmp23 ;
   int __cil_tmp24 ;
   long __cil_tmp25 ;
   int __cil_tmp26 ;
   bool __cil_tmp27 ;
 
   {
   {
 #line 192
   __cil_tmp13 = dev->dev_private;
 #line 192
   dev_priv = (drm_i915_private_t *)__cil_tmp13;
 #line 196
   __cil_tmp14 = & dev_priv->mm.inactive_list;
 #line 196
   __cil_tmp15 = (struct list_head  const  *)__cil_tmp14;
 #line 196
   tmp = list_empty(__cil_tmp15);
   }
 #line 196
   if (tmp != 0) {
     {
 #line 196
     __cil_tmp16 = & dev_priv->mm.flushing_list;
 #line 196
     __cil_tmp17 = (struct list_head  const  *)__cil_tmp16;
 #line 196
     tmp___0 = list_empty(__cil_tmp17);
     }
 #line 196
     if (tmp___0 != 0) {
       {
 #line 196
       __cil_tmp18 = & dev_priv->mm.active_list;
 #line 196
       __cil_tmp19 = (struct list_head  const  *)__cil_tmp18;
 #line 196
       tmp___1 = list_empty(__cil_tmp19);
       }
 #line 196
       if (tmp___1 != 0) {
 #line 196
         tmp___2 = 1;
       } else {
 #line 196
         tmp___2 = 0;
       }
     } else {
 #line 196
       tmp___2 = 0;
     }
   } else {
 #line 196
     tmp___2 = 0;
   }
 #line 196
   lists_empty = (bool )tmp___2;
 #line 199
   if ((int )lists_empty) {
 #line 200
     return (-28);
   } else {
 
   }
   {
 #line 202
   __cil_tmp20 = (int )purgeable_only;
 #line 202
   __cil_tmp21 = (bool )__cil_tmp20;
 #line 202
   trace_i915_gem_evict_everything(dev, __cil_tmp21);
 #line 205
   ret = i915_gpu_idle(dev);
   }
 #line 206
   if (ret != 0) {
 #line 207
     return (ret);
   } else {
 
   }
   {
 #line 209
   __cil_tmp22 = & dev_priv->mm.flushing_list;
 #line 209
   __cil_tmp23 = (struct list_head  const  *)__cil_tmp22;
 #line 209
   tmp___3 = list_empty(__cil_tmp23);
 #line 209
   __cil_tmp24 = tmp___3 == 0;
 #line 209
   __cil_tmp25 = (long )__cil_tmp24;
 #line 209
   tmp___4 = __builtin_expect(__cil_tmp25, 0L);
   }
 #line 209
   if (tmp___4 != 0L) {
 #line 209
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_evict.c.p"),
                          "i" (209), "i" (12UL));
     ldv_37126: ;
 #line 209
     goto ldv_37126;
   } else {
 
   }
   {
 #line 211
   __cil_tmp26 = (int )purgeable_only;
 #line 211
   __cil_tmp27 = (bool )__cil_tmp26;
 #line 211
   tmp___5 = i915_gem_evict_inactive(dev, __cil_tmp27);
   }
 #line 211
   return (tmp___5);
 }
 }
 #line 216 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_evict.c.p"
 int i915_gem_evict_inactive(struct drm_device *dev , bool purgeable_only ) 
 { drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_object *obj ;
   struct drm_i915_gem_object *next ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   int ret ;
   int tmp ;
   struct list_head  const  *__mptr___1 ;
   void *__cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct drm_i915_gem_object *__cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct drm_i915_gem_object *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   struct drm_i915_gem_object *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
 
   {
 #line 218
   __cil_tmp11 = dev->dev_private;
 #line 218
   dev_priv = (drm_i915_private_t *)__cil_tmp11;
 #line 221
   __cil_tmp12 = dev_priv->mm.inactive_list.next;
 #line 221
   __mptr = (struct list_head  const  *)__cil_tmp12;
 #line 221
   __cil_tmp13 = (struct drm_i915_gem_object *)__mptr;
 #line 221
   obj = __cil_tmp13 + 1152921504606846800UL;
 #line 221
   __cil_tmp14 = obj->mm_list.next;
 #line 221
   __mptr___0 = (struct list_head  const  *)__cil_tmp14;
 #line 221
   __cil_tmp15 = (struct drm_i915_gem_object *)__mptr___0;
 #line 221
   next = __cil_tmp15 + 1152921504606846800UL;
 #line 221
   goto ldv_37142;
   ldv_37141: ;
 #line 223
   if (! purgeable_only) {
 #line 223
     goto _L;
   } else {
     {
 #line 223
     __cil_tmp16 = (unsigned char *)obj;
 #line 223
     __cil_tmp17 = __cil_tmp16 + 225UL;
 #line 223
     __cil_tmp18 = *__cil_tmp17;
 #line 223
     __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 223
     if (__cil_tmp19 != 0U) {
       _L: 
       {
 #line 224
       tmp = i915_gem_object_unbind(obj);
 #line 224
       ret = tmp;
       }
 #line 225
       if (ret != 0) {
 #line 226
         return (ret);
       } else {
 
       }
     } else {
 
     }
     }
   }
 #line 221
   obj = next;
 #line 221
   __cil_tmp20 = next->mm_list.next;
 #line 221
   __mptr___1 = (struct list_head  const  *)__cil_tmp20;
 #line 221
   __cil_tmp21 = (struct drm_i915_gem_object *)__mptr___1;
 #line 221
   next = __cil_tmp21 + 1152921504606846800UL;
   ldv_37142: ;
   {
 #line 221
   __cil_tmp22 = & dev_priv->mm.inactive_list;
 #line 221
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 221
   __cil_tmp24 = & obj->mm_list;
 #line 221
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 221
   if (__cil_tmp25 != __cil_tmp23) {
 #line 222
     goto ldv_37141;
   } else {
 #line 224
     goto ldv_37143;
   }
   }
   ldv_37143: ;
 #line 230
   return (0);
 }
 }
 #line 273 "include/linux/list.h"
 __inline static void __list_splice(struct list_head  const  *list , struct list_head *prev ,
                                    struct list_head *next ) 
 { struct list_head *first ;
   struct list_head *last ;
   struct list_head *__cil_tmp6 ;
   struct list_head *__cil_tmp7 ;
 
   {
 #line 277
   __cil_tmp6 = list->next;
 #line 277
   first = (struct list_head *)__cil_tmp6;
 #line 278
   __cil_tmp7 = list->prev;
 #line 278
   last = (struct list_head *)__cil_tmp7;
 #line 280
   first->prev = prev;
 #line 281
   prev->next = first;
 #line 283
   last->next = next;
 #line 284
   next->prev = last;
 #line 285
   return;
 }
 }
 #line 292 "include/linux/list.h"
 __inline static void list_splice(struct list_head  const  *list , struct list_head *head ) 
 { int tmp ;
   struct list_head *__cil_tmp4 ;
 
   {
   {
 #line 295
   tmp = list_empty(list);
   }
 #line 295
   if (tmp == 0) {
     {
 #line 296
     __cil_tmp4 = head->next;
 #line 296
     __list_splice(list, head, __cil_tmp4);
     }
   } else {
 
   }
 #line 297
   return;
 }
 }
 #line 610 "include/linux/list.h"
 __inline static void hlist_add_head(struct hlist_node *n , struct hlist_head *h ) 
 { struct hlist_node *first ;
   struct hlist_node *__cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
 
   {
 #line 612
   first = h->first;
 #line 613
   n->next = first;
   {
 #line 614
   __cil_tmp4 = (struct hlist_node *)0;
 #line 614
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 614
   __cil_tmp6 = (unsigned long )first;
 #line 614
   if (__cil_tmp6 != __cil_tmp5) {
 #line 615
     first->pprev = & n->next;
   } else {
 
   }
   }
 #line 616
   h->first = n;
 #line 617
   n->pprev = & h->first;
 #line 618
   return;
 }
 }
 #line 118 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_ringbuffer.h"
 __inline static u32 intel_ring_sync_index(struct intel_ring_buffer *ring , struct intel_ring_buffer *other ) 
 { int idx ;
   long __cil_tmp4 ;
   long __cil_tmp5 ;
   long __cil_tmp6 ;
   long __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
 
   {
 #line 129
   __cil_tmp4 = (long )ring;
 #line 129
   __cil_tmp5 = (long )other;
 #line 129
   __cil_tmp6 = __cil_tmp5 - __cil_tmp4;
 #line 129
   __cil_tmp7 = __cil_tmp6 / 456L;
 #line 129
   __cil_tmp8 = (unsigned int )__cil_tmp7;
 #line 129
   __cil_tmp9 = __cil_tmp8 + 4294967295U;
 #line 129
   idx = (int )__cil_tmp9;
 #line 130
   if (idx < 0) {
 #line 131
     idx = idx + 3;
   } else {
 
   }
 #line 133
   return ((u32 )idx);
 }
 }
 #line 183
 int intel_ring_sync(struct intel_ring_buffer *ring , struct intel_ring_buffer *to ,
                     u32 seqno ) ;
 #line 254 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_ring_dispatch ;
 #line 254 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_gem_ring_dispatch(struct intel_ring_buffer *ring ,
                                                   u32 seqno ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , struct intel_ring_buffer * , u32  ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 235
   __cil_tmp11 = & __tracepoint_i915_gem_ring_dispatch.key;
 #line 235
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 235
   if ((int )tmp___1) {
     {
 #line 235
     rcu_read_lock_sched_notrace();
 #line 235
     __cil_tmp12 = & __tracepoint_i915_gem_ring_dispatch.funcs;
 #line 235
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 235
     __cil_tmp14 = *__cil_tmp13;
 #line 235
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 235
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 235
     if (tmp != 0) {
 #line 235
       if (! __warned) {
         {
 #line 235
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 235
         if (tmp___0 == 0) {
           {
 #line 235
           __warned = (bool )1;
 #line 235
           __cil_tmp15 = (int const   )254;
 #line 235
           __cil_tmp16 = (int )__cil_tmp15;
 #line 235
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 235
     it_func_ptr = _________p1;
     {
 #line 235
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 235
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 235
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 235
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36141: 
       {
 #line 235
       it_func = it_func_ptr->func;
 #line 235
       __data = it_func_ptr->data;
 #line 235
       __cil_tmp20 = (void (*)(void * , struct intel_ring_buffer * , u32  ))it_func;
 #line 235
       (*__cil_tmp20)(__data, ring, seqno);
 #line 235
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 235
       __cil_tmp21 = (void *)0;
 #line 235
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 235
       __cil_tmp23 = it_func_ptr->func;
 #line 235
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 235
       if (__cil_tmp24 != __cil_tmp22) {
 #line 236
         goto ldv_36141;
       } else {
 #line 238
         goto ldv_36142;
       }
       }
       ldv_36142: ;
     } else {
 
     }
     }
     {
 #line 235
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 237
   return;
 }
 }
 #line 248 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 void intel_mark_busy(struct drm_device *dev , struct drm_i915_gem_object *obj ) ;
 #line 162 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static void i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj , struct intel_ring_buffer *ring ,
                                               struct change_domains *cd ) 
 { uint32_t invalidate_domains ;
   uint32_t flush_domains ;
   int tmp ;
   uint32_t __cil_tmp7 ;
   uint32_t __cil_tmp8 ;
   uint32_t __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   uint32_t __cil_tmp12 ;
   uint32_t __cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   uint32_t __cil_tmp15 ;
   uint32_t __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct intel_ring_buffer *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   uint32_t __cil_tmp21 ;
   uint32_t __cil_tmp22 ;
   uint32_t __cil_tmp23 ;
   uint32_t __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   unsigned char *__cil_tmp26 ;
   unsigned char *__cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   uint32_t __cil_tmp34 ;
   uint32_t __cil_tmp35 ;
   uint32_t __cil_tmp36 ;
   uint32_t __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   uint32_t __cil_tmp39 ;
   uint32_t __cil_tmp40 ;
   uint32_t __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   int __cil_tmp44 ;
   uint32_t __cil_tmp45 ;
   atomic_t *__cil_tmp46 ;
   atomic_t const   *__cil_tmp47 ;
   uint32_t __cil_tmp48 ;
   uint32_t __cil_tmp49 ;
   uint32_t __cil_tmp50 ;
   uint32_t __cil_tmp51 ;
   uint32_t __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   struct intel_ring_buffer *__cil_tmp54 ;
   enum intel_ring_id __cil_tmp55 ;
   uint32_t __cil_tmp56 ;
   uint32_t __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   enum intel_ring_id __cil_tmp59 ;
   uint32_t __cil_tmp60 ;
   uint32_t __cil_tmp61 ;
 
   {
 #line 166
   invalidate_domains = 0U;
 #line 166
   flush_domains = 0U;
   {
 #line 172
   __cil_tmp7 = obj->base.pending_write_domain;
 #line 172
   if (__cil_tmp7 == 0U) {
 #line 173
     __cil_tmp8 = obj->base.read_domains;
 #line 173
     __cil_tmp9 = obj->base.pending_read_domains;
 #line 173
     obj->base.pending_read_domains = __cil_tmp9 | __cil_tmp8;
   } else {
 
   }
   }
   {
 #line 181
   __cil_tmp10 = obj->base.write_domain;
 #line 181
   if (__cil_tmp10 != 0U) {
     {
 #line 181
     __cil_tmp11 = obj->base.pending_read_domains;
 #line 181
     __cil_tmp12 = obj->base.write_domain;
 #line 181
     if (__cil_tmp12 != __cil_tmp11) {
 #line 185
       __cil_tmp13 = obj->base.write_domain;
 #line 185
       flush_domains = __cil_tmp13 | flush_domains;
 #line 186
       __cil_tmp14 = obj->base.write_domain;
 #line 186
       __cil_tmp15 = ~ __cil_tmp14;
 #line 186
       __cil_tmp16 = obj->base.pending_read_domains;
 #line 186
       __cil_tmp17 = __cil_tmp16 & __cil_tmp15;
 #line 186
       invalidate_domains = __cil_tmp17 | invalidate_domains;
     } else {
       {
 #line 181
       __cil_tmp18 = (unsigned long )ring;
 #line 181
       __cil_tmp19 = obj->ring;
 #line 181
       __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 181
       if (__cil_tmp20 != __cil_tmp18) {
 #line 185
         __cil_tmp21 = obj->base.write_domain;
 #line 185
         flush_domains = __cil_tmp21 | flush_domains;
 #line 186
         __cil_tmp22 = obj->base.write_domain;
 #line 186
         __cil_tmp23 = ~ __cil_tmp22;
 #line 186
         __cil_tmp24 = obj->base.pending_read_domains;
 #line 186
         __cil_tmp25 = __cil_tmp24 & __cil_tmp23;
 #line 186
         invalidate_domains = __cil_tmp25 | invalidate_domains;
       } else {
         {
 #line 181
         __cil_tmp26 = (unsigned char *)obj;
 #line 181
         __cil_tmp27 = __cil_tmp26 + 226UL;
 #line 181
         __cil_tmp28 = *__cil_tmp27;
 #line 181
         __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 181
         if (__cil_tmp29 != 0U) {
           {
 #line 181
           __cil_tmp30 = (unsigned char *)obj;
 #line 181
           __cil_tmp31 = __cil_tmp30 + 226UL;
 #line 181
           __cil_tmp32 = *__cil_tmp31;
 #line 181
           __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 181
           if (__cil_tmp33 == 0U) {
 #line 185
             __cil_tmp34 = obj->base.write_domain;
 #line 185
             flush_domains = __cil_tmp34 | flush_domains;
 #line 186
             __cil_tmp35 = obj->base.write_domain;
 #line 186
             __cil_tmp36 = ~ __cil_tmp35;
 #line 186
             __cil_tmp37 = obj->base.pending_read_domains;
 #line 186
             __cil_tmp38 = __cil_tmp37 & __cil_tmp36;
 #line 186
             invalidate_domains = __cil_tmp38 | invalidate_domains;
           } else {
 
           }
           }
         } else {
 
         }
         }
       }
       }
     }
     }
   } else {
 
   }
   }
 #line 193
   __cil_tmp39 = obj->base.read_domains;
 #line 193
   __cil_tmp40 = ~ __cil_tmp39;
 #line 193
   __cil_tmp41 = obj->base.pending_read_domains;
 #line 193
   __cil_tmp42 = __cil_tmp41 & __cil_tmp40;
 #line 193
   invalidate_domains = __cil_tmp42 | invalidate_domains;
   {
 #line 194
   __cil_tmp43 = flush_domains | invalidate_domains;
 #line 194
   __cil_tmp44 = (int )__cil_tmp43;
 #line 194
   if (__cil_tmp44 & 1) {
     {
 #line 195
     i915_gem_clflush_object(obj);
     }
   } else {
 
   }
   }
   {
 #line 197
   __cil_tmp45 = obj->base.pending_write_domain;
 #line 197
   if (__cil_tmp45 != 0U) {
     {
 #line 198
     __cil_tmp46 = & obj->pending_flip;
 #line 198
     __cil_tmp47 = (atomic_t const   *)__cil_tmp46;
 #line 198
     tmp = atomic_read(__cil_tmp47);
 #line 198
     __cil_tmp48 = (uint32_t )tmp;
 #line 198
     __cil_tmp49 = cd->flips;
 #line 198
     cd->flips = __cil_tmp49 | __cil_tmp48;
     }
   } else {
 
   }
   }
 #line 206
   if (flush_domains == 0U) {
     {
 #line 206
     __cil_tmp50 = obj->base.pending_write_domain;
 #line 206
     if (__cil_tmp50 == 0U) {
 #line 207
       obj->base.pending_write_domain = obj->base.write_domain;
     } else {
 
     }
     }
   } else {
 
   }
 #line 209
   __cil_tmp51 = cd->invalidate_domains;
 #line 209
   cd->invalidate_domains = __cil_tmp51 | invalidate_domains;
 #line 210
   __cil_tmp52 = cd->flush_domains;
 #line 210
   cd->flush_domains = __cil_tmp52 | flush_domains;
   {
 #line 211
   __cil_tmp53 = flush_domains & 4294967230U;
 #line 211
   if (__cil_tmp53 != 0U) {
 #line 212
     __cil_tmp54 = obj->ring;
 #line 212
     __cil_tmp55 = __cil_tmp54->id;
 #line 212
     __cil_tmp56 = (uint32_t )__cil_tmp55;
 #line 212
     __cil_tmp57 = cd->flush_rings;
 #line 212
     cd->flush_rings = __cil_tmp57 | __cil_tmp56;
   } else {
 
   }
   }
   {
 #line 213
   __cil_tmp58 = invalidate_domains & 4294967230U;
 #line 213
   if (__cil_tmp58 != 0U) {
 #line 214
     __cil_tmp59 = ring->id;
 #line 214
     __cil_tmp60 = (uint32_t )__cil_tmp59;
 #line 214
     __cil_tmp61 = cd->flush_rings;
 #line 214
     cd->flush_rings = __cil_tmp61 | __cil_tmp60;
   } else {
 
   }
   }
 #line 215
   return;
 }
 }
 #line 223 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static struct eb_objects *eb_create(int size ) 
 { struct eb_objects *eb ;
   int count ;
   void *tmp ;
   unsigned long __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct eb_objects *__cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
 
   {
 #line 226
   count = 256;
 #line 227
   goto ldv_37569;
   ldv_37568: 
 #line 228
   count = count >> 1;
   ldv_37569: ;
 #line 227
   if (count > size) {
 #line 228
     goto ldv_37568;
   } else {
 #line 230
     goto ldv_37570;
   }
   ldv_37570: 
   {
 #line 229
   __cil_tmp5 = (unsigned long )count;
 #line 229
   __cil_tmp6 = __cil_tmp5 + 1UL;
 #line 229
   __cil_tmp7 = __cil_tmp6 * 8UL;
 #line 229
   tmp = kzalloc(__cil_tmp7, 208U);
 #line 229
   eb = (struct eb_objects *)tmp;
   }
   {
 #line 232
   __cil_tmp8 = (struct eb_objects *)0;
 #line 232
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 232
   __cil_tmp10 = (unsigned long )eb;
 #line 232
   if (__cil_tmp10 == __cil_tmp9) {
 #line 233
     return (eb);
   } else {
 
   }
   }
 #line 235
   eb->and = count + -1;
 #line 236
   return (eb);
 }
 }
 #line 240 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static void eb_reset(struct eb_objects *eb ) 
 { struct hlist_head (*__cil_tmp2)[0U] ;
   void *__cil_tmp3 ;
   int __cil_tmp4 ;
   int __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
 
   {
   {
 #line 242
   __cil_tmp2 = & eb->buckets;
 #line 242
   __cil_tmp3 = (void *)__cil_tmp2;
 #line 242
   __cil_tmp4 = eb->and;
 #line 242
   __cil_tmp5 = __cil_tmp4 + 1;
 #line 242
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 242
   __cil_tmp7 = __cil_tmp6 * 8UL;
 #line 242
   memset(__cil_tmp3, 0, __cil_tmp7);
   }
 #line 243
   return;
 }
 }
 #line 246 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static void eb_add_object(struct eb_objects *eb , struct drm_i915_gem_object *obj ) 
 { struct hlist_node *__cil_tmp3 ;
   int __cil_tmp4 ;
   unsigned long __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   struct hlist_head (*__cil_tmp8)[0U] ;
   struct hlist_head *__cil_tmp9 ;
   struct hlist_head *__cil_tmp10 ;
 
   {
   {
 #line 248
   __cil_tmp3 = & obj->exec_node;
 #line 248
   __cil_tmp4 = eb->and;
 #line 248
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 248
   __cil_tmp6 = obj->exec_handle;
 #line 248
   __cil_tmp7 = __cil_tmp6 & __cil_tmp5;
 #line 248
   __cil_tmp8 = & eb->buckets;
 #line 248
   __cil_tmp9 = (struct hlist_head *)__cil_tmp8;
 #line 248
   __cil_tmp10 = __cil_tmp9 + __cil_tmp7;
 #line 248
   hlist_add_head(__cil_tmp3, __cil_tmp10);
   }
 #line 250
   return;
 }
 }
 #line 253 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static struct drm_i915_gem_object *eb_get_object(struct eb_objects *eb , unsigned long handle ) 
 { struct hlist_head *head ;
   struct hlist_node *node ;
   struct drm_i915_gem_object *obj ;
   struct hlist_node  const  *__mptr ;
   int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   struct hlist_head (*__cil_tmp10)[0U] ;
   struct hlist_head *__cil_tmp11 ;
   struct drm_i915_gem_object *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   struct hlist_node *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
 
   {
 #line 259
   __cil_tmp7 = eb->and;
 #line 259
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 259
   __cil_tmp9 = __cil_tmp8 & handle;
 #line 259
   __cil_tmp10 = & eb->buckets;
 #line 259
   __cil_tmp11 = (struct hlist_head *)__cil_tmp10;
 #line 259
   head = __cil_tmp11 + __cil_tmp9;
 #line 260
   node = head->first;
 #line 260
   goto ldv_37588;
   ldv_37587: 
 #line 261
   __mptr = (struct hlist_node  const  *)node;
 #line 261
   __cil_tmp12 = (struct drm_i915_gem_object *)__mptr;
 #line 261
   obj = __cil_tmp12 + 1152921504606846720UL;
   {
 #line 262
   __cil_tmp13 = obj->exec_handle;
 #line 262
   if (__cil_tmp13 == handle) {
 #line 263
     return (obj);
   } else {
 
   }
   }
 #line 260
   node = node->next;
   ldv_37588: ;
   {
 #line 260
   __cil_tmp14 = (struct hlist_node *)0;
 #line 260
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 260
   __cil_tmp16 = (unsigned long )node;
 #line 260
   if (__cil_tmp16 != __cil_tmp15) {
 #line 261
     goto ldv_37587;
   } else {
 #line 263
     goto ldv_37589;
   }
   }
   ldv_37589: ;
 #line 266
   return ((struct drm_i915_gem_object *)0);
 }
 }
 #line 270 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static void eb_destroy(struct eb_objects *eb ) 
 { void const   *__cil_tmp2 ;
 
   {
   {
 #line 272
   __cil_tmp2 = (void const   *)eb;
 #line 272
   kfree(__cil_tmp2);
   }
 #line 273
   return;
 }
 }
 #line 276 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj , struct eb_objects *eb ,
                                               struct drm_i915_gem_relocation_entry *reloc ) 
 { struct drm_device *dev ;
   struct drm_gem_object *target_obj ;
   uint32_t target_offset ;
   int ret ;
   struct drm_i915_gem_object *tmp ;
   long tmp___0 ;
   struct drm_gem_object  const  *__mptr ;
   long tmp___1 ;
   long tmp___2 ;
   long tmp___3 ;
   long tmp___4 ;
   long tmp___5 ;
   int tmp___6 ;
   long tmp___7 ;
   long tmp___8 ;
   long tmp___9 ;
   uint32_t page_offset___0 ;
   char *vaddr ;
   void *tmp___10 ;
   struct drm_i915_private *dev_priv ;
   uint32_t *reloc_entry ;
   void *reloc_page ;
   struct thread_info *tmp___11 ;
   __u32 __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_gem_object *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   int __cil_tmp32 ;
   long __cil_tmp33 ;
   struct drm_i915_gem_object *__cil_tmp34 ;
   int __cil_tmp35 ;
   long __cil_tmp36 ;
   __u32 __cil_tmp37 ;
   __u32 __cil_tmp38 ;
   __u32 __cil_tmp39 ;
   __u32 __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   int __cil_tmp42 ;
   long __cil_tmp43 ;
   __u32 __cil_tmp44 ;
   __u64 __cil_tmp45 ;
   int __cil_tmp46 ;
   __u32 __cil_tmp47 ;
   __u32 __cil_tmp48 ;
   __u32 __cil_tmp49 ;
   __u32 __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   int __cil_tmp52 ;
   long __cil_tmp53 ;
   long __cil_tmp54 ;
   __u32 __cil_tmp55 ;
   __u64 __cil_tmp56 ;
   int __cil_tmp57 ;
   __u32 __cil_tmp58 ;
   __u32 __cil_tmp59 ;
   __u32 __cil_tmp60 ;
   int __cil_tmp61 ;
   long __cil_tmp62 ;
   uint32_t __cil_tmp63 ;
   int __cil_tmp64 ;
   long __cil_tmp65 ;
   uint32_t __cil_tmp66 ;
   __u32 __cil_tmp67 ;
   int __cil_tmp68 ;
   long __cil_tmp69 ;
   __u32 __cil_tmp70 ;
   __u64 __cil_tmp71 ;
   int __cil_tmp72 ;
   __u32 __cil_tmp73 ;
   uint32_t __cil_tmp74 ;
   __u32 __cil_tmp75 ;
   uint32_t __cil_tmp76 ;
   __u32 __cil_tmp77 ;
   uint32_t __cil_tmp78 ;
   __u64 __cil_tmp79 ;
   __u64 __cil_tmp80 ;
   size_t __cil_tmp81 ;
   size_t __cil_tmp82 ;
   unsigned long long __cil_tmp83 ;
   __u64 __cil_tmp84 ;
   int __cil_tmp85 ;
   long __cil_tmp86 ;
   __u32 __cil_tmp87 ;
   __u64 __cil_tmp88 ;
   int __cil_tmp89 ;
   size_t __cil_tmp90 ;
   int __cil_tmp91 ;
   __u64 __cil_tmp92 ;
   unsigned long long __cil_tmp93 ;
   int __cil_tmp94 ;
   long __cil_tmp95 ;
   __u32 __cil_tmp96 ;
   __u64 __cil_tmp97 ;
   int __cil_tmp98 ;
   __u32 __cil_tmp99 ;
   uint32_t __cil_tmp100 ;
   __u64 __cil_tmp101 ;
   uint32_t __cil_tmp102 ;
   __u64 __cil_tmp103 ;
   __u64 __cil_tmp104 ;
   struct page **__cil_tmp105 ;
   struct page **__cil_tmp106 ;
   struct page *__cil_tmp107 ;
   unsigned long __cil_tmp108 ;
   uint32_t *__cil_tmp109 ;
   uint32_t *__cil_tmp110 ;
   void *__cil_tmp111 ;
   void *__cil_tmp112 ;
   unsigned char *__cil_tmp113 ;
   unsigned char *__cil_tmp114 ;
   unsigned char __cil_tmp115 ;
   unsigned int __cil_tmp116 ;
   int __cil_tmp117 ;
   int __cil_tmp118 ;
   bool __cil_tmp119 ;
   uint32_t __cil_tmp120 ;
   __u64 __cil_tmp121 ;
   __u64 __cil_tmp122 ;
   struct io_mapping *__cil_tmp123 ;
   __u64 __cil_tmp124 ;
   unsigned long __cil_tmp125 ;
   unsigned long __cil_tmp126 ;
   __u64 __cil_tmp127 ;
   unsigned long long __cil_tmp128 ;
   void *__cil_tmp129 ;
   __u32 __cil_tmp130 ;
   void *__cil_tmp131 ;
 
   {
   {
 #line 280
   dev = obj->base.dev;
 #line 283
   ret = -22;
 #line 286
   __cil_tmp27 = reloc->target_handle;
 #line 286
   __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 286
   tmp = eb_get_object(eb, __cil_tmp28);
 #line 286
   target_obj = & tmp->base;
 #line 287
   __cil_tmp29 = (struct drm_gem_object *)0;
 #line 287
   __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 287
   __cil_tmp31 = (unsigned long )target_obj;
 #line 287
   __cil_tmp32 = __cil_tmp31 == __cil_tmp30;
 #line 287
   __cil_tmp33 = (long )__cil_tmp32;
 #line 287
   tmp___0 = __builtin_expect(__cil_tmp33, 0L);
   }
 #line 287
   if (tmp___0 != 0L) {
 #line 288
     return (-2);
   } else {
 
   }
   {
 #line 290
   __mptr = (struct drm_gem_object  const  *)target_obj;
 #line 290
   __cil_tmp34 = (struct drm_i915_gem_object *)__mptr;
 #line 290
   target_offset = __cil_tmp34->gtt_offset;
 #line 295
   __cil_tmp35 = target_offset == 0U;
 #line 295
   __cil_tmp36 = (long )__cil_tmp35;
 #line 295
   tmp___1 = __builtin_expect(__cil_tmp36, 0L);
   }
 #line 295
   if (tmp___1 != 0L) {
     {
 #line 296
     __cil_tmp37 = reloc->target_handle;
 #line 296
     drm_err("i915_gem_execbuffer_relocate_entry", "No GTT space found for object %d\n",
             __cil_tmp37);
     }
 #line 298
     return (ret);
   } else {
 
   }
   {
 #line 302
   __cil_tmp38 = reloc->write_domain;
 #line 302
   __cil_tmp39 = __cil_tmp38 - 1U;
 #line 302
   __cil_tmp40 = reloc->write_domain;
 #line 302
   __cil_tmp41 = __cil_tmp40 & __cil_tmp39;
 #line 302
   __cil_tmp42 = __cil_tmp41 != 0U;
 #line 302
   __cil_tmp43 = (long )__cil_tmp42;
 #line 302
   tmp___2 = __builtin_expect(__cil_tmp43, 0L);
   }
 #line 302
   if (tmp___2 != 0L) {
     {
 #line 303
     __cil_tmp44 = reloc->target_handle;
 #line 303
     __cil_tmp45 = reloc->offset;
 #line 303
     __cil_tmp46 = (int )__cil_tmp45;
 #line 303
     __cil_tmp47 = reloc->read_domains;
 #line 303
     __cil_tmp48 = reloc->write_domain;
 #line 303
     drm_err("i915_gem_execbuffer_relocate_entry", "reloc with multiple write domains: obj %p target %d offset %d read %08x write %08x",
             obj, __cil_tmp44, __cil_tmp46, __cil_tmp47, __cil_tmp48);
     }
 #line 310
     return (ret);
   } else {
 
   }
   {
 #line 312
   __cil_tmp49 = reloc->read_domains;
 #line 312
   __cil_tmp50 = reloc->write_domain;
 #line 312
   __cil_tmp51 = __cil_tmp50 | __cil_tmp49;
 #line 312
   __cil_tmp52 = (int )__cil_tmp51;
 #line 312
   __cil_tmp53 = (long )__cil_tmp52;
 #line 312
   __cil_tmp54 = __cil_tmp53 & 1L;
 #line 312
   tmp___3 = __builtin_expect(__cil_tmp54, 0L);
   }
 #line 312
   if (tmp___3 != 0L) {
     {
 #line 313
     __cil_tmp55 = reloc->target_handle;
 #line 313
     __cil_tmp56 = reloc->offset;
 #line 313
     __cil_tmp57 = (int )__cil_tmp56;
 #line 313
     __cil_tmp58 = reloc->read_domains;
 #line 313
     __cil_tmp59 = reloc->write_domain;
 #line 313
     drm_err("i915_gem_execbuffer_relocate_entry", "reloc with read/write CPU domains: obj %p target %d offset %d read %08x write %08x",
             obj, __cil_tmp55, __cil_tmp57, __cil_tmp58, __cil_tmp59);
     }
 #line 320
     return (ret);
   } else {
 
   }
   {
 #line 322
   __cil_tmp60 = reloc->write_domain;
 #line 322
   __cil_tmp61 = __cil_tmp60 != 0U;
 #line 322
   __cil_tmp62 = (long )__cil_tmp61;
 #line 322
   tmp___4 = __builtin_expect(__cil_tmp62, 0L);
   }
 #line 322
   if (tmp___4 != 0L) {
     {
 #line 322
     __cil_tmp63 = target_obj->pending_write_domain;
 #line 322
     __cil_tmp64 = __cil_tmp63 != 0U;
 #line 322
     __cil_tmp65 = (long )__cil_tmp64;
 #line 322
     tmp___5 = __builtin_expect(__cil_tmp65, 0L);
     }
 #line 322
     if (tmp___5 != 0L) {
 #line 322
       tmp___6 = 1;
     } else {
 #line 322
       tmp___6 = 0;
     }
   } else {
 #line 322
     tmp___6 = 0;
   }
 #line 322
   if (tmp___6 != 0) {
     {
 #line 322
     __cil_tmp66 = target_obj->pending_write_domain;
 #line 322
     __cil_tmp67 = reloc->write_domain;
 #line 322
     __cil_tmp68 = __cil_tmp67 != __cil_tmp66;
 #line 322
     __cil_tmp69 = (long )__cil_tmp68;
 #line 322
     tmp___7 = __builtin_expect(__cil_tmp69, 0L);
     }
 #line 322
     if (tmp___7 != 0L) {
       {
 #line 324
       __cil_tmp70 = reloc->target_handle;
 #line 324
       __cil_tmp71 = reloc->offset;
 #line 324
       __cil_tmp72 = (int )__cil_tmp71;
 #line 324
       __cil_tmp73 = reloc->write_domain;
 #line 324
       __cil_tmp74 = target_obj->pending_write_domain;
 #line 324
       drm_err("i915_gem_execbuffer_relocate_entry", "Write domain conflict: obj %p target %d offset %d new %08x old %08x\n",
               obj, __cil_tmp70, __cil_tmp72, __cil_tmp73, __cil_tmp74);
       }
 #line 331
       return (ret);
     } else {
 
     }
   } else {
 
   }
 #line 334
   __cil_tmp75 = reloc->read_domains;
 #line 334
   __cil_tmp76 = target_obj->pending_read_domains;
 #line 334
   target_obj->pending_read_domains = __cil_tmp76 | __cil_tmp75;
 #line 335
   __cil_tmp77 = reloc->write_domain;
 #line 335
   __cil_tmp78 = target_obj->pending_write_domain;
 #line 335
   target_obj->pending_write_domain = __cil_tmp78 | __cil_tmp77;
   {
 #line 340
   __cil_tmp79 = reloc->presumed_offset;
 #line 340
   __cil_tmp80 = (__u64 )target_offset;
 #line 340
   if (__cil_tmp80 == __cil_tmp79) {
 #line 341
     return (0);
   } else {
 
   }
   }
   {
 #line 344
   __cil_tmp81 = obj->base.size;
 #line 344
   __cil_tmp82 = __cil_tmp81 - 4UL;
 #line 344
   __cil_tmp83 = (unsigned long long )__cil_tmp82;
 #line 344
   __cil_tmp84 = reloc->offset;
 #line 344
   __cil_tmp85 = __cil_tmp84 > __cil_tmp83;
 #line 344
   __cil_tmp86 = (long )__cil_tmp85;
 #line 344
   tmp___8 = __builtin_expect(__cil_tmp86, 0L);
   }
 #line 344
   if (tmp___8 != 0L) {
     {
 #line 345
     __cil_tmp87 = reloc->target_handle;
 #line 345
     __cil_tmp88 = reloc->offset;
 #line 345
     __cil_tmp89 = (int )__cil_tmp88;
 #line 345
     __cil_tmp90 = obj->base.size;
 #line 345
     __cil_tmp91 = (int )__cil_tmp90;
 #line 345
     drm_err("i915_gem_execbuffer_relocate_entry", "Relocation beyond object bounds: obj %p target %d offset %d size %d.\n",
             obj, __cil_tmp87, __cil_tmp89, __cil_tmp91);
     }
 #line 350
     return (ret);
   } else {
 
   }
   {
 #line 352
   __cil_tmp92 = reloc->offset;
 #line 352
   __cil_tmp93 = __cil_tmp92 & 3ULL;
 #line 352
   __cil_tmp94 = __cil_tmp93 != 0ULL;
 #line 352
   __cil_tmp95 = (long )__cil_tmp94;
 #line 352
   tmp___9 = __builtin_expect(__cil_tmp95, 0L);
   }
 #line 352
   if (tmp___9 != 0L) {
     {
 #line 353
     __cil_tmp96 = reloc->target_handle;
 #line 353
     __cil_tmp97 = reloc->offset;
 #line 353
     __cil_tmp98 = (int )__cil_tmp97;
 #line 353
     drm_err("i915_gem_execbuffer_relocate_entry", "Relocation not 4-byte aligned: obj %p target %d offset %d.\n",
             obj, __cil_tmp96, __cil_tmp98);
     }
 #line 357
     return (ret);
   } else {
 
   }
 #line 360
   __cil_tmp99 = reloc->delta;
 #line 360
   reloc->delta = __cil_tmp99 + target_offset;
   {
 #line 361
   __cil_tmp100 = obj->base.write_domain;
 #line 361
   if (__cil_tmp100 == 1U) {
     {
 #line 362
     __cil_tmp101 = reloc->offset;
 #line 362
     __cil_tmp102 = (uint32_t )__cil_tmp101;
 #line 362
     page_offset___0 = __cil_tmp102 & 4095U;
 #line 365
     __cil_tmp103 = reloc->offset;
 #line 365
     __cil_tmp104 = __cil_tmp103 >> 12;
 #line 365
     __cil_tmp105 = obj->pages;
 #line 365
     __cil_tmp106 = __cil_tmp105 + __cil_tmp104;
 #line 365
     __cil_tmp107 = *__cil_tmp106;
 #line 365
     tmp___10 = __kmap_atomic(__cil_tmp107);
 #line 365
     vaddr = (char *)tmp___10;
 #line 366
     __cil_tmp108 = (unsigned long )page_offset___0;
 #line 366
     __cil_tmp109 = (uint32_t *)vaddr;
 #line 366
     __cil_tmp110 = __cil_tmp109 + __cil_tmp108;
 #line 366
     *__cil_tmp110 = reloc->delta;
 #line 367
     __cil_tmp111 = (void *)vaddr;
 #line 367
     __kunmap_atomic(__cil_tmp111);
     }
   } else {
 #line 369
     __cil_tmp112 = dev->dev_private;
 #line 369
     dev_priv = (struct drm_i915_private *)__cil_tmp112;
     {
 #line 374
     __cil_tmp113 = (unsigned char *)obj;
 #line 374
     __cil_tmp114 = __cil_tmp113 + 224UL;
 #line 374
     __cil_tmp115 = *__cil_tmp114;
 #line 374
     __cil_tmp116 = (unsigned int )__cil_tmp115;
 #line 374
     if (__cil_tmp116 != 0U) {
       {
 #line 374
       tmp___11 = current_thread_info();
       }
       {
 #line 374
       __cil_tmp117 = tmp___11->preempt_count;
 #line 374
       __cil_tmp118 = __cil_tmp117 & -268435457;
 #line 374
       if (__cil_tmp118 != 0) {
 #line 375
         return (-14);
       } else {
 
       }
       }
     } else {
 
     }
     }
     {
 #line 377
     __cil_tmp119 = (bool )1;
 #line 377
     ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp119);
     }
 #line 378
     if (ret != 0) {
 #line 379
       return (ret);
     } else {
 
     }
     {
 #line 382
     __cil_tmp120 = obj->gtt_offset;
 #line 382
     __cil_tmp121 = (__u64 )__cil_tmp120;
 #line 382
     __cil_tmp122 = reloc->offset;
 #line 382
     reloc->offset = __cil_tmp122 + __cil_tmp121;
 #line 383
     __cil_tmp123 = dev_priv->mm.gtt_mapping;
 #line 383
     __cil_tmp124 = reloc->offset;
 #line 383
     __cil_tmp125 = (unsigned long )__cil_tmp124;
 #line 383
     __cil_tmp126 = __cil_tmp125 & 1152921504606842880UL;
 #line 383
     reloc_page = io_mapping_map_atomic_wc(__cil_tmp123, __cil_tmp126);
 #line 385
     __cil_tmp127 = reloc->offset;
 #line 385
     __cil_tmp128 = __cil_tmp127 & 4095ULL;
 #line 385
     __cil_tmp129 = reloc_page + __cil_tmp128;
 #line 385
     reloc_entry = (uint32_t *)__cil_tmp129;
 #line 387
     __cil_tmp130 = reloc->delta;
 #line 387
     __cil_tmp131 = (void *)reloc_entry;
 #line 387
     iowrite32(__cil_tmp130, __cil_tmp131);
 #line 388
     io_mapping_unmap_atomic(reloc_page);
     }
   }
   }
 #line 392
   reloc->presumed_offset = (__u64 )target_offset;
 #line 394
   return (0);
 }
 }
 #line 398 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj , struct eb_objects *eb ) 
 { struct drm_i915_gem_relocation_entry *user_relocs ;
   struct drm_i915_gem_exec_object2 *entry ;
   int i ;
   int ret ;
   struct drm_i915_gem_relocation_entry reloc ;
   int tmp ;
   int tmp___0 ;
   __u64 __cil_tmp10 ;
   void *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void const   *__cil_tmp13 ;
   void const   *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct drm_i915_gem_relocation_entry *__cil_tmp16 ;
   __u64 *__cil_tmp17 ;
   void *__cil_tmp18 ;
   __u64 *__cil_tmp19 ;
   void const   *__cil_tmp20 ;
   __u32 __cil_tmp21 ;
   __u32 __cil_tmp22 ;
 
   {
 #line 402
   entry = obj->exec_entry;
 #line 405
   __cil_tmp10 = entry->relocs_ptr;
 #line 405
   user_relocs = (struct drm_i915_gem_relocation_entry *)__cil_tmp10;
 #line 406
   i = 0;
 #line 406
   goto ldv_37620;
   ldv_37619: 
   {
 #line 409
   __cil_tmp11 = (void *)(& reloc);
 #line 409
   __cil_tmp12 = (unsigned long )i;
 #line 409
   __cil_tmp13 = (void const   *)user_relocs;
 #line 409
   __cil_tmp14 = __cil_tmp13 + __cil_tmp12;
 #line 409
   tmp = __copy_from_user_inatomic(__cil_tmp11, __cil_tmp14, 32U);
   }
 #line 409
   if (tmp != 0) {
 #line 412
     return (-14);
   } else {
 
   }
   {
 #line 414
   ret = i915_gem_execbuffer_relocate_entry(obj, eb, & reloc);
   }
 #line 415
   if (ret != 0) {
 #line 416
     return (ret);
   } else {
 
   }
   {
 #line 418
   __cil_tmp15 = (unsigned long )i;
 #line 418
   __cil_tmp16 = user_relocs + __cil_tmp15;
 #line 418
   __cil_tmp17 = & __cil_tmp16->presumed_offset;
 #line 418
   __cil_tmp18 = (void *)__cil_tmp17;
 #line 418
   __cil_tmp19 = & reloc.presumed_offset;
 #line 418
   __cil_tmp20 = (void const   *)__cil_tmp19;
 #line 418
   tmp___0 = __copy_from_user_inatomic(__cil_tmp18, __cil_tmp20, 8U);
   }
 #line 418
   if (tmp___0 != 0) {
 #line 421
     return (-14);
   } else {
 
   }
 #line 406
   i = i + 1;
   ldv_37620: ;
   {
 #line 406
   __cil_tmp21 = entry->relocation_count;
 #line 406
   __cil_tmp22 = (__u32 )i;
 #line 406
   if (__cil_tmp22 < __cil_tmp21) {
 #line 407
     goto ldv_37619;
   } else {
 #line 409
     goto ldv_37621;
   }
   }
   ldv_37621: ;
 #line 424
   return (0);
 }
 }
 #line 428 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj ,
                                                     struct eb_objects *eb , struct drm_i915_gem_relocation_entry *relocs ) 
 { struct drm_i915_gem_exec_object2  const  *entry ;
   int i ;
   int ret ;
   struct drm_i915_gem_exec_object2 *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_i915_gem_relocation_entry *__cil_tmp9 ;
   __u32 __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
 
   {
 #line 432
   __cil_tmp7 = obj->exec_entry;
 #line 432
   entry = (struct drm_i915_gem_exec_object2  const  *)__cil_tmp7;
 #line 435
   i = 0;
 #line 435
   goto ldv_37631;
   ldv_37630: 
   {
 #line 436
   __cil_tmp8 = (unsigned long )i;
 #line 436
   __cil_tmp9 = relocs + __cil_tmp8;
 #line 436
   ret = i915_gem_execbuffer_relocate_entry(obj, eb, __cil_tmp9);
   }
 #line 437
   if (ret != 0) {
 #line 438
     return (ret);
   } else {
 
   }
 #line 435
   i = i + 1;
   ldv_37631: ;
   {
 #line 435
   __cil_tmp10 = entry->relocation_count;
 #line 435
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 435
   __cil_tmp12 = (unsigned int )i;
 #line 435
   if (__cil_tmp12 < __cil_tmp11) {
 #line 436
     goto ldv_37630;
   } else {
 #line 438
     goto ldv_37632;
   }
   }
   ldv_37632: ;
 #line 441
   return (0);
 }
 }
 #line 445 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_relocate(struct drm_device *dev , struct eb_objects *eb ,
                                         struct list_head *objects ) 
 { struct drm_i915_gem_object *obj ;
   int ret ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head *__cil_tmp8 ;
   struct drm_i915_gem_object *__cil_tmp9 ;
   struct list_head *__cil_tmp10 ;
   struct drm_i915_gem_object *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
 
   {
   {
 #line 450
   ret = 0;
 #line 459
   pagefault_disable();
 #line 460
   __cil_tmp8 = objects->next;
 #line 460
   __mptr = (struct list_head  const  *)__cil_tmp8;
 #line 460
   __cil_tmp9 = (struct drm_i915_gem_object *)__mptr;
 #line 460
   obj = __cil_tmp9 + 1152921504606846768UL;
   }
 #line 460
   goto ldv_37646;
   ldv_37645: 
   {
 #line 461
   ret = i915_gem_execbuffer_relocate_object(obj, eb);
   }
 #line 462
   if (ret != 0) {
 #line 463
     goto ldv_37644;
   } else {
 
   }
 #line 460
   __cil_tmp10 = obj->exec_list.next;
 #line 460
   __mptr___0 = (struct list_head  const  *)__cil_tmp10;
 #line 460
   __cil_tmp11 = (struct drm_i915_gem_object *)__mptr___0;
 #line 460
   obj = __cil_tmp11 + 1152921504606846768UL;
   ldv_37646: ;
   {
 #line 460
   __cil_tmp12 = (unsigned long )objects;
 #line 460
   __cil_tmp13 = & obj->exec_list;
 #line 460
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 460
   if (__cil_tmp14 != __cil_tmp12) {
 #line 461
     goto ldv_37645;
   } else {
 #line 463
     goto ldv_37644;
   }
   }
   ldv_37644: 
   {
 #line 465
   pagefault_enable();
   }
 #line 467
   return (ret);
 }
 }
 #line 471 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring , struct drm_file *file ,
                                        struct list_head *objects ) 
 { struct drm_i915_gem_object *obj ;
   int ret ;
   int retry ;
   bool has_fenced_gpu_access ;
   struct list_head ordered_objects ;
   struct drm_i915_gem_exec_object2 *entry ;
   bool need_fence ;
   bool need_mappable ;
   struct list_head  const  *__mptr ;
   int tmp ;
   int tmp___0 ;
   int tmp___1 ;
   struct list_head  const  *__mptr___0 ;
   struct drm_i915_gem_exec_object2 *entry___0 ;
   bool need_fence___0 ;
   bool need_mappable___0 ;
   int tmp___2 ;
   int tmp___3 ;
   struct list_head  const  *__mptr___1 ;
   struct list_head  const  *__mptr___2 ;
   struct drm_i915_gem_exec_object2 *entry___1 ;
   bool need_fence___1 ;
   int tmp___4 ;
   bool need_mappable___1 ;
   int tmp___5 ;
   struct list_head  const  *__mptr___3 ;
   struct list_head  const  *__mptr___4 ;
   struct list_head  const  *__mptr___5 ;
   struct list_head  const  *__mptr___6 ;
   struct list_head  const  *__mptr___7 ;
   struct drm_device *__cil_tmp34 ;
   void *__cil_tmp35 ;
   struct drm_i915_private *__cil_tmp36 ;
   struct intel_device_info  const  *__cil_tmp37 ;
   u8 __cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   int __cil_tmp41 ;
   struct list_head *__cil_tmp42 ;
   struct drm_i915_gem_object *__cil_tmp43 ;
   __u64 __cil_tmp44 ;
   int __cil_tmp45 ;
   unsigned char *__cil_tmp46 ;
   unsigned char *__cil_tmp47 ;
   unsigned char __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   __u32 __cil_tmp50 ;
   int __cil_tmp51 ;
   struct list_head *__cil_tmp52 ;
   struct list_head *__cil_tmp53 ;
   struct list_head  const  *__cil_tmp54 ;
   struct list_head  const  *__cil_tmp55 ;
   struct list_head *__cil_tmp56 ;
   struct drm_i915_gem_object *__cil_tmp57 ;
   struct drm_mm_node *__cil_tmp58 ;
   unsigned long __cil_tmp59 ;
   struct drm_mm_node *__cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   __u64 __cil_tmp62 ;
   int __cil_tmp63 ;
   unsigned char *__cil_tmp64 ;
   unsigned char *__cil_tmp65 ;
   unsigned char __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   __u32 __cil_tmp68 ;
   int __cil_tmp69 ;
   __u64 __cil_tmp70 ;
   __u64 __cil_tmp71 ;
   __u64 __cil_tmp72 ;
   uint32_t __cil_tmp73 ;
   __u64 __cil_tmp74 ;
   unsigned long long __cil_tmp75 ;
   unsigned char *__cil_tmp76 ;
   unsigned char *__cil_tmp77 ;
   unsigned char __cil_tmp78 ;
   unsigned int __cil_tmp79 ;
   __u64 __cil_tmp80 ;
   uint32_t __cil_tmp81 ;
   int __cil_tmp82 ;
   bool __cil_tmp83 ;
   __u64 __cil_tmp84 ;
   uint32_t __cil_tmp85 ;
   int __cil_tmp86 ;
   bool __cil_tmp87 ;
   struct list_head *__cil_tmp88 ;
   struct drm_i915_gem_object *__cil_tmp89 ;
   unsigned long __cil_tmp90 ;
   struct list_head *__cil_tmp91 ;
   unsigned long __cil_tmp92 ;
   struct list_head *__cil_tmp93 ;
   struct drm_i915_gem_object *__cil_tmp94 ;
   __u64 __cil_tmp95 ;
   int __cil_tmp96 ;
   unsigned char *__cil_tmp97 ;
   unsigned char *__cil_tmp98 ;
   unsigned char __cil_tmp99 ;
   unsigned int __cil_tmp100 ;
   struct drm_mm_node *__cil_tmp101 ;
   unsigned long __cil_tmp102 ;
   struct drm_mm_node *__cil_tmp103 ;
   unsigned long __cil_tmp104 ;
   __u32 __cil_tmp105 ;
   int __cil_tmp106 ;
   __u64 __cil_tmp107 ;
   uint32_t __cil_tmp108 ;
   int __cil_tmp109 ;
   bool __cil_tmp110 ;
   __u64 __cil_tmp111 ;
   int __cil_tmp112 ;
   unsigned char *__cil_tmp113 ;
   unsigned char *__cil_tmp114 ;
   unsigned char __cil_tmp115 ;
   unsigned int __cil_tmp116 ;
   uint32_t __cil_tmp117 ;
   struct list_head *__cil_tmp118 ;
   struct drm_i915_gem_object *__cil_tmp119 ;
   unsigned long __cil_tmp120 ;
   struct list_head *__cil_tmp121 ;
   unsigned long __cil_tmp122 ;
   struct list_head *__cil_tmp123 ;
   struct drm_i915_gem_object *__cil_tmp124 ;
   struct drm_mm_node *__cil_tmp125 ;
   unsigned long __cil_tmp126 ;
   struct drm_mm_node *__cil_tmp127 ;
   unsigned long __cil_tmp128 ;
   struct list_head *__cil_tmp129 ;
   struct drm_i915_gem_object *__cil_tmp130 ;
   unsigned long __cil_tmp131 ;
   struct list_head *__cil_tmp132 ;
   unsigned long __cil_tmp133 ;
   struct drm_device *__cil_tmp134 ;
   int __cil_tmp135 ;
   bool __cil_tmp136 ;
   struct list_head *__cil_tmp137 ;
   struct drm_i915_gem_object *__cil_tmp138 ;
   struct drm_mm_node *__cil_tmp139 ;
   unsigned long __cil_tmp140 ;
   struct drm_mm_node *__cil_tmp141 ;
   unsigned long __cil_tmp142 ;
   struct list_head *__cil_tmp143 ;
   struct drm_i915_gem_object *__cil_tmp144 ;
   unsigned long __cil_tmp145 ;
   struct list_head *__cil_tmp146 ;
   unsigned long __cil_tmp147 ;
 
   {
   {
 #line 477
   __cil_tmp34 = ring->dev;
 #line 477
   __cil_tmp35 = __cil_tmp34->dev_private;
 #line 477
   __cil_tmp36 = (struct drm_i915_private *)__cil_tmp35;
 #line 477
   __cil_tmp37 = __cil_tmp36->info;
 #line 477
   __cil_tmp38 = __cil_tmp37->gen;
 #line 477
   __cil_tmp39 = (unsigned char )__cil_tmp38;
 #line 477
   __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 477
   __cil_tmp41 = __cil_tmp40 <= 3U;
 #line 477
   has_fenced_gpu_access = (bool )__cil_tmp41;
 #line 480
   INIT_LIST_HEAD(& ordered_objects);
   }
 #line 481
   goto ldv_37663;
   ldv_37662: 
 #line 485
   __cil_tmp42 = objects->next;
 #line 485
   __mptr = (struct list_head  const  *)__cil_tmp42;
 #line 485
   __cil_tmp43 = (struct drm_i915_gem_object *)__mptr;
 #line 485
   obj = __cil_tmp43 + 1152921504606846768UL;
 #line 488
   entry = obj->exec_entry;
 #line 490
   if ((int )has_fenced_gpu_access) {
     {
 #line 490
     __cil_tmp44 = entry->flags;
 #line 490
     __cil_tmp45 = (int )__cil_tmp44;
 #line 490
     if (__cil_tmp45 & 1) {
       {
 #line 490
       __cil_tmp46 = (unsigned char *)obj;
 #line 490
       __cil_tmp47 = __cil_tmp46 + 225UL;
 #line 490
       __cil_tmp48 = *__cil_tmp47;
 #line 490
       __cil_tmp49 = (unsigned int )__cil_tmp48;
 #line 490
       if (__cil_tmp49 != 0U) {
 #line 490
         tmp = 1;
       } else {
 #line 490
         tmp = 0;
       }
       }
     } else {
 #line 490
       tmp = 0;
     }
     }
   } else {
 #line 490
     tmp = 0;
   }
 #line 490
   need_fence = (bool )tmp;
   {
 #line 494
   __cil_tmp50 = entry->relocation_count;
 #line 494
   if (__cil_tmp50 != 0U) {
 #line 494
     tmp___0 = 1;
   } else {
     {
 #line 494
     __cil_tmp51 = (int )need_fence;
 #line 494
     if (__cil_tmp51 != 0) {
 #line 494
       tmp___0 = 1;
     } else {
 #line 494
       tmp___0 = 0;
     }
     }
   }
   }
 #line 494
   need_mappable = (bool )tmp___0;
 #line 497
   if ((int )need_mappable) {
     {
 #line 498
     __cil_tmp52 = & obj->exec_list;
 #line 498
     list_move(__cil_tmp52, & ordered_objects);
     }
   } else {
     {
 #line 500
     __cil_tmp53 = & obj->exec_list;
 #line 500
     list_move_tail(__cil_tmp53, & ordered_objects);
     }
   }
 #line 502
   obj->base.pending_read_domains = 0U;
 #line 503
   obj->base.pending_write_domain = 0U;
   ldv_37663: 
   {
 #line 481
   __cil_tmp54 = (struct list_head  const  *)objects;
 #line 481
   tmp___1 = list_empty(__cil_tmp54);
   }
 #line 481
   if (tmp___1 == 0) {
 #line 482
     goto ldv_37662;
   } else {
 #line 484
     goto ldv_37664;
   }
   ldv_37664: 
   {
 #line 505
   __cil_tmp55 = (struct list_head  const  *)(& ordered_objects);
 #line 505
   list_splice(__cil_tmp55, objects);
 #line 519
   retry = 0;
   }
   ldv_37694: 
 #line 521
   ret = 0;
 #line 524
   __cil_tmp56 = objects->next;
 #line 524
   __mptr___0 = (struct list_head  const  *)__cil_tmp56;
 #line 524
   __cil_tmp57 = (struct drm_i915_gem_object *)__mptr___0;
 #line 524
   obj = __cil_tmp57 + 1152921504606846768UL;
 #line 524
   goto ldv_37675;
   ldv_37674: 
 #line 525
   entry___0 = obj->exec_entry;
   {
 #line 527
   __cil_tmp58 = (struct drm_mm_node *)0;
 #line 527
   __cil_tmp59 = (unsigned long )__cil_tmp58;
 #line 527
   __cil_tmp60 = obj->gtt_space;
 #line 527
   __cil_tmp61 = (unsigned long )__cil_tmp60;
 #line 527
   if (__cil_tmp61 == __cil_tmp59) {
 #line 528
     goto ldv_37672;
   } else {
 
   }
   }
 #line 530
   if ((int )has_fenced_gpu_access) {
     {
 #line 530
     __cil_tmp62 = entry___0->flags;
 #line 530
     __cil_tmp63 = (int )__cil_tmp62;
 #line 530
     if (__cil_tmp63 & 1) {
       {
 #line 530
       __cil_tmp64 = (unsigned char *)obj;
 #line 530
       __cil_tmp65 = __cil_tmp64 + 225UL;
 #line 530
       __cil_tmp66 = *__cil_tmp65;
 #line 530
       __cil_tmp67 = (unsigned int )__cil_tmp66;
 #line 530
       if (__cil_tmp67 != 0U) {
 #line 530
         tmp___2 = 1;
       } else {
 #line 530
         tmp___2 = 0;
       }
       }
     } else {
 #line 530
       tmp___2 = 0;
     }
     }
   } else {
 #line 530
     tmp___2 = 0;
   }
 #line 530
   need_fence___0 = (bool )tmp___2;
   {
 #line 534
   __cil_tmp68 = entry___0->relocation_count;
 #line 534
   if (__cil_tmp68 != 0U) {
 #line 534
     tmp___3 = 1;
   } else {
     {
 #line 534
     __cil_tmp69 = (int )need_fence___0;
 #line 534
     if (__cil_tmp69 != 0) {
 #line 534
       tmp___3 = 1;
     } else {
 #line 534
       tmp___3 = 0;
     }
     }
   }
   }
 #line 534
   need_mappable___0 = (bool )tmp___3;
   {
 #line 537
   __cil_tmp70 = entry___0->alignment;
 #line 537
   if (__cil_tmp70 != 0ULL) {
     {
 #line 537
     __cil_tmp71 = entry___0->alignment;
 #line 537
     __cil_tmp72 = __cil_tmp71 - 1ULL;
 #line 537
     __cil_tmp73 = obj->gtt_offset;
 #line 537
     __cil_tmp74 = (__u64 )__cil_tmp73;
 #line 537
     __cil_tmp75 = __cil_tmp74 & __cil_tmp72;
 #line 537
     if (__cil_tmp75 != 0ULL) {
       {
 #line 539
       ret = i915_gem_object_unbind(obj);
       }
     } else {
 #line 537
       goto _L;
     }
     }
   } else
   _L: 
 #line 537
   if ((int )need_mappable___0) {
     {
 #line 537
     __cil_tmp76 = (unsigned char *)obj;
 #line 537
     __cil_tmp77 = __cil_tmp76 + 226UL;
 #line 537
     __cil_tmp78 = *__cil_tmp77;
 #line 537
     __cil_tmp79 = (unsigned int )__cil_tmp78;
 #line 537
     if (__cil_tmp79 == 0U) {
       {
 #line 539
       ret = i915_gem_object_unbind(obj);
       }
     } else {
       {
 #line 541
       __cil_tmp80 = entry___0->alignment;
 #line 541
       __cil_tmp81 = (uint32_t )__cil_tmp80;
 #line 541
       __cil_tmp82 = (int )need_mappable___0;
 #line 541
       __cil_tmp83 = (bool )__cil_tmp82;
 #line 541
       ret = i915_gem_object_pin(obj, __cil_tmp81, __cil_tmp83);
       }
     }
     }
   } else {
     {
 #line 541
     __cil_tmp84 = entry___0->alignment;
 #line 541
     __cil_tmp85 = (uint32_t )__cil_tmp84;
 #line 541
     __cil_tmp86 = (int )need_mappable___0;
 #line 541
     __cil_tmp87 = (bool )__cil_tmp86;
 #line 541
     ret = i915_gem_object_pin(obj, __cil_tmp85, __cil_tmp87);
     }
   }
   }
 #line 544
   if (ret != 0) {
 #line 545
     goto err;
   } else {
 
   }
 #line 547
   entry___0 = entry___0 + 1;
   ldv_37672: 
 #line 524
   __cil_tmp88 = obj->exec_list.next;
 #line 524
   __mptr___1 = (struct list_head  const  *)__cil_tmp88;
 #line 524
   __cil_tmp89 = (struct drm_i915_gem_object *)__mptr___1;
 #line 524
   obj = __cil_tmp89 + 1152921504606846768UL;
   ldv_37675: ;
   {
 #line 524
   __cil_tmp90 = (unsigned long )objects;
 #line 524
   __cil_tmp91 = & obj->exec_list;
 #line 524
   __cil_tmp92 = (unsigned long )__cil_tmp91;
 #line 524
   if (__cil_tmp92 != __cil_tmp90) {
 #line 525
     goto ldv_37674;
   } else {
 #line 527
     goto ldv_37676;
   }
   }
   ldv_37676: 
 #line 551
   __cil_tmp93 = objects->next;
 #line 551
   __mptr___2 = (struct list_head  const  *)__cil_tmp93;
 #line 551
   __cil_tmp94 = (struct drm_i915_gem_object *)__mptr___2;
 #line 551
   obj = __cil_tmp94 + 1152921504606846768UL;
 #line 551
   goto ldv_37686;
   ldv_37685: 
 #line 552
   entry___1 = obj->exec_entry;
 #line 555
   if ((int )has_fenced_gpu_access) {
     {
 #line 555
     __cil_tmp95 = entry___1->flags;
 #line 555
     __cil_tmp96 = (int )__cil_tmp95;
 #line 555
     if (__cil_tmp96 & 1) {
       {
 #line 555
       __cil_tmp97 = (unsigned char *)obj;
 #line 555
       __cil_tmp98 = __cil_tmp97 + 225UL;
 #line 555
       __cil_tmp99 = *__cil_tmp98;
 #line 555
       __cil_tmp100 = (unsigned int )__cil_tmp99;
 #line 555
       if (__cil_tmp100 != 0U) {
 #line 555
         tmp___4 = 1;
       } else {
 #line 555
         tmp___4 = 0;
       }
       }
     } else {
 #line 555
       tmp___4 = 0;
     }
     }
   } else {
 #line 555
     tmp___4 = 0;
   }
 #line 555
   need_fence___1 = (bool )tmp___4;
   {
 #line 560
   __cil_tmp101 = (struct drm_mm_node *)0;
 #line 560
   __cil_tmp102 = (unsigned long )__cil_tmp101;
 #line 560
   __cil_tmp103 = obj->gtt_space;
 #line 560
   __cil_tmp104 = (unsigned long )__cil_tmp103;
 #line 560
   if (__cil_tmp104 == __cil_tmp102) {
     {
 #line 561
     __cil_tmp105 = entry___1->relocation_count;
 #line 561
     if (__cil_tmp105 != 0U) {
 #line 561
       tmp___5 = 1;
     } else {
       {
 #line 561
       __cil_tmp106 = (int )need_fence___1;
 #line 561
       if (__cil_tmp106 != 0) {
 #line 561
         tmp___5 = 1;
       } else {
 #line 561
         tmp___5 = 0;
       }
       }
     }
     }
     {
 #line 561
     need_mappable___1 = (bool )tmp___5;
 #line 564
     __cil_tmp107 = entry___1->alignment;
 #line 564
     __cil_tmp108 = (uint32_t )__cil_tmp107;
 #line 564
     __cil_tmp109 = (int )need_mappable___1;
 #line 564
     __cil_tmp110 = (bool )__cil_tmp109;
 #line 564
     ret = i915_gem_object_pin(obj, __cil_tmp108, __cil_tmp110);
     }
 #line 567
     if (ret != 0) {
 #line 568
       goto ldv_37684;
     } else {
 
     }
   } else {
 
   }
   }
 #line 571
   if ((int )has_fenced_gpu_access) {
 #line 572
     if ((int )need_fence___1) {
       {
 #line 573
       ret = i915_gem_object_get_fence(obj, ring);
       }
 #line 574
       if (ret != 0) {
 #line 575
         goto ldv_37684;
       } else {
 
       }
     } else {
       {
 #line 576
       __cil_tmp111 = entry___1->flags;
 #line 576
       __cil_tmp112 = (int )__cil_tmp111;
 #line 576
       if (__cil_tmp112 & 1) {
         {
 #line 576
         __cil_tmp113 = (unsigned char *)obj;
 #line 576
         __cil_tmp114 = __cil_tmp113 + 225UL;
 #line 576
         __cil_tmp115 = *__cil_tmp114;
 #line 576
         __cil_tmp116 = (unsigned int )__cil_tmp115;
 #line 576
         if (__cil_tmp116 == 0U) {
           {
 #line 579
           ret = i915_gem_object_put_fence(obj);
           }
 #line 580
           if (ret != 0) {
 #line 581
             goto ldv_37684;
           } else {
 
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     }
 #line 583
     obj->pending_fenced_gpu_access = (unsigned char )need_fence___1;
   } else {
 
   }
 #line 586
   __cil_tmp117 = obj->gtt_offset;
 #line 586
   entry___1->offset = (__u64 )__cil_tmp117;
 #line 551
   __cil_tmp118 = obj->exec_list.next;
 #line 551
   __mptr___3 = (struct list_head  const  *)__cil_tmp118;
 #line 551
   __cil_tmp119 = (struct drm_i915_gem_object *)__mptr___3;
 #line 551
   obj = __cil_tmp119 + 1152921504606846768UL;
   ldv_37686: ;
   {
 #line 551
   __cil_tmp120 = (unsigned long )objects;
 #line 551
   __cil_tmp121 = & obj->exec_list;
 #line 551
   __cil_tmp122 = (unsigned long )__cil_tmp121;
 #line 551
   if (__cil_tmp122 != __cil_tmp120) {
 #line 552
     goto ldv_37685;
   } else {
 #line 554
     goto ldv_37684;
   }
   }
   ldv_37684: 
 #line 590
   __cil_tmp123 = objects->next;
 #line 590
   __mptr___4 = (struct list_head  const  *)__cil_tmp123;
 #line 590
   __cil_tmp124 = (struct drm_i915_gem_object *)__mptr___4;
 #line 590
   obj = __cil_tmp124 + 1152921504606846768UL;
 #line 590
   goto ldv_37692;
   ldv_37691: ;
   {
 #line 591
   __cil_tmp125 = (struct drm_mm_node *)0;
 #line 591
   __cil_tmp126 = (unsigned long )__cil_tmp125;
 #line 591
   __cil_tmp127 = obj->gtt_space;
 #line 591
   __cil_tmp128 = (unsigned long )__cil_tmp127;
 #line 591
   if (__cil_tmp128 != __cil_tmp126) {
     {
 #line 592
     i915_gem_object_unpin(obj);
     }
   } else {
 
   }
   }
 #line 590
   __cil_tmp129 = obj->exec_list.next;
 #line 590
   __mptr___5 = (struct list_head  const  *)__cil_tmp129;
 #line 590
   __cil_tmp130 = (struct drm_i915_gem_object *)__mptr___5;
 #line 590
   obj = __cil_tmp130 + 1152921504606846768UL;
   ldv_37692: ;
   {
 #line 590
   __cil_tmp131 = (unsigned long )objects;
 #line 590
   __cil_tmp132 = & obj->exec_list;
 #line 590
   __cil_tmp133 = (unsigned long )__cil_tmp132;
 #line 590
   if (__cil_tmp133 != __cil_tmp131) {
 #line 591
     goto ldv_37691;
   } else {
 #line 593
     goto ldv_37693;
   }
   }
   ldv_37693: ;
 #line 595
   if (ret != -28) {
 #line 596
     return (ret);
   } else
 #line 595
   if (retry > 1) {
 #line 596
     return (ret);
   } else {
 
   }
   {
 #line 601
   __cil_tmp134 = ring->dev;
 #line 601
   __cil_tmp135 = retry == 0;
 #line 601
   __cil_tmp136 = (bool )__cil_tmp135;
 #line 601
   ret = i915_gem_evict_everything(__cil_tmp134, __cil_tmp136);
   }
 #line 602
   if (ret != 0) {
 #line 603
     return (ret);
   } else {
 
   }
 #line 605
   retry = retry + 1;
 #line 606
   goto ldv_37694;
   err: 
 #line 609
   __cil_tmp137 = obj->exec_list.prev;
 #line 609
   __mptr___6 = (struct list_head  const  *)__cil_tmp137;
 #line 609
   __cil_tmp138 = (struct drm_i915_gem_object *)__mptr___6;
 #line 609
   obj = __cil_tmp138 + 1152921504606846768UL;
 #line 612
   goto ldv_37700;
   ldv_37699: ;
   {
 #line 613
   __cil_tmp139 = (struct drm_mm_node *)0;
 #line 613
   __cil_tmp140 = (unsigned long )__cil_tmp139;
 #line 613
   __cil_tmp141 = obj->gtt_space;
 #line 613
   __cil_tmp142 = (unsigned long )__cil_tmp141;
 #line 613
   if (__cil_tmp142 != __cil_tmp140) {
     {
 #line 614
     i915_gem_object_unpin(obj);
     }
   } else {
 
   }
   }
 #line 616
   __cil_tmp143 = obj->exec_list.prev;
 #line 616
   __mptr___7 = (struct list_head  const  *)__cil_tmp143;
 #line 616
   __cil_tmp144 = (struct drm_i915_gem_object *)__mptr___7;
 #line 616
   obj = __cil_tmp144 + 1152921504606846768UL;
   ldv_37700: ;
   {
 #line 612
   __cil_tmp145 = (unsigned long )objects;
 #line 612
   __cil_tmp146 = & obj->exec_list;
 #line 612
   __cil_tmp147 = (unsigned long )__cil_tmp146;
 #line 612
   if (__cil_tmp147 != __cil_tmp145) {
 #line 613
     goto ldv_37699;
   } else {
 #line 615
     goto ldv_37701;
   }
   }
   ldv_37701: ;
 #line 621
   return (ret);
 }
 }
 #line 625 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_relocate_slow(struct drm_device *dev , struct drm_file *file ,
                                              struct intel_ring_buffer *ring , struct list_head *objects ,
                                              struct eb_objects *eb , struct drm_i915_gem_exec_object2 *exec ,
                                              int count ) 
 { struct drm_i915_gem_relocation_entry *reloc ;
   struct drm_i915_gem_object *obj ;
   int *reloc_offset ;
   int i ;
   int total ;
   int ret ;
   struct list_head  const  *__mptr ;
   int tmp ;
   void *tmp___0 ;
   void *tmp___1 ;
   struct drm_i915_gem_relocation_entry *user_relocs ;
   unsigned long tmp___2 ;
   struct drm_gem_object  const  *__mptr___0 ;
   struct drm_gem_object *tmp___3 ;
   struct list_head  const  *__mptr___1 ;
   int offset ;
   struct list_head  const  *__mptr___2 ;
   struct list_head *__cil_tmp25 ;
   struct drm_i915_gem_object *__cil_tmp26 ;
   struct list_head *__cil_tmp27 ;
   struct drm_gem_object *__cil_tmp28 ;
   struct list_head  const  *__cil_tmp29 ;
   struct mutex *__cil_tmp30 ;
   __u32 __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp33 ;
   __u32 __cil_tmp34 ;
   __u32 __cil_tmp35 ;
   size_t __cil_tmp36 ;
   size_t __cil_tmp37 ;
   struct drm_i915_gem_relocation_entry *__cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   void *__cil_tmp41 ;
   void *__cil_tmp42 ;
   struct mutex *__cil_tmp43 ;
   int *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   void *__cil_tmp47 ;
   void *__cil_tmp48 ;
   struct mutex *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp51 ;
   __u64 __cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   void *__cil_tmp54 ;
   void *__cil_tmp55 ;
   void const   *__cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp58 ;
   __u32 __cil_tmp59 ;
   unsigned long __cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   struct mutex *__cil_tmp62 ;
   unsigned long __cil_tmp63 ;
   int *__cil_tmp64 ;
   __u32 __cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp67 ;
   __u32 __cil_tmp68 ;
   __u32 __cil_tmp69 ;
   struct mutex *__cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp72 ;
   __u32 __cil_tmp73 ;
   struct drm_gem_object *__cil_tmp74 ;
   unsigned long __cil_tmp75 ;
   struct drm_gem_object *__cil_tmp76 ;
   unsigned long __cil_tmp77 ;
   unsigned long __cil_tmp78 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp79 ;
   __u32 __cil_tmp80 ;
   struct list_head *__cil_tmp81 ;
   unsigned long __cil_tmp82 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp83 ;
   __u32 __cil_tmp84 ;
   unsigned long __cil_tmp85 ;
   struct list_head *__cil_tmp86 ;
   struct drm_i915_gem_object *__cil_tmp87 ;
   long __cil_tmp88 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp89 ;
   long __cil_tmp90 ;
   long __cil_tmp91 ;
   long __cil_tmp92 ;
   unsigned long __cil_tmp93 ;
   int *__cil_tmp94 ;
   int __cil_tmp95 ;
   unsigned long __cil_tmp96 ;
   struct drm_i915_gem_relocation_entry *__cil_tmp97 ;
   struct list_head *__cil_tmp98 ;
   struct drm_i915_gem_object *__cil_tmp99 ;
   unsigned long __cil_tmp100 ;
   struct list_head *__cil_tmp101 ;
   unsigned long __cil_tmp102 ;
   void *__cil_tmp103 ;
   void *__cil_tmp104 ;
 
   {
 #line 639
   goto ldv_37720;
   ldv_37719: 
   {
 #line 640
   __cil_tmp25 = objects->next;
 #line 640
   __mptr = (struct list_head  const  *)__cil_tmp25;
 #line 640
   __cil_tmp26 = (struct drm_i915_gem_object *)__mptr;
 #line 640
   obj = __cil_tmp26 + 1152921504606846768UL;
 #line 643
   __cil_tmp27 = & obj->exec_list;
 #line 643
   list_del_init(__cil_tmp27);
 #line 644
   __cil_tmp28 = & obj->base;
 #line 644
   drm_gem_object_unreference(__cil_tmp28);
   }
   ldv_37720: 
   {
 #line 639
   __cil_tmp29 = (struct list_head  const  *)objects;
 #line 639
   tmp = list_empty(__cil_tmp29);
   }
 #line 639
   if (tmp == 0) {
 #line 640
     goto ldv_37719;
   } else {
 #line 642
     goto ldv_37721;
   }
   ldv_37721: 
   {
 #line 647
   __cil_tmp30 = & dev->struct_mutex;
 #line 647
   mutex_unlock(__cil_tmp30);
 #line 649
   total = 0;
 #line 650
   i = 0;
   }
 #line 650
   goto ldv_37723;
   ldv_37722: 
 #line 651
   __cil_tmp31 = (__u32 )total;
 #line 651
   __cil_tmp32 = (unsigned long )i;
 #line 651
   __cil_tmp33 = exec + __cil_tmp32;
 #line 651
   __cil_tmp34 = __cil_tmp33->relocation_count;
 #line 651
   __cil_tmp35 = __cil_tmp34 + __cil_tmp31;
 #line 651
   total = (int )__cil_tmp35;
 #line 650
   i = i + 1;
   ldv_37723: ;
 #line 650
   if (i < count) {
 #line 651
     goto ldv_37722;
   } else {
 #line 653
     goto ldv_37724;
   }
   ldv_37724: 
   {
 #line 653
   __cil_tmp36 = (size_t )count;
 #line 653
   tmp___0 = drm_malloc_ab(__cil_tmp36, 4UL);
 #line 653
   reloc_offset = (int *)tmp___0;
 #line 654
   __cil_tmp37 = (size_t )total;
 #line 654
   tmp___1 = drm_malloc_ab(__cil_tmp37, 32UL);
 #line 654
   reloc = (struct drm_i915_gem_relocation_entry *)tmp___1;
   }
   {
 #line 655
   __cil_tmp38 = (struct drm_i915_gem_relocation_entry *)0;
 #line 655
   __cil_tmp39 = (unsigned long )__cil_tmp38;
 #line 655
   __cil_tmp40 = (unsigned long )reloc;
 #line 655
   if (__cil_tmp40 == __cil_tmp39) {
     {
 #line 656
     __cil_tmp41 = (void *)reloc;
 #line 656
     drm_free_large(__cil_tmp41);
 #line 657
     __cil_tmp42 = (void *)reloc_offset;
 #line 657
     drm_free_large(__cil_tmp42);
 #line 658
     __cil_tmp43 = & dev->struct_mutex;
 #line 658
     mutex_lock_nested(__cil_tmp43, 0U);
     }
 #line 659
     return (-12);
   } else {
     {
 #line 655
     __cil_tmp44 = (int *)0;
 #line 655
     __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 655
     __cil_tmp46 = (unsigned long )reloc_offset;
 #line 655
     if (__cil_tmp46 == __cil_tmp45) {
       {
 #line 656
       __cil_tmp47 = (void *)reloc;
 #line 656
       drm_free_large(__cil_tmp47);
 #line 657
       __cil_tmp48 = (void *)reloc_offset;
 #line 657
       drm_free_large(__cil_tmp48);
 #line 658
       __cil_tmp49 = & dev->struct_mutex;
 #line 658
       mutex_lock_nested(__cil_tmp49, 0U);
       }
 #line 659
       return (-12);
     } else {
 
     }
     }
   }
   }
 #line 662
   total = 0;
 #line 663
   i = 0;
 #line 663
   goto ldv_37728;
   ldv_37727: 
   {
 #line 666
   __cil_tmp50 = (unsigned long )i;
 #line 666
   __cil_tmp51 = exec + __cil_tmp50;
 #line 666
   __cil_tmp52 = __cil_tmp51->relocs_ptr;
 #line 666
   user_relocs = (struct drm_i915_gem_relocation_entry *)__cil_tmp52;
 #line 668
   __cil_tmp53 = (unsigned long )total;
 #line 668
   __cil_tmp54 = (void *)reloc;
 #line 668
   __cil_tmp55 = __cil_tmp54 + __cil_tmp53;
 #line 668
   __cil_tmp56 = (void const   *)user_relocs;
 #line 668
   __cil_tmp57 = (unsigned long )i;
 #line 668
   __cil_tmp58 = exec + __cil_tmp57;
 #line 668
   __cil_tmp59 = __cil_tmp58->relocation_count;
 #line 668
   __cil_tmp60 = (unsigned long )__cil_tmp59;
 #line 668
   __cil_tmp61 = __cil_tmp60 * 32UL;
 #line 668
   tmp___2 = copy_from_user(__cil_tmp55, __cil_tmp56, __cil_tmp61);
   }
 #line 668
   if (tmp___2 != 0UL) {
     {
 #line 670
     ret = -14;
 #line 671
     __cil_tmp62 = & dev->struct_mutex;
 #line 671
     mutex_lock_nested(__cil_tmp62, 0U);
     }
 #line 672
     goto err;
   } else {
 
   }
 #line 675
   __cil_tmp63 = (unsigned long )i;
 #line 675
   __cil_tmp64 = reloc_offset + __cil_tmp63;
 #line 675
   *__cil_tmp64 = total;
 #line 676
   __cil_tmp65 = (__u32 )total;
 #line 676
   __cil_tmp66 = (unsigned long )i;
 #line 676
   __cil_tmp67 = exec + __cil_tmp66;
 #line 676
   __cil_tmp68 = __cil_tmp67->relocation_count;
 #line 676
   __cil_tmp69 = __cil_tmp68 + __cil_tmp65;
 #line 676
   total = (int )__cil_tmp69;
 #line 663
   i = i + 1;
   ldv_37728: ;
 #line 663
   if (i < count) {
 #line 664
     goto ldv_37727;
   } else {
 #line 666
     goto ldv_37729;
   }
   ldv_37729: 
   {
 #line 679
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 680
   if (ret != 0) {
     {
 #line 681
     __cil_tmp70 = & dev->struct_mutex;
 #line 681
     mutex_lock_nested(__cil_tmp70, 0U);
     }
 #line 682
     goto err;
   } else {
 
   }
   {
 #line 686
   eb_reset(eb);
 #line 687
   i = 0;
   }
 #line 687
   goto ldv_37734;
   ldv_37733: 
   {
 #line 688
   __cil_tmp71 = (unsigned long )i;
 #line 688
   __cil_tmp72 = exec + __cil_tmp71;
 #line 688
   __cil_tmp73 = __cil_tmp72->handle;
 #line 688
   tmp___3 = drm_gem_object_lookup(dev, file, __cil_tmp73);
 #line 688
   __mptr___0 = (struct drm_gem_object  const  *)tmp___3;
 #line 688
   obj = (struct drm_i915_gem_object *)__mptr___0;
   }
   {
 #line 690
   __cil_tmp74 = (struct drm_gem_object *)0;
 #line 690
   __cil_tmp75 = (unsigned long )__cil_tmp74;
 #line 690
   __cil_tmp76 = & obj->base;
 #line 690
   __cil_tmp77 = (unsigned long )__cil_tmp76;
 #line 690
   if (__cil_tmp77 == __cil_tmp75) {
     {
 #line 691
     __cil_tmp78 = (unsigned long )i;
 #line 691
     __cil_tmp79 = exec + __cil_tmp78;
 #line 691
     __cil_tmp80 = __cil_tmp79->handle;
 #line 691
     drm_err("i915_gem_execbuffer_relocate_slow", "Invalid object handle %d at index %d\n",
             __cil_tmp80, i);
 #line 693
     ret = -2;
     }
 #line 694
     goto err;
   } else {
 
   }
   }
   {
 #line 697
   __cil_tmp81 = & obj->exec_list;
 #line 697
   list_add_tail(__cil_tmp81, objects);
 #line 698
   __cil_tmp82 = (unsigned long )i;
 #line 698
   __cil_tmp83 = exec + __cil_tmp82;
 #line 698
   __cil_tmp84 = __cil_tmp83->handle;
 #line 698
   obj->exec_handle = (unsigned long )__cil_tmp84;
 #line 699
   __cil_tmp85 = (unsigned long )i;
 #line 699
   obj->exec_entry = exec + __cil_tmp85;
 #line 700
   eb_add_object(eb, obj);
 #line 687
   i = i + 1;
   }
   ldv_37734: ;
 #line 687
   if (i < count) {
 #line 688
     goto ldv_37733;
   } else {
 #line 690
     goto ldv_37735;
   }
   ldv_37735: 
   {
 #line 703
   ret = i915_gem_execbuffer_reserve(ring, file, objects);
   }
 #line 704
   if (ret != 0) {
 #line 705
     goto err;
   } else {
 
   }
 #line 707
   __cil_tmp86 = objects->next;
 #line 707
   __mptr___1 = (struct list_head  const  *)__cil_tmp86;
 #line 707
   __cil_tmp87 = (struct drm_i915_gem_object *)__mptr___1;
 #line 707
   obj = __cil_tmp87 + 1152921504606846768UL;
 #line 707
   goto ldv_37742;
   ldv_37741: 
   {
 #line 708
   __cil_tmp88 = (long )exec;
 #line 708
   __cil_tmp89 = obj->exec_entry;
 #line 708
   __cil_tmp90 = (long )__cil_tmp89;
 #line 708
   __cil_tmp91 = __cil_tmp90 - __cil_tmp88;
 #line 708
   __cil_tmp92 = __cil_tmp91 / 56L;
 #line 708
   offset = (int )__cil_tmp92;
 #line 709
   __cil_tmp93 = (unsigned long )offset;
 #line 709
   __cil_tmp94 = reloc_offset + __cil_tmp93;
 #line 709
   __cil_tmp95 = *__cil_tmp94;
 #line 709
   __cil_tmp96 = (unsigned long )__cil_tmp95;
 #line 709
   __cil_tmp97 = reloc + __cil_tmp96;
 #line 709
   ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, __cil_tmp97);
   }
 #line 711
   if (ret != 0) {
 #line 712
     goto err;
   } else {
 
   }
 #line 707
   __cil_tmp98 = obj->exec_list.next;
 #line 707
   __mptr___2 = (struct list_head  const  *)__cil_tmp98;
 #line 707
   __cil_tmp99 = (struct drm_i915_gem_object *)__mptr___2;
 #line 707
   obj = __cil_tmp99 + 1152921504606846768UL;
   ldv_37742: ;
   {
 #line 707
   __cil_tmp100 = (unsigned long )objects;
 #line 707
   __cil_tmp101 = & obj->exec_list;
 #line 707
   __cil_tmp102 = (unsigned long )__cil_tmp101;
 #line 707
   if (__cil_tmp102 != __cil_tmp100) {
 #line 708
     goto ldv_37741;
   } else {
 #line 710
     goto ldv_37743;
   }
   }
   ldv_37743: ;
   err: 
   {
 #line 722
   __cil_tmp103 = (void *)reloc;
 #line 722
   drm_free_large(__cil_tmp103);
 #line 723
   __cil_tmp104 = (void *)reloc_offset;
 #line 723
   drm_free_large(__cil_tmp104);
   }
 #line 724
   return (ret);
 }
 }
 #line 728 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_flush(struct drm_device *dev , uint32_t invalidate_domains ,
                                      uint32_t flush_domains , uint32_t flush_rings ) 
 { drm_i915_private_t *dev_priv ;
   int i ;
   int ret ;
   void *__cil_tmp8 ;
   int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   int __cil_tmp13 ;
   uint32_t __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct intel_ring_buffer (*__cil_tmp17)[3U] ;
   struct intel_ring_buffer *__cil_tmp18 ;
   struct intel_ring_buffer *__cil_tmp19 ;
 
   {
 #line 733
   __cil_tmp8 = dev->dev_private;
 #line 733
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
   {
 #line 736
   __cil_tmp9 = (int )flush_domains;
 #line 736
   if (__cil_tmp9 & 1) {
     {
 #line 737
     intel_gtt_chipset_flush();
     }
   } else {
 
   }
   }
   {
 #line 739
   __cil_tmp10 = flush_domains & 64U;
 #line 739
   if (__cil_tmp10 != 0U) {
 #line 740
     __asm__  volatile   ("sfence": : : "memory");
   } else {
 
   }
   }
   {
 #line 742
   __cil_tmp11 = flush_domains | invalidate_domains;
 #line 742
   __cil_tmp12 = __cil_tmp11 & 4294967230U;
 #line 742
   if (__cil_tmp12 != 0U) {
 #line 743
     i = 0;
 #line 743
     goto ldv_37754;
     ldv_37753: ;
     {
 #line 744
     __cil_tmp13 = 1 << i;
 #line 744
     __cil_tmp14 = (uint32_t )__cil_tmp13;
 #line 744
     __cil_tmp15 = __cil_tmp14 & flush_rings;
 #line 744
     if (__cil_tmp15 != 0U) {
       {
 #line 745
       __cil_tmp16 = (unsigned long )i;
 #line 745
       __cil_tmp17 = & dev_priv->ring;
 #line 745
       __cil_tmp18 = (struct intel_ring_buffer *)__cil_tmp17;
 #line 745
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 745
       ret = i915_gem_flush_ring(__cil_tmp19, invalidate_domains, flush_domains);
       }
 #line 748
       if (ret != 0) {
 #line 749
         return (ret);
       } else {
 
       }
     } else {
 
     }
     }
 #line 743
     i = i + 1;
     ldv_37754: ;
 #line 743
     if (i <= 2) {
 #line 744
       goto ldv_37753;
     } else {
 #line 746
       goto ldv_37755;
     }
     ldv_37755: ;
   } else {
 
   }
   }
 #line 753
   return (0);
 }
 }
 #line 757 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj , struct intel_ring_buffer *to ) 
 { struct intel_ring_buffer *from ;
   u32 seqno ;
   int ret ;
   int idx ;
   int tmp ;
   u32 tmp___0 ;
   struct drm_i915_gem_request *request ;
   void *tmp___1 ;
   int tmp___2 ;
   struct intel_ring_buffer *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct drm_device *__cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   u8 __cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   u32 __cil_tmp24 ;
   u32 __cil_tmp25 ;
   struct drm_i915_gem_request *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_file *__cil_tmp29 ;
   void const   *__cil_tmp30 ;
   u32 __cil_tmp31 ;
 
   {
 #line 760
   from = obj->ring;
   {
 #line 764
   __cil_tmp12 = (struct intel_ring_buffer *)0;
 #line 764
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 764
   __cil_tmp14 = (unsigned long )from;
 #line 764
   if (__cil_tmp14 == __cil_tmp13) {
 #line 765
     return (0);
   } else {
     {
 #line 764
     __cil_tmp15 = (unsigned long )from;
 #line 764
     __cil_tmp16 = (unsigned long )to;
 #line 764
     if (__cil_tmp16 == __cil_tmp15) {
 #line 765
       return (0);
     } else {
 
     }
     }
   }
   }
   {
 #line 768
   __cil_tmp17 = obj->base.dev;
 #line 768
   __cil_tmp18 = __cil_tmp17->dev_private;
 #line 768
   __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 768
   __cil_tmp20 = __cil_tmp19->info;
 #line 768
   __cil_tmp21 = __cil_tmp20->gen;
 #line 768
   __cil_tmp22 = (unsigned char )__cil_tmp21;
 #line 768
   __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 768
   if (__cil_tmp23 <= 5U) {
     {
 #line 769
     tmp = i915_gem_object_wait_rendering(obj);
     }
 #line 769
     return (tmp);
   } else
 #line 768
   if (i915_semaphores == 0U) {
     {
 #line 769
     tmp = i915_gem_object_wait_rendering(obj);
     }
 #line 769
     return (tmp);
   } else {
 
   }
   }
   {
 #line 771
   tmp___0 = intel_ring_sync_index(from, to);
 #line 771
   idx = (int )tmp___0;
 #line 773
   seqno = obj->last_rendering_seqno;
   }
   {
 #line 774
   __cil_tmp24 = from->sync_seqno[idx];
 #line 774
   if (__cil_tmp24 >= seqno) {
 #line 775
     return (0);
   } else {
 
   }
   }
   {
 #line 777
   __cil_tmp25 = from->outstanding_lazy_request;
 #line 777
   if (__cil_tmp25 == seqno) {
     {
 #line 780
     tmp___1 = kzalloc(64UL, 208U);
 #line 780
     request = (struct drm_i915_gem_request *)tmp___1;
     }
     {
 #line 781
     __cil_tmp26 = (struct drm_i915_gem_request *)0;
 #line 781
     __cil_tmp27 = (unsigned long )__cil_tmp26;
 #line 781
     __cil_tmp28 = (unsigned long )request;
 #line 781
     if (__cil_tmp28 == __cil_tmp27) {
 #line 782
       return (-12);
     } else {
 
     }
     }
     {
 #line 784
     __cil_tmp29 = (struct drm_file *)0;
 #line 784
     ret = i915_add_request(from, __cil_tmp29, request);
     }
 #line 785
     if (ret != 0) {
       {
 #line 786
       __cil_tmp30 = (void const   *)request;
 #line 786
       kfree(__cil_tmp30);
       }
 #line 787
       return (ret);
     } else {
 
     }
 #line 790
     seqno = request->seqno;
   } else {
 
   }
   }
   {
 #line 793
   from->sync_seqno[idx] = seqno;
 #line 794
   __cil_tmp31 = seqno - 1U;
 #line 794
   tmp___2 = intel_ring_sync(to, from, __cil_tmp31);
   }
 #line 794
   return (tmp___2);
 }
 }
 #line 798 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring , u32 flips ) 
 { u32 plane ;
   u32 flip_mask ;
   int ret ;
   int __cil_tmp6 ;
   u32 __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   u32 __cil_tmp11 ;
 
   {
 #line 808
   plane = 0U;
 #line 808
   goto ldv_37774;
   ldv_37773: ;
   {
 #line 809
   __cil_tmp6 = (int )plane;
 #line 809
   __cil_tmp7 = flips >> __cil_tmp6;
 #line 809
   __cil_tmp8 = __cil_tmp7 & 1U;
 #line 809
   if (__cil_tmp8 == 0U) {
 #line 810
     goto ldv_37772;
   } else {
 
   }
   }
 #line 812
   if (plane != 0U) {
 #line 813
     flip_mask = 64U;
   } else {
 #line 815
     flip_mask = 4U;
   }
   {
 #line 817
   ret = intel_ring_begin(ring, 2);
   }
 #line 818
   if (ret != 0) {
 #line 819
     return (ret);
   } else {
 
   }
   {
 #line 821
   __cil_tmp9 = flip_mask | 25165824U;
 #line 821
   intel_ring_emit(ring, __cil_tmp9);
 #line 822
   intel_ring_emit(ring, 0U);
 #line 823
   intel_ring_advance(ring);
   }
   ldv_37772: 
 #line 808
   plane = plane + 1U;
   ldv_37774: ;
   {
 #line 808
   __cil_tmp10 = (int )plane;
 #line 808
   __cil_tmp11 = flips >> __cil_tmp10;
 #line 808
   if (__cil_tmp11 != 0U) {
 #line 809
     goto ldv_37773;
   } else {
 #line 811
     goto ldv_37775;
   }
   }
   ldv_37775: ;
 #line 826
   return (0);
 }
 }
 #line 831 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring , struct list_head *objects ) 
 { struct drm_i915_gem_object *obj ;
   struct change_domains cd ;
   int ret ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   struct list_head  const  *__mptr___2 ;
   void *__cil_tmp10 ;
   struct list_head *__cil_tmp11 ;
   struct drm_i915_gem_object *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct drm_i915_gem_object *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   struct drm_device *__cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   struct drm_i915_gem_object *__cil_tmp21 ;
   struct list_head *__cil_tmp22 ;
   struct drm_i915_gem_object *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct list_head *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
 
   {
   {
 #line 838
   __cil_tmp10 = (void *)(& cd);
 #line 838
   memset(__cil_tmp10, 0, 16UL);
 #line 839
   __cil_tmp11 = objects->next;
 #line 839
   __mptr = (struct list_head  const  *)__cil_tmp11;
 #line 839
   __cil_tmp12 = (struct drm_i915_gem_object *)__mptr;
 #line 839
   obj = __cil_tmp12 + 1152921504606846768UL;
   }
 #line 839
   goto ldv_37788;
   ldv_37787: 
   {
 #line 840
   i915_gem_object_set_to_gpu_domain(obj, ring, & cd);
 #line 839
   __cil_tmp13 = obj->exec_list.next;
 #line 839
   __mptr___0 = (struct list_head  const  *)__cil_tmp13;
 #line 839
   __cil_tmp14 = (struct drm_i915_gem_object *)__mptr___0;
 #line 839
   obj = __cil_tmp14 + 1152921504606846768UL;
   }
   ldv_37788: ;
   {
 #line 839
   __cil_tmp15 = (unsigned long )objects;
 #line 839
   __cil_tmp16 = & obj->exec_list;
 #line 839
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 839
   if (__cil_tmp17 != __cil_tmp15) {
 #line 840
     goto ldv_37787;
   } else {
 #line 842
     goto ldv_37789;
   }
   }
   ldv_37789: ;
   {
 #line 842
   __cil_tmp18 = cd.invalidate_domains | cd.flush_domains;
 #line 842
   if (__cil_tmp18 != 0U) {
     {
 #line 843
     __cil_tmp19 = ring->dev;
 #line 843
     ret = i915_gem_execbuffer_flush(__cil_tmp19, cd.invalidate_domains, cd.flush_domains,
                                     cd.flush_rings);
     }
 #line 847
     if (ret != 0) {
 #line 848
       return (ret);
     } else {
 
     }
   } else {
 
   }
   }
 #line 851
   if (cd.flips != 0U) {
     {
 #line 852
     ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
     }
 #line 853
     if (ret != 0) {
 #line 854
       return (ret);
     } else {
 
     }
   } else {
 
   }
 #line 857
   __cil_tmp20 = objects->next;
 #line 857
   __mptr___1 = (struct list_head  const  *)__cil_tmp20;
 #line 857
   __cil_tmp21 = (struct drm_i915_gem_object *)__mptr___1;
 #line 857
   obj = __cil_tmp21 + 1152921504606846768UL;
 #line 857
   goto ldv_37795;
   ldv_37794: 
   {
 #line 858
   ret = i915_gem_execbuffer_sync_rings(obj, ring);
   }
 #line 859
   if (ret != 0) {
 #line 860
     return (ret);
   } else {
 
   }
 #line 857
   __cil_tmp22 = obj->exec_list.next;
 #line 857
   __mptr___2 = (struct list_head  const  *)__cil_tmp22;
 #line 857
   __cil_tmp23 = (struct drm_i915_gem_object *)__mptr___2;
 #line 857
   obj = __cil_tmp23 + 1152921504606846768UL;
   ldv_37795: ;
   {
 #line 857
   __cil_tmp24 = (unsigned long )objects;
 #line 857
   __cil_tmp25 = & obj->exec_list;
 #line 857
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 857
   if (__cil_tmp26 != __cil_tmp24) {
 #line 858
     goto ldv_37794;
   } else {
 #line 860
     goto ldv_37796;
   }
   }
   ldv_37796: ;
 #line 863
   return (0);
 }
 }
 #line 867 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec ) 
 { __u32 __cil_tmp2 ;
   __u32 __cil_tmp3 ;
   unsigned int __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
 
   {
   {
 #line 869
   __cil_tmp2 = exec->batch_len;
 #line 869
   __cil_tmp3 = exec->batch_start_offset;
 #line 869
   __cil_tmp4 = __cil_tmp3 | __cil_tmp2;
 #line 869
   __cil_tmp5 = __cil_tmp4 & 7U;
 #line 869
   __cil_tmp6 = __cil_tmp5 == 0U;
 #line 869
   return ((bool )__cil_tmp6);
   }
 }
 }
 #line 873 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int validate_exec_list(struct drm_i915_gem_exec_object2 *exec , int count ) 
 { int i ;
   char *ptr ;
   int length ;
   unsigned long flag ;
   unsigned long roksum ;
   struct thread_info *tmp ;
   long tmp___0 ;
   unsigned long flag___0 ;
   unsigned long roksum___0 ;
   struct thread_info *tmp___1 ;
   long tmp___2 ;
   int tmp___3 ;
   unsigned long __cil_tmp15 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp16 ;
   __u64 __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp19 ;
   __u32 __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp22 ;
   __u32 __cil_tmp23 ;
   __u32 __cil_tmp24 ;
   int __cil_tmp25 ;
   long __cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
   char const   *__cil_tmp29 ;
 
   {
 #line 878
   i = 0;
 #line 878
   goto ldv_37814;
   ldv_37813: 
 #line 879
   __cil_tmp15 = (unsigned long )i;
 #line 879
   __cil_tmp16 = exec + __cil_tmp15;
 #line 879
   __cil_tmp17 = __cil_tmp16->relocs_ptr;
 #line 879
   ptr = (char *)__cil_tmp17;
   {
 #line 883
   __cil_tmp18 = (unsigned long )i;
 #line 883
   __cil_tmp19 = exec + __cil_tmp18;
 #line 883
   __cil_tmp20 = __cil_tmp19->relocation_count;
 #line 883
   if (__cil_tmp20 > 67108863U) {
 #line 885
     return (-22);
   } else {
 
   }
   }
   {
 #line 887
   __cil_tmp21 = (unsigned long )i;
 #line 887
   __cil_tmp22 = exec + __cil_tmp21;
 #line 887
   __cil_tmp23 = __cil_tmp22->relocation_count;
 #line 887
   __cil_tmp24 = __cil_tmp23 * 32U;
 #line 887
   length = (int )__cil_tmp24;
 #line 889
   tmp = current_thread_info();
 #line 889
   __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" (ptr),
             "g" ((long )length), "rm" (tmp->addr_limit.seg));
 #line 889
   __cil_tmp25 = flag == 0UL;
 #line 889
   __cil_tmp26 = (long )__cil_tmp25;
 #line 889
   tmp___0 = __builtin_expect(__cil_tmp26, 1L);
   }
 #line 889
   if (tmp___0 == 0L) {
 #line 890
     return (-14);
   } else {
 
   }
   {
 #line 893
   tmp___1 = current_thread_info();
 #line 893
   __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag___0), "=r" (roksum___0): "1" (ptr),
             "g" ((long )length), "rm" (tmp___1->addr_limit.seg));
 #line 893
   __cil_tmp27 = flag___0 == 0UL;
 #line 893
   __cil_tmp28 = (long )__cil_tmp27;
 #line 893
   tmp___2 = __builtin_expect(__cil_tmp28, 1L);
   }
 #line 893
   if (tmp___2 == 0L) {
 #line 894
     return (-14);
   } else {
 
   }
   {
 #line 896
   __cil_tmp29 = (char const   *)ptr;
 #line 896
   tmp___3 = fault_in_pages_readable(__cil_tmp29, length);
   }
 #line 896
   if (tmp___3 != 0) {
 #line 897
     return (-14);
   } else {
 
   }
 #line 878
   i = i + 1;
   ldv_37814: ;
 #line 878
   if (i < count) {
 #line 879
     goto ldv_37813;
   } else {
 #line 881
     goto ldv_37815;
   }
   ldv_37815: ;
 #line 900
   return (0);
 }
 }
 #line 904 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static void i915_gem_execbuffer_move_to_active(struct list_head *objects , struct intel_ring_buffer *ring ,
                                                u32 seqno ) 
 { struct drm_i915_gem_object *obj ;
   struct list_head  const  *__mptr ;
   u32 old_read ;
   u32 old_write ;
   struct list_head  const  *__mptr___0 ;
   struct list_head *__cil_tmp9 ;
   struct drm_i915_gem_object *__cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   struct list_head *__cil_tmp12 ;
   struct list_head *__cil_tmp13 ;
   struct drm_device *__cil_tmp14 ;
   struct list_head *__cil_tmp15 ;
   struct drm_i915_gem_object *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
 
   {
 #line 910
   __cil_tmp9 = objects->next;
 #line 910
   __mptr = (struct list_head  const  *)__cil_tmp9;
 #line 910
   __cil_tmp10 = (struct drm_i915_gem_object *)__mptr;
 #line 910
   obj = __cil_tmp10 + 1152921504606846768UL;
 #line 910
   goto ldv_37829;
   ldv_37828: 
   {
 #line 911
   old_read = obj->base.read_domains;
 #line 912
   old_write = obj->base.write_domain;
 #line 915
   obj->base.read_domains = obj->base.pending_read_domains;
 #line 916
   obj->base.write_domain = obj->base.pending_write_domain;
 #line 917
   obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
 #line 919
   i915_gem_object_move_to_active(obj, ring, seqno);
   }
   {
 #line 920
   __cil_tmp11 = obj->base.write_domain;
 #line 920
   if (__cil_tmp11 != 0U) {
     {
 #line 921
     obj->dirty = (unsigned char)1;
 #line 922
     obj->pending_gpu_write = (unsigned char)1;
 #line 923
     __cil_tmp12 = & obj->gpu_write_list;
 #line 923
     __cil_tmp13 = & ring->gpu_write_list;
 #line 923
     list_move_tail(__cil_tmp12, __cil_tmp13);
 #line 925
     __cil_tmp14 = ring->dev;
 #line 925
     intel_mark_busy(__cil_tmp14, obj);
     }
   } else {
 
   }
   }
   {
 #line 928
   trace_i915_gem_object_change_domain(obj, old_read, old_write);
 #line 910
   __cil_tmp15 = obj->exec_list.next;
 #line 910
   __mptr___0 = (struct list_head  const  *)__cil_tmp15;
 #line 910
   __cil_tmp16 = (struct drm_i915_gem_object *)__mptr___0;
 #line 910
   obj = __cil_tmp16 + 1152921504606846768UL;
   }
   ldv_37829: ;
   {
 #line 910
   __cil_tmp17 = (unsigned long )objects;
 #line 910
   __cil_tmp18 = & obj->exec_list;
 #line 910
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 910
   if (__cil_tmp19 != __cil_tmp17) {
 #line 911
     goto ldv_37828;
   } else {
 #line 913
     goto ldv_37830;
   }
   }
   ldv_37830: ;
 #line 915
   return;
 }
 }
 #line 933 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static void i915_gem_execbuffer_retire_commands(struct drm_device *dev , struct drm_file *file ,
                                                 struct intel_ring_buffer *ring ) 
 { struct drm_i915_gem_request *request ;
   u32 invalidate ;
   int tmp ;
   void *tmp___0 ;
   int tmp___1 ;
   void *__cil_tmp9 ;
   struct drm_i915_private *__cil_tmp10 ;
   struct intel_device_info  const  *__cil_tmp11 ;
   u8 __cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   int (*__cil_tmp15)(struct intel_ring_buffer * , u32  , u32  ) ;
   struct drm_i915_gem_request *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   void const   *__cil_tmp19 ;
   void const   *__cil_tmp20 ;
 
   {
 #line 946
   invalidate = 8U;
   {
 #line 947
   __cil_tmp9 = dev->dev_private;
 #line 947
   __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
 #line 947
   __cil_tmp11 = __cil_tmp10->info;
 #line 947
   __cil_tmp12 = __cil_tmp11->gen;
 #line 947
   __cil_tmp13 = (unsigned char )__cil_tmp12;
 #line 947
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 947
   if (__cil_tmp14 > 3U) {
 #line 948
     invalidate = invalidate | 4U;
   } else {
 
   }
   }
   {
 #line 949
   __cil_tmp15 = ring->flush;
 #line 949
   tmp = (*__cil_tmp15)(ring, invalidate, 0U);
   }
 #line 949
   if (tmp != 0) {
     {
 #line 950
     i915_gem_next_request_seqno(ring);
     }
 #line 951
     return;
   } else {
 
   }
   {
 #line 955
   tmp___0 = kzalloc(64UL, 208U);
 #line 955
   request = (struct drm_i915_gem_request *)tmp___0;
   }
   {
 #line 956
   __cil_tmp16 = (struct drm_i915_gem_request *)0;
 #line 956
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 956
   __cil_tmp18 = (unsigned long )request;
 #line 956
   if (__cil_tmp18 == __cil_tmp17) {
     {
 #line 957
     i915_gem_next_request_seqno(ring);
 #line 958
     __cil_tmp19 = (void const   *)request;
 #line 958
     kfree(__cil_tmp19);
     }
   } else {
     {
 #line 956
     tmp___1 = i915_add_request(ring, file, request);
     }
 #line 956
     if (tmp___1 != 0) {
       {
 #line 957
       i915_gem_next_request_seqno(ring);
 #line 958
       __cil_tmp20 = (void const   *)request;
 #line 958
       kfree(__cil_tmp20);
       }
     } else {
 
     }
   }
   }
 #line 960
   return;
 }
 }
 #line 963 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 static int i915_gem_do_execbuffer(struct drm_device *dev , void *data , struct drm_file *file ,
                                   struct drm_i915_gem_execbuffer2 *args , struct drm_i915_gem_exec_object2 *exec ) 
 { drm_i915_private_t *dev_priv ;
   struct list_head objects ;
   struct eb_objects *eb ;
   struct drm_i915_gem_object *batch_obj ;
   struct drm_clip_rect *cliprects ;
   struct intel_ring_buffer *ring ;
   u32 exec_start ;
   u32 exec_len ;
   u32 seqno ;
   int ret ;
   int mode ;
   int i ;
   bool tmp ;
   int tmp___0 ;
   void *tmp___1 ;
   unsigned long tmp___2 ;
   struct drm_i915_gem_object *obj ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp___3 ;
   int tmp___4 ;
   struct list_head  const  *__mptr___0 ;
   int tmp___5 ;
   long tmp___6 ;
   long tmp___7 ;
   struct drm_i915_gem_object *obj___0 ;
   struct list_head  const  *__mptr___1 ;
   int tmp___8 ;
   void *__cil_tmp33 ;
   __u32 __cil_tmp34 ;
   int __cil_tmp35 ;
   __u64 __cil_tmp36 ;
   unsigned long long __cil_tmp37 ;
   int __cil_tmp38 ;
   __u64 __cil_tmp39 ;
   unsigned long long __cil_tmp40 ;
   int __cil_tmp41 ;
   __u64 __cil_tmp42 ;
   unsigned long long __cil_tmp43 ;
   int __cil_tmp44 ;
   __u64 __cil_tmp45 ;
   unsigned long long __cil_tmp46 ;
   int __cil_tmp47 ;
   struct intel_ring_buffer (*__cil_tmp48)[3U] ;
   void *__cil_tmp49 ;
   struct drm_i915_private *__cil_tmp50 ;
   struct intel_device_info  const  *__cil_tmp51 ;
   unsigned char *__cil_tmp52 ;
   unsigned char *__cil_tmp53 ;
   unsigned char __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   struct intel_ring_buffer (*__cil_tmp56)[3U] ;
   struct intel_ring_buffer *__cil_tmp57 ;
   void *__cil_tmp58 ;
   struct drm_i915_private *__cil_tmp59 ;
   struct intel_device_info  const  *__cil_tmp60 ;
   unsigned char *__cil_tmp61 ;
   unsigned char *__cil_tmp62 ;
   unsigned char __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   struct intel_ring_buffer (*__cil_tmp65)[3U] ;
   struct intel_ring_buffer *__cil_tmp66 ;
   __u64 __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   __u64 __cil_tmp70 ;
   int __cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   struct intel_ring_buffer (*__cil_tmp73)[3U] ;
   struct intel_ring_buffer *__cil_tmp74 ;
   unsigned long __cil_tmp75 ;
   int __cil_tmp76 ;
   void *__cil_tmp77 ;
   struct drm_i915_private *__cil_tmp78 ;
   struct intel_device_info  const  *__cil_tmp79 ;
   u8 __cil_tmp80 ;
   unsigned char __cil_tmp81 ;
   unsigned int __cil_tmp82 ;
   void *__cil_tmp83 ;
   struct drm_i915_private *__cil_tmp84 ;
   struct intel_device_info  const  *__cil_tmp85 ;
   u8 __cil_tmp86 ;
   unsigned char __cil_tmp87 ;
   unsigned int __cil_tmp88 ;
   int __cil_tmp89 ;
   u32 __cil_tmp90 ;
   __u32 __cil_tmp91 ;
   __u32 __cil_tmp92 ;
   __u32 __cil_tmp93 ;
   unsigned long __cil_tmp94 ;
   struct intel_ring_buffer (*__cil_tmp95)[3U] ;
   struct intel_ring_buffer *__cil_tmp96 ;
   unsigned long __cil_tmp97 ;
   __u32 __cil_tmp98 ;
   unsigned long __cil_tmp99 ;
   unsigned long __cil_tmp100 ;
   struct drm_clip_rect *__cil_tmp101 ;
   unsigned long __cil_tmp102 ;
   unsigned long __cil_tmp103 ;
   void *__cil_tmp104 ;
   __u64 __cil_tmp105 ;
   void const   *__cil_tmp106 ;
   __u32 __cil_tmp107 ;
   unsigned long __cil_tmp108 ;
   unsigned long __cil_tmp109 ;
   int __cil_tmp110 ;
   struct mutex *__cil_tmp111 ;
   __u32 __cil_tmp112 ;
   int __cil_tmp113 ;
   struct eb_objects *__cil_tmp114 ;
   unsigned long __cil_tmp115 ;
   unsigned long __cil_tmp116 ;
   struct mutex *__cil_tmp117 ;
   unsigned long __cil_tmp118 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp119 ;
   __u32 __cil_tmp120 ;
   struct drm_gem_object *__cil_tmp121 ;
   unsigned long __cil_tmp122 ;
   struct drm_gem_object *__cil_tmp123 ;
   unsigned long __cil_tmp124 ;
   unsigned long __cil_tmp125 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp126 ;
   __u32 __cil_tmp127 ;
   struct list_head *__cil_tmp128 ;
   struct list_head  const  *__cil_tmp129 ;
   unsigned long __cil_tmp130 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp131 ;
   __u32 __cil_tmp132 ;
   struct list_head *__cil_tmp133 ;
   unsigned long __cil_tmp134 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp135 ;
   __u32 __cil_tmp136 ;
   unsigned long __cil_tmp137 ;
   __u32 __cil_tmp138 ;
   __u32 __cil_tmp139 ;
   struct drm_i915_gem_object *__cil_tmp140 ;
   __u32 __cil_tmp141 ;
   int __cil_tmp142 ;
   struct mutex *__cil_tmp143 ;
   int __cil_tmp144 ;
   long __cil_tmp145 ;
   uint32_t __cil_tmp146 ;
   uint32_t __cil_tmp147 ;
   u32 __cil_tmp148 ;
   u32 __cil_tmp149 ;
   int __cil_tmp150 ;
   long __cil_tmp151 ;
   unsigned int __cil_tmp152 ;
   __u32 __cil_tmp153 ;
   uint32_t __cil_tmp154 ;
   struct drm_clip_rect *__cil_tmp155 ;
   unsigned long __cil_tmp156 ;
   unsigned long __cil_tmp157 ;
   unsigned long __cil_tmp158 ;
   struct drm_clip_rect *__cil_tmp159 ;
   __u32 __cil_tmp160 ;
   int __cil_tmp161 ;
   __u32 __cil_tmp162 ;
   int __cil_tmp163 ;
   int (*__cil_tmp164)(struct intel_ring_buffer * , u32  , u32  ) ;
   __u32 __cil_tmp165 ;
   __u32 __cil_tmp166 ;
   int (*__cil_tmp167)(struct intel_ring_buffer * , u32  , u32  ) ;
   struct drm_i915_gem_object *__cil_tmp168 ;
   struct list_head *__cil_tmp169 ;
   struct drm_gem_object *__cil_tmp170 ;
   struct list_head  const  *__cil_tmp171 ;
   struct mutex *__cil_tmp172 ;
   void const   *__cil_tmp173 ;
 
   {
   {
 #line 968
   __cil_tmp33 = dev->dev_private;
 #line 968
   dev_priv = (drm_i915_private_t *)__cil_tmp33;
 #line 972
   cliprects = (struct drm_clip_rect *)0;
 #line 978
   tmp = i915_gem_check_execbuffer(args);
   }
 #line 978
   if (tmp) {
 #line 978
     tmp___0 = 0;
   } else {
 #line 978
     tmp___0 = 1;
   }
 #line 978
   if (tmp___0) {
     {
 #line 979
     drm_err("i915_gem_do_execbuffer", "execbuf with invalid offset/length\n");
     }
 #line 980
     return (-22);
   } else {
 
   }
   {
 #line 983
   __cil_tmp34 = args->buffer_count;
 #line 983
   __cil_tmp35 = (int )__cil_tmp34;
 #line 983
   ret = validate_exec_list(exec, __cil_tmp35);
   }
 #line 984
   if (ret != 0) {
 #line 985
     return (ret);
   } else {
 
   }
   {
 #line 988
   __cil_tmp36 = args->flags;
 #line 988
   __cil_tmp37 = __cil_tmp36 & 7ULL;
 #line 988
   __cil_tmp38 = (int )__cil_tmp37;
 #line 988
   if (__cil_tmp38 == 0) {
 #line 988
     goto case_0;
   } else {
     {
 #line 989
     __cil_tmp39 = args->flags;
 #line 989
     __cil_tmp40 = __cil_tmp39 & 7ULL;
 #line 989
     __cil_tmp41 = (int )__cil_tmp40;
 #line 989
     if (__cil_tmp41 == 1) {
 #line 989
       goto case_1;
     } else {
       {
 #line 992
       __cil_tmp42 = args->flags;
 #line 992
       __cil_tmp43 = __cil_tmp42 & 7ULL;
 #line 992
       __cil_tmp44 = (int )__cil_tmp43;
 #line 992
       if (__cil_tmp44 == 2) {
 #line 992
         goto case_2;
       } else {
         {
 #line 999
         __cil_tmp45 = args->flags;
 #line 999
         __cil_tmp46 = __cil_tmp45 & 7ULL;
 #line 999
         __cil_tmp47 = (int )__cil_tmp46;
 #line 999
         if (__cil_tmp47 == 3) {
 #line 999
           goto case_3;
         } else {
 #line 1006
           goto switch_default;
 #line 987
           if (0) {
             case_0: ;
             case_1: 
 #line 990
             __cil_tmp48 = & dev_priv->ring;
 #line 990
             ring = (struct intel_ring_buffer *)__cil_tmp48;
 #line 991
             goto ldv_37860;
             case_2: ;
             {
 #line 993
             __cil_tmp49 = dev->dev_private;
 #line 993
             __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
 #line 993
             __cil_tmp51 = __cil_tmp50->info;
 #line 993
             __cil_tmp52 = (unsigned char *)__cil_tmp51;
 #line 993
             __cil_tmp53 = __cil_tmp52 + 3UL;
 #line 993
             __cil_tmp54 = *__cil_tmp53;
 #line 993
             __cil_tmp55 = (unsigned int )__cil_tmp54;
 #line 993
             if (__cil_tmp55 == 0U) {
               {
 #line 994
               drm_err("i915_gem_do_execbuffer", "execbuf with invalid ring (BSD)\n");
               }
 #line 995
               return (-22);
             } else {
 
             }
             }
 #line 997
             __cil_tmp56 = & dev_priv->ring;
 #line 997
             __cil_tmp57 = (struct intel_ring_buffer *)__cil_tmp56;
 #line 997
             ring = __cil_tmp57 + 1UL;
 #line 998
             goto ldv_37860;
             case_3: ;
             {
 #line 1000
             __cil_tmp58 = dev->dev_private;
 #line 1000
             __cil_tmp59 = (struct drm_i915_private *)__cil_tmp58;
 #line 1000
             __cil_tmp60 = __cil_tmp59->info;
 #line 1000
             __cil_tmp61 = (unsigned char *)__cil_tmp60;
 #line 1000
             __cil_tmp62 = __cil_tmp61 + 3UL;
 #line 1000
             __cil_tmp63 = *__cil_tmp62;
 #line 1000
             __cil_tmp64 = (unsigned int )__cil_tmp63;
 #line 1000
             if (__cil_tmp64 == 0U) {
               {
 #line 1001
               drm_err("i915_gem_do_execbuffer", "execbuf with invalid ring (BLT)\n");
               }
 #line 1002
               return (-22);
             } else {
 
             }
             }
 #line 1004
             __cil_tmp65 = & dev_priv->ring;
 #line 1004
             __cil_tmp66 = (struct intel_ring_buffer *)__cil_tmp65;
 #line 1004
             ring = __cil_tmp66 + 2UL;
 #line 1005
             goto ldv_37860;
             switch_default: 
             {
 #line 1007
             __cil_tmp67 = args->flags;
 #line 1007
             __cil_tmp68 = (int )__cil_tmp67;
 #line 1007
             __cil_tmp69 = __cil_tmp68 & 7;
 #line 1007
             drm_err("i915_gem_do_execbuffer", "execbuf with unknown ring: %d\n", __cil_tmp69);
             }
 #line 1009
             return (-22);
           } else {
 
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_37860: 
 #line 1012
   __cil_tmp70 = args->flags;
 #line 1012
   __cil_tmp71 = (int )__cil_tmp70;
 #line 1012
   mode = __cil_tmp71 & 192;
 #line 1014
   if (mode == 0) {
 #line 1014
     goto case_0___0;
   } else
 #line 1015
   if (mode == 64) {
 #line 1015
     goto case_64;
   } else
 #line 1016
   if (mode == 128) {
 #line 1016
     goto case_128;
   } else {
 #line 1040
     goto switch_default___0;
 #line 1013
     if (0) {
       case_0___0: ;
       case_64: ;
       case_128: ;
       {
 #line 1017
       __cil_tmp72 = (unsigned long )ring;
 #line 1017
       __cil_tmp73 = & dev_priv->ring;
 #line 1017
       __cil_tmp74 = (struct intel_ring_buffer *)__cil_tmp73;
 #line 1017
       __cil_tmp75 = (unsigned long )__cil_tmp74;
 #line 1017
       if (__cil_tmp75 == __cil_tmp72) {
         {
 #line 1017
         __cil_tmp76 = dev_priv->relative_constants_mode;
 #line 1017
         if (__cil_tmp76 != mode) {
           {
 #line 1019
           __cil_tmp77 = dev->dev_private;
 #line 1019
           __cil_tmp78 = (struct drm_i915_private *)__cil_tmp77;
 #line 1019
           __cil_tmp79 = __cil_tmp78->info;
 #line 1019
           __cil_tmp80 = __cil_tmp79->gen;
 #line 1019
           __cil_tmp81 = (unsigned char )__cil_tmp80;
 #line 1019
           __cil_tmp82 = (unsigned int )__cil_tmp81;
 #line 1019
           if (__cil_tmp82 <= 3U) {
 #line 1020
             return (-22);
           } else {
 
           }
           }
           {
 #line 1022
           __cil_tmp83 = dev->dev_private;
 #line 1022
           __cil_tmp84 = (struct drm_i915_private *)__cil_tmp83;
 #line 1022
           __cil_tmp85 = __cil_tmp84->info;
 #line 1022
           __cil_tmp86 = __cil_tmp85->gen;
 #line 1022
           __cil_tmp87 = (unsigned char )__cil_tmp86;
 #line 1022
           __cil_tmp88 = (unsigned int )__cil_tmp87;
 #line 1022
           if (__cil_tmp88 > 5U) {
 #line 1022
             if (mode == 128) {
 #line 1024
               return (-22);
             } else {
 
             }
           } else {
 
           }
           }
           {
 #line 1026
           ret = intel_ring_begin(ring, 4);
           }
 #line 1027
           if (ret != 0) {
 #line 1028
             return (ret);
           } else {
 
           }
           {
 #line 1030
           intel_ring_emit(ring, 0U);
 #line 1031
           intel_ring_emit(ring, 285212673U);
 #line 1032
           intel_ring_emit(ring, 8384U);
 #line 1033
           __cil_tmp89 = mode | 12582912;
 #line 1033
           __cil_tmp90 = (u32 )__cil_tmp89;
 #line 1033
           intel_ring_emit(ring, __cil_tmp90);
 #line 1035
           intel_ring_advance(ring);
 #line 1037
           dev_priv->relative_constants_mode = mode;
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
 #line 1039
       goto ldv_37867;
       switch_default___0: 
       {
 #line 1041
       drm_err("i915_gem_do_execbuffer", "execbuf with unknown constants: %d\n", mode);
       }
 #line 1042
       return (-22);
     } else {
 
     }
   }
   ldv_37867: ;
   {
 #line 1045
   __cil_tmp91 = args->buffer_count;
 #line 1045
   if (__cil_tmp91 == 0U) {
     {
 #line 1046
     __cil_tmp92 = args->buffer_count;
 #line 1046
     drm_err("i915_gem_do_execbuffer", "execbuf with %d buffers\n", __cil_tmp92);
     }
 #line 1047
     return (-22);
   } else {
 
   }
   }
   {
 #line 1050
   __cil_tmp93 = args->num_cliprects;
 #line 1050
   if (__cil_tmp93 != 0U) {
     {
 #line 1051
     __cil_tmp94 = (unsigned long )ring;
 #line 1051
     __cil_tmp95 = & dev_priv->ring;
 #line 1051
     __cil_tmp96 = (struct intel_ring_buffer *)__cil_tmp95;
 #line 1051
     __cil_tmp97 = (unsigned long )__cil_tmp96;
 #line 1051
     if (__cil_tmp97 != __cil_tmp94) {
       {
 #line 1052
       drm_err("i915_gem_do_execbuffer", "clip rectangles are only valid with the render ring\n");
       }
 #line 1053
       return (-22);
     } else {
 
     }
     }
     {
 #line 1056
     __cil_tmp98 = args->num_cliprects;
 #line 1056
     __cil_tmp99 = (unsigned long )__cil_tmp98;
 #line 1056
     __cil_tmp100 = __cil_tmp99 * 8UL;
 #line 1056
     tmp___1 = kmalloc(__cil_tmp100, 208U);
 #line 1056
     cliprects = (struct drm_clip_rect *)tmp___1;
     }
     {
 #line 1058
     __cil_tmp101 = (struct drm_clip_rect *)0;
 #line 1058
     __cil_tmp102 = (unsigned long )__cil_tmp101;
 #line 1058
     __cil_tmp103 = (unsigned long )cliprects;
 #line 1058
     if (__cil_tmp103 == __cil_tmp102) {
 #line 1059
       ret = -12;
 #line 1060
       goto pre_mutex_err;
     } else {
 
     }
     }
     {
 #line 1063
     __cil_tmp104 = (void *)cliprects;
 #line 1063
     __cil_tmp105 = args->cliprects_ptr;
 #line 1063
     __cil_tmp106 = (void const   *)__cil_tmp105;
 #line 1063
     __cil_tmp107 = args->num_cliprects;
 #line 1063
     __cil_tmp108 = (unsigned long )__cil_tmp107;
 #line 1063
     __cil_tmp109 = __cil_tmp108 * 8UL;
 #line 1063
     tmp___2 = copy_from_user(__cil_tmp104, __cil_tmp106, __cil_tmp109);
     }
 #line 1063
     if (tmp___2 != 0UL) {
 #line 1067
       ret = -14;
 #line 1068
       goto pre_mutex_err;
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1072
   ret = i915_mutex_lock_interruptible(dev);
   }
 #line 1073
   if (ret != 0) {
 #line 1074
     goto pre_mutex_err;
   } else {
 
   }
   {
 #line 1076
   __cil_tmp110 = dev_priv->mm.suspended;
 #line 1076
   if (__cil_tmp110 != 0) {
     {
 #line 1077
     __cil_tmp111 = & dev->struct_mutex;
 #line 1077
     mutex_unlock(__cil_tmp111);
 #line 1078
     ret = -16;
     }
 #line 1079
     goto pre_mutex_err;
   } else {
 
   }
   }
   {
 #line 1082
   __cil_tmp112 = args->buffer_count;
 #line 1082
   __cil_tmp113 = (int )__cil_tmp112;
 #line 1082
   eb = eb_create(__cil_tmp113);
   }
   {
 #line 1083
   __cil_tmp114 = (struct eb_objects *)0;
 #line 1083
   __cil_tmp115 = (unsigned long )__cil_tmp114;
 #line 1083
   __cil_tmp116 = (unsigned long )eb;
 #line 1083
   if (__cil_tmp116 == __cil_tmp115) {
     {
 #line 1084
     __cil_tmp117 = & dev->struct_mutex;
 #line 1084
     mutex_unlock(__cil_tmp117);
 #line 1085
     ret = -12;
     }
 #line 1086
     goto pre_mutex_err;
   } else {
 
   }
   }
   {
 #line 1090
   INIT_LIST_HEAD(& objects);
 #line 1091
   i = 0;
   }
 #line 1091
   goto ldv_37875;
   ldv_37874: 
   {
 #line 1094
   __cil_tmp118 = (unsigned long )i;
 #line 1094
   __cil_tmp119 = exec + __cil_tmp118;
 #line 1094
   __cil_tmp120 = __cil_tmp119->handle;
 #line 1094
   tmp___3 = drm_gem_object_lookup(dev, file, __cil_tmp120);
 #line 1094
   __mptr = (struct drm_gem_object  const  *)tmp___3;
 #line 1094
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 1096
   __cil_tmp121 = (struct drm_gem_object *)0;
 #line 1096
   __cil_tmp122 = (unsigned long )__cil_tmp121;
 #line 1096
   __cil_tmp123 = & obj->base;
 #line 1096
   __cil_tmp124 = (unsigned long )__cil_tmp123;
 #line 1096
   if (__cil_tmp124 == __cil_tmp122) {
     {
 #line 1097
     __cil_tmp125 = (unsigned long )i;
 #line 1097
     __cil_tmp126 = exec + __cil_tmp125;
 #line 1097
     __cil_tmp127 = __cil_tmp126->handle;
 #line 1097
     drm_err("i915_gem_do_execbuffer", "Invalid object handle %d at index %d\n", __cil_tmp127,
             i);
 #line 1100
     ret = -2;
     }
 #line 1101
     goto err;
   } else {
 
   }
   }
   {
 #line 1104
   __cil_tmp128 = & obj->exec_list;
 #line 1104
   __cil_tmp129 = (struct list_head  const  *)__cil_tmp128;
 #line 1104
   tmp___4 = list_empty(__cil_tmp129);
   }
 #line 1104
   if (tmp___4 == 0) {
     {
 #line 1105
     __cil_tmp130 = (unsigned long )i;
 #line 1105
     __cil_tmp131 = exec + __cil_tmp130;
 #line 1105
     __cil_tmp132 = __cil_tmp131->handle;
 #line 1105
     drm_err("i915_gem_do_execbuffer", "Object %p [handle %d, index %d] appears more than once in object list\n",
             obj, __cil_tmp132, i);
 #line 1107
     ret = -22;
     }
 #line 1108
     goto err;
   } else {
 
   }
   {
 #line 1111
   __cil_tmp133 = & obj->exec_list;
 #line 1111
   list_add_tail(__cil_tmp133, & objects);
 #line 1112
   __cil_tmp134 = (unsigned long )i;
 #line 1112
   __cil_tmp135 = exec + __cil_tmp134;
 #line 1112
   __cil_tmp136 = __cil_tmp135->handle;
 #line 1112
   obj->exec_handle = (unsigned long )__cil_tmp136;
 #line 1113
   __cil_tmp137 = (unsigned long )i;
 #line 1113
   obj->exec_entry = exec + __cil_tmp137;
 #line 1114
   eb_add_object(eb, obj);
 #line 1091
   i = i + 1;
   }
   ldv_37875: ;
   {
 #line 1091
   __cil_tmp138 = args->buffer_count;
 #line 1091
   __cil_tmp139 = (__u32 )i;
 #line 1091
   if (__cil_tmp139 < __cil_tmp138) {
 #line 1092
     goto ldv_37874;
   } else {
 #line 1094
     goto ldv_37876;
   }
   }
   ldv_37876: 
   {
 #line 1118
   __mptr___0 = (struct list_head  const  *)objects.prev;
 #line 1118
   __cil_tmp140 = (struct drm_i915_gem_object *)__mptr___0;
 #line 1118
   batch_obj = __cil_tmp140 + 1152921504606846768UL;
 #line 1123
   ret = i915_gem_execbuffer_reserve(ring, file, & objects);
   }
 #line 1124
   if (ret != 0) {
 #line 1125
     goto err;
   } else {
 
   }
   {
 #line 1128
   ret = i915_gem_execbuffer_relocate(dev, eb, & objects);
   }
 #line 1129
   if (ret != 0) {
 #line 1130
     if (ret == -14) {
       {
 #line 1131
       __cil_tmp141 = args->buffer_count;
 #line 1131
       __cil_tmp142 = (int )__cil_tmp141;
 #line 1131
       ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, & objects, eb, exec,
                                               __cil_tmp142);
 #line 1135
       __cil_tmp143 = & dev->struct_mutex;
 #line 1135
       tmp___5 = mutex_is_locked(__cil_tmp143);
 #line 1135
       __cil_tmp144 = tmp___5 == 0;
 #line 1135
       __cil_tmp145 = (long )__cil_tmp144;
 #line 1135
       tmp___6 = __builtin_expect(__cil_tmp145, 0L);
       }
 #line 1135
       if (tmp___6 != 0L) {
 #line 1135
         __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"),
                              "i" (1135), "i" (12UL));
         ldv_37879: ;
 #line 1135
         goto ldv_37879;
       } else {
 
       }
     } else {
 
     }
 #line 1137
     if (ret != 0) {
 #line 1138
       goto err;
     } else {
 
     }
   } else {
 
   }
   {
 #line 1142
   __cil_tmp146 = batch_obj->base.pending_write_domain;
 #line 1142
   if (__cil_tmp146 != 0U) {
     {
 #line 1143
     drm_err("i915_gem_do_execbuffer", "Attempting to use self-modifying batch buffer\n");
 #line 1144
     ret = -22;
     }
 #line 1145
     goto err;
   } else {
 
   }
   }
   {
 #line 1147
   __cil_tmp147 = batch_obj->base.pending_read_domains;
 #line 1147
   batch_obj->base.pending_read_domains = __cil_tmp147 | 8U;
 #line 1149
   ret = i915_gem_execbuffer_move_to_gpu(ring, & objects);
   }
 #line 1150
   if (ret != 0) {
 #line 1151
     goto err;
   } else {
 
   }
   {
 #line 1153
   seqno = i915_gem_next_request_seqno(ring);
 #line 1154
   i = 0;
   }
 #line 1154
   goto ldv_37884;
   ldv_37883: ;
   {
 #line 1155
   __cil_tmp148 = ring->sync_seqno[i];
 #line 1155
   if (__cil_tmp148 > seqno) {
     {
 #line 1160
     ret = i915_gpu_idle(dev);
     }
 #line 1161
     if (ret != 0) {
 #line 1162
       goto err;
     } else {
 
     }
     {
 #line 1164
     __cil_tmp149 = ring->sync_seqno[i];
 #line 1164
     __cil_tmp150 = __cil_tmp149 != 0U;
 #line 1164
     __cil_tmp151 = (long )__cil_tmp150;
 #line 1164
     tmp___7 = __builtin_expect(__cil_tmp151, 0L);
     }
 #line 1164
     if (tmp___7 != 0L) {
 #line 1164
       __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"),
                            "i" (1164), "i" (12UL));
       ldv_37882: ;
 #line 1164
       goto ldv_37882;
     } else {
 
     }
   } else {
 
   }
   }
 #line 1154
   i = i + 1;
   ldv_37884: ;
   {
 #line 1154
   __cil_tmp152 = (unsigned int )i;
 #line 1154
   if (__cil_tmp152 <= 1U) {
 #line 1155
     goto ldv_37883;
   } else {
 #line 1157
     goto ldv_37885;
   }
   }
   ldv_37885: 
   {
 #line 1168
   trace_i915_gem_ring_dispatch(ring, seqno);
 #line 1170
   __cil_tmp153 = args->batch_start_offset;
 #line 1170
   __cil_tmp154 = batch_obj->gtt_offset;
 #line 1170
   exec_start = __cil_tmp154 + __cil_tmp153;
 #line 1171
   exec_len = args->batch_len;
   }
   {
 #line 1172
   __cil_tmp155 = (struct drm_clip_rect *)0;
 #line 1172
   __cil_tmp156 = (unsigned long )__cil_tmp155;
 #line 1172
   __cil_tmp157 = (unsigned long )cliprects;
 #line 1172
   if (__cil_tmp157 != __cil_tmp156) {
 #line 1173
     i = 0;
 #line 1173
     goto ldv_37887;
     ldv_37886: 
     {
 #line 1174
     __cil_tmp158 = (unsigned long )i;
 #line 1174
     __cil_tmp159 = cliprects + __cil_tmp158;
 #line 1174
     __cil_tmp160 = args->DR1;
 #line 1174
     __cil_tmp161 = (int )__cil_tmp160;
 #line 1174
     __cil_tmp162 = args->DR4;
 #line 1174
     __cil_tmp163 = (int )__cil_tmp162;
 #line 1174
     ret = i915_emit_box(dev, __cil_tmp159, __cil_tmp161, __cil_tmp163);
     }
 #line 1176
     if (ret != 0) {
 #line 1177
       goto err;
     } else {
 
     }
     {
 #line 1179
     __cil_tmp164 = ring->dispatch_execbuffer;
 #line 1179
     ret = (*__cil_tmp164)(ring, exec_start, exec_len);
     }
 #line 1181
     if (ret != 0) {
 #line 1182
       goto err;
     } else {
 
     }
 #line 1173
     i = i + 1;
     ldv_37887: ;
     {
 #line 1173
     __cil_tmp165 = args->num_cliprects;
 #line 1173
     __cil_tmp166 = (__u32 )i;
 #line 1173
     if (__cil_tmp166 < __cil_tmp165) {
 #line 1174
       goto ldv_37886;
     } else {
 #line 1176
       goto ldv_37888;
     }
     }
     ldv_37888: ;
   } else {
     {
 #line 1185
     __cil_tmp167 = ring->dispatch_execbuffer;
 #line 1185
     ret = (*__cil_tmp167)(ring, exec_start, exec_len);
     }
 #line 1186
     if (ret != 0) {
 #line 1187
       goto err;
     } else {
 
     }
   }
   }
   {
 #line 1190
   i915_gem_execbuffer_move_to_active(& objects, ring, seqno);
 #line 1191
   i915_gem_execbuffer_retire_commands(dev, file, ring);
   }
   err: 
   {
 #line 1194
   eb_destroy(eb);
   }
 #line 1195
   goto ldv_37893;
   ldv_37892: 
   {
 #line 1198
   __mptr___1 = (struct list_head  const  *)objects.next;
 #line 1198
   __cil_tmp168 = (struct drm_i915_gem_object *)__mptr___1;
 #line 1198
   obj___0 = __cil_tmp168 + 1152921504606846768UL;
 #line 1201
   __cil_tmp169 = & obj___0->exec_list;
 #line 1201
   list_del_init(__cil_tmp169);
 #line 1202
   __cil_tmp170 = & obj___0->base;
 #line 1202
   drm_gem_object_unreference(__cil_tmp170);
   }
   ldv_37893: 
   {
 #line 1195
   __cil_tmp171 = (struct list_head  const  *)(& objects);
 #line 1195
   tmp___8 = list_empty(__cil_tmp171);
   }
 #line 1195
   if (tmp___8 == 0) {
 #line 1196
     goto ldv_37892;
   } else {
 #line 1198
     goto ldv_37894;
   }
   ldv_37894: 
   {
 #line 1205
   __cil_tmp172 = & dev->struct_mutex;
 #line 1205
   mutex_unlock(__cil_tmp172);
   }
   pre_mutex_err: 
   {
 #line 1208
   __cil_tmp173 = (void const   *)cliprects;
 #line 1208
   kfree(__cil_tmp173);
   }
 #line 1209
   return (ret);
 }
 }
 #line 1217 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 int i915_gem_execbuffer(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_execbuffer *args ;
   struct drm_i915_gem_execbuffer2 exec2 ;
   struct drm_i915_gem_exec_object *exec_list ;
   struct drm_i915_gem_exec_object2 *exec2_list ;
   int ret ;
   int i ;
   void *tmp ;
   void *tmp___0 ;
   unsigned long tmp___1 ;
   __u32 __cil_tmp13 ;
   __u32 __cil_tmp14 ;
   __u32 __cil_tmp15 ;
   size_t __cil_tmp16 ;
   __u32 __cil_tmp17 ;
   size_t __cil_tmp18 ;
   struct drm_i915_gem_exec_object *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   __u32 __cil_tmp22 ;
   void *__cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   __u32 __cil_tmp28 ;
   void *__cil_tmp29 ;
   void *__cil_tmp30 ;
   void *__cil_tmp31 ;
   __u64 __cil_tmp32 ;
   void const   *__cil_tmp33 ;
   __u32 __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   __u32 __cil_tmp37 ;
   void *__cil_tmp38 ;
   void *__cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct drm_i915_gem_exec_object *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   struct drm_i915_gem_exec_object *__cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   struct drm_i915_gem_exec_object *__cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   struct drm_i915_gem_exec_object *__cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp57 ;
   unsigned long __cil_tmp58 ;
   struct drm_i915_gem_exec_object *__cil_tmp59 ;
   void *__cil_tmp60 ;
   struct drm_i915_private *__cil_tmp61 ;
   struct intel_device_info  const  *__cil_tmp62 ;
   u8 __cil_tmp63 ;
   unsigned char __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   unsigned long __cil_tmp66 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp69 ;
   __u32 __cil_tmp70 ;
   __u32 __cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   struct drm_i915_gem_exec_object *__cil_tmp73 ;
   unsigned long __cil_tmp74 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp75 ;
   __u32 __cil_tmp76 ;
   __u32 __cil_tmp77 ;
   __u64 __cil_tmp78 ;
   void *__cil_tmp79 ;
   void const   *__cil_tmp80 ;
   __u32 __cil_tmp81 ;
   __u32 __cil_tmp82 ;
   __u32 __cil_tmp83 ;
   void *__cil_tmp84 ;
   void *__cil_tmp85 ;
 
   {
 #line 1220
   args = (struct drm_i915_gem_execbuffer *)data;
 #line 1222
   exec_list = (struct drm_i915_gem_exec_object *)0;
 #line 1223
   exec2_list = (struct drm_i915_gem_exec_object2 *)0;
   {
 #line 1226
   __cil_tmp13 = args->buffer_count;
 #line 1226
   if (__cil_tmp13 == 0U) {
     {
 #line 1227
     __cil_tmp14 = args->buffer_count;
 #line 1227
     drm_err("i915_gem_execbuffer", "execbuf with %d buffers\n", __cil_tmp14);
     }
 #line 1228
     return (-22);
   } else {
 
   }
   }
   {
 #line 1232
   __cil_tmp15 = args->buffer_count;
 #line 1232
   __cil_tmp16 = (size_t )__cil_tmp15;
 #line 1232
   tmp = drm_malloc_ab(32UL, __cil_tmp16);
 #line 1232
   exec_list = (struct drm_i915_gem_exec_object *)tmp;
 #line 1233
   __cil_tmp17 = args->buffer_count;
 #line 1233
   __cil_tmp18 = (size_t )__cil_tmp17;
 #line 1233
   tmp___0 = drm_malloc_ab(56UL, __cil_tmp18);
 #line 1233
   exec2_list = (struct drm_i915_gem_exec_object2 *)tmp___0;
   }
   {
 #line 1234
   __cil_tmp19 = (struct drm_i915_gem_exec_object *)0;
 #line 1234
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 1234
   __cil_tmp21 = (unsigned long )exec_list;
 #line 1234
   if (__cil_tmp21 == __cil_tmp20) {
     {
 #line 1235
     __cil_tmp22 = args->buffer_count;
 #line 1235
     drm_err("i915_gem_execbuffer", "Failed to allocate exec list for %d buffers\n",
             __cil_tmp22);
 #line 1237
     __cil_tmp23 = (void *)exec_list;
 #line 1237
     drm_free_large(__cil_tmp23);
 #line 1238
     __cil_tmp24 = (void *)exec2_list;
 #line 1238
     drm_free_large(__cil_tmp24);
     }
 #line 1239
     return (-12);
   } else {
     {
 #line 1234
     __cil_tmp25 = (struct drm_i915_gem_exec_object2 *)0;
 #line 1234
     __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 1234
     __cil_tmp27 = (unsigned long )exec2_list;
 #line 1234
     if (__cil_tmp27 == __cil_tmp26) {
       {
 #line 1235
       __cil_tmp28 = args->buffer_count;
 #line 1235
       drm_err("i915_gem_execbuffer", "Failed to allocate exec list for %d buffers\n",
               __cil_tmp28);
 #line 1237
       __cil_tmp29 = (void *)exec_list;
 #line 1237
       drm_free_large(__cil_tmp29);
 #line 1238
       __cil_tmp30 = (void *)exec2_list;
 #line 1238
       drm_free_large(__cil_tmp30);
       }
 #line 1239
       return (-12);
     } else {
 
     }
     }
   }
   }
   {
 #line 1241
   __cil_tmp31 = (void *)exec_list;
 #line 1241
   __cil_tmp32 = args->buffers_ptr;
 #line 1241
   __cil_tmp33 = (void const   *)__cil_tmp32;
 #line 1241
   __cil_tmp34 = args->buffer_count;
 #line 1241
   __cil_tmp35 = (unsigned long )__cil_tmp34;
 #line 1241
   __cil_tmp36 = __cil_tmp35 * 32UL;
 #line 1241
   tmp___1 = copy_from_user(__cil_tmp31, __cil_tmp33, __cil_tmp36);
 #line 1241
   ret = (int )tmp___1;
   }
 #line 1245
   if (ret != 0) {
     {
 #line 1246
     __cil_tmp37 = args->buffer_count;
 #line 1246
     drm_err("i915_gem_execbuffer", "copy %d exec entries failed %d\n", __cil_tmp37,
             ret);
 #line 1248
     __cil_tmp38 = (void *)exec_list;
 #line 1248
     drm_free_large(__cil_tmp38);
 #line 1249
     __cil_tmp39 = (void *)exec2_list;
 #line 1249
     drm_free_large(__cil_tmp39);
     }
 #line 1250
     return (-14);
   } else {
 
   }
 #line 1253
   i = 0;
 #line 1253
   goto ldv_37909;
   ldv_37908: 
 #line 1254
   __cil_tmp40 = (unsigned long )i;
 #line 1254
   __cil_tmp41 = exec2_list + __cil_tmp40;
 #line 1254
   __cil_tmp42 = (unsigned long )i;
 #line 1254
   __cil_tmp43 = exec_list + __cil_tmp42;
 #line 1254
   __cil_tmp41->handle = __cil_tmp43->handle;
 #line 1255
   __cil_tmp44 = (unsigned long )i;
 #line 1255
   __cil_tmp45 = exec2_list + __cil_tmp44;
 #line 1255
   __cil_tmp46 = (unsigned long )i;
 #line 1255
   __cil_tmp47 = exec_list + __cil_tmp46;
 #line 1255
   __cil_tmp45->relocation_count = __cil_tmp47->relocation_count;
 #line 1256
   __cil_tmp48 = (unsigned long )i;
 #line 1256
   __cil_tmp49 = exec2_list + __cil_tmp48;
 #line 1256
   __cil_tmp50 = (unsigned long )i;
 #line 1256
   __cil_tmp51 = exec_list + __cil_tmp50;
 #line 1256
   __cil_tmp49->relocs_ptr = __cil_tmp51->relocs_ptr;
 #line 1257
   __cil_tmp52 = (unsigned long )i;
 #line 1257
   __cil_tmp53 = exec2_list + __cil_tmp52;
 #line 1257
   __cil_tmp54 = (unsigned long )i;
 #line 1257
   __cil_tmp55 = exec_list + __cil_tmp54;
 #line 1257
   __cil_tmp53->alignment = __cil_tmp55->alignment;
 #line 1258
   __cil_tmp56 = (unsigned long )i;
 #line 1258
   __cil_tmp57 = exec2_list + __cil_tmp56;
 #line 1258
   __cil_tmp58 = (unsigned long )i;
 #line 1258
   __cil_tmp59 = exec_list + __cil_tmp58;
 #line 1258
   __cil_tmp57->offset = __cil_tmp59->offset;
   {
 #line 1259
   __cil_tmp60 = dev->dev_private;
 #line 1259
   __cil_tmp61 = (struct drm_i915_private *)__cil_tmp60;
 #line 1259
   __cil_tmp62 = __cil_tmp61->info;
 #line 1259
   __cil_tmp63 = __cil_tmp62->gen;
 #line 1259
   __cil_tmp64 = (unsigned char )__cil_tmp63;
 #line 1259
   __cil_tmp65 = (unsigned int )__cil_tmp64;
 #line 1259
   if (__cil_tmp65 <= 3U) {
 #line 1260
     __cil_tmp66 = (unsigned long )i;
 #line 1260
     __cil_tmp67 = exec2_list + __cil_tmp66;
 #line 1260
     __cil_tmp67->flags = 1ULL;
   } else {
 #line 1262
     __cil_tmp68 = (unsigned long )i;
 #line 1262
     __cil_tmp69 = exec2_list + __cil_tmp68;
 #line 1262
     __cil_tmp69->flags = 0ULL;
   }
   }
 #line 1253
   i = i + 1;
   ldv_37909: ;
   {
 #line 1253
   __cil_tmp70 = args->buffer_count;
 #line 1253
   __cil_tmp71 = (__u32 )i;
 #line 1253
   if (__cil_tmp71 < __cil_tmp70) {
 #line 1254
     goto ldv_37908;
   } else {
 #line 1256
     goto ldv_37910;
   }
   }
   ldv_37910: 
   {
 #line 1265
   exec2.buffers_ptr = args->buffers_ptr;
 #line 1266
   exec2.buffer_count = args->buffer_count;
 #line 1267
   exec2.batch_start_offset = args->batch_start_offset;
 #line 1268
   exec2.batch_len = args->batch_len;
 #line 1269
   exec2.DR1 = args->DR1;
 #line 1270
   exec2.DR4 = args->DR4;
 #line 1271
   exec2.num_cliprects = args->num_cliprects;
 #line 1272
   exec2.cliprects_ptr = args->cliprects_ptr;
 #line 1273
   exec2.flags = 1ULL;
 #line 1275
   ret = i915_gem_do_execbuffer(dev, data, file, & exec2, exec2_list);
   }
 #line 1276
   if (ret == 0) {
 #line 1278
     i = 0;
 #line 1278
     goto ldv_37912;
     ldv_37911: 
 #line 1279
     __cil_tmp72 = (unsigned long )i;
 #line 1279
     __cil_tmp73 = exec_list + __cil_tmp72;
 #line 1279
     __cil_tmp74 = (unsigned long )i;
 #line 1279
     __cil_tmp75 = exec2_list + __cil_tmp74;
 #line 1279
     __cil_tmp73->offset = __cil_tmp75->offset;
 #line 1278
     i = i + 1;
     ldv_37912: ;
     {
 #line 1278
     __cil_tmp76 = args->buffer_count;
 #line 1278
     __cil_tmp77 = (__u32 )i;
 #line 1278
     if (__cil_tmp77 < __cil_tmp76) {
 #line 1279
       goto ldv_37911;
     } else {
 #line 1281
       goto ldv_37913;
     }
     }
     ldv_37913: 
     {
 #line 1281
     __cil_tmp78 = args->buffers_ptr;
 #line 1281
     __cil_tmp79 = (void *)__cil_tmp78;
 #line 1281
     __cil_tmp80 = (void const   *)exec_list;
 #line 1281
     __cil_tmp81 = args->buffer_count;
 #line 1281
     __cil_tmp82 = __cil_tmp81 * 32U;
 #line 1281
     ret = copy_to_user(__cil_tmp79, __cil_tmp80, __cil_tmp82);
     }
 #line 1285
     if (ret != 0) {
       {
 #line 1286
       ret = -14;
 #line 1287
       __cil_tmp83 = args->buffer_count;
 #line 1287
       drm_err("i915_gem_execbuffer", "failed to copy %d exec entries back to user (%d)\n",
               __cil_tmp83, ret);
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 1293
   __cil_tmp84 = (void *)exec_list;
 #line 1293
   drm_free_large(__cil_tmp84);
 #line 1294
   __cil_tmp85 = (void *)exec2_list;
 #line 1294
   drm_free_large(__cil_tmp85);
   }
 #line 1295
   return (ret);
 }
 }
 #line 1299 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_execbuffer.c.p"
 int i915_gem_execbuffer2(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_execbuffer2 *args ;
   struct drm_i915_gem_exec_object2 *exec2_list ;
   int ret ;
   void *tmp ;
   void *tmp___0 ;
   unsigned long tmp___1 ;
   __u32 __cil_tmp10 ;
   __u32 __cil_tmp11 ;
   __u32 __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   __u32 __cil_tmp18 ;
   size_t __cil_tmp19 ;
   struct drm_i915_gem_exec_object2 *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   __u32 __cil_tmp23 ;
   void *__cil_tmp24 ;
   __u64 __cil_tmp25 ;
   void const   *__cil_tmp26 ;
   __u32 __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   __u32 __cil_tmp30 ;
   void *__cil_tmp31 ;
   __u64 __cil_tmp32 ;
   void *__cil_tmp33 ;
   void const   *__cil_tmp34 ;
   __u32 __cil_tmp35 ;
   __u32 __cil_tmp36 ;
   __u32 __cil_tmp37 ;
   void *__cil_tmp38 ;
 
   {
 #line 1302
   args = (struct drm_i915_gem_execbuffer2 *)data;
 #line 1303
   exec2_list = (struct drm_i915_gem_exec_object2 *)0;
   {
 #line 1306
   __cil_tmp10 = args->buffer_count;
 #line 1306
   if (__cil_tmp10 == 0U) {
     {
 #line 1307
     __cil_tmp11 = args->buffer_count;
 #line 1307
     drm_err("i915_gem_execbuffer2", "execbuf2 with %d buffers\n", __cil_tmp11);
     }
 #line 1308
     return (-22);
   } else {
 
   }
   }
   {
 #line 1311
   __cil_tmp12 = args->buffer_count;
 #line 1311
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 1311
   __cil_tmp14 = __cil_tmp13 * 56UL;
 #line 1311
   tmp = kmalloc(__cil_tmp14, 4816U);
 #line 1311
   exec2_list = (struct drm_i915_gem_exec_object2 *)tmp;
   }
   {
 #line 1313
   __cil_tmp15 = (struct drm_i915_gem_exec_object2 *)0;
 #line 1313
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 1313
   __cil_tmp17 = (unsigned long )exec2_list;
 #line 1313
   if (__cil_tmp17 == __cil_tmp16) {
     {
 #line 1314
     __cil_tmp18 = args->buffer_count;
 #line 1314
     __cil_tmp19 = (size_t )__cil_tmp18;
 #line 1314
     tmp___0 = drm_malloc_ab(56UL, __cil_tmp19);
 #line 1314
     exec2_list = (struct drm_i915_gem_exec_object2 *)tmp___0;
     }
   } else {
 
   }
   }
   {
 #line 1316
   __cil_tmp20 = (struct drm_i915_gem_exec_object2 *)0;
 #line 1316
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 1316
   __cil_tmp22 = (unsigned long )exec2_list;
 #line 1316
   if (__cil_tmp22 == __cil_tmp21) {
     {
 #line 1317
     __cil_tmp23 = args->buffer_count;
 #line 1317
     drm_err("i915_gem_execbuffer2", "Failed to allocate exec list for %d buffers\n",
             __cil_tmp23);
     }
 #line 1319
     return (-12);
   } else {
 
   }
   }
   {
 #line 1321
   __cil_tmp24 = (void *)exec2_list;
 #line 1321
   __cil_tmp25 = args->buffers_ptr;
 #line 1321
   __cil_tmp26 = (void const   *)__cil_tmp25;
 #line 1321
   __cil_tmp27 = args->buffer_count;
 #line 1321
   __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 1321
   __cil_tmp29 = __cil_tmp28 * 56UL;
 #line 1321
   tmp___1 = copy_from_user(__cil_tmp24, __cil_tmp26, __cil_tmp29);
 #line 1321
   ret = (int )tmp___1;
   }
 #line 1325
   if (ret != 0) {
     {
 #line 1326
     __cil_tmp30 = args->buffer_count;
 #line 1326
     drm_err("i915_gem_execbuffer2", "copy %d exec entries failed %d\n", __cil_tmp30,
             ret);
 #line 1328
     __cil_tmp31 = (void *)exec2_list;
 #line 1328
     drm_free_large(__cil_tmp31);
     }
 #line 1329
     return (-14);
   } else {
 
   }
   {
 #line 1332
   ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
   }
 #line 1333
   if (ret == 0) {
     {
 #line 1335
     __cil_tmp32 = args->buffers_ptr;
 #line 1335
     __cil_tmp33 = (void *)__cil_tmp32;
 #line 1335
     __cil_tmp34 = (void const   *)exec2_list;
 #line 1335
     __cil_tmp35 = args->buffer_count;
 #line 1335
     __cil_tmp36 = __cil_tmp35 * 56U;
 #line 1335
     ret = copy_to_user(__cil_tmp33, __cil_tmp34, __cil_tmp36);
     }
 #line 1339
     if (ret != 0) {
       {
 #line 1340
       ret = -14;
 #line 1341
       __cil_tmp37 = args->buffer_count;
 #line 1341
       drm_err("i915_gem_execbuffer2", "failed to copy %d exec entries back to user (%d)\n",
               __cil_tmp37, ret);
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 1347
   __cil_tmp38 = (void *)exec2_list;
 #line 1347
   drm_free_large(__cil_tmp38);
   }
 #line 1348
   return (ret);
 }
 }
 #line 19 "include/drm/intel-gtt.h"
 extern void intel_gtt_unmap_memory(struct scatterlist * , int  ) ;
 #line 21
 extern int intel_gtt_map_memory(struct page ** , unsigned int  , struct scatterlist ** ,
                                 int * ) ;
 #line 23
 extern void intel_gtt_insert_sg_entries(struct scatterlist * , unsigned int  , unsigned int  ,
                                         unsigned int  ) ;
 #line 27
 extern void intel_gtt_insert_pages(unsigned int  , unsigned int  , struct page ** ,
                                    unsigned int  ) ;
 #line 40 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_gtt.c.p"
 static unsigned int cache_level_to_agp_type(struct drm_device *dev , enum i915_cache_level cache_level ) 
 { unsigned int __cil_tmp3 ;
   int __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   int __cil_tmp8 ;
   void *__cil_tmp9 ;
   struct drm_i915_private *__cil_tmp10 ;
   struct intel_device_info  const  *__cil_tmp11 ;
   u8 __cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
 
   {
   {
 #line 44
   __cil_tmp3 = (unsigned int )cache_level;
 #line 44
   __cil_tmp4 = (int )__cil_tmp3;
 #line 44
   if (__cil_tmp4 == 2) {
 #line 44
     goto case_2;
   } else {
     {
 #line 51
     __cil_tmp5 = (unsigned int )cache_level;
 #line 51
     __cil_tmp6 = (int )__cil_tmp5;
 #line 51
     if (__cil_tmp6 == 1) {
 #line 51
       goto case_1;
     } else {
       {
 #line 54
       __cil_tmp7 = (unsigned int )cache_level;
 #line 54
       __cil_tmp8 = (int )__cil_tmp7;
 #line 54
       if (__cil_tmp8 == 0) {
 #line 54
         goto case_0;
       } else {
 #line 53
         goto switch_default;
 #line 43
         if (0) {
           case_2: ;
           {
 #line 45
           __cil_tmp9 = dev->dev_private;
 #line 45
           __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
 #line 45
           __cil_tmp11 = __cil_tmp10->info;
 #line 45
           __cil_tmp12 = __cil_tmp11->gen;
 #line 45
           __cil_tmp13 = (unsigned char )__cil_tmp12;
 #line 45
           __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 45
           if (__cil_tmp14 > 5U) {
 #line 46
             return (65538U);
           } else {
 
           }
           }
           case_1: ;
 #line 52
           return (65537U);
           switch_default: ;
           case_0: ;
 #line 55
           return (65536U);
         } else {
 
         }
       }
       }
     }
     }
   }
   }
 }
 }
 #line 59 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_gtt.c.p"
 void i915_gem_restore_gtt_mappings(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   struct list_head  const  *__mptr ;
   unsigned int agp_type ;
   unsigned int tmp ;
   long tmp___0 ;
   struct list_head  const  *__mptr___0 ;
   void *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   struct drm_i915_gem_object *__cil_tmp19 ;
   unsigned char __cil_tmp20 ;
   enum i915_cache_level __cil_tmp21 ;
   struct intel_gtt  const  *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   struct scatterlist *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct scatterlist *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   int __cil_tmp31 ;
   long __cil_tmp32 ;
   struct scatterlist *__cil_tmp33 ;
   int __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   struct drm_mm_node *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   struct drm_mm_node *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   size_t __cil_tmp44 ;
   size_t __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   struct page **__cil_tmp47 ;
   struct list_head *__cil_tmp48 ;
   struct drm_i915_gem_object *__cil_tmp49 ;
   struct list_head *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   struct list_head *__cil_tmp52 ;
   unsigned long __cil_tmp53 ;
 
   {
   {
 #line 61
   __cil_tmp9 = dev->dev_private;
 #line 61
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 65
   __cil_tmp10 = dev_priv->mm.gtt_start;
 #line 65
   __cil_tmp11 = __cil_tmp10 / 4096UL;
 #line 65
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 65
   __cil_tmp13 = dev_priv->mm.gtt_start;
 #line 65
   __cil_tmp14 = dev_priv->mm.gtt_end;
 #line 65
   __cil_tmp15 = __cil_tmp14 - __cil_tmp13;
 #line 65
   __cil_tmp16 = __cil_tmp15 / 4096UL;
 #line 65
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 65
   intel_gtt_clear_range(__cil_tmp12, __cil_tmp17);
 #line 68
   __cil_tmp18 = dev_priv->mm.gtt_list.next;
 #line 68
   __mptr = (struct list_head  const  *)__cil_tmp18;
 #line 68
   __cil_tmp19 = (struct drm_i915_gem_object *)__mptr;
 #line 68
   obj = __cil_tmp19 + 1152921504606846832UL;
   }
 #line 68
   goto ldv_37568;
   ldv_37567: 
   {
 #line 69
   __cil_tmp20 = obj->cache_level;
 #line 69
   __cil_tmp21 = (enum i915_cache_level )__cil_tmp20;
 #line 69
   tmp = cache_level_to_agp_type(dev, __cil_tmp21);
 #line 69
   agp_type = tmp;
 #line 72
   i915_gem_clflush_object(obj);
   }
   {
 #line 74
   __cil_tmp22 = dev_priv->mm.gtt;
 #line 74
   __cil_tmp23 = (unsigned char *)__cil_tmp22;
 #line 74
   __cil_tmp24 = __cil_tmp23 + 12UL;
 #line 74
   __cil_tmp25 = *__cil_tmp24;
 #line 74
   __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 74
   if (__cil_tmp26 != 0U) {
     {
 #line 75
     __cil_tmp27 = (struct scatterlist *)0;
 #line 75
     __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 75
     __cil_tmp29 = obj->sg_list;
 #line 75
     __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 75
     __cil_tmp31 = __cil_tmp30 == __cil_tmp28;
 #line 75
     __cil_tmp32 = (long )__cil_tmp31;
 #line 75
     tmp___0 = __builtin_expect(__cil_tmp32, 0L);
     }
 #line 75
     if (tmp___0 != 0L) {
 #line 75
       __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_gtt.c.p"),
                            "i" (75), "i" (12UL));
       ldv_37566: ;
 #line 75
       goto ldv_37566;
     } else {
 
     }
     {
 #line 77
     __cil_tmp33 = obj->sg_list;
 #line 77
     __cil_tmp34 = obj->num_sg;
 #line 77
     __cil_tmp35 = (unsigned int )__cil_tmp34;
 #line 77
     __cil_tmp36 = obj->gtt_space;
 #line 77
     __cil_tmp37 = __cil_tmp36->start;
 #line 77
     __cil_tmp38 = __cil_tmp37 >> 12;
 #line 77
     __cil_tmp39 = (unsigned int )__cil_tmp38;
 #line 77
     intel_gtt_insert_sg_entries(__cil_tmp33, __cil_tmp35, __cil_tmp39, agp_type);
     }
   } else {
     {
 #line 82
     __cil_tmp40 = obj->gtt_space;
 #line 82
     __cil_tmp41 = __cil_tmp40->start;
 #line 82
     __cil_tmp42 = __cil_tmp41 >> 12;
 #line 82
     __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 82
     __cil_tmp44 = obj->base.size;
 #line 82
     __cil_tmp45 = __cil_tmp44 >> 12;
 #line 82
     __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 82
     __cil_tmp47 = obj->pages;
 #line 82
     intel_gtt_insert_pages(__cil_tmp43, __cil_tmp46, __cil_tmp47, agp_type);
     }
   }
   }
 #line 68
   __cil_tmp48 = obj->gtt_list.next;
 #line 68
   __mptr___0 = (struct list_head  const  *)__cil_tmp48;
 #line 68
   __cil_tmp49 = (struct drm_i915_gem_object *)__mptr___0;
 #line 68
   obj = __cil_tmp49 + 1152921504606846832UL;
   ldv_37568: ;
   {
 #line 68
   __cil_tmp50 = & dev_priv->mm.gtt_list;
 #line 68
   __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 68
   __cil_tmp52 = & obj->gtt_list;
 #line 68
   __cil_tmp53 = (unsigned long )__cil_tmp52;
 #line 68
   if (__cil_tmp53 != __cil_tmp51) {
 #line 69
     goto ldv_37567;
   } else {
 #line 71
     goto ldv_37569;
   }
   }
   ldv_37569: 
   {
 #line 89
   intel_gtt_chipset_flush();
   }
 #line 90
   return;
 }
 }
 #line 92 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_gtt.c.p"
 int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   unsigned int agp_type ;
   unsigned int tmp ;
   int ret ;
   void *__cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   enum i915_cache_level __cil_tmp9 ;
   struct intel_gtt  const  *__cil_tmp10 ;
   unsigned char *__cil_tmp11 ;
   unsigned char *__cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   struct page **__cil_tmp15 ;
   size_t __cil_tmp16 ;
   size_t __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   struct scatterlist **__cil_tmp19 ;
   int *__cil_tmp20 ;
   struct scatterlist *__cil_tmp21 ;
   int __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   struct drm_mm_node *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   struct drm_mm_node *__cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   size_t __cil_tmp32 ;
   size_t __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   struct page **__cil_tmp35 ;
 
   {
   {
 #line 94
   dev = obj->base.dev;
 #line 95
   __cil_tmp7 = dev->dev_private;
 #line 95
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 96
   __cil_tmp8 = obj->cache_level;
 #line 96
   __cil_tmp9 = (enum i915_cache_level )__cil_tmp8;
 #line 96
   tmp = cache_level_to_agp_type(dev, __cil_tmp9);
 #line 96
   agp_type = tmp;
   }
   {
 #line 99
   __cil_tmp10 = dev_priv->mm.gtt;
 #line 99
   __cil_tmp11 = (unsigned char *)__cil_tmp10;
 #line 99
   __cil_tmp12 = __cil_tmp11 + 12UL;
 #line 99
   __cil_tmp13 = *__cil_tmp12;
 #line 99
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 99
   if (__cil_tmp14 != 0U) {
     {
 #line 100
     __cil_tmp15 = obj->pages;
 #line 100
     __cil_tmp16 = obj->base.size;
 #line 100
     __cil_tmp17 = __cil_tmp16 >> 12;
 #line 100
     __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 100
     __cil_tmp19 = & obj->sg_list;
 #line 100
     __cil_tmp20 = & obj->num_sg;
 #line 100
     ret = intel_gtt_map_memory(__cil_tmp15, __cil_tmp18, __cil_tmp19, __cil_tmp20);
     }
 #line 104
     if (ret != 0) {
 #line 105
       return (ret);
     } else {
 
     }
     {
 #line 107
     __cil_tmp21 = obj->sg_list;
 #line 107
     __cil_tmp22 = obj->num_sg;
 #line 107
     __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 107
     __cil_tmp24 = obj->gtt_space;
 #line 107
     __cil_tmp25 = __cil_tmp24->start;
 #line 107
     __cil_tmp26 = __cil_tmp25 >> 12;
 #line 107
     __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 107
     intel_gtt_insert_sg_entries(__cil_tmp21, __cil_tmp23, __cil_tmp27, agp_type);
     }
   } else {
     {
 #line 112
     __cil_tmp28 = obj->gtt_space;
 #line 112
     __cil_tmp29 = __cil_tmp28->start;
 #line 112
     __cil_tmp30 = __cil_tmp29 >> 12;
 #line 112
     __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 112
     __cil_tmp32 = obj->base.size;
 #line 112
     __cil_tmp33 = __cil_tmp32 >> 12;
 #line 112
     __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 112
     __cil_tmp35 = obj->pages;
 #line 112
     intel_gtt_insert_pages(__cil_tmp31, __cil_tmp34, __cil_tmp35, agp_type);
     }
   }
   }
 #line 117
   return (0);
 }
 }
 #line 120 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_gtt.c.p"
 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj ) 
 { struct drm_mm_node *__cil_tmp2 ;
   unsigned long __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   size_t __cil_tmp6 ;
   size_t __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   struct scatterlist *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct scatterlist *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct scatterlist *__cil_tmp13 ;
   int __cil_tmp14 ;
 
   {
   {
 #line 122
   __cil_tmp2 = obj->gtt_space;
 #line 122
   __cil_tmp3 = __cil_tmp2->start;
 #line 122
   __cil_tmp4 = __cil_tmp3 >> 12;
 #line 122
   __cil_tmp5 = (unsigned int )__cil_tmp4;
 #line 122
   __cil_tmp6 = obj->base.size;
 #line 122
   __cil_tmp7 = __cil_tmp6 >> 12;
 #line 122
   __cil_tmp8 = (unsigned int )__cil_tmp7;
 #line 122
   intel_gtt_clear_range(__cil_tmp5, __cil_tmp8);
   }
   {
 #line 125
   __cil_tmp9 = (struct scatterlist *)0;
 #line 125
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 125
   __cil_tmp11 = obj->sg_list;
 #line 125
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 125
   if (__cil_tmp12 != __cil_tmp10) {
     {
 #line 126
     __cil_tmp13 = obj->sg_list;
 #line 126
     __cil_tmp14 = obj->num_sg;
 #line 126
     intel_gtt_unmap_memory(__cil_tmp13, __cil_tmp14);
 #line 127
     obj->sg_list = (struct scatterlist *)0;
     }
   } else {
 
   }
   }
 #line 129
   return;
 }
 }
 #line 82 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/bitops.h"
 __inline static void __set_bit(int nr , unsigned long volatile   *addr ) 
 { long volatile   *__cil_tmp3 ;
 
   {
 #line 84
   __cil_tmp3 = (long volatile   *)addr;
 #line 84
   __asm__  volatile   ("bts %1,%0": "+m" (*__cil_tmp3): "Ir" (nr): "memory");
 #line 85
   return;
 }
 }
 #line 125 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/bitops.h"
 __inline static void __clear_bit(int nr , unsigned long volatile   *addr ) 
 { long volatile   *__cil_tmp3 ;
 
   {
 #line 127
   __cil_tmp3 = (long volatile   *)addr;
 #line 127
   __asm__  volatile   ("btr %1,%0": "+m" (*__cil_tmp3): "Ir" (nr));
 #line 128
   return;
 }
 }
 #line 1360 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u16 i915_read16___1(struct drm_i915_private *dev_priv , u32 reg ) 
 { u16 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1360
   val = (u16 )0U;
   {
 #line 1360
   __cil_tmp4 = dev_priv->info;
 #line 1360
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1360
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1360
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1360
   if (__cil_tmp7 > 5U) {
 #line 1360
     if (reg <= 262143U) {
 #line 1360
       if (reg != 41356U) {
         {
 #line 1360
         gen6_gt_force_wake_get(dev_priv);
 #line 1360
         __cil_tmp8 = (unsigned long )reg;
 #line 1360
         __cil_tmp9 = dev_priv->regs;
 #line 1360
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1360
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1360
         val = readw(__cil_tmp11);
 #line 1360
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1360
         __cil_tmp12 = (unsigned long )reg;
 #line 1360
         __cil_tmp13 = dev_priv->regs;
 #line 1360
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1360
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1360
         val = readw(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1360
       __cil_tmp16 = (unsigned long )reg;
 #line 1360
       __cil_tmp17 = dev_priv->regs;
 #line 1360
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1360
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1360
       val = readw(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1360
     __cil_tmp20 = (unsigned long )reg;
 #line 1360
     __cil_tmp21 = dev_priv->regs;
 #line 1360
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1360
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1360
     val = readw(__cil_tmp23);
     }
   }
   }
   {
 #line 1360
   __cil_tmp24 = (bool )0;
 #line 1360
   __cil_tmp25 = (u64 )val;
 #line 1360
   trace_i915_reg_rw(__cil_tmp24, reg, __cil_tmp25, 2);
   }
 #line 1360
   return (val);
 }
 }
 #line 96 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev ) 
 { drm_i915_private_t *dev_priv ;
   uint32_t swizzle_x ;
   uint32_t swizzle_y ;
   uint32_t dcc ;
   u16 tmp ;
   u16 tmp___0 ;
   void *__cil_tmp8 ;
   void *__cil_tmp9 ;
   struct drm_i915_private *__cil_tmp10 ;
   struct intel_device_info  const  *__cil_tmp11 ;
   u8 __cil_tmp12 ;
   unsigned char __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   void *__cil_tmp15 ;
   struct drm_i915_private *__cil_tmp16 ;
   struct intel_device_info  const  *__cil_tmp17 ;
   u8 __cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char *__cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   int __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
 
   {
 #line 98
   __cil_tmp8 = dev->dev_private;
 #line 98
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 99
   swizzle_x = 5U;
 #line 100
   swizzle_y = 5U;
   {
 #line 102
   __cil_tmp9 = dev->dev_private;
 #line 102
   __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
 #line 102
   __cil_tmp11 = __cil_tmp10->info;
 #line 102
   __cil_tmp12 = __cil_tmp11->gen;
 #line 102
   __cil_tmp13 = (unsigned char )__cil_tmp12;
 #line 102
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 102
   if (__cil_tmp14 > 4U) {
 #line 106
     swizzle_x = 2U;
 #line 107
     swizzle_y = 1U;
   } else {
     {
 #line 108
     __cil_tmp15 = dev->dev_private;
 #line 108
     __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
 #line 108
     __cil_tmp17 = __cil_tmp16->info;
 #line 108
     __cil_tmp18 = __cil_tmp17->gen;
 #line 108
     __cil_tmp19 = (unsigned char )__cil_tmp18;
 #line 108
     __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 108
     if (__cil_tmp20 == 2U) {
 #line 112
       swizzle_x = 0U;
 #line 113
       swizzle_y = 0U;
     } else {
       {
 #line 114
       __cil_tmp21 = dev->dev_private;
 #line 114
       __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 114
       __cil_tmp23 = __cil_tmp22->info;
 #line 114
       __cil_tmp24 = (unsigned char *)__cil_tmp23;
 #line 114
       __cil_tmp25 = __cil_tmp24 + 1UL;
 #line 114
       __cil_tmp26 = *__cil_tmp25;
 #line 114
       __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 114
       if (__cil_tmp27 != 0U) {
         {
 #line 125
         dcc = i915_read32(dev_priv, 66048U);
         }
         {
 #line 127
         __cil_tmp28 = dcc & 3U;
 #line 127
         __cil_tmp29 = (int )__cil_tmp28;
 #line 127
         if (__cil_tmp29 == 0) {
 #line 127
           goto case_0;
         } else {
           {
 #line 128
           __cil_tmp30 = dcc & 3U;
 #line 128
           __cil_tmp31 = (int )__cil_tmp30;
 #line 128
           if (__cil_tmp31 == 1) {
 #line 128
             goto case_1;
           } else {
             {
 #line 132
             __cil_tmp32 = dcc & 3U;
 #line 132
             __cil_tmp33 = (int )__cil_tmp32;
 #line 132
             if (__cil_tmp33 == 2) {
 #line 132
               goto case_2;
             } else
 #line 126
             if (0) {
               case_0: ;
               case_1: 
 #line 129
               swizzle_x = 0U;
 #line 130
               swizzle_y = 0U;
 #line 131
               goto ldv_37065;
               case_2: ;
               {
 #line 133
               __cil_tmp34 = dcc & 1024U;
 #line 133
               if (__cil_tmp34 != 0U) {
 #line 137
                 swizzle_x = 2U;
 #line 138
                 swizzle_y = 1U;
               } else {
                 {
 #line 139
                 __cil_tmp35 = dcc & 512U;
 #line 139
                 if (__cil_tmp35 == 0U) {
 #line 141
                   swizzle_x = 4U;
 #line 142
                   swizzle_y = 3U;
                 } else {
 #line 145
                   swizzle_x = 7U;
 #line 146
                   swizzle_y = 6U;
                 }
                 }
               }
               }
 #line 148
               goto ldv_37065;
             } else {
 
             }
             }
           }
           }
         }
         }
         ldv_37065: ;
 #line 150
         if (dcc == 4294967295U) {
           {
 #line 151
           drm_err("i915_gem_detect_bit_6_swizzle", "Couldn\'t read from MCHBAR.  Disabling tiling.\n");
 #line 153
           swizzle_x = 5U;
 #line 154
           swizzle_y = 5U;
           }
         } else {
 
         }
       } else {
         {
 #line 177
         tmp = i915_read16___1(dev_priv, 66054U);
 #line 177
         tmp___0 = i915_read16___1(dev_priv, 67078U);
         }
         {
 #line 177
         __cil_tmp36 = (int )tmp___0;
 #line 177
         __cil_tmp37 = (int )tmp;
 #line 177
         if (__cil_tmp37 != __cil_tmp36) {
 #line 178
           swizzle_x = 0U;
 #line 179
           swizzle_y = 0U;
         } else {
 #line 181
           swizzle_x = 2U;
 #line 182
           swizzle_y = 1U;
         }
         }
       }
       }
     }
     }
   }
   }
 #line 186
   dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 #line 187
   dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 #line 188
   return;
 }
 }
 #line 192 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 static bool i915_tiling_ok(struct drm_device *dev , int stride , int size , int tiling_mode ) 
 { int tile_width ;
   void *__cil_tmp6 ;
   struct drm_i915_private *__cil_tmp7 ;
   struct intel_device_info  const  *__cil_tmp8 ;
   u8 __cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char *__cil_tmp22 ;
   unsigned char __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   int __cil_tmp25 ;
   void *__cil_tmp26 ;
   struct drm_i915_private *__cil_tmp27 ;
   struct intel_device_info  const  *__cil_tmp28 ;
   u8 __cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   void *__cil_tmp32 ;
   struct drm_i915_private *__cil_tmp33 ;
   struct intel_device_info  const  *__cil_tmp34 ;
   u8 __cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   void *__cil_tmp38 ;
   struct drm_i915_private *__cil_tmp39 ;
   struct intel_device_info  const  *__cil_tmp40 ;
   u8 __cil_tmp41 ;
   unsigned char __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   int __cil_tmp44 ;
   int __cil_tmp45 ;
   int __cil_tmp46 ;
   int __cil_tmp47 ;
 
   {
 #line 197
   if (tiling_mode == 0) {
 #line 198
     return ((bool )1);
   } else {
 
   }
   {
 #line 200
   __cil_tmp6 = dev->dev_private;
 #line 200
   __cil_tmp7 = (struct drm_i915_private *)__cil_tmp6;
 #line 200
   __cil_tmp8 = __cil_tmp7->info;
 #line 200
   __cil_tmp9 = __cil_tmp8->gen;
 #line 200
   __cil_tmp10 = (unsigned char )__cil_tmp9;
 #line 200
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 200
   if (__cil_tmp11 == 2U) {
 #line 202
     tile_width = 128;
   } else
 #line 200
   if (tiling_mode == 2) {
     {
 #line 200
     __cil_tmp12 = dev->dev_private;
 #line 200
     __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 200
     __cil_tmp14 = __cil_tmp13->info;
 #line 200
     __cil_tmp15 = __cil_tmp14->gen;
 #line 200
     __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 200
     __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 200
     if (__cil_tmp17 != 2U) {
       {
 #line 200
       __cil_tmp18 = dev->dev_private;
 #line 200
       __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 200
       __cil_tmp20 = __cil_tmp19->info;
 #line 200
       __cil_tmp21 = (unsigned char *)__cil_tmp20;
 #line 200
       __cil_tmp22 = __cil_tmp21 + 1UL;
 #line 200
       __cil_tmp23 = *__cil_tmp22;
 #line 200
       __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 200
       if (__cil_tmp24 == 0U) {
         {
 #line 200
         __cil_tmp25 = dev->pci_device;
 #line 200
         if (__cil_tmp25 != 9618) {
 #line 202
           tile_width = 128;
         } else {
 #line 204
           tile_width = 512;
         }
         }
       } else {
 #line 204
         tile_width = 512;
       }
       }
     } else {
 #line 204
       tile_width = 512;
     }
     }
   } else {
 #line 204
     tile_width = 512;
   }
   }
   {
 #line 207
   __cil_tmp26 = dev->dev_private;
 #line 207
   __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
 #line 207
   __cil_tmp28 = __cil_tmp27->info;
 #line 207
   __cil_tmp29 = __cil_tmp28->gen;
 #line 207
   __cil_tmp30 = (unsigned char )__cil_tmp29;
 #line 207
   __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 207
   if (__cil_tmp31 > 3U) {
 #line 210
     if (stride > 131199) {
 #line 211
       return ((bool )0);
     } else {
 #line 213
       if (stride > 8192) {
 #line 214
         return ((bool )0);
       } else {
 
       }
       {
 #line 216
       __cil_tmp32 = dev->dev_private;
 #line 216
       __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
 #line 216
       __cil_tmp34 = __cil_tmp33->info;
 #line 216
       __cil_tmp35 = __cil_tmp34->gen;
 #line 216
       __cil_tmp36 = (unsigned char )__cil_tmp35;
 #line 216
       __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 216
       if (__cil_tmp37 == 3U) {
 #line 217
         if (size > 268435456) {
 #line 218
           return ((bool )0);
         } else
 #line 220
         if (size > 134217728) {
 #line 221
           return ((bool )0);
         } else {
 
         }
       } else {
 
       }
       }
     }
   } else {
 
   }
   }
   {
 #line 226
   __cil_tmp38 = dev->dev_private;
 #line 226
   __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
 #line 226
   __cil_tmp40 = __cil_tmp39->info;
 #line 226
   __cil_tmp41 = __cil_tmp40->gen;
 #line 226
   __cil_tmp42 = (unsigned char )__cil_tmp41;
 #line 226
   __cil_tmp43 = (unsigned int )__cil_tmp42;
 #line 226
   if (__cil_tmp43 > 3U) {
     {
 #line 227
     __cil_tmp44 = tile_width + -1;
 #line 227
     __cil_tmp45 = __cil_tmp44 & stride;
 #line 227
     if (__cil_tmp45 != 0) {
 #line 228
       return ((bool )0);
     } else {
 
     }
     }
 #line 229
     return ((bool )1);
   } else {
 
   }
   }
 #line 233
   if (stride < tile_width) {
 #line 234
     return ((bool )0);
   } else {
 
   }
   {
 #line 236
   __cil_tmp46 = stride + -1;
 #line 236
   __cil_tmp47 = __cil_tmp46 & stride;
 #line 236
   if (__cil_tmp47 != 0) {
 #line 237
     return ((bool )0);
   } else {
 
   }
   }
 #line 239
   return ((bool )1);
 }
 }
 #line 244 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 static bool i915_gem_object_fence_ok(struct drm_i915_gem_object *obj , int tiling_mode ) 
 { u32 size ;
   struct drm_device *__cil_tmp4 ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   struct drm_device *__cil_tmp11 ;
   void *__cil_tmp12 ;
   struct drm_i915_private *__cil_tmp13 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   uint32_t __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   uint32_t __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
   struct drm_device *__cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   struct intel_device_info  const  *__cil_tmp25 ;
   u8 __cil_tmp26 ;
   unsigned char __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   size_t __cil_tmp29 ;
   size_t __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   struct drm_mm_node *__cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   u32 __cil_tmp34 ;
   uint32_t __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
 
   {
 #line 248
   if (tiling_mode == 0) {
 #line 249
     return ((bool )1);
   } else {
 
   }
   {
 #line 251
   __cil_tmp4 = obj->base.dev;
 #line 251
   __cil_tmp5 = __cil_tmp4->dev_private;
 #line 251
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 251
   __cil_tmp7 = __cil_tmp6->info;
 #line 251
   __cil_tmp8 = __cil_tmp7->gen;
 #line 251
   __cil_tmp9 = (unsigned char )__cil_tmp8;
 #line 251
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 251
   if (__cil_tmp10 > 3U) {
 #line 252
     return ((bool )1);
   } else {
 
   }
   }
   {
 #line 254
   __cil_tmp11 = obj->base.dev;
 #line 254
   __cil_tmp12 = __cil_tmp11->dev_private;
 #line 254
   __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
 #line 254
   __cil_tmp14 = __cil_tmp13->info;
 #line 254
   __cil_tmp15 = __cil_tmp14->gen;
 #line 254
   __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 254
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 254
   if (__cil_tmp17 == 3U) {
     {
 #line 255
     __cil_tmp18 = obj->gtt_offset;
 #line 255
     __cil_tmp19 = __cil_tmp18 & 4027580415U;
 #line 255
     if (__cil_tmp19 != 0U) {
 #line 256
       return ((bool )0);
     } else {
       {
 #line 258
       __cil_tmp20 = obj->gtt_offset;
 #line 258
       __cil_tmp21 = __cil_tmp20 & 4161273855U;
 #line 258
       if (__cil_tmp21 != 0U) {
 #line 259
         return ((bool )0);
       } else {
 
       }
       }
     }
     }
   } else {
 
   }
   }
   {
 #line 266
   __cil_tmp22 = obj->base.dev;
 #line 266
   __cil_tmp23 = __cil_tmp22->dev_private;
 #line 266
   __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 266
   __cil_tmp25 = __cil_tmp24->info;
 #line 266
   __cil_tmp26 = __cil_tmp25->gen;
 #line 266
   __cil_tmp27 = (unsigned char )__cil_tmp26;
 #line 266
   __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 266
   if (__cil_tmp28 == 3U) {
 #line 267
     size = 1048576U;
   } else {
 #line 269
     size = 524288U;
   }
   }
 #line 271
   goto ldv_37081;
   ldv_37080: 
 #line 272
   size = size << 1;
   ldv_37081: ;
   {
 #line 271
   __cil_tmp29 = obj->base.size;
 #line 271
   __cil_tmp30 = (size_t )size;
 #line 271
   if (__cil_tmp30 < __cil_tmp29) {
 #line 272
     goto ldv_37080;
   } else {
 #line 274
     goto ldv_37082;
   }
   }
   ldv_37082: ;
   {
 #line 274
   __cil_tmp31 = (unsigned long )size;
 #line 274
   __cil_tmp32 = obj->gtt_space;
 #line 274
   __cil_tmp33 = __cil_tmp32->size;
 #line 274
   if (__cil_tmp33 != __cil_tmp31) {
 #line 275
     return ((bool )0);
   } else {
 
   }
   }
   {
 #line 277
   __cil_tmp34 = size - 1U;
 #line 277
   __cil_tmp35 = obj->gtt_offset;
 #line 277
   __cil_tmp36 = __cil_tmp35 & __cil_tmp34;
 #line 277
   if (__cil_tmp36 != 0U) {
 #line 278
     return ((bool )0);
   } else {
 
   }
   }
 #line 280
   return ((bool )1);
 }
 }
 #line 288 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 int i915_gem_set_tiling(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_set_tiling *args ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_object *obj ;
   int ret ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   bool tmp___0 ;
   int tmp___1 ;
   bool tmp___2 ;
   int tmp___3 ;
   u32 unfenced_alignment ;
   uint32_t tmp___4 ;
   void *__cil_tmp16 ;
   __u32 __cil_tmp17 ;
   struct drm_gem_object *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct drm_gem_object *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   __u32 __cil_tmp22 ;
   int __cil_tmp23 ;
   size_t __cil_tmp24 ;
   int __cil_tmp25 ;
   __u32 __cil_tmp26 ;
   int __cil_tmp27 ;
   struct drm_gem_object *__cil_tmp28 ;
   unsigned int *__cil_tmp29 ;
   unsigned int *__cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   struct drm_gem_object *__cil_tmp32 ;
   __u32 __cil_tmp33 ;
   __u32 __cil_tmp34 ;
   __u32 __cil_tmp35 ;
   __u32 __cil_tmp36 ;
   __u32 __cil_tmp37 ;
   struct mutex *__cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   __u32 __cil_tmp40 ;
   __u32 __cil_tmp41 ;
   uint32_t __cil_tmp42 ;
   __u32 __cil_tmp43 ;
   struct drm_mm_node *__cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct drm_mm_node *__cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   size_t __cil_tmp49 ;
   uint32_t __cil_tmp50 ;
   size_t __cil_tmp51 ;
   size_t __cil_tmp52 ;
   __u32 __cil_tmp53 ;
   int __cil_tmp54 ;
   unsigned char *__cil_tmp55 ;
   unsigned char *__cil_tmp56 ;
   unsigned char __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   size_t __cil_tmp59 ;
   uint32_t __cil_tmp60 ;
   __u32 __cil_tmp61 ;
   int __cil_tmp62 ;
   u32 __cil_tmp63 ;
   uint32_t __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   __u32 __cil_tmp66 ;
   unsigned char __cil_tmp67 ;
   struct drm_gem_object *__cil_tmp68 ;
   struct mutex *__cil_tmp69 ;
 
   {
   {
 #line 291
   args = (struct drm_i915_gem_set_tiling *)data;
 #line 292
   __cil_tmp16 = dev->dev_private;
 #line 292
   dev_priv = (drm_i915_private_t *)__cil_tmp16;
 #line 294
   ret = 0;
 #line 296
   __cil_tmp17 = args->handle;
 #line 296
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp17);
 #line 296
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 296
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 297
   __cil_tmp18 = (struct drm_gem_object *)0;
 #line 297
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 297
   __cil_tmp20 = & obj->base;
 #line 297
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 297
   if (__cil_tmp21 == __cil_tmp19) {
 #line 298
     return (-2);
   } else {
 
   }
   }
   {
 #line 300
   __cil_tmp22 = args->stride;
 #line 300
   __cil_tmp23 = (int )__cil_tmp22;
 #line 300
   __cil_tmp24 = obj->base.size;
 #line 300
   __cil_tmp25 = (int )__cil_tmp24;
 #line 300
   __cil_tmp26 = args->tiling_mode;
 #line 300
   __cil_tmp27 = (int )__cil_tmp26;
 #line 300
   tmp___0 = i915_tiling_ok(dev, __cil_tmp23, __cil_tmp25, __cil_tmp27);
   }
 #line 300
   if (tmp___0) {
 #line 300
     tmp___1 = 0;
   } else {
 #line 300
     tmp___1 = 1;
   }
 #line 300
   if (tmp___1) {
     {
 #line 302
     __cil_tmp28 = & obj->base;
 #line 302
     drm_gem_object_unreference_unlocked(__cil_tmp28);
     }
 #line 303
     return (-22);
   } else {
 
   }
   {
 #line 306
   __cil_tmp29 = (unsigned int *)obj;
 #line 306
   __cil_tmp30 = __cil_tmp29 + 56UL;
 #line 306
   __cil_tmp31 = *__cil_tmp30;
 #line 306
   if (__cil_tmp31 != 0U) {
     {
 #line 307
     __cil_tmp32 = & obj->base;
 #line 307
     drm_gem_object_unreference_unlocked(__cil_tmp32);
     }
 #line 308
     return (-16);
   } else {
 
   }
   }
   {
 #line 311
   __cil_tmp33 = args->tiling_mode;
 #line 311
   if (__cil_tmp33 == 0U) {
 #line 312
     args->swizzle_mode = 0U;
 #line 313
     args->stride = 0U;
   } else {
     {
 #line 315
     __cil_tmp34 = args->tiling_mode;
 #line 315
     if (__cil_tmp34 == 1U) {
 #line 316
       args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
     } else {
 #line 318
       args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
     }
     }
     {
 #line 327
     __cil_tmp35 = args->swizzle_mode;
 #line 327
     if (__cil_tmp35 == 6U) {
 #line 328
       args->swizzle_mode = 1U;
     } else {
 
     }
     }
     {
 #line 329
     __cil_tmp36 = args->swizzle_mode;
 #line 329
     if (__cil_tmp36 == 7U) {
 #line 330
       args->swizzle_mode = 2U;
     } else {
 
     }
     }
     {
 #line 333
     __cil_tmp37 = args->swizzle_mode;
 #line 333
     if (__cil_tmp37 == 5U) {
 #line 334
       args->tiling_mode = 0U;
 #line 335
       args->swizzle_mode = 0U;
 #line 336
       args->stride = 0U;
     } else {
 
     }
     }
   }
   }
   {
 #line 340
   __cil_tmp38 = & dev->struct_mutex;
 #line 340
   mutex_lock_nested(__cil_tmp38, 0U);
   }
   {
 #line 341
   __cil_tmp39 = obj->tiling_mode;
 #line 341
   __cil_tmp40 = (__u32 )__cil_tmp39;
 #line 341
   __cil_tmp41 = args->tiling_mode;
 #line 341
   if (__cil_tmp41 != __cil_tmp40) {
 #line 341
     goto _L;
   } else {
     {
 #line 341
     __cil_tmp42 = obj->stride;
 #line 341
     __cil_tmp43 = args->stride;
 #line 341
     if (__cil_tmp43 != __cil_tmp42) {
       _L: 
       {
 #line 348
       i915_gem_release_mmap(obj);
       }
       {
 #line 350
       __cil_tmp44 = (struct drm_mm_node *)0;
 #line 350
       __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 350
       __cil_tmp46 = obj->gtt_space;
 #line 350
       __cil_tmp47 = (unsigned long )__cil_tmp46;
 #line 350
       if (__cil_tmp47 == __cil_tmp45) {
 #line 350
         tmp___3 = 1;
       } else {
         {
 #line 350
         __cil_tmp48 = dev_priv->mm.gtt_mappable_end;
 #line 350
         __cil_tmp49 = obj->base.size;
 #line 350
         __cil_tmp50 = obj->gtt_offset;
 #line 350
         __cil_tmp51 = (size_t )__cil_tmp50;
 #line 350
         __cil_tmp52 = __cil_tmp51 + __cil_tmp49;
 #line 350
         if (__cil_tmp52 <= __cil_tmp48) {
           {
 #line 350
           __cil_tmp53 = args->tiling_mode;
 #line 350
           __cil_tmp54 = (int )__cil_tmp53;
 #line 350
           tmp___2 = i915_gem_object_fence_ok(obj, __cil_tmp54);
           }
 #line 350
           if ((int )tmp___2) {
 #line 350
             tmp___3 = 1;
           } else {
 #line 350
             tmp___3 = 0;
           }
         } else {
 #line 350
           tmp___3 = 0;
         }
         }
       }
       }
 #line 350
       obj->map_and_fenceable = (unsigned char )tmp___3;
       {
 #line 356
       __cil_tmp55 = (unsigned char *)obj;
 #line 356
       __cil_tmp56 = __cil_tmp55 + 226UL;
 #line 356
       __cil_tmp57 = *__cil_tmp56;
 #line 356
       __cil_tmp58 = (unsigned int )__cil_tmp57;
 #line 356
       if (__cil_tmp58 == 0U) {
         {
 #line 357
         __cil_tmp59 = obj->base.size;
 #line 357
         __cil_tmp60 = (uint32_t )__cil_tmp59;
 #line 357
         __cil_tmp61 = args->tiling_mode;
 #line 357
         __cil_tmp62 = (int )__cil_tmp61;
 #line 357
         tmp___4 = i915_gem_get_unfenced_gtt_alignment(dev, __cil_tmp60, __cil_tmp62);
 #line 357
         unfenced_alignment = tmp___4;
         }
         {
 #line 361
         __cil_tmp63 = unfenced_alignment - 1U;
 #line 361
         __cil_tmp64 = obj->gtt_offset;
 #line 361
         __cil_tmp65 = __cil_tmp64 & __cil_tmp63;
 #line 361
         if (__cil_tmp65 != 0U) {
           {
 #line 362
           ret = i915_gem_object_unbind(obj);
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
 #line 365
       if (ret == 0) {
 #line 366
         obj->tiling_changed = (unsigned char)1;
 #line 367
         __cil_tmp66 = args->tiling_mode;
 #line 367
         obj->tiling_mode = (unsigned char )__cil_tmp66;
 #line 368
         obj->stride = args->stride;
       } else {
 
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 372
   args->stride = obj->stride;
 #line 373
   __cil_tmp67 = obj->tiling_mode;
 #line 373
   args->tiling_mode = (__u32 )__cil_tmp67;
 #line 374
   __cil_tmp68 = & obj->base;
 #line 374
   drm_gem_object_unreference(__cil_tmp68);
 #line 375
   __cil_tmp69 = & dev->struct_mutex;
 #line 375
   mutex_unlock(__cil_tmp69);
   }
 #line 377
   return (ret);
 }
 }
 #line 384 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 int i915_gem_get_tiling(struct drm_device *dev , void *data , struct drm_file *file ) 
 { struct drm_i915_gem_get_tiling *args ;
   drm_i915_private_t *dev_priv ;
   struct drm_i915_gem_object *obj ;
   struct drm_gem_object  const  *__mptr ;
   struct drm_gem_object *tmp ;
   void *__cil_tmp9 ;
   __u32 __cil_tmp10 ;
   struct drm_gem_object *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_gem_object *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   struct mutex *__cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   int __cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   int __cil_tmp20 ;
   unsigned char __cil_tmp21 ;
   int __cil_tmp22 ;
   __u32 __cil_tmp23 ;
   __u32 __cil_tmp24 ;
   struct drm_gem_object *__cil_tmp25 ;
   struct mutex *__cil_tmp26 ;
 
   {
   {
 #line 387
   args = (struct drm_i915_gem_get_tiling *)data;
 #line 388
   __cil_tmp9 = dev->dev_private;
 #line 388
   dev_priv = (drm_i915_private_t *)__cil_tmp9;
 #line 391
   __cil_tmp10 = args->handle;
 #line 391
   tmp = drm_gem_object_lookup(dev, file, __cil_tmp10);
 #line 391
   __mptr = (struct drm_gem_object  const  *)tmp;
 #line 391
   obj = (struct drm_i915_gem_object *)__mptr;
   }
   {
 #line 392
   __cil_tmp11 = (struct drm_gem_object *)0;
 #line 392
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 392
   __cil_tmp13 = & obj->base;
 #line 392
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 392
   if (__cil_tmp14 == __cil_tmp12) {
 #line 393
     return (-2);
   } else {
 
   }
   }
   {
 #line 395
   __cil_tmp15 = & dev->struct_mutex;
 #line 395
   mutex_lock_nested(__cil_tmp15, 0U);
 #line 397
   __cil_tmp16 = obj->tiling_mode;
 #line 397
   args->tiling_mode = (__u32 )__cil_tmp16;
   }
   {
 #line 399
   __cil_tmp17 = obj->tiling_mode;
 #line 399
   __cil_tmp18 = (int )__cil_tmp17;
 #line 399
   if (__cil_tmp18 == 1) {
 #line 399
     goto case_1;
   } else {
     {
 #line 402
     __cil_tmp19 = obj->tiling_mode;
 #line 402
     __cil_tmp20 = (int )__cil_tmp19;
 #line 402
     if (__cil_tmp20 == 2) {
 #line 402
       goto case_2;
     } else {
       {
 #line 405
       __cil_tmp21 = obj->tiling_mode;
 #line 405
       __cil_tmp22 = (int )__cil_tmp21;
 #line 405
       if (__cil_tmp22 == 0) {
 #line 405
         goto case_0;
       } else {
 #line 408
         goto switch_default;
 #line 398
         if (0) {
           case_1: 
 #line 400
           args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 #line 401
           goto ldv_37106;
           case_2: 
 #line 403
           args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 #line 404
           goto ldv_37106;
           case_0: 
 #line 406
           args->swizzle_mode = 0U;
 #line 407
           goto ldv_37106;
           switch_default: 
           {
 #line 409
           drm_err("i915_gem_get_tiling", "unknown tiling mode\n");
           }
         } else {
 
         }
       }
       }
     }
     }
   }
   }
   ldv_37106: ;
   {
 #line 413
   __cil_tmp23 = args->swizzle_mode;
 #line 413
   if (__cil_tmp23 == 6U) {
 #line 414
     args->swizzle_mode = 1U;
   } else {
 
   }
   }
   {
 #line 415
   __cil_tmp24 = args->swizzle_mode;
 #line 415
   if (__cil_tmp24 == 7U) {
 #line 416
     args->swizzle_mode = 2U;
   } else {
 
   }
   }
   {
 #line 418
   __cil_tmp25 = & obj->base;
 #line 418
   drm_gem_object_unreference(__cil_tmp25);
 #line 419
   __cil_tmp26 = & dev->struct_mutex;
 #line 419
   mutex_unlock(__cil_tmp26);
   }
 #line 421
   return (0);
 }
 }
 #line 430 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 static void i915_gem_swizzle_page(struct page *page ) 
 { char temp[64U] ;
   char *vaddr ;
   int i ;
   void *tmp ;
   size_t __len ;
   void *__ret ;
   size_t __len___0 ;
   void *__ret___0 ;
   size_t __len___1 ;
   void *__ret___1 ;
   void *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   void const   *__cil_tmp14 ;
   void const   *__cil_tmp15 ;
   void *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   void const   *__cil_tmp18 ;
   void const   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   char *__cil_tmp25 ;
   void const   *__cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   void *__cil_tmp28 ;
   void *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   char *__cil_tmp32 ;
   void const   *__cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   char *__cil_tmp36 ;
   void *__cil_tmp37 ;
   void const   *__cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   char *__cil_tmp41 ;
   void *__cil_tmp42 ;
   void const   *__cil_tmp43 ;
   unsigned int __cil_tmp44 ;
 
   {
   {
 #line 436
   tmp = kmap(page);
 #line 436
   vaddr = (char *)tmp;
 #line 438
   i = 0;
   }
 #line 438
   goto ldv_37127;
   ldv_37126: 
 #line 439
   __len = 64UL;
 #line 439
   if (__len > 63UL) {
     {
 #line 439
     __cil_tmp12 = (void *)(& temp);
 #line 439
     __cil_tmp13 = (unsigned long )i;
 #line 439
     __cil_tmp14 = (void const   *)vaddr;
 #line 439
     __cil_tmp15 = __cil_tmp14 + __cil_tmp13;
 #line 439
     __ret = __memcpy(__cil_tmp12, __cil_tmp15, __len);
     }
   } else {
     {
 #line 439
     __cil_tmp16 = (void *)(& temp);
 #line 439
     __cil_tmp17 = (unsigned long )i;
 #line 439
     __cil_tmp18 = (void const   *)vaddr;
 #line 439
     __cil_tmp19 = __cil_tmp18 + __cil_tmp17;
 #line 439
     __ret = __builtin_memcpy(__cil_tmp16, __cil_tmp19, __len);
     }
   }
 #line 440
   __len___0 = 64UL;
 #line 440
   if (__len___0 > 63UL) {
     {
 #line 440
     __cil_tmp20 = (unsigned long )i;
 #line 440
     __cil_tmp21 = (void *)vaddr;
 #line 440
     __cil_tmp22 = __cil_tmp21 + __cil_tmp20;
 #line 440
     __cil_tmp23 = (unsigned long )i;
 #line 440
     __cil_tmp24 = __cil_tmp23 + 64UL;
 #line 440
     __cil_tmp25 = vaddr + __cil_tmp24;
 #line 440
     __cil_tmp26 = (void const   *)__cil_tmp25;
 #line 440
     __ret___0 = __memcpy(__cil_tmp22, __cil_tmp26, __len___0);
     }
   } else {
     {
 #line 440
     __cil_tmp27 = (unsigned long )i;
 #line 440
     __cil_tmp28 = (void *)vaddr;
 #line 440
     __cil_tmp29 = __cil_tmp28 + __cil_tmp27;
 #line 440
     __cil_tmp30 = (unsigned long )i;
 #line 440
     __cil_tmp31 = __cil_tmp30 + 64UL;
 #line 440
     __cil_tmp32 = vaddr + __cil_tmp31;
 #line 440
     __cil_tmp33 = (void const   *)__cil_tmp32;
 #line 440
     __ret___0 = __builtin_memcpy(__cil_tmp29, __cil_tmp33, __len___0);
     }
   }
 #line 441
   __len___1 = 64UL;
 #line 441
   if (__len___1 > 63UL) {
     {
 #line 441
     __cil_tmp34 = (unsigned long )i;
 #line 441
     __cil_tmp35 = __cil_tmp34 + 64UL;
 #line 441
     __cil_tmp36 = vaddr + __cil_tmp35;
 #line 441
     __cil_tmp37 = (void *)__cil_tmp36;
 #line 441
     __cil_tmp38 = (void const   *)(& temp);
 #line 441
     __ret___1 = __memcpy(__cil_tmp37, __cil_tmp38, __len___1);
     }
   } else {
     {
 #line 441
     __cil_tmp39 = (unsigned long )i;
 #line 441
     __cil_tmp40 = __cil_tmp39 + 64UL;
 #line 441
     __cil_tmp41 = vaddr + __cil_tmp40;
 #line 441
     __cil_tmp42 = (void *)__cil_tmp41;
 #line 441
     __cil_tmp43 = (void const   *)(& temp);
 #line 441
     __ret___1 = __builtin_memcpy(__cil_tmp42, __cil_tmp43, __len___1);
     }
   }
 #line 438
   i = i + 128;
   ldv_37127: ;
   {
 #line 438
   __cil_tmp44 = (unsigned int )i;
 #line 438
   if (__cil_tmp44 <= 4095U) {
 #line 439
     goto ldv_37126;
   } else {
 #line 441
     goto ldv_37128;
   }
   }
   ldv_37128: 
   {
 #line 444
   kunmap(page);
   }
 #line 445
   return;
 }
 }
 #line 448 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int page_count___0 ;
   int i ;
   char new_bit_17 ;
   int tmp ;
   void *__cil_tmp8 ;
   size_t __cil_tmp9 ;
   size_t __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   unsigned long *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long *__cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct page **__cil_tmp17 ;
   struct page **__cil_tmp18 ;
   struct page *__cil_tmp19 ;
   long __cil_tmp20 ;
   long __cil_tmp21 ;
   long __cil_tmp22 ;
   unsigned long long __cil_tmp23 ;
   unsigned long long __cil_tmp24 ;
   unsigned long long __cil_tmp25 ;
   unsigned long *__cil_tmp26 ;
   unsigned long const volatile   *__cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   _Bool __cil_tmp31 ;
   int __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   struct page **__cil_tmp34 ;
   struct page **__cil_tmp35 ;
   struct page *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct page **__cil_tmp38 ;
   struct page **__cil_tmp39 ;
   struct page *__cil_tmp40 ;
 
   {
 #line 450
   dev = obj->base.dev;
 #line 451
   __cil_tmp8 = dev->dev_private;
 #line 451
   dev_priv = (drm_i915_private_t *)__cil_tmp8;
 #line 452
   __cil_tmp9 = obj->base.size;
 #line 452
   __cil_tmp10 = __cil_tmp9 >> 12;
 #line 452
   page_count___0 = (int )__cil_tmp10;
   {
 #line 455
   __cil_tmp11 = dev_priv->mm.bit_6_swizzle_x;
 #line 455
   if (__cil_tmp11 != 7U) {
 #line 456
     return;
   } else {
 
   }
   }
   {
 #line 458
   __cil_tmp12 = (unsigned long *)0;
 #line 458
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 458
   __cil_tmp14 = obj->bit_17;
 #line 458
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 458
   if (__cil_tmp15 == __cil_tmp13) {
 #line 459
     return;
   } else {
 
   }
   }
 #line 461
   i = 0;
 #line 461
   goto ldv_37138;
   ldv_37137: 
   {
 #line 462
   __cil_tmp16 = (unsigned long )i;
 #line 462
   __cil_tmp17 = obj->pages;
 #line 462
   __cil_tmp18 = __cil_tmp17 + __cil_tmp16;
 #line 462
   __cil_tmp19 = *__cil_tmp18;
 #line 462
   __cil_tmp20 = (long )__cil_tmp19;
 #line 462
   __cil_tmp21 = __cil_tmp20 + 24189255811072L;
 #line 462
   __cil_tmp22 = __cil_tmp21 / 56L;
 #line 462
   __cil_tmp23 = (unsigned long long )__cil_tmp22;
 #line 462
   __cil_tmp24 = __cil_tmp23 << 12;
 #line 462
   __cil_tmp25 = __cil_tmp24 >> 17;
 #line 462
   new_bit_17 = (char )__cil_tmp25;
 #line 463
   __cil_tmp26 = obj->bit_17;
 #line 463
   __cil_tmp27 = (unsigned long const volatile   *)__cil_tmp26;
 #line 463
   tmp = variable_test_bit(i, __cil_tmp27);
   }
   {
 #line 463
   __cil_tmp28 = tmp != 0;
 #line 463
   __cil_tmp29 = (int )new_bit_17;
 #line 463
   __cil_tmp30 = __cil_tmp29 & 1;
 #line 463
   __cil_tmp31 = (_Bool )__cil_tmp30;
 #line 463
   __cil_tmp32 = (int )__cil_tmp31;
 #line 463
   if (__cil_tmp32 ^ __cil_tmp28) {
     {
 #line 465
     __cil_tmp33 = (unsigned long )i;
 #line 465
     __cil_tmp34 = obj->pages;
 #line 465
     __cil_tmp35 = __cil_tmp34 + __cil_tmp33;
 #line 465
     __cil_tmp36 = *__cil_tmp35;
 #line 465
     i915_gem_swizzle_page(__cil_tmp36);
 #line 466
     __cil_tmp37 = (unsigned long )i;
 #line 466
     __cil_tmp38 = obj->pages;
 #line 466
     __cil_tmp39 = __cil_tmp38 + __cil_tmp37;
 #line 466
     __cil_tmp40 = *__cil_tmp39;
 #line 466
     set_page_dirty(__cil_tmp40);
     }
   } else {
 
   }
   }
 #line 461
   i = i + 1;
   ldv_37138: ;
 #line 461
   if (i < page_count___0) {
 #line 462
     goto ldv_37137;
   } else {
 #line 464
     goto ldv_37139;
   }
   ldv_37139: ;
 #line 466
   return;
 }
 }
 #line 472 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_gem_tiling.c.p"
 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj ) 
 { struct drm_device *dev ;
   drm_i915_private_t *dev_priv ;
   int page_count___0 ;
   int i ;
   void *tmp ;
   void *__cil_tmp7 ;
   size_t __cil_tmp8 ;
   size_t __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   unsigned long *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct page **__cil_tmp24 ;
   struct page **__cil_tmp25 ;
   struct page *__cil_tmp26 ;
   long __cil_tmp27 ;
   long __cil_tmp28 ;
   long __cil_tmp29 ;
   unsigned long long __cil_tmp30 ;
   unsigned long long __cil_tmp31 ;
   unsigned long long __cil_tmp32 ;
   unsigned long *__cil_tmp33 ;
   unsigned long volatile   *__cil_tmp34 ;
   unsigned long *__cil_tmp35 ;
   unsigned long volatile   *__cil_tmp36 ;
 
   {
 #line 474
   dev = obj->base.dev;
 #line 475
   __cil_tmp7 = dev->dev_private;
 #line 475
   dev_priv = (drm_i915_private_t *)__cil_tmp7;
 #line 476
   __cil_tmp8 = obj->base.size;
 #line 476
   __cil_tmp9 = __cil_tmp8 >> 12;
 #line 476
   page_count___0 = (int )__cil_tmp9;
   {
 #line 479
   __cil_tmp10 = dev_priv->mm.bit_6_swizzle_x;
 #line 479
   if (__cil_tmp10 != 7U) {
 #line 480
     return;
   } else {
 
   }
   }
   {
 #line 482
   __cil_tmp11 = (unsigned long *)0;
 #line 482
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 482
   __cil_tmp13 = obj->bit_17;
 #line 482
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 482
   if (__cil_tmp14 == __cil_tmp12) {
     {
 #line 483
     __cil_tmp15 = (unsigned long )page_count___0;
 #line 483
     __cil_tmp16 = __cil_tmp15 + 63UL;
 #line 483
     __cil_tmp17 = __cil_tmp16 / 64UL;
 #line 483
     __cil_tmp18 = __cil_tmp17 * 8UL;
 #line 483
     tmp = kmalloc(__cil_tmp18, 208U);
 #line 483
     obj->bit_17 = (unsigned long *)tmp;
     }
     {
 #line 485
     __cil_tmp19 = (unsigned long *)0;
 #line 485
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 485
     __cil_tmp21 = obj->bit_17;
 #line 485
     __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 485
     if (__cil_tmp22 == __cil_tmp20) {
       {
 #line 486
       drm_err("i915_gem_object_save_bit_17_swizzle", "Failed to allocate memory for bit 17 record\n");
       }
 #line 488
       return;
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 492
   i = 0;
 #line 492
   goto ldv_37149;
   ldv_37148: ;
   {
 #line 493
   __cil_tmp23 = (unsigned long )i;
 #line 493
   __cil_tmp24 = obj->pages;
 #line 493
   __cil_tmp25 = __cil_tmp24 + __cil_tmp23;
 #line 493
   __cil_tmp26 = *__cil_tmp25;
 #line 493
   __cil_tmp27 = (long )__cil_tmp26;
 #line 493
   __cil_tmp28 = __cil_tmp27 + 24189255811072L;
 #line 493
   __cil_tmp29 = __cil_tmp28 / 56L;
 #line 493
   __cil_tmp30 = (unsigned long long )__cil_tmp29;
 #line 493
   __cil_tmp31 = __cil_tmp30 << 12;
 #line 493
   __cil_tmp32 = __cil_tmp31 & 131072ULL;
 #line 493
   if (__cil_tmp32 != 0ULL) {
     {
 #line 494
     __cil_tmp33 = obj->bit_17;
 #line 494
     __cil_tmp34 = (unsigned long volatile   *)__cil_tmp33;
 #line 494
     __set_bit(i, __cil_tmp34);
     }
   } else {
     {
 #line 496
     __cil_tmp35 = obj->bit_17;
 #line 496
     __cil_tmp36 = (unsigned long volatile   *)__cil_tmp35;
 #line 496
     __clear_bit(i, __cil_tmp36);
     }
   }
   }
 #line 492
   i = i + 1;
   ldv_37149: ;
 #line 492
   if (i < page_count___0) {
 #line 493
     goto ldv_37148;
   } else {
 #line 495
     goto ldv_37150;
   }
   ldv_37150: ;
 #line 497
   return;
 }
 }
 #line 344 "drivers/gpu/drm/i915/i915_trace.h"
 struct tracepoint __tracepoint_i915_ring_wait_begin ;
 #line 349
 struct tracepoint __tracepoint_i915_ring_wait_end ;
 #line 367
 struct tracepoint __tracepoint_i915_flip_request ;
 #line 385
 struct tracepoint __tracepoint_i915_flip_complete ;
 #line 34 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_create[23U]  = 
 #line 34 "drivers/gpu/drm/i915/./i915_trace.h"
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'c',      (char const   )'r',      (char const   )'e',      (char const   )'a', 
         (char const   )'t',      (char const   )'e',      (char const   )'\000'};
 #line 34 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_create  =    {(char const   *)(& __tpstrtab_i915_gem_object_create), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 57 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_bind[21U]  = 
 #line 57
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'b',      (char const   )'i',      (char const   )'n',      (char const   )'d', 
         (char const   )'\000'};
 #line 57 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_bind  =    {(char const   *)(& __tpstrtab_i915_gem_object_bind), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 77 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_unbind[23U]  = 
 #line 77
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'u',      (char const   )'n',      (char const   )'b',      (char const   )'i', 
         (char const   )'n',      (char const   )'d',      (char const   )'\000'};
 #line 77 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_unbind  =    {(char const   *)(& __tpstrtab_i915_gem_object_unbind), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 101 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_change_domain[30U]  = 
 #line 101
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'c',      (char const   )'h',      (char const   )'a',      (char const   )'n', 
         (char const   )'g',      (char const   )'e',      (char const   )'_',      (char const   )'d', 
         (char const   )'o',      (char const   )'m',      (char const   )'a',      (char const   )'i', 
         (char const   )'n',      (char const   )'\000'};
 #line 101 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_change_domain  =    {(char const   *)(& __tpstrtab_i915_gem_object_change_domain), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 121 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_pwrite[23U]  = 
 #line 121
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'p',      (char const   )'w',      (char const   )'r',      (char const   )'i', 
         (char const   )'t',      (char const   )'e',      (char const   )'\000'};
 #line 121 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_pwrite  =    {(char const   *)(& __tpstrtab_i915_gem_object_pwrite), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 141 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_pread[22U]  = 
 #line 141
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'p',      (char const   )'r',      (char const   )'e',      (char const   )'a', 
         (char const   )'d',      (char const   )'\000'};
 #line 141 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_pread  =    {(char const   *)(& __tpstrtab_i915_gem_object_pread), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 166 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_fault[22U]  = 
 #line 166
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'f',      (char const   )'a',      (char const   )'u',      (char const   )'l', 
         (char const   )'t',      (char const   )'\000'};
 #line 166 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_fault  =    {(char const   *)(& __tpstrtab_i915_gem_object_fault), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 186 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_clflush[24U]  = 
 #line 186
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'c',      (char const   )'l',      (char const   )'f',      (char const   )'l', 
         (char const   )'u',      (char const   )'s',      (char const   )'h',      (char const   )'\000'};
 #line 186 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_clflush  =    {(char const   *)(& __tpstrtab_i915_gem_object_clflush), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 191 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_object_destroy[24U]  = 
 #line 191
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'o',      (char const   )'b',      (char const   )'j', 
         (char const   )'e',      (char const   )'c',      (char const   )'t',      (char const   )'_', 
         (char const   )'d',      (char const   )'e',      (char const   )'s',      (char const   )'t', 
         (char const   )'r',      (char const   )'o',      (char const   )'y',      (char const   )'\000'};
 #line 191 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_object_destroy  =    {(char const   *)(& __tpstrtab_i915_gem_object_destroy), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 214 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_evict[15U]  = 
 #line 214
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'e',      (char const   )'v',      (char const   )'i', 
         (char const   )'c',      (char const   )'t',      (char const   )'\000'};
 #line 214 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_evict  =    {(char const   *)(& __tpstrtab_i915_gem_evict), {{0}}, (void (*)(void))0, (void (*)(void))0,
     (struct tracepoint_func *)0};
 #line 233 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_evict_everything[26U]  = 
 #line 233
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'e',      (char const   )'v',      (char const   )'i', 
         (char const   )'c',      (char const   )'t',      (char const   )'_',      (char const   )'e', 
         (char const   )'v',      (char const   )'e',      (char const   )'r',      (char const   )'y', 
         (char const   )'t',      (char const   )'h',      (char const   )'i',      (char const   )'n', 
         (char const   )'g',      (char const   )'\000'};
 #line 233 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_evict_everything  =    {(char const   *)(& __tpstrtab_i915_gem_evict_everything), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 254 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_ring_dispatch[23U]  = 
 #line 254
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'i',      (char const   )'n', 
         (char const   )'g',      (char const   )'_',      (char const   )'d',      (char const   )'i', 
         (char const   )'s',      (char const   )'p',      (char const   )'a',      (char const   )'t', 
         (char const   )'c',      (char const   )'h',      (char const   )'\000'};
 #line 254 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_ring_dispatch  =    {(char const   *)(& __tpstrtab_i915_gem_ring_dispatch), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 277 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_ring_flush[20U]  = 
 #line 277
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'i',      (char const   )'n', 
         (char const   )'g',      (char const   )'_',      (char const   )'f',      (char const   )'l', 
         (char const   )'u',      (char const   )'s',      (char const   )'h',      (char const   )'\000'};
 #line 277 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_ring_flush  =    {(char const   *)(& __tpstrtab_i915_gem_ring_flush), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 302 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_request_add[21U]  = 
 #line 302
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'q', 
         (char const   )'u',      (char const   )'e',      (char const   )'s',      (char const   )'t', 
         (char const   )'_',      (char const   )'a',      (char const   )'d',      (char const   )'d', 
         (char const   )'\000'};
 #line 302 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_request_add  =    {(char const   *)(& __tpstrtab_i915_gem_request_add), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 307 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_request_complete[26U]  = 
 #line 307
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'q', 
         (char const   )'u',      (char const   )'e',      (char const   )'s',      (char const   )'t', 
         (char const   )'_',      (char const   )'c',      (char const   )'o',      (char const   )'m', 
         (char const   )'p',      (char const   )'l',      (char const   )'e',      (char const   )'t', 
         (char const   )'e',      (char const   )'\000'};
 #line 307 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_request_complete  =    {(char const   *)(& __tpstrtab_i915_gem_request_complete), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 312 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_request_retire[24U]  = 
 #line 312
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'q', 
         (char const   )'u',      (char const   )'e',      (char const   )'s',      (char const   )'t', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'t', 
         (char const   )'i',      (char const   )'r',      (char const   )'e',      (char const   )'\000'};
 #line 312 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_request_retire  =    {(char const   *)(& __tpstrtab_i915_gem_request_retire), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 317 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_request_wait_begin[28U]  = 
 #line 317
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'q', 
         (char const   )'u',      (char const   )'e',      (char const   )'s',      (char const   )'t', 
         (char const   )'_',      (char const   )'w',      (char const   )'a',      (char const   )'i', 
         (char const   )'t',      (char const   )'_',      (char const   )'b',      (char const   )'e', 
         (char const   )'g',      (char const   )'i',      (char const   )'n',      (char const   )'\000'};
 #line 317 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_request_wait_begin  =    {(char const   *)(& __tpstrtab_i915_gem_request_wait_begin), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 322 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_gem_request_wait_end[26U]  = 
 #line 322
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'g',      (char const   )'e',      (char const   )'m', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'q', 
         (char const   )'u',      (char const   )'e',      (char const   )'s',      (char const   )'t', 
         (char const   )'_',      (char const   )'w',      (char const   )'a',      (char const   )'i', 
         (char const   )'t',      (char const   )'_',      (char const   )'e',      (char const   )'n', 
         (char const   )'d',      (char const   )'\000'};
 #line 322 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_gem_request_wait_end  =    {(char const   *)(& __tpstrtab_i915_gem_request_wait_end), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 344 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_ring_wait_begin[21U]  = 
 #line 344
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'r',      (char const   )'i',      (char const   )'n', 
         (char const   )'g',      (char const   )'_',      (char const   )'w',      (char const   )'a', 
         (char const   )'i',      (char const   )'t',      (char const   )'_',      (char const   )'b', 
         (char const   )'e',      (char const   )'g',      (char const   )'i',      (char const   )'n', 
         (char const   )'\000'};
 #line 344 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_ring_wait_begin  =    {(char const   *)(& __tpstrtab_i915_ring_wait_begin), {{0}}, (void (*)(void))0,
     (void (*)(void))0, (struct tracepoint_func *)0};
 #line 349 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_ring_wait_end[19U]  = 
 #line 349
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'r',      (char const   )'i',      (char const   )'n', 
         (char const   )'g',      (char const   )'_',      (char const   )'w',      (char const   )'a', 
         (char const   )'i',      (char const   )'t',      (char const   )'_',      (char const   )'e', 
         (char const   )'n',      (char const   )'d',      (char const   )'\000'};
 #line 349 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_ring_wait_end  =    {(char const   *)(& __tpstrtab_i915_ring_wait_end), {{0}}, (void (*)(void))0, (void (*)(void))0,
     (struct tracepoint_func *)0};
 #line 367 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_flip_request[18U]  = 
 #line 367
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'f',      (char const   )'l',      (char const   )'i', 
         (char const   )'p',      (char const   )'_',      (char const   )'r',      (char const   )'e', 
         (char const   )'q',      (char const   )'u',      (char const   )'e',      (char const   )'s', 
         (char const   )'t',      (char const   )'\000'};
 #line 367 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_flip_request  =    {(char const   *)(& __tpstrtab_i915_flip_request), {{0}}, (void (*)(void))0, (void (*)(void))0,
     (struct tracepoint_func *)0};
 #line 385 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_flip_complete[19U]  = 
 #line 385
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'f',      (char const   )'l',      (char const   )'i', 
         (char const   )'p',      (char const   )'_',      (char const   )'c',      (char const   )'o', 
         (char const   )'m',      (char const   )'p',      (char const   )'l',      (char const   )'e', 
         (char const   )'t',      (char const   )'e',      (char const   )'\000'};
 #line 385 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_flip_complete  =    {(char const   *)(& __tpstrtab_i915_flip_complete), {{0}}, (void (*)(void))0, (void (*)(void))0,
     (struct tracepoint_func *)0};
 #line 411 "drivers/gpu/drm/i915/./i915_trace.h"
 static char const   __tpstrtab_i915_reg_rw[12U]  = 
 #line 411
   {      (char const   )'i',      (char const   )'9',      (char const   )'1',      (char const   )'5', 
         (char const   )'_',      (char const   )'r',      (char const   )'e',      (char const   )'g', 
         (char const   )'_',      (char const   )'r',      (char const   )'w',      (char const   )'\000'};
 #line 411 "drivers/gpu/drm/i915/./i915_trace.h"
 struct tracepoint __tracepoint_i915_reg_rw  =    {(char const   *)(& __tpstrtab_i915_reg_rw), {{0}}, (void (*)(void))0, (void (*)(void))0,
     (struct tracepoint_func *)0};
 #line 52 "include/linux/log2.h"
 __inline static bool is_power_of_2(unsigned long n ) 
 { int tmp ;
   unsigned long __cil_tmp3 ;
   unsigned long __cil_tmp4 ;
 
   {
 #line 54
   if (n != 0UL) {
     {
 #line 54
     __cil_tmp3 = n - 1UL;
 #line 54
     __cil_tmp4 = __cil_tmp3 & n;
 #line 54
     if (__cil_tmp4 == 0UL) {
 #line 54
       tmp = 1;
     } else {
 #line 54
       tmp = 0;
     }
     }
   } else {
 #line 54
     tmp = 0;
   }
 #line 54
   return ((bool )tmp);
 }
 }
 #line 22 "include/linux/err.h"
 __inline static void *ERR_PTR(long error ) 
 { 
 
   {
 #line 24
   return ((void *)error);
 }
 }
 #line 47 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
 __inline static void atomic_add(int i , atomic_t *v ) 
 { 
 
   {
 #line 49
   __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; addl %1,%0": "+m" (v->counter): "ir" (i));
 #line 51
   return;
 }
 }
 #line 61 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/atomic.h"
 __inline static void atomic_sub(int i , atomic_t *v ) 
 { 
 
   {
 #line 63
   __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; subl %1,%0": "+m" (v->counter): "ir" (i));
 #line 65
   return;
 }
 }
 #line 224 "include/linux/time.h"
 __inline static s64 timeval_to_ns(struct timeval  const  *tv ) 
 { __kernel_suseconds_t __cil_tmp2 ;
   long __cil_tmp3 ;
   long __cil_tmp4 ;
   long long __cil_tmp5 ;
   __kernel_time_t __cil_tmp6 ;
   long long __cil_tmp7 ;
   long long __cil_tmp8 ;
 
   {
   {
 #line 226
   __cil_tmp2 = tv->tv_usec;
 #line 226
   __cil_tmp3 = (long )__cil_tmp2;
 #line 226
   __cil_tmp4 = __cil_tmp3 * 1000L;
 #line 226
   __cil_tmp5 = (long long )__cil_tmp4;
 #line 226
   __cil_tmp6 = tv->tv_sec;
 #line 226
   __cil_tmp7 = (long long )__cil_tmp6;
 #line 226
   __cil_tmp8 = __cil_tmp7 * 1000000000LL;
 #line 226
   return (__cil_tmp8 + __cil_tmp5);
   }
 }
 }
 #line 244
 extern struct timeval ns_to_timeval(s64  ) ;
 #line 360 "include/linux/workqueue.h"
 extern int schedule_work(struct work_struct * ) ;
 #line 310 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static void outb(unsigned char value , int port ) 
 { 
 
   {
 #line 310
   __asm__  volatile   ("outb %b0, %w1": : "a" (value), "Nd" (port));
 #line 311
   return;
 }
 }
 #line 310 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
 __inline static unsigned char inb(int port ) 
 { unsigned char value ;
 
   {
 #line 310
   __asm__  volatile   ("inb %w1, %b0": "=a" (value): "Nd" (port));
 #line 310
   return (value);
 }
 }
 #line 97 "include/linux/vgaarb.h"
 extern int vga_get(struct pci_dev * , unsigned int  , int  ) ;
 #line 120 "include/linux/vgaarb.h"
 __inline static int vga_get_uninterruptible(struct pci_dev *pdev , unsigned int rsrc ) 
 { int tmp ;
 
   {
   {
 #line 123
   tmp = vga_get(pdev, rsrc, 0);
   }
 #line 123
   return (tmp);
 }
 }
 #line 157
 extern void vga_put(struct pci_dev * , unsigned int  ) ;
 #line 731 "include/linux/pci.h"
 extern int pci_bus_write_config_word(struct pci_bus * , unsigned int  , int  , u16  ) ;
 #line 754 "include/linux/pci.h"
 __inline static int pci_write_config_word(struct pci_dev *dev , int where , u16 val ) 
 { int tmp ;
   struct pci_bus *__cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   int __cil_tmp7 ;
   u16 __cil_tmp8 ;
 
   {
   {
 #line 756
   __cil_tmp5 = dev->bus;
 #line 756
   __cil_tmp6 = dev->devfn;
 #line 756
   __cil_tmp7 = (int )val;
 #line 756
   __cil_tmp8 = (u16 )__cil_tmp7;
 #line 756
   tmp = pci_bus_write_config_word(__cil_tmp5, __cil_tmp6, where, __cil_tmp8);
   }
 #line 756
   return (tmp);
 }
 }
 #line 635 "include/drm/drm_crtc.h"
 extern void drm_crtc_init(struct drm_device * , struct drm_crtc * , struct drm_crtc_funcs  const  * ) ;
 #line 638
 extern void drm_crtc_cleanup(struct drm_crtc * ) ;
 #line 652
 extern void drm_encoder_cleanup(struct drm_encoder * ) ;
 #line 654
 extern char *drm_get_connector_name(struct drm_connector * ) ;
 #line 669
 extern void drm_mode_debug_printmodeline(struct drm_display_mode * ) ;
 #line 670
 extern void drm_mode_config_init(struct drm_device * ) ;
 #line 672
 extern void drm_mode_config_cleanup(struct drm_device * ) ;
 #line 673
 extern void drm_mode_set_name(struct drm_display_mode * ) ;
 #line 696
 extern void drm_mode_set_crtcinfo(struct drm_display_mode * , int  ) ;
 #line 710
 extern int drm_framebuffer_init(struct drm_device * , struct drm_framebuffer * , struct drm_framebuffer_funcs  const  * ) ;
 #line 713
 extern void drm_framebuffer_cleanup(struct drm_framebuffer * ) ;
 #line 732
 extern char *drm_get_encoder_name(struct drm_encoder * ) ;
 #line 734
 extern int drm_mode_connector_attach_encoder(struct drm_connector * , struct drm_encoder * ) ;
 #line 738
 extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc * , int  ) ;
 #line 740
 extern struct drm_mode_object *drm_mode_object_find(struct drm_device * , uint32_t  ,
                                                     uint32_t  ) ;
 #line 1392 "include/drm/drmP.h"
 extern u32 drm_vblank_count_and_time(struct drm_device * , int  , struct timeval * ) ;
 #line 1395
 extern int drm_vblank_get(struct drm_device * , int  ) ;
 #line 1396
 extern void drm_vblank_put(struct drm_device * , int  ) ;
 #line 1397
 extern void drm_vblank_off(struct drm_device * , int  ) ;
 #line 1418
 extern void drm_vblank_pre_modeset(struct drm_device * , int  ) ;
 #line 1419
 extern void drm_vblank_post_modeset(struct drm_device * , int  ) ;
 #line 367 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_flip_request(int plane , struct drm_i915_gem_object *obj ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , int  , struct drm_i915_gem_object * ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 351
   __cil_tmp11 = & __tracepoint_i915_flip_request.key;
 #line 351
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 351
   if ((int )tmp___1) {
     {
 #line 351
     rcu_read_lock_sched_notrace();
 #line 351
     __cil_tmp12 = & __tracepoint_i915_flip_request.funcs;
 #line 351
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 351
     __cil_tmp14 = *__cil_tmp13;
 #line 351
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 351
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 351
     if (tmp != 0) {
 #line 351
       if (! __warned) {
         {
 #line 351
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 351
         if (tmp___0 == 0) {
           {
 #line 351
           __warned = (bool )1;
 #line 351
           __cil_tmp15 = (int const   )367;
 #line 351
           __cil_tmp16 = (int )__cil_tmp15;
 #line 351
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 351
     it_func_ptr = _________p1;
     {
 #line 351
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 351
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 351
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 351
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36608: 
       {
 #line 351
       it_func = it_func_ptr->func;
 #line 351
       __data = it_func_ptr->data;
 #line 351
       __cil_tmp20 = (void (*)(void * , int  , struct drm_i915_gem_object * ))it_func;
 #line 351
       (*__cil_tmp20)(__data, plane, obj);
 #line 351
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 351
       __cil_tmp21 = (void *)0;
 #line 351
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 351
       __cil_tmp23 = it_func_ptr->func;
 #line 351
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 351
       if (__cil_tmp24 != __cil_tmp22) {
 #line 352
         goto ldv_36608;
       } else {
 #line 354
         goto ldv_36609;
       }
       }
       ldv_36609: ;
     } else {
 
     }
     }
     {
 #line 351
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 353
   return;
 }
 }
 #line 385 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_flip_complete(int plane , struct drm_i915_gem_object *obj ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp11 ;
   struct tracepoint_func **__cil_tmp12 ;
   struct tracepoint_func * volatile  *__cil_tmp13 ;
   struct tracepoint_func * volatile  __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   struct tracepoint_func *__cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(void * , int  , struct drm_i915_gem_object * ) ;
   void *__cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   void *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
 
   {
   {
 #line 369
   __cil_tmp11 = & __tracepoint_i915_flip_complete.key;
 #line 369
   tmp___1 = static_branch(__cil_tmp11);
   }
 #line 369
   if ((int )tmp___1) {
     {
 #line 369
     rcu_read_lock_sched_notrace();
 #line 369
     __cil_tmp12 = & __tracepoint_i915_flip_complete.funcs;
 #line 369
     __cil_tmp13 = (struct tracepoint_func * volatile  *)__cil_tmp12;
 #line 369
     __cil_tmp14 = *__cil_tmp13;
 #line 369
     _________p1 = (struct tracepoint_func *)__cil_tmp14;
 #line 369
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 369
     if (tmp != 0) {
 #line 369
       if (! __warned) {
         {
 #line 369
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 369
         if (tmp___0 == 0) {
           {
 #line 369
           __warned = (bool )1;
 #line 369
           __cil_tmp15 = (int const   )385;
 #line 369
           __cil_tmp16 = (int )__cil_tmp15;
 #line 369
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp16);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 369
     it_func_ptr = _________p1;
     {
 #line 369
     __cil_tmp17 = (struct tracepoint_func *)0;
 #line 369
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 369
     __cil_tmp19 = (unsigned long )it_func_ptr;
 #line 369
     if (__cil_tmp19 != __cil_tmp18) {
       ldv_36644: 
       {
 #line 369
       it_func = it_func_ptr->func;
 #line 369
       __data = it_func_ptr->data;
 #line 369
       __cil_tmp20 = (void (*)(void * , int  , struct drm_i915_gem_object * ))it_func;
 #line 369
       (*__cil_tmp20)(__data, plane, obj);
 #line 369
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 369
       __cil_tmp21 = (void *)0;
 #line 369
       __cil_tmp22 = (unsigned long )__cil_tmp21;
 #line 369
       __cil_tmp23 = it_func_ptr->func;
 #line 369
       __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 369
       if (__cil_tmp24 != __cil_tmp22) {
 #line 370
         goto ldv_36644;
       } else {
 #line 372
         goto ldv_36645;
       }
       }
       ldv_36645: ;
     } else {
 
     }
     }
     {
 #line 369
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 371
   return;
 }
 }
 #line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
 __inline static void trace_i915_reg_rw___6(bool write , u32 reg , u64 val , int len ) 
 { struct tracepoint_func *it_func_ptr ;
   void *it_func ;
   void *__data ;
   struct tracepoint_func *_________p1 ;
   bool __warned ;
   int tmp ;
   int tmp___0 ;
   bool tmp___1 ;
   struct jump_label_key *__cil_tmp13 ;
   struct tracepoint_func **__cil_tmp14 ;
   struct tracepoint_func * volatile  *__cil_tmp15 ;
   struct tracepoint_func * volatile  __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct tracepoint_func *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   void *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   void *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
 
   {
   {
 #line 387
   __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
 #line 387
   tmp___1 = static_branch(__cil_tmp13);
   }
 #line 387
   if ((int )tmp___1) {
     {
 #line 387
     rcu_read_lock_sched_notrace();
 #line 387
     __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
 #line 387
     __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
 #line 387
     __cil_tmp16 = *__cil_tmp15;
 #line 387
     _________p1 = (struct tracepoint_func *)__cil_tmp16;
 #line 387
     tmp = debug_lockdep_rcu_enabled();
     }
 #line 387
     if (tmp != 0) {
 #line 387
       if (! __warned) {
         {
 #line 387
         tmp___0 = rcu_read_lock_sched_held();
         }
 #line 387
         if (tmp___0 == 0) {
           {
 #line 387
           __warned = (bool )1;
 #line 387
           __cil_tmp17 = (int const   )411;
 #line 387
           __cil_tmp18 = (int )__cil_tmp17;
 #line 387
           lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                   __cil_tmp18);
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
 #line 387
     it_func_ptr = _________p1;
     {
 #line 387
     __cil_tmp19 = (struct tracepoint_func *)0;
 #line 387
     __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 387
     __cil_tmp21 = (unsigned long )it_func_ptr;
 #line 387
     if (__cil_tmp21 != __cil_tmp20) {
       ldv_36684: 
       {
 #line 387
       it_func = it_func_ptr->func;
 #line 387
       __data = it_func_ptr->data;
 #line 387
       __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
 #line 387
       __cil_tmp23 = (int )write;
 #line 387
       __cil_tmp24 = (bool )__cil_tmp23;
 #line 387
       (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
 #line 387
       it_func_ptr = it_func_ptr + 1;
       }
       {
 #line 387
       __cil_tmp25 = (void *)0;
 #line 387
       __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 387
       __cil_tmp27 = it_func_ptr->func;
 #line 387
       __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 387
       if (__cil_tmp28 != __cil_tmp26) {
 #line 388
         goto ldv_36684;
       } else {
 #line 390
         goto ldv_36685;
       }
       }
       ldv_36685: ;
     } else {
 
     }
     }
     {
 #line 387
     rcu_read_lock_sched_notrace();
     }
   } else {
 
   }
 #line 389
   return;
 }
 }
 #line 1275 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 void intel_unregister_dsm_handler(void) ;
 #line 1290
 void intel_enable_fbc(struct drm_crtc *crtc , unsigned long interval ) ;
 #line 1296
 int intel_trans_dp_port_sel(struct drm_crtc *crtc ) ;
 #line 1360 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u16 i915_read16___2(struct drm_i915_private *dev_priv , u32 reg ) 
 { u16 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1360
   val = (u16 )0U;
   {
 #line 1360
   __cil_tmp4 = dev_priv->info;
 #line 1360
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1360
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1360
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1360
   if (__cil_tmp7 > 5U) {
 #line 1360
     if (reg <= 262143U) {
 #line 1360
       if (reg != 41356U) {
         {
 #line 1360
         gen6_gt_force_wake_get(dev_priv);
 #line 1360
         __cil_tmp8 = (unsigned long )reg;
 #line 1360
         __cil_tmp9 = dev_priv->regs;
 #line 1360
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1360
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1360
         val = readw(__cil_tmp11);
 #line 1360
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1360
         __cil_tmp12 = (unsigned long )reg;
 #line 1360
         __cil_tmp13 = dev_priv->regs;
 #line 1360
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1360
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1360
         val = readw(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1360
       __cil_tmp16 = (unsigned long )reg;
 #line 1360
       __cil_tmp17 = dev_priv->regs;
 #line 1360
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1360
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1360
       val = readw(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1360
     __cil_tmp20 = (unsigned long )reg;
 #line 1360
     __cil_tmp21 = dev_priv->regs;
 #line 1360
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1360
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1360
     val = readw(__cil_tmp23);
     }
   }
   }
   {
 #line 1360
   __cil_tmp24 = (bool )0;
 #line 1360
   __cil_tmp25 = (u64 )val;
 #line 1360
   trace_i915_reg_rw___6(__cil_tmp24, reg, __cil_tmp25, 2);
   }
 #line 1360
   return (val);
 }
 }
 #line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static u32 i915_read32___6(struct drm_i915_private *dev_priv , u32 reg ) 
 { u32 val ;
   struct intel_device_info  const  *__cil_tmp4 ;
   u8 __cil_tmp5 ;
   unsigned char __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   void const volatile   *__cil_tmp10 ;
   void const volatile   *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void const volatile   *__cil_tmp14 ;
   void const volatile   *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   void *__cil_tmp21 ;
   void const volatile   *__cil_tmp22 ;
   void const volatile   *__cil_tmp23 ;
   bool __cil_tmp24 ;
   u64 __cil_tmp25 ;
 
   {
 #line 1361
   val = 0U;
   {
 #line 1361
   __cil_tmp4 = dev_priv->info;
 #line 1361
   __cil_tmp5 = __cil_tmp4->gen;
 #line 1361
   __cil_tmp6 = (unsigned char )__cil_tmp5;
 #line 1361
   __cil_tmp7 = (unsigned int )__cil_tmp6;
 #line 1361
   if (__cil_tmp7 > 5U) {
 #line 1361
     if (reg <= 262143U) {
 #line 1361
       if (reg != 41356U) {
         {
 #line 1361
         gen6_gt_force_wake_get(dev_priv);
 #line 1361
         __cil_tmp8 = (unsigned long )reg;
 #line 1361
         __cil_tmp9 = dev_priv->regs;
 #line 1361
         __cil_tmp10 = (void const volatile   *)__cil_tmp9;
 #line 1361
         __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
 #line 1361
         val = readl(__cil_tmp11);
 #line 1361
         gen6_gt_force_wake_put(dev_priv);
         }
       } else {
         {
 #line 1361
         __cil_tmp12 = (unsigned long )reg;
 #line 1361
         __cil_tmp13 = dev_priv->regs;
 #line 1361
         __cil_tmp14 = (void const volatile   *)__cil_tmp13;
 #line 1361
         __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1361
         val = readl(__cil_tmp15);
         }
       }
     } else {
       {
 #line 1361
       __cil_tmp16 = (unsigned long )reg;
 #line 1361
       __cil_tmp17 = dev_priv->regs;
 #line 1361
       __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1361
       __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1361
       val = readl(__cil_tmp19);
       }
     }
   } else {
     {
 #line 1361
     __cil_tmp20 = (unsigned long )reg;
 #line 1361
     __cil_tmp21 = dev_priv->regs;
 #line 1361
     __cil_tmp22 = (void const volatile   *)__cil_tmp21;
 #line 1361
     __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
 #line 1361
     val = readl(__cil_tmp23);
     }
   }
   }
   {
 #line 1361
   __cil_tmp24 = (bool )0;
 #line 1361
   __cil_tmp25 = (u64 )val;
 #line 1361
   trace_i915_reg_rw___6(__cil_tmp24, reg, __cil_tmp25, 4);
   }
 #line 1361
   return (val);
 }
 }
 #line 1374 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static void i915_write16___0(struct drm_i915_private *dev_priv , u32 reg ,
                                       u16 val ) 
 { bool __cil_tmp4 ;
   u64 __cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   unsigned short __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   void *__cil_tmp13 ;
   void volatile   *__cil_tmp14 ;
   void volatile   *__cil_tmp15 ;
 
   {
   {
 #line 1374
   __cil_tmp4 = (bool )1;
 #line 1374
   __cil_tmp5 = (u64 )val;
 #line 1374
   trace_i915_reg_rw___6(__cil_tmp4, reg, __cil_tmp5, 2);
   }
   {
 #line 1374
   __cil_tmp6 = dev_priv->info;
 #line 1374
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1374
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1374
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1374
   if (__cil_tmp9 > 5U) {
 #line 1374
     if (reg <= 262143U) {
 #line 1374
       if (reg != 41356U) {
         {
 #line 1374
         __gen6_gt_wait_for_fifo(dev_priv);
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1374
   __cil_tmp10 = (int )val;
 #line 1374
   __cil_tmp11 = (unsigned short )__cil_tmp10;
 #line 1374
   __cil_tmp12 = (unsigned long )reg;
 #line 1374
   __cil_tmp13 = dev_priv->regs;
 #line 1374
   __cil_tmp14 = (void volatile   *)__cil_tmp13;
 #line 1374
   __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
 #line 1374
   writew(__cil_tmp11, __cil_tmp15);
   }
 #line 1375
   return;
 }
 }
 #line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
 __inline static void i915_write32___4(struct drm_i915_private *dev_priv , u32 reg ,
                                       u32 val ) 
 { bool __cil_tmp4 ;
   u64 __cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   void *__cil_tmp11 ;
   void volatile   *__cil_tmp12 ;
   void volatile   *__cil_tmp13 ;
 
   {
   {
 #line 1375
   __cil_tmp4 = (bool )1;
 #line 1375
   __cil_tmp5 = (u64 )val;
 #line 1375
   trace_i915_reg_rw___6(__cil_tmp4, reg, __cil_tmp5, 4);
   }
   {
 #line 1375
   __cil_tmp6 = dev_priv->info;
 #line 1375
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1375
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1375
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1375
   if (__cil_tmp9 > 5U) {
 #line 1375
     if (reg <= 262143U) {
 #line 1375
       if (reg != 41356U) {
         {
 #line 1375
         __gen6_gt_wait_for_fifo(dev_priv);
         }
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 1375
   __cil_tmp10 = (unsigned long )reg;
 #line 1375
   __cil_tmp11 = dev_priv->regs;
 #line 1375
   __cil_tmp12 = (void volatile   *)__cil_tmp11;
 #line 1375
   __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
 #line 1375
   writel(val, __cil_tmp13);
   }
 #line 1376
   return;
 }
 }
 #line 108 "include/drm/drm_crtc_helper.h"
 extern void drm_helper_disable_unused_functions(struct drm_device * ) ;
 #line 109
 extern int drm_crtc_helper_set_config(struct drm_mode_set * ) ;
 #line 110
 extern bool drm_crtc_helper_set_mode(struct drm_crtc * , struct drm_display_mode * ,
                                      int  , int  , struct drm_framebuffer * ) ;
 #line 119
 extern int drm_helper_mode_fill_fb_struct(struct drm_framebuffer * , struct drm_mode_fb_cmd * ) ;
 #line 122 "include/drm/drm_crtc_helper.h"
 __inline static void drm_crtc_helper_add(struct drm_crtc *crtc , struct drm_crtc_helper_funcs  const  *funcs ) 
 { 
 
   {
 #line 125
   crtc->helper_private = (void *)funcs;
 #line 126
   return;
 }
 }
 #line 142
 extern void drm_kms_helper_poll_fini(struct drm_device * ) ;
 #line 123 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 __inline static int intel_mode_get_pixel_multiplier(struct drm_display_mode  const  *mode ) 
 { int __cil_tmp2 ;
   int __cil_tmp3 ;
 
   {
   {
 #line 125
   __cil_tmp2 = mode->private_flags;
 #line 125
   __cil_tmp3 = (int )__cil_tmp2;
 #line 125
   return (__cil_tmp3 & 15);
   }
 }
 }
 #line 220 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 __inline static struct drm_crtc *intel_get_crtc_for_plane(struct drm_device *dev ,
                                                           int plane ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp4 ;
 
   {
 #line 222
   __cil_tmp4 = dev->dev_private;
 #line 222
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 223
   return (dev_priv->plane_to_crtc_mapping[plane]);
 }
 }
 #line 242
 void intel_crt_init(struct drm_device *dev ) ;
 #line 243
 void intel_hdmi_init(struct drm_device *dev , int sdvox_reg ) ;
 #line 245
 bool intel_sdvo_init(struct drm_device *dev , int sdvo_reg ) ;
 #line 246
 void intel_dvo_init(struct drm_device *dev ) ;
 #line 247
 void intel_tv_init(struct drm_device *dev ) ;
 #line 250
 bool intel_lvds_init(struct drm_device *dev ) ;
 #line 251
 void intel_dp_init(struct drm_device *dev , int output_reg ) ;
 #line 253
 void intel_dp_set_m_n(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) ;
 #line 255
 bool intel_dpd_is_edp(struct drm_device *dev ) ;
 #line 256
 void intel_edp_link_config(struct intel_encoder *intel_encoder , int *lane_num , int *link_bw ) ;
 #line 257
 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder ) ;
 #line 269
 void intel_panel_setup_backlight(struct drm_device *dev ) ;
 #line 274
 void intel_crtc_load_lut(struct drm_crtc *crtc ) ;
 #line 275
 void intel_encoder_prepare(struct drm_encoder *encoder ) ;
 #line 276
 void intel_encoder_commit(struct drm_encoder *encoder ) ;
 #line 277
 void intel_encoder_destroy(struct drm_encoder *encoder ) ;
 #line 279 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
 __inline static struct intel_encoder *intel_attached_encoder(struct drm_connector *connector ) 
 { struct drm_connector  const  *__mptr ;
   struct intel_connector *__cil_tmp3 ;
 
   {
 #line 281
   __mptr = (struct drm_connector  const  *)connector;
   {
 #line 281
   __cil_tmp3 = (struct intel_connector *)__mptr;
 #line 281
   return (__cil_tmp3->encoder);
   }
 }
 }
 #line 284
 void intel_connector_attach_encoder(struct intel_connector *connector , struct intel_encoder *encoder ) ;
 #line 286
 struct drm_encoder *intel_best_encoder(struct drm_connector *connector ) ;
 #line 288
 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev , struct drm_crtc *crtc ) ;
 #line 292
 void intel_wait_for_vblank(struct drm_device *dev , int pipe ) ;
 #line 293
 void intel_wait_for_pipe_off(struct drm_device *dev , int pipe ) ;
 #line 300
 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder , struct drm_connector *connector ,
                                 struct drm_display_mode *mode , struct intel_load_detect_pipe *old ) ;
 #line 304
 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder , struct drm_connector *connector ,
                                     struct intel_load_detect_pipe *old ) ;
 #line 312
 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc , u16 red , u16 green , u16 blue ,
                              int regno ) ;
 #line 314
 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc , u16 *red , u16 *green , u16 *blue ,
                              int regno ) ;
 #line 323
 int intel_pin_and_fence_fb_obj(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                struct intel_ring_buffer *pipelined ) ;
 #line 327
 int intel_framebuffer_init(struct drm_device *dev , struct intel_framebuffer *intel_fb ,
                            struct drm_mode_fb_cmd *mode_cmd , struct drm_i915_gem_object *obj ) ;
 #line 338
 void intel_setup_overlay(struct drm_device *dev ) ;
 #line 340
 int intel_overlay_switch_off(struct intel_overlay *overlay ) ;
 #line 346
 void intel_fb_output_poll_changed(struct drm_device *dev ) ;
 #line 52 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 bool intel_pipe_has_type(struct drm_crtc *crtc , int type ) ;
 #line 53
 static void intel_update_watermarks(struct drm_device *dev ) ;
 #line 54
 static void intel_increase_pllclock(struct drm_crtc *crtc ) ;
 #line 55
 static void intel_crtc_update_cursor(struct drm_crtc *crtc , bool on ) ;
 #line 91
 static bool intel_find_best_PLL(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                 int target , int refclk , intel_clock_t *best_clock ) ;
 #line 94
 static bool intel_g4x_find_best_PLL(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                     int target , int refclk , intel_clock_t *best_clock ) ;
 #line 98
 static bool intel_find_pll_g4x_dp(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                   int target , int refclk , intel_clock_t *best_clock ) ;
 #line 101
 static bool intel_find_pll_ironlake_dp(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                        int target , int refclk , intel_clock_t *best_clock ) ;
 #line 105 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 __inline static u32 intel_fdi_link_freq(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   void *__cil_tmp4 ;
   struct drm_i915_private *__cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   void *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
 
   {
   {
 #line 107
   __cil_tmp4 = dev->dev_private;
 #line 107
   __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
 #line 107
   __cil_tmp6 = __cil_tmp5->info;
 #line 107
   __cil_tmp7 = __cil_tmp6->gen;
 #line 107
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 107
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 107
   if (__cil_tmp9 == 5U) {
     {
 #line 108
     __cil_tmp10 = dev->dev_private;
 #line 108
     dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 109
     tmp = i915_read32___6(dev_priv, 286720U);
     }
     {
 #line 109
     __cil_tmp11 = tmp & 255U;
 #line 109
     return (__cil_tmp11 + 2U);
     }
   } else {
 #line 111
     return (27U);
   }
   }
 }
 }
 #line 114 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_i8xx_dvo  = 
 #line 114
      {{25000, 350000}, {930000, 1400000}, {3, 16}, {96, 140}, {18, 26}, {6, 16}, {4,
                                                                                 128},
     {2, 33}, {165000, 4, 2}, & intel_find_best_PLL};
 #line 128 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_i8xx_lvds  = 
 #line 128
      {{25000, 350000}, {930000, 1400000}, {3, 16}, {96, 140}, {18, 26}, {6, 16}, {4,
                                                                                 128},
     {1, 6}, {165000, 14, 7}, & intel_find_best_PLL};
 #line 142 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_i9xx_sdvo  = 
 #line 142
      {{20000, 400000}, {1400000, 2800000}, {1, 6}, {70, 120}, {10, 22}, {5, 9}, {5,
                                                                                80},
     {1, 8}, {200000, 10, 5}, & intel_find_best_PLL};
 #line 156 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_i9xx_lvds  = 
 #line 156
      {{20000, 400000}, {1400000, 2800000}, {1, 6}, {70, 120}, {10, 22}, {5, 9}, {7,
                                                                                98},
     {1, 8}, {112000, 14, 7}, & intel_find_best_PLL};
 #line 171 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_g4x_sdvo  = 
 #line 171
      {{25000, 270000}, {1750000, 3500000}, {1, 4}, {104, 138}, {17, 23}, {5, 11}, {10,
                                                                                  30},
     {1, 3}, {270000, 10, 10}, & intel_g4x_find_best_PLL};
 #line 187 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_g4x_hdmi  = 
 #line 187
      {{22000, 400000}, {1750000, 3500000}, {1, 4}, {104, 138}, {16, 23}, {5, 11}, {5,
                                                                                  80},
     {1, 8}, {165000, 10, 5}, & intel_g4x_find_best_PLL};
 #line 201 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_g4x_single_channel_lvds  = 
 #line 201
      {{20000, 115000}, {1750000, 3500000}, {1, 3}, {104, 138}, {17, 23}, {5, 11}, {28,
                                                                                  112},
     {2, 8}, {0, 14, 14}, & intel_g4x_find_best_PLL};
 #line 216 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_g4x_dual_channel_lvds  = 
 #line 216
      {{80000, 224000}, {1750000, 3500000}, {1, 3}, {104, 138}, {17, 23}, {5, 11}, {14,
                                                                                  42},
     {2, 6}, {0, 7, 7}, & intel_g4x_find_best_PLL};
 #line 231 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_g4x_display_port  = 
 #line 231
      {{161670, 227000}, {1750000, 3500000}, {1, 2}, {97, 108}, {16, 18}, {5, 6}, {10,
                                                                                 20},
     {1, 2}, {0, 10, 10}, & intel_find_pll_g4x_dp};
 #line 245 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_pineview_sdvo  = 
 #line 245
      {{20000, 400000}, {1700000, 3500000}, {3, 6}, {2, 256}, {0, 0}, {0, 254}, {5, 80},
     {1, 8}, {200000, 10, 5}, & intel_find_best_PLL};
 #line 261 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_pineview_lvds  = 
 #line 261
      {{20000, 400000}, {1700000, 3500000}, {3, 6}, {2, 256}, {0, 0}, {0, 254}, {7, 112},
     {1, 8}, {112000, 14, 14}, & intel_find_best_PLL};
 #line 280 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_ironlake_dac  = 
 #line 280
      {{25000, 350000}, {1760000, 3510000}, {1, 5}, {79, 127}, {12, 22}, {5, 9}, {5,
                                                                                80},
     {1, 8}, {225000, 10, 5}, & intel_g4x_find_best_PLL};
 #line 294 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_ironlake_single_lvds  = 
 #line 294
      {{25000, 350000}, {1760000, 3510000}, {1, 3}, {79, 118}, {12, 22}, {5, 9}, {28,
                                                                                112},
     {2, 8}, {225000, 14, 14}, & intel_g4x_find_best_PLL};
 #line 308 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_ironlake_dual_lvds  = 
 #line 308
      {{25000, 350000}, {1760000, 3510000}, {1, 3}, {79, 127}, {12, 22}, {5, 9}, {14,
                                                                                56},
     {2, 8}, {225000, 7, 7}, & intel_g4x_find_best_PLL};
 #line 323 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_ironlake_single_lvds_100m  = 
 #line 323
      {{25000, 350000}, {1760000, 3510000}, {1, 2}, {79, 126}, {12, 22}, {5, 9}, {28,
                                                                                112},
     {2, 8}, {225000, 14, 14}, & intel_g4x_find_best_PLL};
 #line 337 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_ironlake_dual_lvds_100m  = 
 #line 337
      {{25000, 350000}, {1760000, 3510000}, {1, 3}, {79, 126}, {12, 22}, {5, 9}, {14,
                                                                                42},
     {2, 6}, {225000, 7, 7}, & intel_g4x_find_best_PLL};
 #line 351 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_limit  const  intel_limits_ironlake_display_port  = 
 #line 351
      {{25000, 350000}, {1760000, 3510000}, {1, 2}, {81, 90}, {12, 22}, {5, 9}, {10,
                                                                               20},
     {1, 2}, {0, 10, 10}, & intel_find_pll_ironlake_dp};
 #line 365 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static intel_limit_t const   *intel_ironlake_limit(struct drm_crtc *crtc , int refclk ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   intel_limit_t const   *limit ;
   u32 tmp ;
   bool tmp___0 ;
   bool tmp___1 ;
   bool tmp___2 ;
   void *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
 
   {
   {
 #line 368
   dev = crtc->dev;
 #line 369
   __cil_tmp10 = dev->dev_private;
 #line 369
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 372
   tmp___2 = intel_pipe_has_type(crtc, 4);
   }
 #line 372
   if ((int )tmp___2) {
     {
 #line 373
     tmp = i915_read32___6(dev_priv, 921984U);
     }
     {
 #line 373
     __cil_tmp11 = tmp & 48U;
 #line 373
     if (__cil_tmp11 == 48U) {
 #line 376
       if (refclk == 100000) {
 #line 377
         limit = & intel_limits_ironlake_dual_lvds_100m;
       } else {
 #line 379
         limit = & intel_limits_ironlake_dual_lvds;
       }
     } else
 #line 381
     if (refclk == 100000) {
 #line 382
       limit = & intel_limits_ironlake_single_lvds_100m;
     } else {
 #line 384
       limit = & intel_limits_ironlake_single_lvds;
     }
     }
   } else {
     {
 #line 386
     tmp___0 = intel_pipe_has_type(crtc, 7);
     }
 #line 386
     if ((int )tmp___0) {
 #line 388
       limit = & intel_limits_ironlake_display_port;
     } else {
       {
 #line 386
       tmp___1 = intel_pipe_has_type(crtc, 8);
       }
 #line 386
       if ((int )tmp___1) {
 #line 388
         limit = & intel_limits_ironlake_display_port;
       } else {
 #line 390
         limit = & intel_limits_ironlake_dac;
       }
     }
   }
 #line 392
   return (limit);
 }
 }
 #line 395 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static intel_limit_t const   *intel_g4x_limit(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   intel_limit_t const   *limit ;
   u32 tmp ;
   bool tmp___0 ;
   bool tmp___1 ;
   bool tmp___2 ;
   bool tmp___3 ;
   bool tmp___4 ;
   void *__cil_tmp11 ;
   unsigned int __cil_tmp12 ;
 
   {
   {
 #line 397
   dev = crtc->dev;
 #line 398
   __cil_tmp11 = dev->dev_private;
 #line 398
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 401
   tmp___4 = intel_pipe_has_type(crtc, 4);
   }
 #line 401
   if ((int )tmp___4) {
     {
 #line 402
     tmp = i915_read32___6(dev_priv, 397696U);
     }
     {
 #line 402
     __cil_tmp12 = tmp & 48U;
 #line 402
     if (__cil_tmp12 == 48U) {
 #line 405
       limit = & intel_limits_g4x_dual_channel_lvds;
     } else {
 #line 408
       limit = & intel_limits_g4x_single_channel_lvds;
     }
     }
   } else {
     {
 #line 409
     tmp___2 = intel_pipe_has_type(crtc, 6);
     }
 #line 409
     if ((int )tmp___2) {
 #line 411
       limit = & intel_limits_g4x_hdmi;
     } else {
       {
 #line 409
       tmp___3 = intel_pipe_has_type(crtc, 1);
       }
 #line 409
       if ((int )tmp___3) {
 #line 411
         limit = & intel_limits_g4x_hdmi;
       } else {
         {
 #line 412
         tmp___1 = intel_pipe_has_type(crtc, 3);
         }
 #line 412
         if ((int )tmp___1) {
 #line 413
           limit = & intel_limits_g4x_sdvo;
         } else {
           {
 #line 414
           tmp___0 = intel_pipe_has_type(crtc, 7);
           }
 #line 414
           if ((int )tmp___0) {
 #line 415
             limit = & intel_limits_g4x_display_port;
           } else {
 #line 417
             limit = & intel_limits_i9xx_sdvo;
           }
         }
       }
     }
   }
 #line 419
   return (limit);
 }
 }
 #line 422 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static intel_limit_t const   *intel_limit(struct drm_crtc *crtc , int refclk ) 
 { struct drm_device *dev ;
   intel_limit_t const   *limit ;
   bool tmp ;
   bool tmp___0 ;
   bool tmp___1 ;
   void *__cil_tmp8 ;
   struct drm_i915_private *__cil_tmp9 ;
   struct intel_device_info  const  *__cil_tmp10 ;
   u8 __cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   u8 __cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   void *__cil_tmp20 ;
   struct drm_i915_private *__cil_tmp21 ;
   struct intel_device_info  const  *__cil_tmp22 ;
   unsigned char *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   void *__cil_tmp27 ;
   struct drm_i915_private *__cil_tmp28 ;
   struct intel_device_info  const  *__cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   void *__cil_tmp34 ;
   struct drm_i915_private *__cil_tmp35 ;
   struct intel_device_info  const  *__cil_tmp36 ;
   unsigned char *__cil_tmp37 ;
   unsigned char *__cil_tmp38 ;
   unsigned char __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   void *__cil_tmp41 ;
   struct drm_i915_private *__cil_tmp42 ;
   struct intel_device_info  const  *__cil_tmp43 ;
   u8 __cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
 
   {
 #line 424
   dev = crtc->dev;
   {
 #line 427
   __cil_tmp8 = dev->dev_private;
 #line 427
   __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
 #line 427
   __cil_tmp10 = __cil_tmp9->info;
 #line 427
   __cil_tmp11 = __cil_tmp10->gen;
 #line 427
   __cil_tmp12 = (unsigned char )__cil_tmp11;
 #line 427
   __cil_tmp13 = (unsigned int )__cil_tmp12;
 #line 427
   if (__cil_tmp13 == 5U) {
     {
 #line 428
     limit = intel_ironlake_limit(crtc, refclk);
     }
   } else {
     {
 #line 427
     __cil_tmp14 = dev->dev_private;
 #line 427
     __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 427
     __cil_tmp16 = __cil_tmp15->info;
 #line 427
     __cil_tmp17 = __cil_tmp16->gen;
 #line 427
     __cil_tmp18 = (unsigned char )__cil_tmp17;
 #line 427
     __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 427
     if (__cil_tmp19 == 6U) {
       {
 #line 428
       limit = intel_ironlake_limit(crtc, refclk);
       }
     } else {
       {
 #line 427
       __cil_tmp20 = dev->dev_private;
 #line 427
       __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
 #line 427
       __cil_tmp22 = __cil_tmp21->info;
 #line 427
       __cil_tmp23 = (unsigned char *)__cil_tmp22;
 #line 427
       __cil_tmp24 = __cil_tmp23 + 2UL;
 #line 427
       __cil_tmp25 = *__cil_tmp24;
 #line 427
       __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 427
       if (__cil_tmp26 != 0U) {
         {
 #line 428
         limit = intel_ironlake_limit(crtc, refclk);
         }
       } else {
         {
 #line 429
         __cil_tmp27 = dev->dev_private;
 #line 429
         __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
 #line 429
         __cil_tmp29 = __cil_tmp28->info;
 #line 429
         __cil_tmp30 = (unsigned char *)__cil_tmp29;
 #line 429
         __cil_tmp31 = __cil_tmp30 + 1UL;
 #line 429
         __cil_tmp32 = *__cil_tmp31;
 #line 429
         __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 429
         if (__cil_tmp33 != 0U) {
           {
 #line 430
           limit = intel_g4x_limit(crtc);
           }
         } else {
           {
 #line 431
           __cil_tmp34 = dev->dev_private;
 #line 431
           __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
 #line 431
           __cil_tmp36 = __cil_tmp35->info;
 #line 431
           __cil_tmp37 = (unsigned char *)__cil_tmp36;
 #line 431
           __cil_tmp38 = __cil_tmp37 + 1UL;
 #line 431
           __cil_tmp39 = *__cil_tmp38;
 #line 431
           __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 431
           if (__cil_tmp40 != 0U) {
             {
 #line 432
             tmp = intel_pipe_has_type(crtc, 4);
             }
 #line 432
             if ((int )tmp) {
 #line 433
               limit = & intel_limits_pineview_lvds;
             } else {
 #line 435
               limit = & intel_limits_pineview_sdvo;
             }
           } else {
             {
 #line 436
             __cil_tmp41 = dev->dev_private;
 #line 436
             __cil_tmp42 = (struct drm_i915_private *)__cil_tmp41;
 #line 436
             __cil_tmp43 = __cil_tmp42->info;
 #line 436
             __cil_tmp44 = __cil_tmp43->gen;
 #line 436
             __cil_tmp45 = (unsigned char )__cil_tmp44;
 #line 436
             __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 436
             if (__cil_tmp46 != 2U) {
               {
 #line 437
               tmp___0 = intel_pipe_has_type(crtc, 4);
               }
 #line 437
               if ((int )tmp___0) {
 #line 438
                 limit = & intel_limits_i9xx_lvds;
               } else {
 #line 440
                 limit = & intel_limits_i9xx_sdvo;
               }
             } else {
               {
 #line 442
               tmp___1 = intel_pipe_has_type(crtc, 4);
               }
 #line 442
               if ((int )tmp___1) {
 #line 443
                 limit = & intel_limits_i8xx_lvds;
               } else {
 #line 445
                 limit = & intel_limits_i8xx_dvo;
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
 #line 447
   return (limit);
 }
 }
 #line 451 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void pineview_clock(int refclk , intel_clock_t *clock ) 
 { int __cil_tmp3 ;
   int __cil_tmp4 ;
   int __cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
 
   {
 #line 453
   __cil_tmp3 = clock->m2;
 #line 453
   clock->m = __cil_tmp3 + 2;
 #line 454
   __cil_tmp4 = clock->p2;
 #line 454
   __cil_tmp5 = clock->p1;
 #line 454
   clock->p = __cil_tmp5 * __cil_tmp4;
 #line 455
   __cil_tmp6 = clock->n;
 #line 455
   __cil_tmp7 = clock->m;
 #line 455
   __cil_tmp8 = __cil_tmp7 * refclk;
 #line 455
   clock->vco = __cil_tmp8 / __cil_tmp6;
 #line 456
   __cil_tmp9 = clock->p;
 #line 456
   __cil_tmp10 = clock->vco;
 #line 456
   clock->dot = __cil_tmp10 / __cil_tmp9;
 #line 457
   return;
 }
 }
 #line 459 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_clock(struct drm_device *dev , int refclk , intel_clock_t *clock ) 
 { void *__cil_tmp4 ;
   struct drm_i915_private *__cil_tmp5 ;
   struct intel_device_info  const  *__cil_tmp6 ;
   unsigned char *__cil_tmp7 ;
   unsigned char *__cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
 
   {
   {
 #line 461
   __cil_tmp4 = dev->dev_private;
 #line 461
   __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
 #line 461
   __cil_tmp6 = __cil_tmp5->info;
 #line 461
   __cil_tmp7 = (unsigned char *)__cil_tmp6;
 #line 461
   __cil_tmp8 = __cil_tmp7 + 1UL;
 #line 461
   __cil_tmp9 = *__cil_tmp8;
 #line 461
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 461
   if (__cil_tmp10 != 0U) {
     {
 #line 462
     pineview_clock(refclk, clock);
     }
 #line 463
     return;
   } else {
 
   }
   }
 #line 465
   __cil_tmp11 = clock->m2;
 #line 465
   __cil_tmp12 = __cil_tmp11 + 2;
 #line 465
   __cil_tmp13 = clock->m1;
 #line 465
   __cil_tmp14 = __cil_tmp13 * 5;
 #line 465
   __cil_tmp15 = __cil_tmp14 + 10;
 #line 465
   clock->m = __cil_tmp15 + __cil_tmp12;
 #line 466
   __cil_tmp16 = clock->p2;
 #line 466
   __cil_tmp17 = clock->p1;
 #line 466
   clock->p = __cil_tmp17 * __cil_tmp16;
 #line 467
   __cil_tmp18 = clock->n;
 #line 467
   __cil_tmp19 = __cil_tmp18 + 2;
 #line 467
   __cil_tmp20 = clock->m;
 #line 467
   __cil_tmp21 = __cil_tmp20 * refclk;
 #line 467
   clock->vco = __cil_tmp21 / __cil_tmp19;
 #line 468
   __cil_tmp22 = clock->p;
 #line 468
   __cil_tmp23 = clock->vco;
 #line 468
   clock->dot = __cil_tmp23 / __cil_tmp22;
 #line 469
   return;
 }
 }
 #line 474 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 bool intel_pipe_has_type(struct drm_crtc *crtc , int type ) 
 { struct drm_device *dev ;
   struct drm_mode_config *mode_config ;
   struct intel_encoder *encoder ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head *__cil_tmp8 ;
   struct intel_encoder *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct drm_crtc *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   int __cil_tmp13 ;
   struct list_head *__cil_tmp14 ;
   struct intel_encoder *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
 
   {
 #line 476
   dev = crtc->dev;
 #line 477
   mode_config = & dev->mode_config;
 #line 480
   __cil_tmp8 = mode_config->encoder_list.next;
 #line 480
   __mptr = (struct list_head  const  *)__cil_tmp8;
 #line 480
   __cil_tmp9 = (struct intel_encoder *)__mptr;
 #line 480
   encoder = __cil_tmp9 + 1152921504606846968UL;
 #line 480
   goto ldv_38120;
   ldv_38119: ;
   {
 #line 481
   __cil_tmp10 = (unsigned long )crtc;
 #line 481
   __cil_tmp11 = encoder->base.crtc;
 #line 481
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 481
   if (__cil_tmp12 == __cil_tmp10) {
     {
 #line 481
     __cil_tmp13 = encoder->type;
 #line 481
     if (__cil_tmp13 == type) {
 #line 482
       return ((bool )1);
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 480
   __cil_tmp14 = encoder->base.head.next;
 #line 480
   __mptr___0 = (struct list_head  const  *)__cil_tmp14;
 #line 480
   __cil_tmp15 = (struct intel_encoder *)__mptr___0;
 #line 480
   encoder = __cil_tmp15 + 1152921504606846968UL;
   ldv_38120: ;
   {
 #line 480
   __cil_tmp16 = & mode_config->encoder_list;
 #line 480
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 480
   __cil_tmp18 = & encoder->base.head;
 #line 480
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 480
   if (__cil_tmp19 != __cil_tmp17) {
 #line 481
     goto ldv_38119;
   } else {
 #line 483
     goto ldv_38121;
   }
   }
   ldv_38121: ;
 #line 484
   return ((bool )0);
 }
 }
 #line 493 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_PLL_is_valid(struct drm_device *dev , intel_limit_t const   *limit ,
                                intel_clock_t const   *clock ) 
 { int __cil_tmp4 ;
   int __cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   void *__cil_tmp40 ;
   struct drm_i915_private *__cil_tmp41 ;
   struct intel_device_info  const  *__cil_tmp42 ;
   unsigned char *__cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   int __cil_tmp51 ;
   int __cil_tmp52 ;
   int __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   int __cil_tmp61 ;
   int __cil_tmp62 ;
   int __cil_tmp63 ;
   int __cil_tmp64 ;
   int __cil_tmp65 ;
   int __cil_tmp66 ;
   int __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   int __cil_tmp70 ;
   int __cil_tmp71 ;
   int __cil_tmp72 ;
   int __cil_tmp73 ;
   int __cil_tmp74 ;
   int __cil_tmp75 ;
   int __cil_tmp76 ;
   int __cil_tmp77 ;
   int __cil_tmp78 ;
 
   {
   {
 #line 497
   __cil_tmp4 = limit->p1.min;
 #line 497
   __cil_tmp5 = (int )__cil_tmp4;
 #line 497
   __cil_tmp6 = clock->p1;
 #line 497
   __cil_tmp7 = (int )__cil_tmp6;
 #line 497
   if (__cil_tmp7 < __cil_tmp5) {
 #line 498
     return ((bool )0);
   } else {
     {
 #line 497
     __cil_tmp8 = clock->p1;
 #line 497
     __cil_tmp9 = (int )__cil_tmp8;
 #line 497
     __cil_tmp10 = limit->p1.max;
 #line 497
     __cil_tmp11 = (int )__cil_tmp10;
 #line 497
     if (__cil_tmp11 < __cil_tmp9) {
 #line 498
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 499
   __cil_tmp12 = limit->p.min;
 #line 499
   __cil_tmp13 = (int )__cil_tmp12;
 #line 499
   __cil_tmp14 = clock->p;
 #line 499
   __cil_tmp15 = (int )__cil_tmp14;
 #line 499
   if (__cil_tmp15 < __cil_tmp13) {
 #line 500
     return ((bool )0);
   } else {
     {
 #line 499
     __cil_tmp16 = clock->p;
 #line 499
     __cil_tmp17 = (int )__cil_tmp16;
 #line 499
     __cil_tmp18 = limit->p.max;
 #line 499
     __cil_tmp19 = (int )__cil_tmp18;
 #line 499
     if (__cil_tmp19 < __cil_tmp17) {
 #line 500
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 501
   __cil_tmp20 = limit->m2.min;
 #line 501
   __cil_tmp21 = (int )__cil_tmp20;
 #line 501
   __cil_tmp22 = clock->m2;
 #line 501
   __cil_tmp23 = (int )__cil_tmp22;
 #line 501
   if (__cil_tmp23 < __cil_tmp21) {
 #line 502
     return ((bool )0);
   } else {
     {
 #line 501
     __cil_tmp24 = clock->m2;
 #line 501
     __cil_tmp25 = (int )__cil_tmp24;
 #line 501
     __cil_tmp26 = limit->m2.max;
 #line 501
     __cil_tmp27 = (int )__cil_tmp26;
 #line 501
     if (__cil_tmp27 < __cil_tmp25) {
 #line 502
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 503
   __cil_tmp28 = limit->m1.min;
 #line 503
   __cil_tmp29 = (int )__cil_tmp28;
 #line 503
   __cil_tmp30 = clock->m1;
 #line 503
   __cil_tmp31 = (int )__cil_tmp30;
 #line 503
   if (__cil_tmp31 < __cil_tmp29) {
 #line 504
     return ((bool )0);
   } else {
     {
 #line 503
     __cil_tmp32 = clock->m1;
 #line 503
     __cil_tmp33 = (int )__cil_tmp32;
 #line 503
     __cil_tmp34 = limit->m1.max;
 #line 503
     __cil_tmp35 = (int )__cil_tmp34;
 #line 503
     if (__cil_tmp35 < __cil_tmp33) {
 #line 504
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 505
   __cil_tmp36 = clock->m2;
 #line 505
   __cil_tmp37 = (int )__cil_tmp36;
 #line 505
   __cil_tmp38 = clock->m1;
 #line 505
   __cil_tmp39 = (int )__cil_tmp38;
 #line 505
   if (__cil_tmp39 <= __cil_tmp37) {
     {
 #line 505
     __cil_tmp40 = dev->dev_private;
 #line 505
     __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
 #line 505
     __cil_tmp42 = __cil_tmp41->info;
 #line 505
     __cil_tmp43 = (unsigned char *)__cil_tmp42;
 #line 505
     __cil_tmp44 = __cil_tmp43 + 1UL;
 #line 505
     __cil_tmp45 = *__cil_tmp44;
 #line 505
     __cil_tmp46 = (unsigned int )__cil_tmp45;
 #line 505
     if (__cil_tmp46 == 0U) {
 #line 506
       return ((bool )0);
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 507
   __cil_tmp47 = limit->m.min;
 #line 507
   __cil_tmp48 = (int )__cil_tmp47;
 #line 507
   __cil_tmp49 = clock->m;
 #line 507
   __cil_tmp50 = (int )__cil_tmp49;
 #line 507
   if (__cil_tmp50 < __cil_tmp48) {
 #line 508
     return ((bool )0);
   } else {
     {
 #line 507
     __cil_tmp51 = clock->m;
 #line 507
     __cil_tmp52 = (int )__cil_tmp51;
 #line 507
     __cil_tmp53 = limit->m.max;
 #line 507
     __cil_tmp54 = (int )__cil_tmp53;
 #line 507
     if (__cil_tmp54 < __cil_tmp52) {
 #line 508
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 509
   __cil_tmp55 = limit->n.min;
 #line 509
   __cil_tmp56 = (int )__cil_tmp55;
 #line 509
   __cil_tmp57 = clock->n;
 #line 509
   __cil_tmp58 = (int )__cil_tmp57;
 #line 509
   if (__cil_tmp58 < __cil_tmp56) {
 #line 510
     return ((bool )0);
   } else {
     {
 #line 509
     __cil_tmp59 = clock->n;
 #line 509
     __cil_tmp60 = (int )__cil_tmp59;
 #line 509
     __cil_tmp61 = limit->n.max;
 #line 509
     __cil_tmp62 = (int )__cil_tmp61;
 #line 509
     if (__cil_tmp62 < __cil_tmp60) {
 #line 510
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 511
   __cil_tmp63 = limit->vco.min;
 #line 511
   __cil_tmp64 = (int )__cil_tmp63;
 #line 511
   __cil_tmp65 = clock->vco;
 #line 511
   __cil_tmp66 = (int )__cil_tmp65;
 #line 511
   if (__cil_tmp66 < __cil_tmp64) {
 #line 512
     return ((bool )0);
   } else {
     {
 #line 511
     __cil_tmp67 = clock->vco;
 #line 511
     __cil_tmp68 = (int )__cil_tmp67;
 #line 511
     __cil_tmp69 = limit->vco.max;
 #line 511
     __cil_tmp70 = (int )__cil_tmp69;
 #line 511
     if (__cil_tmp70 < __cil_tmp68) {
 #line 512
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
   {
 #line 516
   __cil_tmp71 = limit->dot.min;
 #line 516
   __cil_tmp72 = (int )__cil_tmp71;
 #line 516
   __cil_tmp73 = clock->dot;
 #line 516
   __cil_tmp74 = (int )__cil_tmp73;
 #line 516
   if (__cil_tmp74 < __cil_tmp72) {
 #line 517
     return ((bool )0);
   } else {
     {
 #line 516
     __cil_tmp75 = clock->dot;
 #line 516
     __cil_tmp76 = (int )__cil_tmp75;
 #line 516
     __cil_tmp77 = limit->dot.max;
 #line 516
     __cil_tmp78 = (int )__cil_tmp77;
 #line 516
     if (__cil_tmp78 < __cil_tmp76) {
 #line 517
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
 #line 519
   return ((bool )1);
 }
 }
 #line 523 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_find_best_PLL(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                 int target , int refclk , intel_clock_t *best_clock ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   intel_clock_t clock ;
   int err ;
   u32 tmp ;
   bool tmp___0 ;
   u32 tmp___1 ;
   int this_err ;
   bool tmp___2 ;
   int tmp___3 ;
   long ret ;
   int __x___0 ;
   int tmp___4 ;
   void *__cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   void *__cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   void *__cil_tmp30 ;
   struct drm_i915_private *__cil_tmp31 ;
   struct intel_device_info  const  *__cil_tmp32 ;
   unsigned char *__cil_tmp33 ;
   unsigned char *__cil_tmp34 ;
   unsigned char __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   intel_clock_t const   *__cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   int __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   int __cil_tmp45 ;
   int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
 
   {
   {
 #line 527
   dev = crtc->dev;
 #line 528
   __cil_tmp19 = dev->dev_private;
 #line 528
   dev_priv = (struct drm_i915_private *)__cil_tmp19;
 #line 530
   err = target;
 #line 532
   tmp___0 = intel_pipe_has_type(crtc, 4);
   }
 #line 532
   if ((int )tmp___0) {
     {
 #line 532
     tmp___1 = i915_read32___6(dev_priv, 397696U);
     }
 #line 532
     if (tmp___1 != 0U) {
       {
 #line 540
       tmp = i915_read32___6(dev_priv, 397696U);
       }
       {
 #line 540
       __cil_tmp20 = tmp & 48U;
 #line 540
       if (__cil_tmp20 == 48U) {
 #line 542
         __cil_tmp21 = limit->p2.p2_fast;
 #line 542
         clock.p2 = (int )__cil_tmp21;
       } else {
 #line 544
         __cil_tmp22 = limit->p2.p2_slow;
 #line 544
         clock.p2 = (int )__cil_tmp22;
       }
       }
     } else {
 #line 532
       goto _L;
     }
   } else {
     _L: 
     {
 #line 546
     __cil_tmp23 = limit->p2.dot_limit;
 #line 546
     __cil_tmp24 = (int )__cil_tmp23;
 #line 546
     if (__cil_tmp24 > target) {
 #line 547
       __cil_tmp25 = limit->p2.p2_slow;
 #line 547
       clock.p2 = (int )__cil_tmp25;
     } else {
 #line 549
       __cil_tmp26 = limit->p2.p2_fast;
 #line 549
       clock.p2 = (int )__cil_tmp26;
     }
     }
   }
   {
 #line 552
   __cil_tmp27 = (void *)best_clock;
 #line 552
   memset(__cil_tmp27, 0, 36UL);
 #line 554
   __cil_tmp28 = limit->m1.min;
 #line 554
   clock.m1 = (int )__cil_tmp28;
   }
 #line 554
   goto ldv_38154;
   ldv_38153: 
 #line 556
   __cil_tmp29 = limit->m2.min;
 #line 556
   clock.m2 = (int )__cil_tmp29;
 #line 556
   goto ldv_38152;
   ldv_38151: ;
 #line 559
   if (clock.m2 >= clock.m1) {
     {
 #line 559
     __cil_tmp30 = dev->dev_private;
 #line 559
     __cil_tmp31 = (struct drm_i915_private *)__cil_tmp30;
 #line 559
     __cil_tmp32 = __cil_tmp31->info;
 #line 559
     __cil_tmp33 = (unsigned char *)__cil_tmp32;
 #line 559
     __cil_tmp34 = __cil_tmp33 + 1UL;
 #line 559
     __cil_tmp35 = *__cil_tmp34;
 #line 559
     __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 559
     if (__cil_tmp36 == 0U) {
 #line 560
       goto ldv_38138;
     } else {
 
     }
     }
   } else {
 
   }
 #line 561
   __cil_tmp37 = limit->n.min;
 #line 561
   clock.n = (int )__cil_tmp37;
 #line 561
   goto ldv_38149;
   ldv_38148: 
 #line 563
   __cil_tmp38 = limit->p1.min;
 #line 563
   clock.p1 = (int )__cil_tmp38;
 #line 563
   goto ldv_38146;
   ldv_38145: 
   {
 #line 567
   intel_clock(dev, refclk, & clock);
 #line 568
   __cil_tmp39 = (intel_clock_t const   *)(& clock);
 #line 568
   tmp___2 = intel_PLL_is_valid(dev, limit, __cil_tmp39);
   }
 #line 568
   if (tmp___2) {
 #line 568
     tmp___3 = 0;
   } else {
 #line 568
     tmp___3 = 1;
   }
 #line 568
   if (tmp___3) {
 #line 570
     goto ldv_38140;
   } else {
 
   }
 #line 572
   __x___0 = clock.dot - target;
 #line 572
   if (__x___0 < 0) {
 #line 572
     tmp___4 = - __x___0;
   } else {
 #line 572
     tmp___4 = __x___0;
   }
 #line 572
   ret = (long )tmp___4;
 #line 572
   this_err = (int )ret;
 #line 573
   if (this_err < err) {
 #line 574
     *best_clock = clock;
 #line 575
     err = this_err;
   } else {
 
   }
   ldv_38140: 
 #line 564
   clock.p1 = clock.p1 + 1;
   ldv_38146: ;
   {
 #line 563
   __cil_tmp40 = limit->p1.max;
 #line 563
   __cil_tmp41 = (int )__cil_tmp40;
 #line 563
   if (clock.p1 <= __cil_tmp41) {
 #line 565
     goto ldv_38145;
   } else {
 #line 567
     goto ldv_38147;
   }
   }
   ldv_38147: 
 #line 562
   clock.n = clock.n + 1;
   ldv_38149: ;
   {
 #line 561
   __cil_tmp42 = limit->n.max;
 #line 561
   __cil_tmp43 = (int )__cil_tmp42;
 #line 561
   if (clock.n <= __cil_tmp43) {
 #line 563
     goto ldv_38148;
   } else {
 #line 565
     goto ldv_38150;
   }
   }
   ldv_38150: 
 #line 557
   clock.m2 = clock.m2 + 1;
   ldv_38152: ;
   {
 #line 556
   __cil_tmp44 = limit->m2.max;
 #line 556
   __cil_tmp45 = (int )__cil_tmp44;
 #line 556
   if (clock.m2 <= __cil_tmp45) {
 #line 558
     goto ldv_38151;
   } else {
 #line 560
     goto ldv_38138;
   }
   }
   ldv_38138: 
 #line 555
   clock.m1 = clock.m1 + 1;
   ldv_38154: ;
   {
 #line 554
   __cil_tmp46 = limit->m1.max;
 #line 554
   __cil_tmp47 = (int )__cil_tmp46;
 #line 554
   if (clock.m1 <= __cil_tmp47) {
 #line 555
     goto ldv_38153;
   } else {
 #line 557
     goto ldv_38155;
   }
   }
   ldv_38155: ;
   {
 #line 582
   __cil_tmp48 = err != target;
 #line 582
   return ((bool )__cil_tmp48);
   }
 }
 }
 #line 586 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_g4x_find_best_PLL(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                     int target , int refclk , intel_clock_t *best_clock ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   intel_clock_t clock ;
   int max_n ;
   bool found ;
   int err_most ;
   int lvds_reg ;
   u32 tmp ;
   bool tmp___0 ;
   int this_err ;
   bool tmp___1 ;
   int tmp___2 ;
   long ret ;
   int __x___0 ;
   int tmp___3 ;
   void *__cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   void *__cil_tmp24 ;
   struct drm_i915_private *__cil_tmp25 ;
   struct intel_device_info  const  *__cil_tmp26 ;
   u8 __cil_tmp27 ;
   unsigned char __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   void *__cil_tmp30 ;
   struct drm_i915_private *__cil_tmp31 ;
   struct intel_device_info  const  *__cil_tmp32 ;
   u8 __cil_tmp33 ;
   unsigned char __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   void *__cil_tmp36 ;
   struct drm_i915_private *__cil_tmp37 ;
   struct intel_device_info  const  *__cil_tmp38 ;
   unsigned char *__cil_tmp39 ;
   unsigned char *__cil_tmp40 ;
   unsigned char __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   u32 __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   int __cil_tmp45 ;
   int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   void *__cil_tmp51 ;
   int __cil_tmp52 ;
   int __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   intel_clock_t const   *__cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   int __cil_tmp61 ;
   int __cil_tmp62 ;
   int __cil_tmp63 ;
 
   {
   {
 #line 589
   dev = crtc->dev;
 #line 590
   __cil_tmp21 = dev->dev_private;
 #line 590
   dev_priv = (struct drm_i915_private *)__cil_tmp21;
 #line 595
   __cil_tmp22 = target >> 9;
 #line 595
   __cil_tmp23 = target >> 8;
 #line 595
   err_most = __cil_tmp23 + __cil_tmp22;
 #line 596
   found = (bool )0;
 #line 598
   tmp___0 = intel_pipe_has_type(crtc, 4);
   }
 #line 598
   if ((int )tmp___0) {
     {
 #line 601
     __cil_tmp24 = dev->dev_private;
 #line 601
     __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
 #line 601
     __cil_tmp26 = __cil_tmp25->info;
 #line 601
     __cil_tmp27 = __cil_tmp26->gen;
 #line 601
     __cil_tmp28 = (unsigned char )__cil_tmp27;
 #line 601
     __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 601
     if (__cil_tmp29 == 5U) {
 #line 602
       lvds_reg = 921984;
     } else {
       {
 #line 601
       __cil_tmp30 = dev->dev_private;
 #line 601
       __cil_tmp31 = (struct drm_i915_private *)__cil_tmp30;
 #line 601
       __cil_tmp32 = __cil_tmp31->info;
 #line 601
       __cil_tmp33 = __cil_tmp32->gen;
 #line 601
       __cil_tmp34 = (unsigned char )__cil_tmp33;
 #line 601
       __cil_tmp35 = (unsigned int )__cil_tmp34;
 #line 601
       if (__cil_tmp35 == 6U) {
 #line 602
         lvds_reg = 921984;
       } else {
         {
 #line 601
         __cil_tmp36 = dev->dev_private;
 #line 601
         __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
 #line 601
         __cil_tmp38 = __cil_tmp37->info;
 #line 601
         __cil_tmp39 = (unsigned char *)__cil_tmp38;
 #line 601
         __cil_tmp40 = __cil_tmp39 + 2UL;
 #line 601
         __cil_tmp41 = *__cil_tmp40;
 #line 601
         __cil_tmp42 = (unsigned int )__cil_tmp41;
 #line 601
         if (__cil_tmp42 != 0U) {
 #line 602
           lvds_reg = 921984;
         } else {
 #line 604
           lvds_reg = 397696;
         }
         }
       }
       }
     }
     }
     {
 #line 605
     __cil_tmp43 = (u32 )lvds_reg;
 #line 605
     tmp = i915_read32___6(dev_priv, __cil_tmp43);
     }
     {
 #line 605
     __cil_tmp44 = tmp & 48U;
 #line 605
     if (__cil_tmp44 == 48U) {
 #line 607
       __cil_tmp45 = limit->p2.p2_fast;
 #line 607
       clock.p2 = (int )__cil_tmp45;
     } else {
 #line 609
       __cil_tmp46 = limit->p2.p2_slow;
 #line 609
       clock.p2 = (int )__cil_tmp46;
     }
     }
   } else {
     {
 #line 611
     __cil_tmp47 = limit->p2.dot_limit;
 #line 611
     __cil_tmp48 = (int )__cil_tmp47;
 #line 611
     if (__cil_tmp48 > target) {
 #line 612
       __cil_tmp49 = limit->p2.p2_slow;
 #line 612
       clock.p2 = (int )__cil_tmp49;
     } else {
 #line 614
       __cil_tmp50 = limit->p2.p2_fast;
 #line 614
       clock.p2 = (int )__cil_tmp50;
     }
     }
   }
   {
 #line 617
   __cil_tmp51 = (void *)best_clock;
 #line 617
   memset(__cil_tmp51, 0, 36UL);
 #line 618
   __cil_tmp52 = limit->n.max;
 #line 618
   max_n = (int )__cil_tmp52;
 #line 620
   __cil_tmp53 = limit->n.min;
 #line 620
   clock.n = (int )__cil_tmp53;
   }
 #line 620
   goto ldv_38186;
   ldv_38185: 
 #line 622
   __cil_tmp54 = limit->m1.max;
 #line 622
   clock.m1 = (int )__cil_tmp54;
 #line 622
   goto ldv_38183;
   ldv_38182: 
 #line 624
   __cil_tmp55 = limit->m2.max;
 #line 624
   clock.m2 = (int )__cil_tmp55;
 #line 624
   goto ldv_38180;
   ldv_38179: 
 #line 626
   __cil_tmp56 = limit->p1.max;
 #line 626
   clock.p1 = (int )__cil_tmp56;
 #line 626
   goto ldv_38177;
   ldv_38176: 
   {
 #line 630
   intel_clock(dev, refclk, & clock);
 #line 631
   __cil_tmp57 = (intel_clock_t const   *)(& clock);
 #line 631
   tmp___1 = intel_PLL_is_valid(dev, limit, __cil_tmp57);
   }
 #line 631
   if (tmp___1) {
 #line 631
     tmp___2 = 0;
   } else {
 #line 631
     tmp___2 = 1;
   }
 #line 631
   if (tmp___2) {
 #line 633
     goto ldv_38171;
   } else {
 
   }
 #line 635
   __x___0 = clock.dot - target;
 #line 635
   if (__x___0 < 0) {
 #line 635
     tmp___3 = - __x___0;
   } else {
 #line 635
     tmp___3 = __x___0;
   }
 #line 635
   ret = (long )tmp___3;
 #line 635
   this_err = (int )ret;
 #line 636
   if (this_err < err_most) {
 #line 637
     *best_clock = clock;
 #line 638
     err_most = this_err;
 #line 639
     max_n = clock.n;
 #line 640
     found = (bool )1;
   } else {
 
   }
   ldv_38171: 
 #line 627
   clock.p1 = clock.p1 - 1;
   ldv_38177: ;
   {
 #line 626
   __cil_tmp58 = limit->p1.min;
 #line 626
   __cil_tmp59 = (int )__cil_tmp58;
 #line 626
   if (clock.p1 >= __cil_tmp59) {
 #line 628
     goto ldv_38176;
   } else {
 #line 630
     goto ldv_38178;
   }
   }
   ldv_38178: 
 #line 625
   clock.m2 = clock.m2 - 1;
   ldv_38180: ;
   {
 #line 624
   __cil_tmp60 = limit->m2.min;
 #line 624
   __cil_tmp61 = (int )__cil_tmp60;
 #line 624
   if (clock.m2 >= __cil_tmp61) {
 #line 626
     goto ldv_38179;
   } else {
 #line 628
     goto ldv_38181;
   }
   }
   ldv_38181: 
 #line 623
   clock.m1 = clock.m1 - 1;
   ldv_38183: ;
   {
 #line 622
   __cil_tmp62 = limit->m1.min;
 #line 622
   __cil_tmp63 = (int )__cil_tmp62;
 #line 622
   if (clock.m1 >= __cil_tmp63) {
 #line 624
     goto ldv_38182;
   } else {
 #line 626
     goto ldv_38184;
   }
   }
   ldv_38184: 
 #line 620
   clock.n = clock.n + 1;
   ldv_38186: ;
 #line 620
   if (clock.n <= max_n) {
 #line 621
     goto ldv_38185;
   } else {
 #line 623
     goto ldv_38187;
   }
   ldv_38187: ;
 #line 646
   return (found);
 }
 }
 #line 650 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_find_pll_ironlake_dp(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                        int target , int refclk , intel_clock_t *best_clock ) 
 { struct drm_device *dev ;
   intel_clock_t clock ;
   size_t __len ;
   void *__ret ;
   void *__cil_tmp10 ;
   void const   *__cil_tmp11 ;
   void *__cil_tmp12 ;
   void const   *__cil_tmp13 ;
 
   {
 #line 653
   dev = crtc->dev;
 #line 656
   if (target <= 199999) {
 #line 657
     clock.n = 1;
 #line 658
     clock.p1 = 2;
 #line 659
     clock.p2 = 10;
 #line 660
     clock.m1 = 12;
 #line 661
     clock.m2 = 9;
   } else {
 #line 663
     clock.n = 2;
 #line 664
     clock.p1 = 1;
 #line 665
     clock.p2 = 10;
 #line 666
     clock.m1 = 14;
 #line 667
     clock.m2 = 8;
   }
   {
 #line 669
   intel_clock(dev, refclk, & clock);
 #line 670
   __len = 36UL;
   }
 #line 670
   if (__len > 63UL) {
     {
 #line 670
     __cil_tmp10 = (void *)best_clock;
 #line 670
     __cil_tmp11 = (void const   *)(& clock);
 #line 670
     __ret = __memcpy(__cil_tmp10, __cil_tmp11, __len);
     }
   } else {
     {
 #line 670
     __cil_tmp12 = (void *)best_clock;
 #line 670
     __cil_tmp13 = (void const   *)(& clock);
 #line 670
     __ret = __builtin_memcpy(__cil_tmp12, __cil_tmp13, __len);
     }
   }
 #line 671
   return ((bool )1);
 }
 }
 #line 676 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_find_pll_g4x_dp(intel_limit_t const   *limit , struct drm_crtc *crtc ,
                                   int target , int refclk , intel_clock_t *best_clock ) 
 { intel_clock_t clock ;
   size_t __len ;
   void *__ret ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   void *__cil_tmp15 ;
   void const   *__cil_tmp16 ;
   void *__cil_tmp17 ;
   void const   *__cil_tmp18 ;
 
   {
 #line 680
   if (target <= 199999) {
 #line 681
     clock.p1 = 2;
 #line 682
     clock.p2 = 10;
 #line 683
     clock.n = 2;
 #line 684
     clock.m1 = 23;
 #line 685
     clock.m2 = 8;
   } else {
 #line 687
     clock.p1 = 1;
 #line 688
     clock.p2 = 10;
 #line 689
     clock.n = 1;
 #line 690
     clock.m1 = 14;
 #line 691
     clock.m2 = 2;
   }
 #line 693
   __cil_tmp9 = clock.m2 + 2;
 #line 693
   __cil_tmp10 = clock.m1 * 5;
 #line 693
   __cil_tmp11 = __cil_tmp10 + 10;
 #line 693
   clock.m = __cil_tmp11 + __cil_tmp9;
 #line 694
   clock.p = clock.p1 * clock.p2;
 #line 695
   __cil_tmp12 = clock.n + 2;
 #line 695
   __cil_tmp13 = clock.m * 96000;
 #line 695
   __cil_tmp14 = __cil_tmp13 / __cil_tmp12;
 #line 695
   clock.dot = __cil_tmp14 / clock.p;
 #line 696
   clock.vco = 0;
 #line 697
   __len = 36UL;
 #line 697
   if (__len > 63UL) {
     {
 #line 697
     __cil_tmp15 = (void *)best_clock;
 #line 697
     __cil_tmp16 = (void const   *)(& clock);
 #line 697
     __ret = __memcpy(__cil_tmp15, __cil_tmp16, __len);
     }
   } else {
     {
 #line 697
     __cil_tmp17 = (void *)best_clock;
 #line 697
     __cil_tmp18 = (void const   *)(& clock);
 #line 697
     __ret = __builtin_memcpy(__cil_tmp17, __cil_tmp18, __len);
     }
   }
 #line 698
   return ((bool )1);
 }
 }
 #line 709 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_wait_for_vblank(struct drm_device *dev , int pipe ) 
 { struct drm_i915_private *dev_priv ;
   int pipestat_reg ;
   u32 tmp ;
   unsigned long timeout__ ;
   unsigned long tmp___0 ;
   int ret__ ;
   struct thread_info *tmp___1 ;
   int pfo_ret__ ;
   int tmp___2 ;
   u32 tmp___3 ;
   void *__cil_tmp13 ;
   int __cil_tmp14 ;
   u32 __cil_tmp15 ;
   u32 __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   long __cil_tmp21 ;
   long __cil_tmp22 ;
   long __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   atomic_t const   *__cil_tmp26 ;
   u32 __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
 
   {
   {
 #line 711
   __cil_tmp13 = dev->dev_private;
 #line 711
   dev_priv = (struct drm_i915_private *)__cil_tmp13;
 #line 712
   __cil_tmp14 = pipe * 4096;
 #line 712
   pipestat_reg = __cil_tmp14 + 458788;
 #line 727
   __cil_tmp15 = (u32 )pipestat_reg;
 #line 727
   tmp = i915_read32___6(dev_priv, __cil_tmp15);
 #line 727
   __cil_tmp16 = (u32 )pipestat_reg;
 #line 727
   __cil_tmp17 = tmp | 2U;
 #line 727
   i915_write32___4(dev_priv, __cil_tmp16, __cil_tmp17);
 #line 731
   __cil_tmp18 = (unsigned int const   )50U;
 #line 731
   __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 731
   tmp___0 = msecs_to_jiffies(__cil_tmp19);
 #line 731
   __cil_tmp20 = (unsigned long )jiffies;
 #line 731
   timeout__ = tmp___0 + __cil_tmp20;
 #line 731
   ret__ = 0;
   }
 #line 731
   goto ldv_38235;
   ldv_38234: ;
   {
 #line 731
   __cil_tmp21 = (long )jiffies;
 #line 731
   __cil_tmp22 = (long )timeout__;
 #line 731
   __cil_tmp23 = __cil_tmp22 - __cil_tmp21;
 #line 731
   if (__cil_tmp23 < 0L) {
 #line 731
     ret__ = -110;
 #line 731
     goto ldv_38225;
   } else {
 
   }
   }
   {
 #line 731
   tmp___1 = current_thread_info();
   }
   {
 #line 731
   __cil_tmp24 = tmp___1->preempt_count;
 #line 731
   __cil_tmp25 = __cil_tmp24 & -268435457;
 #line 731
   if (__cil_tmp25 == 0) {
 #line 731
     if (1) {
 #line 731
       goto case_4;
     } else {
 #line 731
       goto switch_default;
 #line 731
       if (0) {
 #line 731
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 731
         goto ldv_38228;
 #line 731
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 731
         goto ldv_38228;
         case_4: 
 #line 731
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 731
         goto ldv_38228;
 #line 731
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 731
         goto ldv_38228;
         switch_default: 
         {
 #line 731
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_38228: 
     {
 #line 731
     __cil_tmp26 = (atomic_t const   *)(& kgdb_active);
 #line 731
     tmp___2 = atomic_read(__cil_tmp26);
     }
 #line 731
     if (pfo_ret__ != tmp___2) {
       {
 #line 731
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38235: 
   {
 #line 731
   __cil_tmp27 = (u32 )pipestat_reg;
 #line 731
   tmp___3 = i915_read32___6(dev_priv, __cil_tmp27);
   }
   {
 #line 731
   __cil_tmp28 = (unsigned long )tmp___3;
 #line 731
   __cil_tmp29 = __cil_tmp28 & 2UL;
 #line 731
   if (__cil_tmp29 == 0UL) {
 #line 732
     goto ldv_38234;
   } else {
 #line 734
     goto ldv_38225;
   }
   }
   ldv_38225: ;
 #line 731
   if (ret__ != 0) {
     {
 #line 734
     drm_ut_debug_printk(4U, "drm", "intel_wait_for_vblank", "vblank wait timed out\n");
     }
   } else {
 
   }
 #line 735
   return;
 }
 }
 #line 754 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_wait_for_pipe_off(struct drm_device *dev , int pipe ) 
 { struct drm_i915_private *dev_priv ;
   int reg ;
   unsigned long timeout__ ;
   unsigned long tmp ;
   int ret__ ;
   struct thread_info *tmp___0 ;
   int pfo_ret__ ;
   int tmp___1 ;
   u32 tmp___2 ;
   u32 last_line ;
   int reg___0 ;
   unsigned long timeout ;
   unsigned long tmp___3 ;
   u32 tmp___4 ;
   unsigned long __ms ;
   unsigned long tmp___5 ;
   u32 tmp___6 ;
   void *__cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   u8 __cil_tmp24 ;
   unsigned char __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   long __cil_tmp31 ;
   long __cil_tmp32 ;
   long __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   atomic_t const   *__cil_tmp36 ;
   u32 __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   int __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   u32 __cil_tmp43 ;
   u32 __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   long __cil_tmp46 ;
   long __cil_tmp47 ;
   long __cil_tmp48 ;
   long __cil_tmp49 ;
   long __cil_tmp50 ;
   long __cil_tmp51 ;
 
   {
 #line 756
   __cil_tmp20 = dev->dev_private;
 #line 756
   dev_priv = (struct drm_i915_private *)__cil_tmp20;
   {
 #line 758
   __cil_tmp21 = dev->dev_private;
 #line 758
   __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 758
   __cil_tmp23 = __cil_tmp22->info;
 #line 758
   __cil_tmp24 = __cil_tmp23->gen;
 #line 758
   __cil_tmp25 = (unsigned char )__cil_tmp24;
 #line 758
   __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 758
   if (__cil_tmp26 > 3U) {
     {
 #line 759
     __cil_tmp27 = pipe * 4096;
 #line 759
     reg = __cil_tmp27 + 458760;
 #line 762
     __cil_tmp28 = (unsigned int const   )100U;
 #line 762
     __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 762
     tmp = msecs_to_jiffies(__cil_tmp29);
 #line 762
     __cil_tmp30 = (unsigned long )jiffies;
 #line 762
     timeout__ = tmp + __cil_tmp30;
 #line 762
     ret__ = 0;
     }
 #line 762
     goto ldv_38262;
     ldv_38261: ;
     {
 #line 762
     __cil_tmp31 = (long )jiffies;
 #line 762
     __cil_tmp32 = (long )timeout__;
 #line 762
     __cil_tmp33 = __cil_tmp32 - __cil_tmp31;
 #line 762
     if (__cil_tmp33 < 0L) {
 #line 762
       ret__ = -110;
 #line 762
       goto ldv_38252;
     } else {
 
     }
     }
     {
 #line 762
     tmp___0 = current_thread_info();
     }
     {
 #line 762
     __cil_tmp34 = tmp___0->preempt_count;
 #line 762
     __cil_tmp35 = __cil_tmp34 & -268435457;
 #line 762
     if (__cil_tmp35 == 0) {
 #line 762
       if (1) {
 #line 762
         goto case_4;
       } else {
 #line 762
         goto switch_default;
 #line 762
         if (0) {
 #line 762
           __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 762
           goto ldv_38255;
 #line 762
           __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 762
           goto ldv_38255;
           case_4: 
 #line 762
           __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 762
           goto ldv_38255;
 #line 762
           __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 762
           goto ldv_38255;
           switch_default: 
           {
 #line 762
           __bad_percpu_size();
           }
         } else {
 
         }
       }
       ldv_38255: 
       {
 #line 762
       __cil_tmp36 = (atomic_t const   *)(& kgdb_active);
 #line 762
       tmp___1 = atomic_read(__cil_tmp36);
       }
 #line 762
       if (pfo_ret__ != tmp___1) {
         {
 #line 762
         msleep(1U);
         }
       } else {
 
       }
     } else {
 
     }
     }
     ldv_38262: 
     {
 #line 762
     __cil_tmp37 = (u32 )reg;
 #line 762
     tmp___2 = i915_read32___6(dev_priv, __cil_tmp37);
     }
     {
 #line 762
     __cil_tmp38 = tmp___2 & 1073741824U;
 #line 762
     if (__cil_tmp38 != 0U) {
 #line 763
       goto ldv_38261;
     } else {
 #line 765
       goto ldv_38252;
     }
     }
     ldv_38252: ;
 #line 762
     if (ret__ != 0) {
       {
 #line 764
       drm_ut_debug_printk(4U, "drm", "intel_wait_for_pipe_off", "pipe_off wait timed out\n");
       }
     } else {
 
     }
   } else {
     {
 #line 767
     __cil_tmp39 = pipe + 112;
 #line 767
     reg___0 = __cil_tmp39 * 4096;
 #line 768
     __cil_tmp40 = (unsigned int const   )100U;
 #line 768
     __cil_tmp41 = (unsigned int )__cil_tmp40;
 #line 768
     tmp___3 = msecs_to_jiffies(__cil_tmp41);
 #line 768
     __cil_tmp42 = (unsigned long )jiffies;
 #line 768
     timeout = tmp___3 + __cil_tmp42;
     }
     ldv_38278: 
     {
 #line 772
     __cil_tmp43 = (u32 )reg___0;
 #line 772
     tmp___4 = i915_read32___6(dev_priv, __cil_tmp43);
 #line 772
     last_line = tmp___4 & 4095U;
     }
 #line 773
     if (1) {
       {
 #line 773
       __const_udelay(21475000UL);
       }
     } else {
 #line 773
       __ms = 5UL;
 #line 773
       goto ldv_38270;
       ldv_38269: 
       {
 #line 773
       __const_udelay(4295000UL);
       }
       ldv_38270: 
 #line 773
       tmp___5 = __ms;
 #line 773
       __ms = __ms - 1UL;
 #line 773
       if (tmp___5 != 0UL) {
 #line 774
         goto ldv_38269;
       } else {
 #line 776
         goto ldv_38271;
       }
       ldv_38271: ;
     }
     {
 #line 775
     __cil_tmp44 = (u32 )reg___0;
 #line 775
     tmp___6 = i915_read32___6(dev_priv, __cil_tmp44);
     }
     {
 #line 775
     __cil_tmp45 = tmp___6 & 4095U;
 #line 775
     if (__cil_tmp45 != last_line) {
       {
 #line 775
       __cil_tmp46 = (long )timeout;
 #line 775
       __cil_tmp47 = (long )jiffies;
 #line 775
       __cil_tmp48 = __cil_tmp47 - __cil_tmp46;
 #line 775
       if (__cil_tmp48 < 0L) {
 #line 776
         goto ldv_38278;
       } else {
 #line 778
         goto ldv_38279;
       }
       }
     } else {
 #line 778
       goto ldv_38279;
     }
     }
     ldv_38279: ;
     {
 #line 776
     __cil_tmp49 = (long )jiffies;
 #line 776
     __cil_tmp50 = (long )timeout;
 #line 776
     __cil_tmp51 = __cil_tmp50 - __cil_tmp49;
 #line 776
     if (__cil_tmp51 < 0L) {
       {
 #line 777
       drm_ut_debug_printk(4U, "drm", "intel_wait_for_pipe_off", "pipe_off wait timed out\n");
       }
     } else {
 
     }
     }
   }
   }
 #line 779
   return;
 }
 }
 #line 781 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static char const   *state_string(bool enabled ) 
 { char const   *tmp ;
 
   {
 #line 783
   if ((int )enabled) {
 #line 783
     tmp = "on";
   } else {
 #line 783
     tmp = "off";
   }
 #line 783
   return (tmp);
 }
 }
 #line 787 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pll(struct drm_i915_private *dev_priv , enum pipe pipe , bool state ) 
 { int reg ;
   u32 val ;
   bool cur_state ;
   int __ret_warn_on ;
   char const   *tmp ;
   char const   *tmp___0 ;
   long tmp___1 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
 
   {
   {
 #line 794
   __cil_tmp11 = (unsigned int )pipe;
 #line 794
   __cil_tmp12 = __cil_tmp11 + 6149U;
 #line 794
   __cil_tmp13 = __cil_tmp12 * 4U;
 #line 794
   reg = (int )__cil_tmp13;
 #line 795
   __cil_tmp14 = (u32 )reg;
 #line 795
   val = i915_read32___6(dev_priv, __cil_tmp14);
 #line 796
   __cil_tmp15 = (int )val;
 #line 796
   __cil_tmp16 = __cil_tmp15 < 0;
 #line 796
   cur_state = (bool )__cil_tmp16;
 #line 797
   __cil_tmp17 = (int )state;
 #line 797
   __cil_tmp18 = (int )cur_state;
 #line 797
   __ret_warn_on = __cil_tmp18 != __cil_tmp17;
 #line 797
   __cil_tmp19 = __ret_warn_on != 0;
 #line 797
   __cil_tmp20 = (long )__cil_tmp19;
 #line 797
   tmp___1 = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 797
   if (tmp___1 != 0L) {
     {
 #line 797
     __cil_tmp21 = (int )cur_state;
 #line 797
     __cil_tmp22 = (bool )__cil_tmp21;
 #line 797
     tmp = state_string(__cil_tmp22);
 #line 797
     __cil_tmp23 = (int )state;
 #line 797
     __cil_tmp24 = (bool )__cil_tmp23;
 #line 797
     tmp___0 = state_string(__cil_tmp24);
 #line 797
     __cil_tmp25 = (int const   )799;
 #line 797
     __cil_tmp26 = (int )__cil_tmp25;
 #line 797
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp26, "PLL state assertion failure (expected %s, current %s)\n",
                       tmp___0, tmp);
     }
   } else {
 
   }
   {
 #line 797
   __cil_tmp27 = __ret_warn_on != 0;
 #line 797
   __cil_tmp28 = (long )__cil_tmp27;
 #line 797
   __builtin_expect(__cil_tmp28, 0L);
   }
 #line 799
   return;
 }
 }
 #line 805 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pch_pll(struct drm_i915_private *dev_priv , enum pipe pipe , bool state ) 
 { int reg ;
   u32 val ;
   bool cur_state ;
   int __ret_warn_on ;
   char const   *tmp ;
   char const   *tmp___0 ;
   long tmp___1 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
 
   {
   {
 #line 812
   __cil_tmp11 = (unsigned int )pipe;
 #line 812
   __cil_tmp12 = __cil_tmp11 + 202757U;
 #line 812
   __cil_tmp13 = __cil_tmp12 * 4U;
 #line 812
   reg = (int )__cil_tmp13;
 #line 813
   __cil_tmp14 = (u32 )reg;
 #line 813
   val = i915_read32___6(dev_priv, __cil_tmp14);
 #line 814
   __cil_tmp15 = (int )val;
 #line 814
   __cil_tmp16 = __cil_tmp15 < 0;
 #line 814
   cur_state = (bool )__cil_tmp16;
 #line 815
   __cil_tmp17 = (int )state;
 #line 815
   __cil_tmp18 = (int )cur_state;
 #line 815
   __ret_warn_on = __cil_tmp18 != __cil_tmp17;
 #line 815
   __cil_tmp19 = __ret_warn_on != 0;
 #line 815
   __cil_tmp20 = (long )__cil_tmp19;
 #line 815
   tmp___1 = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 815
   if (tmp___1 != 0L) {
     {
 #line 815
     __cil_tmp21 = (int )cur_state;
 #line 815
     __cil_tmp22 = (bool )__cil_tmp21;
 #line 815
     tmp = state_string(__cil_tmp22);
 #line 815
     __cil_tmp23 = (int )state;
 #line 815
     __cil_tmp24 = (bool )__cil_tmp23;
 #line 815
     tmp___0 = state_string(__cil_tmp24);
 #line 815
     __cil_tmp25 = (int const   )817;
 #line 815
     __cil_tmp26 = (int )__cil_tmp25;
 #line 815
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp26, "PCH PLL state assertion failure (expected %s, current %s)\n",
                       tmp___0, tmp);
     }
   } else {
 
   }
   {
 #line 815
   __cil_tmp27 = __ret_warn_on != 0;
 #line 815
   __cil_tmp28 = (long )__cil_tmp27;
 #line 815
   __builtin_expect(__cil_tmp28, 0L);
   }
 #line 817
   return;
 }
 }
 #line 822 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_fdi_tx(struct drm_i915_private *dev_priv , enum pipe pipe , bool state ) 
 { int reg ;
   u32 val ;
   bool cur_state ;
   int __ret_warn_on ;
   char const   *tmp ;
   char const   *tmp___0 ;
   long tmp___1 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
 
   {
   {
 #line 829
   __cil_tmp11 = (unsigned int )pipe;
 #line 829
   __cil_tmp12 = __cil_tmp11 * 4096U;
 #line 829
   __cil_tmp13 = __cil_tmp12 + 393472U;
 #line 829
   reg = (int )__cil_tmp13;
 #line 830
   __cil_tmp14 = (u32 )reg;
 #line 830
   val = i915_read32___6(dev_priv, __cil_tmp14);
 #line 831
   __cil_tmp15 = (int )val;
 #line 831
   __cil_tmp16 = __cil_tmp15 < 0;
 #line 831
   cur_state = (bool )__cil_tmp16;
 #line 832
   __cil_tmp17 = (int )state;
 #line 832
   __cil_tmp18 = (int )cur_state;
 #line 832
   __ret_warn_on = __cil_tmp18 != __cil_tmp17;
 #line 832
   __cil_tmp19 = __ret_warn_on != 0;
 #line 832
   __cil_tmp20 = (long )__cil_tmp19;
 #line 832
   tmp___1 = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 832
   if (tmp___1 != 0L) {
     {
 #line 832
     __cil_tmp21 = (int )cur_state;
 #line 832
     __cil_tmp22 = (bool )__cil_tmp21;
 #line 832
     tmp = state_string(__cil_tmp22);
 #line 832
     __cil_tmp23 = (int )state;
 #line 832
     __cil_tmp24 = (bool )__cil_tmp23;
 #line 832
     tmp___0 = state_string(__cil_tmp24);
 #line 832
     __cil_tmp25 = (int const   )834;
 #line 832
     __cil_tmp26 = (int )__cil_tmp25;
 #line 832
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp26, "FDI TX state assertion failure (expected %s, current %s)\n",
                       tmp___0, tmp);
     }
   } else {
 
   }
   {
 #line 832
   __cil_tmp27 = __ret_warn_on != 0;
 #line 832
   __cil_tmp28 = (long )__cil_tmp27;
 #line 832
   __builtin_expect(__cil_tmp28, 0L);
   }
 #line 834
   return;
 }
 }
 #line 839 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_fdi_rx(struct drm_i915_private *dev_priv , enum pipe pipe , bool state ) 
 { int reg ;
   u32 val ;
   bool cur_state ;
   int __ret_warn_on ;
   char const   *tmp ;
   char const   *tmp___0 ;
   long tmp___1 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
 
   {
   {
 #line 846
   __cil_tmp11 = (unsigned int )pipe;
 #line 846
   __cil_tmp12 = __cil_tmp11 * 4096U;
 #line 846
   __cil_tmp13 = __cil_tmp12 + 983052U;
 #line 846
   reg = (int )__cil_tmp13;
 #line 847
   __cil_tmp14 = (u32 )reg;
 #line 847
   val = i915_read32___6(dev_priv, __cil_tmp14);
 #line 848
   __cil_tmp15 = (int )val;
 #line 848
   __cil_tmp16 = __cil_tmp15 < 0;
 #line 848
   cur_state = (bool )__cil_tmp16;
 #line 849
   __cil_tmp17 = (int )state;
 #line 849
   __cil_tmp18 = (int )cur_state;
 #line 849
   __ret_warn_on = __cil_tmp18 != __cil_tmp17;
 #line 849
   __cil_tmp19 = __ret_warn_on != 0;
 #line 849
   __cil_tmp20 = (long )__cil_tmp19;
 #line 849
   tmp___1 = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 849
   if (tmp___1 != 0L) {
     {
 #line 849
     __cil_tmp21 = (int )cur_state;
 #line 849
     __cil_tmp22 = (bool )__cil_tmp21;
 #line 849
     tmp = state_string(__cil_tmp22);
 #line 849
     __cil_tmp23 = (int )state;
 #line 849
     __cil_tmp24 = (bool )__cil_tmp23;
 #line 849
     tmp___0 = state_string(__cil_tmp24);
 #line 849
     __cil_tmp25 = (int const   )851;
 #line 849
     __cil_tmp26 = (int )__cil_tmp25;
 #line 849
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp26, "FDI RX state assertion failure (expected %s, current %s)\n",
                       tmp___0, tmp);
     }
   } else {
 
   }
   {
 #line 849
   __cil_tmp27 = __ret_warn_on != 0;
 #line 849
   __cil_tmp28 = (long )__cil_tmp27;
 #line 849
   __builtin_expect(__cil_tmp28, 0L);
   }
 #line 851
   return;
 }
 }
 #line 856 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   int __ret_warn_on ;
   long tmp ;
   struct intel_device_info  const  *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   int __cil_tmp16 ;
   long __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   long __cil_tmp21 ;
 
   {
   {
 #line 863
   __cil_tmp7 = dev_priv->info;
 #line 863
   __cil_tmp8 = __cil_tmp7->gen;
 #line 863
   __cil_tmp9 = (unsigned char )__cil_tmp8;
 #line 863
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 863
   if (__cil_tmp10 == 5U) {
 #line 864
     return;
   } else {
 
   }
   }
   {
 #line 866
   __cil_tmp11 = (unsigned int )pipe;
 #line 866
   __cil_tmp12 = __cil_tmp11 * 4096U;
 #line 866
   __cil_tmp13 = __cil_tmp12 + 393472U;
 #line 866
   reg = (int )__cil_tmp13;
 #line 867
   __cil_tmp14 = (u32 )reg;
 #line 867
   val = i915_read32___6(dev_priv, __cil_tmp14);
 #line 868
   __cil_tmp15 = val & 16384U;
 #line 868
   __ret_warn_on = __cil_tmp15 == 0U;
 #line 868
   __cil_tmp16 = __ret_warn_on != 0;
 #line 868
   __cil_tmp17 = (long )__cil_tmp16;
 #line 868
   tmp = __builtin_expect(__cil_tmp17, 0L);
   }
 #line 868
   if (tmp != 0L) {
     {
 #line 868
     __cil_tmp18 = (int const   )868;
 #line 868
     __cil_tmp19 = (int )__cil_tmp18;
 #line 868
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp19, "FDI TX PLL assertion failure, should be active but is disabled\n");
     }
   } else {
 
   }
   {
 #line 868
   __cil_tmp20 = __ret_warn_on != 0;
 #line 868
   __cil_tmp21 = (long )__cil_tmp20;
 #line 868
   __builtin_expect(__cil_tmp21, 0L);
   }
 #line 870
   return;
 }
 }
 #line 871 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   int __ret_warn_on ;
   long tmp ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   u32 __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   int __cil_tmp12 ;
   long __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   long __cil_tmp17 ;
 
   {
   {
 #line 877
   __cil_tmp7 = (unsigned int )pipe;
 #line 877
   __cil_tmp8 = __cil_tmp7 * 4096U;
 #line 877
   __cil_tmp9 = __cil_tmp8 + 983052U;
 #line 877
   reg = (int )__cil_tmp9;
 #line 878
   __cil_tmp10 = (u32 )reg;
 #line 878
   val = i915_read32___6(dev_priv, __cil_tmp10);
 #line 879
   __cil_tmp11 = val & 8192U;
 #line 879
   __ret_warn_on = __cil_tmp11 == 0U;
 #line 879
   __cil_tmp12 = __ret_warn_on != 0;
 #line 879
   __cil_tmp13 = (long )__cil_tmp12;
 #line 879
   tmp = __builtin_expect(__cil_tmp13, 0L);
   }
 #line 879
   if (tmp != 0L) {
     {
 #line 879
     __cil_tmp14 = (int const   )879;
 #line 879
     __cil_tmp15 = (int )__cil_tmp14;
 #line 879
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp15, "FDI RX PLL assertion failure, should be active but is disabled\n");
     }
   } else {
 
   }
   {
 #line 879
   __cil_tmp16 = __ret_warn_on != 0;
 #line 879
   __cil_tmp17 = (long )__cil_tmp16;
 #line 879
   __builtin_expect(__cil_tmp17, 0L);
   }
 #line 881
   return;
 }
 }
 #line 882 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_panel_unlocked(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int pp_reg ;
   int lvds_reg ;
   u32 val ;
   enum pipe panel_pipe ;
   bool locked ;
   u32 tmp ;
   int __ret_warn_on ;
   int tmp___0 ;
   long tmp___1 ;
   struct drm_device *__cil_tmp12 ;
   void *__cil_tmp13 ;
   struct drm_i915_private *__cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   u8 __cil_tmp16 ;
   unsigned char __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   struct drm_device *__cil_tmp19 ;
   void *__cil_tmp20 ;
   struct drm_i915_private *__cil_tmp21 ;
   struct intel_device_info  const  *__cil_tmp22 ;
   u8 __cil_tmp23 ;
   unsigned char __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   struct drm_device *__cil_tmp26 ;
   void *__cil_tmp27 ;
   struct drm_i915_private *__cil_tmp28 ;
   struct intel_device_info  const  *__cil_tmp29 ;
   unsigned char *__cil_tmp30 ;
   unsigned char *__cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   u32 __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   int __cil_tmp41 ;
   long __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   long __cil_tmp48 ;
 
   {
 #line 887
   panel_pipe = (enum pipe )0;
 #line 888
   locked = locked;
   {
 #line 890
   __cil_tmp12 = dev_priv->dev;
 #line 890
   __cil_tmp13 = __cil_tmp12->dev_private;
 #line 890
   __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
 #line 890
   __cil_tmp15 = __cil_tmp14->info;
 #line 890
   __cil_tmp16 = __cil_tmp15->gen;
 #line 890
   __cil_tmp17 = (unsigned char )__cil_tmp16;
 #line 890
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 890
   if (__cil_tmp18 == 5U) {
 #line 891
     pp_reg = 815620;
 #line 892
     lvds_reg = 921984;
   } else {
     {
 #line 890
     __cil_tmp19 = dev_priv->dev;
 #line 890
     __cil_tmp20 = __cil_tmp19->dev_private;
 #line 890
     __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
 #line 890
     __cil_tmp22 = __cil_tmp21->info;
 #line 890
     __cil_tmp23 = __cil_tmp22->gen;
 #line 890
     __cil_tmp24 = (unsigned char )__cil_tmp23;
 #line 890
     __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 890
     if (__cil_tmp25 == 6U) {
 #line 891
       pp_reg = 815620;
 #line 892
       lvds_reg = 921984;
     } else {
       {
 #line 890
       __cil_tmp26 = dev_priv->dev;
 #line 890
       __cil_tmp27 = __cil_tmp26->dev_private;
 #line 890
       __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
 #line 890
       __cil_tmp29 = __cil_tmp28->info;
 #line 890
       __cil_tmp30 = (unsigned char *)__cil_tmp29;
 #line 890
       __cil_tmp31 = __cil_tmp30 + 2UL;
 #line 890
       __cil_tmp32 = *__cil_tmp31;
 #line 890
       __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 890
       if (__cil_tmp33 != 0U) {
 #line 891
         pp_reg = 815620;
 #line 892
         lvds_reg = 921984;
       } else {
 #line 894
         pp_reg = 397828;
 #line 895
         lvds_reg = 397696;
       }
       }
     }
     }
   }
   }
   {
 #line 898
   __cil_tmp34 = (u32 )pp_reg;
 #line 898
   val = i915_read32___6(dev_priv, __cil_tmp34);
   }
   {
 #line 899
   __cil_tmp35 = val & 1U;
 #line 899
   if (__cil_tmp35 == 0U) {
 #line 901
     locked = (bool )0;
   } else {
     {
 #line 899
     __cil_tmp36 = val & 2882338816U;
 #line 899
     if (__cil_tmp36 == 2882338816U) {
 #line 901
       locked = (bool )0;
     } else {
 
     }
     }
   }
   }
   {
 #line 903
   __cil_tmp37 = (u32 )lvds_reg;
 #line 903
   tmp = i915_read32___6(dev_priv, __cil_tmp37);
   }
   {
 #line 903
   __cil_tmp38 = tmp & 1073741824U;
 #line 903
   if (__cil_tmp38 != 0U) {
 #line 904
     panel_pipe = (enum pipe )1;
   } else {
 
   }
   }
   {
 #line 906
   __cil_tmp39 = (unsigned int )pipe;
 #line 906
   __cil_tmp40 = (unsigned int )panel_pipe;
 #line 906
   if (__cil_tmp40 == __cil_tmp39) {
 #line 906
     if ((int )locked) {
 #line 906
       tmp___0 = 1;
     } else {
 #line 906
       tmp___0 = 0;
     }
   } else {
 #line 906
     tmp___0 = 0;
   }
   }
   {
 #line 906
   __ret_warn_on = tmp___0;
 #line 906
   __cil_tmp41 = __ret_warn_on != 0;
 #line 906
   __cil_tmp42 = (long )__cil_tmp41;
 #line 906
   tmp___1 = __builtin_expect(__cil_tmp42, 0L);
   }
 #line 906
   if (tmp___1 != 0L) {
     {
 #line 906
     __cil_tmp43 = (int const   )908;
 #line 906
     __cil_tmp44 = (int )__cil_tmp43;
 #line 906
     __cil_tmp45 = (unsigned int )pipe;
 #line 906
     __cil_tmp46 = __cil_tmp45 + 65U;
 #line 906
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp44, "panel assertion failure, pipe %c regs locked\n",
                       __cil_tmp46);
     }
   } else {
 
   }
   {
 #line 906
   __cil_tmp47 = __ret_warn_on != 0;
 #line 906
   __cil_tmp48 = (long )__cil_tmp47;
 #line 906
   __builtin_expect(__cil_tmp48, 0L);
   }
 #line 908
   return;
 }
 }
 #line 911 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pipe(struct drm_i915_private *dev_priv , enum pipe pipe , bool state ) 
 { int reg ;
   u32 val ;
   bool cur_state ;
   int __ret_warn_on ;
   char const   *tmp ;
   char const   *tmp___0 ;
   long tmp___1 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   u32 __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
   int __cil_tmp21 ;
   bool __cil_tmp22 ;
   int __cil_tmp23 ;
   bool __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
   long __cil_tmp30 ;
 
   {
   {
 #line 918
   __cil_tmp11 = (unsigned int )pipe;
 #line 918
   __cil_tmp12 = __cil_tmp11 * 4096U;
 #line 918
   __cil_tmp13 = __cil_tmp12 + 458760U;
 #line 918
   reg = (int )__cil_tmp13;
 #line 919
   __cil_tmp14 = (u32 )reg;
 #line 919
   val = i915_read32___6(dev_priv, __cil_tmp14);
 #line 920
   __cil_tmp15 = (int )val;
 #line 920
   __cil_tmp16 = __cil_tmp15 < 0;
 #line 920
   cur_state = (bool )__cil_tmp16;
 #line 921
   __cil_tmp17 = (int )state;
 #line 921
   __cil_tmp18 = (int )cur_state;
 #line 921
   __ret_warn_on = __cil_tmp18 != __cil_tmp17;
 #line 921
   __cil_tmp19 = __ret_warn_on != 0;
 #line 921
   __cil_tmp20 = (long )__cil_tmp19;
 #line 921
   tmp___1 = __builtin_expect(__cil_tmp20, 0L);
   }
 #line 921
   if (tmp___1 != 0L) {
     {
 #line 921
     __cil_tmp21 = (int )cur_state;
 #line 921
     __cil_tmp22 = (bool )__cil_tmp21;
 #line 921
     tmp = state_string(__cil_tmp22);
 #line 921
     __cil_tmp23 = (int )state;
 #line 921
     __cil_tmp24 = (bool )__cil_tmp23;
 #line 921
     tmp___0 = state_string(__cil_tmp24);
 #line 921
     __cil_tmp25 = (int const   )923;
 #line 921
     __cil_tmp26 = (int )__cil_tmp25;
 #line 921
     __cil_tmp27 = (unsigned int )pipe;
 #line 921
     __cil_tmp28 = __cil_tmp27 + 65U;
 #line 921
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp26, "pipe %c assertion failure (expected %s, current %s)\n",
                       __cil_tmp28, tmp___0, tmp);
     }
   } else {
 
   }
   {
 #line 921
   __cil_tmp29 = __ret_warn_on != 0;
 #line 921
   __cil_tmp30 = (long )__cil_tmp29;
 #line 921
   __builtin_expect(__cil_tmp30, 0L);
   }
 #line 923
   return;
 }
 }
 #line 928 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_plane_enabled(struct drm_i915_private *dev_priv , enum plane plane ) 
 { int reg ;
   u32 val ;
   int __ret_warn_on ;
   long tmp ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   u32 __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   long __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   long __cil_tmp19 ;
 
   {
   {
 #line 934
   __cil_tmp7 = (unsigned int )plane;
 #line 934
   __cil_tmp8 = __cil_tmp7 * 4096U;
 #line 934
   __cil_tmp9 = __cil_tmp8 + 459136U;
 #line 934
   reg = (int )__cil_tmp9;
 #line 935
   __cil_tmp10 = (u32 )reg;
 #line 935
   val = i915_read32___6(dev_priv, __cil_tmp10);
 #line 936
   __cil_tmp11 = (int )val;
 #line 936
   __ret_warn_on = __cil_tmp11 >= 0;
 #line 936
   __cil_tmp12 = __ret_warn_on != 0;
 #line 936
   __cil_tmp13 = (long )__cil_tmp12;
 #line 936
   tmp = __builtin_expect(__cil_tmp13, 0L);
   }
 #line 936
   if (tmp != 0L) {
     {
 #line 936
     __cil_tmp14 = (int const   )938;
 #line 936
     __cil_tmp15 = (int )__cil_tmp14;
 #line 936
     __cil_tmp16 = (unsigned int )plane;
 #line 936
     __cil_tmp17 = __cil_tmp16 + 65U;
 #line 936
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp15, "plane %c assertion failure, should be active but is disabled\n",
                       __cil_tmp17);
     }
   } else {
 
   }
   {
 #line 936
   __cil_tmp18 = __ret_warn_on != 0;
 #line 936
   __cil_tmp19 = (long )__cil_tmp18;
 #line 936
   __builtin_expect(__cil_tmp19, 0L);
   }
 #line 938
   return;
 }
 }
 #line 941 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_planes_disabled(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   int i ;
   u32 val ;
   int cur_pipe ;
   int __ret_warn_on ;
   int tmp ;
   long tmp___0 ;
   struct drm_device *__cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   struct drm_device *__cil_tmp17 ;
   void *__cil_tmp18 ;
   struct drm_i915_private *__cil_tmp19 ;
   struct intel_device_info  const  *__cil_tmp20 ;
   u8 __cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   struct drm_device *__cil_tmp24 ;
   void *__cil_tmp25 ;
   struct drm_i915_private *__cil_tmp26 ;
   struct intel_device_info  const  *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char *__cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   int __cil_tmp32 ;
   u32 __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   int __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   int __cil_tmp39 ;
   long __cil_tmp40 ;
   int __cil_tmp41 ;
   int __cil_tmp42 ;
   int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   int __cil_tmp46 ;
   long __cil_tmp47 ;
 
   {
   {
 #line 949
   __cil_tmp10 = dev_priv->dev;
 #line 949
   __cil_tmp11 = __cil_tmp10->dev_private;
 #line 949
   __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 949
   __cil_tmp13 = __cil_tmp12->info;
 #line 949
   __cil_tmp14 = __cil_tmp13->gen;
 #line 949
   __cil_tmp15 = (unsigned char )__cil_tmp14;
 #line 949
   __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 949
   if (__cil_tmp16 == 5U) {
 #line 950
     return;
   } else {
     {
 #line 949
     __cil_tmp17 = dev_priv->dev;
 #line 949
     __cil_tmp18 = __cil_tmp17->dev_private;
 #line 949
     __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
 #line 949
     __cil_tmp20 = __cil_tmp19->info;
 #line 949
     __cil_tmp21 = __cil_tmp20->gen;
 #line 949
     __cil_tmp22 = (unsigned char )__cil_tmp21;
 #line 949
     __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 949
     if (__cil_tmp23 == 6U) {
 #line 950
       return;
     } else {
       {
 #line 949
       __cil_tmp24 = dev_priv->dev;
 #line 949
       __cil_tmp25 = __cil_tmp24->dev_private;
 #line 949
       __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
 #line 949
       __cil_tmp27 = __cil_tmp26->info;
 #line 949
       __cil_tmp28 = (unsigned char *)__cil_tmp27;
 #line 949
       __cil_tmp29 = __cil_tmp28 + 2UL;
 #line 949
       __cil_tmp30 = *__cil_tmp29;
 #line 949
       __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 949
       if (__cil_tmp31 != 0U) {
 #line 950
         return;
       } else {
 
       }
       }
     }
     }
   }
   }
 #line 953
   i = 0;
 #line 953
   goto ldv_38385;
   ldv_38384: 
   {
 #line 954
   __cil_tmp32 = i * 4096;
 #line 954
   reg = __cil_tmp32 + 459136;
 #line 955
   __cil_tmp33 = (u32 )reg;
 #line 955
   val = i915_read32___6(dev_priv, __cil_tmp33);
 #line 956
   __cil_tmp34 = val & 50331648U;
 #line 956
   __cil_tmp35 = __cil_tmp34 >> 24;
 #line 956
   cur_pipe = (int )__cil_tmp35;
   }
   {
 #line 958
   __cil_tmp36 = (int )val;
 #line 958
   if (__cil_tmp36 < 0) {
     {
 #line 958
     __cil_tmp37 = (unsigned int )pipe;
 #line 958
     __cil_tmp38 = (unsigned int )cur_pipe;
 #line 958
     if (__cil_tmp38 == __cil_tmp37) {
 #line 958
       tmp = 1;
     } else {
 #line 958
       tmp = 0;
     }
     }
   } else {
 #line 958
     tmp = 0;
   }
   }
   {
 #line 958
   __ret_warn_on = tmp;
 #line 958
   __cil_tmp39 = __ret_warn_on != 0;
 #line 958
   __cil_tmp40 = (long )__cil_tmp39;
 #line 958
   tmp___0 = __builtin_expect(__cil_tmp40, 0L);
   }
 #line 958
   if (tmp___0 != 0L) {
     {
 #line 958
     __cil_tmp41 = (int const   )960;
 #line 958
     __cil_tmp42 = (int )__cil_tmp41;
 #line 958
     __cil_tmp43 = i + 65;
 #line 958
     __cil_tmp44 = (unsigned int )pipe;
 #line 958
     __cil_tmp45 = __cil_tmp44 + 65U;
 #line 958
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp42, "plane %c assertion failure, should be off on pipe %c but is still active\n",
                       __cil_tmp43, __cil_tmp45);
     }
   } else {
 
   }
   {
 #line 958
   __cil_tmp46 = __ret_warn_on != 0;
 #line 958
   __cil_tmp47 = (long )__cil_tmp46;
 #line 958
   __builtin_expect(__cil_tmp47, 0L);
 #line 953
   i = i + 1;
   }
   ldv_38385: ;
 #line 953
   if (i <= 1) {
 #line 954
     goto ldv_38384;
   } else {
 #line 956
     goto ldv_38386;
   }
   ldv_38386: ;
 #line 958
   return;
 }
 }
 #line 964 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv ) 
 { u32 val ;
   bool enabled ;
   int __ret_warn_on ;
   long tmp ;
   unsigned int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   long __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   long __cil_tmp13 ;
 
   {
   {
 #line 969
   val = i915_read32___6(dev_priv, 811520U);
 #line 970
   __cil_tmp6 = val & 8064U;
 #line 970
   __cil_tmp7 = __cil_tmp6 != 0U;
 #line 970
   enabled = (bool )__cil_tmp7;
 #line 972
   __ret_warn_on = ! enabled;
 #line 972
   __cil_tmp8 = __ret_warn_on != 0;
 #line 972
   __cil_tmp9 = (long )__cil_tmp8;
 #line 972
   tmp = __builtin_expect(__cil_tmp9, 0L);
   }
 #line 972
   if (tmp != 0L) {
     {
 #line 972
     __cil_tmp10 = (int const   )972;
 #line 972
     __cil_tmp11 = (int )__cil_tmp10;
 #line 972
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp11, "PCH refclk assertion failure, should be active but is disabled\n");
     }
   } else {
 
   }
   {
 #line 972
   __cil_tmp12 = __ret_warn_on != 0;
 #line 972
   __cil_tmp13 = (long )__cil_tmp12;
 #line 972
   __builtin_expect(__cil_tmp13, 0L);
   }
 #line 974
   return;
 }
 }
 #line 975 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   bool enabled ;
   int __ret_warn_on ;
   long tmp ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   u32 __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   long __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   int __cil_tmp20 ;
   long __cil_tmp21 ;
 
   {
   {
 #line 982
   __cil_tmp8 = (unsigned int )pipe;
 #line 982
   __cil_tmp9 = __cil_tmp8 * 4096U;
 #line 982
   __cil_tmp10 = __cil_tmp9 + 983048U;
 #line 982
   reg = (int )__cil_tmp10;
 #line 983
   __cil_tmp11 = (u32 )reg;
 #line 983
   val = i915_read32___6(dev_priv, __cil_tmp11);
 #line 984
   __cil_tmp12 = (int )val;
 #line 984
   __cil_tmp13 = __cil_tmp12 < 0;
 #line 984
   enabled = (bool )__cil_tmp13;
 #line 985
   __ret_warn_on = (int )enabled;
 #line 985
   __cil_tmp14 = __ret_warn_on != 0;
 #line 985
   __cil_tmp15 = (long )__cil_tmp14;
 #line 985
   tmp = __builtin_expect(__cil_tmp15, 0L);
   }
 #line 985
   if (tmp != 0L) {
     {
 #line 985
     __cil_tmp16 = (int const   )987;
 #line 985
     __cil_tmp17 = (int )__cil_tmp16;
 #line 985
     __cil_tmp18 = (unsigned int )pipe;
 #line 985
     __cil_tmp19 = __cil_tmp18 + 65U;
 #line 985
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp17, "transcoder assertion failed, should be off on pipe %c but is still active\n",
                       __cil_tmp19);
     }
   } else {
 
   }
   {
 #line 985
   __cil_tmp20 = __ret_warn_on != 0;
 #line 985
   __cil_tmp21 = (long )__cil_tmp20;
 #line 985
   __builtin_expect(__cil_tmp21, 0L);
   }
 #line 987
   return;
 }
 }
 #line 990 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv , enum pipe pipe ,
                                    int reg ) 
 { u32 val ;
   u32 tmp ;
   int __ret_warn_on ;
   long tmp___0 ;
   u32 __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   int __cil_tmp13 ;
   long __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
 
   {
   {
 #line 993
   __cil_tmp8 = (u32 )reg;
 #line 993
   tmp = i915_read32___6(dev_priv, __cil_tmp8);
 #line 993
   val = tmp;
 #line 994
   __cil_tmp9 = (unsigned int )pipe;
 #line 994
   __cil_tmp10 = __cil_tmp9 << 30;
 #line 994
   __cil_tmp11 = __cil_tmp10 | 2147483648U;
 #line 994
   __cil_tmp12 = val & 3221225472U;
 #line 994
   __ret_warn_on = __cil_tmp12 == __cil_tmp11;
 #line 994
   __cil_tmp13 = __ret_warn_on != 0;
 #line 994
   __cil_tmp14 = (long )__cil_tmp13;
 #line 994
   tmp___0 = __builtin_expect(__cil_tmp14, 0L);
   }
 #line 994
   if (tmp___0 != 0L) {
     {
 #line 994
     __cil_tmp15 = (int const   )996;
 #line 994
     __cil_tmp16 = (int )__cil_tmp15;
 #line 994
     __cil_tmp17 = (unsigned int )pipe;
 #line 994
     __cil_tmp18 = __cil_tmp17 + 65U;
 #line 994
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp16, "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
                       reg, __cil_tmp18);
     }
   } else {
 
   }
   {
 #line 994
   __cil_tmp19 = __ret_warn_on != 0;
 #line 994
   __cil_tmp20 = (long )__cil_tmp19;
 #line 994
   __builtin_expect(__cil_tmp20, 0L);
   }
 #line 996
   return;
 }
 }
 #line 999 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv , enum pipe pipe ,
                                      int reg ) 
 { u32 val ;
   u32 tmp ;
   int __ret_warn_on ;
   long tmp___0 ;
   u32 __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   int __cil_tmp13 ;
   long __cil_tmp14 ;
   int __cil_tmp15 ;
   int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   long __cil_tmp20 ;
 
   {
   {
 #line 1002
   __cil_tmp8 = (u32 )reg;
 #line 1002
   tmp = i915_read32___6(dev_priv, __cil_tmp8);
 #line 1002
   val = tmp;
 #line 1003
   __cil_tmp9 = (unsigned int )pipe;
 #line 1003
   __cil_tmp10 = __cil_tmp9 << 30;
 #line 1003
   __cil_tmp11 = __cil_tmp10 | 2147483648U;
 #line 1003
   __cil_tmp12 = val & 3221225472U;
 #line 1003
   __ret_warn_on = __cil_tmp12 == __cil_tmp11;
 #line 1003
   __cil_tmp13 = __ret_warn_on != 0;
 #line 1003
   __cil_tmp14 = (long )__cil_tmp13;
 #line 1003
   tmp___0 = __builtin_expect(__cil_tmp14, 0L);
   }
 #line 1003
   if (tmp___0 != 0L) {
     {
 #line 1003
     __cil_tmp15 = (int const   )1005;
 #line 1003
     __cil_tmp16 = (int )__cil_tmp15;
 #line 1003
     __cil_tmp17 = (unsigned int )pipe;
 #line 1003
     __cil_tmp18 = __cil_tmp17 + 65U;
 #line 1003
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp16, "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
                       reg, __cil_tmp18);
     }
   } else {
 
   }
   {
 #line 1003
   __cil_tmp19 = __ret_warn_on != 0;
 #line 1003
   __cil_tmp20 = (long )__cil_tmp19;
 #line 1003
   __builtin_expect(__cil_tmp20, 0L);
   }
 #line 1005
   return;
 }
 }
 #line 1008 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   int __ret_warn_on ;
   long tmp ;
   int __ret_warn_on___0 ;
   long tmp___0 ;
   u32 __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   int __cil_tmp14 ;
   long __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   int __cil_tmp20 ;
   long __cil_tmp21 ;
   u32 __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   int __cil_tmp27 ;
   long __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   int __cil_tmp33 ;
   long __cil_tmp34 ;
 
   {
   {
 #line 1014
   assert_pch_dp_disabled(dev_priv, pipe, 934144);
 #line 1015
   assert_pch_dp_disabled(dev_priv, pipe, 934400);
 #line 1016
   assert_pch_dp_disabled(dev_priv, pipe, 934656);
 #line 1018
   reg = 921856;
 #line 1019
   __cil_tmp9 = (u32 )reg;
 #line 1019
   val = i915_read32___6(dev_priv, __cil_tmp9);
 #line 1020
   __cil_tmp10 = (unsigned int )pipe;
 #line 1020
   __cil_tmp11 = __cil_tmp10 << 30;
 #line 1020
   __cil_tmp12 = __cil_tmp11 | 2147483648U;
 #line 1020
   __cil_tmp13 = val & 3221225472U;
 #line 1020
   __ret_warn_on = __cil_tmp13 == __cil_tmp12;
 #line 1020
   __cil_tmp14 = __ret_warn_on != 0;
 #line 1020
   __cil_tmp15 = (long )__cil_tmp14;
 #line 1020
   tmp = __builtin_expect(__cil_tmp15, 0L);
   }
 #line 1020
   if (tmp != 0L) {
     {
 #line 1020
     __cil_tmp16 = (int const   )1022;
 #line 1020
     __cil_tmp17 = (int )__cil_tmp16;
 #line 1020
     __cil_tmp18 = (unsigned int )pipe;
 #line 1020
     __cil_tmp19 = __cil_tmp18 + 65U;
 #line 1020
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp17, "PCH VGA enabled on transcoder %c, should be disabled\n",
                       __cil_tmp19);
     }
   } else {
 
   }
   {
 #line 1020
   __cil_tmp20 = __ret_warn_on != 0;
 #line 1020
   __cil_tmp21 = (long )__cil_tmp20;
 #line 1020
   __builtin_expect(__cil_tmp21, 0L);
 #line 1024
   reg = 921984;
 #line 1025
   __cil_tmp22 = (u32 )reg;
 #line 1025
   val = i915_read32___6(dev_priv, __cil_tmp22);
 #line 1026
   __cil_tmp23 = (unsigned int )pipe;
 #line 1026
   __cil_tmp24 = __cil_tmp23 << 30;
 #line 1026
   __cil_tmp25 = __cil_tmp24 | 2147483648U;
 #line 1026
   __cil_tmp26 = val & 3221225472U;
 #line 1026
   __ret_warn_on___0 = __cil_tmp26 == __cil_tmp25;
 #line 1026
   __cil_tmp27 = __ret_warn_on___0 != 0;
 #line 1026
   __cil_tmp28 = (long )__cil_tmp27;
 #line 1026
   tmp___0 = __builtin_expect(__cil_tmp28, 0L);
   }
 #line 1026
   if (tmp___0 != 0L) {
     {
 #line 1026
     __cil_tmp29 = (int const   )1028;
 #line 1026
     __cil_tmp30 = (int )__cil_tmp29;
 #line 1026
     __cil_tmp31 = (unsigned int )pipe;
 #line 1026
     __cil_tmp32 = __cil_tmp31 + 65U;
 #line 1026
     warn_slowpath_fmt("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp30, "PCH LVDS enabled on transcoder %c, should be disabled\n",
                       __cil_tmp32);
     }
   } else {
 
   }
   {
 #line 1026
   __cil_tmp33 = __ret_warn_on___0 != 0;
 #line 1026
   __cil_tmp34 = (long )__cil_tmp33;
 #line 1026
   __builtin_expect(__cil_tmp34, 0L);
 #line 1030
   assert_pch_hdmi_disabled(dev_priv, pipe, 921920);
 #line 1031
   assert_pch_hdmi_disabled(dev_priv, pipe, 921936);
 #line 1032
   assert_pch_hdmi_disabled(dev_priv, pipe, 921952);
   }
 #line 1033
   return;
 }
 }
 #line 1046 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_enable_pll(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   long tmp ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   long __cil_tmp11 ;
   struct drm_device *__cil_tmp12 ;
   void *__cil_tmp13 ;
   struct drm_i915_private *__cil_tmp14 ;
   struct intel_device_info  const  *__cil_tmp15 ;
   unsigned char *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   struct drm_device *__cil_tmp20 ;
   int __cil_tmp21 ;
   unsigned int __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   u32 __cil_tmp25 ;
   u32 __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   void *__cil_tmp28 ;
   void const volatile   *__cil_tmp29 ;
   void const volatile   *__cil_tmp30 ;
   u32 __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   void *__cil_tmp33 ;
   void const volatile   *__cil_tmp34 ;
   void const volatile   *__cil_tmp35 ;
   u32 __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   void *__cil_tmp38 ;
   void const volatile   *__cil_tmp39 ;
   void const volatile   *__cil_tmp40 ;
 
   {
   {
 #line 1052
   __cil_tmp6 = dev_priv->info;
 #line 1052
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1052
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1052
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1052
   __cil_tmp10 = __cil_tmp9 > 4U;
 #line 1052
   __cil_tmp11 = (long )__cil_tmp10;
 #line 1052
   tmp = __builtin_expect(__cil_tmp11, 0L);
   }
 #line 1052
   if (tmp != 0L) {
 #line 1052
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                          "i" (1052), "i" (12UL));
     ldv_38435: ;
 #line 1052
     goto ldv_38435;
   } else {
 
   }
   {
 #line 1055
   __cil_tmp12 = dev_priv->dev;
 #line 1055
   __cil_tmp13 = __cil_tmp12->dev_private;
 #line 1055
   __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
 #line 1055
   __cil_tmp15 = __cil_tmp14->info;
 #line 1055
   __cil_tmp16 = (unsigned char *)__cil_tmp15;
 #line 1055
   __cil_tmp17 = __cil_tmp16 + 1UL;
 #line 1055
   __cil_tmp18 = *__cil_tmp17;
 #line 1055
   __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 1055
   if (__cil_tmp19 != 0U) {
     {
 #line 1055
     __cil_tmp20 = dev_priv->dev;
 #line 1055
     __cil_tmp21 = __cil_tmp20->pci_device;
 #line 1055
     if (__cil_tmp21 != 13687) {
       {
 #line 1056
       assert_panel_unlocked(dev_priv, pipe);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1058
   __cil_tmp22 = (unsigned int )pipe;
 #line 1058
   __cil_tmp23 = __cil_tmp22 + 6149U;
 #line 1058
   __cil_tmp24 = __cil_tmp23 * 4U;
 #line 1058
   reg = (int )__cil_tmp24;
 #line 1059
   __cil_tmp25 = (u32 )reg;
 #line 1059
   val = i915_read32___6(dev_priv, __cil_tmp25);
 #line 1060
   val = val | 2147483648U;
 #line 1063
   __cil_tmp26 = (u32 )reg;
 #line 1063
   i915_write32___4(dev_priv, __cil_tmp26, val);
 #line 1064
   __cil_tmp27 = (unsigned long )reg;
 #line 1064
   __cil_tmp28 = dev_priv->regs;
 #line 1064
   __cil_tmp29 = (void const volatile   *)__cil_tmp28;
 #line 1064
   __cil_tmp30 = __cil_tmp29 + __cil_tmp27;
 #line 1064
   readl(__cil_tmp30);
 #line 1065
   __const_udelay(644250UL);
 #line 1066
   __cil_tmp31 = (u32 )reg;
 #line 1066
   i915_write32___4(dev_priv, __cil_tmp31, val);
 #line 1067
   __cil_tmp32 = (unsigned long )reg;
 #line 1067
   __cil_tmp33 = dev_priv->regs;
 #line 1067
   __cil_tmp34 = (void const volatile   *)__cil_tmp33;
 #line 1067
   __cil_tmp35 = __cil_tmp34 + __cil_tmp32;
 #line 1067
   readl(__cil_tmp35);
 #line 1068
   __const_udelay(644250UL);
 #line 1069
   __cil_tmp36 = (u32 )reg;
 #line 1069
   i915_write32___4(dev_priv, __cil_tmp36, val);
 #line 1070
   __cil_tmp37 = (unsigned long )reg;
 #line 1070
   __cil_tmp38 = dev_priv->regs;
 #line 1070
   __cil_tmp39 = (void const volatile   *)__cil_tmp38;
 #line 1070
   __cil_tmp40 = __cil_tmp39 + __cil_tmp37;
 #line 1070
   readl(__cil_tmp40);
 #line 1071
   __const_udelay(644250UL);
   }
 #line 1072
   return;
 }
 }
 #line 1083 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_disable_pll(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   unsigned int __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   int __cil_tmp7 ;
   bool __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   u32 __cil_tmp12 ;
   u32 __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   void *__cil_tmp15 ;
   void const volatile   *__cil_tmp16 ;
   void const volatile   *__cil_tmp17 ;
 
   {
   {
 #line 1089
   __cil_tmp5 = (unsigned int )pipe;
 #line 1089
   if (__cil_tmp5 == 0U) {
     {
 #line 1089
     __cil_tmp6 = dev_priv->quirks;
 #line 1089
     __cil_tmp7 = (int )__cil_tmp6;
 #line 1089
     if (__cil_tmp7 & 1) {
 #line 1090
       return;
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1093
   __cil_tmp8 = (bool )0;
 #line 1093
   assert_pipe(dev_priv, pipe, __cil_tmp8);
 #line 1095
   __cil_tmp9 = (unsigned int )pipe;
 #line 1095
   __cil_tmp10 = __cil_tmp9 + 6149U;
 #line 1095
   __cil_tmp11 = __cil_tmp10 * 4U;
 #line 1095
   reg = (int )__cil_tmp11;
 #line 1096
   __cil_tmp12 = (u32 )reg;
 #line 1096
   val = i915_read32___6(dev_priv, __cil_tmp12);
 #line 1097
   val = val & 2147483647U;
 #line 1098
   __cil_tmp13 = (u32 )reg;
 #line 1098
   i915_write32___4(dev_priv, __cil_tmp13, val);
 #line 1099
   __cil_tmp14 = (unsigned long )reg;
 #line 1099
   __cil_tmp15 = dev_priv->regs;
 #line 1099
   __cil_tmp16 = (void const volatile   *)__cil_tmp15;
 #line 1099
   __cil_tmp17 = __cil_tmp16 + __cil_tmp14;
 #line 1099
   readl(__cil_tmp17);
   }
 #line 1100
   return;
 }
 }
 #line 1110 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   long tmp ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   long __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   u32 __cil_tmp15 ;
   u32 __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   void *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   void const volatile   *__cil_tmp20 ;
 
   {
   {
 #line 1117
   __cil_tmp6 = dev_priv->info;
 #line 1117
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1117
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1117
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1117
   __cil_tmp10 = __cil_tmp9 <= 4U;
 #line 1117
   __cil_tmp11 = (long )__cil_tmp10;
 #line 1117
   tmp = __builtin_expect(__cil_tmp11, 0L);
   }
 #line 1117
   if (tmp != 0L) {
 #line 1117
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                          "i" (1117), "i" (12UL));
     ldv_38448: ;
 #line 1117
     goto ldv_38448;
   } else {
 
   }
   {
 #line 1120
   assert_pch_refclk_enabled(dev_priv);
 #line 1122
   __cil_tmp12 = (unsigned int )pipe;
 #line 1122
   __cil_tmp13 = __cil_tmp12 + 202757U;
 #line 1122
   __cil_tmp14 = __cil_tmp13 * 4U;
 #line 1122
   reg = (int )__cil_tmp14;
 #line 1123
   __cil_tmp15 = (u32 )reg;
 #line 1123
   val = i915_read32___6(dev_priv, __cil_tmp15);
 #line 1124
   val = val | 2147483648U;
 #line 1125
   __cil_tmp16 = (u32 )reg;
 #line 1125
   i915_write32___4(dev_priv, __cil_tmp16, val);
 #line 1126
   __cil_tmp17 = (unsigned long )reg;
 #line 1126
   __cil_tmp18 = dev_priv->regs;
 #line 1126
   __cil_tmp19 = (void const volatile   *)__cil_tmp18;
 #line 1126
   __cil_tmp20 = __cil_tmp19 + __cil_tmp17;
 #line 1126
   readl(__cil_tmp20);
 #line 1127
   __const_udelay(859000UL);
   }
 #line 1128
   return;
 }
 }
 #line 1130 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   long tmp ;
   struct intel_device_info  const  *__cil_tmp6 ;
   u8 __cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   int __cil_tmp10 ;
   long __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   u32 __cil_tmp15 ;
   u32 __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   void *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   void const volatile   *__cil_tmp20 ;
 
   {
   {
 #line 1137
   __cil_tmp6 = dev_priv->info;
 #line 1137
   __cil_tmp7 = __cil_tmp6->gen;
 #line 1137
   __cil_tmp8 = (unsigned char )__cil_tmp7;
 #line 1137
   __cil_tmp9 = (unsigned int )__cil_tmp8;
 #line 1137
   __cil_tmp10 = __cil_tmp9 <= 4U;
 #line 1137
   __cil_tmp11 = (long )__cil_tmp10;
 #line 1137
   tmp = __builtin_expect(__cil_tmp11, 0L);
   }
 #line 1137
   if (tmp != 0L) {
 #line 1137
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                          "i" (1137), "i" (12UL));
     ldv_38455: ;
 #line 1137
     goto ldv_38455;
   } else {
 
   }
   {
 #line 1140
   assert_transcoder_disabled(dev_priv, pipe);
 #line 1142
   __cil_tmp12 = (unsigned int )pipe;
 #line 1142
   __cil_tmp13 = __cil_tmp12 + 202757U;
 #line 1142
   __cil_tmp14 = __cil_tmp13 * 4U;
 #line 1142
   reg = (int )__cil_tmp14;
 #line 1143
   __cil_tmp15 = (u32 )reg;
 #line 1143
   val = i915_read32___6(dev_priv, __cil_tmp15);
 #line 1144
   val = val & 2147483647U;
 #line 1145
   __cil_tmp16 = (u32 )reg;
 #line 1145
   i915_write32___4(dev_priv, __cil_tmp16, val);
 #line 1146
   __cil_tmp17 = (unsigned long )reg;
 #line 1146
   __cil_tmp18 = dev_priv->regs;
 #line 1146
   __cil_tmp19 = (void const volatile   *)__cil_tmp18;
 #line 1146
   __cil_tmp20 = __cil_tmp19 + __cil_tmp17;
 #line 1146
   readl(__cil_tmp20);
 #line 1147
   __const_udelay(859000UL);
   }
 #line 1148
   return;
 }
 }
 #line 1150 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_enable_transcoder(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   long tmp ;
   u32 tmp___0 ;
   unsigned long timeout__ ;
   unsigned long tmp___1 ;
   int ret__ ;
   struct thread_info *tmp___2 ;
   int pfo_ret__ ;
   int tmp___3 ;
   u32 tmp___4 ;
   struct intel_device_info  const  *__cil_tmp14 ;
   u8 __cil_tmp15 ;
   unsigned char __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   long __cil_tmp19 ;
   bool __cil_tmp20 ;
   bool __cil_tmp21 ;
   bool __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   u32 __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   u32 __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned int __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   long __cil_tmp36 ;
   long __cil_tmp37 ;
   long __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   atomic_t const   *__cil_tmp41 ;
   u32 __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
 
   {
   {
 #line 1157
   __cil_tmp14 = dev_priv->info;
 #line 1157
   __cil_tmp15 = __cil_tmp14->gen;
 #line 1157
   __cil_tmp16 = (unsigned char )__cil_tmp15;
 #line 1157
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 1157
   __cil_tmp18 = __cil_tmp17 <= 4U;
 #line 1157
   __cil_tmp19 = (long )__cil_tmp18;
 #line 1157
   tmp = __builtin_expect(__cil_tmp19, 0L);
   }
 #line 1157
   if (tmp != 0L) {
 #line 1157
     __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                          "i" (1157), "i" (12UL));
     ldv_38462: ;
 #line 1157
     goto ldv_38462;
   } else {
 
   }
   {
 #line 1160
   __cil_tmp20 = (bool )1;
 #line 1160
   assert_pch_pll(dev_priv, pipe, __cil_tmp20);
 #line 1163
   __cil_tmp21 = (bool )1;
 #line 1163
   assert_fdi_tx(dev_priv, pipe, __cil_tmp21);
 #line 1164
   __cil_tmp22 = (bool )1;
 #line 1164
   assert_fdi_rx(dev_priv, pipe, __cil_tmp22);
 #line 1166
   __cil_tmp23 = (unsigned int )pipe;
 #line 1166
   __cil_tmp24 = __cil_tmp23 * 4096U;
 #line 1166
   __cil_tmp25 = __cil_tmp24 + 983048U;
 #line 1166
   reg = (int )__cil_tmp25;
 #line 1167
   __cil_tmp26 = (u32 )reg;
 #line 1167
   val = i915_read32___6(dev_priv, __cil_tmp26);
 #line 1172
   val = val & 4294967071U;
 #line 1173
   __cil_tmp27 = (unsigned int )pipe;
 #line 1173
   __cil_tmp28 = __cil_tmp27 * 4096U;
 #line 1173
   __cil_tmp29 = __cil_tmp28 + 458760U;
 #line 1173
   tmp___0 = i915_read32___6(dev_priv, __cil_tmp29);
 #line 1173
   __cil_tmp30 = tmp___0 & 224U;
 #line 1173
   val = __cil_tmp30 | val;
 #line 1174
   __cil_tmp31 = (u32 )reg;
 #line 1174
   __cil_tmp32 = val | 2147483648U;
 #line 1174
   i915_write32___4(dev_priv, __cil_tmp31, __cil_tmp32);
 #line 1175
   __cil_tmp33 = (unsigned int const   )100U;
 #line 1175
   __cil_tmp34 = (unsigned int )__cil_tmp33;
 #line 1175
   tmp___1 = msecs_to_jiffies(__cil_tmp34);
 #line 1175
   __cil_tmp35 = (unsigned long )jiffies;
 #line 1175
   timeout__ = tmp___1 + __cil_tmp35;
 #line 1175
   ret__ = 0;
   }
 #line 1175
   goto ldv_38481;
   ldv_38480: ;
   {
 #line 1175
   __cil_tmp36 = (long )jiffies;
 #line 1175
   __cil_tmp37 = (long )timeout__;
 #line 1175
   __cil_tmp38 = __cil_tmp37 - __cil_tmp36;
 #line 1175
   if (__cil_tmp38 < 0L) {
 #line 1175
     ret__ = -110;
 #line 1175
     goto ldv_38471;
   } else {
 
   }
   }
   {
 #line 1175
   tmp___2 = current_thread_info();
   }
   {
 #line 1175
   __cil_tmp39 = tmp___2->preempt_count;
 #line 1175
   __cil_tmp40 = __cil_tmp39 & -268435457;
 #line 1175
   if (__cil_tmp40 == 0) {
 #line 1175
     if (1) {
 #line 1175
       goto case_4;
     } else {
 #line 1175
       goto switch_default;
 #line 1175
       if (0) {
 #line 1175
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 1175
         goto ldv_38474;
 #line 1175
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1175
         goto ldv_38474;
         case_4: 
 #line 1175
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1175
         goto ldv_38474;
 #line 1175
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1175
         goto ldv_38474;
         switch_default: 
         {
 #line 1175
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_38474: 
     {
 #line 1175
     __cil_tmp41 = (atomic_t const   *)(& kgdb_active);
 #line 1175
     tmp___3 = atomic_read(__cil_tmp41);
     }
 #line 1175
     if (pfo_ret__ != tmp___3) {
       {
 #line 1175
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38481: 
   {
 #line 1175
   __cil_tmp42 = (u32 )reg;
 #line 1175
   tmp___4 = i915_read32___6(dev_priv, __cil_tmp42);
   }
   {
 #line 1175
   __cil_tmp43 = tmp___4 & 1073741824U;
 #line 1175
   if (__cil_tmp43 == 0U) {
 #line 1176
     goto ldv_38480;
   } else {
 #line 1178
     goto ldv_38471;
   }
   }
   ldv_38471: ;
 #line 1175
   if (ret__ != 0) {
     {
 #line 1176
     __cil_tmp44 = (unsigned int )pipe;
 #line 1176
     drm_err("intel_enable_transcoder", "failed to enable transcoder %d\n", __cil_tmp44);
     }
   } else {
 
   }
 #line 1177
   return;
 }
 }
 #line 1179 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_disable_transcoder(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   unsigned long timeout__ ;
   unsigned long tmp ;
   int ret__ ;
   struct thread_info *tmp___0 ;
   int pfo_ret__ ;
   int tmp___1 ;
   u32 tmp___2 ;
   bool __cil_tmp12 ;
   bool __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   u32 __cil_tmp17 ;
   u32 __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   long __cil_tmp22 ;
   long __cil_tmp23 ;
   long __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   atomic_t const   *__cil_tmp27 ;
   u32 __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
 
   {
   {
 #line 1186
   __cil_tmp12 = (bool )0;
 #line 1186
   assert_fdi_tx(dev_priv, pipe, __cil_tmp12);
 #line 1187
   __cil_tmp13 = (bool )0;
 #line 1187
   assert_fdi_rx(dev_priv, pipe, __cil_tmp13);
 #line 1190
   assert_pch_ports_disabled(dev_priv, pipe);
 #line 1192
   __cil_tmp14 = (unsigned int )pipe;
 #line 1192
   __cil_tmp15 = __cil_tmp14 * 4096U;
 #line 1192
   __cil_tmp16 = __cil_tmp15 + 983048U;
 #line 1192
   reg = (int )__cil_tmp16;
 #line 1193
   __cil_tmp17 = (u32 )reg;
 #line 1193
   val = i915_read32___6(dev_priv, __cil_tmp17);
 #line 1194
   val = val & 2147483647U;
 #line 1195
   __cil_tmp18 = (u32 )reg;
 #line 1195
   i915_write32___4(dev_priv, __cil_tmp18, val);
 #line 1197
   __cil_tmp19 = (unsigned int const   )50U;
 #line 1197
   __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 1197
   tmp = msecs_to_jiffies(__cil_tmp20);
 #line 1197
   __cil_tmp21 = (unsigned long )jiffies;
 #line 1197
   timeout__ = tmp + __cil_tmp21;
 #line 1197
   ret__ = 0;
   }
 #line 1197
   goto ldv_38508;
   ldv_38507: ;
   {
 #line 1197
   __cil_tmp22 = (long )jiffies;
 #line 1197
   __cil_tmp23 = (long )timeout__;
 #line 1197
   __cil_tmp24 = __cil_tmp23 - __cil_tmp22;
 #line 1197
   if (__cil_tmp24 < 0L) {
 #line 1197
     ret__ = -110;
 #line 1197
     goto ldv_38498;
   } else {
 
   }
   }
   {
 #line 1197
   tmp___0 = current_thread_info();
   }
   {
 #line 1197
   __cil_tmp25 = tmp___0->preempt_count;
 #line 1197
   __cil_tmp26 = __cil_tmp25 & -268435457;
 #line 1197
   if (__cil_tmp26 == 0) {
 #line 1197
     if (1) {
 #line 1197
       goto case_4;
     } else {
 #line 1197
       goto switch_default;
 #line 1197
       if (0) {
 #line 1197
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 1197
         goto ldv_38501;
 #line 1197
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1197
         goto ldv_38501;
         case_4: 
 #line 1197
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1197
         goto ldv_38501;
 #line 1197
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1197
         goto ldv_38501;
         switch_default: 
         {
 #line 1197
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_38501: 
     {
 #line 1197
     __cil_tmp27 = (atomic_t const   *)(& kgdb_active);
 #line 1197
     tmp___1 = atomic_read(__cil_tmp27);
     }
 #line 1197
     if (pfo_ret__ != tmp___1) {
       {
 #line 1197
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38508: 
   {
 #line 1197
   __cil_tmp28 = (u32 )reg;
 #line 1197
   tmp___2 = i915_read32___6(dev_priv, __cil_tmp28);
   }
   {
 #line 1197
   __cil_tmp29 = tmp___2 & 1073741824U;
 #line 1197
   if (__cil_tmp29 != 0U) {
 #line 1198
     goto ldv_38507;
   } else {
 #line 1200
     goto ldv_38498;
   }
   }
   ldv_38498: ;
 #line 1197
   if (ret__ != 0) {
     {
 #line 1198
     drm_err("intel_disable_transcoder", "failed to disable transcoder\n");
     }
   } else {
 
   }
 #line 1199
   return;
 }
 }
 #line 1215 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_enable_pipe(struct drm_i915_private *dev_priv , enum pipe pipe ,
                               bool pch_port ) 
 { int reg ;
   u32 val ;
   struct drm_device *__cil_tmp6 ;
   void *__cil_tmp7 ;
   struct drm_i915_private *__cil_tmp8 ;
   struct intel_device_info  const  *__cil_tmp9 ;
   u8 __cil_tmp10 ;
   unsigned char __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   struct drm_device *__cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   u8 __cil_tmp17 ;
   unsigned char __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   struct drm_device *__cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char *__cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   bool __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   u32 __cil_tmp32 ;
   int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   struct drm_device *__cil_tmp36 ;
   int __cil_tmp37 ;
 
   {
   {
 #line 1226
   __cil_tmp6 = dev_priv->dev;
 #line 1226
   __cil_tmp7 = __cil_tmp6->dev_private;
 #line 1226
   __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
 #line 1226
   __cil_tmp9 = __cil_tmp8->info;
 #line 1226
   __cil_tmp10 = __cil_tmp9->gen;
 #line 1226
   __cil_tmp11 = (unsigned char )__cil_tmp10;
 #line 1226
   __cil_tmp12 = (unsigned int )__cil_tmp11;
 #line 1226
   if (__cil_tmp12 != 5U) {
     {
 #line 1226
     __cil_tmp13 = dev_priv->dev;
 #line 1226
     __cil_tmp14 = __cil_tmp13->dev_private;
 #line 1226
     __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 1226
     __cil_tmp16 = __cil_tmp15->info;
 #line 1226
     __cil_tmp17 = __cil_tmp16->gen;
 #line 1226
     __cil_tmp18 = (unsigned char )__cil_tmp17;
 #line 1226
     __cil_tmp19 = (unsigned int )__cil_tmp18;
 #line 1226
     if (__cil_tmp19 != 6U) {
       {
 #line 1226
       __cil_tmp20 = dev_priv->dev;
 #line 1226
       __cil_tmp21 = __cil_tmp20->dev_private;
 #line 1226
       __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 1226
       __cil_tmp23 = __cil_tmp22->info;
 #line 1226
       __cil_tmp24 = (unsigned char *)__cil_tmp23;
 #line 1226
       __cil_tmp25 = __cil_tmp24 + 2UL;
 #line 1226
       __cil_tmp26 = *__cil_tmp25;
 #line 1226
       __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1226
       if (__cil_tmp27 == 0U) {
         {
 #line 1227
         __cil_tmp28 = (bool )1;
 #line 1227
         assert_pll(dev_priv, pipe, __cil_tmp28);
         }
       } else {
 #line 1226
         goto _L___0;
       }
       }
     } else {
 #line 1226
       goto _L___0;
     }
     }
   } else
   _L___0: 
 #line 1229
   if ((int )pch_port) {
     {
 #line 1231
     assert_fdi_rx_pll_enabled(dev_priv, pipe);
 #line 1232
     assert_fdi_tx_pll_enabled(dev_priv, pipe);
     }
   } else {
 
   }
   }
   {
 #line 1237
   __cil_tmp29 = (unsigned int )pipe;
 #line 1237
   __cil_tmp30 = __cil_tmp29 * 4096U;
 #line 1237
   __cil_tmp31 = __cil_tmp30 + 458760U;
 #line 1237
   reg = (int )__cil_tmp31;
 #line 1238
   __cil_tmp32 = (u32 )reg;
 #line 1238
   val = i915_read32___6(dev_priv, __cil_tmp32);
   }
   {
 #line 1239
   __cil_tmp33 = (int )val;
 #line 1239
   if (__cil_tmp33 < 0) {
 #line 1240
     return;
   } else {
 
   }
   }
   {
 #line 1242
   __cil_tmp34 = (u32 )reg;
 #line 1242
   __cil_tmp35 = val | 2147483648U;
 #line 1242
   i915_write32___4(dev_priv, __cil_tmp34, __cil_tmp35);
 #line 1243
   __cil_tmp36 = dev_priv->dev;
 #line 1243
   __cil_tmp37 = (int )pipe;
 #line 1243
   intel_wait_for_vblank(__cil_tmp36, __cil_tmp37);
   }
 #line 1244
   return;
 }
 }
 #line 1258 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_disable_pipe(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { int reg ;
   u32 val ;
   unsigned int __cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   u32 __cil_tmp11 ;
   int __cil_tmp12 ;
   u32 __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   struct drm_device *__cil_tmp15 ;
   int __cil_tmp16 ;
 
   {
   {
 #line 1268
   assert_planes_disabled(dev_priv, pipe);
   }
   {
 #line 1271
   __cil_tmp5 = (unsigned int )pipe;
 #line 1271
   if (__cil_tmp5 == 0U) {
     {
 #line 1271
     __cil_tmp6 = dev_priv->quirks;
 #line 1271
     __cil_tmp7 = (int )__cil_tmp6;
 #line 1271
     if (__cil_tmp7 & 1) {
 #line 1272
       return;
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1274
   __cil_tmp8 = (unsigned int )pipe;
 #line 1274
   __cil_tmp9 = __cil_tmp8 * 4096U;
 #line 1274
   __cil_tmp10 = __cil_tmp9 + 458760U;
 #line 1274
   reg = (int )__cil_tmp10;
 #line 1275
   __cil_tmp11 = (u32 )reg;
 #line 1275
   val = i915_read32___6(dev_priv, __cil_tmp11);
   }
   {
 #line 1276
   __cil_tmp12 = (int )val;
 #line 1276
   if (__cil_tmp12 >= 0) {
 #line 1277
     return;
   } else {
 
   }
   }
   {
 #line 1279
   __cil_tmp13 = (u32 )reg;
 #line 1279
   __cil_tmp14 = val & 2147483647U;
 #line 1279
   i915_write32___4(dev_priv, __cil_tmp13, __cil_tmp14);
 #line 1280
   __cil_tmp15 = dev_priv->dev;
 #line 1280
   __cil_tmp16 = (int )pipe;
 #line 1280
   intel_wait_for_pipe_off(__cil_tmp15, __cil_tmp16);
   }
 #line 1281
   return;
 }
 }
 #line 1291 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_enable_plane(struct drm_i915_private *dev_priv , enum plane plane ,
                                enum pipe pipe ) 
 { int reg ;
   u32 val ;
   bool __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   u32 __cil_tmp10 ;
   int __cil_tmp11 ;
   u32 __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   struct drm_device *__cil_tmp14 ;
   int __cil_tmp15 ;
 
   {
   {
 #line 1298
   __cil_tmp6 = (bool )1;
 #line 1298
   assert_pipe(dev_priv, pipe, __cil_tmp6);
 #line 1300
   __cil_tmp7 = (unsigned int )plane;
 #line 1300
   __cil_tmp8 = __cil_tmp7 * 4096U;
 #line 1300
   __cil_tmp9 = __cil_tmp8 + 459136U;
 #line 1300
   reg = (int )__cil_tmp9;
 #line 1301
   __cil_tmp10 = (u32 )reg;
 #line 1301
   val = i915_read32___6(dev_priv, __cil_tmp10);
   }
   {
 #line 1302
   __cil_tmp11 = (int )val;
 #line 1302
   if (__cil_tmp11 < 0) {
 #line 1303
     return;
   } else {
 
   }
   }
   {
 #line 1305
   __cil_tmp12 = (u32 )reg;
 #line 1305
   __cil_tmp13 = val | 2147483648U;
 #line 1305
   i915_write32___4(dev_priv, __cil_tmp12, __cil_tmp13);
 #line 1306
   __cil_tmp14 = dev_priv->dev;
 #line 1306
   __cil_tmp15 = (int )pipe;
 #line 1306
   intel_wait_for_vblank(__cil_tmp14, __cil_tmp15);
   }
 #line 1307
   return;
 }
 }
 #line 1313 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_flush_display_plane(struct drm_i915_private *dev_priv , enum plane plane ) 
 { u32 reg ;
   u32 tmp ;
   unsigned int __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
 
   {
   {
 #line 1316
   __cil_tmp5 = (unsigned int )plane;
 #line 1316
   __cil_tmp6 = __cil_tmp5 * 4096U;
 #line 1316
   reg = __cil_tmp6 + 459140U;
 #line 1317
   tmp = i915_read32___6(dev_priv, reg);
 #line 1317
   i915_write32___4(dev_priv, reg, tmp);
   }
 #line 1318
   return;
 }
 }
 #line 1328 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_disable_plane(struct drm_i915_private *dev_priv , enum plane plane ,
                                 enum pipe pipe ) 
 { int reg ;
   u32 val ;
   unsigned int __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   u32 __cil_tmp9 ;
   int __cil_tmp10 ;
   u32 __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   struct drm_device *__cil_tmp13 ;
   int __cil_tmp14 ;
 
   {
   {
 #line 1334
   __cil_tmp6 = (unsigned int )plane;
 #line 1334
   __cil_tmp7 = __cil_tmp6 * 4096U;
 #line 1334
   __cil_tmp8 = __cil_tmp7 + 459136U;
 #line 1334
   reg = (int )__cil_tmp8;
 #line 1335
   __cil_tmp9 = (u32 )reg;
 #line 1335
   val = i915_read32___6(dev_priv, __cil_tmp9);
   }
   {
 #line 1336
   __cil_tmp10 = (int )val;
 #line 1336
   if (__cil_tmp10 >= 0) {
 #line 1337
     return;
   } else {
 
   }
   }
   {
 #line 1339
   __cil_tmp11 = (u32 )reg;
 #line 1339
   __cil_tmp12 = val & 2147483647U;
 #line 1339
   i915_write32___4(dev_priv, __cil_tmp11, __cil_tmp12);
 #line 1340
   intel_flush_display_plane(dev_priv, plane);
 #line 1341
   __cil_tmp13 = dev_priv->dev;
 #line 1341
   __cil_tmp14 = (int )pipe;
 #line 1341
   intel_wait_for_vblank(__cil_tmp13, __cil_tmp14);
   }
 #line 1342
   return;
 }
 }
 #line 1344 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void disable_pch_dp(struct drm_i915_private *dev_priv , enum pipe pipe , int reg ) 
 { u32 val ;
   u32 tmp ;
   u32 __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   u32 __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
 
   {
   {
 #line 1347
   __cil_tmp6 = (u32 )reg;
 #line 1347
   tmp = i915_read32___6(dev_priv, __cil_tmp6);
 #line 1347
   val = tmp;
   }
   {
 #line 1348
   __cil_tmp7 = (unsigned int )pipe;
 #line 1348
   __cil_tmp8 = __cil_tmp7 << 30;
 #line 1348
   __cil_tmp9 = __cil_tmp8 | 2147483648U;
 #line 1348
   __cil_tmp10 = val & 3221225472U;
 #line 1348
   if (__cil_tmp10 == __cil_tmp9) {
     {
 #line 1349
     __cil_tmp11 = (u32 )reg;
 #line 1349
     __cil_tmp12 = val & 2147483647U;
 #line 1349
     i915_write32___4(dev_priv, __cil_tmp11, __cil_tmp12);
     }
   } else {
 
   }
   }
 #line 1350
   return;
 }
 }
 #line 1352 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void disable_pch_hdmi(struct drm_i915_private *dev_priv , enum pipe pipe ,
                              int reg ) 
 { u32 val ;
   u32 tmp ;
   u32 __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   u32 __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
 
   {
   {
 #line 1355
   __cil_tmp6 = (u32 )reg;
 #line 1355
   tmp = i915_read32___6(dev_priv, __cil_tmp6);
 #line 1355
   val = tmp;
   }
   {
 #line 1356
   __cil_tmp7 = (unsigned int )pipe;
 #line 1356
   __cil_tmp8 = __cil_tmp7 << 30;
 #line 1356
   __cil_tmp9 = __cil_tmp8 | 2147483648U;
 #line 1356
   __cil_tmp10 = val & 3221225472U;
 #line 1356
   if (__cil_tmp10 == __cil_tmp9) {
     {
 #line 1357
     __cil_tmp11 = (u32 )reg;
 #line 1357
     __cil_tmp12 = val & 2147483647U;
 #line 1357
     i915_write32___4(dev_priv, __cil_tmp11, __cil_tmp12);
     }
   } else {
 
   }
   }
 #line 1358
   return;
 }
 }
 #line 1361 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv , enum pipe pipe ) 
 { u32 reg ;
   u32 val ;
   unsigned int __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   unsigned int __cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   void *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
 
   {
   {
 #line 1366
   val = i915_read32___6(dev_priv, 815620U);
 #line 1367
   __cil_tmp5 = val | 2882338816U;
 #line 1367
   i915_write32___4(dev_priv, 815620U, __cil_tmp5);
 #line 1369
   disable_pch_dp(dev_priv, pipe, 934144);
 #line 1370
   disable_pch_dp(dev_priv, pipe, 934400);
 #line 1371
   disable_pch_dp(dev_priv, pipe, 934656);
 #line 1373
   reg = 921856U;
 #line 1374
   val = i915_read32___6(dev_priv, reg);
   }
   {
 #line 1375
   __cil_tmp6 = (unsigned int )pipe;
 #line 1375
   __cil_tmp7 = __cil_tmp6 << 30;
 #line 1375
   __cil_tmp8 = __cil_tmp7 | 2147483648U;
 #line 1375
   __cil_tmp9 = val & 3221225472U;
 #line 1375
   if (__cil_tmp9 == __cil_tmp8) {
     {
 #line 1376
     __cil_tmp10 = val & 2147483647U;
 #line 1376
     i915_write32___4(dev_priv, reg, __cil_tmp10);
     }
   } else {
 
   }
   }
   {
 #line 1378
   reg = 921984U;
 #line 1379
   val = i915_read32___6(dev_priv, reg);
   }
   {
 #line 1380
   __cil_tmp11 = (unsigned int )pipe;
 #line 1380
   __cil_tmp12 = __cil_tmp11 << 30;
 #line 1380
   __cil_tmp13 = __cil_tmp12 | 2147483648U;
 #line 1380
   __cil_tmp14 = val & 3221225472U;
 #line 1380
   if (__cil_tmp14 == __cil_tmp13) {
     {
 #line 1381
     __cil_tmp15 = val & 2147483647U;
 #line 1381
     i915_write32___4(dev_priv, reg, __cil_tmp15);
 #line 1382
     __cil_tmp16 = (unsigned long )reg;
 #line 1382
     __cil_tmp17 = dev_priv->regs;
 #line 1382
     __cil_tmp18 = (void const volatile   *)__cil_tmp17;
 #line 1382
     __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
 #line 1382
     readl(__cil_tmp19);
 #line 1383
     __const_udelay(429500UL);
     }
   } else {
 
   }
   }
   {
 #line 1386
   disable_pch_hdmi(dev_priv, pipe, 921920);
 #line 1387
   disable_pch_hdmi(dev_priv, pipe, 921936);
 #line 1388
   disable_pch_hdmi(dev_priv, pipe, 921952);
   }
 #line 1389
   return;
 }
 }
 #line 1391 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i8xx_enable_fbc(struct drm_crtc *crtc , unsigned long interval ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct drm_framebuffer *fb ;
   struct intel_framebuffer *intel_fb ;
   struct drm_framebuffer  const  *__mptr ;
   struct drm_i915_gem_object *obj ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr___0 ;
   int plane ;
   int i ;
   u32 fbc_ctl ;
   u32 fbc_ctl2 ;
   u32 tmp ;
   void *__cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   int __cil_tmp20 ;
   signed char __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   enum plane __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   signed char __cil_tmp35 ;
   enum plane __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   u32 __cil_tmp40 ;
   unsigned char *__cil_tmp41 ;
   unsigned char *__cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   int __cil_tmp45 ;
   u32 __cil_tmp46 ;
   void *__cil_tmp47 ;
   struct drm_i915_private *__cil_tmp48 ;
   struct intel_device_info  const  *__cil_tmp49 ;
   unsigned char *__cil_tmp50 ;
   unsigned char *__cil_tmp51 ;
   unsigned char __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   u32 __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   u32 __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned char *__cil_tmp61 ;
   unsigned char *__cil_tmp62 ;
   unsigned char __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   int __cil_tmp65 ;
   u32 __cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
 
   {
 #line 1393
   dev = crtc->dev;
 #line 1394
   __cil_tmp16 = dev->dev_private;
 #line 1394
   dev_priv = (struct drm_i915_private *)__cil_tmp16;
 #line 1395
   fb = crtc->fb;
 #line 1396
   __mptr = (struct drm_framebuffer  const  *)fb;
 #line 1396
   intel_fb = (struct intel_framebuffer *)__mptr;
 #line 1397
   obj = intel_fb->obj;
 #line 1398
   __mptr___0 = (struct drm_crtc  const  *)crtc;
 #line 1398
   intel_crtc = (struct intel_crtc *)__mptr___0;
   {
 #line 1402
   __cil_tmp17 = dev_priv->cfb_pitch;
 #line 1402
   __cil_tmp18 = fb->pitch;
 #line 1402
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 1402
   if (__cil_tmp19 == __cil_tmp17) {
     {
 #line 1402
     __cil_tmp20 = dev_priv->cfb_fence;
 #line 1402
     __cil_tmp21 = obj->fence_reg;
 #line 1402
     __cil_tmp22 = (int )__cil_tmp21;
 #line 1402
     if (__cil_tmp22 == __cil_tmp20) {
       {
 #line 1402
       __cil_tmp23 = dev_priv->cfb_plane;
 #line 1402
       __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 1402
       __cil_tmp25 = intel_crtc->plane;
 #line 1402
       __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 1402
       if (__cil_tmp26 == __cil_tmp24) {
         {
 #line 1402
         tmp = i915_read32___6(dev_priv, 12808U);
         }
         {
 #line 1402
         __cil_tmp27 = (int )tmp;
 #line 1402
         if (__cil_tmp27 < 0) {
 #line 1406
           return;
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 1408
   i8xx_disable_fbc(dev);
 #line 1410
   __cil_tmp28 = dev_priv->cfb_size;
 #line 1410
   dev_priv->cfb_pitch = __cil_tmp28 / 1536UL;
   }
   {
 #line 1412
   __cil_tmp29 = dev_priv->cfb_pitch;
 #line 1412
   __cil_tmp30 = fb->pitch;
 #line 1412
   __cil_tmp31 = (unsigned long )__cil_tmp30;
 #line 1412
   if (__cil_tmp31 < __cil_tmp29) {
 #line 1413
     __cil_tmp32 = fb->pitch;
 #line 1413
     dev_priv->cfb_pitch = (unsigned long )__cil_tmp32;
   } else {
 
   }
   }
 #line 1416
   __cil_tmp33 = dev_priv->cfb_pitch;
 #line 1416
   __cil_tmp34 = __cil_tmp33 / 64UL;
 #line 1416
   dev_priv->cfb_pitch = __cil_tmp34 - 1UL;
 #line 1417
   __cil_tmp35 = obj->fence_reg;
 #line 1417
   dev_priv->cfb_fence = (int )__cil_tmp35;
 #line 1418
   __cil_tmp36 = intel_crtc->plane;
 #line 1418
   dev_priv->cfb_plane = (int )__cil_tmp36;
 #line 1419
   __cil_tmp37 = dev_priv->cfb_plane;
 #line 1419
   plane = __cil_tmp37 != 0;
 #line 1422
   i = 0;
 #line 1422
   goto ldv_38580;
   ldv_38579: 
   {
 #line 1423
   __cil_tmp38 = i + 3264;
 #line 1423
   __cil_tmp39 = __cil_tmp38 * 4;
 #line 1423
   __cil_tmp40 = (u32 )__cil_tmp39;
 #line 1423
   i915_write32___4(dev_priv, __cil_tmp40, 0U);
 #line 1422
   i = i + 1;
   }
   ldv_38580: ;
 #line 1422
   if (i <= 48) {
 #line 1423
     goto ldv_38579;
   } else {
 #line 1425
     goto ldv_38581;
   }
   ldv_38581: 
 #line 1426
   fbc_ctl2 = (u32 )plane;
   {
 #line 1427
   __cil_tmp41 = (unsigned char *)obj;
 #line 1427
   __cil_tmp42 = __cil_tmp41 + 225UL;
 #line 1427
   __cil_tmp43 = *__cil_tmp42;
 #line 1427
   __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 1427
   if (__cil_tmp44 != 0U) {
 #line 1428
     fbc_ctl2 = fbc_ctl2 | 2U;
   } else {
 
   }
   }
   {
 #line 1429
   i915_write32___4(dev_priv, 12820U, fbc_ctl2);
 #line 1430
   __cil_tmp45 = crtc->y;
 #line 1430
   __cil_tmp46 = (u32 )__cil_tmp45;
 #line 1430
   i915_write32___4(dev_priv, 12827U, __cil_tmp46);
 #line 1433
   fbc_ctl = 3221225472U;
   }
   {
 #line 1434
   __cil_tmp47 = dev->dev_private;
 #line 1434
   __cil_tmp48 = (struct drm_i915_private *)__cil_tmp47;
 #line 1434
   __cil_tmp49 = __cil_tmp48->info;
 #line 1434
   __cil_tmp50 = (unsigned char *)__cil_tmp49;
 #line 1434
   __cil_tmp51 = __cil_tmp50 + 1UL;
 #line 1434
   __cil_tmp52 = *__cil_tmp51;
 #line 1434
   __cil_tmp53 = (unsigned int )__cil_tmp52;
 #line 1434
   if (__cil_tmp53 != 0U) {
 #line 1435
     fbc_ctl = fbc_ctl | 8192U;
   } else {
 
   }
   }
 #line 1436
   __cil_tmp54 = dev_priv->cfb_pitch;
 #line 1436
   __cil_tmp55 = (u32 )__cil_tmp54;
 #line 1436
   __cil_tmp56 = __cil_tmp55 & 255U;
 #line 1436
   __cil_tmp57 = __cil_tmp56 << 5U;
 #line 1436
   fbc_ctl = __cil_tmp57 | fbc_ctl;
 #line 1437
   __cil_tmp58 = (u32 )interval;
 #line 1437
   __cil_tmp59 = __cil_tmp58 & 12287U;
 #line 1437
   __cil_tmp60 = __cil_tmp59 << 16U;
 #line 1437
   fbc_ctl = __cil_tmp60 | fbc_ctl;
   {
 #line 1438
   __cil_tmp61 = (unsigned char *)obj;
 #line 1438
   __cil_tmp62 = __cil_tmp61 + 225UL;
 #line 1438
   __cil_tmp63 = *__cil_tmp62;
 #line 1438
   __cil_tmp64 = (unsigned int )__cil_tmp63;
 #line 1438
   if (__cil_tmp64 != 0U) {
 #line 1439
     __cil_tmp65 = dev_priv->cfb_fence;
 #line 1439
     __cil_tmp66 = (u32 )__cil_tmp65;
 #line 1439
     fbc_ctl = __cil_tmp66 | fbc_ctl;
   } else {
 
   }
   }
   {
 #line 1440
   i915_write32___4(dev_priv, 12808U, fbc_ctl);
 #line 1442
   __cil_tmp67 = dev_priv->cfb_pitch;
 #line 1442
   __cil_tmp68 = crtc->y;
 #line 1442
   __cil_tmp69 = dev_priv->cfb_plane;
 #line 1442
   drm_ut_debug_printk(4U, "drm", "i8xx_enable_fbc", "enabled FBC, pitch %ld, yoff %d, plane %d, ",
                       __cil_tmp67, __cil_tmp68, __cil_tmp69);
   }
 #line 1443
   return;
 }
 }
 #line 1446 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void i8xx_disable_fbc(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 fbc_ctl ;
   unsigned long timeout__ ;
   unsigned long tmp ;
   int ret__ ;
   struct thread_info *tmp___0 ;
   int pfo_ret__ ;
   int tmp___1 ;
   u32 tmp___2 ;
   void *__cil_tmp11 ;
   int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   unsigned int __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   long __cil_tmp16 ;
   long __cil_tmp17 ;
   long __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   atomic_t const   *__cil_tmp21 ;
   int __cil_tmp22 ;
 
   {
   {
 #line 1448
   __cil_tmp11 = dev->dev_private;
 #line 1448
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 1452
   fbc_ctl = i915_read32___6(dev_priv, 12808U);
   }
   {
 #line 1453
   __cil_tmp12 = (int )fbc_ctl;
 #line 1453
   if (__cil_tmp12 >= 0) {
 #line 1454
     return;
   } else {
 
   }
   }
   {
 #line 1456
   fbc_ctl = fbc_ctl & 2147483647U;
 #line 1457
   i915_write32___4(dev_priv, 12808U, fbc_ctl);
 #line 1460
   __cil_tmp13 = (unsigned int const   )10U;
 #line 1460
   __cil_tmp14 = (unsigned int )__cil_tmp13;
 #line 1460
   tmp = msecs_to_jiffies(__cil_tmp14);
 #line 1460
   __cil_tmp15 = (unsigned long )jiffies;
 #line 1460
   timeout__ = tmp + __cil_tmp15;
 #line 1460
   ret__ = 0;
   }
 #line 1460
   goto ldv_38606;
   ldv_38605: ;
   {
 #line 1460
   __cil_tmp16 = (long )jiffies;
 #line 1460
   __cil_tmp17 = (long )timeout__;
 #line 1460
   __cil_tmp18 = __cil_tmp17 - __cil_tmp16;
 #line 1460
   if (__cil_tmp18 < 0L) {
 #line 1460
     ret__ = -110;
 #line 1460
     goto ldv_38596;
   } else {
 
   }
   }
   {
 #line 1460
   tmp___0 = current_thread_info();
   }
   {
 #line 1460
   __cil_tmp19 = tmp___0->preempt_count;
 #line 1460
   __cil_tmp20 = __cil_tmp19 & -268435457;
 #line 1460
   if (__cil_tmp20 == 0) {
 #line 1460
     if (1) {
 #line 1460
       goto case_4;
     } else {
 #line 1460
       goto switch_default;
 #line 1460
       if (0) {
 #line 1460
         __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 1460
         goto ldv_38599;
 #line 1460
         __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1460
         goto ldv_38599;
         case_4: 
 #line 1460
         __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1460
         goto ldv_38599;
 #line 1460
         __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1460
         goto ldv_38599;
         switch_default: 
         {
 #line 1460
         __bad_percpu_size();
         }
       } else {
 
       }
     }
     ldv_38599: 
     {
 #line 1460
     __cil_tmp21 = (atomic_t const   *)(& kgdb_active);
 #line 1460
     tmp___1 = atomic_read(__cil_tmp21);
     }
 #line 1460
     if (pfo_ret__ != tmp___1) {
       {
 #line 1460
       msleep(1U);
       }
     } else {
 
     }
   } else {
 
   }
   }
   ldv_38606: 
   {
 #line 1460
   tmp___2 = i915_read32___6(dev_priv, 12816U);
   }
   {
 #line 1460
   __cil_tmp22 = (int )tmp___2;
 #line 1460
   if (__cil_tmp22 < 0) {
 #line 1461
     goto ldv_38605;
   } else {
 #line 1463
     goto ldv_38596;
   }
   }
   ldv_38596: ;
 #line 1460
   if (ret__ != 0) {
     {
 #line 1461
     drm_ut_debug_printk(4U, "drm", "i8xx_disable_fbc", "FBC idle timed out\n");
     }
 #line 1462
     return;
   } else {
 
   }
   {
 #line 1465
   drm_ut_debug_printk(4U, "drm", "i8xx_disable_fbc", "disabled FBC\n");
   }
 #line 1466
   return;
 }
 }
 #line 1468 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool i8xx_fbc_enabled(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   void *__cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
 
   {
   {
 #line 1470
   __cil_tmp4 = dev->dev_private;
 #line 1470
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1472
   tmp = i915_read32___6(dev_priv, 12808U);
   }
   {
 #line 1472
   __cil_tmp5 = tmp & 2147483648U;
 #line 1472
   __cil_tmp6 = __cil_tmp5 != 0U;
 #line 1472
   return ((bool )__cil_tmp6);
   }
 }
 }
 #line 1475 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void g4x_enable_fbc(struct drm_crtc *crtc , unsigned long interval ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct drm_framebuffer *fb ;
   struct intel_framebuffer *intel_fb ;
   struct drm_framebuffer  const  *__mptr ;
   struct drm_i915_gem_object *obj ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr___0 ;
   int plane ;
   int tmp ;
   unsigned long stall_watermark ;
   u32 dpfc_ctl ;
   u32 tmp___0 ;
   void *__cil_tmp16 ;
   enum plane __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   int __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   signed char __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   enum plane __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   enum pipe __cil_tmp34 ;
   int __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   signed char __cil_tmp38 ;
   enum plane __cil_tmp39 ;
   int __cil_tmp40 ;
   unsigned char *__cil_tmp41 ;
   unsigned char *__cil_tmp42 ;
   unsigned char __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   int __cil_tmp45 ;
   u32 __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   u32 __cil_tmp48 ;
   u32 __cil_tmp49 ;
   u32 __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   int __cil_tmp53 ;
   u32 __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   enum plane __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
 
   {
 #line 1477
   dev = crtc->dev;
 #line 1478
   __cil_tmp16 = dev->dev_private;
 #line 1478
   dev_priv = (struct drm_i915_private *)__cil_tmp16;
 #line 1479
   fb = crtc->fb;
 #line 1480
   __mptr = (struct drm_framebuffer  const  *)fb;
 #line 1480
   intel_fb = (struct intel_framebuffer *)__mptr;
 #line 1481
   obj = intel_fb->obj;
 #line 1482
   __mptr___0 = (struct drm_crtc  const  *)crtc;
 #line 1482
   intel_crtc = (struct intel_crtc *)__mptr___0;
   {
 #line 1483
   __cil_tmp17 = intel_crtc->plane;
 #line 1483
   __cil_tmp18 = (unsigned int )__cil_tmp17;
 #line 1483
   if (__cil_tmp18 == 0U) {
 #line 1483
     tmp = 0;
   } else {
 #line 1483
     tmp = 1073741824;
   }
   }
   {
 #line 1483
   plane = tmp;
 #line 1484
   stall_watermark = 200UL;
 #line 1487
   dpfc_ctl = i915_read32___6(dev_priv, 12808U);
   }
   {
 #line 1488
   __cil_tmp19 = (int )dpfc_ctl;
 #line 1488
   if (__cil_tmp19 < 0) {
     {
 #line 1489
     __cil_tmp20 = dev_priv->cfb_pitch;
 #line 1489
     __cil_tmp21 = __cil_tmp20 / 64UL;
 #line 1489
     __cil_tmp22 = __cil_tmp21 - 1UL;
 #line 1489
     __cil_tmp23 = dev_priv->cfb_pitch;
 #line 1489
     if (__cil_tmp23 == __cil_tmp22) {
       {
 #line 1489
       __cil_tmp24 = obj->fence_reg;
 #line 1489
       __cil_tmp25 = (int )__cil_tmp24;
 #line 1489
       __cil_tmp26 = dev_priv->cfb_fence;
 #line 1489
       if (__cil_tmp26 == __cil_tmp25) {
         {
 #line 1489
         __cil_tmp27 = intel_crtc->plane;
 #line 1489
         __cil_tmp28 = (unsigned int )__cil_tmp27;
 #line 1489
         __cil_tmp29 = dev_priv->cfb_plane;
 #line 1489
         __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 1489
         if (__cil_tmp30 == __cil_tmp28) {
           {
 #line 1489
           __cil_tmp31 = crtc->y;
 #line 1489
           __cil_tmp32 = dev_priv->cfb_y;
 #line 1489
           if (__cil_tmp32 == __cil_tmp31) {
 #line 1493
             return;
           } else {
 
           }
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
     {
 #line 1495
     __cil_tmp33 = dpfc_ctl & 2147483647U;
 #line 1495
     i915_write32___4(dev_priv, 12808U, __cil_tmp33);
 #line 1496
     __cil_tmp34 = intel_crtc->pipe;
 #line 1496
     __cil_tmp35 = (int )__cil_tmp34;
 #line 1496
     intel_wait_for_vblank(dev, __cil_tmp35);
     }
   } else {
 
   }
   }
 #line 1499
   __cil_tmp36 = dev_priv->cfb_pitch;
 #line 1499
   __cil_tmp37 = __cil_tmp36 / 64UL;
 #line 1499
   dev_priv->cfb_pitch = __cil_tmp37 - 1UL;
 #line 1500
   __cil_tmp38 = obj->fence_reg;
 #line 1500
   dev_priv->cfb_fence = (int )__cil_tmp38;
 #line 1501
   __cil_tmp39 = intel_crtc->plane;
 #line 1501
   dev_priv->cfb_plane = (int )__cil_tmp39;
 #line 1502
   dev_priv->cfb_y = crtc->y;
 #line 1504
   __cil_tmp40 = plane | 1024;
 #line 1504
   dpfc_ctl = (u32 )__cil_tmp40;
   {
 #line 1505
   __cil_tmp41 = (unsigned char *)obj;
 #line 1505
   __cil_tmp42 = __cil_tmp41 + 225UL;
 #line 1505
   __cil_tmp43 = *__cil_tmp42;
 #line 1505
   __cil_tmp44 = (unsigned int )__cil_tmp43;
 #line 1505
   if (__cil_tmp44 != 0U) {
     {
 #line 1506
     __cil_tmp45 = dev_priv->cfb_fence;
 #line 1506
     __cil_tmp46 = (u32 )__cil_tmp45;
 #line 1506
     __cil_tmp47 = __cil_tmp46 | dpfc_ctl;
 #line 1506
     dpfc_ctl = __cil_tmp47 | 536870912U;
 #line 1507
     i915_write32___4(dev_priv, 12836U, 2147483648U);
     }
   } else {
     {
 #line 1509
     i915_write32___4(dev_priv, 12836U, 2147483647U);
     }
   }
   }
   {
 #line 1512
   __cil_tmp48 = (u32 )interval;
 #line 1512
   __cil_tmp49 = (u32 )stall_watermark;
 #line 1512
   __cil_tmp50 = __cil_tmp49 << 16U;
 #line 1512
   __cil_tmp51 = __cil_tmp50 | __cil_tmp48;
 #line 1512
   __cil_tmp52 = __cil_tmp51 | 134217728U;
 #line 1512
   i915_write32___4(dev_priv, 12812U, __cil_tmp52);
 #line 1515
   __cil_tmp53 = crtc->y;
 #line 1515
   __cil_tmp54 = (u32 )__cil_tmp53;
 #line 1515
   i915_write32___4(dev_priv, 12824U, __cil_tmp54);
 #line 1518
   tmp___0 = i915_read32___6(dev_priv, 12808U);
 #line 1518
   __cil_tmp55 = tmp___0 | 2147483648U;
 #line 1518
   i915_write32___4(dev_priv, 12808U, __cil_tmp55);
 #line 1520
   __cil_tmp56 = intel_crtc->plane;
 #line 1520
   __cil_tmp57 = (unsigned int )__cil_tmp56;
 #line 1520
   drm_ut_debug_printk(4U, "drm", "g4x_enable_fbc", "enabled fbc on plane %d\n", __cil_tmp57);
   }
 #line 1521
   return;
 }
 }
 #line 1523 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void g4x_disable_fbc(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 dpfc_ctl ;
   void *__cil_tmp4 ;
   int __cil_tmp5 ;
 
   {
   {
 #line 1525
   __cil_tmp4 = dev->dev_private;
 #line 1525
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1529
   dpfc_ctl = i915_read32___6(dev_priv, 12808U);
   }
   {
 #line 1530
   __cil_tmp5 = (int )dpfc_ctl;
 #line 1530
   if (__cil_tmp5 < 0) {
     {
 #line 1531
     dpfc_ctl = dpfc_ctl & 2147483647U;
 #line 1532
     i915_write32___4(dev_priv, 12808U, dpfc_ctl);
 #line 1534
     drm_ut_debug_printk(4U, "drm", "g4x_disable_fbc", "disabled FBC\n");
     }
   } else {
 
   }
   }
 #line 1536
   return;
 }
 }
 #line 1538 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool g4x_fbc_enabled(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   void *__cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
 
   {
   {
 #line 1540
   __cil_tmp4 = dev->dev_private;
 #line 1540
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1542
   tmp = i915_read32___6(dev_priv, 12808U);
   }
   {
 #line 1542
   __cil_tmp5 = tmp & 2147483648U;
 #line 1542
   __cil_tmp6 = __cil_tmp5 != 0U;
 #line 1542
   return ((bool )__cil_tmp6);
   }
 }
 }
 #line 1545 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void sandybridge_blit_fbc_update(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 blt_ecoskpd ;
   void *__cil_tmp4 ;
   void *__cil_tmp5 ;
   void const volatile   *__cil_tmp6 ;
   void const volatile   *__cil_tmp7 ;
 
   {
   {
 #line 1547
   __cil_tmp4 = dev->dev_private;
 #line 1547
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1551
   gen6_gt_force_wake_get(dev_priv);
 #line 1552
   blt_ecoskpd = i915_read32___6(dev_priv, 139728U);
 #line 1553
   blt_ecoskpd = blt_ecoskpd | 524288U;
 #line 1555
   i915_write32___4(dev_priv, 139728U, blt_ecoskpd);
 #line 1556
   blt_ecoskpd = blt_ecoskpd | 8U;
 #line 1557
   i915_write32___4(dev_priv, 139728U, blt_ecoskpd);
 #line 1558
   blt_ecoskpd = blt_ecoskpd & 4294443007U;
 #line 1560
   i915_write32___4(dev_priv, 139728U, blt_ecoskpd);
 #line 1561
   __cil_tmp5 = dev_priv->regs;
 #line 1561
   __cil_tmp6 = (void const volatile   *)__cil_tmp5;
 #line 1561
   __cil_tmp7 = __cil_tmp6 + 139728U;
 #line 1561
   readl(__cil_tmp7);
 #line 1562
   gen6_gt_force_wake_put(dev_priv);
   }
 #line 1563
   return;
 }
 }
 #line 1565 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_enable_fbc(struct drm_crtc *crtc , unsigned long interval ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct drm_framebuffer *fb ;
   struct intel_framebuffer *intel_fb ;
   struct drm_framebuffer  const  *__mptr ;
   struct drm_i915_gem_object *obj ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr___0 ;
   int plane ;
   int tmp ;
   unsigned long stall_watermark ;
   u32 dpfc_ctl ;
   void *__cil_tmp15 ;
   enum plane __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   signed char __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   enum plane __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   uint32_t __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   enum pipe __cil_tmp36 ;
   int __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   signed char __cil_tmp40 ;
   enum plane __cil_tmp41 ;
   uint32_t __cil_tmp42 ;
   u32 __cil_tmp43 ;
   unsigned char *__cil_tmp44 ;
   unsigned char *__cil_tmp45 ;
   unsigned char __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   int __cil_tmp48 ;
   u32 __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   u32 __cil_tmp51 ;
   u32 __cil_tmp52 ;
   u32 __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   int __cil_tmp56 ;
   u32 __cil_tmp57 ;
   uint32_t __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   void *__cil_tmp61 ;
   struct drm_i915_private *__cil_tmp62 ;
   struct intel_device_info  const  *__cil_tmp63 ;
   u8 __cil_tmp64 ;
   unsigned char __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   int __cil_tmp67 ;
   int __cil_tmp68 ;
   u32 __cil_tmp69 ;
   int __cil_tmp70 ;
   u32 __cil_tmp71 ;
   enum plane __cil_tmp72 ;
   unsigned int __cil_tmp73 ;
 
   {
 #line 1567
   dev = crtc->dev;
 #line 1568
   __cil_tmp15 = dev->dev_private;
 #line 1568
   dev_priv = (struct drm_i915_private *)__cil_tmp15;
 #line 1569
   fb = crtc->fb;
 #line 1570
   __mptr = (struct drm_framebuffer  const  *)fb;
 #line 1570
   intel_fb = (struct intel_framebuffer *)__mptr;
 #line 1571
   obj = intel_fb->obj;
 #line 1572
   __mptr___0 = (struct drm_crtc  const  *)crtc;
 #line 1572
   intel_crtc = (struct intel_crtc *)__mptr___0;
   {
 #line 1573
   __cil_tmp16 = intel_crtc->plane;
 #line 1573
   __cil_tmp17 = (unsigned int )__cil_tmp16;
 #line 1573
   if (__cil_tmp17 == 0U) {
 #line 1573
     tmp = 0;
   } else {
 #line 1573
     tmp = 1073741824;
   }
   }
   {
 #line 1573
   plane = tmp;
 #line 1574
   stall_watermark = 200UL;
 #line 1577
   dpfc_ctl = i915_read32___6(dev_priv, 274952U);
   }
   {
 #line 1578
   __cil_tmp18 = (int )dpfc_ctl;
 #line 1578
   if (__cil_tmp18 < 0) {
     {
 #line 1579
     __cil_tmp19 = dev_priv->cfb_pitch;
 #line 1579
     __cil_tmp20 = __cil_tmp19 / 64UL;
 #line 1579
     __cil_tmp21 = __cil_tmp20 - 1UL;
 #line 1579
     __cil_tmp22 = dev_priv->cfb_pitch;
 #line 1579
     if (__cil_tmp22 == __cil_tmp21) {
       {
 #line 1579
       __cil_tmp23 = obj->fence_reg;
 #line 1579
       __cil_tmp24 = (int )__cil_tmp23;
 #line 1579
       __cil_tmp25 = dev_priv->cfb_fence;
 #line 1579
       if (__cil_tmp25 == __cil_tmp24) {
         {
 #line 1579
         __cil_tmp26 = intel_crtc->plane;
 #line 1579
         __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1579
         __cil_tmp28 = dev_priv->cfb_plane;
 #line 1579
         __cil_tmp29 = (unsigned int )__cil_tmp28;
 #line 1579
         if (__cil_tmp29 == __cil_tmp27) {
           {
 #line 1579
           __cil_tmp30 = obj->gtt_offset;
 #line 1579
           __cil_tmp31 = (unsigned long )__cil_tmp30;
 #line 1579
           __cil_tmp32 = dev_priv->cfb_offset;
 #line 1579
           if (__cil_tmp32 == __cil_tmp31) {
             {
 #line 1579
             __cil_tmp33 = crtc->y;
 #line 1579
             __cil_tmp34 = dev_priv->cfb_y;
 #line 1579
             if (__cil_tmp34 == __cil_tmp33) {
 #line 1584
               return;
             } else {
 
             }
             }
           } else {
 
           }
           }
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
     {
 #line 1586
     __cil_tmp35 = dpfc_ctl & 2147483647U;
 #line 1586
     i915_write32___4(dev_priv, 274952U, __cil_tmp35);
 #line 1587
     __cil_tmp36 = intel_crtc->pipe;
 #line 1587
     __cil_tmp37 = (int )__cil_tmp36;
 #line 1587
     intel_wait_for_vblank(dev, __cil_tmp37);
     }
   } else {
 
   }
   }
 #line 1590
   __cil_tmp38 = dev_priv->cfb_pitch;
 #line 1590
   __cil_tmp39 = __cil_tmp38 / 64UL;
 #line 1590
   dev_priv->cfb_pitch = __cil_tmp39 - 1UL;
 #line 1591
   __cil_tmp40 = obj->fence_reg;
 #line 1591
   dev_priv->cfb_fence = (int )__cil_tmp40;
 #line 1592
   __cil_tmp41 = intel_crtc->plane;
 #line 1592
   dev_priv->cfb_plane = (int )__cil_tmp41;
 #line 1593
   __cil_tmp42 = obj->gtt_offset;
 #line 1593
   dev_priv->cfb_offset = (unsigned long )__cil_tmp42;
 #line 1594
   dev_priv->cfb_y = crtc->y;
 #line 1596
   dpfc_ctl = dpfc_ctl & 536870656U;
 #line 1597
   __cil_tmp43 = (u32 )plane;
 #line 1597
   dpfc_ctl = dpfc_ctl | __cil_tmp43;
   {
 #line 1598
   __cil_tmp44 = (unsigned char *)obj;
 #line 1598
   __cil_tmp45 = __cil_tmp44 + 225UL;
 #line 1598
   __cil_tmp46 = *__cil_tmp45;
 #line 1598
   __cil_tmp47 = (unsigned int )__cil_tmp46;
 #line 1598
   if (__cil_tmp47 != 0U) {
     {
 #line 1599
     __cil_tmp48 = dev_priv->cfb_fence;
 #line 1599
     __cil_tmp49 = (u32 )__cil_tmp48;
 #line 1599
     __cil_tmp50 = __cil_tmp49 | dpfc_ctl;
 #line 1599
     dpfc_ctl = __cil_tmp50 | 536870912U;
 #line 1600
     i915_write32___4(dev_priv, 274980U, 2147483648U);
     }
   } else {
     {
 #line 1602
     i915_write32___4(dev_priv, 274980U, 2147483647U);
     }
   }
   }
   {
 #line 1605
   __cil_tmp51 = (u32 )interval;
 #line 1605
   __cil_tmp52 = (u32 )stall_watermark;
 #line 1605
   __cil_tmp53 = __cil_tmp52 << 16U;
 #line 1605
   __cil_tmp54 = __cil_tmp53 | __cil_tmp51;
 #line 1605
   __cil_tmp55 = __cil_tmp54 | 134217728U;
 #line 1605
   i915_write32___4(dev_priv, 274956U, __cil_tmp55);
 #line 1608
   __cil_tmp56 = crtc->y;
 #line 1608
   __cil_tmp57 = (u32 )__cil_tmp56;
 #line 1608
   i915_write32___4(dev_priv, 274968U, __cil_tmp57);
 #line 1609
   __cil_tmp58 = obj->gtt_offset;
 #line 1609
   __cil_tmp59 = __cil_tmp58 | 1U;
 #line 1609
   i915_write32___4(dev_priv, 8488U, __cil_tmp59);
 #line 1611
   __cil_tmp60 = dpfc_ctl | 2147483648U;
 #line 1611
   i915_write32___4(dev_priv, 274952U, __cil_tmp60);
   }
   {
 #line 1613
   __cil_tmp61 = dev->dev_private;
 #line 1613
   __cil_tmp62 = (struct drm_i915_private *)__cil_tmp61;
 #line 1613
   __cil_tmp63 = __cil_tmp62->info;
 #line 1613
   __cil_tmp64 = __cil_tmp63->gen;
 #line 1613
   __cil_tmp65 = (unsigned char )__cil_tmp64;
 #line 1613
   __cil_tmp66 = (unsigned int )__cil_tmp65;
 #line 1613
   if (__cil_tmp66 == 6U) {
     {
 #line 1614
     __cil_tmp67 = dev_priv->cfb_fence;
 #line 1614
     __cil_tmp68 = __cil_tmp67 | 536870912;
 #line 1614
     __cil_tmp69 = (u32 )__cil_tmp68;
 #line 1614
     i915_write32___4(dev_priv, 1048832U, __cil_tmp69);
 #line 1616
     __cil_tmp70 = crtc->y;
 #line 1616
     __cil_tmp71 = (u32 )__cil_tmp70;
 #line 1616
     i915_write32___4(dev_priv, 1048836U, __cil_tmp71);
 #line 1617
     sandybridge_blit_fbc_update(dev);
     }
   } else {
 
   }
   }
   {
 #line 1620
   __cil_tmp72 = intel_crtc->plane;
 #line 1620
   __cil_tmp73 = (unsigned int )__cil_tmp72;
 #line 1620
   drm_ut_debug_printk(4U, "drm", "ironlake_enable_fbc", "enabled fbc on plane %d\n",
                       __cil_tmp73);
   }
 #line 1621
   return;
 }
 }
 #line 1623 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void ironlake_disable_fbc(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 dpfc_ctl ;
   void *__cil_tmp4 ;
   int __cil_tmp5 ;
 
   {
   {
 #line 1625
   __cil_tmp4 = dev->dev_private;
 #line 1625
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1629
   dpfc_ctl = i915_read32___6(dev_priv, 274952U);
   }
   {
 #line 1630
   __cil_tmp5 = (int )dpfc_ctl;
 #line 1630
   if (__cil_tmp5 < 0) {
     {
 #line 1631
     dpfc_ctl = dpfc_ctl & 2147483647U;
 #line 1632
     i915_write32___4(dev_priv, 274952U, dpfc_ctl);
 #line 1634
     drm_ut_debug_printk(4U, "drm", "ironlake_disable_fbc", "disabled FBC\n");
     }
   } else {
 
   }
   }
 #line 1636
   return;
 }
 }
 #line 1638 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool ironlake_fbc_enabled(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   void *__cil_tmp4 ;
   unsigned int __cil_tmp5 ;
   int __cil_tmp6 ;
 
   {
   {
 #line 1640
   __cil_tmp4 = dev->dev_private;
 #line 1640
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 1642
   tmp = i915_read32___6(dev_priv, 274952U);
   }
   {
 #line 1642
   __cil_tmp5 = tmp & 2147483648U;
 #line 1642
   __cil_tmp6 = __cil_tmp5 != 0U;
 #line 1642
   return ((bool )__cil_tmp6);
   }
 }
 }
 #line 1645 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 bool intel_fbc_enabled(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   bool tmp ;
   void *__cil_tmp4 ;
   bool (*__cil_tmp5)(struct drm_device * ) ;
   unsigned long __cil_tmp6 ;
   bool (*__cil_tmp7)(struct drm_device * ) ;
   unsigned long __cil_tmp8 ;
   bool (*__cil_tmp9)(struct drm_device * ) ;
 
   {
 #line 1647
   __cil_tmp4 = dev->dev_private;
 #line 1647
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
   {
 #line 1649
   __cil_tmp5 = (bool (*)(struct drm_device * ))0;
 #line 1649
   __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 1649
   __cil_tmp7 = dev_priv->display.fbc_enabled;
 #line 1649
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 1649
   if (__cil_tmp8 == __cil_tmp6) {
 #line 1650
     return ((bool )0);
   } else {
 
   }
   }
   {
 #line 1652
   __cil_tmp9 = dev_priv->display.fbc_enabled;
 #line 1652
   tmp = (*__cil_tmp9)(dev);
   }
 #line 1652
   return (tmp);
 }
 }
 #line 1655 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_enable_fbc(struct drm_crtc *crtc , unsigned long interval ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_device *__cil_tmp4 ;
   void *__cil_tmp5 ;
   void (*__cil_tmp6)(struct drm_crtc * , unsigned long  ) ;
   unsigned long __cil_tmp7 ;
   void (*__cil_tmp8)(struct drm_crtc * , unsigned long  ) ;
   unsigned long __cil_tmp9 ;
   void (*__cil_tmp10)(struct drm_crtc * , unsigned long  ) ;
 
   {
 #line 1657
   __cil_tmp4 = crtc->dev;
 #line 1657
   __cil_tmp5 = __cil_tmp4->dev_private;
 #line 1657
   dev_priv = (struct drm_i915_private *)__cil_tmp5;
   {
 #line 1659
   __cil_tmp6 = (void (*)(struct drm_crtc * , unsigned long  ))0;
 #line 1659
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 1659
   __cil_tmp8 = dev_priv->display.enable_fbc;
 #line 1659
   __cil_tmp9 = (unsigned long )__cil_tmp8;
 #line 1659
   if (__cil_tmp9 == __cil_tmp7) {
 #line 1660
     return;
   } else {
 
   }
   }
   {
 #line 1662
   __cil_tmp10 = dev_priv->display.enable_fbc;
 #line 1662
   (*__cil_tmp10)(crtc, interval);
   }
 #line 1663
   return;
 }
 }
 #line 1665 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_disable_fbc(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp3 ;
   void (*__cil_tmp4)(struct drm_device * ) ;
   unsigned long __cil_tmp5 ;
   void (*__cil_tmp6)(struct drm_device * ) ;
   unsigned long __cil_tmp7 ;
   void (*__cil_tmp8)(struct drm_device * ) ;
 
   {
 #line 1667
   __cil_tmp3 = dev->dev_private;
 #line 1667
   dev_priv = (struct drm_i915_private *)__cil_tmp3;
   {
 #line 1669
   __cil_tmp4 = (void (*)(struct drm_device * ))0;
 #line 1669
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 1669
   __cil_tmp6 = dev_priv->display.disable_fbc;
 #line 1669
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 1669
   if (__cil_tmp7 == __cil_tmp5) {
 #line 1670
     return;
   } else {
 
   }
   }
   {
 #line 1672
   __cil_tmp8 = dev_priv->display.disable_fbc;
 #line 1672
   (*__cil_tmp8)(dev);
   }
 #line 1673
   return;
 }
 }
 #line 1694 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_update_fbc(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_crtc *crtc ;
   struct drm_crtc *tmp_crtc ;
   struct intel_crtc *intel_crtc ;
   struct drm_framebuffer *fb ;
   struct intel_framebuffer *intel_fb ;
   struct drm_i915_gem_object *obj ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct drm_crtc  const  *__mptr___1 ;
   struct drm_framebuffer  const  *__mptr___2 ;
   int pfo_ret__ ;
   int tmp ;
   bool tmp___0 ;
   void *__cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   struct list_head *__cil_tmp24 ;
   struct drm_crtc *__cil_tmp25 ;
   bool __cil_tmp26 ;
   struct drm_framebuffer *__cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   struct drm_framebuffer *__cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   struct drm_crtc *__cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   struct list_head *__cil_tmp34 ;
   struct drm_crtc *__cil_tmp35 ;
   struct list_head *__cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   struct list_head *__cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   struct drm_crtc *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   struct drm_framebuffer *__cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   struct drm_framebuffer *__cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   struct drm_i915_gem_object *__cil_tmp48 ;
   size_t __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   void *__cil_tmp57 ;
   struct drm_i915_private *__cil_tmp58 ;
   struct intel_device_info  const  *__cil_tmp59 ;
   unsigned char *__cil_tmp60 ;
   unsigned char *__cil_tmp61 ;
   unsigned char __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   enum plane __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   unsigned char *__cil_tmp66 ;
   unsigned char *__cil_tmp67 ;
   unsigned char __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   atomic_t const   *__cil_tmp70 ;
 
   {
   {
 #line 1696
   __cil_tmp16 = dev->dev_private;
 #line 1696
   dev_priv = (struct drm_i915_private *)__cil_tmp16;
 #line 1697
   crtc = (struct drm_crtc *)0;
 #line 1703
   drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "\n");
   }
 #line 1705
   if (i915_powersave == 0U) {
 #line 1706
     return;
   } else {
 
   }
   {
 #line 1708
   __cil_tmp17 = dev->dev_private;
 #line 1708
   __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 1708
   __cil_tmp19 = __cil_tmp18->info;
 #line 1708
   __cil_tmp20 = (unsigned char *)__cil_tmp19;
 #line 1708
   __cil_tmp21 = __cil_tmp20 + 2UL;
 #line 1708
   __cil_tmp22 = *__cil_tmp21;
 #line 1708
   __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 1708
   if (__cil_tmp23 == 0U) {
 #line 1709
     return;
   } else {
 
   }
   }
 #line 1720
   __cil_tmp24 = dev->mode_config.crtc_list.next;
 #line 1720
   __mptr = (struct list_head  const  *)__cil_tmp24;
 #line 1720
   __cil_tmp25 = (struct drm_crtc *)__mptr;
 #line 1720
   tmp_crtc = __cil_tmp25 + 1152921504606846968UL;
 #line 1720
   goto ldv_38704;
   ldv_38703: ;
   {
 #line 1721
   __cil_tmp26 = tmp_crtc->enabled;
 #line 1721
   if ((int )__cil_tmp26) {
     {
 #line 1721
     __cil_tmp27 = (struct drm_framebuffer *)0;
 #line 1721
     __cil_tmp28 = (unsigned long )__cil_tmp27;
 #line 1721
     __cil_tmp29 = tmp_crtc->fb;
 #line 1721
     __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 1721
     if (__cil_tmp30 != __cil_tmp28) {
       {
 #line 1722
       __cil_tmp31 = (struct drm_crtc *)0;
 #line 1722
       __cil_tmp32 = (unsigned long )__cil_tmp31;
 #line 1722
       __cil_tmp33 = (unsigned long )crtc;
 #line 1722
       if (__cil_tmp33 != __cil_tmp32) {
         {
 #line 1723
         drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "more than one pipe active, disabling compression\n");
 #line 1724
         dev_priv->no_fbc_reason = (enum no_fbc_reason )6;
         }
 #line 1725
         goto out_disable;
       } else {
 
       }
       }
 #line 1727
       crtc = tmp_crtc;
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 1720
   __cil_tmp34 = tmp_crtc->head.next;
 #line 1720
   __mptr___0 = (struct list_head  const  *)__cil_tmp34;
 #line 1720
   __cil_tmp35 = (struct drm_crtc *)__mptr___0;
 #line 1720
   tmp_crtc = __cil_tmp35 + 1152921504606846968UL;
   ldv_38704: ;
   {
 #line 1720
   __cil_tmp36 = & dev->mode_config.crtc_list;
 #line 1720
   __cil_tmp37 = (unsigned long )__cil_tmp36;
 #line 1720
   __cil_tmp38 = & tmp_crtc->head;
 #line 1720
   __cil_tmp39 = (unsigned long )__cil_tmp38;
 #line 1720
   if (__cil_tmp39 != __cil_tmp37) {
 #line 1721
     goto ldv_38703;
   } else {
 #line 1723
     goto ldv_38705;
   }
   }
   ldv_38705: ;
   {
 #line 1731
   __cil_tmp40 = (struct drm_crtc *)0;
 #line 1731
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 1731
   __cil_tmp42 = (unsigned long )crtc;
 #line 1731
   if (__cil_tmp42 == __cil_tmp41) {
     {
 #line 1732
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "no output, disabling\n");
 #line 1733
     dev_priv->no_fbc_reason = (enum no_fbc_reason )0;
     }
 #line 1734
     goto out_disable;
   } else {
     {
 #line 1731
     __cil_tmp43 = (struct drm_framebuffer *)0;
 #line 1731
     __cil_tmp44 = (unsigned long )__cil_tmp43;
 #line 1731
     __cil_tmp45 = crtc->fb;
 #line 1731
     __cil_tmp46 = (unsigned long )__cil_tmp45;
 #line 1731
     if (__cil_tmp46 == __cil_tmp44) {
       {
 #line 1732
       drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "no output, disabling\n");
 #line 1733
       dev_priv->no_fbc_reason = (enum no_fbc_reason )0;
       }
 #line 1734
       goto out_disable;
     } else {
 
     }
     }
   }
   }
 #line 1737
   __mptr___1 = (struct drm_crtc  const  *)crtc;
 #line 1737
   intel_crtc = (struct intel_crtc *)__mptr___1;
 #line 1738
   fb = crtc->fb;
 #line 1739
   __mptr___2 = (struct drm_framebuffer  const  *)fb;
 #line 1739
   intel_fb = (struct intel_framebuffer *)__mptr___2;
 #line 1740
   obj = intel_fb->obj;
 #line 1742
   if (i915_enable_fbc == 0U) {
     {
 #line 1743
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "fbc disabled per module param (default off)\n");
 #line 1744
     dev_priv->no_fbc_reason = (enum no_fbc_reason )7;
     }
 #line 1745
     goto out_disable;
   } else {
 
   }
   {
 #line 1747
   __cil_tmp47 = dev_priv->cfb_size;
 #line 1747
   __cil_tmp48 = intel_fb->obj;
 #line 1747
   __cil_tmp49 = __cil_tmp48->base.size;
 #line 1747
   if (__cil_tmp49 > __cil_tmp47) {
     {
 #line 1748
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "framebuffer too large, disabling compression\n");
 #line 1750
     dev_priv->no_fbc_reason = (enum no_fbc_reason )1;
     }
 #line 1751
     goto out_disable;
   } else {
 
   }
   }
   {
 #line 1753
   __cil_tmp50 = crtc->mode.flags;
 #line 1753
   __cil_tmp51 = __cil_tmp50 & 16U;
 #line 1753
   if (__cil_tmp51 != 0U) {
     {
 #line 1755
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "mode incompatible with compression, disabling\n");
 #line 1757
     dev_priv->no_fbc_reason = (enum no_fbc_reason )2;
     }
 #line 1758
     goto out_disable;
   } else {
     {
 #line 1753
     __cil_tmp52 = crtc->mode.flags;
 #line 1753
     __cil_tmp53 = __cil_tmp52 & 32U;
 #line 1753
     if (__cil_tmp53 != 0U) {
       {
 #line 1755
       drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "mode incompatible with compression, disabling\n");
 #line 1757
       dev_priv->no_fbc_reason = (enum no_fbc_reason )2;
       }
 #line 1758
       goto out_disable;
     } else {
 
     }
     }
   }
   }
   {
 #line 1760
   __cil_tmp54 = crtc->mode.hdisplay;
 #line 1760
   if (__cil_tmp54 > 2048) {
     {
 #line 1762
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "mode too large for compression, disabling\n");
 #line 1763
     dev_priv->no_fbc_reason = (enum no_fbc_reason )3;
     }
 #line 1764
     goto out_disable;
   } else {
     {
 #line 1760
     __cil_tmp55 = crtc->mode.vdisplay;
 #line 1760
     if (__cil_tmp55 > 1536) {
       {
 #line 1762
       drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "mode too large for compression, disabling\n");
 #line 1763
       dev_priv->no_fbc_reason = (enum no_fbc_reason )3;
       }
 #line 1764
       goto out_disable;
     } else {
 
     }
     }
   }
   }
   {
 #line 1766
   __cil_tmp56 = dev->pci_device;
 #line 1766
   if (__cil_tmp56 == 9618) {
 #line 1766
     goto _L;
   } else {
     {
 #line 1766
     __cil_tmp57 = dev->dev_private;
 #line 1766
     __cil_tmp58 = (struct drm_i915_private *)__cil_tmp57;
 #line 1766
     __cil_tmp59 = __cil_tmp58->info;
 #line 1766
     __cil_tmp60 = (unsigned char *)__cil_tmp59;
 #line 1766
     __cil_tmp61 = __cil_tmp60 + 1UL;
 #line 1766
     __cil_tmp62 = *__cil_tmp61;
 #line 1766
     __cil_tmp63 = (unsigned int )__cil_tmp62;
 #line 1766
     if (__cil_tmp63 != 0U) {
       _L: 
       {
 #line 1766
       __cil_tmp64 = intel_crtc->plane;
 #line 1766
       __cil_tmp65 = (unsigned int )__cil_tmp64;
 #line 1766
       if (__cil_tmp65 != 0U) {
         {
 #line 1767
         drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "plane not 0, disabling compression\n");
 #line 1768
         dev_priv->no_fbc_reason = (enum no_fbc_reason )4;
         }
 #line 1769
         goto out_disable;
       } else {
 
       }
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 1771
   __cil_tmp66 = (unsigned char *)obj;
 #line 1771
   __cil_tmp67 = __cil_tmp66 + 225UL;
 #line 1771
   __cil_tmp68 = *__cil_tmp67;
 #line 1771
   __cil_tmp69 = (unsigned int )__cil_tmp68;
 #line 1771
   if (__cil_tmp69 != 4U) {
     {
 #line 1772
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "framebuffer not tiled, disabling compression\n");
 #line 1773
     dev_priv->no_fbc_reason = (enum no_fbc_reason )5;
     }
 #line 1774
     goto out_disable;
   } else {
 
   }
   }
 #line 1778
   if (1) {
 #line 1778
     goto case_4;
   } else {
 #line 1778
     goto switch_default;
 #line 1778
     if (0) {
 #line 1778
       __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
 #line 1778
       goto ldv_38712;
 #line 1778
       __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1778
       goto ldv_38712;
       case_4: 
 #line 1778
       __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1778
       goto ldv_38712;
 #line 1778
       __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
 #line 1778
       goto ldv_38712;
       switch_default: 
       {
 #line 1778
       __bad_percpu_size();
       }
     } else {
 
     }
   }
   ldv_38712: 
   {
 #line 1778
   __cil_tmp70 = (atomic_t const   *)(& kgdb_active);
 #line 1778
   tmp = atomic_read(__cil_tmp70);
   }
 #line 1778
   if (pfo_ret__ == tmp) {
 #line 1779
     goto out_disable;
   } else {
 
   }
   {
 #line 1781
   intel_enable_fbc(crtc, 500UL);
   }
 #line 1782
   return;
   out_disable: 
   {
 #line 1786
   tmp___0 = intel_fbc_enabled(dev);
   }
 #line 1786
   if ((int )tmp___0) {
     {
 #line 1787
     drm_ut_debug_printk(4U, "drm", "intel_update_fbc", "unsupported config, disabling FBC\n");
 #line 1788
     intel_disable_fbc(dev);
     }
   } else {
 
   }
 #line 1790
   return;
 }
 }
 #line 1793 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 int intel_pin_and_fence_fb_obj(struct drm_device *dev , struct drm_i915_gem_object *obj ,
                                struct intel_ring_buffer *pipelined ) 
 { struct drm_i915_private *dev_priv ;
   u32 alignment ;
   int ret ;
   void *__cil_tmp7 ;
   unsigned char __cil_tmp8 ;
   int __cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   int __cil_tmp11 ;
   unsigned char __cil_tmp12 ;
   int __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   struct intel_device_info  const  *__cil_tmp23 ;
   unsigned char *__cil_tmp24 ;
   unsigned char *__cil_tmp25 ;
   unsigned char __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   void *__cil_tmp28 ;
   struct drm_i915_private *__cil_tmp29 ;
   struct intel_device_info  const  *__cil_tmp30 ;
   u8 __cil_tmp31 ;
   unsigned char __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   bool __cil_tmp34 ;
   unsigned char *__cil_tmp35 ;
   unsigned char *__cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
 
   {
 #line 1797
   __cil_tmp7 = dev->dev_private;
 #line 1797
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
   {
 #line 1802
   __cil_tmp8 = obj->tiling_mode;
 #line 1802
   __cil_tmp9 = (int )__cil_tmp8;
 #line 1802
   if (__cil_tmp9 == 0) {
 #line 1802
     goto case_0;
   } else {
     {
 #line 1810
     __cil_tmp10 = obj->tiling_mode;
 #line 1810
     __cil_tmp11 = (int )__cil_tmp10;
 #line 1810
     if (__cil_tmp11 == 1) {
 #line 1810
       goto case_1;
     } else {
       {
 #line 1814
       __cil_tmp12 = obj->tiling_mode;
 #line 1814
       __cil_tmp13 = (int )__cil_tmp12;
 #line 1814
       if (__cil_tmp13 == 2) {
 #line 1814
         goto case_2;
       } else {
 #line 1818
         goto switch_default;
 #line 1801
         if (0) {
           case_0: ;
           {
 #line 1803
           __cil_tmp14 = dev->dev_private;
 #line 1803
           __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 1803
           __cil_tmp16 = __cil_tmp15->info;
 #line 1803
           __cil_tmp17 = (unsigned char *)__cil_tmp16;
 #line 1803
           __cil_tmp18 = __cil_tmp17 + 2UL;
 #line 1803
           __cil_tmp19 = *__cil_tmp18;
 #line 1803
           __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 1803
           if (__cil_tmp20 != 0U) {
 #line 1804
             alignment = 131072U;
           } else {
             {
 #line 1803
             __cil_tmp21 = dev->dev_private;
 #line 1803
             __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 1803
             __cil_tmp23 = __cil_tmp22->info;
 #line 1803
             __cil_tmp24 = (unsigned char *)__cil_tmp23;
 #line 1803
             __cil_tmp25 = __cil_tmp24 + 2UL;
 #line 1803
             __cil_tmp26 = *__cil_tmp25;
 #line 1803
             __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1803
             if (__cil_tmp27 != 0U) {
 #line 1804
               alignment = 131072U;
             } else {
               {
 #line 1805
               __cil_tmp28 = dev->dev_private;
 #line 1805
               __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
 #line 1805
               __cil_tmp30 = __cil_tmp29->info;
 #line 1805
               __cil_tmp31 = __cil_tmp30->gen;
 #line 1805
               __cil_tmp32 = (unsigned char )__cil_tmp31;
 #line 1805
               __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 1805
               if (__cil_tmp33 > 3U) {
 #line 1806
                 alignment = 4096U;
               } else {
 #line 1808
                 alignment = 65536U;
               }
               }
             }
             }
           }
           }
 #line 1809
           goto ldv_38727;
           case_1: 
 #line 1812
           alignment = 0U;
 #line 1813
           goto ldv_38727;
           case_2: 
           {
 #line 1816
           drm_err("intel_pin_and_fence_fb_obj", "Y tiled not allowed for scan out buffers\n");
           }
 #line 1817
           return (-22);
           switch_default: 
 #line 1819
           __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                                "i" (1819), "i" (12UL));
           ldv_38732: ;
 #line 1819
           goto ldv_38732;
         } else {
 
         }
       }
       }
     }
     }
   }
   }
   ldv_38727: 
   {
 #line 1822
   dev_priv->mm.interruptible = (bool )0;
 #line 1823
   __cil_tmp34 = (bool )1;
 #line 1823
   ret = i915_gem_object_pin(obj, alignment, __cil_tmp34);
   }
 #line 1824
   if (ret != 0) {
 #line 1825
     goto err_interruptible;
   } else {
 
   }
   {
 #line 1827
   ret = i915_gem_object_set_to_display_plane(obj, pipelined);
   }
 #line 1828
   if (ret != 0) {
 #line 1829
     goto err_unpin;
   } else {
 
   }
   {
 #line 1836
   __cil_tmp35 = (unsigned char *)obj;
 #line 1836
   __cil_tmp36 = __cil_tmp35 + 225UL;
 #line 1836
   __cil_tmp37 = *__cil_tmp36;
 #line 1836
   __cil_tmp38 = (unsigned int )__cil_tmp37;
 #line 1836
   if (__cil_tmp38 != 0U) {
     {
 #line 1837
     ret = i915_gem_object_get_fence(obj, pipelined);
     }
 #line 1838
     if (ret != 0) {
 #line 1839
       goto err_unpin;
     } else {
 
     }
   } else {
 
   }
   }
 #line 1842
   dev_priv->mm.interruptible = (bool )1;
 #line 1843
   return (0);
   err_unpin: 
   {
 #line 1846
   i915_gem_object_unpin(obj);
   }
   err_interruptible: 
 #line 1848
   dev_priv->mm.interruptible = (bool )1;
 #line 1849
   return (ret);
 }
 }
 #line 1854 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int intel_pipe_set_base_atomic(struct drm_crtc *crtc , struct drm_framebuffer *fb ,
                                       int x , int y , enum mode_set_atomic state ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   struct intel_framebuffer *intel_fb ;
   struct drm_i915_gem_object *obj ;
   int plane ;
   unsigned long Start ;
   unsigned long Offset ;
   u32 dspcntr ;
   u32 reg ;
   struct drm_framebuffer  const  *__mptr___0 ;
   void *__cil_tmp18 ;
   enum plane __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   void *__cil_tmp27 ;
   struct drm_i915_private *__cil_tmp28 ;
   struct intel_device_info  const  *__cil_tmp29 ;
   u8 __cil_tmp30 ;
   unsigned char __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   unsigned char *__cil_tmp33 ;
   unsigned char *__cil_tmp34 ;
   unsigned char __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   void *__cil_tmp37 ;
   struct drm_i915_private *__cil_tmp38 ;
   struct intel_device_info  const  *__cil_tmp39 ;
   u8 __cil_tmp40 ;
   unsigned char __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   void *__cil_tmp43 ;
   struct drm_i915_private *__cil_tmp44 ;
   struct intel_device_info  const  *__cil_tmp45 ;
   u8 __cil_tmp46 ;
   unsigned char __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   void *__cil_tmp49 ;
   struct drm_i915_private *__cil_tmp50 ;
   struct intel_device_info  const  *__cil_tmp51 ;
   unsigned char *__cil_tmp52 ;
   unsigned char *__cil_tmp53 ;
   unsigned char __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   uint32_t __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   int __cil_tmp66 ;
   int __cil_tmp67 ;
   u32 __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   void *__cil_tmp70 ;
   struct drm_i915_private *__cil_tmp71 ;
   struct intel_device_info  const  *__cil_tmp72 ;
   u8 __cil_tmp73 ;
   unsigned char __cil_tmp74 ;
   unsigned int __cil_tmp75 ;
   int __cil_tmp76 ;
   int __cil_tmp77 ;
   u32 __cil_tmp78 ;
   u32 __cil_tmp79 ;
   int __cil_tmp80 ;
   int __cil_tmp81 ;
   u32 __cil_tmp82 ;
   int __cil_tmp83 ;
   int __cil_tmp84 ;
   u32 __cil_tmp85 ;
   int __cil_tmp86 ;
   int __cil_tmp87 ;
   u32 __cil_tmp88 ;
   u32 __cil_tmp89 ;
   int __cil_tmp90 ;
   int __cil_tmp91 ;
   u32 __cil_tmp92 ;
   u32 __cil_tmp93 ;
   u32 __cil_tmp94 ;
   u32 __cil_tmp95 ;
   unsigned long __cil_tmp96 ;
   void *__cil_tmp97 ;
   void const volatile   *__cil_tmp98 ;
   void const volatile   *__cil_tmp99 ;
 
   {
 #line 1857
   dev = crtc->dev;
 #line 1858
   __cil_tmp18 = dev->dev_private;
 #line 1858
   dev_priv = (struct drm_i915_private *)__cil_tmp18;
 #line 1859
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 1859
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 1862
   __cil_tmp19 = intel_crtc->plane;
 #line 1862
   plane = (int )__cil_tmp19;
 #line 1868
   if (plane == 0) {
 #line 1868
     goto case_0;
   } else
 #line 1869
   if (plane == 1) {
 #line 1869
     goto case_1;
   } else {
 #line 1871
     goto switch_default;
 #line 1867
     if (0) {
       case_0: ;
       case_1: ;
 #line 1870
       goto ldv_38756;
       switch_default: 
       {
 #line 1872
       drm_err("intel_pipe_set_base_atomic", "Can\'t update plane %d in SAREA\n", plane);
       }
 #line 1873
       return (-22);
     } else {
 
     }
   }
   ldv_38756: 
   {
 #line 1876
   __mptr___0 = (struct drm_framebuffer  const  *)fb;
 #line 1876
   intel_fb = (struct intel_framebuffer *)__mptr___0;
 #line 1877
   obj = intel_fb->obj;
 #line 1879
   __cil_tmp20 = plane * 4096;
 #line 1879
   __cil_tmp21 = __cil_tmp20 + 459136;
 #line 1879
   reg = (u32 )__cil_tmp21;
 #line 1880
   dspcntr = i915_read32___6(dev_priv, reg);
 #line 1882
   dspcntr = dspcntr & 3288334335U;
   }
   {
 #line 1884
   __cil_tmp22 = fb->bits_per_pixel;
 #line 1884
   if (__cil_tmp22 == 8) {
 #line 1884
     goto case_8;
   } else {
     {
 #line 1887
     __cil_tmp23 = fb->bits_per_pixel;
 #line 1887
     if (__cil_tmp23 == 16) {
 #line 1887
       goto case_16;
     } else {
       {
 #line 1893
       __cil_tmp24 = fb->bits_per_pixel;
 #line 1893
       if (__cil_tmp24 == 24) {
 #line 1893
         goto case_24;
       } else {
         {
 #line 1894
         __cil_tmp25 = fb->bits_per_pixel;
 #line 1894
         if (__cil_tmp25 == 32) {
 #line 1894
           goto case_32;
         } else {
 #line 1897
           goto switch_default___0;
 #line 1883
           if (0) {
             case_8: 
 #line 1885
             dspcntr = dspcntr | 134217728U;
 #line 1886
             goto ldv_38762;
             case_16: ;
             {
 #line 1888
             __cil_tmp26 = fb->depth;
 #line 1888
             if (__cil_tmp26 == 15U) {
 #line 1889
               dspcntr = dspcntr | 268435456U;
             } else {
 #line 1891
               dspcntr = dspcntr | 335544320U;
             }
             }
 #line 1892
             goto ldv_38762;
             case_24: ;
             case_32: 
 #line 1895
             dspcntr = dspcntr | 402653184U;
 #line 1896
             goto ldv_38762;
             switch_default___0: 
             {
 #line 1898
             drm_err("intel_pipe_set_base_atomic", "Unknown color depth\n");
             }
 #line 1899
             return (-22);
           } else {
 
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_38762: ;
   {
 #line 1901
   __cil_tmp27 = dev->dev_private;
 #line 1901
   __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
 #line 1901
   __cil_tmp29 = __cil_tmp28->info;
 #line 1901
   __cil_tmp30 = __cil_tmp29->gen;
 #line 1901
   __cil_tmp31 = (unsigned char )__cil_tmp30;
 #line 1901
   __cil_tmp32 = (unsigned int )__cil_tmp31;
 #line 1901
   if (__cil_tmp32 > 3U) {
     {
 #line 1902
     __cil_tmp33 = (unsigned char *)obj;
 #line 1902
     __cil_tmp34 = __cil_tmp33 + 225UL;
 #line 1902
     __cil_tmp35 = *__cil_tmp34;
 #line 1902
     __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 1902
     if (__cil_tmp36 != 0U) {
 #line 1903
       dspcntr = dspcntr | 1024U;
     } else {
 #line 1905
       dspcntr = dspcntr & 4294966271U;
     }
     }
   } else {
 
   }
   }
   {
 #line 1908
   __cil_tmp37 = dev->dev_private;
 #line 1908
   __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
 #line 1908
   __cil_tmp39 = __cil_tmp38->info;
 #line 1908
   __cil_tmp40 = __cil_tmp39->gen;
 #line 1908
   __cil_tmp41 = (unsigned char )__cil_tmp40;
 #line 1908
   __cil_tmp42 = (unsigned int )__cil_tmp41;
 #line 1908
   if (__cil_tmp42 == 5U) {
 #line 1910
     dspcntr = dspcntr | 16384U;
   } else {
     {
 #line 1908
     __cil_tmp43 = dev->dev_private;
 #line 1908
     __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
 #line 1908
     __cil_tmp45 = __cil_tmp44->info;
 #line 1908
     __cil_tmp46 = __cil_tmp45->gen;
 #line 1908
     __cil_tmp47 = (unsigned char )__cil_tmp46;
 #line 1908
     __cil_tmp48 = (unsigned int )__cil_tmp47;
 #line 1908
     if (__cil_tmp48 == 6U) {
 #line 1910
       dspcntr = dspcntr | 16384U;
     } else {
       {
 #line 1908
       __cil_tmp49 = dev->dev_private;
 #line 1908
       __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
 #line 1908
       __cil_tmp51 = __cil_tmp50->info;
 #line 1908
       __cil_tmp52 = (unsigned char *)__cil_tmp51;
 #line 1908
       __cil_tmp53 = __cil_tmp52 + 2UL;
 #line 1908
       __cil_tmp54 = *__cil_tmp53;
 #line 1908
       __cil_tmp55 = (unsigned int )__cil_tmp54;
 #line 1908
       if (__cil_tmp55 != 0U) {
 #line 1910
         dspcntr = dspcntr | 16384U;
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 1912
   i915_write32___4(dev_priv, reg, dspcntr);
 #line 1914
   __cil_tmp56 = obj->gtt_offset;
 #line 1914
   Start = (unsigned long )__cil_tmp56;
 #line 1915
   __cil_tmp57 = fb->bits_per_pixel;
 #line 1915
   __cil_tmp58 = __cil_tmp57 / 8;
 #line 1915
   __cil_tmp59 = __cil_tmp58 * x;
 #line 1915
   __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 1915
   __cil_tmp61 = (unsigned int )y;
 #line 1915
   __cil_tmp62 = fb->pitch;
 #line 1915
   __cil_tmp63 = __cil_tmp62 * __cil_tmp61;
 #line 1915
   __cil_tmp64 = __cil_tmp63 + __cil_tmp60;
 #line 1915
   Offset = (unsigned long )__cil_tmp64;
 #line 1917
   __cil_tmp65 = fb->pitch;
 #line 1917
   drm_ut_debug_printk(4U, "drm", "intel_pipe_set_base_atomic", "Writing base %08lX %08lX %d %d %d\n",
                       Start, Offset, x, y, __cil_tmp65);
 #line 1919
   __cil_tmp66 = plane * 4096;
 #line 1919
   __cil_tmp67 = __cil_tmp66 + 459144;
 #line 1919
   __cil_tmp68 = (u32 )__cil_tmp67;
 #line 1919
   __cil_tmp69 = fb->pitch;
 #line 1919
   i915_write32___4(dev_priv, __cil_tmp68, __cil_tmp69);
   }
   {
 #line 1920
   __cil_tmp70 = dev->dev_private;
 #line 1920
   __cil_tmp71 = (struct drm_i915_private *)__cil_tmp70;
 #line 1920
   __cil_tmp72 = __cil_tmp71->info;
 #line 1920
   __cil_tmp73 = __cil_tmp72->gen;
 #line 1920
   __cil_tmp74 = (unsigned char )__cil_tmp73;
 #line 1920
   __cil_tmp75 = (unsigned int )__cil_tmp74;
 #line 1920
   if (__cil_tmp75 > 3U) {
     {
 #line 1921
     __cil_tmp76 = plane * 4096;
 #line 1921
     __cil_tmp77 = __cil_tmp76 + 459164;
 #line 1921
     __cil_tmp78 = (u32 )__cil_tmp77;
 #line 1921
     __cil_tmp79 = (u32 )Start;
 #line 1921
     i915_write32___4(dev_priv, __cil_tmp78, __cil_tmp79);
 #line 1922
     __cil_tmp80 = plane * 4096;
 #line 1922
     __cil_tmp81 = __cil_tmp80 + 459172;
 #line 1922
     __cil_tmp82 = (u32 )__cil_tmp81;
 #line 1922
     __cil_tmp83 = y << 16;
 #line 1922
     __cil_tmp84 = __cil_tmp83 | x;
 #line 1922
     __cil_tmp85 = (u32 )__cil_tmp84;
 #line 1922
     i915_write32___4(dev_priv, __cil_tmp82, __cil_tmp85);
 #line 1923
     __cil_tmp86 = plane * 4096;
 #line 1923
     __cil_tmp87 = __cil_tmp86 + 459140;
 #line 1923
     __cil_tmp88 = (u32 )__cil_tmp87;
 #line 1923
     __cil_tmp89 = (u32 )Offset;
 #line 1923
     i915_write32___4(dev_priv, __cil_tmp88, __cil_tmp89);
     }
   } else {
     {
 #line 1925
     __cil_tmp90 = plane * 4096;
 #line 1925
     __cil_tmp91 = __cil_tmp90 + 459140;
 #line 1925
     __cil_tmp92 = (u32 )__cil_tmp91;
 #line 1925
     __cil_tmp93 = (u32 )Offset;
 #line 1925
     __cil_tmp94 = (u32 )Start;
 #line 1925
     __cil_tmp95 = __cil_tmp94 + __cil_tmp93;
 #line 1925
     i915_write32___4(dev_priv, __cil_tmp92, __cil_tmp95);
     }
   }
   }
   {
 #line 1926
   __cil_tmp96 = (unsigned long )reg;
 #line 1926
   __cil_tmp97 = dev_priv->regs;
 #line 1926
   __cil_tmp98 = (void const volatile   *)__cil_tmp97;
 #line 1926
   __cil_tmp99 = __cil_tmp98 + __cil_tmp96;
 #line 1926
   readl(__cil_tmp99);
 #line 1928
   intel_update_fbc(dev);
 #line 1929
   intel_increase_pllclock(crtc);
   }
 #line 1931
   return (0);
 }
 }
 #line 1935 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int intel_pipe_set_base(struct drm_crtc *crtc , int x , int y , struct drm_framebuffer *old_fb ) 
 { struct drm_device *dev ;
   struct drm_i915_master_private *master_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int ret ;
   struct drm_framebuffer  const  *__mptr___0 ;
   struct drm_i915_private *dev_priv ;
   struct drm_i915_gem_object *obj ;
   struct drm_framebuffer  const  *__mptr___1 ;
   int tmp ;
   int tmp___0 ;
   wait_queue_t __wait ;
   struct task_struct *tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   struct drm_framebuffer  const  *__mptr___2 ;
   struct drm_framebuffer  const  *__mptr___3 ;
   struct drm_framebuffer *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   struct drm_framebuffer *__cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   enum plane __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   int __cil_tmp28 ;
   enum plane __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   int __cil_tmp31 ;
   struct mutex *__cil_tmp32 ;
   struct drm_framebuffer *__cil_tmp33 ;
   struct intel_framebuffer *__cil_tmp34 ;
   struct drm_i915_gem_object *__cil_tmp35 ;
   struct intel_ring_buffer *__cil_tmp36 ;
   struct mutex *__cil_tmp37 ;
   struct drm_framebuffer *__cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   void *__cil_tmp41 ;
   struct intel_framebuffer *__cil_tmp42 ;
   atomic_t *__cil_tmp43 ;
   atomic_t const   *__cil_tmp44 ;
   atomic_t *__cil_tmp45 ;
   atomic_t const   *__cil_tmp46 ;
   wait_queue_head_t *__cil_tmp47 ;
   atomic_t *__cil_tmp48 ;
   atomic_t const   *__cil_tmp49 ;
   atomic_t *__cil_tmp50 ;
   atomic_t const   *__cil_tmp51 ;
   wait_queue_head_t *__cil_tmp52 ;
   struct drm_framebuffer *__cil_tmp53 ;
   enum mode_set_atomic __cil_tmp54 ;
   struct drm_framebuffer *__cil_tmp55 ;
   struct intel_framebuffer *__cil_tmp56 ;
   struct drm_i915_gem_object *__cil_tmp57 ;
   struct mutex *__cil_tmp58 ;
   struct drm_framebuffer *__cil_tmp59 ;
   unsigned long __cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   enum pipe __cil_tmp62 ;
   int __cil_tmp63 ;
   struct intel_framebuffer *__cil_tmp64 ;
   struct drm_i915_gem_object *__cil_tmp65 ;
   struct mutex *__cil_tmp66 ;
   struct drm_master *__cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   struct drm_minor *__cil_tmp69 ;
   struct drm_master *__cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   struct drm_minor *__cil_tmp72 ;
   struct drm_master *__cil_tmp73 ;
   void *__cil_tmp74 ;
   struct _drm_i915_sarea *__cil_tmp75 ;
   unsigned long __cil_tmp76 ;
   struct _drm_i915_sarea *__cil_tmp77 ;
   unsigned long __cil_tmp78 ;
   enum pipe __cil_tmp79 ;
   unsigned int __cil_tmp80 ;
   struct _drm_i915_sarea *__cil_tmp81 ;
   struct _drm_i915_sarea *__cil_tmp82 ;
   struct _drm_i915_sarea *__cil_tmp83 ;
   struct _drm_i915_sarea *__cil_tmp84 ;
 
   {
 #line 1938
   dev = crtc->dev;
 #line 1940
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 1940
   intel_crtc = (struct intel_crtc *)__mptr;
   {
 #line 1944
   __cil_tmp22 = (struct drm_framebuffer *)0;
 #line 1944
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 1944
   __cil_tmp24 = crtc->fb;
 #line 1944
   __cil_tmp25 = (unsigned long )__cil_tmp24;
 #line 1944
   if (__cil_tmp25 == __cil_tmp23) {
     {
 #line 1945
     drm_ut_debug_printk(4U, "drm", "intel_pipe_set_base", "No FB bound\n");
     }
 #line 1946
     return (0);
   } else {
 
   }
   }
   {
 #line 1950
   __cil_tmp26 = intel_crtc->plane;
 #line 1950
   __cil_tmp27 = (unsigned int )__cil_tmp26;
 #line 1950
   __cil_tmp28 = (int )__cil_tmp27;
 #line 1950
   if (__cil_tmp28 == 0) {
 #line 1950
     goto case_0;
   } else {
     {
 #line 1951
     __cil_tmp29 = intel_crtc->plane;
 #line 1951
     __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 1951
     __cil_tmp31 = (int )__cil_tmp30;
 #line 1951
     if (__cil_tmp31 == 1) {
 #line 1951
       goto case_1;
     } else {
 #line 1953
       goto switch_default;
 #line 1949
       if (0) {
         case_0: ;
         case_1: ;
 #line 1952
         goto ldv_38782;
         switch_default: ;
 #line 1954
         return (-22);
       } else {
 
       }
     }
     }
   }
   }
   ldv_38782: 
   {
 #line 1957
   __cil_tmp32 = & dev->struct_mutex;
 #line 1957
   mutex_lock_nested(__cil_tmp32, 0U);
 #line 1959
   __cil_tmp33 = crtc->fb;
 #line 1959
   __mptr___0 = (struct drm_framebuffer  const  *)__cil_tmp33;
 #line 1959
   __cil_tmp34 = (struct intel_framebuffer *)__mptr___0;
 #line 1959
   __cil_tmp35 = __cil_tmp34->obj;
 #line 1959
   __cil_tmp36 = (struct intel_ring_buffer *)0;
 #line 1959
   ret = intel_pin_and_fence_fb_obj(dev, __cil_tmp35, __cil_tmp36);
   }
 #line 1961
   if (ret != 0) {
     {
 #line 1962
     __cil_tmp37 = & dev->struct_mutex;
 #line 1962
     mutex_unlock(__cil_tmp37);
     }
 #line 1963
     return (ret);
   } else {
 
   }
   {
 #line 1966
   __cil_tmp38 = (struct drm_framebuffer *)0;
 #line 1966
   __cil_tmp39 = (unsigned long )__cil_tmp38;
 #line 1966
   __cil_tmp40 = (unsigned long )old_fb;
 #line 1966
   if (__cil_tmp40 != __cil_tmp39) {
     {
 #line 1967
     __cil_tmp41 = dev->dev_private;
 #line 1967
     dev_priv = (struct drm_i915_private *)__cil_tmp41;
 #line 1968
     __mptr___1 = (struct drm_framebuffer  const  *)old_fb;
 #line 1968
     __cil_tmp42 = (struct intel_framebuffer *)__mptr___1;
 #line 1968
     obj = __cil_tmp42->obj;
 #line 1970
     __cil_tmp43 = & dev_priv->mm.wedged;
 #line 1970
     __cil_tmp44 = (atomic_t const   *)__cil_tmp43;
 #line 1970
     tmp = atomic_read(__cil_tmp44);
     }
 #line 1970
     if (tmp != 0) {
 #line 1970
       goto ldv_38790;
     } else {
       {
 #line 1970
       __cil_tmp45 = & obj->pending_flip;
 #line 1970
       __cil_tmp46 = (atomic_t const   *)__cil_tmp45;
 #line 1970
       tmp___0 = atomic_read(__cil_tmp46);
       }
 #line 1970
       if (tmp___0 == 0) {
 #line 1970
         goto ldv_38790;
       } else {
 
       }
     }
     {
 #line 1970
     tmp___1 = get_current();
 #line 1970
     __wait.flags = 0U;
 #line 1970
     __wait.private = (void *)tmp___1;
 #line 1970
     __wait.func = & autoremove_wake_function;
 #line 1970
     __wait.task_list.next = & __wait.task_list;
 #line 1970
     __wait.task_list.prev = & __wait.task_list;
     }
     ldv_38793: 
     {
 #line 1970
     __cil_tmp47 = & dev_priv->pending_flip_queue;
 #line 1970
     prepare_to_wait(__cil_tmp47, & __wait, 2);
 #line 1970
     __cil_tmp48 = & dev_priv->mm.wedged;
 #line 1970
     __cil_tmp49 = (atomic_t const   *)__cil_tmp48;
 #line 1970
     tmp___2 = atomic_read(__cil_tmp49);
     }
 #line 1970
     if (tmp___2 != 0) {
 #line 1970
       goto ldv_38792;
     } else {
       {
 #line 1970
       __cil_tmp50 = & obj->pending_flip;
 #line 1970
       __cil_tmp51 = (atomic_t const   *)__cil_tmp50;
 #line 1970
       tmp___3 = atomic_read(__cil_tmp51);
       }
 #line 1970
       if (tmp___3 == 0) {
 #line 1970
         goto ldv_38792;
       } else {
 
       }
     }
     {
 #line 1970
     schedule();
     }
 #line 1970
     goto ldv_38793;
     ldv_38792: 
     {
 #line 1970
     __cil_tmp52 = & dev_priv->pending_flip_queue;
 #line 1970
     finish_wait(__cil_tmp52, & __wait);
     }
     ldv_38790: 
     {
 #line 1982
     ret = i915_gem_object_flush_gpu(obj);
     }
   } else {
 
   }
   }
   {
 #line 1986
   __cil_tmp53 = crtc->fb;
 #line 1986
   __cil_tmp54 = (enum mode_set_atomic )0;
 #line 1986
   ret = intel_pipe_set_base_atomic(crtc, __cil_tmp53, x, y, __cil_tmp54);
   }
 #line 1988
   if (ret != 0) {
     {
 #line 1989
     __cil_tmp55 = crtc->fb;
 #line 1989
     __mptr___2 = (struct drm_framebuffer  const  *)__cil_tmp55;
 #line 1989
     __cil_tmp56 = (struct intel_framebuffer *)__mptr___2;
 #line 1989
     __cil_tmp57 = __cil_tmp56->obj;
 #line 1989
     i915_gem_object_unpin(__cil_tmp57);
 #line 1990
     __cil_tmp58 = & dev->struct_mutex;
 #line 1990
     mutex_unlock(__cil_tmp58);
     }
 #line 1991
     return (ret);
   } else {
 
   }
   {
 #line 1994
   __cil_tmp59 = (struct drm_framebuffer *)0;
 #line 1994
   __cil_tmp60 = (unsigned long )__cil_tmp59;
 #line 1994
   __cil_tmp61 = (unsigned long )old_fb;
 #line 1994
   if (__cil_tmp61 != __cil_tmp60) {
     {
 #line 1995
     __cil_tmp62 = intel_crtc->pipe;
 #line 1995
     __cil_tmp63 = (int )__cil_tmp62;
 #line 1995
     intel_wait_for_vblank(dev, __cil_tmp63);
 #line 1996
     __mptr___3 = (struct drm_framebuffer  const  *)old_fb;
 #line 1996
     __cil_tmp64 = (struct intel_framebuffer *)__mptr___3;
 #line 1996
     __cil_tmp65 = __cil_tmp64->obj;
 #line 1996
     i915_gem_object_unpin(__cil_tmp65);
     }
   } else {
 
   }
   }
   {
 #line 1999
   __cil_tmp66 = & dev->struct_mutex;
 #line 1999
   mutex_unlock(__cil_tmp66);
   }
   {
 #line 2001
   __cil_tmp67 = (struct drm_master *)0;
 #line 2001
   __cil_tmp68 = (unsigned long )__cil_tmp67;
 #line 2001
   __cil_tmp69 = dev->primary;
 #line 2001
   __cil_tmp70 = __cil_tmp69->master;
 #line 2001
   __cil_tmp71 = (unsigned long )__cil_tmp70;
 #line 2001
   if (__cil_tmp71 == __cil_tmp68) {
 #line 2002
     return (0);
   } else {
 
   }
   }
 #line 2004
   __cil_tmp72 = dev->primary;
 #line 2004
   __cil_tmp73 = __cil_tmp72->master;
 #line 2004
   __cil_tmp74 = __cil_tmp73->driver_priv;
 #line 2004
   master_priv = (struct drm_i915_master_private *)__cil_tmp74;
   {
 #line 2005
   __cil_tmp75 = (struct _drm_i915_sarea *)0;
 #line 2005
   __cil_tmp76 = (unsigned long )__cil_tmp75;
 #line 2005
   __cil_tmp77 = master_priv->sarea_priv;
 #line 2005
   __cil_tmp78 = (unsigned long )__cil_tmp77;
 #line 2005
   if (__cil_tmp78 == __cil_tmp76) {
 #line 2006
     return (0);
   } else {
 
   }
   }
   {
 #line 2008
   __cil_tmp79 = intel_crtc->pipe;
 #line 2008
   __cil_tmp80 = (unsigned int )__cil_tmp79;
 #line 2008
   if (__cil_tmp80 != 0U) {
 #line 2009
     __cil_tmp81 = master_priv->sarea_priv;
 #line 2009
     __cil_tmp81->pipeB_x = x;
 #line 2010
     __cil_tmp82 = master_priv->sarea_priv;
 #line 2010
     __cil_tmp82->pipeB_y = y;
   } else {
 #line 2012
     __cil_tmp83 = master_priv->sarea_priv;
 #line 2012
     __cil_tmp83->pipeA_x = x;
 #line 2013
     __cil_tmp84 = master_priv->sarea_priv;
 #line 2013
     __cil_tmp84->pipeA_y = y;
   }
   }
 #line 2016
   return (0);
 }
 }
 #line 2019 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_set_pll_edp(struct drm_crtc *crtc , int clock ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   u32 dpa_ctl ;
   u32 temp ;
   void *__cil_tmp7 ;
   unsigned int __cil_tmp8 ;
   unsigned int __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   void *__cil_tmp11 ;
   void const volatile   *__cil_tmp12 ;
   void const volatile   *__cil_tmp13 ;
 
   {
   {
 #line 2021
   dev = crtc->dev;
 #line 2022
   __cil_tmp7 = dev->dev_private;
 #line 2022
   dev_priv = (struct drm_i915_private *)__cil_tmp7;
 #line 2025
   drm_ut_debug_printk(4U, "drm", "ironlake_set_pll_edp", "eDP PLL enable for clock %d\n",
                       clock);
 #line 2026
   dpa_ctl = i915_read32___6(dev_priv, 409600U);
 #line 2027
   dpa_ctl = dpa_ctl & 4294770687U;
   }
 #line 2029
   if (clock <= 199999) {
     {
 #line 2031
     dpa_ctl = dpa_ctl | 65536U;
 #line 2038
     temp = i915_read32___6(dev_priv, 286732U);
 #line 2039
     temp = temp & 4294901760U;
 #line 2040
     __cil_tmp8 = temp | 33060U;
 #line 2040
     i915_write32___4(dev_priv, 286732U, __cil_tmp8);
 #line 2042
     temp = i915_read32___6(dev_priv, 286736U);
 #line 2043
     __cil_tmp9 = temp | 1U;
 #line 2043
     i915_write32___4(dev_priv, 286736U, __cil_tmp9);
 #line 2045
     temp = i915_read32___6(dev_priv, 286772U);
 #line 2046
     __cil_tmp10 = temp | 16777216U;
 #line 2046
     i915_write32___4(dev_priv, 286772U, __cil_tmp10);
     }
   } else {
 #line 2048
     dpa_ctl = dpa_ctl;
   }
   {
 #line 2050
   i915_write32___4(dev_priv, 409600U, dpa_ctl);
 #line 2052
   __cil_tmp11 = dev_priv->regs;
 #line 2052
   __cil_tmp12 = (void const volatile   *)__cil_tmp11;
 #line 2052
   __cil_tmp13 = __cil_tmp12 + 409600U;
 #line 2052
   readl(__cil_tmp13);
 #line 2053
   __const_udelay(2147500UL);
   }
 #line 2054
   return;
 }
 }
 #line 2056 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_fdi_normal_train(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   u32 reg ;
   u32 temp ;
   u32 tmp ;
   void *__cil_tmp10 ;
   enum pipe __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   void *__cil_tmp14 ;
   struct drm_i915_private *__cil_tmp15 ;
   struct intel_device_info  const  *__cil_tmp16 ;
   unsigned char *__cil_tmp17 ;
   unsigned char *__cil_tmp18 ;
   unsigned char __cil_tmp19 ;
   unsigned int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   void *__cil_tmp23 ;
   struct drm_i915_private *__cil_tmp24 ;
   enum intel_pch __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   void *__cil_tmp29 ;
   void const volatile   *__cil_tmp30 ;
   void const volatile   *__cil_tmp31 ;
   void *__cil_tmp32 ;
   struct drm_i915_private *__cil_tmp33 ;
   struct intel_device_info  const  *__cil_tmp34 ;
   unsigned char *__cil_tmp35 ;
   unsigned char *__cil_tmp36 ;
   unsigned char __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
 
   {
   {
 #line 2058
   dev = crtc->dev;
 #line 2059
   __cil_tmp10 = dev->dev_private;
 #line 2059
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 2060
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2060
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2061
   __cil_tmp11 = intel_crtc->pipe;
 #line 2061
   pipe = (int )__cil_tmp11;
 #line 2065
   __cil_tmp12 = pipe * 4096;
 #line 2065
   __cil_tmp13 = __cil_tmp12 + 393472;
 #line 2065
   reg = (u32 )__cil_tmp13;
 #line 2066
   temp = i915_read32___6(dev_priv, reg);
   }
   {
 #line 2067
   __cil_tmp14 = dev->dev_private;
 #line 2067
   __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
 #line 2067
   __cil_tmp16 = __cil_tmp15->info;
 #line 2067
   __cil_tmp17 = (unsigned char *)__cil_tmp16;
 #line 2067
   __cil_tmp18 = __cil_tmp17 + 2UL;
 #line 2067
   __cil_tmp19 = *__cil_tmp18;
 #line 2067
   __cil_tmp20 = (unsigned int )__cil_tmp19;
 #line 2067
   if (__cil_tmp20 != 0U) {
 #line 2068
     temp = temp & 4294966527U;
 #line 2069
     temp = temp | 262912U;
   } else {
 #line 2071
     temp = temp & 3489660927U;
 #line 2072
     temp = temp | 805568512U;
   }
   }
   {
 #line 2074
   i915_write32___4(dev_priv, reg, temp);
 #line 2076
   __cil_tmp21 = pipe * 4096;
 #line 2076
   __cil_tmp22 = __cil_tmp21 + 983052;
 #line 2076
   reg = (u32 )__cil_tmp22;
 #line 2077
   temp = i915_read32___6(dev_priv, reg);
   }
   {
 #line 2078
   __cil_tmp23 = dev->dev_private;
 #line 2078
   __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
 #line 2078
   __cil_tmp25 = __cil_tmp24->pch_type;
 #line 2078
   __cil_tmp26 = (unsigned int )__cil_tmp25;
 #line 2078
   if (__cil_tmp26 == 1U) {
 #line 2079
     temp = temp & 4294966527U;
 #line 2080
     temp = temp | 768U;
   } else {
 #line 2082
     temp = temp & 3489660927U;
 #line 2083
     temp = temp | 805306368U;
   }
   }
   {
 #line 2085
   __cil_tmp27 = temp | 64U;
 #line 2085
   i915_write32___4(dev_priv, reg, __cil_tmp27);
 #line 2088
   __cil_tmp28 = (unsigned long )reg;
 #line 2088
   __cil_tmp29 = dev_priv->regs;
 #line 2088
   __cil_tmp30 = (void const volatile   *)__cil_tmp29;
 #line 2088
   __cil_tmp31 = __cil_tmp30 + __cil_tmp28;
 #line 2088
   readl(__cil_tmp31);
 #line 2089
   __const_udelay(4295000UL);
   }
   {
 #line 2092
   __cil_tmp32 = dev->dev_private;
 #line 2092
   __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
 #line 2092
   __cil_tmp34 = __cil_tmp33->info;
 #line 2092
   __cil_tmp35 = (unsigned char *)__cil_tmp34;
 #line 2092
   __cil_tmp36 = __cil_tmp35 + 2UL;
 #line 2092
   __cil_tmp37 = *__cil_tmp36;
 #line 2092
   __cil_tmp38 = (unsigned int )__cil_tmp37;
 #line 2092
   if (__cil_tmp38 != 0U) {
     {
 #line 2093
     tmp = i915_read32___6(dev_priv, reg);
 #line 2093
     __cil_tmp39 = tmp | 201326592U;
 #line 2093
     i915_write32___4(dev_priv, reg, __cil_tmp39);
     }
   } else {
 
   }
   }
 #line 2094
   return;
 }
 }
 #line 2098 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_fdi_link_train(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   u32 reg ;
   u32 temp ;
   u32 tries ;
   void *__cil_tmp11 ;
   enum pipe __cil_tmp12 ;
   enum plane __cil_tmp13 ;
   enum pipe __cil_tmp14 ;
   bool __cil_tmp15 ;
   enum plane __cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   u32 __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   void *__cil_tmp30 ;
   void const volatile   *__cil_tmp31 ;
   void const volatile   *__cil_tmp32 ;
   void *__cil_tmp33 ;
   struct drm_i915_private *__cil_tmp34 ;
   enum intel_pch __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   u32 __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   void *__cil_tmp52 ;
   void const volatile   *__cil_tmp53 ;
   void const volatile   *__cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
 
   {
   {
 #line 2100
   dev = crtc->dev;
 #line 2101
   __cil_tmp11 = dev->dev_private;
 #line 2101
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 2102
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2102
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2103
   __cil_tmp12 = intel_crtc->pipe;
 #line 2103
   pipe = (int )__cil_tmp12;
 #line 2104
   __cil_tmp13 = intel_crtc->plane;
 #line 2104
   plane = (int )__cil_tmp13;
 #line 2108
   __cil_tmp14 = (enum pipe )pipe;
 #line 2108
   __cil_tmp15 = (bool )1;
 #line 2108
   assert_pipe(dev_priv, __cil_tmp14, __cil_tmp15);
 #line 2109
   __cil_tmp16 = (enum plane )plane;
 #line 2109
   assert_plane_enabled(dev_priv, __cil_tmp16);
 #line 2113
   __cil_tmp17 = pipe * 4096;
 #line 2113
   __cil_tmp18 = __cil_tmp17 + 983064;
 #line 2113
   reg = (u32 )__cil_tmp18;
 #line 2114
   temp = i915_read32___6(dev_priv, reg);
 #line 2115
   temp = temp & 4294966783U;
 #line 2116
   temp = temp & 4294967039U;
 #line 2117
   i915_write32___4(dev_priv, reg, temp);
 #line 2118
   i915_read32___6(dev_priv, reg);
 #line 2119
   __const_udelay(644250UL);
 #line 2122
   __cil_tmp19 = pipe * 4096;
 #line 2122
   __cil_tmp20 = __cil_tmp19 + 393472;
 #line 2122
   reg = (u32 )__cil_tmp20;
 #line 2123
   temp = i915_read32___6(dev_priv, reg);
 #line 2124
   temp = temp & 4291297279U;
 #line 2125
   __cil_tmp21 = intel_crtc->fdi_lanes;
 #line 2125
   __cil_tmp22 = __cil_tmp21 + -1;
 #line 2125
   __cil_tmp23 = __cil_tmp22 << 19;
 #line 2125
   __cil_tmp24 = (u32 )__cil_tmp23;
 #line 2125
   temp = __cil_tmp24 | temp;
 #line 2126
   temp = temp & 3489660927U;
 #line 2127
   temp = temp;
 #line 2128
   __cil_tmp25 = temp | 2147483648U;
 #line 2128
   i915_write32___4(dev_priv, reg, __cil_tmp25);
 #line 2130
   __cil_tmp26 = pipe * 4096;
 #line 2130
   __cil_tmp27 = __cil_tmp26 + 983052;
 #line 2130
   reg = (u32 )__cil_tmp27;
 #line 2131
   temp = i915_read32___6(dev_priv, reg);
 #line 2132
   temp = temp & 3489660927U;
 #line 2133
   temp = temp;
 #line 2134
   __cil_tmp28 = temp | 2147483648U;
 #line 2134
   i915_write32___4(dev_priv, reg, __cil_tmp28);
 #line 2136
   __cil_tmp29 = (unsigned long )reg;
 #line 2136
   __cil_tmp30 = dev_priv->regs;
 #line 2136
   __cil_tmp31 = (void const volatile   *)__cil_tmp30;
 #line 2136
   __cil_tmp32 = __cil_tmp31 + __cil_tmp29;
 #line 2136
   readl(__cil_tmp32);
 #line 2137
   __const_udelay(644250UL);
   }
   {
 #line 2140
   __cil_tmp33 = dev->dev_private;
 #line 2140
   __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
 #line 2140
   __cil_tmp35 = __cil_tmp34->pch_type;
 #line 2140
   __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 2140
   if (__cil_tmp36 == 0U) {
     {
 #line 2141
     __cil_tmp37 = pipe + 198659;
 #line 2141
     __cil_tmp38 = __cil_tmp37 * 4;
 #line 2141
     __cil_tmp39 = (u32 )__cil_tmp38;
 #line 2141
     i915_write32___4(dev_priv, __cil_tmp39, 2U);
 #line 2142
     __cil_tmp40 = pipe + 198659;
 #line 2142
     __cil_tmp41 = __cil_tmp40 * 4;
 #line 2142
     __cil_tmp42 = (u32 )__cil_tmp41;
 #line 2142
     i915_write32___4(dev_priv, __cil_tmp42, 3U);
     }
   } else {
 
   }
   }
 #line 2146
   __cil_tmp43 = pipe * 4096;
 #line 2146
   __cil_tmp44 = __cil_tmp43 + 983060;
 #line 2146
   reg = (u32 )__cil_tmp44;
 #line 2147
   tries = 0U;
 #line 2147
   goto ldv_38834;
   ldv_38833: 
   {
 #line 2148
   temp = i915_read32___6(dev_priv, reg);
 #line 2149
   drm_ut_debug_printk(4U, "drm", "ironlake_fdi_link_train", "FDI_RX_IIR 0x%x\n", temp);
   }
   {
 #line 2151
   __cil_tmp45 = temp & 256U;
 #line 2151
   if (__cil_tmp45 != 0U) {
     {
 #line 2152
     drm_ut_debug_printk(4U, "drm", "ironlake_fdi_link_train", "FDI train 1 done.\n");
 #line 2153
     __cil_tmp46 = temp | 256U;
 #line 2153
     i915_write32___4(dev_priv, reg, __cil_tmp46);
     }
 #line 2154
     goto ldv_38832;
   } else {
 
   }
   }
 #line 2147
   tries = tries + 1U;
   ldv_38834: ;
 #line 2147
   if (tries <= 4U) {
 #line 2148
     goto ldv_38833;
   } else {
 #line 2150
     goto ldv_38832;
   }
   ldv_38832: ;
 #line 2157
   if (tries == 5U) {
     {
 #line 2158
     drm_err("ironlake_fdi_link_train", "FDI train 1 fail!\n");
     }
   } else {
 
   }
   {
 #line 2161
   __cil_tmp47 = pipe * 4096;
 #line 2161
   __cil_tmp48 = __cil_tmp47 + 393472;
 #line 2161
   reg = (u32 )__cil_tmp48;
 #line 2162
   temp = i915_read32___6(dev_priv, reg);
 #line 2163
   temp = temp & 3489660927U;
 #line 2164
   temp = temp | 268435456U;
 #line 2165
   i915_write32___4(dev_priv, reg, temp);
 #line 2167
   __cil_tmp49 = pipe * 4096;
 #line 2167
   __cil_tmp50 = __cil_tmp49 + 983052;
 #line 2167
   reg = (u32 )__cil_tmp50;
 #line 2168
   temp = i915_read32___6(dev_priv, reg);
 #line 2169
   temp = temp & 3489660927U;
 #line 2170
   temp = temp | 268435456U;
 #line 2171
   i915_write32___4(dev_priv, reg, temp);
 #line 2173
   __cil_tmp51 = (unsigned long )reg;
 #line 2173
   __cil_tmp52 = dev_priv->regs;
 #line 2173
   __cil_tmp53 = (void const volatile   *)__cil_tmp52;
 #line 2173
   __cil_tmp54 = __cil_tmp53 + __cil_tmp51;
 #line 2173
   readl(__cil_tmp54);
 #line 2174
   __const_udelay(644250UL);
 #line 2176
   __cil_tmp55 = pipe * 4096;
 #line 2176
   __cil_tmp56 = __cil_tmp55 + 983060;
 #line 2176
   reg = (u32 )__cil_tmp56;
 #line 2177
   tries = 0U;
   }
 #line 2177
   goto ldv_38837;
   ldv_38836: 
   {
 #line 2178
   temp = i915_read32___6(dev_priv, reg);
 #line 2179
   drm_ut_debug_printk(4U, "drm", "ironlake_fdi_link_train", "FDI_RX_IIR 0x%x\n", temp);
   }
   {
 #line 2181
   __cil_tmp57 = temp & 512U;
 #line 2181
   if (__cil_tmp57 != 0U) {
     {
 #line 2182
     __cil_tmp58 = temp | 512U;
 #line 2182
     i915_write32___4(dev_priv, reg, __cil_tmp58);
 #line 2183
     drm_ut_debug_printk(4U, "drm", "ironlake_fdi_link_train", "FDI train 2 done.\n");
     }
 #line 2184
     goto ldv_38835;
   } else {
 
   }
   }
 #line 2177
   tries = tries + 1U;
   ldv_38837: ;
 #line 2177
   if (tries <= 4U) {
 #line 2178
     goto ldv_38836;
   } else {
 #line 2180
     goto ldv_38835;
   }
   ldv_38835: ;
 #line 2187
   if (tries == 5U) {
     {
 #line 2188
     drm_err("ironlake_fdi_link_train", "FDI train 2 fail!\n");
     }
   } else {
 
   }
   {
 #line 2190
   drm_ut_debug_printk(4U, "drm", "ironlake_fdi_link_train", "FDI train done\n");
   }
 #line 2191
   return;
 }
 }
 #line 2194 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int const   snb_b_fdi_train_param[4U]  = {      (int const   )0,      (int const   )243269632,      (int const   )239075328,      (int const   )234881024};
 #line 2202 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void gen6_fdi_link_train(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   u32 reg ;
   u32 temp ;
   u32 i ;
   void *__cil_tmp10 ;
   enum pipe __cil_tmp11 ;
   int __cil_tmp12 ;
   int __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   void *__cil_tmp15 ;
   void const volatile   *__cil_tmp16 ;
   void const volatile   *__cil_tmp17 ;
   int __cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   u32 __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   void *__cil_tmp27 ;
   struct drm_i915_private *__cil_tmp28 ;
   enum intel_pch __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   void *__cil_tmp33 ;
   void const volatile   *__cil_tmp34 ;
   void const volatile   *__cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   void *__cil_tmp40 ;
   void const volatile   *__cil_tmp41 ;
   void const volatile   *__cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   void *__cil_tmp49 ;
   struct drm_i915_private *__cil_tmp50 ;
   struct intel_device_info  const  *__cil_tmp51 ;
   u8 __cil_tmp52 ;
   unsigned char __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   void *__cil_tmp57 ;
   struct drm_i915_private *__cil_tmp58 ;
   enum intel_pch __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   void *__cil_tmp62 ;
   void const volatile   *__cil_tmp63 ;
   void const volatile   *__cil_tmp64 ;
   int __cil_tmp65 ;
   int __cil_tmp66 ;
   u32 __cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   void *__cil_tmp69 ;
   void const volatile   *__cil_tmp70 ;
   void const volatile   *__cil_tmp71 ;
   int __cil_tmp72 ;
   int __cil_tmp73 ;
   unsigned int __cil_tmp74 ;
   unsigned int __cil_tmp75 ;
 
   {
   {
 #line 2204
   dev = crtc->dev;
 #line 2205
   __cil_tmp10 = dev->dev_private;
 #line 2205
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 2206
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2206
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2207
   __cil_tmp11 = intel_crtc->pipe;
 #line 2207
   pipe = (int )__cil_tmp11;
 #line 2212
   __cil_tmp12 = pipe * 4096;
 #line 2212
   __cil_tmp13 = __cil_tmp12 + 983064;
 #line 2212
   reg = (u32 )__cil_tmp13;
 #line 2213
   temp = i915_read32___6(dev_priv, reg);
 #line 2214
   temp = temp & 4294966783U;
 #line 2215
   temp = temp & 4294967039U;
 #line 2216
   i915_write32___4(dev_priv, reg, temp);
 #line 2218
   __cil_tmp14 = (unsigned long )reg;
 #line 2218
   __cil_tmp15 = dev_priv->regs;
 #line 2218
   __cil_tmp16 = (void const volatile   *)__cil_tmp15;
 #line 2218
   __cil_tmp17 = __cil_tmp16 + __cil_tmp14;
 #line 2218
   readl(__cil_tmp17);
 #line 2219
   __const_udelay(644250UL);
 #line 2222
   __cil_tmp18 = pipe * 4096;
 #line 2222
   __cil_tmp19 = __cil_tmp18 + 393472;
 #line 2222
   reg = (u32 )__cil_tmp19;
 #line 2223
   temp = i915_read32___6(dev_priv, reg);
 #line 2224
   temp = temp & 4291297279U;
 #line 2225
   __cil_tmp20 = intel_crtc->fdi_lanes;
 #line 2225
   __cil_tmp21 = __cil_tmp20 + -1;
 #line 2225
   __cil_tmp22 = __cil_tmp21 << 19;
 #line 2225
   __cil_tmp23 = (u32 )__cil_tmp22;
 #line 2225
   temp = __cil_tmp23 | temp;
 #line 2226
   temp = temp & 3489660927U;
 #line 2227
   temp = temp;
 #line 2228
   temp = temp & 4030726143U;
 #line 2230
   temp = temp;
 #line 2231
   __cil_tmp24 = temp | 2147483648U;
 #line 2231
   i915_write32___4(dev_priv, reg, __cil_tmp24);
 #line 2233
   __cil_tmp25 = pipe * 4096;
 #line 2233
   __cil_tmp26 = __cil_tmp25 + 983052;
 #line 2233
   reg = (u32 )__cil_tmp26;
 #line 2234
   temp = i915_read32___6(dev_priv, reg);
   }
   {
 #line 2235
   __cil_tmp27 = dev->dev_private;
 #line 2235
   __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
 #line 2235
   __cil_tmp29 = __cil_tmp28->pch_type;
 #line 2235
   __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 2235
   if (__cil_tmp30 == 1U) {
 #line 2236
     temp = temp & 4294966527U;
 #line 2237
     temp = temp;
   } else {
 #line 2239
     temp = temp & 3489660927U;
 #line 2240
     temp = temp;
   }
   }
   {
 #line 2242
   __cil_tmp31 = temp | 2147483648U;
 #line 2242
   i915_write32___4(dev_priv, reg, __cil_tmp31);
 #line 2244
   __cil_tmp32 = (unsigned long )reg;
 #line 2244
   __cil_tmp33 = dev_priv->regs;
 #line 2244
   __cil_tmp34 = (void const volatile   *)__cil_tmp33;
 #line 2244
   __cil_tmp35 = __cil_tmp34 + __cil_tmp32;
 #line 2244
   readl(__cil_tmp35);
 #line 2245
   __const_udelay(644250UL);
 #line 2247
   i = 0U;
   }
 #line 2247
   goto ldv_38854;
   ldv_38853: 
   {
 #line 2248
   __cil_tmp36 = pipe * 4096;
 #line 2248
   __cil_tmp37 = __cil_tmp36 + 393472;
 #line 2248
   reg = (u32 )__cil_tmp37;
 #line 2249
   temp = i915_read32___6(dev_priv, reg);
 #line 2250
   temp = temp & 4030726143U;
 #line 2251
   __cil_tmp38 = (u32 )snb_b_fdi_train_param[i];
 #line 2251
   temp = __cil_tmp38 | temp;
 #line 2252
   i915_write32___4(dev_priv, reg, temp);
 #line 2254
   __cil_tmp39 = (unsigned long )reg;
 #line 2254
   __cil_tmp40 = dev_priv->regs;
 #line 2254
   __cil_tmp41 = (void const volatile   *)__cil_tmp40;
 #line 2254
   __cil_tmp42 = __cil_tmp41 + __cil_tmp39;
 #line 2254
   readl(__cil_tmp42);
 #line 2255
   __const_udelay(2147500UL);
 #line 2257
   __cil_tmp43 = pipe * 4096;
 #line 2257
   __cil_tmp44 = __cil_tmp43 + 983060;
 #line 2257
   reg = (u32 )__cil_tmp44;
 #line 2258
   temp = i915_read32___6(dev_priv, reg);
 #line 2259
   drm_ut_debug_printk(4U, "drm", "gen6_fdi_link_train", "FDI_RX_IIR 0x%x\n", temp);
   }
   {
 #line 2261
   __cil_tmp45 = temp & 256U;
 #line 2261
   if (__cil_tmp45 != 0U) {
     {
 #line 2262
     __cil_tmp46 = temp | 256U;
 #line 2262
     i915_write32___4(dev_priv, reg, __cil_tmp46);
 #line 2263
     drm_ut_debug_printk(4U, "drm", "gen6_fdi_link_train", "FDI train 1 done.\n");
     }
 #line 2264
     goto ldv_38852;
   } else {
 
   }
   }
 #line 2247
   i = i + 1U;
   ldv_38854: ;
 #line 2247
   if (i <= 3U) {
 #line 2248
     goto ldv_38853;
   } else {
 #line 2250
     goto ldv_38852;
   }
   ldv_38852: ;
 #line 2267
   if (i == 4U) {
     {
 #line 2268
     drm_err("gen6_fdi_link_train", "FDI train 1 fail!\n");
     }
   } else {
 
   }
   {
 #line 2271
   __cil_tmp47 = pipe * 4096;
 #line 2271
   __cil_tmp48 = __cil_tmp47 + 393472;
 #line 2271
   reg = (u32 )__cil_tmp48;
 #line 2272
   temp = i915_read32___6(dev_priv, reg);
 #line 2273
   temp = temp & 3489660927U;
 #line 2274
   temp = temp | 268435456U;
   }
   {
 #line 2275
   __cil_tmp49 = dev->dev_private;
 #line 2275
   __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
 #line 2275
   __cil_tmp51 = __cil_tmp50->info;
 #line 2275
   __cil_tmp52 = __cil_tmp51->gen;
 #line 2275
   __cil_tmp53 = (unsigned char )__cil_tmp52;
 #line 2275
   __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 2275
   if (__cil_tmp54 == 6U) {
 #line 2276
     temp = temp & 4030726143U;
 #line 2278
     temp = temp;
   } else {
 
   }
   }
   {
 #line 2280
   i915_write32___4(dev_priv, reg, temp);
 #line 2282
   __cil_tmp55 = pipe * 4096;
 #line 2282
   __cil_tmp56 = __cil_tmp55 + 983052;
 #line 2282
   reg = (u32 )__cil_tmp56;
 #line 2283
   temp = i915_read32___6(dev_priv, reg);
   }
   {
 #line 2284
   __cil_tmp57 = dev->dev_private;
 #line 2284
   __cil_tmp58 = (struct drm_i915_private *)__cil_tmp57;
 #line 2284
   __cil_tmp59 = __cil_tmp58->pch_type;
 #line 2284
   __cil_tmp60 = (unsigned int )__cil_tmp59;
 #line 2284
   if (__cil_tmp60 == 1U) {
 #line 2285
     temp = temp & 4294966527U;
 #line 2286
     temp = temp | 256U;
   } else {
 #line 2288
     temp = temp & 3489660927U;
 #line 2289
     temp = temp | 268435456U;
   }
   }
   {
 #line 2291
   i915_write32___4(dev_priv, reg, temp);
 #line 2293
   __cil_tmp61 = (unsigned long )reg;
 #line 2293
   __cil_tmp62 = dev_priv->regs;
 #line 2293
   __cil_tmp63 = (void const volatile   *)__cil_tmp62;
 #line 2293
   __cil_tmp64 = __cil_tmp63 + __cil_tmp61;
 #line 2293
   readl(__cil_tmp64);
 #line 2294
   __const_udelay(644250UL);
 #line 2296
   i = 0U;
   }
 #line 2296
   goto ldv_38857;
   ldv_38856: 
   {
 #line 2297
   __cil_tmp65 = pipe * 4096;
 #line 2297
   __cil_tmp66 = __cil_tmp65 + 393472;
 #line 2297
   reg = (u32 )__cil_tmp66;
 #line 2298
   temp = i915_read32___6(dev_priv, reg);
 #line 2299
   temp = temp & 4030726143U;
 #line 2300
   __cil_tmp67 = (u32 )snb_b_fdi_train_param[i];
 #line 2300
   temp = __cil_tmp67 | temp;
 #line 2301
   i915_write32___4(dev_priv, reg, temp);
 #line 2303
   __cil_tmp68 = (unsigned long )reg;
 #line 2303
   __cil_tmp69 = dev_priv->regs;
 #line 2303
   __cil_tmp70 = (void const volatile   *)__cil_tmp69;
 #line 2303
   __cil_tmp71 = __cil_tmp70 + __cil_tmp68;
 #line 2303
   readl(__cil_tmp71);
 #line 2304
   __const_udelay(2147500UL);
 #line 2306
   __cil_tmp72 = pipe * 4096;
 #line 2306
   __cil_tmp73 = __cil_tmp72 + 983060;
 #line 2306
   reg = (u32 )__cil_tmp73;
 #line 2307
   temp = i915_read32___6(dev_priv, reg);
 #line 2308
   drm_ut_debug_printk(4U, "drm", "gen6_fdi_link_train", "FDI_RX_IIR 0x%x\n", temp);
   }
   {
 #line 2310
   __cil_tmp74 = temp & 512U;
 #line 2310
   if (__cil_tmp74 != 0U) {
     {
 #line 2311
     __cil_tmp75 = temp | 512U;
 #line 2311
     i915_write32___4(dev_priv, reg, __cil_tmp75);
 #line 2312
     drm_ut_debug_printk(4U, "drm", "gen6_fdi_link_train", "FDI train 2 done.\n");
     }
 #line 2313
     goto ldv_38855;
   } else {
 
   }
   }
 #line 2296
   i = i + 1U;
   ldv_38857: ;
 #line 2296
   if (i <= 3U) {
 #line 2297
     goto ldv_38856;
   } else {
 #line 2299
     goto ldv_38855;
   }
   ldv_38855: ;
 #line 2316
   if (i == 4U) {
     {
 #line 2317
     drm_err("gen6_fdi_link_train", "FDI train 2 fail!\n");
     }
   } else {
 
   }
   {
 #line 2319
   drm_ut_debug_printk(4U, "drm", "gen6_fdi_link_train", "FDI train done.\n");
   }
 #line 2320
   return;
 }
 }
 #line 2323 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   u32 reg ;
   u32 temp ;
   u32 i ;
   u32 tmp ;
   void *__cil_tmp11 ;
   enum pipe __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   void *__cil_tmp16 ;
   void const volatile   *__cil_tmp17 ;
   void const volatile   *__cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   u32 __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   void *__cil_tmp30 ;
   void const volatile   *__cil_tmp31 ;
   void const volatile   *__cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   u32 __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   void *__cil_tmp37 ;
   void const volatile   *__cil_tmp38 ;
   void const volatile   *__cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   int __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   void *__cil_tmp51 ;
   void const volatile   *__cil_tmp52 ;
   void const volatile   *__cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   u32 __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   void *__cil_tmp58 ;
   void const volatile   *__cil_tmp59 ;
   void const volatile   *__cil_tmp60 ;
   int __cil_tmp61 ;
   int __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
 
   {
   {
 #line 2325
   dev = crtc->dev;
 #line 2326
   __cil_tmp11 = dev->dev_private;
 #line 2326
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 2327
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2327
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2328
   __cil_tmp12 = intel_crtc->pipe;
 #line 2328
   pipe = (int )__cil_tmp12;
 #line 2333
   __cil_tmp13 = pipe * 4096;
 #line 2333
   __cil_tmp14 = __cil_tmp13 + 983064;
 #line 2333
   reg = (u32 )__cil_tmp14;
 #line 2334
   temp = i915_read32___6(dev_priv, reg);
 #line 2335
   temp = temp & 4294966783U;
 #line 2336
   temp = temp & 4294967039U;
 #line 2337
   i915_write32___4(dev_priv, reg, temp);
 #line 2339
   __cil_tmp15 = (unsigned long )reg;
 #line 2339
   __cil_tmp16 = dev_priv->regs;
 #line 2339
   __cil_tmp17 = (void const volatile   *)__cil_tmp16;
 #line 2339
   __cil_tmp18 = __cil_tmp17 + __cil_tmp15;
 #line 2339
   readl(__cil_tmp18);
 #line 2340
   __const_udelay(644250UL);
 #line 2343
   __cil_tmp19 = pipe * 4096;
 #line 2343
   __cil_tmp20 = __cil_tmp19 + 393472;
 #line 2343
   reg = (u32 )__cil_tmp20;
 #line 2344
   temp = i915_read32___6(dev_priv, reg);
 #line 2345
   temp = temp & 4291297279U;
 #line 2346
   __cil_tmp21 = intel_crtc->fdi_lanes;
 #line 2346
   __cil_tmp22 = __cil_tmp21 + -1;
 #line 2346
   __cil_tmp23 = __cil_tmp22 << 19;
 #line 2346
   __cil_tmp24 = (u32 )__cil_tmp23;
 #line 2346
   temp = __cil_tmp24 | temp;
 #line 2347
   temp = temp & 4294965503U;
 #line 2348
   temp = temp;
 #line 2349
   temp = temp & 4030726143U;
 #line 2350
   temp = temp;
 #line 2351
   __cil_tmp25 = temp | 2147483648U;
 #line 2351
   i915_write32___4(dev_priv, reg, __cil_tmp25);
 #line 2353
   __cil_tmp26 = pipe * 4096;
 #line 2353
   __cil_tmp27 = __cil_tmp26 + 983052;
 #line 2353
   reg = (u32 )__cil_tmp27;
 #line 2354
   temp = i915_read32___6(dev_priv, reg);
 #line 2355
   temp = temp & 4294966271U;
 #line 2356
   temp = temp & 4294966527U;
 #line 2357
   temp = temp;
 #line 2358
   __cil_tmp28 = temp | 2147483648U;
 #line 2358
   i915_write32___4(dev_priv, reg, __cil_tmp28);
 #line 2360
   __cil_tmp29 = (unsigned long )reg;
 #line 2360
   __cil_tmp30 = dev_priv->regs;
 #line 2360
   __cil_tmp31 = (void const volatile   *)__cil_tmp30;
 #line 2360
   __cil_tmp32 = __cil_tmp31 + __cil_tmp29;
 #line 2360
   readl(__cil_tmp32);
 #line 2361
   __const_udelay(644250UL);
 #line 2363
   i = 0U;
   }
 #line 2363
   goto ldv_38873;
   ldv_38872: 
   {
 #line 2364
   __cil_tmp33 = pipe * 4096;
 #line 2364
   __cil_tmp34 = __cil_tmp33 + 393472;
 #line 2364
   reg = (u32 )__cil_tmp34;
 #line 2365
   temp = i915_read32___6(dev_priv, reg);
 #line 2366
   temp = temp & 4030726143U;
 #line 2367
   __cil_tmp35 = (u32 )snb_b_fdi_train_param[i];
 #line 2367
   temp = __cil_tmp35 | temp;
 #line 2368
   i915_write32___4(dev_priv, reg, temp);
 #line 2370
   __cil_tmp36 = (unsigned long )reg;
 #line 2370
   __cil_tmp37 = dev_priv->regs;
 #line 2370
   __cil_tmp38 = (void const volatile   *)__cil_tmp37;
 #line 2370
   __cil_tmp39 = __cil_tmp38 + __cil_tmp36;
 #line 2370
   readl(__cil_tmp39);
 #line 2371
   __const_udelay(2147500UL);
 #line 2373
   __cil_tmp40 = pipe * 4096;
 #line 2373
   __cil_tmp41 = __cil_tmp40 + 983060;
 #line 2373
   reg = (u32 )__cil_tmp41;
 #line 2374
   temp = i915_read32___6(dev_priv, reg);
 #line 2375
   drm_ut_debug_printk(4U, "drm", "ivb_manual_fdi_link_train", "FDI_RX_IIR 0x%x\n",
                       temp);
   }
   {
 #line 2377
   __cil_tmp42 = temp & 256U;
 #line 2377
   if (__cil_tmp42 != 0U) {
     {
 #line 2379
     __cil_tmp43 = temp | 256U;
 #line 2379
     i915_write32___4(dev_priv, reg, __cil_tmp43);
 #line 2380
     drm_ut_debug_printk(4U, "drm", "ivb_manual_fdi_link_train", "FDI train 1 done.\n");
     }
 #line 2381
     goto ldv_38871;
   } else {
     {
 #line 2377
     tmp = i915_read32___6(dev_priv, reg);
     }
     {
 #line 2377
     __cil_tmp44 = tmp & 256U;
 #line 2377
     if (__cil_tmp44 != 0U) {
       {
 #line 2379
       __cil_tmp45 = temp | 256U;
 #line 2379
       i915_write32___4(dev_priv, reg, __cil_tmp45);
 #line 2380
       drm_ut_debug_printk(4U, "drm", "ivb_manual_fdi_link_train", "FDI train 1 done.\n");
       }
 #line 2381
       goto ldv_38871;
     } else {
 
     }
     }
   }
   }
 #line 2363
   i = i + 1U;
   ldv_38873: ;
 #line 2363
   if (i <= 3U) {
 #line 2364
     goto ldv_38872;
   } else {
 #line 2366
     goto ldv_38871;
   }
   ldv_38871: ;
 #line 2384
   if (i == 4U) {
     {
 #line 2385
     drm_err("ivb_manual_fdi_link_train", "FDI train 1 fail!\n");
     }
   } else {
 
   }
   {
 #line 2388
   __cil_tmp46 = pipe * 4096;
 #line 2388
   __cil_tmp47 = __cil_tmp46 + 393472;
 #line 2388
   reg = (u32 )__cil_tmp47;
 #line 2389
   temp = i915_read32___6(dev_priv, reg);
 #line 2390
   temp = temp & 4294966527U;
 #line 2391
   temp = temp | 256U;
 #line 2392
   temp = temp & 4030726143U;
 #line 2393
   temp = temp;
 #line 2394
   i915_write32___4(dev_priv, reg, temp);
 #line 2396
   __cil_tmp48 = pipe * 4096;
 #line 2396
   __cil_tmp49 = __cil_tmp48 + 983052;
 #line 2396
   reg = (u32 )__cil_tmp49;
 #line 2397
   temp = i915_read32___6(dev_priv, reg);
 #line 2398
   temp = temp & 4294966527U;
 #line 2399
   temp = temp | 256U;
 #line 2400
   i915_write32___4(dev_priv, reg, temp);
 #line 2402
   __cil_tmp50 = (unsigned long )reg;
 #line 2402
   __cil_tmp51 = dev_priv->regs;
 #line 2402
   __cil_tmp52 = (void const volatile   *)__cil_tmp51;
 #line 2402
   __cil_tmp53 = __cil_tmp52 + __cil_tmp50;
 #line 2402
   readl(__cil_tmp53);
 #line 2403
   __const_udelay(644250UL);
 #line 2405
   i = 0U;
   }
 #line 2405
   goto ldv_38876;
   ldv_38875: 
   {
 #line 2406
   __cil_tmp54 = pipe * 4096;
 #line 2406
   __cil_tmp55 = __cil_tmp54 + 393472;
 #line 2406
   reg = (u32 )__cil_tmp55;
 #line 2407
   temp = i915_read32___6(dev_priv, reg);
 #line 2408
   temp = temp & 4030726143U;
 #line 2409
   __cil_tmp56 = (u32 )snb_b_fdi_train_param[i];
 #line 2409
   temp = __cil_tmp56 | temp;
 #line 2410
   i915_write32___4(dev_priv, reg, temp);
 #line 2412
   __cil_tmp57 = (unsigned long )reg;
 #line 2412
   __cil_tmp58 = dev_priv->regs;
 #line 2412
   __cil_tmp59 = (void const volatile   *)__cil_tmp58;
 #line 2412
   __cil_tmp60 = __cil_tmp59 + __cil_tmp57;
 #line 2412
   readl(__cil_tmp60);
 #line 2413
   __const_udelay(2147500UL);
 #line 2415
   __cil_tmp61 = pipe * 4096;
 #line 2415
   __cil_tmp62 = __cil_tmp61 + 983060;
 #line 2415
   reg = (u32 )__cil_tmp62;
 #line 2416
   temp = i915_read32___6(dev_priv, reg);
 #line 2417
   drm_ut_debug_printk(4U, "drm", "ivb_manual_fdi_link_train", "FDI_RX_IIR 0x%x\n",
                       temp);
   }
   {
 #line 2419
   __cil_tmp63 = temp & 512U;
 #line 2419
   if (__cil_tmp63 != 0U) {
     {
 #line 2420
     __cil_tmp64 = temp | 512U;
 #line 2420
     i915_write32___4(dev_priv, reg, __cil_tmp64);
 #line 2421
     drm_ut_debug_printk(4U, "drm", "ivb_manual_fdi_link_train", "FDI train 2 done.\n");
     }
 #line 2422
     goto ldv_38874;
   } else {
 
   }
   }
 #line 2405
   i = i + 1U;
   ldv_38876: ;
 #line 2405
   if (i <= 3U) {
 #line 2406
     goto ldv_38875;
   } else {
 #line 2408
     goto ldv_38874;
   }
   ldv_38874: ;
 #line 2425
   if (i == 4U) {
     {
 #line 2426
     drm_err("ivb_manual_fdi_link_train", "FDI train 2 fail!\n");
     }
   } else {
 
   }
   {
 #line 2428
   drm_ut_debug_printk(4U, "drm", "ivb_manual_fdi_link_train", "FDI train done.\n");
   }
 #line 2429
   return;
 }
 }
 #line 2431 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   u32 reg ;
   u32 temp ;
   u32 tmp ;
   u32 tmp___0 ;
   void *__cil_tmp11 ;
   enum pipe __cil_tmp12 ;
   int __cil_tmp13 ;
   int __cil_tmp14 ;
   u32 __cil_tmp15 ;
   int __cil_tmp16 ;
   int __cil_tmp17 ;
   u32 __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   u32 __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   u32 __cil_tmp28 ;
   unsigned int __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   void *__cil_tmp33 ;
   void const volatile   *__cil_tmp34 ;
   void const volatile   *__cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   void *__cil_tmp38 ;
   void const volatile   *__cil_tmp39 ;
   void const volatile   *__cil_tmp40 ;
   int __cil_tmp41 ;
   int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   void *__cil_tmp46 ;
   void const volatile   *__cil_tmp47 ;
   void const volatile   *__cil_tmp48 ;
 
   {
   {
 #line 2433
   dev = crtc->dev;
 #line 2434
   __cil_tmp11 = dev->dev_private;
 #line 2434
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 2435
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2435
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2436
   __cil_tmp12 = intel_crtc->pipe;
 #line 2436
   pipe = (int )__cil_tmp12;
 #line 2440
   __cil_tmp13 = pipe * 4096;
 #line 2440
   __cil_tmp14 = __cil_tmp13 + 393264;
 #line 2440
   __cil_tmp15 = (u32 )__cil_tmp14;
 #line 2440
   tmp = i915_read32___6(dev_priv, __cil_tmp15);
 #line 2440
   __cil_tmp16 = pipe * 4096;
 #line 2440
   __cil_tmp17 = __cil_tmp16 + 983088;
 #line 2440
   __cil_tmp18 = (u32 )__cil_tmp17;
 #line 2440
   __cil_tmp19 = tmp & 2113929216U;
 #line 2440
   i915_write32___4(dev_priv, __cil_tmp18, __cil_tmp19);
 #line 2444
   __cil_tmp20 = pipe * 4096;
 #line 2444
   __cil_tmp21 = __cil_tmp20 + 983052;
 #line 2444
   reg = (u32 )__cil_tmp21;
 #line 2445
   temp = i915_read32___6(dev_priv, reg);
 #line 2446
   temp = temp & 4290838527U;
 #line 2447
   __cil_tmp22 = intel_crtc->fdi_lanes;
 #line 2447
   __cil_tmp23 = __cil_tmp22 + -1;
 #line 2447
   __cil_tmp24 = __cil_tmp23 << 19;
 #line 2447
   __cil_tmp25 = (u32 )__cil_tmp24;
 #line 2447
   temp = __cil_tmp25 | temp;
 #line 2448
   __cil_tmp26 = pipe * 4096;
 #line 2448
   __cil_tmp27 = __cil_tmp26 + 458760;
 #line 2448
   __cil_tmp28 = (u32 )__cil_tmp27;
 #line 2448
   tmp___0 = i915_read32___6(dev_priv, __cil_tmp28);
 #line 2448
   __cil_tmp29 = tmp___0 & 224U;
 #line 2448
   __cil_tmp30 = __cil_tmp29 << 11;
 #line 2448
   temp = __cil_tmp30 | temp;
 #line 2449
   __cil_tmp31 = temp | 8192U;
 #line 2449
   i915_write32___4(dev_priv, reg, __cil_tmp31);
 #line 2451
   __cil_tmp32 = (unsigned long )reg;
 #line 2451
   __cil_tmp33 = dev_priv->regs;
 #line 2451
   __cil_tmp34 = (void const volatile   *)__cil_tmp33;
 #line 2451
   __cil_tmp35 = __cil_tmp34 + __cil_tmp32;
 #line 2451
   readl(__cil_tmp35);
 #line 2452
   __const_udelay(859000UL);
 #line 2455
   temp = i915_read32___6(dev_priv, reg);
 #line 2456
   __cil_tmp36 = temp | 16U;
 #line 2456
   i915_write32___4(dev_priv, reg, __cil_tmp36);
 #line 2458
   __cil_tmp37 = (unsigned long )reg;
 #line 2458
   __cil_tmp38 = dev_priv->regs;
 #line 2458
   __cil_tmp39 = (void const volatile   *)__cil_tmp38;
 #line 2458
   __cil_tmp40 = __cil_tmp39 + __cil_tmp37;
 #line 2458
   readl(__cil_tmp40);
 #line 2459
   __const_udelay(859000UL);
 #line 2462
   __cil_tmp41 = pipe * 4096;
 #line 2462
   __cil_tmp42 = __cil_tmp41 + 393472;
 #line 2462
   reg = (u32 )__cil_tmp42;
 #line 2463
   temp = i915_read32___6(dev_priv, reg);
   }
   {
 #line 2464
   __cil_tmp43 = temp & 16384U;
 #line 2464
   if (__cil_tmp43 == 0U) {
     {
 #line 2465
     __cil_tmp44 = temp | 16384U;
 #line 2465
     i915_write32___4(dev_priv, reg, __cil_tmp44);
 #line 2467
     __cil_tmp45 = (unsigned long )reg;
 #line 2467
     __cil_tmp46 = dev_priv->regs;
 #line 2467
     __cil_tmp47 = (void const volatile   *)__cil_tmp46;
 #line 2467
     __cil_tmp48 = __cil_tmp47 + __cil_tmp45;
 #line 2467
     readl(__cil_tmp48);
 #line 2468
     __const_udelay(429500UL);
     }
   } else {
 
   }
   }
 #line 2470
   return;
 }
 }
 #line 2472 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_fdi_disable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   u32 reg ;
   u32 temp ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp12 ;
   enum pipe __cil_tmp13 ;
   int __cil_tmp14 ;
   int __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   void *__cil_tmp18 ;
   void const volatile   *__cil_tmp19 ;
   void const volatile   *__cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   u32 __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   void *__cil_tmp30 ;
   void const volatile   *__cil_tmp31 ;
   void const volatile   *__cil_tmp32 ;
   void *__cil_tmp33 ;
   struct drm_i915_private *__cil_tmp34 ;
   enum intel_pch __cil_tmp35 ;
   unsigned int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   u32 __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   int __cil_tmp44 ;
   int __cil_tmp45 ;
   u32 __cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   void *__cil_tmp51 ;
   struct drm_i915_private *__cil_tmp52 ;
   enum intel_pch __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   u32 __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned long __cil_tmp60 ;
   void *__cil_tmp61 ;
   void const volatile   *__cil_tmp62 ;
   void const volatile   *__cil_tmp63 ;
 
   {
   {
 #line 2474
   dev = crtc->dev;
 #line 2475
   __cil_tmp12 = dev->dev_private;
 #line 2475
   dev_priv = (struct drm_i915_private *)__cil_tmp12;
 #line 2476
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2476
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2477
   __cil_tmp13 = intel_crtc->pipe;
 #line 2477
   pipe = (int )__cil_tmp13;
 #line 2481
   __cil_tmp14 = pipe * 4096;
 #line 2481
   __cil_tmp15 = __cil_tmp14 + 393472;
 #line 2481
   reg = (u32 )__cil_tmp15;
 #line 2482
   temp = i915_read32___6(dev_priv, reg);
 #line 2483
   __cil_tmp16 = temp & 2147483647U;
 #line 2483
   i915_write32___4(dev_priv, reg, __cil_tmp16);
 #line 2484
   __cil_tmp17 = (unsigned long )reg;
 #line 2484
   __cil_tmp18 = dev_priv->regs;
 #line 2484
   __cil_tmp19 = (void const volatile   *)__cil_tmp18;
 #line 2484
   __cil_tmp20 = __cil_tmp19 + __cil_tmp17;
 #line 2484
   readl(__cil_tmp20);
 #line 2486
   __cil_tmp21 = pipe * 4096;
 #line 2486
   __cil_tmp22 = __cil_tmp21 + 983052;
 #line 2486
   reg = (u32 )__cil_tmp22;
 #line 2487
   temp = i915_read32___6(dev_priv, reg);
 #line 2488
   temp = temp & 4294508543U;
 #line 2489
   __cil_tmp23 = pipe * 4096;
 #line 2489
   __cil_tmp24 = __cil_tmp23 + 458760;
 #line 2489
   __cil_tmp25 = (u32 )__cil_tmp24;
 #line 2489
   tmp = i915_read32___6(dev_priv, __cil_tmp25);
 #line 2489
   __cil_tmp26 = tmp & 224U;
 #line 2489
   __cil_tmp27 = __cil_tmp26 << 11;
 #line 2489
   temp = __cil_tmp27 | temp;
 #line 2490
   __cil_tmp28 = temp & 2147483647U;
 #line 2490
   i915_write32___4(dev_priv, reg, __cil_tmp28);
 #line 2492
   __cil_tmp29 = (unsigned long )reg;
 #line 2492
   __cil_tmp30 = dev_priv->regs;
 #line 2492
   __cil_tmp31 = (void const volatile   *)__cil_tmp30;
 #line 2492
   __cil_tmp32 = __cil_tmp31 + __cil_tmp29;
 #line 2492
   readl(__cil_tmp32);
 #line 2493
   __const_udelay(429500UL);
   }
   {
 #line 2496
   __cil_tmp33 = dev->dev_private;
 #line 2496
   __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
 #line 2496
   __cil_tmp35 = __cil_tmp34->pch_type;
 #line 2496
   __cil_tmp36 = (unsigned int )__cil_tmp35;
 #line 2496
   if (__cil_tmp36 == 0U) {
     {
 #line 2497
     __cil_tmp37 = pipe + 198659;
 #line 2497
     __cil_tmp38 = __cil_tmp37 * 4;
 #line 2497
     __cil_tmp39 = (u32 )__cil_tmp38;
 #line 2497
     i915_write32___4(dev_priv, __cil_tmp39, 2U);
 #line 2498
     __cil_tmp40 = pipe + 198659;
 #line 2498
     __cil_tmp41 = __cil_tmp40 * 4;
 #line 2498
     __cil_tmp42 = (u32 )__cil_tmp41;
 #line 2498
     __cil_tmp43 = __cil_tmp42 & 4294967294U;
 #line 2498
     tmp___0 = i915_read32___6(dev_priv, __cil_tmp43);
 #line 2498
     __cil_tmp44 = pipe + 198659;
 #line 2498
     __cil_tmp45 = __cil_tmp44 * 4;
 #line 2498
     __cil_tmp46 = (u32 )__cil_tmp45;
 #line 2498
     i915_write32___4(dev_priv, __cil_tmp46, tmp___0);
     }
   } else {
 
   }
   }
   {
 #line 2504
   __cil_tmp47 = pipe * 4096;
 #line 2504
   __cil_tmp48 = __cil_tmp47 + 393472;
 #line 2504
   reg = (u32 )__cil_tmp48;
 #line 2505
   temp = i915_read32___6(dev_priv, reg);
 #line 2506
   temp = temp & 3489660927U;
 #line 2507
   temp = temp;
 #line 2508
   i915_write32___4(dev_priv, reg, temp);
 #line 2510
   __cil_tmp49 = pipe * 4096;
 #line 2510
   __cil_tmp50 = __cil_tmp49 + 983052;
 #line 2510
   reg = (u32 )__cil_tmp50;
 #line 2511
   temp = i915_read32___6(dev_priv, reg);
   }
   {
 #line 2512
   __cil_tmp51 = dev->dev_private;
 #line 2512
   __cil_tmp52 = (struct drm_i915_private *)__cil_tmp51;
 #line 2512
   __cil_tmp53 = __cil_tmp52->pch_type;
 #line 2512
   __cil_tmp54 = (unsigned int )__cil_tmp53;
 #line 2512
   if (__cil_tmp54 == 1U) {
 #line 2513
     temp = temp & 4294966527U;
 #line 2514
     temp = temp;
   } else {
 #line 2516
     temp = temp & 3489660927U;
 #line 2517
     temp = temp;
   }
   }
   {
 #line 2520
   temp = temp & 4294508543U;
 #line 2521
   __cil_tmp55 = pipe * 4096;
 #line 2521
   __cil_tmp56 = __cil_tmp55 + 458760;
 #line 2521
   __cil_tmp57 = (u32 )__cil_tmp56;
 #line 2521
   tmp___1 = i915_read32___6(dev_priv, __cil_tmp57);
 #line 2521
   __cil_tmp58 = tmp___1 & 224U;
 #line 2521
   __cil_tmp59 = __cil_tmp58 << 11;
 #line 2521
   temp = __cil_tmp59 | temp;
 #line 2522
   i915_write32___4(dev_priv, reg, temp);
 #line 2524
   __cil_tmp60 = (unsigned long )reg;
 #line 2524
   __cil_tmp61 = dev_priv->regs;
 #line 2524
   __cil_tmp62 = (void const volatile   *)__cil_tmp61;
 #line 2524
   __cil_tmp63 = __cil_tmp62 + __cil_tmp60;
 #line 2524
   readl(__cil_tmp63);
 #line 2525
   __const_udelay(429500UL);
   }
 #line 2526
   return;
 }
 }
 #line 2532 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_clear_scanline_wait(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct intel_ring_buffer *ring ;
   u32 tmp ;
   void *__cil_tmp5 ;
   void *__cil_tmp6 ;
   struct drm_i915_private *__cil_tmp7 ;
   struct intel_device_info  const  *__cil_tmp8 ;
   u8 __cil_tmp9 ;
   unsigned char __cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   struct intel_ring_buffer (*__cil_tmp12)[3U] ;
   u32 __cil_tmp13 ;
   u32 __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   u32 __cil_tmp16 ;
   u32 __cil_tmp17 ;
 
   {
 #line 2534
   __cil_tmp5 = dev->dev_private;
 #line 2534
   dev_priv = (struct drm_i915_private *)__cil_tmp5;
   {
 #line 2538
   __cil_tmp6 = dev->dev_private;
 #line 2538
   __cil_tmp7 = (struct drm_i915_private *)__cil_tmp6;
 #line 2538
   __cil_tmp8 = __cil_tmp7->info;
 #line 2538
   __cil_tmp9 = __cil_tmp8->gen;
 #line 2538
   __cil_tmp10 = (unsigned char )__cil_tmp9;
 #line 2538
   __cil_tmp11 = (unsigned int )__cil_tmp10;
 #line 2538
   if (__cil_tmp11 == 2U) {
 #line 2540
     return;
   } else {
 
   }
   }
   {
 #line 2542
   __cil_tmp12 = & dev_priv->ring;
 #line 2542
   ring = (struct intel_ring_buffer *)__cil_tmp12;
 #line 2543
   __cil_tmp13 = ring->mmio_base;
 #line 2543
   __cil_tmp14 = __cil_tmp13 + 60U;
 #line 2543
   tmp = i915_read32___6(dev_priv, __cil_tmp14);
   }
   {
 #line 2544
   __cil_tmp15 = tmp & 2048U;
 #line 2544
   if (__cil_tmp15 != 0U) {
     {
 #line 2545
     __cil_tmp16 = ring->mmio_base;
 #line 2545
     __cil_tmp17 = __cil_tmp16 + 60U;
 #line 2545
     i915_write32___4(dev_priv, __cil_tmp17, tmp);
     }
   } else {
 
   }
   }
 #line 2546
   return;
 }
 }
 #line 2548 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc ) 
 { struct drm_i915_gem_object *obj ;
   struct drm_i915_private *dev_priv ;
   struct drm_framebuffer  const  *__mptr ;
   int tmp ;
   wait_queue_t __wait ;
   struct task_struct *tmp___0 ;
   int tmp___1 ;
   struct drm_framebuffer *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct drm_framebuffer *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_framebuffer *__cil_tmp13 ;
   struct intel_framebuffer *__cil_tmp14 ;
   struct drm_device *__cil_tmp15 ;
   void *__cil_tmp16 ;
   atomic_t *__cil_tmp17 ;
   atomic_t const   *__cil_tmp18 ;
   wait_queue_head_t *__cil_tmp19 ;
   atomic_t *__cil_tmp20 ;
   atomic_t const   *__cil_tmp21 ;
   wait_queue_head_t *__cil_tmp22 ;
 
   {
   {
 #line 2553
   __cil_tmp9 = (struct drm_framebuffer *)0;
 #line 2553
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 2553
   __cil_tmp11 = crtc->fb;
 #line 2553
   __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 2553
   if (__cil_tmp12 == __cil_tmp10) {
 #line 2554
     return;
   } else {
 
   }
   }
   {
 #line 2556
   __cil_tmp13 = crtc->fb;
 #line 2556
   __mptr = (struct drm_framebuffer  const  *)__cil_tmp13;
 #line 2556
   __cil_tmp14 = (struct intel_framebuffer *)__mptr;
 #line 2556
   obj = __cil_tmp14->obj;
 #line 2557
   __cil_tmp15 = crtc->dev;
 #line 2557
   __cil_tmp16 = __cil_tmp15->dev_private;
 #line 2557
   dev_priv = (struct drm_i915_private *)__cil_tmp16;
 #line 2558
   __cil_tmp17 = & obj->pending_flip;
 #line 2558
   __cil_tmp18 = (atomic_t const   *)__cil_tmp17;
 #line 2558
   tmp = atomic_read(__cil_tmp18);
   }
 #line 2558
   if (tmp == 0) {
 #line 2558
     goto ldv_38912;
   } else {
 
   }
   {
 #line 2558
   tmp___0 = get_current();
 #line 2558
   __wait.flags = 0U;
 #line 2558
   __wait.private = (void *)tmp___0;
 #line 2558
   __wait.func = & autoremove_wake_function;
 #line 2558
   __wait.task_list.next = & __wait.task_list;
 #line 2558
   __wait.task_list.prev = & __wait.task_list;
   }
   ldv_38915: 
   {
 #line 2558
   __cil_tmp19 = & dev_priv->pending_flip_queue;
 #line 2558
   prepare_to_wait(__cil_tmp19, & __wait, 2);
 #line 2558
   __cil_tmp20 = & obj->pending_flip;
 #line 2558
   __cil_tmp21 = (atomic_t const   *)__cil_tmp20;
 #line 2558
   tmp___1 = atomic_read(__cil_tmp21);
   }
 #line 2558
   if (tmp___1 == 0) {
 #line 2558
     goto ldv_38914;
   } else {
 
   }
   {
 #line 2558
   schedule();
   }
 #line 2558
   goto ldv_38915;
   ldv_38914: 
   {
 #line 2558
   __cil_tmp22 = & dev_priv->pending_flip_queue;
 #line 2558
   finish_wait(__cil_tmp22, & __wait);
   }
   ldv_38912: ;
 #line 2561
   return;
 }
 }
 #line 2562 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_crtc_driving_pch(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_mode_config *mode_config ;
   struct intel_encoder *encoder ;
   struct list_head  const  *__mptr ;
   bool tmp ;
   int tmp___0 ;
   struct list_head  const  *__mptr___0 ;
   struct list_head *__cil_tmp9 ;
   struct intel_encoder *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   struct drm_crtc *__cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   int __cil_tmp14 ;
   struct drm_encoder *__cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   struct intel_encoder *__cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
 
   {
 #line 2564
   dev = crtc->dev;
 #line 2565
   mode_config = & dev->mode_config;
 #line 2572
   __cil_tmp9 = mode_config->encoder_list.next;
 #line 2572
   __mptr = (struct list_head  const  *)__cil_tmp9;
 #line 2572
   __cil_tmp10 = (struct intel_encoder *)__mptr;
 #line 2572
   encoder = __cil_tmp10 + 1152921504606846968UL;
 #line 2572
   goto ldv_38929;
   ldv_38928: ;
   {
 #line 2573
   __cil_tmp11 = (unsigned long )crtc;
 #line 2573
   __cil_tmp12 = encoder->base.crtc;
 #line 2573
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 2573
   if (__cil_tmp13 != __cil_tmp11) {
 #line 2574
     goto ldv_38926;
   } else {
 
   }
   }
   {
 #line 2577
   __cil_tmp14 = encoder->type;
 #line 2577
   if (__cil_tmp14 == 8) {
 #line 2577
     goto case_8;
   } else
 #line 2576
   if (0) {
     case_8: 
     {
 #line 2578
     __cil_tmp15 = & encoder->base;
 #line 2578
     tmp = intel_encoder_is_pch_edp(__cil_tmp15);
     }
 #line 2578
     if (tmp) {
 #line 2578
       tmp___0 = 0;
     } else {
 #line 2578
       tmp___0 = 1;
     }
 #line 2578
     if (tmp___0) {
 #line 2579
       return ((bool )0);
     } else {
 
     }
 #line 2580
     goto ldv_38926;
   } else {
 
   }
   }
   ldv_38926: 
 #line 2572
   __cil_tmp16 = encoder->base.head.next;
 #line 2572
   __mptr___0 = (struct list_head  const  *)__cil_tmp16;
 #line 2572
   __cil_tmp17 = (struct intel_encoder *)__mptr___0;
 #line 2572
   encoder = __cil_tmp17 + 1152921504606846968UL;
   ldv_38929: ;
   {
 #line 2572
   __cil_tmp18 = & mode_config->encoder_list;
 #line 2572
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 2572
   __cil_tmp20 = & encoder->base.head;
 #line 2572
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 2572
   if (__cil_tmp21 != __cil_tmp19) {
 #line 2573
     goto ldv_38928;
   } else {
 #line 2575
     goto ldv_38930;
   }
   }
   ldv_38930: ;
 #line 2584
   return ((bool )1);
 }
 }
 #line 2595 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_pch_enable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   u32 reg ;
   u32 temp ;
   u32 tmp ;
   u32 tmp___0 ;
   u32 tmp___1 ;
   u32 tmp___2 ;
   u32 tmp___3 ;
   u32 tmp___4 ;
   int tmp___5 ;
   bool tmp___6 ;
   void *__cil_tmp17 ;
   enum pipe __cil_tmp18 ;
   void (*__cil_tmp19)(struct drm_crtc * ) ;
   enum pipe __cil_tmp20 ;
   void *__cil_tmp21 ;
   struct drm_i915_private *__cil_tmp22 ;
   enum intel_pch __cil_tmp23 ;
   unsigned int __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   unsigned int __cil_tmp26 ;
   enum pipe __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   u32 __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   u32 __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   int __cil_tmp40 ;
   int __cil_tmp41 ;
   u32 __cil_tmp42 ;
   int __cil_tmp43 ;
   int __cil_tmp44 ;
   u32 __cil_tmp45 ;
   int __cil_tmp46 ;
   int __cil_tmp47 ;
   u32 __cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   u32 __cil_tmp51 ;
   int __cil_tmp52 ;
   int __cil_tmp53 ;
   u32 __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   u32 __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   u32 __cil_tmp60 ;
   int __cil_tmp61 ;
   int __cil_tmp62 ;
   u32 __cil_tmp63 ;
   void *__cil_tmp64 ;
   struct drm_i915_private *__cil_tmp65 ;
   enum intel_pch __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   unsigned int __cil_tmp70 ;
   int __cil_tmp71 ;
   unsigned int __cil_tmp72 ;
   unsigned int __cil_tmp73 ;
   enum pipe __cil_tmp74 ;
 
   {
   {
 #line 2597
   dev = crtc->dev;
 #line 2598
   __cil_tmp17 = dev->dev_private;
 #line 2598
   dev_priv = (struct drm_i915_private *)__cil_tmp17;
 #line 2599
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2599
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2600
   __cil_tmp18 = intel_crtc->pipe;
 #line 2600
   pipe = (int )__cil_tmp18;
 #line 2604
   __cil_tmp19 = dev_priv->display.fdi_link_train;
 #line 2604
   (*__cil_tmp19)(crtc);
 #line 2606
   __cil_tmp20 = (enum pipe )pipe;
 #line 2606
   intel_enable_pch_pll(dev_priv, __cil_tmp20);
   }
   {
 #line 2608
   __cil_tmp21 = dev->dev_private;
 #line 2608
   __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
 #line 2608
   __cil_tmp23 = __cil_tmp22->pch_type;
 #line 2608
   __cil_tmp24 = (unsigned int )__cil_tmp23;
 #line 2608
   if (__cil_tmp24 == 1U) {
     {
 #line 2610
     temp = i915_read32___6(dev_priv, 815104U);
     }
 #line 2611
     if (pipe == 0) {
       {
 #line 2611
       __cil_tmp25 = temp & 8U;
 #line 2611
       if (__cil_tmp25 == 0U) {
 #line 2612
         temp = temp | 8U;
       } else {
 #line 2611
         goto _L;
       }
       }
     } else
     _L: 
 #line 2613
     if (pipe == 1) {
       {
 #line 2613
       __cil_tmp26 = temp & 128U;
 #line 2613
       if (__cil_tmp26 == 0U) {
 #line 2614
         temp = temp | 144U;
       } else {
 
       }
       }
     } else {
 
     }
     {
 #line 2615
     i915_write32___4(dev_priv, 815104U, temp);
     }
   } else {
 
   }
   }
   {
 #line 2619
   __cil_tmp27 = (enum pipe )pipe;
 #line 2619
   assert_panel_unlocked(dev_priv, __cil_tmp27);
 #line 2620
   __cil_tmp28 = pipe + 96;
 #line 2620
   __cil_tmp29 = __cil_tmp28 * 4096;
 #line 2620
   __cil_tmp30 = (u32 )__cil_tmp29;
 #line 2620
   tmp = i915_read32___6(dev_priv, __cil_tmp30);
 #line 2620
   __cil_tmp31 = pipe + 224;
 #line 2620
   __cil_tmp32 = __cil_tmp31 * 4096;
 #line 2620
   __cil_tmp33 = (u32 )__cil_tmp32;
 #line 2620
   i915_write32___4(dev_priv, __cil_tmp33, tmp);
 #line 2621
   __cil_tmp34 = pipe * 4096;
 #line 2621
   __cil_tmp35 = __cil_tmp34 + 393220;
 #line 2621
   __cil_tmp36 = (u32 )__cil_tmp35;
 #line 2621
   tmp___0 = i915_read32___6(dev_priv, __cil_tmp36);
 #line 2621
   __cil_tmp37 = pipe * 4096;
 #line 2621
   __cil_tmp38 = __cil_tmp37 + 917508;
 #line 2621
   __cil_tmp39 = (u32 )__cil_tmp38;
 #line 2621
   i915_write32___4(dev_priv, __cil_tmp39, tmp___0);
 #line 2622
   __cil_tmp40 = pipe * 4096;
 #line 2622
   __cil_tmp41 = __cil_tmp40 + 393224;
 #line 2622
   __cil_tmp42 = (u32 )__cil_tmp41;
 #line 2622
   tmp___1 = i915_read32___6(dev_priv, __cil_tmp42);
 #line 2622
   __cil_tmp43 = pipe * 4096;
 #line 2622
   __cil_tmp44 = __cil_tmp43 + 917512;
 #line 2622
   __cil_tmp45 = (u32 )__cil_tmp44;
 #line 2622
   i915_write32___4(dev_priv, __cil_tmp45, tmp___1);
 #line 2624
   __cil_tmp46 = pipe * 4096;
 #line 2624
   __cil_tmp47 = __cil_tmp46 + 393228;
 #line 2624
   __cil_tmp48 = (u32 )__cil_tmp47;
 #line 2624
   tmp___2 = i915_read32___6(dev_priv, __cil_tmp48);
 #line 2624
   __cil_tmp49 = pipe * 4096;
 #line 2624
   __cil_tmp50 = __cil_tmp49 + 917516;
 #line 2624
   __cil_tmp51 = (u32 )__cil_tmp50;
 #line 2624
   i915_write32___4(dev_priv, __cil_tmp51, tmp___2);
 #line 2625
   __cil_tmp52 = pipe * 4096;
 #line 2625
   __cil_tmp53 = __cil_tmp52 + 393232;
 #line 2625
   __cil_tmp54 = (u32 )__cil_tmp53;
 #line 2625
   tmp___3 = i915_read32___6(dev_priv, __cil_tmp54);
 #line 2625
   __cil_tmp55 = pipe * 4096;
 #line 2625
   __cil_tmp56 = __cil_tmp55 + 917520;
 #line 2625
   __cil_tmp57 = (u32 )__cil_tmp56;
 #line 2625
   i915_write32___4(dev_priv, __cil_tmp57, tmp___3);
 #line 2626
   __cil_tmp58 = pipe * 4096;
 #line 2626
   __cil_tmp59 = __cil_tmp58 + 393236;
 #line 2626
   __cil_tmp60 = (u32 )__cil_tmp59;
 #line 2626
   tmp___4 = i915_read32___6(dev_priv, __cil_tmp60);
 #line 2626
   __cil_tmp61 = pipe * 4096;
 #line 2626
   __cil_tmp62 = __cil_tmp61 + 917524;
 #line 2626
   __cil_tmp63 = (u32 )__cil_tmp62;
 #line 2626
   i915_write32___4(dev_priv, __cil_tmp63, tmp___4);
 #line 2628
   intel_fdi_normal_train(crtc);
   }
   {
 #line 2631
   __cil_tmp64 = dev->dev_private;
 #line 2631
   __cil_tmp65 = (struct drm_i915_private *)__cil_tmp64;
 #line 2631
   __cil_tmp66 = __cil_tmp65->pch_type;
 #line 2631
   __cil_tmp67 = (unsigned int )__cil_tmp66;
 #line 2631
   if (__cil_tmp67 == 1U) {
     {
 #line 2631
     tmp___6 = intel_pipe_has_type(crtc, 7);
     }
 #line 2631
     if ((int )tmp___6) {
       {
 #line 2633
       __cil_tmp68 = pipe * 4096;
 #line 2633
       __cil_tmp69 = __cil_tmp68 + 918272;
 #line 2633
       reg = (u32 )__cil_tmp69;
 #line 2634
       temp = i915_read32___6(dev_priv, reg);
 #line 2635
       temp = temp & 2684352999U;
 #line 2638
       temp = temp | 2147745792U;
 #line 2640
       temp = temp;
       }
       {
 #line 2642
       __cil_tmp70 = crtc->mode.flags;
 #line 2642
       __cil_tmp71 = (int )__cil_tmp70;
 #line 2642
       if (__cil_tmp71 & 1) {
 #line 2643
         temp = temp | 8U;
       } else {
 
       }
       }
       {
 #line 2644
       __cil_tmp72 = crtc->mode.flags;
 #line 2644
       __cil_tmp73 = __cil_tmp72 & 4U;
 #line 2644
       if (__cil_tmp73 != 0U) {
 #line 2645
         temp = temp | 16U;
       } else {
 
       }
       }
       {
 #line 2647
       tmp___5 = intel_trans_dp_port_sel(crtc);
       }
 #line 2648
       if (tmp___5 == 934144) {
 #line 2648
         goto case_934144;
       } else
 #line 2651
       if (tmp___5 == 934400) {
 #line 2651
         goto case_934400;
       } else
 #line 2654
       if (tmp___5 == 934656) {
 #line 2654
         goto case_934656;
       } else {
 #line 2657
         goto switch_default;
 #line 2647
         if (0) {
           case_934144: 
 #line 2649
           temp = temp;
 #line 2650
           goto ldv_38943;
           case_934400: 
 #line 2652
           temp = temp | 536870912U;
 #line 2653
           goto ldv_38943;
           case_934656: 
 #line 2655
           temp = temp | 1073741824U;
 #line 2656
           goto ldv_38943;
           switch_default: 
           {
 #line 2658
           drm_ut_debug_printk(4U, "drm", "ironlake_pch_enable", "Wrong PCH DP port return. Guess port B\n");
 #line 2659
           temp = temp;
           }
 #line 2660
           goto ldv_38943;
         } else {
 
         }
       }
       ldv_38943: 
       {
 #line 2663
       i915_write32___4(dev_priv, reg, temp);
       }
     } else {
 
     }
   } else {
 
   }
   }
   {
 #line 2666
   __cil_tmp74 = (enum pipe )pipe;
 #line 2666
   intel_enable_transcoder(dev_priv, __cil_tmp74);
   }
 #line 2667
   return;
 }
 }
 #line 2669 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_crtc_enable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   u32 temp ;
   bool is_pch_port ;
   bool tmp ;
   bool tmp___0 ;
   bool tmp___1 ;
   void *__cil_tmp13 ;
   enum pipe __cil_tmp14 ;
   enum plane __cil_tmp15 ;
   bool __cil_tmp16 ;
   int __cil_tmp17 ;
   unsigned int __cil_tmp18 ;
   u32 __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   u32 __cil_tmp22 ;
   int __cil_tmp23 ;
   int __cil_tmp24 ;
   u32 __cil_tmp25 ;
   u32 __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   u32 __cil_tmp29 ;
   u32 __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   u32 __cil_tmp33 ;
   int __cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   u32 __cil_tmp37 ;
   int __cil_tmp38 ;
   int __cil_tmp39 ;
   u32 __cil_tmp40 ;
   u32 __cil_tmp41 ;
   enum pipe __cil_tmp42 ;
   int __cil_tmp43 ;
   bool __cil_tmp44 ;
   enum plane __cil_tmp45 ;
   enum pipe __cil_tmp46 ;
   struct mutex *__cil_tmp47 ;
   struct mutex *__cil_tmp48 ;
   bool __cil_tmp49 ;
 
   {
 #line 2671
   dev = crtc->dev;
 #line 2672
   __cil_tmp13 = dev->dev_private;
 #line 2672
   dev_priv = (struct drm_i915_private *)__cil_tmp13;
 #line 2673
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2673
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2674
   __cil_tmp14 = intel_crtc->pipe;
 #line 2674
   pipe = (int )__cil_tmp14;
 #line 2675
   __cil_tmp15 = intel_crtc->plane;
 #line 2675
   plane = (int )__cil_tmp15;
   {
 #line 2679
   __cil_tmp16 = intel_crtc->active;
 #line 2679
   if ((int )__cil_tmp16) {
 #line 2680
     return;
   } else {
 
   }
   }
   {
 #line 2682
   intel_crtc->active = (bool )1;
 #line 2683
   intel_update_watermarks(dev);
 #line 2685
   tmp = intel_pipe_has_type(crtc, 4);
   }
 #line 2685
   if ((int )tmp) {
     {
 #line 2686
     temp = i915_read32___6(dev_priv, 921984U);
     }
     {
 #line 2687
     __cil_tmp17 = (int )temp;
 #line 2687
     if (__cil_tmp17 >= 0) {
       {
 #line 2688
       __cil_tmp18 = temp | 2147483648U;
 #line 2688
       i915_write32___4(dev_priv, 921984U, __cil_tmp18);
       }
     } else {
 
     }
     }
   } else {
 
   }
   {
 #line 2691
   is_pch_port = intel_crtc_driving_pch(crtc);
   }
 #line 2693
   if ((int )is_pch_port) {
     {
 #line 2694
     ironlake_fdi_pll_enable(crtc);
     }
   } else {
     {
 #line 2696
     ironlake_fdi_disable(crtc);
     }
   }
   {
 #line 2699
   __cil_tmp19 = dev_priv->pch_pf_size;
 #line 2699
   if (__cil_tmp19 != 0U) {
     {
 #line 2699
     tmp___0 = intel_pipe_has_type(crtc, 4);
     }
 #line 2699
     if ((int )tmp___0) {
       {
 #line 2705
       __cil_tmp20 = pipe * 2048;
 #line 2705
       __cil_tmp21 = __cil_tmp20 + 426112;
 #line 2705
       __cil_tmp22 = (u32 )__cil_tmp21;
 #line 2705
       i915_write32___4(dev_priv, __cil_tmp22, 2155872256U);
 #line 2706
       __cil_tmp23 = pipe * 2048;
 #line 2706
       __cil_tmp24 = __cil_tmp23 + 426096;
 #line 2706
       __cil_tmp25 = (u32 )__cil_tmp24;
 #line 2706
       __cil_tmp26 = dev_priv->pch_pf_pos;
 #line 2706
       i915_write32___4(dev_priv, __cil_tmp25, __cil_tmp26);
 #line 2707
       __cil_tmp27 = pipe * 2048;
 #line 2707
       __cil_tmp28 = __cil_tmp27 + 426100;
 #line 2707
       __cil_tmp29 = (u32 )__cil_tmp28;
 #line 2707
       __cil_tmp30 = dev_priv->pch_pf_size;
 #line 2707
       i915_write32___4(dev_priv, __cil_tmp29, __cil_tmp30);
       }
     } else {
       {
 #line 2699
       tmp___1 = intel_pipe_has_type(crtc, 8);
       }
 #line 2699
       if ((int )tmp___1) {
         {
 #line 2705
         __cil_tmp31 = pipe * 2048;
 #line 2705
         __cil_tmp32 = __cil_tmp31 + 426112;
 #line 2705
         __cil_tmp33 = (u32 )__cil_tmp32;
 #line 2705
         i915_write32___4(dev_priv, __cil_tmp33, 2155872256U);
 #line 2706
         __cil_tmp34 = pipe * 2048;
 #line 2706
         __cil_tmp35 = __cil_tmp34 + 426096;
 #line 2706
         __cil_tmp36 = (u32 )__cil_tmp35;
 #line 2706
         __cil_tmp37 = dev_priv->pch_pf_pos;
 #line 2706
         i915_write32___4(dev_priv, __cil_tmp36, __cil_tmp37);
 #line 2707
         __cil_tmp38 = pipe * 2048;
 #line 2707
         __cil_tmp39 = __cil_tmp38 + 426100;
 #line 2707
         __cil_tmp40 = (u32 )__cil_tmp39;
 #line 2707
         __cil_tmp41 = dev_priv->pch_pf_size;
 #line 2707
         i915_write32___4(dev_priv, __cil_tmp40, __cil_tmp41);
         }
       } else {
 
       }
     }
   } else {
 
   }
   }
   {
 #line 2710
   __cil_tmp42 = (enum pipe )pipe;
 #line 2710
   __cil_tmp43 = (int )is_pch_port;
 #line 2710
   __cil_tmp44 = (bool )__cil_tmp43;
 #line 2710
   intel_enable_pipe(dev_priv, __cil_tmp42, __cil_tmp44);
 #line 2711
   __cil_tmp45 = (enum plane )plane;
 #line 2711
   __cil_tmp46 = (enum pipe )pipe;
 #line 2711
   intel_enable_plane(dev_priv, __cil_tmp45, __cil_tmp46);
   }
 #line 2713
   if ((int )is_pch_port) {
     {
 #line 2714
     ironlake_pch_enable(crtc);
     }
   } else {
 
   }
   {
 #line 2716
   intel_crtc_load_lut(crtc);
 #line 2718
   __cil_tmp47 = & dev->struct_mutex;
 #line 2718
   mutex_lock_nested(__cil_tmp47, 0U);
 #line 2719
   intel_update_fbc(dev);
 #line 2720
   __cil_tmp48 = & dev->struct_mutex;
 #line 2720
   mutex_unlock(__cil_tmp48);
 #line 2722
   __cil_tmp49 = (bool )1;
 #line 2722
   intel_crtc_update_cursor(crtc, __cil_tmp49);
   }
 #line 2723
   return;
 }
 }
 #line 2725 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_crtc_disable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   u32 reg ;
   u32 temp ;
   void *__cil_tmp10 ;
   enum pipe __cil_tmp11 ;
   enum plane __cil_tmp12 ;
   bool __cil_tmp13 ;
   bool __cil_tmp14 ;
   enum plane __cil_tmp15 ;
   enum pipe __cil_tmp16 ;
   int __cil_tmp17 ;
   void (*__cil_tmp18)(struct drm_device * ) ;
   unsigned long __cil_tmp19 ;
   void (*__cil_tmp20)(struct drm_device * ) ;
   unsigned long __cil_tmp21 ;
   void (*__cil_tmp22)(struct drm_device * ) ;
   enum pipe __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   u32 __cil_tmp26 ;
   int __cil_tmp27 ;
   int __cil_tmp28 ;
   u32 __cil_tmp29 ;
   enum pipe __cil_tmp30 ;
   enum pipe __cil_tmp31 ;
   void *__cil_tmp32 ;
   struct drm_i915_private *__cil_tmp33 ;
   enum intel_pch __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   enum pipe __cil_tmp38 ;
   int __cil_tmp39 ;
   int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   int __cil_tmp42 ;
   int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   void *__cil_tmp46 ;
   void const volatile   *__cil_tmp47 ;
   void const volatile   *__cil_tmp48 ;
   int __cil_tmp49 ;
   int __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   void *__cil_tmp53 ;
   void const volatile   *__cil_tmp54 ;
   void const volatile   *__cil_tmp55 ;
   struct mutex *__cil_tmp56 ;
   struct mutex *__cil_tmp57 ;
 
   {
 #line 2727
   dev = crtc->dev;
 #line 2728
   __cil_tmp10 = dev->dev_private;
 #line 2728
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 2729
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2729
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2730
   __cil_tmp11 = intel_crtc->pipe;
 #line 2730
   pipe = (int )__cil_tmp11;
 #line 2731
   __cil_tmp12 = intel_crtc->plane;
 #line 2731
   plane = (int )__cil_tmp12;
   {
 #line 2734
   __cil_tmp13 = intel_crtc->active;
 #line 2734
   if (! __cil_tmp13) {
 #line 2735
     return;
   } else {
 
   }
   }
   {
 #line 2737
   intel_crtc_wait_for_pending_flips(crtc);
 #line 2738
   drm_vblank_off(dev, pipe);
 #line 2739
   __cil_tmp14 = (bool )0;
 #line 2739
   intel_crtc_update_cursor(crtc, __cil_tmp14);
 #line 2741
   __cil_tmp15 = (enum plane )plane;
 #line 2741
   __cil_tmp16 = (enum pipe )pipe;
 #line 2741
   intel_disable_plane(dev_priv, __cil_tmp15, __cil_tmp16);
   }
   {
 #line 2743
   __cil_tmp17 = dev_priv->cfb_plane;
 #line 2743
   if (__cil_tmp17 == plane) {
     {
 #line 2743
     __cil_tmp18 = (void (*)(struct drm_device * ))0;
 #line 2743
     __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 2743
     __cil_tmp20 = dev_priv->display.disable_fbc;
 #line 2743
     __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 2743
     if (__cil_tmp21 != __cil_tmp19) {
       {
 #line 2745
       __cil_tmp22 = dev_priv->display.disable_fbc;
 #line 2745
       (*__cil_tmp22)(dev);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 2747
   __cil_tmp23 = (enum pipe )pipe;
 #line 2747
   intel_disable_pipe(dev_priv, __cil_tmp23);
 #line 2750
   __cil_tmp24 = pipe * 2048;
 #line 2750
   __cil_tmp25 = __cil_tmp24 + 426112;
 #line 2750
   __cil_tmp26 = (u32 )__cil_tmp25;
 #line 2750
   i915_write32___4(dev_priv, __cil_tmp26, 0U);
 #line 2751
   __cil_tmp27 = pipe * 2048;
 #line 2751
   __cil_tmp28 = __cil_tmp27 + 426100;
 #line 2751
   __cil_tmp29 = (u32 )__cil_tmp28;
 #line 2751
   i915_write32___4(dev_priv, __cil_tmp29, 0U);
 #line 2753
   ironlake_fdi_disable(crtc);
 #line 2760
   __cil_tmp30 = (enum pipe )pipe;
 #line 2760
   intel_disable_pch_ports(dev_priv, __cil_tmp30);
 #line 2762
   __cil_tmp31 = (enum pipe )pipe;
 #line 2762
   intel_disable_transcoder(dev_priv, __cil_tmp31);
   }
   {
 #line 2764
   __cil_tmp32 = dev->dev_private;
 #line 2764
   __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
 #line 2764
   __cil_tmp34 = __cil_tmp33->pch_type;
 #line 2764
   __cil_tmp35 = (unsigned int )__cil_tmp34;
 #line 2764
   if (__cil_tmp35 == 1U) {
     {
 #line 2766
     __cil_tmp36 = pipe * 4096;
 #line 2766
     __cil_tmp37 = __cil_tmp36 + 918272;
 #line 2766
     reg = (u32 )__cil_tmp37;
 #line 2767
     temp = i915_read32___6(dev_priv, reg);
 #line 2768
     temp = temp & 536870911U;
 #line 2769
     temp = temp | 1610612736U;
 #line 2770
     i915_write32___4(dev_priv, reg, temp);
 #line 2773
     temp = i915_read32___6(dev_priv, 815104U);
     }
 #line 2775
     if (pipe == 0) {
 #line 2775
       goto case_0;
     } else
 #line 2778
     if (pipe == 1) {
 #line 2778
       goto case_1;
     } else
 #line 2781
     if (pipe == 2) {
 #line 2781
       goto case_2;
     } else {
 #line 2785
       goto switch_default;
 #line 2774
       if (0) {
         case_0: 
 #line 2776
         temp = temp & 4294967287U;
 #line 2777
         goto ldv_38973;
         case_1: 
 #line 2779
         temp = temp & 4294967151U;
 #line 2780
         goto ldv_38973;
         case_2: 
 #line 2783
         temp = temp & 4294964991U;
 #line 2784
         goto ldv_38973;
         switch_default: 
 #line 2786
         __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                              "i" (2786), "i" (12UL));
         ldv_38977: ;
 #line 2786
         goto ldv_38977;
       } else {
 
       }
     }
     ldv_38973: 
     {
 #line 2788
     i915_write32___4(dev_priv, 815104U, temp);
     }
   } else {
 
   }
   }
   {
 #line 2792
   __cil_tmp38 = (enum pipe )pipe;
 #line 2792
   intel_disable_pch_pll(dev_priv, __cil_tmp38);
 #line 2795
   __cil_tmp39 = pipe * 4096;
 #line 2795
   __cil_tmp40 = __cil_tmp39 + 983052;
 #line 2795
   reg = (u32 )__cil_tmp40;
 #line 2796
   temp = i915_read32___6(dev_priv, reg);
 #line 2797
   __cil_tmp41 = temp & 4294967279U;
 #line 2797
   i915_write32___4(dev_priv, reg, __cil_tmp41);
 #line 2800
   __cil_tmp42 = pipe * 4096;
 #line 2800
   __cil_tmp43 = __cil_tmp42 + 393472;
 #line 2800
   reg = (u32 )__cil_tmp43;
 #line 2801
   temp = i915_read32___6(dev_priv, reg);
 #line 2802
   __cil_tmp44 = temp & 4294950911U;
 #line 2802
   i915_write32___4(dev_priv, reg, __cil_tmp44);
 #line 2804
   __cil_tmp45 = (unsigned long )reg;
 #line 2804
   __cil_tmp46 = dev_priv->regs;
 #line 2804
   __cil_tmp47 = (void const volatile   *)__cil_tmp46;
 #line 2804
   __cil_tmp48 = __cil_tmp47 + __cil_tmp45;
 #line 2804
   readl(__cil_tmp48);
 #line 2805
   __const_udelay(429500UL);
 #line 2807
   __cil_tmp49 = pipe * 4096;
 #line 2807
   __cil_tmp50 = __cil_tmp49 + 983052;
 #line 2807
   reg = (u32 )__cil_tmp50;
 #line 2808
   temp = i915_read32___6(dev_priv, reg);
 #line 2809
   __cil_tmp51 = temp & 4294959103U;
 #line 2809
   i915_write32___4(dev_priv, reg, __cil_tmp51);
 #line 2812
   __cil_tmp52 = (unsigned long )reg;
 #line 2812
   __cil_tmp53 = dev_priv->regs;
 #line 2812
   __cil_tmp54 = (void const volatile   *)__cil_tmp53;
 #line 2812
   __cil_tmp55 = __cil_tmp54 + __cil_tmp52;
 #line 2812
   readl(__cil_tmp55);
 #line 2813
   __const_udelay(429500UL);
 #line 2815
   intel_crtc->active = (bool )0;
 #line 2816
   intel_update_watermarks(dev);
 #line 2818
   __cil_tmp56 = & dev->struct_mutex;
 #line 2818
   mutex_lock_nested(__cil_tmp56, 0U);
 #line 2819
   intel_update_fbc(dev);
 #line 2820
   intel_clear_scanline_wait(dev);
 #line 2821
   __cil_tmp57 = & dev->struct_mutex;
 #line 2821
   mutex_unlock(__cil_tmp57);
   }
 #line 2822
   return;
 }
 }
 #line 2824 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_crtc_dpms(struct drm_crtc *crtc , int mode ) 
 { struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   enum pipe __cil_tmp7 ;
   enum plane __cil_tmp8 ;
 
   {
 #line 2826
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2826
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2827
   __cil_tmp7 = intel_crtc->pipe;
 #line 2827
   pipe = (int )__cil_tmp7;
 #line 2828
   __cil_tmp8 = intel_crtc->plane;
 #line 2828
   plane = (int )__cil_tmp8;
 #line 2834
   if (mode == 0) {
 #line 2834
     goto case_0;
   } else
 #line 2835
   if (mode == 1) {
 #line 2835
     goto case_1;
   } else
 #line 2836
   if (mode == 2) {
 #line 2836
     goto case_2;
   } else
 #line 2841
   if (mode == 3) {
 #line 2841
     goto case_3;
   } else
 #line 2833
   if (0) {
     case_0: ;
     case_1: ;
     case_2: 
     {
 #line 2837
     drm_ut_debug_printk(4U, "drm", "ironlake_crtc_dpms", "crtc %d/%d dpms on\n", pipe,
                         plane);
 #line 2838
     ironlake_crtc_enable(crtc);
     }
 #line 2839
     goto ldv_38991;
     case_3: 
     {
 #line 2842
     drm_ut_debug_printk(4U, "drm", "ironlake_crtc_dpms", "crtc %d/%d dpms off\n",
                         pipe, plane);
 #line 2843
     ironlake_crtc_disable(crtc);
     }
 #line 2844
     goto ldv_38991;
   } else {
 
   }
   ldv_38991: ;
 #line 2847
   return;
 }
 }
 #line 2848 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc , bool enable ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_overlay *__cil_tmp5 ;
   unsigned long __cil_tmp6 ;
   struct intel_overlay *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   void *__cil_tmp9 ;
   struct mutex *__cil_tmp10 ;
   struct intel_overlay *__cil_tmp11 ;
   struct mutex *__cil_tmp12 ;
 
   {
 #line 2850
   if (! enable) {
     {
 #line 2850
     __cil_tmp5 = (struct intel_overlay *)0;
 #line 2850
     __cil_tmp6 = (unsigned long )__cil_tmp5;
 #line 2850
     __cil_tmp7 = intel_crtc->overlay;
 #line 2850
     __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 2850
     if (__cil_tmp8 != __cil_tmp6) {
       {
 #line 2851
       dev = intel_crtc->base.dev;
 #line 2852
       __cil_tmp9 = dev->dev_private;
 #line 2852
       dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 2854
       __cil_tmp10 = & dev->struct_mutex;
 #line 2854
       mutex_lock_nested(__cil_tmp10, 0U);
 #line 2855
       dev_priv->mm.interruptible = (bool )0;
 #line 2856
       __cil_tmp11 = intel_crtc->overlay;
 #line 2856
       intel_overlay_switch_off(__cil_tmp11);
 #line 2857
       dev_priv->mm.interruptible = (bool )1;
 #line 2858
       __cil_tmp12 = & dev->struct_mutex;
 #line 2858
       mutex_unlock(__cil_tmp12);
       }
     } else {
 
     }
     }
   } else {
 
   }
 #line 2860
   return;
 }
 }
 #line 2866 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i9xx_crtc_enable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   void *__cil_tmp8 ;
   enum pipe __cil_tmp9 ;
   enum plane __cil_tmp10 ;
   bool __cil_tmp11 ;
   enum pipe __cil_tmp12 ;
   enum pipe __cil_tmp13 ;
   bool __cil_tmp14 ;
   enum plane __cil_tmp15 ;
   enum pipe __cil_tmp16 ;
   bool __cil_tmp17 ;
   bool __cil_tmp18 ;
 
   {
 #line 2868
   dev = crtc->dev;
 #line 2869
   __cil_tmp8 = dev->dev_private;
 #line 2869
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 2870
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2870
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2871
   __cil_tmp9 = intel_crtc->pipe;
 #line 2871
   pipe = (int )__cil_tmp9;
 #line 2872
   __cil_tmp10 = intel_crtc->plane;
 #line 2872
   plane = (int )__cil_tmp10;
   {
 #line 2874
   __cil_tmp11 = intel_crtc->active;
 #line 2874
   if ((int )__cil_tmp11) {
 #line 2875
     return;
   } else {
 
   }
   }
   {
 #line 2877
   intel_crtc->active = (bool )1;
 #line 2878
   intel_update_watermarks(dev);
 #line 2880
   __cil_tmp12 = (enum pipe )pipe;
 #line 2880
   intel_enable_pll(dev_priv, __cil_tmp12);
 #line 2881
   __cil_tmp13 = (enum pipe )pipe;
 #line 2881
   __cil_tmp14 = (bool )0;
 #line 2881
   intel_enable_pipe(dev_priv, __cil_tmp13, __cil_tmp14);
 #line 2882
   __cil_tmp15 = (enum plane )plane;
 #line 2882
   __cil_tmp16 = (enum pipe )pipe;
 #line 2882
   intel_enable_plane(dev_priv, __cil_tmp15, __cil_tmp16);
 #line 2884
   intel_crtc_load_lut(crtc);
 #line 2885
   intel_update_fbc(dev);
 #line 2888
   __cil_tmp17 = (bool )1;
 #line 2888
   intel_crtc_dpms_overlay(intel_crtc, __cil_tmp17);
 #line 2889
   __cil_tmp18 = (bool )1;
 #line 2889
   intel_crtc_update_cursor(crtc, __cil_tmp18);
   }
 #line 2890
   return;
 }
 }
 #line 2892 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i9xx_crtc_disable(struct drm_crtc *crtc ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   void *__cil_tmp8 ;
   enum pipe __cil_tmp9 ;
   enum plane __cil_tmp10 ;
   bool __cil_tmp11 ;
   bool __cil_tmp12 ;
   bool __cil_tmp13 ;
   int __cil_tmp14 ;
   void (*__cil_tmp15)(struct drm_device * ) ;
   unsigned long __cil_tmp16 ;
   void (*__cil_tmp17)(struct drm_device * ) ;
   unsigned long __cil_tmp18 ;
   void (*__cil_tmp19)(struct drm_device * ) ;
   enum plane __cil_tmp20 ;
   enum pipe __cil_tmp21 ;
   enum pipe __cil_tmp22 ;
   enum pipe __cil_tmp23 ;
 
   {
 #line 2894
   dev = crtc->dev;
 #line 2895
   __cil_tmp8 = dev->dev_private;
 #line 2895
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 2896
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2896
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2897
   __cil_tmp9 = intel_crtc->pipe;
 #line 2897
   pipe = (int )__cil_tmp9;
 #line 2898
   __cil_tmp10 = intel_crtc->plane;
 #line 2898
   plane = (int )__cil_tmp10;
   {
 #line 2900
   __cil_tmp11 = intel_crtc->active;
 #line 2900
   if (! __cil_tmp11) {
 #line 2901
     return;
   } else {
 
   }
   }
   {
 #line 2904
   intel_crtc_wait_for_pending_flips(crtc);
 #line 2905
   drm_vblank_off(dev, pipe);
 #line 2906
   __cil_tmp12 = (bool )0;
 #line 2906
   intel_crtc_dpms_overlay(intel_crtc, __cil_tmp12);
 #line 2907
   __cil_tmp13 = (bool )0;
 #line 2907
   intel_crtc_update_cursor(crtc, __cil_tmp13);
   }
   {
 #line 2909
   __cil_tmp14 = dev_priv->cfb_plane;
 #line 2909
   if (__cil_tmp14 == plane) {
     {
 #line 2909
     __cil_tmp15 = (void (*)(struct drm_device * ))0;
 #line 2909
     __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 2909
     __cil_tmp17 = dev_priv->display.disable_fbc;
 #line 2909
     __cil_tmp18 = (unsigned long )__cil_tmp17;
 #line 2909
     if (__cil_tmp18 != __cil_tmp16) {
       {
 #line 2911
       __cil_tmp19 = dev_priv->display.disable_fbc;
 #line 2911
       (*__cil_tmp19)(dev);
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 2913
   __cil_tmp20 = (enum plane )plane;
 #line 2913
   __cil_tmp21 = (enum pipe )pipe;
 #line 2913
   intel_disable_plane(dev_priv, __cil_tmp20, __cil_tmp21);
 #line 2914
   __cil_tmp22 = (enum pipe )pipe;
 #line 2914
   intel_disable_pipe(dev_priv, __cil_tmp22);
 #line 2915
   __cil_tmp23 = (enum pipe )pipe;
 #line 2915
   intel_disable_pll(dev_priv, __cil_tmp23);
 #line 2917
   intel_crtc->active = (bool )0;
 #line 2918
   intel_update_fbc(dev);
 #line 2919
   intel_update_watermarks(dev);
 #line 2920
   intel_clear_scanline_wait(dev);
   }
 #line 2921
   return;
 }
 }
 #line 2923 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i9xx_crtc_dpms(struct drm_crtc *crtc , int mode ) 
 { 
 
   {
 #line 2929
   if (mode == 0) {
 #line 2929
     goto case_0;
   } else
 #line 2930
   if (mode == 1) {
 #line 2930
     goto case_1;
   } else
 #line 2931
   if (mode == 2) {
 #line 2931
     goto case_2;
   } else
 #line 2934
   if (mode == 3) {
 #line 2934
     goto case_3;
   } else
 #line 2928
   if (0) {
     case_0: ;
     case_1: ;
     case_2: 
     {
 #line 2932
     i9xx_crtc_enable(crtc);
     }
 #line 2933
     goto ldv_39026;
     case_3: 
     {
 #line 2935
     i9xx_crtc_disable(crtc);
     }
 #line 2936
     goto ldv_39026;
   } else {
 
   }
   ldv_39026: ;
 #line 2939
   return;
 }
 }
 #line 2943 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_crtc_dpms(struct drm_crtc *crtc , int mode ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct drm_i915_master_private *master_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   bool enabled ;
   int tmp ;
   void *__cil_tmp11 ;
   enum pipe __cil_tmp12 ;
   int __cil_tmp13 ;
   void (*__cil_tmp14)(struct drm_crtc * , int  ) ;
   struct drm_master *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   struct drm_minor *__cil_tmp17 ;
   struct drm_master *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct drm_minor *__cil_tmp20 ;
   struct drm_master *__cil_tmp21 ;
   void *__cil_tmp22 ;
   struct _drm_i915_sarea *__cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct _drm_i915_sarea *__cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   bool __cil_tmp27 ;
   struct _drm_i915_sarea *__cil_tmp28 ;
   struct _drm_i915_sarea *__cil_tmp29 ;
   struct _drm_i915_sarea *__cil_tmp30 ;
   struct _drm_i915_sarea *__cil_tmp31 ;
   struct _drm_i915_sarea *__cil_tmp32 ;
   struct _drm_i915_sarea *__cil_tmp33 ;
   struct _drm_i915_sarea *__cil_tmp34 ;
   struct _drm_i915_sarea *__cil_tmp35 ;
   int __cil_tmp36 ;
 
   {
 #line 2945
   dev = crtc->dev;
 #line 2946
   __cil_tmp11 = dev->dev_private;
 #line 2946
   dev_priv = (struct drm_i915_private *)__cil_tmp11;
 #line 2948
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 2948
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 2949
   __cil_tmp12 = intel_crtc->pipe;
 #line 2949
   pipe = (int )__cil_tmp12;
   {
 #line 2952
   __cil_tmp13 = intel_crtc->dpms_mode;
 #line 2952
   if (__cil_tmp13 == mode) {
 #line 2953
     return;
   } else {
 
   }
   }
   {
 #line 2955
   intel_crtc->dpms_mode = mode;
 #line 2957
   __cil_tmp14 = dev_priv->display.dpms;
 #line 2957
   (*__cil_tmp14)(crtc, mode);
   }
   {
 #line 2959
   __cil_tmp15 = (struct drm_master *)0;
 #line 2959
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 2959
   __cil_tmp17 = dev->primary;
 #line 2959
   __cil_tmp18 = __cil_tmp17->master;
 #line 2959
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 2959
   if (__cil_tmp19 == __cil_tmp16) {
 #line 2960
     return;
   } else {
 
   }
   }
 #line 2962
   __cil_tmp20 = dev->primary;
 #line 2962
   __cil_tmp21 = __cil_tmp20->master;
 #line 2962
   __cil_tmp22 = __cil_tmp21->driver_priv;
 #line 2962
   master_priv = (struct drm_i915_master_private *)__cil_tmp22;
   {
 #line 2963
   __cil_tmp23 = (struct _drm_i915_sarea *)0;
 #line 2963
   __cil_tmp24 = (unsigned long )__cil_tmp23;
 #line 2963
   __cil_tmp25 = master_priv->sarea_priv;
 #line 2963
   __cil_tmp26 = (unsigned long )__cil_tmp25;
 #line 2963
   if (__cil_tmp26 == __cil_tmp24) {
 #line 2964
     return;
   } else {
 
   }
   }
   {
 #line 2966
   __cil_tmp27 = crtc->enabled;
 #line 2966
   if ((int )__cil_tmp27) {
 #line 2966
     if (mode != 3) {
 #line 2966
       tmp = 1;
     } else {
 #line 2966
       tmp = 0;
     }
   } else {
 #line 2966
     tmp = 0;
   }
   }
 #line 2966
   enabled = (bool )tmp;
 #line 2969
   if (pipe == 0) {
 #line 2969
     goto case_0;
   } else
 #line 2973
   if (pipe == 1) {
 #line 2973
     goto case_1;
   } else {
 #line 2977
     goto switch_default;
 #line 2968
     if (0) {
       case_0: ;
 #line 2970
       if ((int )enabled) {
 #line 2970
         __cil_tmp28 = master_priv->sarea_priv;
 #line 2970
         __cil_tmp28->pipeA_w = crtc->mode.hdisplay;
       } else {
 #line 2970
         __cil_tmp29 = master_priv->sarea_priv;
 #line 2970
         __cil_tmp29->pipeA_w = 0;
       }
 #line 2971
       if ((int )enabled) {
 #line 2971
         __cil_tmp30 = master_priv->sarea_priv;
 #line 2971
         __cil_tmp30->pipeA_h = crtc->mode.vdisplay;
       } else {
 #line 2971
         __cil_tmp31 = master_priv->sarea_priv;
 #line 2971
         __cil_tmp31->pipeA_h = 0;
       }
 #line 2972
       goto ldv_39041;
       case_1: ;
 #line 2974
       if ((int )enabled) {
 #line 2974
         __cil_tmp32 = master_priv->sarea_priv;
 #line 2974
         __cil_tmp32->pipeB_w = crtc->mode.hdisplay;
       } else {
 #line 2974
         __cil_tmp33 = master_priv->sarea_priv;
 #line 2974
         __cil_tmp33->pipeB_w = 0;
       }
 #line 2975
       if ((int )enabled) {
 #line 2975
         __cil_tmp34 = master_priv->sarea_priv;
 #line 2975
         __cil_tmp34->pipeB_h = crtc->mode.vdisplay;
       } else {
 #line 2975
         __cil_tmp35 = master_priv->sarea_priv;
 #line 2975
         __cil_tmp35->pipeB_h = 0;
       }
 #line 2976
       goto ldv_39041;
       switch_default: 
       {
 #line 2978
       __cil_tmp36 = pipe + 65;
 #line 2978
       drm_err("intel_crtc_dpms", "Can\'t update pipe %c in SAREA\n", __cil_tmp36);
       }
 #line 2979
       goto ldv_39041;
     } else {
 
     }
   }
   ldv_39041: ;
 #line 2982
   return;
 }
 }
 #line 2983 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_crtc_disable(struct drm_crtc *crtc ) 
 { struct drm_crtc_helper_funcs *crtc_funcs ;
   struct drm_device *dev ;
   struct drm_framebuffer  const  *__mptr ;
   void *__cil_tmp5 ;
   void (*__cil_tmp6)(struct drm_crtc * , int  ) ;
   struct drm_framebuffer *__cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   struct drm_framebuffer *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct mutex *__cil_tmp11 ;
   struct drm_framebuffer *__cil_tmp12 ;
   struct intel_framebuffer *__cil_tmp13 ;
   struct drm_i915_gem_object *__cil_tmp14 ;
   struct mutex *__cil_tmp15 ;
 
   {
   {
 #line 2985
   __cil_tmp5 = crtc->helper_private;
 #line 2985
   crtc_funcs = (struct drm_crtc_helper_funcs *)__cil_tmp5;
 #line 2986
   dev = crtc->dev;
 #line 2988
   __cil_tmp6 = crtc_funcs->dpms;
 #line 2988
   (*__cil_tmp6)(crtc, 3);
   }
   {
 #line 2990
   __cil_tmp7 = (struct drm_framebuffer *)0;
 #line 2990
   __cil_tmp8 = (unsigned long )__cil_tmp7;
 #line 2990
   __cil_tmp9 = crtc->fb;
 #line 2990
   __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 2990
   if (__cil_tmp10 != __cil_tmp8) {
     {
 #line 2991
     __cil_tmp11 = & dev->struct_mutex;
 #line 2991
     mutex_lock_nested(__cil_tmp11, 0U);
 #line 2992
     __cil_tmp12 = crtc->fb;
 #line 2992
     __mptr = (struct drm_framebuffer  const  *)__cil_tmp12;
 #line 2992
     __cil_tmp13 = (struct intel_framebuffer *)__mptr;
 #line 2992
     __cil_tmp14 = __cil_tmp13->obj;
 #line 2992
     i915_gem_object_unpin(__cil_tmp14);
 #line 2993
     __cil_tmp15 = & dev->struct_mutex;
 #line 2993
     mutex_unlock(__cil_tmp15);
     }
   } else {
 
   }
   }
 #line 2995
   return;
 }
 }
 #line 3005 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i9xx_crtc_prepare(struct drm_crtc *crtc ) 
 { 
 
   {
   {
 #line 3007
   i9xx_crtc_disable(crtc);
   }
 #line 3008
   return;
 }
 }
 #line 3010 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i9xx_crtc_commit(struct drm_crtc *crtc ) 
 { 
 
   {
   {
 #line 3012
   i9xx_crtc_enable(crtc);
   }
 #line 3013
   return;
 }
 }
 #line 3015 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_crtc_prepare(struct drm_crtc *crtc ) 
 { 
 
   {
   {
 #line 3017
   ironlake_crtc_disable(crtc);
   }
 #line 3018
   return;
 }
 }
 #line 3020 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_crtc_commit(struct drm_crtc *crtc ) 
 { 
 
   {
   {
 #line 3022
   ironlake_crtc_enable(crtc);
   }
 #line 3023
   return;
 }
 }
 #line 3025 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_encoder_prepare(struct drm_encoder *encoder ) 
 { struct drm_encoder_helper_funcs *encoder_funcs ;
   void *__cil_tmp3 ;
   void (*__cil_tmp4)(struct drm_encoder * , int  ) ;
 
   {
   {
 #line 3027
   __cil_tmp3 = encoder->helper_private;
 #line 3027
   encoder_funcs = (struct drm_encoder_helper_funcs *)__cil_tmp3;
 #line 3029
   __cil_tmp4 = encoder_funcs->dpms;
 #line 3029
   (*__cil_tmp4)(encoder, 3);
   }
 #line 3030
   return;
 }
 }
 #line 3032 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_encoder_commit(struct drm_encoder *encoder ) 
 { struct drm_encoder_helper_funcs *encoder_funcs ;
   void *__cil_tmp3 ;
   void (*__cil_tmp4)(struct drm_encoder * , int  ) ;
 
   {
   {
 #line 3034
   __cil_tmp3 = encoder->helper_private;
 #line 3034
   encoder_funcs = (struct drm_encoder_helper_funcs *)__cil_tmp3;
 #line 3036
   __cil_tmp4 = encoder_funcs->dpms;
 #line 3036
   (*__cil_tmp4)(encoder, 0);
   }
 #line 3037
   return;
 }
 }
 #line 3039 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 void intel_encoder_destroy(struct drm_encoder *encoder ) 
 { struct intel_encoder *intel_encoder ;
   struct drm_encoder  const  *__mptr ;
   void const   *__cil_tmp4 ;
 
   {
   {
 #line 3041
   __mptr = (struct drm_encoder  const  *)encoder;
 #line 3041
   intel_encoder = (struct intel_encoder *)__mptr;
 #line 3043
   drm_encoder_cleanup(encoder);
 #line 3044
   __cil_tmp4 = (void const   *)intel_encoder;
 #line 3044
   kfree(__cil_tmp4);
   }
 #line 3045
   return;
 }
 }
 #line 3047 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc , struct drm_display_mode *mode ,
                                   struct drm_display_mode *adjusted_mode ) 
 { struct drm_device *dev ;
   void *__cil_tmp5 ;
   struct drm_i915_private *__cil_tmp6 ;
   struct intel_device_info  const  *__cil_tmp7 ;
   u8 __cil_tmp8 ;
   unsigned char __cil_tmp9 ;
   unsigned int __cil_tmp10 ;
   void *__cil_tmp11 ;
   struct drm_i915_private *__cil_tmp12 ;
   struct intel_device_info  const  *__cil_tmp13 ;
   u8 __cil_tmp14 ;
   unsigned char __cil_tmp15 ;
   unsigned int __cil_tmp16 ;
   void *__cil_tmp17 ;
   struct drm_i915_private *__cil_tmp18 ;
   struct intel_device_info  const  *__cil_tmp19 ;
   unsigned char *__cil_tmp20 ;
   unsigned char *__cil_tmp21 ;
   unsigned char __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
 
   {
 #line 3051
   dev = crtc->dev;
   {
 #line 3053
   __cil_tmp5 = dev->dev_private;
 #line 3053
   __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
 #line 3053
   __cil_tmp7 = __cil_tmp6->info;
 #line 3053
   __cil_tmp8 = __cil_tmp7->gen;
 #line 3053
   __cil_tmp9 = (unsigned char )__cil_tmp8;
 #line 3053
   __cil_tmp10 = (unsigned int )__cil_tmp9;
 #line 3053
   if (__cil_tmp10 == 5U) {
 #line 3053
     goto _L;
   } else {
     {
 #line 3053
     __cil_tmp11 = dev->dev_private;
 #line 3053
     __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
 #line 3053
     __cil_tmp13 = __cil_tmp12->info;
 #line 3053
     __cil_tmp14 = __cil_tmp13->gen;
 #line 3053
     __cil_tmp15 = (unsigned char )__cil_tmp14;
 #line 3053
     __cil_tmp16 = (unsigned int )__cil_tmp15;
 #line 3053
     if (__cil_tmp16 == 6U) {
 #line 3053
       goto _L;
     } else {
       {
 #line 3053
       __cil_tmp17 = dev->dev_private;
 #line 3053
       __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
 #line 3053
       __cil_tmp19 = __cil_tmp18->info;
 #line 3053
       __cil_tmp20 = (unsigned char *)__cil_tmp19;
 #line 3053
       __cil_tmp21 = __cil_tmp20 + 2UL;
 #line 3053
       __cil_tmp22 = *__cil_tmp21;
 #line 3053
       __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 3053
       if (__cil_tmp23 != 0U) {
         _L: 
         {
 #line 3055
         __cil_tmp24 = mode->clock;
 #line 3055
         __cil_tmp25 = __cil_tmp24 * 3;
 #line 3055
         if (__cil_tmp25 > 10800000) {
 #line 3056
           return ((bool )0);
         } else {
 
         }
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 3062
   __cil_tmp26 = adjusted_mode->crtc_htotal;
 #line 3062
   if (__cil_tmp26 == 0) {
     {
 #line 3063
     drm_mode_set_crtcinfo(adjusted_mode, 0);
     }
   } else {
 
   }
   }
 #line 3065
   return ((bool )1);
 }
 }
 #line 3068 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i945_get_display_clock_speed(struct drm_device *dev ) 
 { 
 
   {
 #line 3070
   return (400000);
 }
 }
 #line 3073 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i915_get_display_clock_speed(struct drm_device *dev ) 
 { 
 
   {
 #line 3075
   return (333000);
 }
 }
 #line 3078 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev ) 
 { 
 
   {
 #line 3080
   return (200000);
 }
 }
 #line 3083 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i915gm_get_display_clock_speed(struct drm_device *dev ) 
 { u16 gcfgc ;
   struct pci_dev *__cil_tmp3 ;
   int __cil_tmp4 ;
   int __cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
 
   {
   {
 #line 3085
   gcfgc = (u16 )0U;
 #line 3087
   __cil_tmp3 = dev->pdev;
 #line 3087
   pci_read_config_word(__cil_tmp3, 240, & gcfgc);
   }
   {
 #line 3089
   __cil_tmp4 = (int )gcfgc;
 #line 3089
   __cil_tmp5 = __cil_tmp4 & 128;
 #line 3089
   if (__cil_tmp5 != 0) {
 #line 3090
     return (133000);
   } else {
     {
 #line 3093
     __cil_tmp6 = (int )gcfgc;
 #line 3093
     __cil_tmp7 = __cil_tmp6 & 112;
 #line 3093
     if (__cil_tmp7 == 64) {
 #line 3093
       goto case_64;
     } else {
       {
 #line 3096
       __cil_tmp8 = (int )gcfgc;
 #line 3096
       __cil_tmp9 = __cil_tmp8 & 112;
 #line 3096
       if (__cil_tmp9 == 0) {
 #line 3096
         goto case_0;
       } else {
 #line 3095
         goto switch_default;
 #line 3092
         if (0) {
           case_64: ;
 #line 3094
           return (333000);
           switch_default: ;
           case_0: ;
 #line 3097
           return (190000);
         } else {
 
         }
       }
       }
     }
     }
   }
   }
 }
 }
 #line 3102 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i865_get_display_clock_speed(struct drm_device *dev ) 
 { 
 
   {
 #line 3104
   return (266000);
 }
 }
 #line 3107 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i855_get_display_clock_speed(struct drm_device *dev ) 
 { u16 hpllcc ;
   int __cil_tmp3 ;
   int __cil_tmp4 ;
   int __cil_tmp5 ;
   int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
 
   {
 #line 3109
   hpllcc = (u16 )0U;
   {
 #line 3114
   __cil_tmp3 = (int )hpllcc;
 #line 3114
   __cil_tmp4 = __cil_tmp3 & 15;
 #line 3114
   if (__cil_tmp4 == 0) {
 #line 3114
     goto case_0;
   } else {
     {
 #line 3115
     __cil_tmp5 = (int )hpllcc;
 #line 3115
     __cil_tmp6 = __cil_tmp5 & 15;
 #line 3115
     if (__cil_tmp6 == 1) {
 #line 3115
       goto case_1;
     } else {
       {
 #line 3117
       __cil_tmp7 = (int )hpllcc;
 #line 3117
       __cil_tmp8 = __cil_tmp7 & 15;
 #line 3117
       if (__cil_tmp8 == 3) {
 #line 3117
         goto case_3;
       } else {
         {
 #line 3119
         __cil_tmp9 = (int )hpllcc;
 #line 3119
         __cil_tmp10 = __cil_tmp9 & 15;
 #line 3119
         if (__cil_tmp10 == 2) {
 #line 3119
           goto case_2;
         } else
 #line 3113
         if (0) {
           case_0: ;
           case_1: ;
 #line 3116
           return (200000);
           case_3: ;
 #line 3118
           return (250000);
           case_2: ;
 #line 3120
           return (133000);
         } else {
 
         }
         }
       }
       }
     }
     }
   }
   }
 #line 3124
   return (0);
 }
 }
 #line 3127 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i830_get_display_clock_speed(struct drm_device *dev ) 
 { 
 
   {
 #line 3129
   return (133000);
 }
 }
 #line 3141 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void fdi_reduce_ratio(u32 *num , u32 *den ) 
 { u32 __cil_tmp3 ;
   u32 __cil_tmp4 ;
   u32 __cil_tmp5 ;
   u32 __cil_tmp6 ;
 
   {
 #line 3143
   goto ldv_39125;
   ldv_39124: 
 #line 3144
   __cil_tmp3 = *num;
 #line 3144
   *num = __cil_tmp3 >> 1;
 #line 3145
   __cil_tmp4 = *den;
 #line 3145
   *den = __cil_tmp4 >> 1;
   ldv_39125: ;
   {
 #line 3143
   __cil_tmp5 = *num;
 #line 3143
   if (__cil_tmp5 > 16777215U) {
 #line 3144
     goto ldv_39124;
   } else {
     {
 #line 3143
     __cil_tmp6 = *den;
 #line 3143
     if (__cil_tmp6 > 16777215U) {
 #line 3144
       goto ldv_39124;
     } else {
 #line 3146
       goto ldv_39126;
     }
     }
   }
   }
   ldv_39126: ;
 #line 3148
   return;
 }
 }
 #line 3150 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_compute_m_n(int bits_per_pixel , int nlanes , int pixel_clock ,
                                  int link_clock , struct fdi_m_n *m_n ) 
 { int __cil_tmp6 ;
   int __cil_tmp7 ;
   int __cil_tmp8 ;
   u32 *__cil_tmp9 ;
   u32 *__cil_tmp10 ;
   u32 *__cil_tmp11 ;
   u32 *__cil_tmp12 ;
 
   {
   {
 #line 3153
   m_n->tu = 64U;
 #line 3156
   __cil_tmp6 = bits_per_pixel * pixel_clock;
 #line 3156
   m_n->gmch_m = (u32 )__cil_tmp6;
 #line 3157
   __cil_tmp7 = link_clock * nlanes;
 #line 3157
   __cil_tmp8 = __cil_tmp7 * 8;
 #line 3157
   m_n->gmch_n = (u32 )__cil_tmp8;
 #line 3158
   __cil_tmp9 = & m_n->gmch_m;
 #line 3158
   __cil_tmp10 = & m_n->gmch_n;
 #line 3158
   fdi_reduce_ratio(__cil_tmp9, __cil_tmp10);
 #line 3160
   m_n->link_m = (u32 )pixel_clock;
 #line 3161
   m_n->link_n = (u32 )link_clock;
 #line 3162
   __cil_tmp11 = & m_n->link_m;
 #line 3162
   __cil_tmp12 = & m_n->link_n;
 #line 3162
   fdi_reduce_ratio(__cil_tmp11, __cil_tmp12);
   }
 #line 3163
   return;
 }
 }
 #line 3175 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  pineview_display_wm  =    {512UL, 511UL, 63UL, 10UL, 64UL};
 #line 3182 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  pineview_display_hplloff_wm  =    {512UL, 511UL, 0UL, 10UL, 64UL};
 #line 3189 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  pineview_cursor_wm  =    {64UL, 63UL, 0UL, 5UL, 64UL};
 #line 3196 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  pineview_cursor_hplloff_wm  =    {64UL, 63UL, 0UL, 5UL, 64UL};
 #line 3203 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  g4x_wm_info  =    {127UL, 63UL, 63UL, 2UL, 64UL};
 #line 3210 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  g4x_cursor_wm_info  =    {64UL, 32UL, 8UL, 2UL, 64UL};
 #line 3217 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  i965_cursor_wm_info  =    {64UL, 32UL, 8UL, 2UL, 64UL};
 #line 3224 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  i945_wm_info  =    {127UL, 63UL, 1UL, 2UL, 64UL};
 #line 3231 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  i915_wm_info  =    {95UL, 63UL, 1UL, 2UL, 64UL};
 #line 3238 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  i855_wm_info  =    {127UL, 63UL, 1UL, 2UL, 32UL};
 #line 3245 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  i830_wm_info  =    {95UL, 63UL, 1UL, 2UL, 32UL};
 #line 3253 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  ironlake_display_wm_info  =    {128UL, 64UL, 8UL, 2UL, 64UL};
 #line 3260 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  ironlake_cursor_wm_info  =    {32UL, 16UL, 8UL, 2UL, 64UL};
 #line 3267 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  ironlake_display_srwm_info  =    {512UL, 511UL, 63UL, 2UL, 64UL};
 #line 3274 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  ironlake_cursor_srwm_info  =    {64UL, 63UL, 8UL, 2UL, 64UL};
 #line 3282 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  sandybridge_display_wm_info  =    {128UL, 127UL, 8UL, 2UL, 64UL};
 #line 3289 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  sandybridge_cursor_wm_info  =    {32UL, 31UL, 8UL, 2UL, 64UL};
 #line 3296 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  sandybridge_display_srwm_info  =    {512UL, 511UL, 63UL, 2UL, 64UL};
 #line 3303 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct intel_watermark_params  const  sandybridge_cursor_srwm_info  =    {64UL, 63UL, 8UL, 2UL, 64UL};
 #line 3330 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static unsigned long intel_calculate_wm(unsigned long clock_in_khz , struct intel_watermark_params  const  *wm ,
                                         int fifo_size , int pixel_size , unsigned long latency_ns___0 ) 
 { long entries_required ;
   long wm_size ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
 
   {
   {
 #line 3344
   __cil_tmp8 = (unsigned long )pixel_size;
 #line 3344
   __cil_tmp9 = clock_in_khz / 1000UL;
 #line 3344
   __cil_tmp10 = __cil_tmp9 * __cil_tmp8;
 #line 3344
   __cil_tmp11 = __cil_tmp10 * latency_ns___0;
 #line 3344
   __cil_tmp12 = __cil_tmp11 / 1000UL;
 #line 3344
   entries_required = (long )__cil_tmp12;
 #line 3346
   __cil_tmp13 = wm->cacheline_size;
 #line 3346
   __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 3346
   __cil_tmp15 = (unsigned long )entries_required;
 #line 3346
   __cil_tmp16 = wm->cacheline_size;
 #line 3346
   __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 3346
   __cil_tmp18 = __cil_tmp17 + __cil_tmp15;
 #line 3346
   __cil_tmp19 = __cil_tmp18 - 1UL;
 #line 3346
   __cil_tmp20 = __cil_tmp19 / __cil_tmp14;
 #line 3346
   entries_required = (long )__cil_tmp20;
 #line 3348
   drm_ut_debug_printk(4U, "drm", "intel_calculate_wm", "FIFO entries required for mode: %ld\n",
                       entries_required);
 #line 3350
   __cil_tmp21 = (unsigned long )entries_required;
 #line 3350
   __cil_tmp22 = wm->guard_size;
 #line 3350
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 3350
   __cil_tmp24 = __cil_tmp23 + __cil_tmp21;
 #line 3350
   __cil_tmp25 = (unsigned long )fifo_size;
 #line 3350
   __cil_tmp26 = __cil_tmp25 - __cil_tmp24;
 #line 3350
   wm_size = (long )__cil_tmp26;
 #line 3352
   drm_ut_debug_printk(4U, "drm", "intel_calculate_wm", "FIFO watermark level: %ld\n",
                       wm_size);
   }
   {
 #line 3355
   __cil_tmp27 = wm->max_wm;
 #line 3355
   __cil_tmp28 = (long )__cil_tmp27;
 #line 3355
   if (__cil_tmp28 < wm_size) {
 #line 3356
     __cil_tmp29 = wm->max_wm;
 #line 3356
     wm_size = (long )__cil_tmp29;
   } else {
 
   }
   }
 #line 3357
   if (wm_size <= 0L) {
 #line 3358
     __cil_tmp30 = wm->default_wm;
 #line 3358
     wm_size = (long )__cil_tmp30;
   } else {
 
   }
 #line 3359
   return ((unsigned long )wm_size);
 }
 }
 #line 3373 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct cxsr_latency  const  cxsr_latency_table[30U]  = 
 #line 3373
   {      {1, 0, 800UL, 400UL, 3382UL, 33382UL, 3983UL, 33983UL}, 
         {1, 0, 800UL, 667UL, 3354UL, 33354UL, 3807UL, 33807UL}, 
         {1, 0, 800UL, 800UL, 3347UL, 33347UL, 3763UL, 33763UL}, 
         {1, 1, 800UL, 667UL, 6420UL, 36420UL, 6873UL, 36873UL}, 
         {1, 1, 800UL, 800UL, 5902UL, 35902UL, 6318UL, 36318UL}, 
         {1, 0, 667UL, 400UL, 3400UL, 33400UL, 4021UL, 34021UL}, 
         {1, 0, 667UL, 667UL, 3372UL, 33372UL, 3845UL, 33845UL}, 
         {1, 0, 667UL, 800UL, 3386UL, 33386UL, 3822UL, 33822UL}, 
         {1, 1, 667UL, 667UL, 6438UL, 36438UL, 6911UL, 36911UL}, 
         {1, 1, 667UL, 800UL, 5941UL, 35941UL, 6377UL, 36377UL}, 
         {1, 0, 400UL, 400UL, 3472UL, 33472UL, 4173UL, 34173UL}, 
         {1, 0, 400UL, 667UL, 3443UL, 33443UL, 3996UL, 33996UL}, 
         {1, 0, 400UL, 800UL, 3430UL, 33430UL, 3946UL, 33946UL}, 
         {1, 1, 400UL, 667UL, 6509UL, 36509UL, 7062UL, 37062UL}, 
         {1, 1, 400UL, 800UL, 5985UL, 35985UL, 6501UL, 36501UL}, 
         {0, 0, 800UL, 400UL, 3438UL, 33438UL, 4065UL, 34065UL}, 
         {0, 0, 800UL, 667UL, 3410UL, 33410UL, 3889UL, 33889UL}, 
         {0, 0, 800UL, 800UL, 3403UL, 33403UL, 3845UL, 33845UL}, 
         {0, 1, 800UL, 667UL, 6476UL, 36476UL, 6955UL, 36955UL}, 
         {0, 1, 800UL, 800UL, 5958UL, 35958UL, 6400UL, 36400UL}, 
         {0, 0, 667UL, 400UL, 3456UL, 33456UL, 4103UL, 34106UL}, 
         {0, 0, 667UL, 667UL, 3428UL, 33428UL, 3927UL, 33927UL}, 
         {0, 0, 667UL, 800UL, 3443UL, 33443UL, 3905UL, 33905UL}, 
         {0, 1, 667UL, 667UL, 6494UL, 36494UL, 6993UL, 36993UL}, 
         {0, 1, 667UL, 800UL, 5998UL, 35998UL, 6460UL, 36460UL}, 
         {0, 0, 400UL, 400UL, 3528UL, 33528UL, 4255UL, 34255UL}, 
         {0, 0, 400UL, 667UL, 3500UL, 33500UL, 4079UL, 34079UL}, 
         {0, 0, 400UL, 800UL, 3487UL, 33487UL, 4029UL, 34029UL}, 
         {0, 1, 400UL, 667UL, 6566UL, 36566UL, 7145UL, 37145UL}, 
         {0, 1, 400UL, 800UL, 6042UL, 36042UL, 6584UL, 36584UL}};
 #line 3411 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct cxsr_latency  const  *intel_get_cxsr_latency(int is_desktop , int is_ddr3 ,
                                                            int fsb , int mem ) 
 { struct cxsr_latency  const  *latency ;
   int i ;
   unsigned long __cil_tmp7 ;
   struct cxsr_latency  const  *__cil_tmp8 ;
   int __cil_tmp9 ;
   int __cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   unsigned long __cil_tmp18 ;
   unsigned int __cil_tmp19 ;
 
   {
 #line 3419
   if (fsb == 0) {
 #line 3420
     return ((struct cxsr_latency  const  *)0);
   } else
 #line 3419
   if (mem == 0) {
 #line 3420
     return ((struct cxsr_latency  const  *)0);
   } else {
 
   }
 #line 3422
   i = 0;
 #line 3422
   goto ldv_39190;
   ldv_39189: 
 #line 3423
   __cil_tmp7 = (unsigned long )i;
 #line 3423
   __cil_tmp8 = (struct cxsr_latency  const  *)(& cxsr_latency_table);
 #line 3423
   latency = __cil_tmp8 + __cil_tmp7;
   {
 #line 3424
   __cil_tmp9 = latency->is_desktop;
 #line 3424
   __cil_tmp10 = (int )__cil_tmp9;
 #line 3424
   if (__cil_tmp10 == is_desktop) {
     {
 #line 3424
     __cil_tmp11 = latency->is_ddr3;
 #line 3424
     __cil_tmp12 = (int )__cil_tmp11;
 #line 3424
     if (__cil_tmp12 == is_ddr3) {
       {
 #line 3424
       __cil_tmp13 = latency->fsb_freq;
 #line 3424
       __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 3424
       __cil_tmp15 = (unsigned long )fsb;
 #line 3424
       if (__cil_tmp15 == __cil_tmp14) {
         {
 #line 3424
         __cil_tmp16 = latency->mem_freq;
 #line 3424
         __cil_tmp17 = (unsigned long )__cil_tmp16;
 #line 3424
         __cil_tmp18 = (unsigned long )mem;
 #line 3424
         if (__cil_tmp18 == __cil_tmp17) {
 #line 3427
           return (latency);
         } else {
 
         }
         }
       } else {
 
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 3422
   i = i + 1;
   ldv_39190: ;
   {
 #line 3422
   __cil_tmp19 = (unsigned int )i;
 #line 3422
   if (__cil_tmp19 <= 29U) {
 #line 3423
     goto ldv_39189;
   } else {
 #line 3425
     goto ldv_39191;
   }
   }
   ldv_39191: 
   {
 #line 3430
   drm_ut_debug_printk(4U, "drm", "intel_get_cxsr_latency", "Unknown FSB/MEM found, disable CxSR\n");
   }
 #line 3432
   return ((struct cxsr_latency  const  *)0);
 }
 }
 #line 3435 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void pineview_disable_cxsr(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   void *__cil_tmp4 ;
   unsigned int __cil_tmp5 ;
 
   {
   {
 #line 3437
   __cil_tmp4 = dev->dev_private;
 #line 3437
   dev_priv = (struct drm_i915_private *)__cil_tmp4;
 #line 3440
   tmp = i915_read32___6(dev_priv, 458812U);
 #line 3440
   __cil_tmp5 = tmp & 3221225471U;
 #line 3440
   i915_write32___4(dev_priv, 458812U, __cil_tmp5);
   }
 #line 3441
   return;
 }
 }
 #line 3457 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int const   latency_ns  =    (int const   )5000;
 #line 3459 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i9xx_get_fifo_size(struct drm_device *dev , int plane ) 
 { struct drm_i915_private *dev_priv ;
   uint32_t dsparb ;
   u32 tmp ;
   int size ;
   char *tmp___0 ;
   void *__cil_tmp8 ;
   int __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
 
   {
   {
 #line 3461
   __cil_tmp8 = dev->dev_private;
 #line 3461
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 3462
   tmp = i915_read32___6(dev_priv, 458800U);
 #line 3462
   dsparb = tmp;
 #line 3465
   __cil_tmp9 = (int )dsparb;
 #line 3465
   size = __cil_tmp9 & 127;
   }
 #line 3466
   if (plane != 0) {
 #line 3467
     __cil_tmp10 = (uint32_t )size;
 #line 3467
     __cil_tmp11 = dsparb >> 7;
 #line 3467
     __cil_tmp12 = __cil_tmp11 & 127U;
 #line 3467
     __cil_tmp13 = __cil_tmp12 - __cil_tmp10;
 #line 3467
     size = (int )__cil_tmp13;
   } else {
 
   }
 #line 3469
   if (plane != 0) {
 #line 3469
     tmp___0 = (char *)"B";
   } else {
 #line 3469
     tmp___0 = (char *)"A";
   }
   {
 #line 3469
   drm_ut_debug_printk(4U, "drm", "i9xx_get_fifo_size", "FIFO size - (0x%08x) %s: %d\n",
                       dsparb, tmp___0, size);
   }
 #line 3472
   return (size);
 }
 }
 #line 3475 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i85x_get_fifo_size(struct drm_device *dev , int plane ) 
 { struct drm_i915_private *dev_priv ;
   uint32_t dsparb ;
   u32 tmp ;
   int size ;
   char *tmp___0 ;
   void *__cil_tmp8 ;
   int __cil_tmp9 ;
   uint32_t __cil_tmp10 ;
   uint32_t __cil_tmp11 ;
   unsigned int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
 
   {
   {
 #line 3477
   __cil_tmp8 = dev->dev_private;
 #line 3477
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 3478
   tmp = i915_read32___6(dev_priv, 458800U);
 #line 3478
   dsparb = tmp;
 #line 3481
   __cil_tmp9 = (int )dsparb;
 #line 3481
   size = __cil_tmp9 & 511;
   }
 #line 3482
   if (plane != 0) {
 #line 3483
     __cil_tmp10 = (uint32_t )size;
 #line 3483
     __cil_tmp11 = dsparb >> 9;
 #line 3483
     __cil_tmp12 = __cil_tmp11 & 511U;
 #line 3483
     __cil_tmp13 = __cil_tmp12 - __cil_tmp10;
 #line 3483
     size = (int )__cil_tmp13;
   } else {
 
   }
 #line 3484
   size = size >> 1;
 #line 3486
   if (plane != 0) {
 #line 3486
     tmp___0 = (char *)"B";
   } else {
 #line 3486
     tmp___0 = (char *)"A";
   }
   {
 #line 3486
   drm_ut_debug_printk(4U, "drm", "i85x_get_fifo_size", "FIFO size - (0x%08x) %s: %d\n",
                       dsparb, tmp___0, size);
   }
 #line 3489
   return (size);
 }
 }
 #line 3492 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i845_get_fifo_size(struct drm_device *dev , int plane ) 
 { struct drm_i915_private *dev_priv ;
   uint32_t dsparb ;
   u32 tmp ;
   int size ;
   char *tmp___0 ;
   void *__cil_tmp8 ;
   int __cil_tmp9 ;
 
   {
   {
 #line 3494
   __cil_tmp8 = dev->dev_private;
 #line 3494
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 3495
   tmp = i915_read32___6(dev_priv, 458800U);
 #line 3495
   dsparb = tmp;
 #line 3498
   __cil_tmp9 = (int )dsparb;
 #line 3498
   size = __cil_tmp9 & 127;
 #line 3499
   size = size >> 2;
   }
 #line 3501
   if (plane != 0) {
 #line 3501
     tmp___0 = (char *)"B";
   } else {
 #line 3501
     tmp___0 = (char *)"A";
   }
   {
 #line 3501
   drm_ut_debug_printk(4U, "drm", "i845_get_fifo_size", "FIFO size - (0x%08x) %s: %d\n",
                       dsparb, tmp___0, size);
   }
 #line 3505
   return (size);
 }
 }
 #line 3508 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i830_get_fifo_size(struct drm_device *dev , int plane ) 
 { struct drm_i915_private *dev_priv ;
   uint32_t dsparb ;
   u32 tmp ;
   int size ;
   char *tmp___0 ;
   void *__cil_tmp8 ;
   int __cil_tmp9 ;
 
   {
   {
 #line 3510
   __cil_tmp8 = dev->dev_private;
 #line 3510
   dev_priv = (struct drm_i915_private *)__cil_tmp8;
 #line 3511
   tmp = i915_read32___6(dev_priv, 458800U);
 #line 3511
   dsparb = tmp;
 #line 3514
   __cil_tmp9 = (int )dsparb;
 #line 3514
   size = __cil_tmp9 & 127;
 #line 3515
   size = size >> 1;
   }
 #line 3517
   if (plane != 0) {
 #line 3517
     tmp___0 = (char *)"B";
   } else {
 #line 3517
     tmp___0 = (char *)"A";
   }
   {
 #line 3517
   drm_ut_debug_printk(4U, "drm", "i830_get_fifo_size", "FIFO size - (0x%08x) %s: %d\n",
                       dsparb, tmp___0, size);
   }
 #line 3520
   return (size);
 }
 }
 #line 3523 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev ) 
 { struct drm_crtc *crtc ;
   struct drm_crtc *enabled ;
   struct list_head  const  *__mptr ;
   struct list_head  const  *__mptr___0 ;
   struct list_head *__cil_tmp6 ;
   struct drm_crtc *__cil_tmp7 ;
   bool __cil_tmp8 ;
   struct drm_framebuffer *__cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   struct drm_framebuffer *__cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   struct drm_crtc *__cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct list_head *__cil_tmp16 ;
   struct drm_crtc *__cil_tmp17 ;
   struct list_head *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct list_head *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
 
   {
 #line 3525
   enabled = (struct drm_crtc *)0;
 #line 3527
   __cil_tmp6 = dev->mode_config.crtc_list.next;
 #line 3527
   __mptr = (struct list_head  const  *)__cil_tmp6;
 #line 3527
   __cil_tmp7 = (struct drm_crtc *)__mptr;
 #line 3527
   crtc = __cil_tmp7 + 1152921504606846968UL;
 #line 3527
   goto ldv_39240;
   ldv_39239: ;
   {
 #line 3528
   __cil_tmp8 = crtc->enabled;
 #line 3528
   if ((int )__cil_tmp8) {
     {
 #line 3528
     __cil_tmp9 = (struct drm_framebuffer *)0;
 #line 3528
     __cil_tmp10 = (unsigned long )__cil_tmp9;
 #line 3528
     __cil_tmp11 = crtc->fb;
 #line 3528
     __cil_tmp12 = (unsigned long )__cil_tmp11;
 #line 3528
     if (__cil_tmp12 != __cil_tmp10) {
       {
 #line 3529
       __cil_tmp13 = (struct drm_crtc *)0;
 #line 3529
       __cil_tmp14 = (unsigned long )__cil_tmp13;
 #line 3529
       __cil_tmp15 = (unsigned long )enabled;
 #line 3529
       if (__cil_tmp15 != __cil_tmp14) {
 #line 3530
         return ((struct drm_crtc *)0);
       } else {
 
       }
       }
 #line 3531
       enabled = crtc;
     } else {
 
     }
     }
   } else {
 
   }
   }
 #line 3527
   __cil_tmp16 = crtc->head.next;
 #line 3527
   __mptr___0 = (struct list_head  const  *)__cil_tmp16;
 #line 3527
   __cil_tmp17 = (struct drm_crtc *)__mptr___0;
 #line 3527
   crtc = __cil_tmp17 + 1152921504606846968UL;
   ldv_39240: ;
   {
 #line 3527
   __cil_tmp18 = & dev->mode_config.crtc_list;
 #line 3527
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 3527
   __cil_tmp20 = & crtc->head;
 #line 3527
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 3527
   if (__cil_tmp21 != __cil_tmp19) {
 #line 3528
     goto ldv_39239;
   } else {
 #line 3530
     goto ldv_39241;
   }
   }
   ldv_39241: ;
 #line 3535
   return (enabled);
 }
 }
 #line 3538 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void pineview_update_wm(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_crtc *crtc ;
   struct cxsr_latency  const  *latency ;
   u32 reg ;
   unsigned long wm ;
   int clock ;
   int pixel_size ;
   u32 tmp ;
   void *__cil_tmp10 ;
   int __cil_tmp11 ;
   int __cil_tmp12 ;
   unsigned int __cil_tmp13 ;
   int __cil_tmp14 ;
   unsigned int __cil_tmp15 ;
   int __cil_tmp16 ;
   unsigned int __cil_tmp17 ;
   int __cil_tmp18 ;
   struct cxsr_latency  const  *__cil_tmp19 ;
   unsigned long __cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   struct drm_crtc *__cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   struct drm_framebuffer *__cil_tmp25 ;
   int __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   int __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   u32 __cil_tmp31 ;
   u32 __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   int __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   u32 __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   int __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   u32 __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   int __cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   u32 __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
 
   {
   {
 #line 3540
   __cil_tmp10 = dev->dev_private;
 #line 3540
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 3546
   __cil_tmp11 = dev->pci_device;
 #line 3546
   __cil_tmp12 = __cil_tmp11 == 40961;
 #line 3546
   __cil_tmp13 = dev_priv->is_ddr3;
 #line 3546
   __cil_tmp14 = (int )__cil_tmp13;
 #line 3546
   __cil_tmp15 = dev_priv->fsb_freq;
 #line 3546
   __cil_tmp16 = (int )__cil_tmp15;
 #line 3546
   __cil_tmp17 = dev_priv->mem_freq;
 #line 3546
   __cil_tmp18 = (int )__cil_tmp17;
 #line 3546
   latency = intel_get_cxsr_latency(__cil_tmp12, __cil_tmp14, __cil_tmp16, __cil_tmp18);
   }
   {
 #line 3548
   __cil_tmp19 = (struct cxsr_latency  const  *)0;
 #line 3548
   __cil_tmp20 = (unsigned long )__cil_tmp19;
 #line 3548
   __cil_tmp21 = (unsigned long )latency;
 #line 3548
   if (__cil_tmp21 == __cil_tmp20) {
     {
 #line 3549
     drm_ut_debug_printk(4U, "drm", "pineview_update_wm", "Unknown FSB/MEM found, disable CxSR\n");
 #line 3550
     pineview_disable_cxsr(dev);
     }
 #line 3551
     return;
   } else {
 
   }
   }
   {
 #line 3554
   crtc = single_enabled_crtc(dev);
   }
   {
 #line 3555
   __cil_tmp22 = (struct drm_crtc *)0;
 #line 3555
   __cil_tmp23 = (unsigned long )__cil_tmp22;
 #line 3555
   __cil_tmp24 = (unsigned long )crtc;
 #line 3555
   if (__cil_tmp24 != __cil_tmp23) {
     {
 #line 3556
     clock = crtc->mode.clock;
 #line 3557
     __cil_tmp25 = crtc->fb;
 #line 3557
     __cil_tmp26 = __cil_tmp25->bits_per_pixel;
 #line 3557
     pixel_size = __cil_tmp26 / 8;
 #line 3560
     __cil_tmp27 = (unsigned long )clock;
 #line 3560
     __cil_tmp28 = (int )pineview_display_wm.fifo_size;
 #line 3560
     __cil_tmp29 = latency->display_sr;
 #line 3560
     __cil_tmp30 = (unsigned long )__cil_tmp29;
 #line 3560
     wm = intel_calculate_wm(__cil_tmp27, & pineview_display_wm, __cil_tmp28, pixel_size,
                             __cil_tmp30);
 #line 3563
     reg = i915_read32___6(dev_priv, 458804U);
 #line 3564
     reg = reg & 8388607U;
 #line 3565
     __cil_tmp31 = (u32 )wm;
 #line 3565
     __cil_tmp32 = __cil_tmp31 << 23U;
 #line 3565
     reg = __cil_tmp32 | reg;
 #line 3566
     i915_write32___4(dev_priv, 458804U, reg);
 #line 3567
     drm_ut_debug_printk(4U, "drm", "pineview_update_wm", "DSPFW1 register is %x\n",
                         reg);
 #line 3570
     __cil_tmp33 = (unsigned long )clock;
 #line 3570
     __cil_tmp34 = (int )pineview_display_wm.fifo_size;
 #line 3570
     __cil_tmp35 = latency->cursor_sr;
 #line 3570
     __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 3570
     wm = intel_calculate_wm(__cil_tmp33, & pineview_cursor_wm, __cil_tmp34, pixel_size,
                             __cil_tmp36);
 #line 3573
     reg = i915_read32___6(dev_priv, 458812U);
 #line 3574
     reg = reg & 3238002687U;
 #line 3575
     __cil_tmp37 = (u32 )wm;
 #line 3575
     __cil_tmp38 = __cil_tmp37 & 63U;
 #line 3575
     __cil_tmp39 = __cil_tmp38 << 24U;
 #line 3575
     reg = __cil_tmp39 | reg;
 #line 3576
     i915_write32___4(dev_priv, 458812U, reg);
 #line 3579
     __cil_tmp40 = (unsigned long )clock;
 #line 3579
     __cil_tmp41 = (int )pineview_display_hplloff_wm.fifo_size;
 #line 3579
     __cil_tmp42 = latency->display_hpll_disable;
 #line 3579
     __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 3579
     wm = intel_calculate_wm(__cil_tmp40, & pineview_display_hplloff_wm, __cil_tmp41,
                             pixel_size, __cil_tmp43);
 #line 3582
     reg = i915_read32___6(dev_priv, 458812U);
 #line 3583
     reg = reg & 4294966784U;
 #line 3584
     __cil_tmp44 = (u32 )wm;
 #line 3584
     __cil_tmp45 = __cil_tmp44 & 511U;
 #line 3584
     reg = __cil_tmp45 | reg;
 #line 3585
     i915_write32___4(dev_priv, 458812U, reg);
 #line 3588
     __cil_tmp46 = (unsigned long )clock;
 #line 3588
     __cil_tmp47 = (int )pineview_display_hplloff_wm.fifo_size;
 #line 3588
     __cil_tmp48 = latency->cursor_hpll_disable;
 #line 3588
     __cil_tmp49 = (unsigned long )__cil_tmp48;
 #line 3588
     wm = intel_calculate_wm(__cil_tmp46, & pineview_cursor_hplloff_wm, __cil_tmp47,
                             pixel_size, __cil_tmp49);
 #line 3591
     reg = i915_read32___6(dev_priv, 458812U);
 #line 3592
     reg = reg & 4290838527U;
 #line 3593
     __cil_tmp50 = (u32 )wm;
 #line 3593
     __cil_tmp51 = __cil_tmp50 & 63U;
 #line 3593
     __cil_tmp52 = __cil_tmp51 << 16U;
 #line 3593
     reg = __cil_tmp52 | reg;
 #line 3594
     i915_write32___4(dev_priv, 458812U, reg);
 #line 3595
     drm_ut_debug_printk(4U, "drm", "pineview_update_wm", "DSPFW3 register is %x\n",
                         reg);
 #line 3598
     tmp = i915_read32___6(dev_priv, 458812U);
 #line 3598
     __cil_tmp53 = tmp | 1073741824U;
 #line 3598
     i915_write32___4(dev_priv, 458812U, __cil_tmp53);
 #line 3600
     drm_ut_debug_printk(4U, "drm", "pineview_update_wm", "Self-refresh is enabled\n");
     }
   } else {
     {
 #line 3602
     pineview_disable_cxsr(dev);
 #line 3603
     drm_ut_debug_printk(4U, "drm", "pineview_update_wm", "Self-refresh is disabled\n");
     }
   }
   }
 #line 3605
   return;
 }
 }
 #line 3607 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool g4x_compute_wm0(struct drm_device *dev , int plane , struct intel_watermark_params  const  *display ,
                             int display_latency_ns , struct intel_watermark_params  const  *cursor ,
                             int cursor_latency_ns , int *plane_wm , int *cursor_wm ) 
 { struct drm_crtc *crtc ;
   int htotal ;
   int hdisplay ;
   int clock ;
   int pixel_size ;
   int line_time_us ;
   int line_count ;
   int entries ;
   int tlb_miss ;
   struct drm_framebuffer *__cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   struct drm_framebuffer *__cil_tmp20 ;
   unsigned long __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned long __cil_tmp23 ;
   bool __cil_tmp24 ;
   unsigned long __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   struct drm_framebuffer *__cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   unsigned int __cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   int __cil_tmp53 ;
   int __cil_tmp54 ;
   unsigned long __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   unsigned int __cil_tmp63 ;
   unsigned long __cil_tmp64 ;
   unsigned int __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   unsigned long __cil_tmp68 ;
   unsigned long __cil_tmp69 ;
   unsigned long __cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   unsigned long __cil_tmp73 ;
   unsigned long __cil_tmp74 ;
   unsigned long __cil_tmp75 ;
   unsigned int __cil_tmp76 ;
   unsigned long __cil_tmp77 ;
   unsigned int __cil_tmp78 ;
   unsigned int __cil_tmp79 ;
   unsigned long __cil_tmp80 ;
   int __cil_tmp81 ;
   int __cil_tmp82 ;
   unsigned long __cil_tmp83 ;
 
   {
   {
 #line 3621
   crtc = intel_get_crtc_for_plane(dev, plane);
   }
   {
 #line 3622
   __cil_tmp18 = (struct drm_framebuffer *)0;
 #line 3622
   __cil_tmp19 = (unsigned long )__cil_tmp18;
 #line 3622
   __cil_tmp20 = crtc->fb;
 #line 3622
   __cil_tmp21 = (unsigned long )__cil_tmp20;
 #line 3622
   if (__cil_tmp21 == __cil_tmp19) {
 #line 3623
     __cil_tmp22 = cursor->guard_size;
 #line 3623
     *cursor_wm = (int )__cil_tmp22;
 #line 3624
     __cil_tmp23 = display->guard_size;
 #line 3624
     *plane_wm = (int )__cil_tmp23;
 #line 3625
     return ((bool )0);
   } else {
     {
 #line 3622
     __cil_tmp24 = crtc->enabled;
 #line 3622
     if (! __cil_tmp24) {
 #line 3623
       __cil_tmp25 = cursor->guard_size;
 #line 3623
       *cursor_wm = (int )__cil_tmp25;
 #line 3624
       __cil_tmp26 = display->guard_size;
 #line 3624
       *plane_wm = (int )__cil_tmp26;
 #line 3625
       return ((bool )0);
     } else {
 
     }
     }
   }
   }
 #line 3628
   htotal = crtc->mode.htotal;
 #line 3629
   hdisplay = crtc->mode.hdisplay;
 #line 3630
   clock = crtc->mode.clock;
 #line 3631
   __cil_tmp27 = crtc->fb;
 #line 3631
   __cil_tmp28 = __cil_tmp27->bits_per_pixel;
 #line 3631
   pixel_size = __cil_tmp28 / 8;
 #line 3634
   __cil_tmp29 = clock * pixel_size;
 #line 3634
   __cil_tmp30 = __cil_tmp29 / 1000;
 #line 3634
   __cil_tmp31 = __cil_tmp30 * display_latency_ns;
 #line 3634
   entries = __cil_tmp31 / 1000;
 #line 3635
   __cil_tmp32 = hdisplay * -8;
 #line 3635
   __cil_tmp33 = (unsigned int )__cil_tmp32;
 #line 3635
   __cil_tmp34 = display->cacheline_size;
 #line 3635
   __cil_tmp35 = (unsigned int )__cil_tmp34;
 #line 3635
   __cil_tmp36 = display->fifo_size;
 #line 3635
   __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 3635
   __cil_tmp38 = __cil_tmp37 * __cil_tmp35;
 #line 3635
   __cil_tmp39 = __cil_tmp38 + __cil_tmp33;
 #line 3635
   tlb_miss = (int )__cil_tmp39;
 #line 3636
   if (tlb_miss > 0) {
 #line 3637
     entries = entries + tlb_miss;
   } else {
 
   }
 #line 3638
   __cil_tmp40 = display->cacheline_size;
 #line 3638
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 3638
   __cil_tmp42 = display->cacheline_size;
 #line 3638
   __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 3638
   __cil_tmp44 = (unsigned long )entries;
 #line 3638
   __cil_tmp45 = __cil_tmp44 + __cil_tmp43;
 #line 3638
   __cil_tmp46 = __cil_tmp45 - 1UL;
 #line 3638
   __cil_tmp47 = __cil_tmp46 / __cil_tmp41;
 #line 3638
   entries = (int )__cil_tmp47;
 #line 3639
   __cil_tmp48 = (unsigned int )entries;
 #line 3639
   __cil_tmp49 = display->guard_size;
 #line 3639
   __cil_tmp50 = (unsigned int )__cil_tmp49;
 #line 3639
   __cil_tmp51 = __cil_tmp50 + __cil_tmp48;
 #line 3639
   *plane_wm = (int )__cil_tmp51;
   {
 #line 3640
   __cil_tmp52 = display->max_wm;
 #line 3640
   __cil_tmp53 = (int )__cil_tmp52;
 #line 3640
   __cil_tmp54 = *plane_wm;
 #line 3640
   if (__cil_tmp54 > __cil_tmp53) {
 #line 3641
     __cil_tmp55 = display->max_wm;
 #line 3641
     *plane_wm = (int )__cil_tmp55;
   } else {
 
   }
   }
 #line 3644
   __cil_tmp56 = htotal * 1000;
 #line 3644
   line_time_us = __cil_tmp56 / clock;
 #line 3645
   __cil_tmp57 = cursor_latency_ns / line_time_us;
 #line 3645
   __cil_tmp58 = __cil_tmp57 + 1000;
 #line 3645
   line_count = __cil_tmp58 / 1000;
 #line 3646
   __cil_tmp59 = line_count * 64;
 #line 3646
   entries = __cil_tmp59 * pixel_size;
 #line 3647
   __cil_tmp60 = hdisplay * -8;
 #line 3647
   __cil_tmp61 = (unsigned int )__cil_tmp60;
 #line 3647
   __cil_tmp62 = cursor->cacheline_size;
 #line 3647
   __cil_tmp63 = (unsigned int )__cil_tmp62;
 #line 3647
   __cil_tmp64 = cursor->fifo_size;
 #line 3647
   __cil_tmp65 = (unsigned int )__cil_tmp64;
 #line 3647
   __cil_tmp66 = __cil_tmp65 * __cil_tmp63;
 #line 3647
   __cil_tmp67 = __cil_tmp66 + __cil_tmp61;
 #line 3647
   tlb_miss = (int )__cil_tmp67;
 #line 3648
   if (tlb_miss > 0) {
 #line 3649
     entries = entries + tlb_miss;
   } else {
 
   }
 #line 3650
   __cil_tmp68 = cursor->cacheline_size;
 #line 3650
   __cil_tmp69 = (unsigned long )__cil_tmp68;
 #line 3650
   __cil_tmp70 = cursor->cacheline_size;
 #line 3650
   __cil_tmp71 = (unsigned long )__cil_tmp70;
 #line 3650
   __cil_tmp72 = (unsigned long )entries;
 #line 3650
   __cil_tmp73 = __cil_tmp72 + __cil_tmp71;
 #line 3650
   __cil_tmp74 = __cil_tmp73 - 1UL;
 #line 3650
   __cil_tmp75 = __cil_tmp74 / __cil_tmp69;
 #line 3650
   entries = (int )__cil_tmp75;
 #line 3651
   __cil_tmp76 = (unsigned int )entries;
 #line 3651
   __cil_tmp77 = cursor->guard_size;
 #line 3651
   __cil_tmp78 = (unsigned int )__cil_tmp77;
 #line 3651
   __cil_tmp79 = __cil_tmp78 + __cil_tmp76;
 #line 3651
   *cursor_wm = (int )__cil_tmp79;
   {
 #line 3652
   __cil_tmp80 = cursor->max_wm;
 #line 3652
   __cil_tmp81 = (int )__cil_tmp80;
 #line 3652
   __cil_tmp82 = *cursor_wm;
 #line 3652
   if (__cil_tmp82 > __cil_tmp81) {
 #line 3653
     __cil_tmp83 = cursor->max_wm;
 #line 3653
     *cursor_wm = (int )__cil_tmp83;
   } else {
 
   }
   }
 #line 3655
   return ((bool )1);
 }
 }
 #line 3665 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool g4x_check_srwm(struct drm_device *dev , int display_wm , int cursor_wm ,
                            struct intel_watermark_params  const  *display , struct intel_watermark_params  const  *cursor ) 
 { unsigned long __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
   unsigned long __cil_tmp9 ;
   unsigned long __cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
 
   {
   {
 #line 3670
   drm_ut_debug_printk(4U, "drm", "g4x_check_srwm", "SR watermark: display plane %d, cursor %d\n",
                       display_wm, cursor_wm);
   }
   {
 #line 3673
   __cil_tmp6 = display->max_wm;
 #line 3673
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 3673
   __cil_tmp8 = (unsigned long )display_wm;
 #line 3673
   if (__cil_tmp8 > __cil_tmp7) {
     {
 #line 3674
     __cil_tmp9 = display->max_wm;
 #line 3674
     drm_ut_debug_printk(4U, "drm", "g4x_check_srwm", "display watermark is too large(%d/%ld), disabling\n",
                         display_wm, __cil_tmp9);
     }
 #line 3676
     return ((bool )0);
   } else {
 
   }
   }
   {
 #line 3679
   __cil_tmp10 = cursor->max_wm;
 #line 3679
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3679
   __cil_tmp12 = (unsigned long )cursor_wm;
 #line 3679
   if (__cil_tmp12 > __cil_tmp11) {
     {
 #line 3680
     __cil_tmp13 = cursor->max_wm;
 #line 3680
     drm_ut_debug_printk(4U, "drm", "g4x_check_srwm", "cursor watermark is too large(%d/%ld), disabling\n",
                         cursor_wm, __cil_tmp13);
     }
 #line 3682
     return ((bool )0);
   } else {
 
   }
   }
 #line 3685
   if (display_wm == 0) {
 #line 3685
     if (cursor_wm == 0) {
       {
 #line 3686
       drm_ut_debug_printk(4U, "drm", "g4x_check_srwm", "SR latency is 0, disabling\n");
       }
 #line 3687
       return ((bool )0);
     } else {
 
     }
   } else {
 
   }
 #line 3690
   return ((bool )1);
 }
 }
 #line 3693 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool g4x_compute_srwm(struct drm_device *dev , int plane , int latency_ns___0 ,
                              struct intel_watermark_params  const  *display , struct intel_watermark_params  const  *cursor ,
                              int *display_wm , int *cursor_wm ) 
 { struct drm_crtc *crtc ;
   int hdisplay ;
   int htotal ;
   int pixel_size ;
   int clock ;
   unsigned long line_time_us ;
   int line_count ;
   int line_size ;
   int small ;
   int large ;
   int entries ;
   int tmp ;
   int _min1 ;
   int _min2 ;
   int tmp___0 ;
   bool tmp___1 ;
   struct drm_framebuffer *__cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   int __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned long __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned int __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   int __cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   unsigned long __cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   unsigned long __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   int __cil_tmp60 ;
   int __cil_tmp61 ;
 
   {
 #line 3707
   if (latency_ns___0 == 0) {
 #line 3708
     tmp = 0;
 #line 3708
     *cursor_wm = tmp;
 #line 3708
     *display_wm = tmp;
 #line 3709
     return ((bool )0);
   } else {
 
   }
   {
 #line 3712
   crtc = intel_get_crtc_for_plane(dev, plane);
 #line 3713
   hdisplay = crtc->mode.hdisplay;
 #line 3714
   htotal = crtc->mode.htotal;
 #line 3715
   clock = crtc->mode.clock;
 #line 3716
   __cil_tmp24 = crtc->fb;
 #line 3716
   __cil_tmp25 = __cil_tmp24->bits_per_pixel;
 #line 3716
   pixel_size = __cil_tmp25 / 8;
 #line 3718
   __cil_tmp26 = htotal * 1000;
 #line 3718
   __cil_tmp27 = __cil_tmp26 / clock;
 #line 3718
   line_time_us = (unsigned long )__cil_tmp27;
 #line 3719
   __cil_tmp28 = (unsigned long )latency_ns___0;
 #line 3719
   __cil_tmp29 = __cil_tmp28 / line_time_us;
 #line 3719
   __cil_tmp30 = __cil_tmp29 + 1000UL;
 #line 3719
   __cil_tmp31 = __cil_tmp30 / 1000UL;
 #line 3719
   line_count = (int )__cil_tmp31;
 #line 3720
   line_size = hdisplay * pixel_size;
 #line 3723
   __cil_tmp32 = clock * pixel_size;
 #line 3723
   __cil_tmp33 = __cil_tmp32 / 1000;
 #line 3723
   __cil_tmp34 = __cil_tmp33 * latency_ns___0;
 #line 3723
   small = __cil_tmp34 / 1000;
 #line 3724
   large = line_count * line_size;
 #line 3726
   _min1 = small;
 #line 3726
   _min2 = large;
   }
 #line 3726
   if (_min1 < _min2) {
 #line 3726
     tmp___0 = _min1;
   } else {
 #line 3726
     tmp___0 = _min2;
   }
   {
 #line 3726
   __cil_tmp35 = display->cacheline_size;
 #line 3726
   __cil_tmp36 = (unsigned long )__cil_tmp35;
 #line 3726
   __cil_tmp37 = display->cacheline_size;
 #line 3726
   __cil_tmp38 = (unsigned long )__cil_tmp37;
 #line 3726
   __cil_tmp39 = (unsigned long )tmp___0;
 #line 3726
   __cil_tmp40 = __cil_tmp39 + __cil_tmp38;
 #line 3726
   __cil_tmp41 = __cil_tmp40 - 1UL;
 #line 3726
   __cil_tmp42 = __cil_tmp41 / __cil_tmp36;
 #line 3726
   entries = (int )__cil_tmp42;
 #line 3727
   __cil_tmp43 = (unsigned int )entries;
 #line 3727
   __cil_tmp44 = display->guard_size;
 #line 3727
   __cil_tmp45 = (unsigned int )__cil_tmp44;
 #line 3727
   __cil_tmp46 = __cil_tmp45 + __cil_tmp43;
 #line 3727
   *display_wm = (int )__cil_tmp46;
 #line 3730
   __cil_tmp47 = line_count * pixel_size;
 #line 3730
   entries = __cil_tmp47 * 64;
 #line 3731
   __cil_tmp48 = cursor->cacheline_size;
 #line 3731
   __cil_tmp49 = (unsigned long )__cil_tmp48;
 #line 3731
   __cil_tmp50 = cursor->cacheline_size;
 #line 3731
   __cil_tmp51 = (unsigned long )__cil_tmp50;
 #line 3731
   __cil_tmp52 = (unsigned long )entries;
 #line 3731
   __cil_tmp53 = __cil_tmp52 + __cil_tmp51;
 #line 3731
   __cil_tmp54 = __cil_tmp53 - 1UL;
 #line 3731
   __cil_tmp55 = __cil_tmp54 / __cil_tmp49;
 #line 3731
   entries = (int )__cil_tmp55;
 #line 3732
   __cil_tmp56 = (unsigned int )entries;
 #line 3732
   __cil_tmp57 = cursor->guard_size;
 #line 3732
   __cil_tmp58 = (unsigned int )__cil_tmp57;
 #line 3732
   __cil_tmp59 = __cil_tmp58 + __cil_tmp56;
 #line 3732
   *cursor_wm = (int )__cil_tmp59;
 #line 3734
   __cil_tmp60 = *display_wm;
 #line 3734
   __cil_tmp61 = *cursor_wm;
 #line 3734
   tmp___1 = g4x_check_srwm(dev, __cil_tmp60, __cil_tmp61, display, cursor);
   }
 #line 3734
   return (tmp___1);
 }
 }
 #line 3741 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void g4x_update_wm(struct drm_device *dev ) 
 { int sr_latency_ns ;
   struct drm_i915_private *dev_priv ;
   int planea_wm ;
   int planeb_wm ;
   int cursora_wm ;
   int cursorb_wm ;
   int plane_sr ;
   int cursor_sr ;
   unsigned int enabled ;
   bool tmp ;
   bool tmp___0 ;
   u32 tmp___1 ;
   bool tmp___2 ;
   int tmp___3 ;
   bool tmp___4 ;
   u32 tmp___5 ;
   u32 tmp___6 ;
   void *__cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   int __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   int __cil_tmp25 ;
   int __cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   int __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   int __cil_tmp34 ;
   u32 __cil_tmp35 ;
   int __cil_tmp36 ;
   u32 __cil_tmp37 ;
   unsigned int __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   int __cil_tmp40 ;
   u32 __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
 
   {
   {
 #line 3743
   sr_latency_ns = 12000;
 #line 3744
   __cil_tmp19 = dev->dev_private;
 #line 3744
   dev_priv = (struct drm_i915_private *)__cil_tmp19;
 #line 3747
   enabled = 0U;
 #line 3749
   __cil_tmp20 = (int )latency_ns;
 #line 3749
   __cil_tmp21 = (int )latency_ns;
 #line 3749
   tmp = g4x_compute_wm0(dev, 0, & g4x_wm_info, __cil_tmp20, & g4x_cursor_wm_info,
                         __cil_tmp21, & planea_wm, & cursora_wm);
   }
 #line 3749
   if ((int )tmp) {
 #line 3753
     enabled = enabled | 1U;
   } else {
 
   }
   {
 #line 3755
   __cil_tmp22 = (int )latency_ns;
 #line 3755
   __cil_tmp23 = (int )latency_ns;
 #line 3755
   tmp___0 = g4x_compute_wm0(dev, 1, & g4x_wm_info, __cil_tmp22, & g4x_cursor_wm_info,
                             __cil_tmp23, & planeb_wm, & cursorb_wm);
   }
 #line 3755
   if ((int )tmp___0) {
 #line 3759
     enabled = enabled | 2U;
   } else {
 
   }
   {
 #line 3761
   cursor_sr = 0;
 #line 3761
   plane_sr = cursor_sr;
 #line 3762
   __cil_tmp24 = (unsigned long )enabled;
 #line 3762
   tmp___2 = is_power_of_2(__cil_tmp24);
   }
 #line 3762
   if ((int )tmp___2) {
     {
 #line 3762
     __cil_tmp25 = (int )enabled;
 #line 3762
     tmp___3 = ffs(__cil_tmp25);
 #line 3762
     __cil_tmp26 = tmp___3 + -1;
 #line 3762
     tmp___4 = g4x_compute_srwm(dev, __cil_tmp26, sr_latency_ns, & g4x_wm_info, & g4x_cursor_wm_info,
                                & plane_sr, & cursor_sr);
     }
 #line 3762
     if ((int )tmp___4) {
       {
 #line 3768
       i915_write32___4(dev_priv, 8416U, 32768U);
       }
     } else {
       {
 #line 3770
       tmp___1 = i915_read32___6(dev_priv, 8416U);
 #line 3770
       __cil_tmp27 = tmp___1 & 4294934527U;
 #line 3770
       i915_write32___4(dev_priv, 8416U, __cil_tmp27);
       }
     }
   } else {
     {
 #line 3770
     tmp___1 = i915_read32___6(dev_priv, 8416U);
 #line 3770
     __cil_tmp28 = tmp___1 & 4294934527U;
 #line 3770
     i915_write32___4(dev_priv, 8416U, __cil_tmp28);
     }
   }
   {
 #line 3773
   drm_ut_debug_printk(4U, "drm", "g4x_update_wm", "Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
                       planea_wm, cursora_wm, planeb_wm, cursorb_wm, plane_sr, cursor_sr);
 #line 3778
   __cil_tmp29 = planeb_wm << 8;
 #line 3778
   __cil_tmp30 = cursorb_wm << 16;
 #line 3778
   __cil_tmp31 = plane_sr << 23;
 #line 3778
   __cil_tmp32 = __cil_tmp31 | __cil_tmp30;
 #line 3778
   __cil_tmp33 = __cil_tmp32 | __cil_tmp29;
 #line 3778
   __cil_tmp34 = __cil_tmp33 | planea_wm;
 #line 3778
   __cil_tmp35 = (u32 )__cil_tmp34;
 #line 3778
   i915_write32___4(dev_priv, 458804U, __cil_tmp35);
 #line 3783
   tmp___5 = i915_read32___6(dev_priv, 458808U);
 #line 3783
   __cil_tmp36 = cursora_wm << 8;
 #line 3783
   __cil_tmp37 = (u32 )__cil_tmp36;
 #line 3783
   __cil_tmp38 = tmp___5 & 16128U;
 #line 3783
   __cil_tmp39 = __cil_tmp38 | __cil_tmp37;
 #line 3783
   i915_write32___4(dev_priv, 458808U, __cil_tmp39);
 #line 3787
   tmp___6 = i915_read32___6(dev_priv, 458812U);
 #line 3787
   __cil_tmp40 = cursor_sr << 24;
 #line 3787
   __cil_tmp41 = (u32 )__cil_tmp40;
 #line 3787
   __cil_tmp42 = tmp___6 & 2147483647U;
 #line 3787
   __cil_tmp43 = __cil_tmp42 | __cil_tmp41;
 #line 3787
   i915_write32___4(dev_priv, 458812U, __cil_tmp43);
   }
 #line 3788
   return;
 }
 }
 #line 3792 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i965_update_wm(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_crtc *crtc ;
   int srwm ;
   int cursor_sr ;
   int sr_latency_ns ;
   int clock ;
   int htotal ;
   int hdisplay ;
   int pixel_size ;
   unsigned long line_time_us ;
   int entries ;
   u32 tmp ;
   void *__cil_tmp14 ;
   struct drm_crtc *__cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
   struct drm_framebuffer *__cil_tmp18 ;
   int __cil_tmp19 ;
   int __cil_tmp20 ;
   int __cil_tmp21 ;
   unsigned long __cil_tmp22 ;
   unsigned int __cil_tmp23 ;
   unsigned long __cil_tmp24 ;
   unsigned int __cil_tmp25 ;
   unsigned long __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   unsigned long __cil_tmp28 ;
   unsigned long __cil_tmp29 ;
   unsigned int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   int __cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   unsigned int __cil_tmp35 ;
   unsigned long __cil_tmp36 ;
   unsigned long __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   unsigned long __cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   unsigned long __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   unsigned long __cil_tmp55 ;
   void *__cil_tmp56 ;
   struct drm_i915_private *__cil_tmp57 ;
   struct intel_device_info  const  *__cil_tmp58 ;
   unsigned char *__cil_tmp59 ;
   unsigned char *__cil_tmp60 ;
   unsigned char __cil_tmp61 ;
   unsigned int __cil_tmp62 ;
   void *__cil_tmp63 ;
   struct drm_i915_private *__cil_tmp64 ;
   struct intel_device_info  const  *__cil_tmp65 ;
   unsigned char *__cil_tmp66 ;
   unsigned char *__cil_tmp67 ;
   unsigned char __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   unsigned int __cil_tmp70 ;
   int __cil_tmp71 ;
   int __cil_tmp72 ;
   u32 __cil_tmp73 ;
   int __cil_tmp74 ;
   u32 __cil_tmp75 ;
 
   {
   {
 #line 3794
   __cil_tmp14 = dev->dev_private;
 #line 3794
   dev_priv = (struct drm_i915_private *)__cil_tmp14;
 #line 3796
   srwm = 1;
 #line 3797
   cursor_sr = 16;
 #line 3800
   crtc = single_enabled_crtc(dev);
   }
   {
 #line 3801
   __cil_tmp15 = (struct drm_crtc *)0;
 #line 3801
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 3801
   __cil_tmp17 = (unsigned long )crtc;
 #line 3801
   if (__cil_tmp17 != __cil_tmp16) {
 #line 3803
     sr_latency_ns = 12000;
 #line 3804
     clock = crtc->mode.clock;
 #line 3805
     htotal = crtc->mode.htotal;
 #line 3806
     hdisplay = crtc->mode.hdisplay;
 #line 3807
     __cil_tmp18 = crtc->fb;
 #line 3807
     __cil_tmp19 = __cil_tmp18->bits_per_pixel;
 #line 3807
     pixel_size = __cil_tmp19 / 8;
 #line 3811
     __cil_tmp20 = htotal * 1000;
 #line 3811
     __cil_tmp21 = __cil_tmp20 / clock;
 #line 3811
     line_time_us = (unsigned long )__cil_tmp21;
 #line 3814
     __cil_tmp22 = (unsigned long )hdisplay;
 #line 3814
     __cil_tmp23 = (unsigned int )__cil_tmp22;
 #line 3814
     __cil_tmp24 = (unsigned long )pixel_size;
 #line 3814
     __cil_tmp25 = (unsigned int )__cil_tmp24;
 #line 3814
     __cil_tmp26 = (unsigned long )sr_latency_ns;
 #line 3814
     __cil_tmp27 = __cil_tmp26 / line_time_us;
 #line 3814
     __cil_tmp28 = __cil_tmp27 + 1000UL;
 #line 3814
     __cil_tmp29 = __cil_tmp28 / 1000UL;
 #line 3814
     __cil_tmp30 = (unsigned int )__cil_tmp29;
 #line 3814
     __cil_tmp31 = __cil_tmp30 * __cil_tmp25;
 #line 3814
     __cil_tmp32 = __cil_tmp31 * __cil_tmp23;
 #line 3814
     entries = (int )__cil_tmp32;
 #line 3816
     __cil_tmp33 = entries + 63;
 #line 3816
     entries = __cil_tmp33 / 64;
 #line 3817
     srwm = 512 - entries;
 #line 3818
     if (srwm < 0) {
 #line 3819
       srwm = 1;
     } else {
 
     }
     {
 #line 3820
     srwm = srwm & 511;
 #line 3821
     drm_ut_debug_printk(4U, "drm", "i965_update_wm", "self-refresh entries: %d, wm: %d\n",
                         entries, srwm);
 #line 3824
     __cil_tmp34 = (unsigned long )pixel_size;
 #line 3824
     __cil_tmp35 = (unsigned int )__cil_tmp34;
 #line 3824
     __cil_tmp36 = (unsigned long )sr_latency_ns;
 #line 3824
     __cil_tmp37 = __cil_tmp36 / line_time_us;
 #line 3824
     __cil_tmp38 = __cil_tmp37 + 1000UL;
 #line 3824
     __cil_tmp39 = __cil_tmp38 / 1000UL;
 #line 3824
     __cil_tmp40 = (unsigned int )__cil_tmp39;
 #line 3824
     __cil_tmp41 = __cil_tmp40 * __cil_tmp35;
 #line 3824
     __cil_tmp42 = __cil_tmp41 * 64U;
 #line 3824
     entries = (int )__cil_tmp42;
 #line 3826
     __cil_tmp43 = (unsigned long )i965_cursor_wm_info.cacheline_size;
 #line 3826
     __cil_tmp44 = (unsigned long )i965_cursor_wm_info.cacheline_size;
 #line 3826
     __cil_tmp45 = (unsigned long )entries;
 #line 3826
     __cil_tmp46 = __cil_tmp45 + __cil_tmp44;
 #line 3826
     __cil_tmp47 = __cil_tmp46 - 1UL;
 #line 3826
     __cil_tmp48 = __cil_tmp47 / __cil_tmp43;
 #line 3826
     entries = (int )__cil_tmp48;
 #line 3828
     __cil_tmp49 = (unsigned int )entries;
 #line 3828
     __cil_tmp50 = (unsigned int )i965_cursor_wm_info.guard_size;
 #line 3828
     __cil_tmp51 = __cil_tmp50 + __cil_tmp49;
 #line 3828
     __cil_tmp52 = (unsigned int )i965_cursor_wm_info.fifo_size;
 #line 3828
     __cil_tmp53 = __cil_tmp52 - __cil_tmp51;
 #line 3828
     cursor_sr = (int )__cil_tmp53;
     }
     {
 #line 3831
     __cil_tmp54 = (unsigned long )i965_cursor_wm_info.max_wm;
 #line 3831
     __cil_tmp55 = (unsigned long )cursor_sr;
 #line 3831
     if (__cil_tmp55 > __cil_tmp54) {
 #line 3832
       cursor_sr = (int )i965_cursor_wm_info.max_wm;
     } else {
 
     }
     }
     {
 #line 3834
     drm_ut_debug_printk(4U, "drm", "i965_update_wm", "self-refresh watermark: display plane %d cursor %d\n",
                         srwm, cursor_sr);
     }
     {
 #line 3837
     __cil_tmp56 = dev->dev_private;
 #line 3837
     __cil_tmp57 = (struct drm_i915_private *)__cil_tmp56;
 #line 3837
     __cil_tmp58 = __cil_tmp57->info;
 #line 3837
     __cil_tmp59 = (unsigned char *)__cil_tmp58;
 #line 3837
     __cil_tmp60 = __cil_tmp59 + 2UL;
 #line 3837
     __cil_tmp61 = *__cil_tmp60;
 #line 3837
     __cil_tmp62 = (unsigned int )__cil_tmp61;
 #line 3837
     if (__cil_tmp62 != 0U) {
       {
 #line 3838
       i915_write32___4(dev_priv, 8416U, 32768U);
       }
     } else {
 
     }
     }
   } else {
     {
 #line 3841
     __cil_tmp63 = dev->dev_private;
 #line 3841
     __cil_tmp64 = (struct drm_i915_private *)__cil_tmp63;
 #line 3841
     __cil_tmp65 = __cil_tmp64->info;
 #line 3841
     __cil_tmp66 = (unsigned char *)__cil_tmp65;
 #line 3841
     __cil_tmp67 = __cil_tmp66 + 2UL;
 #line 3841
     __cil_tmp68 = *__cil_tmp67;
 #line 3841
     __cil_tmp69 = (unsigned int )__cil_tmp68;
 #line 3841
     if (__cil_tmp69 != 0U) {
       {
 #line 3842
       tmp = i915_read32___6(dev_priv, 8416U);
 #line 3842
       __cil_tmp70 = tmp & 4294934527U;
 #line 3842
       i915_write32___4(dev_priv, 8416U, __cil_tmp70);
       }
     } else {
 
     }
     }
   }
   }
   {
 #line 3846
   drm_ut_debug_printk(4U, "drm", "i965_update_wm", "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
                       srwm);
 #line 3850
   __cil_tmp71 = srwm << 23;
 #line 3850
   __cil_tmp72 = __cil_tmp71 | 526344;
 #line 3850
   __cil_tmp73 = (u32 )__cil_tmp72;
 #line 3850
   i915_write32___4(dev_priv, 458804U, __cil_tmp73);
 #line 3852
   i915_write32___4(dev_priv, 458808U, 2056U);
 #line 3854
   __cil_tmp74 = cursor_sr << 24;
 #line 3854
   __cil_tmp75 = (u32 )__cil_tmp74;
 #line 3854
   i915_write32___4(dev_priv, 458812U, __cil_tmp75);
   }
 #line 3855
   return;
 }
 }
 #line 3857 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i9xx_update_wm(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct intel_watermark_params  const  *wm_info ;
   uint32_t fwater_lo ;
   uint32_t fwater_hi ;
   int cwm ;
   int srwm ;
   int fifo_size ;
   int planea_wm ;
   int planeb_wm ;
   struct drm_crtc *crtc ;
   struct drm_crtc *enabled ;
   unsigned long tmp ;
   unsigned long tmp___0 ;
   u32 tmp___1 ;
   int sr_latency_ns ;
   int clock ;
   int htotal ;
   int hdisplay ;
   int pixel_size ;
   unsigned long line_time_us ;
   int entries ;
   u32 tmp___2 ;
   void *__cil_tmp24 ;
   void *__cil_tmp25 ;
   struct drm_i915_private *__cil_tmp26 ;
   struct intel_device_info  const  *__cil_tmp27 ;
   unsigned char *__cil_tmp28 ;
   unsigned char *__cil_tmp29 ;
   unsigned char __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   void *__cil_tmp32 ;
   struct drm_i915_private *__cil_tmp33 ;
   struct intel_device_info  const  *__cil_tmp34 ;
   u8 __cil_tmp35 ;
   unsigned char __cil_tmp36 ;
   unsigned int __cil_tmp37 ;
   int (*__cil_tmp38)(struct drm_device * , int  ) ;
   bool __cil_tmp39 ;
   struct drm_framebuffer *__cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   struct drm_framebuffer *__cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   int __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   struct drm_framebuffer *__cil_tmp46 ;
   int __cil_tmp47 ;
   int __cil_tmp48 ;
   unsigned long __cil_tmp49 ;
   unsigned long __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   unsigned long __cil_tmp54 ;
   unsigned int __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   int (*__cil_tmp58)(struct drm_device * , int  ) ;
   bool __cil_tmp59 ;
   struct drm_framebuffer *__cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   struct drm_framebuffer *__cil_tmp62 ;
   unsigned long __cil_tmp63 ;
   int __cil_tmp64 ;
   unsigned long __cil_tmp65 ;
   struct drm_framebuffer *__cil_tmp66 ;
   int __cil_tmp67 ;
   int __cil_tmp68 ;
   unsigned long __cil_tmp69 ;
   struct drm_crtc *__cil_tmp70 ;
   unsigned long __cil_tmp71 ;
   unsigned long __cil_tmp72 ;
   unsigned long __cil_tmp73 ;
   unsigned int __cil_tmp74 ;
   unsigned int __cil_tmp75 ;
   unsigned int __cil_tmp76 ;
   unsigned long __cil_tmp77 ;
   unsigned int __cil_tmp78 ;
   unsigned int __cil_tmp79 ;
   unsigned int __cil_tmp80 ;
   int __cil_tmp81 ;
   void *__cil_tmp82 ;
   struct drm_i915_private *__cil_tmp83 ;
   struct intel_device_info  const  *__cil_tmp84 ;
   unsigned char *__cil_tmp85 ;
   unsigned char *__cil_tmp86 ;
   unsigned char __cil_tmp87 ;
   unsigned int __cil_tmp88 ;
   int __cil_tmp89 ;
   unsigned int __cil_tmp90 ;
   void *__cil_tmp91 ;
   struct drm_i915_private *__cil_tmp92 ;
   struct intel_device_info  const  *__cil_tmp93 ;
   u8 __cil_tmp94 ;
   unsigned char __cil_tmp95 ;
   unsigned int __cil_tmp96 ;
   struct drm_crtc *__cil_tmp97 ;
   unsigned long __cil_tmp98 ;
   unsigned long __cil_tmp99 ;
   struct drm_framebuffer *__cil_tmp100 ;
   int __cil_tmp101 ;
   int __cil_tmp102 ;
   int __cil_tmp103 ;
   unsigned long __cil_tmp104 ;
   unsigned int __cil_tmp105 ;
   unsigned long __cil_tmp106 ;
   unsigned int __cil_tmp107 ;
   unsigned long __cil_tmp108 ;
   unsigned long __cil_tmp109 ;
   unsigned long __cil_tmp110 ;
   unsigned long __cil_tmp111 ;
   unsigned int __cil_tmp112 ;
   unsigned int __cil_tmp113 ;
   unsigned int __cil_tmp114 ;
   unsigned long __cil_tmp115 ;
   unsigned long __cil_tmp116 ;
   unsigned long __cil_tmp117 ;
   unsigned long __cil_tmp118 ;
   unsigned long __cil_tmp119 ;
   unsigned long __cil_tmp120 ;
   unsigned long __cil_tmp121 ;
   unsigned long __cil_tmp122 ;
   unsigned int __cil_tmp123 ;
   unsigned long __cil_tmp124 ;
   unsigned int __cil_tmp125 ;
   unsigned int __cil_tmp126 ;
   int __cil_tmp127 ;
   int __cil_tmp128 ;
   int __cil_tmp129 ;
   u32 __cil_tmp130 ;
   void *__cil_tmp131 ;
   struct drm_i915_private *__cil_tmp132 ;
   struct intel_device_info  const  *__cil_tmp133 ;
   unsigned char *__cil_tmp134 ;
   unsigned char *__cil_tmp135 ;
   unsigned char __cil_tmp136 ;
   unsigned int __cil_tmp137 ;
   int __cil_tmp138 ;
   int __cil_tmp139 ;
   u32 __cil_tmp140 ;
   int __cil_tmp141 ;
   u32 __cil_tmp142 ;
   unsigned int __cil_tmp143 ;
   int __cil_tmp144 ;
   int __cil_tmp145 ;
   int __cil_tmp146 ;
   int __cil_tmp147 ;
   uint32_t __cil_tmp148 ;
   void *__cil_tmp149 ;
   struct drm_i915_private *__cil_tmp150 ;
   struct intel_device_info  const  *__cil_tmp151 ;
   u8 __cil_tmp152 ;
   unsigned char __cil_tmp153 ;
   unsigned int __cil_tmp154 ;
   struct drm_crtc *__cil_tmp155 ;
   unsigned long __cil_tmp156 ;
   unsigned long __cil_tmp157 ;
   int __cil_tmp158 ;
   void *__cil_tmp159 ;
   struct drm_i915_private *__cil_tmp160 ;
   struct intel_device_info  const  *__cil_tmp161 ;
   unsigned char *__cil_tmp162 ;
   unsigned char *__cil_tmp163 ;
   unsigned char __cil_tmp164 ;
   unsigned int __cil_tmp165 ;
   int __cil_tmp166 ;
   unsigned int __cil_tmp167 ;
 
   {
 #line 3859
   __cil_tmp24 = dev->dev_private;
 #line 3859
   dev_priv = (struct drm_i915_private *)__cil_tmp24;
 #line 3863
   srwm = 1;
 #line 3866
   enabled = (struct drm_crtc *)0;
   {
 #line 3868
   __cil_tmp25 = dev->dev_private;
 #line 3868
   __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
 #line 3868
   __cil_tmp27 = __cil_tmp26->info;
 #line 3868
   __cil_tmp28 = (unsigned char *)__cil_tmp27;
 #line 3868
   __cil_tmp29 = __cil_tmp28 + 1UL;
 #line 3868
   __cil_tmp30 = *__cil_tmp29;
 #line 3868
   __cil_tmp31 = (unsigned int )__cil_tmp30;
 #line 3868
   if (__cil_tmp31 != 0U) {
 #line 3869
     wm_info = & i945_wm_info;
   } else {
     {
 #line 3870
     __cil_tmp32 = dev->dev_private;
 #line 3870
     __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
 #line 3870
     __cil_tmp34 = __cil_tmp33->info;
 #line 3870
     __cil_tmp35 = __cil_tmp34->gen;
 #line 3870
     __cil_tmp36 = (unsigned char )__cil_tmp35;
 #line 3870
     __cil_tmp37 = (unsigned int )__cil_tmp36;
 #line 3870
     if (__cil_tmp37 != 2U) {
 #line 3871
       wm_info = & i915_wm_info;
     } else {
 #line 3873
       wm_info = & i855_wm_info;
     }
     }
   }
   }
   {
 #line 3875
   __cil_tmp38 = dev_priv->display.get_fifo_size;
 #line 3875
   fifo_size = (*__cil_tmp38)(dev, 0);
 #line 3876
   crtc = intel_get_crtc_for_plane(dev, 0);
   }
   {
 #line 3877
   __cil_tmp39 = crtc->enabled;
 #line 3877
   if ((int )__cil_tmp39) {
     {
 #line 3877
     __cil_tmp40 = (struct drm_framebuffer *)0;
 #line 3877
     __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 3877
     __cil_tmp42 = crtc->fb;
 #line 3877
     __cil_tmp43 = (unsigned long )__cil_tmp42;
 #line 3877
     if (__cil_tmp43 != __cil_tmp41) {
       {
 #line 3878
       __cil_tmp44 = crtc->mode.clock;
 #line 3878
       __cil_tmp45 = (unsigned long )__cil_tmp44;
 #line 3878
       __cil_tmp46 = crtc->fb;
 #line 3878
       __cil_tmp47 = __cil_tmp46->bits_per_pixel;
 #line 3878
       __cil_tmp48 = __cil_tmp47 / 8;
 #line 3878
       __cil_tmp49 = (unsigned long )latency_ns;
 #line 3878
       tmp = intel_calculate_wm(__cil_tmp45, wm_info, fifo_size, __cil_tmp48, __cil_tmp49);
 #line 3878
       planea_wm = (int )tmp;
 #line 3882
       enabled = crtc;
       }
     } else {
 #line 3884
       __cil_tmp50 = wm_info->guard_size;
 #line 3884
       __cil_tmp51 = (unsigned int )__cil_tmp50;
 #line 3884
       __cil_tmp52 = (unsigned int )fifo_size;
 #line 3884
       __cil_tmp53 = __cil_tmp52 - __cil_tmp51;
 #line 3884
       planea_wm = (int )__cil_tmp53;
     }
     }
   } else {
 #line 3884
     __cil_tmp54 = wm_info->guard_size;
 #line 3884
     __cil_tmp55 = (unsigned int )__cil_tmp54;
 #line 3884
     __cil_tmp56 = (unsigned int )fifo_size;
 #line 3884
     __cil_tmp57 = __cil_tmp56 - __cil_tmp55;
 #line 3884
     planea_wm = (int )__cil_tmp57;
   }
   }
   {
 #line 3886
   __cil_tmp58 = dev_priv->display.get_fifo_size;
 #line 3886
   fifo_size = (*__cil_tmp58)(dev, 1);
 #line 3887
   crtc = intel_get_crtc_for_plane(dev, 1);
   }
   {
 #line 3888
   __cil_tmp59 = crtc->enabled;
 #line 3888
   if ((int )__cil_tmp59) {
     {
 #line 3888
     __cil_tmp60 = (struct drm_framebuffer *)0;
 #line 3888
     __cil_tmp61 = (unsigned long )__cil_tmp60;
 #line 3888
     __cil_tmp62 = crtc->fb;
 #line 3888
     __cil_tmp63 = (unsigned long )__cil_tmp62;
 #line 3888
     if (__cil_tmp63 != __cil_tmp61) {
       {
 #line 3889
       __cil_tmp64 = crtc->mode.clock;
 #line 3889
       __cil_tmp65 = (unsigned long )__cil_tmp64;
 #line 3889
       __cil_tmp66 = crtc->fb;
 #line 3889
       __cil_tmp67 = __cil_tmp66->bits_per_pixel;
 #line 3889
       __cil_tmp68 = __cil_tmp67 / 8;
 #line 3889
       __cil_tmp69 = (unsigned long )latency_ns;
 #line 3889
       tmp___0 = intel_calculate_wm(__cil_tmp65, wm_info, fifo_size, __cil_tmp68, __cil_tmp69);
 #line 3889
       planeb_wm = (int )tmp___0;
       }
       {
 #line 3893
       __cil_tmp70 = (struct drm_crtc *)0;
 #line 3893
       __cil_tmp71 = (unsigned long )__cil_tmp70;
 #line 3893
       __cil_tmp72 = (unsigned long )enabled;
 #line 3893
       if (__cil_tmp72 == __cil_tmp71) {
 #line 3894
         enabled = crtc;
       } else {
 #line 3896
         enabled = (struct drm_crtc *)0;
       }
       }
     } else {
 #line 3898
       __cil_tmp73 = wm_info->guard_size;
 #line 3898
       __cil_tmp74 = (unsigned int )__cil_tmp73;
 #line 3898
       __cil_tmp75 = (unsigned int )fifo_size;
 #line 3898
       __cil_tmp76 = __cil_tmp75 - __cil_tmp74;
 #line 3898
       planeb_wm = (int )__cil_tmp76;
     }
     }
   } else {
 #line 3898
     __cil_tmp77 = wm_info->guard_size;
 #line 3898
     __cil_tmp78 = (unsigned int )__cil_tmp77;
 #line 3898
     __cil_tmp79 = (unsigned int )fifo_size;
 #line 3898
     __cil_tmp80 = __cil_tmp79 - __cil_tmp78;
 #line 3898
     planeb_wm = (int )__cil_tmp80;
   }
   }
   {
 #line 3900
   drm_ut_debug_printk(4U, "drm", "i9xx_update_wm", "FIFO watermarks - A: %d, B: %d\n",
                       planea_wm, planeb_wm);
 #line 3905
   cwm = 2;
   }
   {
 #line 3908
   __cil_tmp81 = dev->pci_device;
 #line 3908
   if (__cil_tmp81 == 10098) {
     {
 #line 3909
     i915_write32___4(dev_priv, 8416U, 2147483648U);
     }
   } else {
     {
 #line 3908
     __cil_tmp82 = dev->dev_private;
 #line 3908
     __cil_tmp83 = (struct drm_i915_private *)__cil_tmp82;
 #line 3908
     __cil_tmp84 = __cil_tmp83->info;
 #line 3908
     __cil_tmp85 = (unsigned char *)__cil_tmp84;
 #line 3908
     __cil_tmp86 = __cil_tmp85 + 1UL;
 #line 3908
     __cil_tmp87 = *__cil_tmp86;
 #line 3908
     __cil_tmp88 = (unsigned int )__cil_tmp87;
 #line 3908
     if (__cil_tmp88 != 0U) {
       {
 #line 3909
       i915_write32___4(dev_priv, 8416U, 2147483648U);
       }
     } else {
       {
 #line 3910
       __cil_tmp89 = dev->pci_device;
 #line 3910
       if (__cil_tmp89 == 9618) {
         {
 #line 3911
         tmp___1 = i915_read32___6(dev_priv, 8384U);
 #line 3911
         __cil_tmp90 = tmp___1 & 4294963199U;
 #line 3911
         i915_write32___4(dev_priv, 8384U, __cil_tmp90);
         }
       } else {
 
       }
       }
     }
     }
   }
   }
   {
 #line 3914
   __cil_tmp91 = dev->dev_private;
 #line 3914
   __cil_tmp92 = (struct drm_i915_private *)__cil_tmp91;
 #line 3914
   __cil_tmp93 = __cil_tmp92->info;
 #line 3914
   __cil_tmp94 = __cil_tmp93->gen;
 #line 3914
   __cil_tmp95 = (unsigned char )__cil_tmp94;
 #line 3914
   __cil_tmp96 = (unsigned int )__cil_tmp95;
 #line 3914
   if (__cil_tmp96 > 2U) {
     {
 #line 3914
     __cil_tmp97 = (struct drm_crtc *)0;
 #line 3914
     __cil_tmp98 = (unsigned long )__cil_tmp97;
 #line 3914
     __cil_tmp99 = (unsigned long )enabled;
 #line 3914
     if (__cil_tmp99 != __cil_tmp98) {
       {
 #line 3916
       sr_latency_ns = 6000;
 #line 3917
       clock = enabled->mode.clock;
 #line 3918
       htotal = enabled->mode.htotal;
 #line 3919
       hdisplay = enabled->mode.hdisplay;
 #line 3920
       __cil_tmp100 = enabled->fb;
 #line 3920
       __cil_tmp101 = __cil_tmp100->bits_per_pixel;
 #line 3920
       pixel_size = __cil_tmp101 / 8;
 #line 3924
       __cil_tmp102 = htotal * 1000;
 #line 3924
       __cil_tmp103 = __cil_tmp102 / clock;
 #line 3924
       line_time_us = (unsigned long )__cil_tmp103;
 #line 3927
       __cil_tmp104 = (unsigned long )hdisplay;
 #line 3927
       __cil_tmp105 = (unsigned int )__cil_tmp104;
 #line 3927
       __cil_tmp106 = (unsigned long )pixel_size;
 #line 3927
       __cil_tmp107 = (unsigned int )__cil_tmp106;
 #line 3927
       __cil_tmp108 = (unsigned long )sr_latency_ns;
 #line 3927
       __cil_tmp109 = __cil_tmp108 / line_time_us;
 #line 3927
       __cil_tmp110 = __cil_tmp109 + 1000UL;
 #line 3927
       __cil_tmp111 = __cil_tmp110 / 1000UL;
 #line 3927
       __cil_tmp112 = (unsigned int )__cil_tmp111;
 #line 3927
       __cil_tmp113 = __cil_tmp112 * __cil_tmp107;
 #line 3927
       __cil_tmp114 = __cil_tmp113 * __cil_tmp105;
 #line 3927
       entries = (int )__cil_tmp114;
 #line 3929
       __cil_tmp115 = wm_info->cacheline_size;
 #line 3929
       __cil_tmp116 = (unsigned long )__cil_tmp115;
 #line 3929
       __cil_tmp117 = wm_info->cacheline_size;
 #line 3929
       __cil_tmp118 = (unsigned long )__cil_tmp117;
 #line 3929
       __cil_tmp119 = (unsigned long )entries;
 #line 3929
       __cil_tmp120 = __cil_tmp119 + __cil_tmp118;
 #line 3929
       __cil_tmp121 = __cil_tmp120 - 1UL;
 #line 3929
       __cil_tmp122 = __cil_tmp121 / __cil_tmp116;
 #line 3929
       entries = (int )__cil_tmp122;
 #line 3930
       drm_ut_debug_printk(4U, "drm", "i9xx_update_wm", "self-refresh entries: %d\n",
                           entries);
 #line 3931
       __cil_tmp123 = (unsigned int )entries;
 #line 3931
       __cil_tmp124 = wm_info->fifo_size;
 #line 3931
       __cil_tmp125 = (unsigned int )__cil_tmp124;
 #line 3931
       __cil_tmp126 = __cil_tmp125 - __cil_tmp123;
 #line 3931
       srwm = (int )__cil_tmp126;
       }
 #line 3932
       if (srwm < 0) {
 #line 3933
         srwm = 1;
       } else {
 
       }
       {
 #line 3935
       __cil_tmp127 = dev->pci_device;
 #line 3935
       if (__cil_tmp127 == 10098) {
         {
 #line 3936
         __cil_tmp128 = srwm & 255;
 #line 3936
         __cil_tmp129 = __cil_tmp128 | 65536;
 #line 3936
         __cil_tmp130 = (u32 )__cil_tmp129;
 #line 3936
         i915_write32___4(dev_priv, 8416U, __cil_tmp130);
         }
       } else {
         {
 #line 3935
         __cil_tmp131 = dev->dev_private;
 #line 3935
         __cil_tmp132 = (struct drm_i915_private *)__cil_tmp131;
 #line 3935
         __cil_tmp133 = __cil_tmp132->info;
 #line 3935
         __cil_tmp134 = (unsigned char *)__cil_tmp133;
 #line 3935
         __cil_tmp135 = __cil_tmp134 + 1UL;
 #line 3935
         __cil_tmp136 = *__cil_tmp135;
 #line 3935
         __cil_tmp137 = (unsigned int )__cil_tmp136;
 #line 3935
         if (__cil_tmp137 != 0U) {
           {
 #line 3936
           __cil_tmp138 = srwm & 255;
 #line 3936
           __cil_tmp139 = __cil_tmp138 | 65536;
 #line 3936
           __cil_tmp140 = (u32 )__cil_tmp139;
 #line 3936
           i915_write32___4(dev_priv, 8416U, __cil_tmp140);
           }
         } else {
           {
 #line 3938
           __cil_tmp141 = dev->pci_device;
 #line 3938
           if (__cil_tmp141 == 9618) {
             {
 #line 3939
             __cil_tmp142 = (u32 )srwm;
 #line 3939
             __cil_tmp143 = __cil_tmp142 & 63U;
 #line 3939
             i915_write32___4(dev_priv, 8416U, __cil_tmp143);
             }
           } else {
 
           }
           }
         }
         }
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
   }
   {
 #line 3942
   drm_ut_debug_printk(4U, "drm", "i9xx_update_wm", "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
                       planea_wm, planeb_wm, cwm, srwm);
 #line 3945
   __cil_tmp144 = planea_wm & 63;
 #line 3945
   __cil_tmp145 = planeb_wm & 63;
 #line 3945
   __cil_tmp146 = __cil_tmp145 << 16;
 #line 3945
   __cil_tmp147 = __cil_tmp146 | __cil_tmp144;
 #line 3945
   fwater_lo = (uint32_t )__cil_tmp147;
 #line 3946
   __cil_tmp148 = (uint32_t )cwm;
 #line 3946
   fwater_hi = __cil_tmp148 & 31U;
 #line 3949
   fwater_lo = fwater_lo | 16777472U;
 #line 3950
   fwater_hi = fwater_hi | 256U;
 #line 3952
   i915_write32___4(dev_priv, 8408U, fwater_lo);
 #line 3953
   i915_write32___4(dev_priv, 8412U, fwater_hi);
   }
   {
 #line 3955
   __cil_tmp149 = dev->dev_private;
 #line 3955
   __cil_tmp150 = (struct drm_i915_private *)__cil_tmp149;
 #line 3955
   __cil_tmp151 = __cil_tmp150->info;
 #line 3955
   __cil_tmp152 = __cil_tmp151->gen;
 #line 3955
   __cil_tmp153 = (unsigned char )__cil_tmp152;
 #line 3955
   __cil_tmp154 = (unsigned int )__cil_tmp153;
 #line 3955
   if (__cil_tmp154 > 2U) {
     {
 #line 3956
     __cil_tmp155 = (struct drm_crtc *)0;
 #line 3956
     __cil_tmp156 = (unsigned long )__cil_tmp155;
 #line 3956
     __cil_tmp157 = (unsigned long )enabled;
 #line 3956
     if (__cil_tmp157 != __cil_tmp156) {
       {
 #line 3957
       __cil_tmp158 = dev->pci_device;
 #line 3957
       if (__cil_tmp158 == 10098) {
         {
 #line 3958
         i915_write32___4(dev_priv, 8416U, 2147516416U);
         }
       } else {
         {
 #line 3957
         __cil_tmp159 = dev->dev_private;
 #line 3957
         __cil_tmp160 = (struct drm_i915_private *)__cil_tmp159;
 #line 3957
         __cil_tmp161 = __cil_tmp160->info;
 #line 3957
         __cil_tmp162 = (unsigned char *)__cil_tmp161;
 #line 3957
         __cil_tmp163 = __cil_tmp162 + 1UL;
 #line 3957
         __cil_tmp164 = *__cil_tmp163;
 #line 3957
         __cil_tmp165 = (unsigned int )__cil_tmp164;
 #line 3957
         if (__cil_tmp165 != 0U) {
           {
 #line 3958
           i915_write32___4(dev_priv, 8416U, 2147516416U);
           }
         } else {
           {
 #line 3960
           __cil_tmp166 = dev->pci_device;
 #line 3960
           if (__cil_tmp166 == 9618) {
             {
 #line 3961
             tmp___2 = i915_read32___6(dev_priv, 8384U);
 #line 3961
             __cil_tmp167 = tmp___2 | 4096U;
 #line 3961
             i915_write32___4(dev_priv, 8384U, __cil_tmp167);
             }
           } else {
 
           }
           }
         }
         }
       }
       }
       {
 #line 3962
       drm_ut_debug_printk(4U, "drm", "i9xx_update_wm", "memory self refresh enabled\n");
       }
     } else {
       {
 #line 3964
       drm_ut_debug_printk(4U, "drm", "i9xx_update_wm", "memory self refresh disabled\n");
       }
     }
     }
   } else {
 
   }
   }
 #line 3965
   return;
 }
 }
 #line 3968 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void i830_update_wm(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   struct drm_crtc *crtc ;
   uint32_t fwater_lo ;
   int planea_wm ;
   int tmp ;
   unsigned long tmp___0 ;
   u32 tmp___1 ;
   void *__cil_tmp9 ;
   struct drm_crtc *__cil_tmp10 ;
   unsigned long __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   int (*__cil_tmp13)(struct drm_device * , int  ) ;
   int __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   struct drm_framebuffer *__cil_tmp16 ;
   int __cil_tmp17 ;
   int __cil_tmp18 ;
   unsigned long __cil_tmp19 ;
   uint32_t __cil_tmp20 ;
   unsigned int __cil_tmp21 ;
 
   {
   {
 #line 3970
   __cil_tmp9 = dev->dev_private;
 #line 3970
   dev_priv = (struct drm_i915_private *)__cil_tmp9;
 #line 3975
   crtc = single_enabled_crtc(dev);
   }
   {
 #line 3976
   __cil_tmp10 = (struct drm_crtc *)0;
 #line 3976
   __cil_tmp11 = (unsigned long )__cil_tmp10;
 #line 3976
   __cil_tmp12 = (unsigned long )crtc;
 #line 3976
   if (__cil_tmp12 == __cil_tmp11) {
 #line 3977
     return;
   } else {
 
   }
   }
   {
 #line 3979
   __cil_tmp13 = dev_priv->display.get_fifo_size;
 #line 3979
   tmp = (*__cil_tmp13)(dev, 0);
 #line 3979
   __cil_tmp14 = crtc->mode.clock;
 #line 3979
   __cil_tmp15 = (unsigned long )__cil_tmp14;
 #line 3979
   __cil_tmp16 = crtc->fb;
 #line 3979
   __cil_tmp17 = __cil_tmp16->bits_per_pixel;
 #line 3979
   __cil_tmp18 = __cil_tmp17 / 8;
 #line 3979
   __cil_tmp19 = (unsigned long )latency_ns;
 #line 3979
   tmp___0 = intel_calculate_wm(__cil_tmp15, & i830_wm_info, tmp, __cil_tmp18, __cil_tmp19);
 #line 3979
   planea_wm = (int )tmp___0;
 #line 3983
   tmp___1 = i915_read32___6(dev_priv, 8408U);
 #line 3983
   fwater_lo = tmp___1 & 4294963200U;
 #line 3984
   __cil_tmp20 = (uint32_t )planea_wm;
 #line 3984
   __cil_tmp21 = __cil_tmp20 | fwater_lo;
 #line 3984
   fwater_lo = __cil_tmp21 | 768U;
 #line 3986
   drm_ut_debug_printk(4U, "drm", "i830_update_wm", "Setting FIFO watermarks - A: %d\n",
                       planea_wm);
 #line 3988
   i915_write32___4(dev_priv, 8408U, fwater_lo);
   }
 #line 3989
   return;
 }
 }
 #line 4001 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool ironlake_check_srwm(struct drm_device *dev , int level , int fbc_wm ,
                                 int display_wm , int cursor_wm , struct intel_watermark_params  const  *display ,
                                 struct intel_watermark_params  const  *cursor ) 
 { struct drm_i915_private *dev_priv ;
   u32 tmp ;
   void *__cil_tmp10 ;
   unsigned int __cil_tmp11 ;
   unsigned long __cil_tmp12 ;
   unsigned long __cil_tmp13 ;
   unsigned long __cil_tmp14 ;
   unsigned long __cil_tmp15 ;
   unsigned long __cil_tmp16 ;
   unsigned long __cil_tmp17 ;
 
   {
   {
 #line 4006
   __cil_tmp10 = dev->dev_private;
 #line 4006
   dev_priv = (struct drm_i915_private *)__cil_tmp10;
 #line 4008
   drm_ut_debug_printk(4U, "drm", "ironlake_check_srwm", "watermark %d: display plane %d, fbc lines %d, cursor %d\n",
                       level, display_wm, fbc_wm, cursor_wm);
   }
 #line 4011
   if (fbc_wm > 15) {
     {
 #line 4012
     drm_ut_debug_printk(4U, "drm", "ironlake_check_srwm", "fbc watermark(%d) is too large(%d), disabling wm%d+\n",
                         fbc_wm, 15, level);
 #line 4016
     tmp = i915_read32___6(dev_priv, 282624U);
 #line 4016
     __cil_tmp11 = tmp | 32768U;
 #line 4016
     i915_write32___4(dev_priv, 282624U, __cil_tmp11);
     }
 #line 4018
     return ((bool )0);
   } else {
 
   }
   {
 #line 4021
   __cil_tmp12 = display->max_wm;
 #line 4021
   __cil_tmp13 = (unsigned long )__cil_tmp12;
 #line 4021
   __cil_tmp14 = (unsigned long )display_wm;
 #line 4021
   if (__cil_tmp14 > __cil_tmp13) {
     {
 #line 4022
     drm_ut_debug_printk(4U, "drm", "ironlake_check_srwm", "display watermark(%d) is too large(%d), disabling wm%d+\n",
                         display_wm, 511, level);
     }
 #line 4024
     return ((bool )0);
   } else {
 
   }
   }
   {
 #line 4027
   __cil_tmp15 = cursor->max_wm;
 #line 4027
   __cil_tmp16 = (unsigned long )__cil_tmp15;
 #line 4027
   __cil_tmp17 = (unsigned long )cursor_wm;
 #line 4027
   if (__cil_tmp17 > __cil_tmp16) {
     {
 #line 4028
     drm_ut_debug_printk(4U, "drm", "ironlake_check_srwm", "cursor watermark(%d) is too large(%d), disabling wm%d+\n",
                         cursor_wm, 63, level);
     }
 #line 4030
     return ((bool )0);
   } else {
 
   }
   }
 #line 4033
   if (fbc_wm == 0) {
 #line 4033
     if (display_wm == 0) {
 #line 4033
       if (cursor_wm == 0) {
         {
 #line 4034
         drm_ut_debug_printk(4U, "drm", "ironlake_check_srwm", "latency %d is 0, disabling wm%d+\n",
                             level, level);
         }
 #line 4035
         return ((bool )0);
       } else {
 
       }
     } else {
 
     }
   } else {
 
   }
 #line 4038
   return ((bool )1);
 }
 }
 #line 4044 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static bool ironlake_compute_srwm(struct drm_device *dev , int level , int plane ,
                                   int latency_ns___0 , struct intel_watermark_params  const  *display ,
                                   struct intel_watermark_params  const  *cursor ,
                                   int *fbc_wm , int *display_wm , int *cursor_wm ) 
 { struct drm_crtc *crtc ;
   unsigned long line_time_us ;
   int hdisplay ;
   int htotal ;
   int pixel_size ;
   int clock ;
   int line_count ;
   int line_size ;
   int small ;
   int large ;
   int entries ;
   int tmp ;
   int tmp___0 ;
   int _min1 ;
   int _min2 ;
   int tmp___1 ;
   bool tmp___2 ;
   struct drm_framebuffer *__cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   unsigned long __cil_tmp31 ;
   unsigned long __cil_tmp32 ;
   unsigned long __cil_tmp33 ;
   unsigned long __cil_tmp34 ;
   int __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   unsigned long __cil_tmp38 ;
   unsigned long __cil_tmp39 ;
   unsigned long __cil_tmp40 ;
   unsigned long __cil_tmp41 ;
   unsigned long __cil_tmp42 ;
   unsigned long __cil_tmp43 ;
   unsigned long __cil_tmp44 ;
   unsigned long __cil_tmp45 ;
   unsigned int __cil_tmp46 ;
   unsigned long __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   int __cil_tmp50 ;
   int __cil_tmp51 ;
   int __cil_tmp52 ;
   int __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   unsigned long __cil_tmp56 ;
   unsigned long __cil_tmp57 ;
   unsigned long __cil_tmp58 ;
   unsigned long __cil_tmp59 ;
   unsigned long __cil_tmp60 ;
   unsigned long __cil_tmp61 ;
   unsigned long __cil_tmp62 ;
   unsigned long __cil_tmp63 ;
   unsigned int __cil_tmp64 ;
   unsigned long __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   int __cil_tmp70 ;
 
   {
 #line 4057
   if (latency_ns___0 == 0) {
 #line 4058
     tmp___0 = 0;
 #line 4058
     *cursor_wm = tmp___0;
 #line 4058
     tmp = tmp___0;
 #line 4058
     *display_wm = tmp;
 #line 4058
     *fbc_wm = tmp;
 #line 4059
     return ((bool )0);
   } else {
 
   }
   {
 #line 4062
   crtc = intel_get_crtc_for_plane(dev, plane);
 #line 4063
   hdisplay = crtc->mode.hdisplay;
 #line 4064
   htotal = crtc->mode.htotal;
 #line 4065
   clock = crtc->mode.clock;
 #line 4066
   __cil_tmp27 = crtc->fb;
 #line 4066
   __cil_tmp28 = __cil_tmp27->bits_per_pixel;
 #line 4066
   pixel_size = __cil_tmp28 / 8;
 #line 4068
   __cil_tmp29 = htotal * 1000;
 #line 4068
   __cil_tmp30 = __cil_tmp29 / clock;
 #line 4068
   line_time_us = (unsigned long )__cil_tmp30;
 #line 4069
   __cil_tmp31 = (unsigned long )latency_ns___0;
 #line 4069
   __cil_tmp32 = __cil_tmp31 / line_time_us;
 #line 4069
   __cil_tmp33 = __cil_tmp32 + 1000UL;
 #line 4069
   __cil_tmp34 = __cil_tmp33 / 1000UL;
 #line 4069
   line_count = (int )__cil_tmp34;
 #line 4070
   line_size = hdisplay * pixel_size;
 #line 4073
   __cil_tmp35 = clock * pixel_size;
 #line 4073
   __cil_tmp36 = __cil_tmp35 / 1000;
 #line 4073
   __cil_tmp37 = __cil_tmp36 * latency_ns___0;
 #line 4073
   small = __cil_tmp37 / 1000;
 #line 4074
   large = line_count * line_size;
 #line 4076
   _min1 = small;
 #line 4076
   _min2 = large;
   }
 #line 4076
   if (_min1 < _min2) {
 #line 4076
     tmp___1 = _min1;
   } else {
 #line 4076
     tmp___1 = _min2;
   }
   {
 #line 4076
   __cil_tmp38 = display->cacheline_size;
 #line 4076
   __cil_tmp39 = (unsigned long )__cil_tmp38;
 #line 4076
   __cil_tmp40 = display->cacheline_size;
 #line 4076
   __cil_tmp41 = (unsigned long )__cil_tmp40;
 #line 4076
   __cil_tmp42 = (unsigned long )tmp___1;
 #line 4076
   __cil_tmp43 = __cil_tmp42 + __cil_tmp41;
 #line 4076
   __cil_tmp44 = __cil_tmp43 - 1UL;
 #line 4076
   __cil_tmp45 = __cil_tmp44 / __cil_tmp39;
 #line 4076
   entries = (int )__cil_tmp45;
 #line 4077
   __cil_tmp46 = (unsigned int )entries;
 #line 4077
   __cil_tmp47 = display->guard_size;
 #line 4077
   __cil_tmp48 = (unsigned int )__cil_tmp47;
 #line 4077
   __cil_tmp49 = __cil_tmp48 + __cil_tmp46;
 #line 4077
   *display_wm = (int )__cil_tmp49;
 #line 4083
   __cil_tmp50 = *display_wm;
 #line 4083
   __cil_tmp51 = __cil_tmp50 * 64;
 #line 4083
   __cil_tmp52 = __cil_tmp51 + line_size;
 #line 4083
   __cil_tmp53 = __cil_tmp52 + -1;
 #line 4083
   __cil_tmp54 = __cil_tmp53 / line_size;
 #line 4083
   *fbc_wm = __cil_tmp54 + 2;
 #line 4086
   __cil_tmp55 = line_count * pixel_size;
 #line 4086
   entries = __cil_tmp55 * 64;
 #line 4087
   __cil_tmp56 = cursor->cacheline_size;
 #line 4087
   __cil_tmp57 = (unsigned long )__cil_tmp56;
 #line 4087
   __cil_tmp58 = cursor->cacheline_size;
 #line 4087
   __cil_tmp59 = (unsigned long )__cil_tmp58;
 #line 4087
   __cil_tmp60 = (unsigned long )entries;
 #line 4087
   __cil_tmp61 = __cil_tmp60 + __cil_tmp59;
 #line 4087
   __cil_tmp62 = __cil_tmp61 - 1UL;
 #line 4087
   __cil_tmp63 = __cil_tmp62 / __cil_tmp57;
 #line 4087
   entries = (int )__cil_tmp63;
 #line 4088
   __cil_tmp64 = (unsigned int )entries;
 #line 4088
   __cil_tmp65 = cursor->guard_size;
 #line 4088
   __cil_tmp66 = (unsigned int )__cil_tmp65;
 #line 4088
   __cil_tmp67 = __cil_tmp66 + __cil_tmp64;
 #line 4088
   *cursor_wm = (int )__cil_tmp67;
 #line 4090
   __cil_tmp68 = *fbc_wm;
 #line 4090
   __cil_tmp69 = *display_wm;
 #line 4090
   __cil_tmp70 = *cursor_wm;
 #line 4090
   tmp___2 = ironlake_check_srwm(dev, level, __cil_tmp68, __cil_tmp69, __cil_tmp70,
                                 display, cursor);
   }
 #line 4090
   return (tmp___2);
 }
 }
 #line 4095 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void ironlake_update_wm(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int fbc_wm ;
   int plane_wm ;
   int cursor_wm ;
   unsigned int enabled ;
   bool tmp ;
   bool tmp___0 ;
   bool tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   u32 tmp___4 ;
   bool tmp___5 ;
   int tmp___6 ;
   u32 tmp___7 ;
   u32 tmp___8 ;
   bool tmp___9 ;
   int tmp___10 ;
   u32 tmp___11 ;
   void *__cil_tmp20 ;
   int __cil_tmp21 ;
   int __cil_tmp22 ;
   u32 __cil_tmp23 ;
   int __cil_tmp24 ;
   int __cil_tmp25 ;
   u32 __cil_tmp26 ;
   unsigned long __cil_tmp27 ;
   int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   unsigned int __cil_tmp31 ;
   unsigned int __cil_tmp32 ;
   int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   int __cil_tmp35 ;
   u32 __cil_tmp36 ;
   int __cil_tmp37 ;
   u32 __cil_tmp38 ;
   unsigned int __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   unsigned int __cil_tmp42 ;
   unsigned int __cil_tmp43 ;
   unsigned int __cil_tmp44 ;
   int __cil_tmp45 ;
   u32 __cil_tmp46 ;
   unsigned int __cil_tmp47 ;
   unsigned int __cil_tmp48 ;
   int __cil_tmp49 ;
   u32 __cil_tmp50 ;
   int __cil_tmp51 ;
   u32 __cil_tmp52 ;
   int __cil_tmp53 ;
   u32 __cil_tmp54 ;
   u32 __cil_tmp55 ;
   unsigned int __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   unsigned int __cil_tmp59 ;
   unsigned int __cil_tmp60 ;
   unsigned int __cil_tmp61 ;
 
   {
   {
 #line 4097
   __cil_tmp20 = dev->dev_private;
 #line 4097
   dev_priv = (struct drm_i915_private *)__cil_tmp20;
 #line 4101
   enabled = 0U;
 #line 4102
   tmp = g4x_compute_wm0(dev, 0, & ironlake_display_wm_info, 700, & ironlake_cursor_wm_info,
                         1300, & plane_wm, & cursor_wm);
   }
 #line 4102
   if ((int )tmp) {
     {
 #line 4108
     __cil_tmp21 = plane_wm << 16;
 #line 4108
     __cil_tmp22 = __cil_tmp21 | cursor_wm;
 #line 4108
     __cil_tmp23 = (u32 )__cil_tmp22;
 #line 4108
     i915_write32___4(dev_priv, 282880U, __cil_tmp23);
 #line 4110
     drm_ut_debug_printk(4U, "drm", "ironlake_update_wm", "FIFO watermarks For pipe A - plane %d, cursor: %d\n",
                         plane_wm, cursor_wm);
 #line 4113
     enabled = enabled | 1U;
     }
   } else {
 
   }
   {
 #line 4116
   tmp___0 = g4x_compute_wm0(dev, 1, & ironlake_display_wm_info, 700, & ironlake_cursor_wm_info,
                             1300, & plane_wm, & cursor_wm);
   }
 #line 4116
   if ((int )tmp___0) {
     {
 #line 4122
     __cil_tmp24 = plane_wm << 16;
 #line 4122
     __cil_tmp25 = __cil_tmp24 | cursor_wm;
 #line 4122
     __cil_tmp26 = (u32 )__cil_tmp25;
 #line 4122
     i915_write32___4(dev_priv, 282884U, __cil_tmp26);
 #line 4124
     drm_ut_debug_printk(4U, "drm", "ironlake_update_wm", "FIFO watermarks For pipe B - plane %d, cursor: %d\n",
                         plane_wm, cursor_wm);
 #line 4127
     enabled = enabled | 2U;
     }
   } else {
 
   }
   {
 #line 4134
   i915_write32___4(dev_priv, 282896U, 0U);
 #line 4135
   i915_write32___4(dev_priv, 282892U, 0U);
 #line 4136
   i915_write32___4(dev_priv, 282888U, 0U);
 #line 4138
   __cil_tmp27 = (unsigned long )enabled;
 #line 4138
   tmp___1 = is_power_of_2(__cil_tmp27);
   }
 #line 4138
   if (tmp___1) {
 #line 4138
     tmp___2 = 0;
   } else {
 #line 4138
     tmp___2 = 1;
   }
 #line 4138
   if (tmp___2) {
 #line 4139
     return;
   } else {
 
   }
   {
 #line 4140
   __cil_tmp28 = (int )enabled;
 #line 4140
   tmp___3 = ffs(__cil_tmp28);
 #line 4140
   __cil_tmp29 = tmp___3 + -1;
 #line 4140
   enabled = (unsigned int )__cil_tmp29;
 #line 4143
   tmp___4 = i915_read32___6(dev_priv, 70178U);
 #line 4143
   __cil_tmp30 = (int )enabled;
 #line 4143
   __cil_tmp31 = tmp___4 & 63U;
 #line 4143
   __cil_tmp32 = __cil_tmp31 * 500U;
 #line 4143
   __cil_tmp33 = (int )__cil_tmp32;
 #line 4143
   tmp___5 = ironlake_compute_srwm(dev, 1, __cil_tmp30, __cil_tmp33, & ironlake_display_srwm_info,
                                   & ironlake_cursor_srwm_info, & fbc_wm, & plane_wm,
                                   & cursor_wm);
   }
 #line 4143
   if (tmp___5) {
 #line 4143
     tmp___6 = 0;
   } else {
 #line 4143
     tmp___6 = 1;
   }
 #line 4143
   if (tmp___6) {
 #line 4148
     return;
   } else {
 
   }
   {
 #line 4150
   tmp___7 = i915_read32___6(dev_priv, 70178U);
 #line 4150
   __cil_tmp34 = (u32 )cursor_wm;
 #line 4150
   __cil_tmp35 = plane_wm << 8;
 #line 4150
   __cil_tmp36 = (u32 )__cil_tmp35;
 #line 4150
   __cil_tmp37 = fbc_wm << 20;
 #line 4150
   __cil_tmp38 = (u32 )__cil_tmp37;
 #line 4150
   __cil_tmp39 = tmp___7 & 63U;
 #line 4150
   __cil_tmp40 = __cil_tmp39 << 24;
 #line 4150
   __cil_tmp41 = __cil_tmp40 | __cil_tmp38;
 #line 4150
   __cil_tmp42 = __cil_tmp41 | __cil_tmp36;
 #line 4150
   __cil_tmp43 = __cil_tmp42 | __cil_tmp34;
 #line 4150
   __cil_tmp44 = __cil_tmp43 | 2147483648U;
 #line 4150
   i915_write32___4(dev_priv, 282888U, __cil_tmp44);
 #line 4158
   tmp___8 = i915_read32___6(dev_priv, 70178U);
 #line 4158
   __cil_tmp45 = (int )enabled;
 #line 4158
   __cil_tmp46 = tmp___8 >> 8;
 #line 4158
   __cil_tmp47 = __cil_tmp46 & 63U;
 #line 4158
   __cil_tmp48 = __cil_tmp47 * 500U;
 #line 4158
   __cil_tmp49 = (int )__cil_tmp48;
 #line 4158
   tmp___9 = ironlake_compute_srwm(dev, 2, __cil_tmp45, __cil_tmp49, & ironlake_display_srwm_info,
                                   & ironlake_cursor_srwm_info, & fbc_wm, & plane_wm,
                                   & cursor_wm);
   }
 #line 4158
   if (tmp___9) {
 #line 4158
     tmp___10 = 0;
   } else {
 #line 4158
     tmp___10 = 1;
   }
 #line 4158
   if (tmp___10) {
 #line 4163
     return;
   } else {
 
   }
   {
 #line 4165
   tmp___11 = i915_read32___6(dev_priv, 70178U);
 #line 4165
   __cil_tmp50 = (u32 )cursor_wm;
 #line 4165
   __cil_tmp51 = plane_wm << 8;
 #line 4165
   __cil_tmp52 = (u32 )__cil_tmp51;
 #line 4165
   __cil_tmp53 = fbc_wm << 20;
 #line 4165
   __cil_tmp54 = (u32 )__cil_tmp53;
 #line 4165
   __cil_tmp55 = tmp___11 >> 8;
 #line 4165
   __cil_tmp56 = __cil_tmp55 & 63U;
 #line 4165
   __cil_tmp57 = __cil_tmp56 << 24;
 #line 4165
   __cil_tmp58 = __cil_tmp57 | __cil_tmp54;
 #line 4165
   __cil_tmp59 = __cil_tmp58 | __cil_tmp52;
 #line 4165
   __cil_tmp60 = __cil_tmp59 | __cil_tmp50;
 #line 4165
   __cil_tmp61 = __cil_tmp60 | 2147483648U;
 #line 4165
   i915_write32___4(dev_priv, 282892U, __cil_tmp61);
   }
 #line 4166
   return;
 }
 }
 #line 4178 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void sandybridge_update_wm(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   int latency ;
   u32 tmp ;
   int fbc_wm ;
   int plane_wm ;
   int cursor_wm ;
   unsigned int enabled ;
   bool tmp___0 ;
   bool tmp___1 ;
   bool tmp___2 ;
   int tmp___3 ;
   int tmp___4 ;
   u32 tmp___5 ;
   bool tmp___6 ;
   int tmp___7 ;
   u32 tmp___8 ;
   u32 tmp___9 ;
   bool tmp___10 ;
   int tmp___11 ;
   u32 tmp___12 ;
   u32 tmp___13 ;
   bool tmp___14 ;
   int tmp___15 ;
   u32 tmp___16 ;
   void *__cil_tmp26 ;
   unsigned int __cil_tmp27 ;
   unsigned int __cil_tmp28 ;
   int __cil_tmp29 ;
   int __cil_tmp30 ;
   u32 __cil_tmp31 ;
   int __cil_tmp32 ;
   int __cil_tmp33 ;
   u32 __cil_tmp34 ;
   unsigned long __cil_tmp35 ;
   int __cil_tmp36 ;
   int __cil_tmp37 ;
   int __cil_tmp38 ;
   u32 __cil_tmp39 ;
   unsigned int __cil_tmp40 ;
   unsigned int __cil_tmp41 ;
   int __cil_tmp42 ;
   u32 __cil_tmp43 ;
   int __cil_tmp44 ;
   u32 __cil_tmp45 ;
   int __cil_tmp46 ;
   u32 __cil_tmp47 ;
   u32 __cil_tmp48 ;
   unsigned int __cil_tmp49 ;
   unsigned int __cil_tmp50 ;
   unsigned int __cil_tmp51 ;
   unsigned int __cil_tmp52 ;
   unsigned int __cil_tmp53 ;
   unsigned int __cil_tmp54 ;
   int __cil_tmp55 ;
   u32 __cil_tmp56 ;
   unsigned int __cil_tmp57 ;
   unsigned int __cil_tmp58 ;
   int __cil_tmp59 ;
   u32 __cil_tmp60 ;
   int __cil_tmp61 ;
   u32 __cil_tmp62 ;
   int __cil_tmp63 ;
   u32 __cil_tmp64 ;
   u32 __cil_tmp65 ;
   unsigned int __cil_tmp66 ;
   unsigned int __cil_tmp67 ;
   unsigned int __cil_tmp68 ;
   unsigned int __cil_tmp69 ;
   unsigned int __cil_tmp70 ;
   unsigned int __cil_tmp71 ;
   int __cil_tmp72 ;
   u32 __cil_tmp73 ;
   unsigned int __cil_tmp74 ;
   unsigned int __cil_tmp75 ;
   int __cil_tmp76 ;
   u32 __cil_tmp77 ;
   int __cil_tmp78 ;
   u32 __cil_tmp79 ;
   int __cil_tmp80 ;
   u32 __cil_tmp81 ;
   unsigned int __cil_tmp82 ;
   unsigned int __cil_tmp83 ;
   unsigned int __cil_tmp84 ;
   unsigned int __cil_tmp85 ;
   unsigned int __cil_tmp86 ;
 
   {
   {
 #line 4180
   __cil_tmp26 = dev->dev_private;
 #line 4180
   dev_priv = (struct drm_i915_private *)__cil_tmp26;
 #line 4181
   tmp = i915_read32___6(dev_priv, 1334544U);
 #line 4181
   __cil_tmp27 = tmp & 63U;
 #line 4181
   __cil_tmp28 = __cil_tmp27 * 100U;
 #line 4181
   latency = (int )__cil_tmp28;
 #line 4185
   enabled = 0U;
 #line 4186
   tmp___0 = g4x_compute_wm0(dev, 0, & sandybridge_display_wm_info, latency, & sandybridge_cursor_wm_info,
                             latency, & plane_wm, & cursor_wm);
   }
 #line 4186
   if ((int )tmp___0) {
     {
 #line 4190
     __cil_tmp29 = plane_wm << 16;
 #line 4190
     __cil_tmp30 = __cil_tmp29 | cursor_wm;
 #line 4190
     __cil_tmp31 = (u32 )__cil_tmp30;
 #line 4190
     i915_write32___4(dev_priv, 282880U, __cil_tmp31);
 #line 4192
     drm_ut_debug_printk(4U, "drm", "sandybridge_update_wm", "FIFO watermarks For pipe A - plane %d, cursor: %d\n",
                         plane_wm, cursor_wm);
 #line 4195
     enabled = enabled | 1U;
     }
   } else {
 
   }
   {
 #line 4198
   tmp___1 = g4x_compute_wm0(dev, 1, & sandybridge_display_wm_info, latency, & sandybridge_cursor_wm_info,
                             latency, & plane_wm, & cursor_wm);
   }
 #line 4198
   if ((int )tmp___1) {
     {
 #line 4202
     __cil_tmp32 = plane_wm << 16;
 #line 4202
     __cil_tmp33 = __cil_tmp32 | cursor_wm;
 #line 4202
     __cil_tmp34 = (u32 )__cil_tmp33;
 #line 4202
     i915_write32___4(dev_priv, 282884U, __cil_tmp34);
 #line 4204
     drm_ut_debug_printk(4U, "drm", "sandybridge_update_wm", "FIFO watermarks For pipe B - plane %d, cursor: %d\n",
                         plane_wm, cursor_wm);
 #line 4207
     enabled = enabled | 2U;
     }
   } else {
 
   }
   {
 #line 4220
   i915_write32___4(dev_priv, 282896U, 0U);
 #line 4221
   i915_write32___4(dev_priv, 282892U, 0U);
 #line 4222
   i915_write32___4(dev_priv, 282888U, 0U);
 #line 4224
   __cil_tmp35 = (unsigned long )enabled;
 #line 4224
   tmp___2 = is_power_of_2(__cil_tmp35);
   }
 #line 4224
   if (tmp___2) {
 #line 4224
     tmp___3 = 0;
   } else {
 #line 4224
     tmp___3 = 1;
   }
 #line 4224
   if (tmp___3) {
 #line 4225
     return;
   } else {
 
   }
   {
 #line 4226
   __cil_tmp36 = (int )enabled;
 #line 4226
   tmp___4 = ffs(__cil_tmp36);
 #line 4226
   __cil_tmp37 = tmp___4 + -1;
 #line 4226
   enabled = (unsigned int )__cil_tmp37;
 #line 4229
   tmp___5 = i915_read32___6(dev_priv, 1334544U);
 #line 4229
   __cil_tmp38 = (int )enabled;
 #line 4229
   __cil_tmp39 = tmp___5 >> 8;
 #line 4229
   __cil_tmp40 = __cil_tmp39 & 63U;
 #line 4229
   __cil_tmp41 = __cil_tmp40 * 500U;
 #line 4229
   __cil_tmp42 = (int )__cil_tmp41;
 #line 4229
   tmp___6 = ironlake_compute_srwm(dev, 1, __cil_tmp38, __cil_tmp42, & sandybridge_display_srwm_info,
                                   & sandybridge_cursor_srwm_info, & fbc_wm, & plane_wm,
                                   & cursor_wm);
   }
 #line 4229
   if (tmp___6) {
 #line 4229
     tmp___7 = 0;
   } else {
 #line 4229
     tmp___7 = 1;
   }
 #line 4229
   if (tmp___7) {
 #line 4234
     return;
   } else {
 
   }
   {
 #line 4236
   tmp___8 = i915_read32___6(dev_priv, 1334544U);
 #line 4236
   __cil_tmp43 = (u32 )cursor_wm;
 #line 4236
   __cil_tmp44 = plane_wm << 8;
 #line 4236
   __cil_tmp45 = (u32 )__cil_tmp44;
 #line 4236
   __cil_tmp46 = fbc_wm << 20;
 #line 4236
   __cil_tmp47 = (u32 )__cil_tmp46;
 #line 4236
   __cil_tmp48 = tmp___8 >> 8;
 #line 4236
   __cil_tmp49 = __cil_tmp48 & 63U;
 #line 4236
   __cil_tmp50 = __cil_tmp49 << 24;
 #line 4236
   __cil_tmp51 = __cil_tmp50 | __cil_tmp47;
 #line 4236
   __cil_tmp52 = __cil_tmp51 | __cil_tmp45;
 #line 4236
   __cil_tmp53 = __cil_tmp52 | __cil_tmp43;
 #line 4236
   __cil_tmp54 = __cil_tmp53 | 2147483648U;
 #line 4236
   i915_write32___4(dev_priv, 282888U, __cil_tmp54);
 #line 4244
   tmp___9 = i915_read32___6(dev_priv, 1334544U);
 #line 4244
   __cil_tmp55 = (int )enabled;
 #line 4244
   __cil_tmp56 = tmp___9 >> 16;
 #line 4244
   __cil_tmp57 = __cil_tmp56 & 63U;
 #line 4244
   __cil_tmp58 = __cil_tmp57 * 500U;
 #line 4244
   __cil_tmp59 = (int )__cil_tmp58;
 #line 4244
   tmp___10 = ironlake_compute_srwm(dev, 2, __cil_tmp55, __cil_tmp59, & sandybridge_display_srwm_info,
                                    & sandybridge_cursor_srwm_info, & fbc_wm, & plane_wm,
                                    & cursor_wm);
   }
 #line 4244
   if (tmp___10) {
 #line 4244
     tmp___11 = 0;
   } else {
 #line 4244
     tmp___11 = 1;
   }
 #line 4244
   if (tmp___11) {
 #line 4249
     return;
   } else {
 
   }
   {
 #line 4251
   tmp___12 = i915_read32___6(dev_priv, 1334544U);
 #line 4251
   __cil_tmp60 = (u32 )cursor_wm;
 #line 4251
   __cil_tmp61 = plane_wm << 8;
 #line 4251
   __cil_tmp62 = (u32 )__cil_tmp61;
 #line 4251
   __cil_tmp63 = fbc_wm << 20;
 #line 4251
   __cil_tmp64 = (u32 )__cil_tmp63;
 #line 4251
   __cil_tmp65 = tmp___12 >> 16;
 #line 4251
   __cil_tmp66 = __cil_tmp65 & 63U;
 #line 4251
   __cil_tmp67 = __cil_tmp66 << 24;
 #line 4251
   __cil_tmp68 = __cil_tmp67 | __cil_tmp64;
 #line 4251
   __cil_tmp69 = __cil_tmp68 | __cil_tmp62;
 #line 4251
   __cil_tmp70 = __cil_tmp69 | __cil_tmp60;
 #line 4251
   __cil_tmp71 = __cil_tmp70 | 2147483648U;
 #line 4251
   i915_write32___4(dev_priv, 282892U, __cil_tmp71);
 #line 4259
   tmp___13 = i915_read32___6(dev_priv, 1334544U);
 #line 4259
   __cil_tmp72 = (int )enabled;
 #line 4259
   __cil_tmp73 = tmp___13 >> 24;
 #line 4259
   __cil_tmp74 = __cil_tmp73 & 63U;
 #line 4259
   __cil_tmp75 = __cil_tmp74 * 500U;
 #line 4259
   __cil_tmp76 = (int )__cil_tmp75;
 #line 4259
   tmp___14 = ironlake_compute_srwm(dev, 3, __cil_tmp72, __cil_tmp76, & sandybridge_display_srwm_info,
                                    & sandybridge_cursor_srwm_info, & fbc_wm, & plane_wm,
                                    & cursor_wm);
   }
 #line 4259
   if (tmp___14) {
 #line 4259
     tmp___15 = 0;
   } else {
 #line 4259
     tmp___15 = 1;
   }
 #line 4259
   if (tmp___15) {
 #line 4264
     return;
   } else {
 
   }
   {
 #line 4266
   tmp___16 = i915_read32___6(dev_priv, 1334544U);
 #line 4266
   __cil_tmp77 = (u32 )cursor_wm;
 #line 4266
   __cil_tmp78 = plane_wm << 8;
 #line 4266
   __cil_tmp79 = (u32 )__cil_tmp78;
 #line 4266
   __cil_tmp80 = fbc_wm << 20;
 #line 4266
   __cil_tmp81 = (u32 )__cil_tmp80;
 #line 4266
   __cil_tmp82 = tmp___16 & 1056964608U;
 #line 4266
   __cil_tmp83 = __cil_tmp82 | __cil_tmp81;
 #line 4266
   __cil_tmp84 = __cil_tmp83 | __cil_tmp79;
 #line 4266
   __cil_tmp85 = __cil_tmp84 | __cil_tmp77;
 #line 4266
   __cil_tmp86 = __cil_tmp85 | 2147483648U;
 #line 4266
   i915_write32___4(dev_priv, 282896U, __cil_tmp86);
   }
 #line 4267
   return;
 }
 }
 #line 4306 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static void intel_update_watermarks(struct drm_device *dev ) 
 { struct drm_i915_private *dev_priv ;
   void *__cil_tmp3 ;
   void (*__cil_tmp4)(struct drm_device * ) ;
   unsigned long __cil_tmp5 ;
   void (*__cil_tmp6)(struct drm_device * ) ;
   unsigned long __cil_tmp7 ;
   void (*__cil_tmp8)(struct drm_device * ) ;
 
   {
 #line 4308
   __cil_tmp3 = dev->dev_private;
 #line 4308
   dev_priv = (struct drm_i915_private *)__cil_tmp3;
   {
 #line 4310
   __cil_tmp4 = (void (*)(struct drm_device * ))0;
 #line 4310
   __cil_tmp5 = (unsigned long )__cil_tmp4;
 #line 4310
   __cil_tmp6 = dev_priv->display.update_wm;
 #line 4310
   __cil_tmp7 = (unsigned long )__cil_tmp6;
 #line 4310
   if (__cil_tmp7 != __cil_tmp5) {
     {
 #line 4311
     __cil_tmp8 = dev_priv->display.update_wm;
 #line 4311
     (*__cil_tmp8)(dev);
     }
   } else {
 
   }
   }
 #line 4312
   return;
 }
 }
 #line 4314 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 __inline static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv ) 
 { int tmp ;
   unsigned char *__cil_tmp3 ;
   unsigned char *__cil_tmp4 ;
   unsigned char __cil_tmp5 ;
   unsigned int __cil_tmp6 ;
   unsigned long __cil_tmp7 ;
   unsigned long __cil_tmp8 ;
 
   {
   {
 #line 4316
   __cil_tmp3 = (unsigned char *)dev_priv;
 #line 4316
   __cil_tmp4 = __cil_tmp3 + 2072UL;
 #line 4316
   __cil_tmp5 = *__cil_tmp4;
 #line 4316
   __cil_tmp6 = (unsigned int )__cil_tmp5;
 #line 4316
   if (__cil_tmp6 != 0U) {
 #line 4316
     if (i915_panel_use_ssc != 0U) {
       {
 #line 4316
       __cil_tmp7 = dev_priv->quirks;
 #line 4316
       __cil_tmp8 = __cil_tmp7 & 2UL;
 #line 4316
       if (__cil_tmp8 == 0UL) {
 #line 4316
         tmp = 1;
       } else {
 #line 4316
         tmp = 0;
       }
       }
     } else {
 #line 4316
       tmp = 0;
     }
   } else {
 #line 4316
     tmp = 0;
   }
   }
 #line 4316
   return ((bool )tmp);
 }
 }
 #line 4320 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
 static int i9xx_crtc_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode ,
                               struct drm_display_mode *adjusted_mode , int x , int y ,
                               struct drm_framebuffer *old_fb ) 
 { struct drm_device *dev ;
   struct drm_i915_private *dev_priv ;
   struct intel_crtc *intel_crtc ;
   struct drm_crtc  const  *__mptr ;
   int pipe ;
   int plane ;
   int refclk ;
   int num_connectors ;
   intel_clock_t clock ;
   intel_clock_t reduced_clock ;
   u32 dpll ;
   u32 fp ;
   u32 fp2 ;
   u32 dspcntr ;
   u32 pipeconf ;
   bool ok ;
   bool has_reduced_clock ;
   bool is_sdvo ;
   bool is_dvo ;
   bool is_crt ;
   bool is_lvds ;
   bool is_tv ;
   bool is_dp ;
   struct drm_mode_config *mode_config ;
   struct intel_encoder *encoder ;
   intel_limit_t const   *limit ;
   int ret ;
   u32 temp ;
   u32 lvds_sync ;
   struct list_head  const  *__mptr___0 ;
   struct list_head  const  *__mptr___1 ;
   bool tmp ;
   int pixel_multiplier ;
   int tmp___0 ;
   bool tmp___1 ;
   int tmp___2 ;
   int tmp___3 ;
   char flags[2U] ;
   int tmp___4 ;
   void *__cil_tmp46 ;
   enum pipe __cil_tmp47 ;
   enum plane __cil_tmp48 ;
   struct list_head *__cil_tmp49 ;
   struct intel_encoder *__cil_tmp50 ;
   unsigned long __cil_tmp51 ;
   struct drm_crtc *__cil_tmp52 ;
   unsigned long __cil_tmp53 ;
   int __cil_tmp54 ;
   int __cil_tmp55 ;
   int __cil_tmp56 ;
   int __cil_tmp57 ;
   int __cil_tmp58 ;
   int __cil_tmp59 ;
   int __cil_tmp60 ;
   bool __cil_tmp61 ;
   struct list_head *__cil_tmp62 ;
   struct intel_encoder *__cil_tmp63 ;
   struct list_head *__cil_tmp64 ;
   unsigned long __cil_tmp65 ;
   struct list_head *__cil_tmp66 ;
   unsigned long __cil_tmp67 ;
   int __cil_tmp68 ;
   int __cil_tmp69 ;
   void *__cil_tmp70 ;
   struct drm_i915_private *__cil_tmp71 ;
   struct intel_device_info  const  *__cil_tmp72 ;
   u8 __cil_tmp73 ;
   unsigned char __cil_tmp74 ;
   unsigned int __cil_tmp75 ;
   bool (*__cil_tmp76)(intel_limit_t const   * , struct drm_crtc * , int  , int  ,
                       intel_clock_t * ) ;
   int __cil_tmp77 ;
   bool __cil_tmp78 ;
   bool __cil_tmp79 ;
   bool (*__cil_tmp80)(intel_limit_t const   * , struct drm_crtc * , int  , int  ,
                       intel_clock_t * ) ;
   int __cil_tmp81 ;
   int __cil_tmp82 ;
   int __cil_tmp83 ;
   int __cil_tmp84 ;
   int __cil_tmp85 ;
   void *__cil_tmp86 ;
   struct drm_i915_private *__cil_tmp87 ;
   struct intel_device_info  const  *__cil_tmp88 ;
   unsigned char *__cil_tmp89 ;
   unsigned char *__cil_tmp90 ;
   unsigned char __cil_tmp91 ;
   unsigned int __cil_tmp92 ;
   int __cil_tmp93 ;
   int __cil_tmp94 ;
   int __cil_tmp95 ;
   int __cil_tmp96 ;
   int __cil_tmp97 ;
   int __cil_tmp98 ;
   int __cil_tmp99 ;
   int __cil_tmp100 ;
   int __cil_tmp101 ;
   int __cil_tmp102 ;
   int __cil_tmp103 ;
   int __cil_tmp104 ;
   int __cil_tmp105 ;
   int __cil_tmp106 ;
   int __cil_tmp107 ;
   int __cil_tmp108 ;
   int __cil_tmp109 ;
   int __cil_tmp110 ;
   void *__cil_tmp111 ;
   struct drm_i915_private *__cil_tmp112 ;
   struct intel_device_info  const  *__cil_tmp113 ;
   u8 __cil_tmp114 ;
   unsigned char __cil_tmp115 ;
   unsigned int __cil_tmp116 ;
   struct drm_display_mode  const  *__cil_tmp117 ;
   int __cil_tmp118 ;
   int __cil_tmp119 ;
   int __cil_tmp120 ;
   u32 __cil_tmp121 ;
   void *__cil_tmp122 ;
   struct drm_i915_private *__cil_tmp123 ;
   struct intel_device_info  const  *__cil_tmp124 ;
   unsigned char *__cil_tmp125 ;
   unsigned char *__cil_tmp126 ;
   unsigned char __cil_tmp127 ;
   unsigned int __cil_tmp128 ;
   int __cil_tmp129 ;
   int __cil_tmp130 ;
   u32 __cil_tmp131 ;
   void *__cil_tmp132 ;
   struct drm_i915_private *__cil_tmp133 ;
   struct intel_device_info  const  *__cil_tmp134 ;
   unsigned char *__cil_tmp135 ;
   unsigned char *__cil_tmp136 ;
   unsigned char __cil_tmp137 ;
   unsigned int __cil_tmp138 ;
   int __cil_tmp139 ;
   int __cil_tmp140 ;
   u32 __cil_tmp141 ;
   void *__cil_tmp142 ;
   struct drm_i915_private *__cil_tmp143 ;
   struct intel_device_info  const  *__cil_tmp144 ;
   unsigned char *__cil_tmp145 ;
   unsigned char *__cil_tmp146 ;
   unsigned char __cil_tmp147 ;
   unsigned int __cil_tmp148 ;
   int __cil_tmp149 ;
   int __cil_tmp150 ;
   int __cil_tmp151 ;
   u32 __cil_tmp152 ;
   int __cil_tmp153 ;
   int __cil_tmp154 ;
   int __cil_tmp155 ;
   u32 __cil_tmp156 ;
   void *__cil_tmp157 ;
   struct drm_i915_private *__cil_tmp158 ;
   struct intel_device_info  const  *__cil_tmp159 ;
   unsigned char *__cil_tmp160 ;
   unsigned char *__cil_tmp161 ;
   unsigned char __cil_tmp162 ;
   unsigned int __cil_tmp163 ;
   int __cil_tmp164 ;
   int __cil_tmp165 ;
   u32 __cil_tmp166 ;
   void *__cil_tmp167 ;
   struct drm_i915_private *__cil_tmp168 ;
   struct intel_device_info  const  *__cil_tmp169 ;
   u8 __cil_tmp170 ;
   unsigned char __cil_tmp171 ;
   unsigned int __cil_tmp172 ;
   int __cil_tmp173 ;
   int __cil_tmp174 ;
   int __cil_tmp175 ;
   u32 __cil_tmp176 ;
   int __cil_tmp177 ;
   int __cil_tmp178 ;
   u32 __cil_tmp179 ;
   int __cil_tmp180 ;
   int __cil_tmp181 ;
   u32 __cil_tmp182 ;
   void *__cil_tmp183 ;
   struct drm_i915_private *__cil_tmp184 ;
   struct intel_device_info  const  *__cil_tmp185 ;
   u8 __cil_tmp186 ;
   unsigned char __cil_tmp187 ;
   unsigned int __cil_tmp188 ;
   int (*__cil_tmp189)(struct drm_device * ) ;
   int __cil_tmp190 ;
   int __cil_tmp191 ;
   int __cil_tmp192 ;
   int __cil_tmp193 ;
   int __cil_tmp194 ;
   u32 __cil_tmp195 ;
   int __cil_tmp196 ;
   int __cil_tmp197 ;
   u32 __cil_tmp198 ;
   unsigned int __cil_tmp199 ;
   int __cil_tmp200 ;
   int __cil_tmp201 ;
   unsigned long __cil_tmp202 ;
   void *__cil_tmp203 ;
   void const volatile   *__cil_tmp204 ;
   void const volatile   *__cil_tmp205 ;
   unsigned int __cil_tmp206 ;
   void *__cil_tmp207 ;
   struct drm_i915_private *__cil_tmp208 ;
   struct intel_device_info  const  *__cil_tmp209 ;
   u8 __cil_tmp210 ;
   unsigned char __cil_tmp211 ;
   unsigned int __cil_tmp212 ;
   unsigned char *__cil_tmp213 ;
   unsigned char *__cil_tmp214 ;
   unsigned char __cil_tmp215 ;
   unsigned int __cil_tmp216 ;
   unsigned int __cil_tmp217 ;
   unsigned int __cil_tmp218 ;
   unsigned int __cil_tmp219 ;
   unsigned int __cil_tmp220 ;
   unsigned int __cil_tmp221 ;
   int __cil_tmp222 ;
   int __cil_tmp223 ;
   int __cil_tmp224 ;
   int __cil_tmp225 ;
   int __cil_tmp226 ;
   int __cil_tmp227 ;
   u32 __cil_tmp228 ;
   int __cil_tmp229 ;
   int __cil_tmp230 ;
   unsigned long __cil_tmp231 ;
   void *__cil_tmp232 ;
   void const volatile   *__cil_tmp233 ;
   void const volatile   *__cil_tmp234 ;
   void *__cil_tmp235 ;
   struct drm_i915_private *__cil_tmp236 ;
   struct intel_device_info  const  *__cil_tmp237 ;
   u8 __cil_tmp238 ;
   unsigned char __cil_tmp239 ;
   unsigned int __cil_tmp240 ;
   struct drm_display_mode  const  *__cil_tmp241 ;
   u32 __cil_tmp242 ;
   int __cil_tmp243 ;
   int __cil_tmp244 ;
   u32 __cil_tmp245 ;
   int __cil_tmp246 ;
   int __cil_tmp247 ;
   u32 __cil_tmp248 ;
   int __cil_tmp249 ;
   int __cil_tmp250 ;
   u32 __cil_tmp251 ;
   void *__cil_tmp252 ;
   struct drm_i915_private *__cil_tmp253 ;
   struct intel_device_info  const  *__cil_tmp254 ;
   unsigned char *__cil_tmp255 ;
   unsigned char *__cil_tmp256 ;
   unsigned char __cil_tmp257 ;
   unsigned int __cil_tmp258 ;
   int __cil_tmp259 ;
   int __cil_tmp260 ;
   u32 __cil_tmp261 ;
   void *__cil_tmp262 ;
   struct drm_i915_private *__cil_tmp263 ;
   struct intel_device_info  const  *__cil_tmp264 ;
   unsigned char *__cil_tmp265 ;
   unsigned char *__cil_tmp266 ;
   unsigned char __cil_tmp267 ;
   unsigned int __cil_tmp268 ;
   unsigned int __cil_tmp269 ;
   unsigned int __cil_tmp270 ;
   int __cil_tmp271 ;
   int __cil_tmp272 ;
   int __cil_tmp273 ;
   int __cil_tmp274 ;
   int __cil_tmp275 ;
   int __cil_tmp276 ;
   int __cil_tmp277 ;
   int __cil_tmp278 ;
   u32 __cil_tmp279 ;
   int __cil_tmp280 ;
   int __cil_tmp281 ;
   int __cil_tmp282 ;
   int __cil_tmp283 ;
   int __cil_tmp284 ;
   int __cil_tmp285 ;
   u32 __cil_tmp286 ;
   int __cil_tmp287 ;
   int __cil_tmp288 ;
   u32 __cil_tmp289 ;
   int __cil_tmp290 ;
   int __cil_tmp291 ;
   int __cil_tmp292 ;
   int __cil_tmp293 ;
   int __cil_tmp294 ;
   int __cil_tmp295 ;
   u32 __cil_tmp296 ;
   int __cil_tmp297 ;
   int __cil_tmp298 ;
   u32 __cil_tmp299 ;
   int __cil_tmp300 ;
   int __cil_tmp301 ;
   int __cil_tmp302 ;
   int __cil_tmp303 ;
   int __cil_tmp304 ;
   int __cil_tmp305 ;
   u32 __cil_tmp306 ;
   int __cil_tmp307 ;
   int __cil_tmp308 ;
   u32 __cil_tmp309 ;
   int __cil_tmp310 ;
   int __cil_tmp311 ;
   int __cil_tmp312 ;
   int __cil_tmp313 ;
   int __cil_tmp314 ;
   int __cil_tmp315 ;
   u32 __cil_tmp316 ;
   int __cil_tmp317 ;
   int __cil_tmp318 ;
   u32 __cil_tmp319 ;
   int __cil_tmp320 ;
   int __cil_tmp321 ;
   int __cil_tmp322 ;
   int __cil_tmp323 ;
   int __cil_tmp324 ;
   int __cil_tmp325 ;
   u32 __cil_tmp326 ;
   int __cil_tmp327 ;
   int __cil_tmp328 ;
   u32 __cil_tmp329 ;
   int __cil_tmp330 ;
   int __cil_tmp331 ;
   int __cil_tmp332 ;
   int __cil_tmp333 ;
   int __cil_tmp334 ;
   int __cil_tmp335 ;
   u32 __cil_tmp336 ;
   int __cil_tmp337 ;
   int __cil_tmp338 ;
   u32 __cil_tmp339 ;
   int __cil_tmp340 ;
   int __cil_tmp341 ;
   int __cil_tmp342 ;
   int __cil_tmp343 ;
   int __cil_tmp344 ;
   int __cil_tmp345 ;
   u32 __cil_tmp346 ;
   int __cil_tmp347 ;
   int __cil_tmp348 ;
   u32 __cil_tmp349 ;
   int __cil_tmp350 ;
   int __cil_tmp351 ;
   u32 __cil_tmp352 ;
   int __cil_tmp353 ;
   int __cil_tmp354 ;
   int __cil_tmp355 ;
   int __cil_tmp356 ;
   int __cil_tmp357 ;
   int __cil_tmp358 ;
   u32 __cil_tmp359 ;
   int __cil_tmp360 ;
   int __cil_tmp361 ;
   u32 __cil_tmp362 ;
   int __cil_tmp363 ;
   int __cil_tmp364 ;
   unsigned long __cil_tmp365 ;
   void *__cil_tmp366 ;
   void const volatile   *__cil_tmp367 ;
   void const volatile   *__cil_tmp368 ;
   enum pipe __cil_tmp369 ;
   bool __cil_tmp370 ;
   int __cil_tmp371 ;
   int __cil_tmp372 ;
   u32 __cil_tmp373 ;
   int __cil_tmp374 ;
   int __cil_tmp375 ;
   unsigned long __cil_tmp376 ;
   void *__cil_tmp377 ;
   void const volatile   *__cil_tmp378 ;
   void const volatile   *__cil_tmp379 ;
   enum plane __cil_tmp380 ;
   enum pipe __cil_tmp381 ;
 
   {
 #line 4326
   dev = crtc->dev;
 #line 4327
   __cil_tmp46 = dev->dev_private;
 #line 4327
   dev_priv = (struct drm_i915_private *)__cil_tmp46;
 #line 4328
   __mptr = (struct drm_crtc  const  *)crtc;
 #line 4328
   intel_crtc = (struct intel_crtc *)__mptr;
 #line 4329
   __cil_tmp47 = intel_crtc->pipe;
 #line 4329
   pipe = (int )__cil_tmp47;
 #line 4330
   __cil_tmp48 = intel_crtc->plane;
 #line 4330
   plane = (int )__cil_tmp48;
 #line 4331
   num_connectors = 0;
 #line 4333
   fp = 0U;
 #line 4333
   fp2 = 0U;
 #line 4334
   has_reduced_clock = (bool )0;
 #line 4334
   is_sdvo = (bool )0;
 #line 4334
   is_dvo = (bool )0;
 #line 4335
   is_crt = (bool )0;
 #line 4335
   is_lvds = (bool )0;
 #line 4335
   is_tv = (bool )0;
 #line 4335
   is_dp = (bool )0;
 #line 4336
   mode_config = & dev->mode_config;
 #line 4341
   lvds_sync = 0U;
 #line 4343
   __cil_tmp49 = mode_config->encoder_list.next;
 #line 4343
   __mptr___0 = (struct list_head  const  *)__cil_tmp49;
 #line 4343
   __cil_tmp50 = (struct intel_encoder *)__mptr___0;
 #line 4343
   encoder = __cil_tmp50 + 1152921504606846968UL;
 #line 4343
   goto ldv_39475;
   ldv_39474: ;
   {
 #line 4344
   __cil_tmp51 = (unsigned long )crtc;
 #line 4344
   __cil_tmp52 = encoder->base.crtc;
 #line 4344
   __cil_tmp53 = (unsigned long )__cil_tmp52;
 #line 4344
   if (__cil_tmp53 != __cil_tmp51) {
 #line 4345
     goto ldv_39465;
   } else {
 
   }
   }
   {
 #line 4348
   __cil_tmp54 = encoder->type;
 #line 4348
   if (__cil_tmp54 == 4) {
 #line 4348
     goto case_4;
   } else {
     {
 #line 4351
     __cil_tmp55 = encoder->type;
 #line 4351
     if (__cil_tmp55 == 3) {
 #line 4351
       goto case_3;
     } else {
       {
 #line 4352
       __cil_tmp56 = encoder->type;
 #line 4352
       if (__cil_tmp56 == 6) {
 #line 4352
         goto case_6;
       } else {
         {
 #line 4357
         __cil_tmp57 = encoder->type;
 #line 4357
         if (__cil_tmp57 == 2) {
 #line 4357
           goto case_2;
         } else {
           {
 #line 4360
           __cil_tmp58 = encoder->type;
 #line 4360
           if (__cil_tmp58 == 5) {
 #line 4360
             goto case_5;
           } else {
             {
 #line 4363
             __cil_tmp59 = encoder->type;
 #line 4363
             if (__cil_tmp59 == 1) {
 #line 4363
               goto case_1;
             } else {
               {
 #line 4366
               __cil_tmp60 = encoder->type;
 #line 4366
               if (__cil_tmp60 == 7) {
 #line 4366
                 goto case_7;
               } else
 #line 4347
               if (0) {
                 case_4: 
 #line 4349
                 is_lvds = (bool )1;
 #line 4350
                 goto ldv_39467;
                 case_3: ;
                 case_6: 
 #line 4353
                 is_sdvo = (bool )1;
                 {
 #line 4354
                 __cil_tmp61 = encoder->needs_tv_clock;
 #line 4354
                 if ((int )__cil_tmp61) {
 #line 4355
                   is_tv = (bool )1;
                 } else {
 
                 }
                 }
 #line 4356
                 goto ldv_39467;
                 case_2: 
 #line 4358
                 is_dvo = (bool )1;
 #line 4359
                 goto ldv_39467;
                 case_5: 
 #line 4361
                 is_tv = (bool )1;
 #line 4362
                 goto ldv_39467;
                 case_1: 
 #line 4364
                 is_crt = (bool )1;
 #line 4365
                 goto ldv_39467;
                 case_7: 
 #line 4367
                 is_dp = (bool )1;
 #line 4368
                 goto ldv_39467;
               } else {
 
               }
               }
             }
             }
           }
           }
         }
         }
       }
       }
     }
     }
   }
   }
   ldv_39467: 
 #line 4371
   num_connectors = num_connectors + 1;
   ldv_39465: 
 #line 4343
   __cil_tmp62 = encoder->base.head.next;
 #line 4343
   __mptr___1 = (struct list_head  const  *)__cil_tmp62;
 #line 4343
   __cil_tmp63 = (struct intel_encoder *)__mptr___1;
 #line 4343
   encoder = __cil_tmp63 + 1152921504606846968UL;
   ldv_39475: ;
   {
 #line 4343
   __cil_tmp64 = & mode_config->encoder_list;
 #line 4343
   __cil_tmp65 = (unsigned long )__cil_tmp64;
 #line 4343
   __cil_tmp66 = & encoder->base.head;
 #line 4343
   __cil_tmp67 = (unsigned long )__cil_tmp66;
 #line 4343
   if (__cil_tmp67 != __cil_tmp65) {
 #line 4344
     goto ldv_39474;
   } else {
 #line 4346
     goto ldv_39476;
   }
   }
   ldv_39476: ;
 #line 4374
   if ((int )is_lvds) {
     {
 #line 4374
     tmp = intel_panel_use_ssc(dev_priv);
     }
 #line 4374
     if ((int )tmp) {
 #line 4374
       if (num_connectors <= 1) {
         {
 #line 4375
         __cil_tmp68 = dev_priv->lvds_ssc_freq;
 #line 4375
         refclk = __cil_tmp68 * 1000;
 #line 4376
         __cil_tmp69 = refclk / 1000;
 #line 4376
         drm_ut_debug_printk(4U, "drm", "i9xx_crtc_mode_set", "using SSC reference clock of %d MHz\n",
                             __cil_tmp69);
         }
       } else {
 #line 4374
         goto _L___0;
       }
     } else {
 #line 4374
       goto _L___0;
     }
   } else {
     _L___0: 
     {
 #line 4378
     __cil_tmp70 = dev->dev_private;
 #line 4378
     __cil_tmp71 = (struct drm_i915_private *)__cil_tmp70;
 #line 4378
     __cil_tmp72 = __cil_tmp71->info;
 #line 4378
     __cil_tmp73 = __cil_tmp72->gen;
 #line 4378
     __cil_tmp74 = (unsigned char )__cil_tmp73;
 #line 4378
     __cil_tmp75 = (unsigned int )__cil_tmp74;
 #line 4378
     if (__cil_tmp75 != 2U) {
 #line 4379
       refclk = 96000;
     } else {
 #line 4381
       refclk = 48000;
     }
     }
   }
   {
 #line 4389
   limit = intel_limit(crtc, refclk);
 #line 4390
   __cil_tmp76 = limit->find_pll;
 #line 4390
   __cil_tmp77 = adjusted_mode->clock;
 #line 4390
   ok = (*__cil_tmp76)(limit, crtc, __cil_tmp77, refclk, & clock);
   }
 #line 4391
   if (! ok) {
     {
 #line 4392
     drm_err("i9xx_crtc_mode_set", "Couldn\'t find PLL settings for mode!\n");
     }
 #line 4393
     return (-22);
   } else {
 
   }
   {
 #line 4397
   __cil_tmp78 = (bool )1;
 #line 4397
   intel_crtc_update_cursor(crtc, __cil_tmp78);
   }
 #line 4399
   if ((int )is_lvds) {
     {
 #line 4399
     __cil_tmp79 = dev_priv->lvds_downclock_avail;
 #line 4399
     if ((int )__cil_tmp79) {
       {
 #line 4400
       __cil_tmp80 = limit->find_pll;
 #line 4400
       __cil_tmp81 = dev_priv->lvds_downclock;
 #line 4400
       has_reduced_clock = (*__cil_tmp80)(limit, crtc, __cil_tmp81, refclk, & reduced_clock);
       }
 #line 4404
       if ((int )has_reduced_clock) {
 #line 4404
         if (clock.p != reduced_clock.p) {
           {
 #line 4411
           drm_ut_debug_printk(4U, "drm", "i9xx_crtc_mode_set", "Different P is found for LVDS clock/downclock\n");
 #line 4413
           has_reduced_clock = (bool )0;
           }
         } else {
 
         }
       } else {
 
       }
     } else {
 
     }
     }
   } else {
 
   }
 #line 4418
   if ((int )is_sdvo) {
 #line 4418
     if ((int )is_tv) {
       {
 #line 4419
       __cil_tmp82 = adjusted_mode->clock;
 #line 4419
       if (__cil_tmp82 > 99999) {
         {
 #line 4419
         __cil_tmp83 = adjusted_mode->clock;
 #line 4419
         if (__cil_tmp83 <= 140499) {
 #line 4421
           clock.p1 = 2;
 #line 4422
           clock.p2 = 10;
 #line 4423
           clock.n = 3;
 #line 4424
           clock.m1 = 16;
 #line 4425
           clock.m2 = 8;
         } else {
 #line 4419
           goto _L___1;
         }
         }
       } else {
         _L___1: 
         {
 #line 4426
         __cil_tmp84 = adjusted_mode->clock;
 #line 4426
         if (__cil_tmp84 > 140499) {
           {
 #line 4426
           __cil_tmp85 = adjusted_mode->clock;
 #line 4426
           if (__cil_tmp85 <= 200000) {
 #line 4428
             clock.p1 = 1;
 #line 4429
             clock.p2 = 10;
 #line 4430
             clock.n = 6;
 #line 4431
             clock.m1 = 12;
 #line 4432
             clock.m2 = 8;
           } else {
 
           }
           }
         } else {
 
         }
         }
       }
       }
     } else {
 
     }
   } else {
 
   }
   {
 #line 4436
   __cil_tmp86 = dev->dev_private;
 #line 4436
   __cil_tmp87 = (struct drm_i915_private *)__cil_tmp86;
 #line 4436
   __cil_tmp88 = __cil_tmp87->info;
 #line 4436
   __cil_tmp89 = (unsigned char *)__cil_tmp88;
 #line 4436
   __cil_tmp90 = __cil_tmp89 + 1UL;
 #line 4436
   __cil_tmp91 = *__cil_tmp90;
 #line 4436
   __cil_tmp92 = (unsigned int )__cil_tmp91;
 #line 4436
   if (__cil_tmp92 != 0U) {
 #line 4437
     __cil_tmp93 = clock.m1 << 8;
 #line 4437
     __cil_tmp94 = 1 << clock.n;
 #line 4437
     __cil_tmp95 = __cil_tmp94 << 16;
 #line 4437
     __cil_tmp96 = __cil_tmp95 | __cil_tmp93;
 #line 4437
     __cil_tmp97 = __cil_tmp96 | clock.m2;
 #line 4437
     fp = (u32 )__cil_tmp97;
 #line 4438
     if ((int )has_reduced_clock) {
 #line 4439
       __cil_tmp98 = reduced_clock.m1 << 8;
 #line 4439
       __cil_tmp99 = 1 << reduced_clock.n;
 #line 4439
       __cil_tmp100 = __cil_tmp99 << 16;
 #line 4439
       __cil_tmp101 = __cil_tmp100 | __cil_tmp98;
 #line 4439
       __cil_tmp102 = __cil_tmp101 | reduced_clock.m2;
 #line 4439
       fp2 = (u32 )__cil_tmp102;
     } else {
 
     }
   } else {
 #line 4442
     __cil_tmp103 = clock.m1 << 8;
 #line 4442
     __cil_tmp104 = clock.n << 16;
 #line 4442
     __cil_tmp105 = __cil_tmp104 | __cil_tmp103;
 #line 4442
     __cil_tmp106 = __cil_tmp105 | clock.m2;
 #line 4442
     fp = (u32 )__cil_tmp106;
 #line 4443
     if ((int )has_reduced_clock) {
 #line 4444
       __cil_tmp107 = reduced_clock.m1 << 8;
 #line 4444
       __cil_tmp108 = reduced_clock.n << 16;
 #line 4444
       __cil_tmp109 = __cil_tmp108 | __cil_tmp107;
 #line 4444
       __cil_tmp110 = __cil_tmp109 | reduced_clock.m2;
 #line 4444
       fp2 = (u32 )__cil_tmp110;
     } else {
 
     }
   }
   }
 #line 4448
   dpll = 268435456U;
   {
 #line 4450
   __cil_tmp111 = dev->dev_private;
 #line 4450
   __cil_tmp112 = (struct drm_i915_private *)__cil_tmp111;
 #line 4450
   __cil_tmp113 = __cil_tmp112->info;
 #line 4450
   __cil_tmp114 = __cil_tmp113->gen;
 #line 4450
   __cil_tmp115 = (unsigned char )__cil_tmp114;
 #line 4450
   __cil_tmp116 = (unsigned int )__cil_tmp115;
 #line 4450
   if (__cil_tmp116 != 2U) {
 #line 4451
     if ((int )is_lvds) {
 #line 4452
       dpll = dpll | 134217728U;
     } else {
 #line 4454
       dpll = dpll | 67108864U;
     }
 #line 4455
     if ((int )is_sdvo) {
       {
 #line 4456
       __cil_tmp117 = (struct drm_display_mode  const  *)adjusted_mode;
 #line 4456
       tmp___0 = intel_mode_get_pixel_multiplier(__cil_tmp117);
 #line 4456
       pixel_multiplier = tmp___0;
       }
 #line 4457
       if (pixel_multiplier > 1) {
         {
 #line 4458
         __cil_tmp118 = dev->pci_device;
 #line 4458
         if (__cil_tmp118 == 10098) {
 #line 4459
           __cil_tmp119 = pixel_multiplier + -1;
 #line 4459
           __cil_tmp120 = __cil_tmp119 << 4;
 #line 4459
           __cil_tmp121 = (u32 )__cil_tmp120;
 #line 4459
           dpll = __cil_tmp121 | dpll;
         } else {
           {
 #line 4458
           __cil_tmp122 = dev->dev_private;
 #line 4458
           __cil_tmp123 = (struct drm_i915_private *)__cil_tmp122;
 #line 4458
           __cil_tmp124 = __cil_tmp123->info;
 #line 4458
           __cil_tmp125 = (unsigned char *)__cil_tmp124;
 #line 4458
           __cil_tmp126 = __cil_tmp125 + 1UL;
 #line 4458
           __cil_tmp127 = *__cil_tmp126;
 #line 4458
           __cil_tmp128 = (unsigned int )__cil_tmp127;
 #line 4458
           if (__cil_tmp128 != 0U) {
 #line 4459
             __cil_tmp129 = pixel_multiplier + -1;
 #line 4459
             __cil_tmp130 = __cil_tmp129 << 4;
 #line 4459
             __cil_tmp131 = (u32 )__cil_tmp130;
 #line 4459
             dpll = __cil_tmp131 | dpll;
           } else {
             {
 #line 4458
             __cil_tmp132 = dev->dev_private;
 #line 4458
             __cil_tmp133 = (struct drm_i915_private *)__cil_tmp132;
 #line 4458
             __cil_tmp134 = __cil_tmp133->info;
 #line 4458
             __cil_tmp135 = (unsigned char *)__cil_tmp134;
 #line 4458
             __cil_tmp136 = __cil_tmp135 + 1UL;
 #line 4458
             __cil_tmp137 = *__cil_tmp136;
 #line 4458
             __cil_tmp138 = (unsigned int )__cil_tmp137;
 #line 4458
             if (__cil_tmp138 != 0U) {
 #line 4459
               __cil_tmp139 = pixel_multiplier + -1;
 #line 4459
               __cil_tmp140 = __cil_tmp139 << 4;
 #line 4459
               __cil_tmp141 = (u32 )__cil_tmp140;
 #line 4459
               dpll = __cil_tmp141 | dpll;
             } else {
 
             }
             }
           }
           }
         }
         }
       } else {
 
       }
 #line 4461
       dpll = dpll | 1073741824U;
     } else {
 
     }
 #line 4463
     if ((int )is_dp) {
 #line 4464
       dpll = dpll | 1073741824U;
     } else {
 
     }
     {
 #line 4467
     __cil_tmp142 = dev->dev_private;
 #line 4467
     __cil_tmp143 = (struct drm_i915_private *)__cil_tmp142;
 #line 4467
     __cil_tmp144 = __cil_tmp143->info;
 #line 4467
     __cil_tmp145 = (unsigned char *)__cil_tmp144;
 #line 4467
     __cil_tmp146 = __cil_tmp145 + 1UL;
 #line 4467
     __cil_tmp147 = *__cil_tmp146;
 #line 4467
     __cil_tmp148 = (unsigned int )__cil_tmp147;
 #line 4467
     if (__cil_tmp148 != 0U) {
 #line 4468
       __cil_tmp149 = clock.p1 + -1;
 #line 4468
       __cil_tmp150 = 1 << __cil_tmp149;
 #line 4468
       __cil_tmp151 = __cil_tmp150 << 15;
 #line 4468
       __cil_tmp152 = (u32 )__cil_tmp151;
 #line 4468
       dpll = __cil_tmp152 | dpll;
     } else {
 #line 4470
       __cil_tmp153 = clock.p1 + -1;
 #line 4470
       __cil_tmp154 = 1 << __cil_tmp153;
 #line 4470
       __cil_tmp155 = __cil_tmp154 << 16;
 #line 4470
       __cil_tmp156 = (u32 )__cil_tmp155;
 #line 4470
       dpll = __cil_tmp156 | dpll;
       {
 #line 4471
       __cil_tmp157 = dev->dev_private;
 #line 4471
       __cil_tmp158 = (struct drm_i915_private *)__cil_tmp157;
 #line 4471
       __cil_tmp159 = __cil_tmp158->info;
 #line 4471
       __cil_tmp160 = (unsigned char *)__cil_tmp159;
 #line 4471
       __cil_tmp161 = __cil_tmp160 + 1UL;
 #line 4471
       __cil_tmp162 = *__cil_tmp161;
 #line 4471
       __cil_tmp163 = (unsigned int )__cil_tmp162;
 #line 4471
       if (__cil_tmp163 != 0U) {
 #line 4471
         if ((int )has_reduced_clock) {
 #line 4472
           __cil_tmp164 = reduced_clock.p1 + -1;
 #line 4472
           __cil_tmp165 = 1 << __cil_tmp164;
 #line 4472
           __cil_tmp166 = (u32 )__cil_tmp165;
 #line 4472
           dpll = __cil_tmp166 | dpll;
         } else {
 
         }
       } else {
 
       }
       }
     }
     }
 #line 4475
     if (clock.p2 == 5) {
 #line 4475
       goto case_5___0;
     } else
 #line 4478
     if (clock.p2 == 7) {
 #line 4478
       goto case_7___0;
     } else
 #line 4481
     if (clock.p2 == 10) {
 #line 4481
       goto case_10;
     } else
 #line 4484
     if (clock.p2 == 14) {
 #line 4484
       goto case_14;
     } else
 #line 4474
     if (0) {
       case_5___0: 
 #line 4476
       dpll = dpll | 16777216U;
 #line 4477
       goto ldv_39480;
       case_7___0: 
 #line 4479
       dpll = dpll | 16777216U;
 #line 4480
       goto ldv_39480;
       case_10: 
 #line 4482
       dpll = dpll;
 #line 4483
       goto ldv_39480;
       case_14: 
 #line 4485
       dpll = dpll;
 #line 4486
       goto ldv_39480;
     } else {
 
     }
     ldv_39480: ;
     {
 #line 4488
     __cil_tmp167 = dev->dev_private;
 #line 4488
     __cil_tmp168 = (struct drm_i915_private *)__cil_tmp167;
 #line 4488
     __cil_tmp169 = __cil_tmp168->info;
 #line 4488
     __cil_tmp170 = __cil_tmp169->gen;
 #line 4488
     __cil_tmp171 = (unsigned char )__cil_tmp170;
 #line 4488
     __cil_tmp172 = (unsigned int )__cil_tmp171;
 #line 4488
     if (__cil_tmp172 > 3U) {
 #line 4489
       dpll = dpll | 3072U;
     } else {
 
     }
     }
   } else
 #line 4491
   if ((int )is_lvds) {
 #line 4492
     __cil_tmp173 = clock.p1 + -1;
 #line 4492
     __cil_tmp174 = 1 << __cil_tmp173;
 #line 4492
     __cil_tmp175 = __cil_tmp174 << 16;
 #line 4492
     __cil_tmp176 = (u32 )__cil_tmp175;
 #line 4492
     dpll = __cil_tmp176 | dpll;
   } else {
 #line 4494
     if (clock.p1 == 2) {
 #line 4495
       dpll = dpll | 2097152U;
     } else {
 #line 4497
       __cil_tmp177 = clock.p1 + -2;
 #line 4497
       __cil_tmp178 = __cil_tmp177 << 16;
 #line 4497
       __cil_tmp179 = (u32 )__cil_tmp178;
 #line 4497
       dpll = __cil_tmp179 | dpll;
     }
 #line 4498
     if (clock.p2 == 4) {
 #line 4499
       dpll = dpll | 8388608U;
     } else {
 
     }
   }
   }
 #line 4503
   if ((int )is_sdvo) {
 #line 4503
     if ((int )is_tv) {
 #line 4504
       dpll = dpll | 16384U;
     } else {
 #line 4503
       goto _L___2;
     }
   } else
   _L___2: 
 #line 4505
   if ((int )is_tv) {
 #line 4508
     dpll = dpll | 3U;
   } else
 #line 4509
   if ((int )is_lvds) {
     {
 #line 4509
     tmp___1 = intel_panel_use_ssc(dev_priv);
     }
 #line 4509
     if ((int )tmp___1) {
 #line 4509
       if (num_connectors <= 1) {
 #line 4510
         dpll = dpll | 24576U;
       } else {
 #line 4512
         dpll = dpll;
       }
     } else {
 #line 4512
       dpll = dpll;
     }
   } else {
 #line 4512
     dpll = dpll;
   }
   {
 #line 4515
   __cil_tmp180 = pipe * 4096;
 #line 4515
   __cil_tmp181 = __cil_tmp180 + 458760;
 #line 4515
   __cil_tmp182 = (u32 )__cil_tmp181;
 #line 4515
   pipeconf = i915_read32___6(dev_priv, __cil_tmp182);
 #line 4518
   dspcntr = 1073741824U;
   }
 #line 4522
   if (pipe == 0) {
 #line 4523
     dspcntr = dspcntr & 4244635647U;
   } else {
 #line 4525
     dspcntr = dspcntr | 16777216U;
   }
 #line 4527
   if (pipe == 0) {
     {
 #line 4527
     __cil_tmp183 = dev->dev_private;
 #line 4527
     __cil_tmp184 = (struct drm_i915_private *)__cil_tmp183;
 #line 4527
     __cil_tmp185 = __cil_tmp184->info;
 #line 4527
     __cil_tmp186 = __cil_tmp185->gen;
 #line 4527
     __cil_tmp187 = (unsigned char )__cil_tmp186;
 #line 4527
     __cil_tmp188 = (unsigned int )__cil_tmp187;
 #line 4527
     if (__cil_tmp188 <= 3U) {
       {
 #line 4534
       __cil_tmp189 = dev_priv->display.get_display_clock_speed;
 #line 4534
       tmp___2 = (*__cil_tmp189)(dev);
       }
       {
 #line 4534
       __cil_tmp190 = tmp___2 * 9;
 #line 4534
       __cil_tmp191 = __cil_tmp190 / 10;
 #line 4534
       __cil_tmp192 = mode->clock;
 #line 4534
       if (__cil_tmp192 > __cil_tmp191) {
 #line 4536
         pipeconf = pipeconf | 1073741824U;
       } else {
 #line 4538
         pipeconf = pipeconf & 3221225471U;
       }
       }
     } else {
 
     }
     }
   } else {
 
   }
 #line 4541
   dpll = dpll | 2147483648U;
 #line 4543
   if (pipe == 0) {
 #line 4543
     tmp___3 = 65;
   } else {
 #line 4543
     tmp___3 = 66;
   }
   {
 #line 4543
   drm_ut_debug_printk(4U, "drm", "i9xx_crtc_mode_set", "Mode for pipe %c:\n", tmp___3);
 #line 4544
   drm_mode_debug_printmodeline(mode);
 #line 4546
   __cil_tmp193 = pipe + 3080;
 #line 4546
   __cil_tmp194 = __cil_tmp193 * 8;
 #line 4546
   __cil_tmp195 = (u32 )__cil_tmp194;
 #line 4546
   i915_write32___4(dev_priv, __cil_tmp195, fp);
 #line 4547
   __cil_tmp196 = pipe + 6149;
 #line 4547
   __cil_tmp197 = __cil_tmp196 * 4;
 #line 4547
   __cil_tmp198 = (u32 )__cil_tmp197;
 #line 4547
   __cil_tmp199 = dpll & 2147483647U;
 #line 4547
   i915_write32___4(dev_priv, __cil_tmp198, __cil_tmp199);
 #line 4549
   __cil_tmp200 = pipe + 6149;
 #line 4549
   __cil_tmp201 = __cil_tmp200 * 4;
 #line 4549
   __cil_tmp202 = (unsigned long )__cil_tmp201;
 #line 4549
   __cil_tmp203 = dev_priv->regs;
 #line 4549
   __cil_tmp204 = (void const volatile   *)__cil_tmp203;
 #line 4549
   __cil_tmp205 = __cil_tmp204 + __cil_tmp202;
 #line 4549
   readl(__cil_tmp205);
 #line 4550
   __const_udelay(644250UL);
   }
 #line 4556
   if ((int )is_lvds) {
     {
 #line 4557
     temp = i915_read32___6(dev_priv, 397696U);
 #line 4558
     temp = temp | 2147484416U;
     }
 #line 4559
     if (pipe == 1) {
 #line 4560
       temp = temp | 1073741824U;
     } else {
 #line 4562
       temp = temp & 3221225471U;
     }
 #line 4565
     __cil_tmp206 = dev_priv->lvds_border_bits;
 #line 4565
     temp = __cil_tmp206 | temp;
 #line 4569
     if (clock.p2 == 7) {
 #line 4570
       temp = temp | 60U;
     } else {
 #line 4572
       temp = temp & 4294967235U;
     }
     {
 #line 4579
     __cil_tmp207 = dev->dev_private;
 #line 4579
     __cil_tmp208 = (struct drm_i915_private *)__cil_tmp207;
 #line 4579
     __cil_tmp209 = __cil_tmp208->info;
 #line 4579
     __cil_tmp210 = __cil_tmp209->gen;
 #line 4579
     __cil_tmp211 = (unsigned char )__cil_tmp210;
 #line 4579
     __cil_tmp212 = (unsigned int )__cil_tmp211;
 #line 4579
     if (__cil_tmp212 > 3U) {
       {
 #line 4580
       __cil_tmp213 = (unsigned char *)dev_priv;
 #line 4580
       __cil_tmp214 = __cil_tmp213 + 2072UL;
 #line 4580
       __cil_tmp215 = *__cil_tmp214;
 #line 4580
       __cil_tmp216 = (unsigned int )__cil_tmp215;
 #line 4580
       if (__cil_tmp216 != 0U) {
 #line 4581
         temp = temp | 33554432U;
       } else {
 #line 4583
         temp = temp & 4261412863U;
       }
       }
     } else {
 
     }
     }
     {
 #line 4585
     __cil_tmp217 = adjusted_mode->flags;
 #line 4585
     __cil_tmp218 = __cil_tmp217 & 2U;
 #line 4585
     if (__cil_tmp218 != 0U) {
 #line 4586
       lvds_sync = lvds_sync | 1048576U;
     } else {
 
     }
     }
     {
 #line 4587
     __cil_tmp219 = adjusted_mode->flags;
 #line 4587
     __cil_tmp220 = __cil_tmp219 & 8U;
 #line 4587
     if (__cil_tmp220 != 0U) {
 #line 4588
       lvds_sync = lvds_sync | 2097152U;
     } else {
 
     }
     }
     {
 #line 4589
     __cil_tmp221 = temp & 3145728U;
 #line 4589
     if (__cil_tmp221 != lvds_sync) {
       {
 #line 4591
       flags[0] = (char )'-';
 #line 4591
       flags[1] = (char )'+';
 #line 4592
       __cil_tmp222 = (int )flags[(temp & 1048576U) == 0U];
 #line 4592
       __cil_tmp223 = (int )flags[(temp & 2097152U) == 0U];
 #line 4592
       __cil_tmp224 = (int )flags[(lvds_sync & 1048576U) == 0U];
 #line 4592
       __cil_tmp225 = (int )flags[(lvds_sync & 2097152U) == 0U];
 #line 4592
       printk("<6>[drm] Changing LVDS panel from (%chsync, %cvsync) to (%chsync, %cvsync)\n",
              __cil_tmp222, __cil_tmp223, __cil_tmp224, __cil_tmp225);
 #line 4598
       temp = temp & 4291821567U;
 #line 4599
       temp = temp | lvds_sync;
       }
     } else {
 
     }
     }
     {
 #line 4601
     i915_write32___4(dev_priv, 397696U, temp);
     }
   } else {
 
   }
 #line 4604
   if ((int )is_dp) {
     {
 #line 4605
     intel_dp_set_m_n(crtc, mode, adjusted_mode);
     }
   } else {
 
   }
   {
 #line 4608
   __cil_tmp226 = pipe + 6149;
 #line 4608
   __cil_tmp227 = __cil_tmp226 * 4;
 #line 4608
   __cil_tmp228 = (u32 )__cil_tmp227;
 #line 4608
   i915_write32___4(dev_priv, __cil_tmp228, dpll);
 #line 4611
   __cil_tmp229 = pipe + 6149;
 #line 4611
   __cil_tmp230 = __cil_tmp229 * 4;
 #line 4611
   __cil_tmp231 = (unsigned long )__cil_tmp230;
 #line 4611
   __cil_tmp232 = dev_priv->regs;
 #line 4611
   __cil_tmp233 = (void const volatile   *)__cil_tmp232;
 #line 4611
   __cil_tmp234 = __cil_tmp233 + __cil_tmp231;
 #line 4611
   readl(__cil_tmp234);
 #line 4612
   __const_udelay(644250UL);
   }
   {
 #line 4614
   __cil_tmp235 = dev->dev_private;
 #line 4614
   __cil_tmp236 = (struct drm_i915_private *)__cil_tmp235;
 #line 4614
   __cil_tmp237 = __cil_tmp236->info;
 #line 4614
   __cil_tmp238 = __cil_tmp237->gen;
 #line 4614
   __cil_tmp239 = (unsigned char )__cil_tmp238;
 #line 4614
   __cil_tmp240 = (unsigned int )__cil_tmp239;
 #line 4614
   if (__cil_tmp240 > 3U) {
 #line 4615
     temp = 0U;
 #line 4616
     if ((int )is_sdvo) {
       {
 #line 4617
       __cil_tmp241 = (struct drm_display_mode  const  *)adjusted_mode;
 #line 4617
       tmp___4 = intel_mode_get_pixel_multiplier(__cil_tmp241);
 #line 4617
       temp = (u32 )tmp___4;
       }
 #line 4618
       if (temp > 1U) {
 #line 4619
         __cil_tmp242 = temp - 1U;
 #line 4619
         temp = __cil_tmp242 << 8;
       } else {
 #line 4621
         temp = 0U;
       }
     } else {
 
     }
     {
 #line 4623
     __cil_tmp243 = pipe + 6151;
 #line 4623
     __cil_tmp244 = __cil_tmp243 * 4;
 #line 4623
     __cil_tmp245 = (u32 )__cil_tmp244;
 #line 4623
     i915_write32___4(dev_priv, __cil_tmp245, temp);
     }
   } else {
     {
 #line 4630
     __cil_tmp246 = pipe + 6149;
 #line 4630
     __cil_tmp247 = __cil_tmp246 * 4;
 #line 4630
     __cil_tmp248 = (u32 )__cil_tmp247;
 #line 4630
     i915_write32___4(dev_priv, __cil_tmp248, dpll);
     }
   }
   }
 #line 4633
   intel_crtc->lowfreq_avail = (bool )0;
 #line 4634
   if ((int )is_lvds) {
 #line 4634
     if ((int )has_reduced_clock) {
 #line 4634
       if (i915_powersave != 0U) {
         {
 #line 4635
         __cil_tmp249 = pipe * 8;
 #line 4635
         __cil_tmp250 = __cil_tmp249 + 24644;
 #line 4635
         __cil_tmp251 = (u32 )__cil_tmp250;
 #line 4635
         i915_write32___4(dev_priv, __cil_tmp251, fp2);
 #line 4636
         intel_crtc->lowfreq_avail = (bool )1;
         }
         {
 #line 4637
         __cil_tmp252 = dev->dev_private;
 #line 4637
         __cil_tmp253 = (struct drm_i915_private *)__cil_tmp252;
 #line 4637
         __cil_tmp254 = __cil_tmp253->info;
 #line 4637
         __cil_tmp255 = (unsigned char *)__cil_tmp254;
 #line 4637
         __cil_tmp256 = __cil_tmp255 + 2UL;
 #line 4637
         __cil_tmp257 = *__cil_tmp256;
 #line 4637
         __cil_tmp258 = (unsigned int )__cil_tmp257;
 #line 4637
         if (__cil_tmp258 != 0U) {
           {
 #line 4638
           drm_ut_debug_printk(4U, "drm", "i9xx_crtc_mode_set", "enabling CxSR downclocking\n");
 #line 4639
           pipeconf = pipeconf | 65536U;
           }
         } else {
 
         }
         }
       } else {
 #line 4634
         goto _L___4;
       }
     } else {
 #line 4634
       goto _L___4;
     }
   } else {
     _L___4: 
     {
 #line 4642
     __cil_tmp259 = pipe * 8;
 #line 4642
     __cil_tmp260 = __cil_tmp259 + 24644;
 #line 4642
     __cil_tmp261 = (u32 )__cil_tmp260;
 #line 4642
     i915_write32___4(dev_priv, __cil_tmp261, fp);
     }
     {
 #line 4643
     __cil_tmp262 = dev->dev_private;
 #line 4643
     __cil_tmp263 = (struct drm_i915_private *)__cil_tmp262;
 #line 4643
     __cil_tmp264 = __cil_tmp263->info;
 #line 4643
     __cil_tmp265 = (unsigned char *)__cil_tmp264;
 #line 4643
     __cil_tmp266 = __cil_tmp265 + 2UL;
 #line 4643
     __cil_tmp267 = *__cil_tmp266;
 #line 4643
     __cil_tmp268 = (unsigned int )__cil_tmp267;
 #line 4643
     if (__cil_tmp268 != 0U) {
       {
 #line 4644
       drm_ut_debug_printk(4U, "drm", "i9xx_crtc_mode_set", "disabling CxSR downclocking\n");
 #line 4645
       pipeconf = pipeconf & 4294901759U;
       }
     } else {
 
     }
     }
   }
   {
 #line 4649
   __cil_tmp269 = adjusted_mode->flags;
 #line 4649
   __cil_tmp270 = __cil_tmp269 & 16U;
 #line 4649
   if (__cil_tmp270 != 0U) {
 #line 4650
     pipeconf = pipeconf | 12582912U;
 #line 4652
     __cil_tmp271 = adjusted_mode->crtc_vdisplay;
 #line 4652
     adjusted_mode->crtc_vdisplay = __cil_tmp271 + -1;
 #line 4653
     __cil_tmp272 = adjusted_mode->crtc_vtotal;
 #line 4653
     adjusted_mode->crtc_vtotal = __cil_tmp272 + -1;
 #line 4654
     __cil_tmp273 = adjusted_mode->crtc_vblank_start;
 #line 4654
     adjusted_mode->crtc_vblank_start = __cil_tmp273 + -1;
 #line 4655
     __cil_tmp274 = adjusted_mode->crtc_vblank_end;
 #line 4655
     adjusted_mode->crtc_vblank_end = __cil_tmp274 + -1;
 #line 4656
     __cil_tmp275 = adjusted_mode->crtc_vsync_end;
 #line 4656
     adjusted_mode->crtc_vsync_end = __cil_tmp275 + -1;
 #line 4657
     __cil_tmp276 = adjusted_mode->crtc_vsync_start;
 #line 4657
     adjusted_mode->crtc_vsync_start = __cil_tmp276 + -1;
   } else {
 #line 4659
     pipeconf = pipeconf & 4282384383U;
   }
   }
   {
 #line 4661
   __cil_tmp277 = pipe + 96;
 #line 4661
   __cil_tmp278 = __cil_tmp277 * 4096;
 #line 4661
   __cil_tmp279 = (u32 )__cil_tmp278;
 #line 4661
   __cil_tmp280 = adjusted_mode->crtc_htotal;
 #line 4661
   __cil_tmp281 = __cil_tmp280 + -1;
 #line 4661
   __cil_tmp282 = __cil_tmp281 << 16;
 #line 4661
   __cil_tmp283 = adjusted_mode->crtc_hdisplay;
 #line 4661
   __cil_tmp284 = __cil_tmp283 + -1;
 #line 4661
   __cil_tmp285 = __cil_tmp284 | __cil_tmp282;
 #line 4661
   __cil_tmp286 = (u32 )__cil_tmp285;
 #line 4661
   i915_write32___4(dev_priv, __cil_tmp279, __cil_tmp286);
 #line 4664
   __cil_tmp287 = pipe * 4096;
 #line 4664
   __cil_tmp288 = __cil_tmp287 + 393220;
 #line 4664
   __cil_tmp289 = (u32 )__cil_tmp288;
 #line 4664
   __cil_tmp290 = adjusted_mode->crtc_hblank_end;
 #line 4664
   __cil_tmp291 = __cil_tmp290 + -1;
 #line 4664
   __cil_tmp292 = __cil_tmp291 << 16;
 #line 4664
   __cil_tmp293 = adjusted_mode->crtc_hblank_start;
 #line 4664
   __cil_tmp294 = __cil_tmp293 + -1;
 #line 4664
   __cil_tmp295 = __cil_tmp294 | __cil_tmp292;
 #line 4664
   __cil_tmp296 = (u32 )__cil_tmp295;
 #line 4664
   i915_write32___4(dev_priv, __cil_tmp289, __cil_tmp296);
 #line 4667
   __cil_tmp297 = pipe * 4096;
 #line 4667
   __cil_tmp298 = __cil_tmp297 + 393224;
 #line 4667
   __cil_tmp299 = (u32 )__cil_tmp298;
 #line 4667
   __cil_tmp300 = adjusted_mode->crtc_hsync_end;
 #line 4667
   __cil_tmp301 = __cil_tmp300 + -1;
 #line 4667
   __cil_tmp302 = __cil_tmp301 << 16;
 #line 4667
   __cil_tmp303 = adjusted_mode->crtc_hsync_start;
 #line 4667
   __cil_tmp304 = __cil_tmp303 + -1;
 #line 4667
   __cil_tmp305 = __cil_tmp304 | __cil_tmp302;
 #line 4667
   __cil_tmp306 = (u32 )__cil_tmp305;
 #line 4667
   i915_write32___4(dev_priv, __cil_tmp299, __cil_tmp306);
 #line 4671
   __cil_tmp307 = pipe * 4096;
 #line 4671
   __cil_tmp308 = __cil_tmp307 + 393228;
 #line 4671
   __cil_tmp309 = (u32 )__cil_tmp308;
 #line 4671
   __cil_tmp310 = adjusted_mode->crtc_vtotal;
 #line 4671
   __cil_tmp311 = __cil_tmp310 + -1;
 #line 4671
   __cil_tmp312 = __cil_tmp311 << 16;
 #line 4671
   __cil_tmp313 = adjusted_mode->crtc_vdisplay;
 #line 4671
   __cil_tmp314 = __cil_tmp313 + -1;
 #line 4671
   __cil_tmp315 = __cil_tmp314 | __cil_tmp312;
 #line 4671
   __cil_tmp316 = (u32 )__cil_tmp315;
 #line 4671
   i915_write32___4(dev_priv, __cil_tmp309, __cil_tmp316);
 #line 4674
   __cil_tmp317 = pipe * 4096;
 #line 4674
   __cil_tmp318 = __cil_tmp317 + 393232;
 #line 4674
   __cil_tmp319 = (u32 )__cil_tmp318;
 #line 4674
   __cil_tmp320 = adjusted_mode->crtc_vblank_end;
 #line 4674
   __cil_tmp321 = __cil_tmp320 + -1;
 #line 4674
   __cil_tmp322 = __cil_tmp321 << 16;
 #line 4674
   __cil_tmp323 = adjusted_mode->crtc_vblank_start;
 #line 4674
   __cil_tmp324 = __cil_tmp323 + -1;
 #line 4674
   __cil_tmp325 = __cil_tmp324 | __cil_tmp322;
 #line 4674
   __cil_tmp326 = (u32 )__cil_tmp325;
 #line 4674
   i915_write32___4(dev_priv, __cil_tmp319, __cil_tmp326);
 #line 4677
   __cil_tmp327 = pipe * 4096;
 #line 4677
   __cil_tmp328 = __cil_tmp327 + 393236;
 #line 4677
   __cil_tmp329 = (u32 )__cil_tmp328;
 #line 4677
   __cil_tmp330 = adjusted_mode->crtc_vsync_end;
 #line 4677
   __cil_tmp331 = __cil_tmp330 + -1;
 #line 4677
   __cil_tmp332 = __cil_tmp331 << 16;
 #line 4677
   __cil_tmp333 = adjusted_mode->crtc_vsync_start;
 #line 4677
   __cil_tmp334 = __cil_tmp333 + -1;
 #line 4677
   __cil_tmp335 = __cil_tmp334 | __cil_tmp332;
 #line 4677
   __cil_tmp336 = (u32 )__cil_tmp335;
 #line 4677
   i915_write32___4(dev_priv, __cil_tmp329, __cil_tmp336);
 #line 4684
   __cil_tmp337 = plane * 4096;
 #line 4684
   __cil_tmp338 = __cil_tmp337 + 459152;
 #line 4684
   __cil_tmp339 = (u32 )__cil_tmp338;
 #line 4684
   __cil_tmp340 = mode->hdisplay;
 #line 4684
  __cil_tmp341 = __cil_tmp340 + -1;
#line 4684
  __cil_tmp342 = mode->vdisplay;
#line 4684
  __cil_tmp343 = __cil_tmp342 + -1;
#line 4684
  __cil_tmp344 = __cil_tmp343 << 16;
#line 4684
  __cil_tmp345 = __cil_tmp344 | __cil_tmp341;
#line 4684
  __cil_tmp346 = (u32 )__cil_tmp345;
#line 4684
  i915_write32___4(dev_priv, __cil_tmp339, __cil_tmp346);
#line 4687
  __cil_tmp347 = plane * 4096;
#line 4687
  __cil_tmp348 = __cil_tmp347 + 459148;
#line 4687
  __cil_tmp349 = (u32 )__cil_tmp348;
#line 4687
  i915_write32___4(dev_priv, __cil_tmp349, 0U);
#line 4688
  __cil_tmp350 = pipe * 4096;
#line 4688
  __cil_tmp351 = __cil_tmp350 + 393244;
#line 4688
  __cil_tmp352 = (u32 )__cil_tmp351;
#line 4688
  __cil_tmp353 = mode->vdisplay;
#line 4688
  __cil_tmp354 = __cil_tmp353 + -1;
#line 4688
  __cil_tmp355 = mode->hdisplay;
#line 4688
  __cil_tmp356 = __cil_tmp355 + -1;
#line 4688
  __cil_tmp357 = __cil_tmp356 << 16;
#line 4688
  __cil_tmp358 = __cil_tmp357 | __cil_tmp354;
#line 4688
  __cil_tmp359 = (u32 )__cil_tmp358;
#line 4688
  i915_write32___4(dev_priv, __cil_tmp352, __cil_tmp359);
#line 4691
  __cil_tmp360 = pipe * 4096;
#line 4691
  __cil_tmp361 = __cil_tmp360 + 458760;
#line 4691
  __cil_tmp362 = (u32 )__cil_tmp361;
#line 4691
  i915_write32___4(dev_priv, __cil_tmp362, pipeconf);
#line 4692
  __cil_tmp363 = pipe * 4096;
#line 4692
  __cil_tmp364 = __cil_tmp363 + 458760;
#line 4692
  __cil_tmp365 = (unsigned long )__cil_tmp364;
#line 4692
  __cil_tmp366 = dev_priv->regs;
#line 4692
  __cil_tmp367 = (void const volatile   *)__cil_tmp366;
#line 4692
  __cil_tmp368 = __cil_tmp367 + __cil_tmp365;
#line 4692
  readl(__cil_tmp368);
#line 4693
  __cil_tmp369 = (enum pipe )pipe;
#line 4693
  __cil_tmp370 = (bool )0;
#line 4693
  intel_enable_pipe(dev_priv, __cil_tmp369, __cil_tmp370);
#line 4695
  intel_wait_for_vblank(dev, pipe);
#line 4697
  __cil_tmp371 = plane * 4096;
#line 4697
  __cil_tmp372 = __cil_tmp371 + 459136;
#line 4697
  __cil_tmp373 = (u32 )__cil_tmp372;
#line 4697
  i915_write32___4(dev_priv, __cil_tmp373, dspcntr);
#line 4698
  __cil_tmp374 = plane * 4096;
#line 4698
  __cil_tmp375 = __cil_tmp374 + 459136;
#line 4698
  __cil_tmp376 = (unsigned long )__cil_tmp375;
#line 4698
  __cil_tmp377 = dev_priv->regs;
#line 4698
  __cil_tmp378 = (void const volatile   *)__cil_tmp377;
#line 4698
  __cil_tmp379 = __cil_tmp378 + __cil_tmp376;
#line 4698
  readl(__cil_tmp379);
#line 4699
  __cil_tmp380 = (enum plane )plane;
#line 4699
  __cil_tmp381 = (enum pipe )pipe;
#line 4699
  intel_enable_plane(dev_priv, __cil_tmp380, __cil_tmp381);
#line 4701
  ret = intel_pipe_set_base(crtc, x, y, old_fb);
#line 4703
  intel_update_watermarks(dev);
  }
#line 4705
  return (ret);
}
}
#line 4708 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int ironlake_crtc_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode ,
                                  struct drm_display_mode *adjusted_mode , int x ,
                                  int y , struct drm_framebuffer *old_fb ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  int plane ;
  int refclk ;
  int num_connectors ;
  intel_clock_t clock ;
  intel_clock_t reduced_clock ;
  u32 dpll ;
  u32 fp ;
  u32 fp2 ;
  u32 dspcntr ;
  u32 pipeconf ;
  bool ok ;
  bool has_reduced_clock ;
  bool is_sdvo ;
  bool is_crt ;
  bool is_lvds ;
  bool is_tv ;
  bool is_dp ;
  struct intel_encoder *has_edp_encoder ;
  struct drm_mode_config *mode_config ;
  struct intel_encoder *encoder ;
  intel_limit_t const   *limit ;
  int ret ;
  struct fdi_m_n m_n ;
  u32 temp ;
  u32 lvds_sync ;
  int target_clock ;
  int pixel_multiplier ;
  int lane ;
  int link_bw ;
  int bpp ;
  int factor ;
  struct list_head  const  *__mptr___0 ;
  struct list_head  const  *__mptr___1 ;
  bool tmp ;
  bool tmp___0 ;
  bool tmp___1 ;
  u32 tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  u32 tmp___5 ;
  u32 bps ;
  bool tmp___6 ;
  bool tmp___7 ;
  bool tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  bool tmp___11 ;
  u32 tmp___12 ;
  int pixel_multiplier___0 ;
  int tmp___13 ;
  bool tmp___14 ;
  bool tmp___15 ;
  int tmp___16 ;
  bool tmp___17 ;
  char flags[2U] ;
  bool tmp___18 ;
  bool tmp___19 ;
  bool tmp___20 ;
  int tmp___21 ;
  void *__cil_tmp71 ;
  enum pipe __cil_tmp72 ;
  enum plane __cil_tmp73 ;
  struct list_head *__cil_tmp74 ;
  struct intel_encoder *__cil_tmp75 ;
  unsigned long __cil_tmp76 ;
  struct drm_crtc *__cil_tmp77 ;
  unsigned long __cil_tmp78 ;
  int __cil_tmp79 ;
  int __cil_tmp80 ;
  int __cil_tmp81 ;
  int __cil_tmp82 ;
  int __cil_tmp83 ;
  int __cil_tmp84 ;
  int __cil_tmp85 ;
  bool __cil_tmp86 ;
  struct list_head *__cil_tmp87 ;
  struct intel_encoder *__cil_tmp88 ;
  struct list_head *__cil_tmp89 ;
  unsigned long __cil_tmp90 ;
  struct list_head *__cil_tmp91 ;
  unsigned long __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  struct intel_encoder *__cil_tmp95 ;
  unsigned long __cil_tmp96 ;
  unsigned long __cil_tmp97 ;
  struct drm_encoder *__cil_tmp98 ;
  bool (*__cil_tmp99)(intel_limit_t const   * , struct drm_crtc * , int  , int  ,
                      intel_clock_t * ) ;
  int __cil_tmp100 ;
  bool __cil_tmp101 ;
  bool __cil_tmp102 ;
  bool (*__cil_tmp103)(intel_limit_t const   * , struct drm_crtc * , int  , int  ,
                       intel_clock_t * ) ;
  int __cil_tmp104 ;
  int __cil_tmp105 ;
  int __cil_tmp106 ;
  int __cil_tmp107 ;
  int __cil_tmp108 ;
  struct drm_display_mode  const  *__cil_tmp109 ;
  struct intel_encoder *__cil_tmp110 ;
  unsigned long __cil_tmp111 ;
  unsigned long __cil_tmp112 ;
  struct drm_encoder *__cil_tmp113 ;
  struct drm_encoder *__cil_tmp114 ;
  u32 __cil_tmp115 ;
  u32 __cil_tmp116 ;
  int __cil_tmp117 ;
  int __cil_tmp118 ;
  u32 __cil_tmp119 ;
  unsigned int __cil_tmp120 ;
  struct intel_encoder *__cil_tmp121 ;
  unsigned long __cil_tmp122 ;
  unsigned long __cil_tmp123 ;
  int __cil_tmp124 ;
  int __cil_tmp125 ;
  int __cil_tmp126 ;
  int __cil_tmp127 ;
  int __cil_tmp128 ;
  int __cil_tmp129 ;
  int __cil_tmp130 ;
  int __cil_tmp131 ;
  int __cil_tmp132 ;
  int __cil_tmp133 ;
  u32 __cil_tmp134 ;
  unsigned int __cil_tmp135 ;
  int __cil_tmp136 ;
  unsigned int __cil_tmp137 ;
  int __cil_tmp138 ;
  unsigned int __cil_tmp139 ;
  int __cil_tmp140 ;
  unsigned int __cil_tmp141 ;
  int __cil_tmp142 ;
  int __cil_tmp143 ;
  int __cil_tmp144 ;
  int __cil_tmp145 ;
  int __cil_tmp146 ;
  u32 __cil_tmp147 ;
  u32 __cil_tmp148 ;
  u32 __cil_tmp149 ;
  void *__cil_tmp150 ;
  void const volatile   *__cil_tmp151 ;
  void const volatile   *__cil_tmp152 ;
  struct intel_encoder *__cil_tmp153 ;
  unsigned long __cil_tmp154 ;
  unsigned long __cil_tmp155 ;
  void *__cil_tmp156 ;
  void const volatile   *__cil_tmp157 ;
  void const volatile   *__cil_tmp158 ;
  struct drm_encoder *__cil_tmp159 ;
  void *__cil_tmp160 ;
  void const volatile   *__cil_tmp161 ;
  void const volatile   *__cil_tmp162 ;
  int __cil_tmp163 ;
  int __cil_tmp164 ;
  int __cil_tmp165 ;
  int __cil_tmp166 ;
  int __cil_tmp167 ;
  int __cil_tmp168 ;
  int __cil_tmp169 ;
  int __cil_tmp170 ;
  int __cil_tmp171 ;
  unsigned int __cil_tmp172 ;
  int __cil_tmp173 ;
  struct drm_display_mode  const  *__cil_tmp174 ;
  int __cil_tmp175 ;
  int __cil_tmp176 ;
  u32 __cil_tmp177 ;
  struct drm_encoder *__cil_tmp178 ;
  int __cil_tmp179 ;
  int __cil_tmp180 ;
  int __cil_tmp181 ;
  u32 __cil_tmp182 ;
  int __cil_tmp183 ;
  int __cil_tmp184 ;
  u32 __cil_tmp185 ;
  int __cil_tmp186 ;
  int __cil_tmp187 ;
  u32 __cil_tmp188 ;
  struct intel_encoder *__cil_tmp189 ;
  unsigned long __cil_tmp190 ;
  unsigned long __cil_tmp191 ;
  int __cil_tmp192 ;
  int __cil_tmp193 ;
  u32 __cil_tmp194 ;
  int __cil_tmp195 ;
  int __cil_tmp196 ;
  u32 __cil_tmp197 ;
  unsigned int __cil_tmp198 ;
  int __cil_tmp199 ;
  int __cil_tmp200 ;
  unsigned long __cil_tmp201 ;
  void *__cil_tmp202 ;
  void const volatile   *__cil_tmp203 ;
  void const volatile   *__cil_tmp204 ;
  struct drm_encoder *__cil_tmp205 ;
  int __cil_tmp206 ;
  int __cil_tmp207 ;
  u32 __cil_tmp208 ;
  int __cil_tmp209 ;
  int __cil_tmp210 ;
  u32 __cil_tmp211 ;
  unsigned int __cil_tmp212 ;
  int __cil_tmp213 ;
  int __cil_tmp214 ;
  unsigned long __cil_tmp215 ;
  void *__cil_tmp216 ;
  void const volatile   *__cil_tmp217 ;
  void const volatile   *__cil_tmp218 ;
  void *__cil_tmp219 ;
  struct drm_i915_private *__cil_tmp220 ;
  enum intel_pch __cil_tmp221 ;
  unsigned int __cil_tmp222 ;
  void *__cil_tmp223 ;
  void const volatile   *__cil_tmp224 ;
  void const volatile   *__cil_tmp225 ;
  void *__cil_tmp226 ;
  struct drm_i915_private *__cil_tmp227 ;
  enum intel_pch __cil_tmp228 ;
  unsigned int __cil_tmp229 ;
  void *__cil_tmp230 ;
  struct drm_i915_private *__cil_tmp231 ;
  enum intel_pch __cil_tmp232 ;
  unsigned int __cil_tmp233 ;
  unsigned int __cil_tmp234 ;
  unsigned int __cil_tmp235 ;
  unsigned int __cil_tmp236 ;
  unsigned int __cil_tmp237 ;
  unsigned int __cil_tmp238 ;
  unsigned int __cil_tmp239 ;
  int __cil_tmp240 ;
  int __cil_tmp241 ;
  int __cil_tmp242 ;
  int __cil_tmp243 ;
  unsigned char *__cil_tmp244 ;
  unsigned char *__cil_tmp245 ;
  unsigned char __cil_tmp246 ;
  unsigned int __cil_tmp247 ;
  struct intel_encoder *__cil_tmp248 ;
  unsigned long __cil_tmp249 ;
  unsigned long __cil_tmp250 ;
  struct drm_encoder *__cil_tmp251 ;
  int __cil_tmp252 ;
  int __cil_tmp253 ;
  u32 __cil_tmp254 ;
  int __cil_tmp255 ;
  int __cil_tmp256 ;
  u32 __cil_tmp257 ;
  int __cil_tmp258 ;
  int __cil_tmp259 ;
  u32 __cil_tmp260 ;
  int __cil_tmp261 ;
  int __cil_tmp262 ;
  u32 __cil_tmp263 ;
  struct intel_encoder *__cil_tmp264 ;
  unsigned long __cil_tmp265 ;
  unsigned long __cil_tmp266 ;
  int __cil_tmp267 ;
  int __cil_tmp268 ;
  u32 __cil_tmp269 ;
  int __cil_tmp270 ;
  int __cil_tmp271 ;
  unsigned long __cil_tmp272 ;
  void *__cil_tmp273 ;
  void const volatile   *__cil_tmp274 ;
  void const volatile   *__cil_tmp275 ;
  int __cil_tmp276 ;
  int __cil_tmp277 ;
  u32 __cil_tmp278 ;
  struct drm_encoder *__cil_tmp279 ;
  int __cil_tmp280 ;
  int __cil_tmp281 ;
  u32 __cil_tmp282 ;
  int __cil_tmp283 ;
  int __cil_tmp284 ;
  unsigned long __cil_tmp285 ;
  void *__cil_tmp286 ;
  void const volatile   *__cil_tmp287 ;
  void const volatile   *__cil_tmp288 ;
  int __cil_tmp289 ;
  int __cil_tmp290 ;
  u32 __cil_tmp291 ;
  int __cil_tmp292 ;
  int __cil_tmp293 ;
  u32 __cil_tmp294 ;
  void *__cil_tmp295 ;
  struct drm_i915_private *__cil_tmp296 ;
  struct intel_device_info  const  *__cil_tmp297 ;
  unsigned char *__cil_tmp298 ;
  unsigned char *__cil_tmp299 ;
  unsigned char __cil_tmp300 ;
  unsigned int __cil_tmp301 ;
  int __cil_tmp302 ;
  int __cil_tmp303 ;
  u32 __cil_tmp304 ;
  void *__cil_tmp305 ;
  struct drm_i915_private *__cil_tmp306 ;
  struct intel_device_info  const  *__cil_tmp307 ;
  unsigned char *__cil_tmp308 ;
  unsigned char *__cil_tmp309 ;
  unsigned char __cil_tmp310 ;
  unsigned int __cil_tmp311 ;
  unsigned int __cil_tmp312 ;
  unsigned int __cil_tmp313 ;
  int __cil_tmp314 ;
  int __cil_tmp315 ;
  int __cil_tmp316 ;
  int __cil_tmp317 ;
  int __cil_tmp318 ;
  int __cil_tmp319 ;
  int __cil_tmp320 ;
  int __cil_tmp321 ;
  u32 __cil_tmp322 ;
  int __cil_tmp323 ;
  int __cil_tmp324 ;
  int __cil_tmp325 ;
  int __cil_tmp326 ;
  int __cil_tmp327 ;
  int __cil_tmp328 ;
  u32 __cil_tmp329 ;
  int __cil_tmp330 ;
  int __cil_tmp331 ;
  u32 __cil_tmp332 ;
  int __cil_tmp333 ;
  int __cil_tmp334 ;
  int __cil_tmp335 ;
  int __cil_tmp336 ;
  int __cil_tmp337 ;
  int __cil_tmp338 ;
  u32 __cil_tmp339 ;
  int __cil_tmp340 ;
  int __cil_tmp341 ;
  u32 __cil_tmp342 ;
  int __cil_tmp343 ;
  int __cil_tmp344 ;
  int __cil_tmp345 ;
  int __cil_tmp346 ;
  int __cil_tmp347 ;
  int __cil_tmp348 ;
  u32 __cil_tmp349 ;
  int __cil_tmp350 ;
  int __cil_tmp351 ;
  u32 __cil_tmp352 ;
  int __cil_tmp353 ;
  int __cil_tmp354 ;
  int __cil_tmp355 ;
  int __cil_tmp356 ;
  int __cil_tmp357 ;
  int __cil_tmp358 ;
  u32 __cil_tmp359 ;
  int __cil_tmp360 ;
  int __cil_tmp361 ;
  u32 __cil_tmp362 ;
  int __cil_tmp363 ;
  int __cil_tmp364 ;
  int __cil_tmp365 ;
  int __cil_tmp366 ;
  int __cil_tmp367 ;
  int __cil_tmp368 ;
  u32 __cil_tmp369 ;
  int __cil_tmp370 ;
  int __cil_tmp371 ;
  u32 __cil_tmp372 ;
  int __cil_tmp373 ;
  int __cil_tmp374 ;
  int __cil_tmp375 ;
  int __cil_tmp376 ;
  int __cil_tmp377 ;
  int __cil_tmp378 ;
  u32 __cil_tmp379 ;
  int __cil_tmp380 ;
  int __cil_tmp381 ;
  u32 __cil_tmp382 ;
  int __cil_tmp383 ;
  int __cil_tmp384 ;
  int __cil_tmp385 ;
  int __cil_tmp386 ;
  int __cil_tmp387 ;
  int __cil_tmp388 ;
  u32 __cil_tmp389 ;
  int __cil_tmp390 ;
  int __cil_tmp391 ;
  u32 __cil_tmp392 ;
  u32 __cil_tmp393 ;
  u32 __cil_tmp394 ;
  unsigned int __cil_tmp395 ;
  int __cil_tmp396 ;
  int __cil_tmp397 ;
  u32 __cil_tmp398 ;
  int __cil_tmp399 ;
  int __cil_tmp400 ;
  u32 __cil_tmp401 ;
  int __cil_tmp402 ;
  int __cil_tmp403 ;
  u32 __cil_tmp404 ;
  struct intel_encoder *__cil_tmp405 ;
  unsigned long __cil_tmp406 ;
  unsigned long __cil_tmp407 ;
  struct drm_encoder *__cil_tmp408 ;
  int __cil_tmp409 ;
  int __cil_tmp410 ;
  int __cil_tmp411 ;
  u32 __cil_tmp412 ;
  int __cil_tmp413 ;
  int __cil_tmp414 ;
  unsigned long __cil_tmp415 ;
  void *__cil_tmp416 ;
  void const volatile   *__cil_tmp417 ;
  void const volatile   *__cil_tmp418 ;
  void *__cil_tmp419 ;
  struct drm_i915_private *__cil_tmp420 ;
  struct intel_device_info  const  *__cil_tmp421 ;
  u8 __cil_tmp422 ;
  unsigned char __cil_tmp423 ;
  unsigned int __cil_tmp424 ;
  unsigned int __cil_tmp425 ;
  int __cil_tmp426 ;
  int __cil_tmp427 ;
  u32 __cil_tmp428 ;
  int __cil_tmp429 ;
  int __cil_tmp430 ;
  unsigned long __cil_tmp431 ;
  void *__cil_tmp432 ;
  void const volatile   *__cil_tmp433 ;
  void const volatile   *__cil_tmp434 ;

  {
#line 4714
  dev = crtc->dev;
#line 4715
  __cil_tmp71 = dev->dev_private;
#line 4715
  dev_priv = (struct drm_i915_private *)__cil_tmp71;
#line 4716
  __mptr = (struct drm_crtc  const  *)crtc;
#line 4716
  intel_crtc = (struct intel_crtc *)__mptr;
#line 4717
  __cil_tmp72 = intel_crtc->pipe;
#line 4717
  pipe = (int )__cil_tmp72;
#line 4718
  __cil_tmp73 = intel_crtc->plane;
#line 4718
  plane = (int )__cil_tmp73;
#line 4719
  num_connectors = 0;
#line 4721
  fp = 0U;
#line 4721
  fp2 = 0U;
#line 4722
  has_reduced_clock = (bool )0;
#line 4722
  is_sdvo = (bool )0;
#line 4723
  is_crt = (bool )0;
#line 4723
  is_lvds = (bool )0;
#line 4723
  is_tv = (bool )0;
#line 4723
  is_dp = (bool )0;
#line 4724
  has_edp_encoder = (struct intel_encoder *)0;
#line 4725
  mode_config = & dev->mode_config;
#line 4729
  m_n.tu = 0U;
#line 4729
  m_n.gmch_m = 0U;
#line 4729
  m_n.gmch_n = 0U;
#line 4729
  m_n.link_m = 0U;
#line 4729
  m_n.link_n = 0U;
#line 4731
  lvds_sync = 0U;
#line 4734
  __cil_tmp74 = mode_config->encoder_list.next;
#line 4734
  __mptr___0 = (struct list_head  const  *)__cil_tmp74;
#line 4734
  __cil_tmp75 = (struct intel_encoder *)__mptr___0;
#line 4734
  encoder = __cil_tmp75 + 1152921504606846968UL;
#line 4734
  goto ldv_39544;
  ldv_39543: ;
  {
#line 4735
  __cil_tmp76 = (unsigned long )crtc;
#line 4735
  __cil_tmp77 = encoder->base.crtc;
#line 4735
  __cil_tmp78 = (unsigned long )__cil_tmp77;
#line 4735
  if (__cil_tmp78 != __cil_tmp76) {
#line 4736
    goto ldv_39534;
  } else {

  }
  }
  {
#line 4739
  __cil_tmp79 = encoder->type;
#line 4739
  if (__cil_tmp79 == 4) {
#line 4739
    goto case_4;
  } else {
    {
#line 4742
    __cil_tmp80 = encoder->type;
#line 4742
    if (__cil_tmp80 == 3) {
#line 4742
      goto case_3;
    } else {
      {
#line 4743
      __cil_tmp81 = encoder->type;
#line 4743
      if (__cil_tmp81 == 6) {
#line 4743
        goto case_6;
      } else {
        {
#line 4748
        __cil_tmp82 = encoder->type;
#line 4748
        if (__cil_tmp82 == 5) {
#line 4748
          goto case_5;
        } else {
          {
#line 4751
          __cil_tmp83 = encoder->type;
#line 4751
          if (__cil_tmp83 == 1) {
#line 4751
            goto case_1;
          } else {
            {
#line 4754
            __cil_tmp84 = encoder->type;
#line 4754
            if (__cil_tmp84 == 7) {
#line 4754
              goto case_7;
            } else {
              {
#line 4757
              __cil_tmp85 = encoder->type;
#line 4757
              if (__cil_tmp85 == 8) {
#line 4757
                goto case_8;
              } else
#line 4738
              if (0) {
                case_4: 
#line 4740
                is_lvds = (bool )1;
#line 4741
                goto ldv_39536;
                case_3: ;
                case_6: 
#line 4744
                is_sdvo = (bool )1;
                {
#line 4745
                __cil_tmp86 = encoder->needs_tv_clock;
#line 4745
                if ((int )__cil_tmp86) {
#line 4746
                  is_tv = (bool )1;
                } else {

                }
                }
#line 4747
                goto ldv_39536;
                case_5: 
#line 4749
                is_tv = (bool )1;
#line 4750
                goto ldv_39536;
                case_1: 
#line 4752
                is_crt = (bool )1;
#line 4753
                goto ldv_39536;
                case_7: 
#line 4755
                is_dp = (bool )1;
#line 4756
                goto ldv_39536;
                case_8: 
#line 4758
                has_edp_encoder = encoder;
#line 4759
                goto ldv_39536;
              } else {

              }
              }
            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_39536: 
#line 4762
  num_connectors = num_connectors + 1;
  ldv_39534: 
#line 4734
  __cil_tmp87 = encoder->base.head.next;
#line 4734
  __mptr___1 = (struct list_head  const  *)__cil_tmp87;
#line 4734
  __cil_tmp88 = (struct intel_encoder *)__mptr___1;
#line 4734
  encoder = __cil_tmp88 + 1152921504606846968UL;
  ldv_39544: ;
  {
#line 4734
  __cil_tmp89 = & mode_config->encoder_list;
#line 4734
  __cil_tmp90 = (unsigned long )__cil_tmp89;
#line 4734
  __cil_tmp91 = & encoder->base.head;
#line 4734
  __cil_tmp92 = (unsigned long )__cil_tmp91;
#line 4734
  if (__cil_tmp92 != __cil_tmp90) {
#line 4735
    goto ldv_39543;
  } else {
#line 4737
    goto ldv_39545;
  }
  }
  ldv_39545: ;
#line 4765
  if ((int )is_lvds) {
    {
#line 4765
    tmp___0 = intel_panel_use_ssc(dev_priv);
    }
#line 4765
    if ((int )tmp___0) {
#line 4765
      if (num_connectors <= 1) {
        {
#line 4766
        __cil_tmp93 = dev_priv->lvds_ssc_freq;
#line 4766
        refclk = __cil_tmp93 * 1000;
#line 4767
        __cil_tmp94 = refclk / 1000;
#line 4767
        drm_ut_debug_printk(4U, "drm", "ironlake_crtc_mode_set", "using SSC reference clock of %d MHz\n",
                            __cil_tmp94);
        }
      } else {
#line 4765
        goto _L___0;
      }
    } else {
#line 4765
      goto _L___0;
    }
  } else {
    _L___0: 
#line 4770
    refclk = 96000;
    {
#line 4771
    __cil_tmp95 = (struct intel_encoder *)0;
#line 4771
    __cil_tmp96 = (unsigned long )__cil_tmp95;
#line 4771
    __cil_tmp97 = (unsigned long )has_edp_encoder;
#line 4771
    if (__cil_tmp97 == __cil_tmp96) {
#line 4773
      refclk = 120000;
    } else {
      {
#line 4771
      __cil_tmp98 = & has_edp_encoder->base;
#line 4771
      tmp = intel_encoder_is_pch_edp(__cil_tmp98);
      }
#line 4771
      if ((int )tmp) {
#line 4773
        refclk = 120000;
      } else {

      }
    }
    }
  }
  {
#line 4781
  limit = intel_limit(crtc, refclk);
#line 4782
  __cil_tmp99 = limit->find_pll;
#line 4782
  __cil_tmp100 = adjusted_mode->clock;
#line 4782
  ok = (*__cil_tmp99)(limit, crtc, __cil_tmp100, refclk, & clock);
  }
#line 4783
  if (! ok) {
    {
#line 4784
    drm_err("ironlake_crtc_mode_set", "Couldn\'t find PLL settings for mode!\n");
    }
#line 4785
    return (-22);
  } else {

  }
  {
#line 4789
  __cil_tmp101 = (bool )1;
#line 4789
  intel_crtc_update_cursor(crtc, __cil_tmp101);
  }
#line 4791
  if ((int )is_lvds) {
    {
#line 4791
    __cil_tmp102 = dev_priv->lvds_downclock_avail;
#line 4791
    if ((int )__cil_tmp102) {
      {
#line 4792
      __cil_tmp103 = limit->find_pll;
#line 4792
      __cil_tmp104 = dev_priv->lvds_downclock;
#line 4792
      has_reduced_clock = (*__cil_tmp103)(limit, crtc, __cil_tmp104, refclk, & reduced_clock);
      }
#line 4796
      if ((int )has_reduced_clock) {
#line 4796
        if (clock.p != reduced_clock.p) {
          {
#line 4803
          drm_ut_debug_printk(4U, "drm", "ironlake_crtc_mode_set", "Different P is found for LVDS clock/downclock\n");
#line 4805
          has_reduced_clock = (bool )0;
          }
        } else {

        }
      } else {

      }
    } else {

    }
    }
  } else {

  }
#line 4810
  if ((int )is_sdvo) {
#line 4810
    if ((int )is_tv) {
      {
#line 4811
      __cil_tmp105 = adjusted_mode->clock;
#line 4811
      if (__cil_tmp105 > 99999) {
        {
#line 4811
        __cil_tmp106 = adjusted_mode->clock;
#line 4811
        if (__cil_tmp106 <= 140499) {
#line 4813
          clock.p1 = 2;
#line 4814
          clock.p2 = 10;
#line 4815
          clock.n = 3;
#line 4816
          clock.m1 = 16;
#line 4817
          clock.m2 = 8;
        } else {
#line 4811
          goto _L___1;
        }
        }
      } else {
        _L___1: 
        {
#line 4818
        __cil_tmp107 = adjusted_mode->clock;
#line 4818
        if (__cil_tmp107 > 140499) {
          {
#line 4818
          __cil_tmp108 = adjusted_mode->clock;
#line 4818
          if (__cil_tmp108 <= 200000) {
#line 4820
            clock.p1 = 1;
#line 4821
            clock.p2 = 10;
#line 4822
            clock.n = 6;
#line 4823
            clock.m1 = 12;
#line 4824
            clock.m2 = 8;
          } else {

          }
          }
        } else {

        }
        }
      }
      }
    } else {

    }
  } else {

  }
  {
#line 4829
  __cil_tmp109 = (struct drm_display_mode  const  *)adjusted_mode;
#line 4829
  pixel_multiplier = intel_mode_get_pixel_multiplier(__cil_tmp109);
#line 4830
  lane = 0;
  }
  {
#line 4833
  __cil_tmp110 = (struct intel_encoder *)0;
#line 4833
  __cil_tmp111 = (unsigned long )__cil_tmp110;
#line 4833
  __cil_tmp112 = (unsigned long )has_edp_encoder;
#line 4833
  if (__cil_tmp112 != __cil_tmp111) {
    {
#line 4833
    __cil_tmp113 = & has_edp_encoder->base;
#line 4833
    tmp___3 = intel_encoder_is_pch_edp(__cil_tmp113);
    }
#line 4833
    if (tmp___3) {
#line 4833
      tmp___4 = 0;
    } else {
#line 4833
      tmp___4 = 1;
    }
#line 4833
    if (tmp___4) {
      {
#line 4835
      target_clock = mode->clock;
#line 4836
      intel_edp_link_config(has_edp_encoder, & lane, & link_bw);
      }
    } else {
#line 4833
      goto _L___2;
    }
  } else {
    _L___2: 
#line 4841
    if ((int )is_dp) {
#line 4842
      target_clock = mode->clock;
    } else {
      {
#line 4841
      __cil_tmp114 = & has_edp_encoder->base;
#line 4841
      tmp___1 = intel_encoder_is_pch_edp(__cil_tmp114);
      }
#line 4841
      if ((int )tmp___1) {
#line 4842
        target_clock = mode->clock;
      } else {
#line 4844
        target_clock = adjusted_mode->clock;
      }
    }
    {
#line 4853
    tmp___2 = intel_fdi_link_freq(dev);
#line 4853
    __cil_tmp115 = tmp___2 * 100000000U;
#line 4853
    __cil_tmp116 = __cil_tmp115 / 10000U;
#line 4853
    link_bw = (int )__cil_tmp116;
    }
  }
  }
  {
#line 4857
  __cil_tmp117 = pipe * 4096;
#line 4857
  __cil_tmp118 = __cil_tmp117 + 458760;
#line 4857
  __cil_tmp119 = (u32 )__cil_tmp118;
#line 4857
  temp = i915_read32___6(dev_priv, __cil_tmp119);
#line 4858
  temp = temp & 4294967071U;
  }
#line 4859
  if ((int )is_lvds) {
    {
#line 4861
    tmp___5 = i915_read32___6(dev_priv, 921984U);
    }
    {
#line 4861
    __cil_tmp120 = tmp___5 & 192U;
#line 4861
    if (__cil_tmp120 == 192U) {
#line 4862
      temp = temp;
    } else {
#line 4864
      temp = temp | 64U;
    }
    }
  } else {
    {
#line 4865
    __cil_tmp121 = (struct intel_encoder *)0;
#line 4865
    __cil_tmp122 = (unsigned long )__cil_tmp121;
#line 4865
    __cil_tmp123 = (unsigned long )has_edp_encoder;
#line 4865
    if (__cil_tmp123 != __cil_tmp122) {
      {
#line 4867
      __cil_tmp124 = dev_priv->edp.bpp;
#line 4867
      __cil_tmp125 = __cil_tmp124 / 3;
#line 4867
      if (__cil_tmp125 == 8) {
#line 4867
        goto case_8___0;
      } else {
        {
#line 4870
        __cil_tmp126 = dev_priv->edp.bpp;
#line 4870
        __cil_tmp127 = __cil_tmp126 / 3;
#line 4870
        if (__cil_tmp127 == 10) {
#line 4870
          goto case_10;
        } else {
          {
#line 4873
          __cil_tmp128 = dev_priv->edp.bpp;
#line 4873
          __cil_tmp129 = __cil_tmp128 / 3;
#line 4873
          if (__cil_tmp129 == 6) {
#line 4873
            goto case_6___0;
          } else {
            {
#line 4876
            __cil_tmp130 = dev_priv->edp.bpp;
#line 4876
            __cil_tmp131 = __cil_tmp130 / 3;
#line 4876
            if (__cil_tmp131 == 12) {
#line 4876
              goto case_12;
            } else
#line 4866
            if (0) {
              case_8___0: 
#line 4868
              temp = temp;
#line 4869
              goto ldv_39548;
              case_10: 
#line 4871
              temp = temp | 32U;
#line 4872
              goto ldv_39548;
              case_6___0: 
#line 4874
              temp = temp | 64U;
#line 4875
              goto ldv_39548;
              case_12: 
#line 4877
              temp = temp | 96U;
#line 4878
              goto ldv_39548;
            } else {

            }
            }
          }
          }
        }
        }
      }
      }
      ldv_39548: ;
    } else {
#line 4881
      temp = temp;
    }
    }
  }
  {
#line 4882
  __cil_tmp132 = pipe * 4096;
#line 4882
  __cil_tmp133 = __cil_tmp132 + 458760;
#line 4882
  __cil_tmp134 = (u32 )__cil_tmp133;
#line 4882
  i915_write32___4(dev_priv, __cil_tmp134, temp);
  }
  {
#line 4885
  __cil_tmp135 = temp & 224U;
#line 4885
  __cil_tmp136 = (int )__cil_tmp135;
#line 4885
  if (__cil_tmp136 == 0) {
#line 4885
    goto case_0;
  } else {
    {
#line 4888
    __cil_tmp137 = temp & 224U;
#line 4888
    __cil_tmp138 = (int )__cil_tmp137;
#line 4888
    if (__cil_tmp138 == 32) {
#line 4888
      goto case_32;
    } else {
      {
#line 4891
      __cil_tmp139 = temp & 224U;
#line 4891
      __cil_tmp140 = (int )__cil_tmp139;
#line 4891
      if (__cil_tmp140 == 64) {
#line 4891
        goto case_64;
      } else {
        {
#line 4894
        __cil_tmp141 = temp & 224U;
#line 4894
        __cil_tmp142 = (int )__cil_tmp141;
#line 4894
        if (__cil_tmp142 == 96) {
#line 4894
          goto case_96;
        } else {
#line 4897
          goto switch_default;
#line 4884
          if (0) {
            case_0: 
#line 4886
            bpp = 24;
#line 4887
            goto ldv_39553;
            case_32: 
#line 4889
            bpp = 30;
#line 4890
            goto ldv_39553;
            case_64: 
#line 4892
            bpp = 18;
#line 4893
            goto ldv_39553;
            case_96: 
#line 4895
            bpp = 36;
#line 4896
            goto ldv_39553;
            switch_default: 
            {
#line 4898
            drm_err("ironlake_crtc_mode_set", "unknown pipe bpc value\n");
#line 4899
            bpp = 24;
            }
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_39553: ;
#line 4902
  if (lane == 0) {
#line 4908
    __cil_tmp143 = target_clock * bpp;
#line 4908
    __cil_tmp144 = __cil_tmp143 * 21;
#line 4908
    __cil_tmp145 = __cil_tmp144 / 20;
#line 4908
    bps = (u32 )__cil_tmp145;
#line 4909
    __cil_tmp146 = link_bw * 8;
#line 4909
    __cil_tmp147 = (u32 )__cil_tmp146;
#line 4909
    __cil_tmp148 = bps / __cil_tmp147;
#line 4909
    __cil_tmp149 = __cil_tmp148 + 1U;
#line 4909
    lane = (int )__cil_tmp149;
  } else {

  }
#line 4912
  intel_crtc->fdi_lanes = lane;
#line 4914
  if (pixel_multiplier > 1) {
#line 4915
    link_bw = link_bw * pixel_multiplier;
  } else {

  }
  {
#line 4916
  ironlake_compute_m_n(bpp, lane, target_clock, link_bw, & m_n);
#line 4923
  temp = i915_read32___6(dev_priv, 811520U);
#line 4925
  temp = temp & 4294965759U;
#line 4926
  temp = temp | 1024U;
#line 4927
  temp = temp & 4294961151U;
#line 4928
  temp = temp | 4096U;
#line 4929
  i915_write32___4(dev_priv, 811520U, temp);
#line 4931
  __cil_tmp150 = dev_priv->regs;
#line 4931
  __cil_tmp151 = (void const volatile   *)__cil_tmp150;
#line 4931
  __cil_tmp152 = __cil_tmp151 + 811520U;
#line 4931
  readl(__cil_tmp152);
#line 4932
  __const_udelay(859000UL);
  }
  {
#line 4934
  __cil_tmp153 = (struct intel_encoder *)0;
#line 4934
  __cil_tmp154 = (unsigned long )__cil_tmp153;
#line 4934
  __cil_tmp155 = (unsigned long )has_edp_encoder;
#line 4934
  if (__cil_tmp155 != __cil_tmp154) {
    {
#line 4935
    tmp___6 = intel_panel_use_ssc(dev_priv);
    }
#line 4935
    if ((int )tmp___6) {
      {
#line 4936
      temp = temp | 2U;
#line 4937
      i915_write32___4(dev_priv, 811520U, temp);
#line 4939
      __cil_tmp156 = dev_priv->regs;
#line 4939
      __cil_tmp157 = (void const volatile   *)__cil_tmp156;
#line 4939
      __cil_tmp158 = __cil_tmp157 + 811520U;
#line 4939
      readl(__cil_tmp158);
#line 4940
      __const_udelay(859000UL);
      }
    } else {

    }
    {
#line 4942
    temp = temp & 4294942719U;
#line 4945
    __cil_tmp159 = & has_edp_encoder->base;
#line 4945
    tmp___9 = intel_encoder_is_pch_edp(__cil_tmp159);
    }
#line 4945
    if (tmp___9) {
#line 4945
      tmp___10 = 0;
    } else {
#line 4945
      tmp___10 = 1;
    }
#line 4945
    if (tmp___10) {
      {
#line 4946
      tmp___7 = intel_panel_use_ssc(dev_priv);
      }
#line 4946
      if ((int )tmp___7) {
#line 4947
        temp = temp | 16384U;
      } else {
#line 4949
        temp = temp | 24576U;
      }
    } else {
      {
#line 4952
      tmp___8 = intel_panel_use_ssc(dev_priv);
      }
#line 4952
      if ((int )tmp___8) {
        {
#line 4953
        drm_err("ironlake_crtc_mode_set", "enabling SSC on PCH\n");
#line 4954
        temp = temp | 256U;
        }
      } else {

      }
    }
    {
#line 4957
    i915_write32___4(dev_priv, 811520U, temp);
#line 4958
    __cil_tmp160 = dev_priv->regs;
#line 4958
    __cil_tmp161 = (void const volatile   *)__cil_tmp160;
#line 4958
    __cil_tmp162 = __cil_tmp161 + 811520U;
#line 4958
    readl(__cil_tmp162);
#line 4959
    __const_udelay(859000UL);
    }
  } else {

  }
  }
#line 4962
  __cil_tmp163 = clock.m1 << 8;
#line 4962
  __cil_tmp164 = clock.n << 16;
#line 4962
  __cil_tmp165 = __cil_tmp164 | __cil_tmp163;
#line 4962
  __cil_tmp166 = __cil_tmp165 | clock.m2;
#line 4962
  fp = (u32 )__cil_tmp166;
#line 4963
  if ((int )has_reduced_clock) {
#line 4964
    __cil_tmp167 = reduced_clock.m1 << 8;
#line 4964
    __cil_tmp168 = reduced_clock.n << 16;
#line 4964
    __cil_tmp169 = __cil_tmp168 | __cil_tmp167;
#line 4964
    __cil_tmp170 = __cil_tmp169 | reduced_clock.m2;
#line 4964
    fp2 = (u32 )__cil_tmp170;
  } else {

  }
#line 4968
  factor = 21;
#line 4969
  if ((int )is_lvds) {
    {
#line 4970
    tmp___11 = intel_panel_use_ssc(dev_priv);
    }
#line 4970
    if ((int )tmp___11) {
      {
#line 4970
      __cil_tmp171 = dev_priv->lvds_ssc_freq;
#line 4970
      if (__cil_tmp171 == 100) {
#line 4973
        factor = 25;
      } else {
#line 4970
        goto _L___3;
      }
      }
    } else {
      _L___3: 
      {
#line 4970
      tmp___12 = i915_read32___6(dev_priv, 921984U);
      }
      {
#line 4970
      __cil_tmp172 = tmp___12 & 48U;
#line 4970
      if (__cil_tmp172 == 48U) {
#line 4973
        factor = 25;
      } else
#line 4974
      if ((int )is_sdvo) {
#line 4974
        if ((int )is_tv) {
#line 4975
          factor = 20;
        } else {

        }
      } else {

      }
      }
    }
  } else {

  }
  {
#line 4977
  __cil_tmp173 = clock.n * factor;
#line 4977
  if (clock.m1 < __cil_tmp173) {
#line 4978
    fp = fp | 12582912U;
  } else {

  }
  }
#line 4980
  dpll = 0U;
#line 4982
  if ((int )is_lvds) {
#line 4983
    dpll = dpll | 134217728U;
  } else {
#line 4985
    dpll = dpll | 67108864U;
  }
#line 4986
  if ((int )is_sdvo) {
    {
#line 4987
    __cil_tmp174 = (struct drm_display_mode  const  *)adjusted_mode;
#line 4987
    tmp___13 = intel_mode_get_pixel_multiplier(__cil_tmp174);
#line 4987
    pixel_multiplier___0 = tmp___13;
    }
#line 4988
    if (pixel_multiplier___0 > 1) {
#line 4989
      __cil_tmp175 = pixel_multiplier___0 + -1;
#line 4989
      __cil_tmp176 = __cil_tmp175 << 9;
#line 4989
      __cil_tmp177 = (u32 )__cil_tmp176;
#line 4989
      dpll = __cil_tmp177 | dpll;
    } else {

    }
#line 4991
    dpll = dpll | 1073741824U;
  } else {

  }
#line 4993
  if ((int )is_dp) {
#line 4994
    dpll = dpll | 1073741824U;
  } else {
    {
#line 4993
    __cil_tmp178 = & has_edp_encoder->base;
#line 4993
    tmp___14 = intel_encoder_is_pch_edp(__cil_tmp178);
    }
#line 4993
    if ((int )tmp___14) {
#line 4994
      dpll = dpll | 1073741824U;
    } else {

    }
  }
#line 4997
  __cil_tmp179 = clock.p1 + -1;
#line 4997
  __cil_tmp180 = 1 << __cil_tmp179;
#line 4997
  __cil_tmp181 = __cil_tmp180 << 16;
#line 4997
  __cil_tmp182 = (u32 )__cil_tmp181;
#line 4997
  dpll = __cil_tmp182 | dpll;
#line 4999
  __cil_tmp183 = clock.p1 + -1;
#line 4999
  __cil_tmp184 = 1 << __cil_tmp183;
#line 4999
  __cil_tmp185 = (u32 )__cil_tmp184;
#line 4999
  dpll = __cil_tmp185 | dpll;
#line 5002
  if (clock.p2 == 5) {
#line 5002
    goto case_5___0;
  } else
#line 5005
  if (clock.p2 == 7) {
#line 5005
    goto case_7___0;
  } else
#line 5008
  if (clock.p2 == 10) {
#line 5008
    goto case_10___0;
  } else
#line 5011
  if (clock.p2 == 14) {
#line 5011
    goto case_14;
  } else
#line 5001
  if (0) {
    case_5___0: 
#line 5003
    dpll = dpll | 16777216U;
#line 5004
    goto ldv_39561;
    case_7___0: 
#line 5006
    dpll = dpll | 16777216U;
#line 5007
    goto ldv_39561;
    case_10___0: 
#line 5009
    dpll = dpll;
#line 5010
    goto ldv_39561;
    case_14: 
#line 5012
    dpll = dpll;
#line 5013
    goto ldv_39561;
  } else {

  }
  ldv_39561: ;
#line 5016
  if ((int )is_sdvo) {
#line 5016
    if ((int )is_tv) {
#line 5017
      dpll = dpll | 16384U;
    } else {
#line 5016
      goto _L___4;
    }
  } else
  _L___4: 
#line 5018
  if ((int )is_tv) {
#line 5021
    dpll = dpll | 3U;
  } else
#line 5022
  if ((int )is_lvds) {
    {
#line 5022
    tmp___15 = intel_panel_use_ssc(dev_priv);
    }
#line 5022
    if ((int )tmp___15) {
#line 5022
      if (num_connectors <= 1) {
#line 5023
        dpll = dpll | 24576U;
      } else {
#line 5025
        dpll = dpll;
      }
    } else {
#line 5025
      dpll = dpll;
    }
  } else {
#line 5025
    dpll = dpll;
  }
  {
#line 5028
  __cil_tmp186 = pipe * 4096;
#line 5028
  __cil_tmp187 = __cil_tmp186 + 458760;
#line 5028
  __cil_tmp188 = (u32 )__cil_tmp187;
#line 5028
  pipeconf = i915_read32___6(dev_priv, __cil_tmp188);
#line 5031
  dspcntr = 1073741824U;
  }
#line 5033
  if (pipe == 0) {
#line 5033
    tmp___16 = 65;
  } else {
#line 5033
    tmp___16 = 66;
  }
  {
#line 5033
  drm_ut_debug_printk(4U, "drm", "ironlake_crtc_mode_set", "Mode for pipe %c:\n",
                      tmp___16);
#line 5034
  drm_mode_debug_printmodeline(mode);
  }
  {
#line 5037
  __cil_tmp189 = (struct intel_encoder *)0;
#line 5037
  __cil_tmp190 = (unsigned long )__cil_tmp189;
#line 5037
  __cil_tmp191 = (unsigned long )has_edp_encoder;
#line 5037
  if (__cil_tmp191 == __cil_tmp190) {
    {
#line 5038
    __cil_tmp192 = pipe + 101384;
#line 5038
    __cil_tmp193 = __cil_tmp192 * 8;
#line 5038
    __cil_tmp194 = (u32 )__cil_tmp193;
#line 5038
    i915_write32___4(dev_priv, __cil_tmp194, fp);
#line 5039
    __cil_tmp195 = pipe + 202757;
#line 5039
    __cil_tmp196 = __cil_tmp195 * 4;
#line 5039
    __cil_tmp197 = (u32 )__cil_tmp196;
#line 5039
    __cil_tmp198 = dpll & 2147483647U;
#line 5039
    i915_write32___4(dev_priv, __cil_tmp197, __cil_tmp198);
#line 5041
    __cil_tmp199 = pipe + 202757;
#line 5041
    __cil_tmp200 = __cil_tmp199 * 4;
#line 5041
    __cil_tmp201 = (unsigned long )__cil_tmp200;
#line 5041
    __cil_tmp202 = dev_priv->regs;
#line 5041
    __cil_tmp203 = (void const volatile   *)__cil_tmp202;
#line 5041
    __cil_tmp204 = __cil_tmp203 + __cil_tmp201;
#line 5041
    readl(__cil_tmp204);
#line 5042
    __const_udelay(644250UL);
    }
  } else {
    {
#line 5037
    __cil_tmp205 = & has_edp_encoder->base;
#line 5037
    tmp___17 = intel_encoder_is_pch_edp(__cil_tmp205);
    }
#line 5037
    if ((int )tmp___17) {
      {
#line 5038
      __cil_tmp206 = pipe + 101384;
#line 5038
      __cil_tmp207 = __cil_tmp206 * 8;
#line 5038
      __cil_tmp208 = (u32 )__cil_tmp207;
#line 5038
      i915_write32___4(dev_priv, __cil_tmp208, fp);
#line 5039
      __cil_tmp209 = pipe + 202757;
#line 5039
      __cil_tmp210 = __cil_tmp209 * 4;
#line 5039
      __cil_tmp211 = (u32 )__cil_tmp210;
#line 5039
      __cil_tmp212 = dpll & 2147483647U;
#line 5039
      i915_write32___4(dev_priv, __cil_tmp211, __cil_tmp212);
#line 5041
      __cil_tmp213 = pipe + 202757;
#line 5041
      __cil_tmp214 = __cil_tmp213 * 4;
#line 5041
      __cil_tmp215 = (unsigned long )__cil_tmp214;
#line 5041
      __cil_tmp216 = dev_priv->regs;
#line 5041
      __cil_tmp217 = (void const volatile   *)__cil_tmp216;
#line 5041
      __cil_tmp218 = __cil_tmp217 + __cil_tmp215;
#line 5041
      readl(__cil_tmp218);
#line 5042
      __const_udelay(644250UL);
      }
    } else {

    }
  }
  }
  {
#line 5046
  __cil_tmp219 = dev->dev_private;
#line 5046
  __cil_tmp220 = (struct drm_i915_private *)__cil_tmp219;
#line 5046
  __cil_tmp221 = __cil_tmp220->pch_type;
#line 5046
  __cil_tmp222 = (unsigned int )__cil_tmp221;
#line 5046
  if (__cil_tmp222 == 1U) {
    {
#line 5047
    temp = i915_read32___6(dev_priv, 815104U);
    }
#line 5049
    if (pipe == 0) {
#line 5049
      goto case_0___0;
    } else
#line 5052
    if (pipe == 1) {
#line 5052
      goto case_1___0;
    } else
#line 5055
    if (pipe == 2) {
#line 5055
      goto case_2;
    } else {
#line 5059
      goto switch_default___0;
#line 5048
      if (0) {
        case_0___0: 
#line 5050
        temp = temp | 8U;
#line 5051
        goto ldv_39566;
        case_1___0: 
#line 5053
        temp = temp | 144U;
#line 5054
        goto ldv_39566;
        case_2: 
#line 5057
        temp = temp | 2304U;
#line 5058
        goto ldv_39566;
        switch_default___0: 
#line 5060
        __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                             "i" (5060), "i" (12UL));
        ldv_39570: ;
#line 5060
        goto ldv_39570;
      } else {

      }
    }
    ldv_39566: 
    {
#line 5062
    i915_write32___4(dev_priv, 815104U, temp);
#line 5064
    __cil_tmp223 = dev_priv->regs;
#line 5064
    __cil_tmp224 = (void const volatile   *)__cil_tmp223;
#line 5064
    __cil_tmp225 = __cil_tmp224 + 815104U;
#line 5064
    readl(__cil_tmp225);
#line 5065
    __const_udelay(644250UL);
    }
  } else {

  }
  }
#line 5072
  if ((int )is_lvds) {
    {
#line 5073
    temp = i915_read32___6(dev_priv, 921984U);
#line 5074
    temp = temp | 2147484416U;
    }
#line 5075
    if (pipe == 1) {
      {
#line 5076
      __cil_tmp226 = dev->dev_private;
#line 5076
      __cil_tmp227 = (struct drm_i915_private *)__cil_tmp226;
#line 5076
      __cil_tmp228 = __cil_tmp227->pch_type;
#line 5076
      __cil_tmp229 = (unsigned int )__cil_tmp228;
#line 5076
      if (__cil_tmp229 == 1U) {
#line 5077
        temp = temp | 536870912U;
      } else {
#line 5079
        temp = temp | 1073741824U;
      }
      }
    } else {
      {
#line 5081
      __cil_tmp230 = dev->dev_private;
#line 5081
      __cil_tmp231 = (struct drm_i915_private *)__cil_tmp230;
#line 5081
      __cil_tmp232 = __cil_tmp231->pch_type;
#line 5081
      __cil_tmp233 = (unsigned int )__cil_tmp232;
#line 5081
      if (__cil_tmp233 == 1U) {
#line 5082
        temp = temp & 2684354559U;
      } else {
#line 5084
        temp = temp & 3221225471U;
      }
      }
    }
#line 5087
    __cil_tmp234 = dev_priv->lvds_border_bits;
#line 5087
    temp = __cil_tmp234 | temp;
#line 5091
    if (clock.p2 == 7) {
#line 5092
      temp = temp | 60U;
    } else {
#line 5094
      temp = temp & 4294967235U;
    }
    {
#line 5100
    __cil_tmp235 = adjusted_mode->flags;
#line 5100
    __cil_tmp236 = __cil_tmp235 & 2U;
#line 5100
    if (__cil_tmp236 != 0U) {
#line 5101
      lvds_sync = lvds_sync | 1048576U;
    } else {

    }
    }
    {
#line 5102
    __cil_tmp237 = adjusted_mode->flags;
#line 5102
    __cil_tmp238 = __cil_tmp237 & 8U;
#line 5102
    if (__cil_tmp238 != 0U) {
#line 5103
      lvds_sync = lvds_sync | 2097152U;
    } else {

    }
    }
    {
#line 5104
    __cil_tmp239 = temp & 3145728U;
#line 5104
    if (__cil_tmp239 != lvds_sync) {
      {
#line 5106
      flags[0] = (char )'-';
#line 5106
      flags[1] = (char )'+';
#line 5107
      __cil_tmp240 = (int )flags[(temp & 1048576U) == 0U];
#line 5107
      __cil_tmp241 = (int )flags[(temp & 2097152U) == 0U];
#line 5107
      __cil_tmp242 = (int )flags[(lvds_sync & 1048576U) == 0U];
#line 5107
      __cil_tmp243 = (int )flags[(lvds_sync & 2097152U) == 0U];
#line 5107
      printk("<6>[drm] Changing LVDS panel from (%chsync, %cvsync) to (%chsync, %cvsync)\n",
             __cil_tmp240, __cil_tmp241, __cil_tmp242, __cil_tmp243);
#line 5113
      temp = temp & 4291821567U;
#line 5114
      temp = temp | lvds_sync;
      }
    } else {

    }
    }
    {
#line 5116
    i915_write32___4(dev_priv, 921984U, temp);
    }
  } else {

  }
#line 5120
  pipeconf = pipeconf & 4294967279U;
#line 5121
  pipeconf = pipeconf & 4294967283U;
  {
#line 5122
  __cil_tmp244 = (unsigned char *)dev_priv;
#line 5122
  __cil_tmp245 = __cil_tmp244 + 2072UL;
#line 5122
  __cil_tmp246 = *__cil_tmp245;
#line 5122
  __cil_tmp247 = (unsigned int )__cil_tmp246;
#line 5122
  if (__cil_tmp247 != 0U) {
#line 5122
    if ((int )is_lvds) {
#line 5123
      pipeconf = pipeconf | 16U;
#line 5124
      pipeconf = pipeconf | 4U;
    } else {
      {
#line 5122
      __cil_tmp248 = (struct intel_encoder *)0;
#line 5122
      __cil_tmp249 = (unsigned long )__cil_tmp248;
#line 5122
      __cil_tmp250 = (unsigned long )has_edp_encoder;
#line 5122
      if (__cil_tmp250 != __cil_tmp249) {
#line 5123
        pipeconf = pipeconf | 16U;
#line 5124
        pipeconf = pipeconf | 4U;
      } else {

      }
      }
    }
  } else {

  }
  }
#line 5127
  if ((int )is_dp) {
    {
#line 5128
    intel_dp_set_m_n(crtc, mode, adjusted_mode);
    }
  } else {
    {
#line 5127
    __cil_tmp251 = & has_edp_encoder->base;
#line 5127
    tmp___18 = intel_encoder_is_pch_edp(__cil_tmp251);
    }
#line 5127
    if ((int )tmp___18) {
      {
#line 5128
      intel_dp_set_m_n(crtc, mode, adjusted_mode);
      }
    } else {
      {
#line 5131
      __cil_tmp252 = pipe * 4096;
#line 5131
      __cil_tmp253 = __cil_tmp252 + 917552;
#line 5131
      __cil_tmp254 = (u32 )__cil_tmp253;
#line 5131
      i915_write32___4(dev_priv, __cil_tmp254, 0U);
#line 5132
      __cil_tmp255 = pipe * 4096;
#line 5132
      __cil_tmp256 = __cil_tmp255 + 917556;
#line 5132
      __cil_tmp257 = (u32 )__cil_tmp256;
#line 5132
      i915_write32___4(dev_priv, __cil_tmp257, 0U);
#line 5133
      __cil_tmp258 = pipe * 4096;
#line 5133
      __cil_tmp259 = __cil_tmp258 + 917568;
#line 5133
      __cil_tmp260 = (u32 )__cil_tmp259;
#line 5133
      i915_write32___4(dev_priv, __cil_tmp260, 0U);
#line 5134
      __cil_tmp261 = pipe * 4096;
#line 5134
      __cil_tmp262 = __cil_tmp261 + 917572;
#line 5134
      __cil_tmp263 = (u32 )__cil_tmp262;
#line 5134
      i915_write32___4(dev_priv, __cil_tmp263, 0U);
      }
    }
  }
  {
#line 5137
  __cil_tmp264 = (struct intel_encoder *)0;
#line 5137
  __cil_tmp265 = (unsigned long )__cil_tmp264;
#line 5137
  __cil_tmp266 = (unsigned long )has_edp_encoder;
#line 5137
  if (__cil_tmp266 == __cil_tmp265) {
    {
#line 5139
    __cil_tmp267 = pipe + 202757;
#line 5139
    __cil_tmp268 = __cil_tmp267 * 4;
#line 5139
    __cil_tmp269 = (u32 )__cil_tmp268;
#line 5139
    i915_write32___4(dev_priv, __cil_tmp269, dpll);
#line 5142
    __cil_tmp270 = pipe + 202757;
#line 5142
    __cil_tmp271 = __cil_tmp270 * 4;
#line 5142
    __cil_tmp272 = (unsigned long )__cil_tmp271;
#line 5142
    __cil_tmp273 = dev_priv->regs;
#line 5142
    __cil_tmp274 = (void const volatile   *)__cil_tmp273;
#line 5142
    __cil_tmp275 = __cil_tmp274 + __cil_tmp272;
#line 5142
    readl(__cil_tmp275);
#line 5143
    __const_udelay(644250UL);
#line 5150
    __cil_tmp276 = pipe + 202757;
#line 5150
    __cil_tmp277 = __cil_tmp276 * 4;
#line 5150
    __cil_tmp278 = (u32 )__cil_tmp277;
#line 5150
    i915_write32___4(dev_priv, __cil_tmp278, dpll);
    }
  } else {
    {
#line 5137
    __cil_tmp279 = & has_edp_encoder->base;
#line 5137
    tmp___19 = intel_encoder_is_pch_edp(__cil_tmp279);
    }
#line 5137
    if ((int )tmp___19) {
      {
#line 5139
      __cil_tmp280 = pipe + 202757;
#line 5139
      __cil_tmp281 = __cil_tmp280 * 4;
#line 5139
      __cil_tmp282 = (u32 )__cil_tmp281;
#line 5139
      i915_write32___4(dev_priv, __cil_tmp282, dpll);
#line 5142
      __cil_tmp283 = pipe + 202757;
#line 5142
      __cil_tmp284 = __cil_tmp283 * 4;
#line 5142
      __cil_tmp285 = (unsigned long )__cil_tmp284;
#line 5142
      __cil_tmp286 = dev_priv->regs;
#line 5142
      __cil_tmp287 = (void const volatile   *)__cil_tmp286;
#line 5142
      __cil_tmp288 = __cil_tmp287 + __cil_tmp285;
#line 5142
      readl(__cil_tmp288);
#line 5143
      __const_udelay(644250UL);
#line 5150
      __cil_tmp289 = pipe + 202757;
#line 5150
      __cil_tmp290 = __cil_tmp289 * 4;
#line 5150
      __cil_tmp291 = (u32 )__cil_tmp290;
#line 5150
      i915_write32___4(dev_priv, __cil_tmp291, dpll);
      }
    } else {

    }
  }
  }
#line 5153
  intel_crtc->lowfreq_avail = (bool )0;
#line 5154
  if ((int )is_lvds) {
#line 5154
    if ((int )has_reduced_clock) {
#line 5154
      if (i915_powersave != 0U) {
        {
#line 5155
        __cil_tmp292 = pipe * 8;
#line 5155
        __cil_tmp293 = __cil_tmp292 + 811076;
#line 5155
        __cil_tmp294 = (u32 )__cil_tmp293;
#line 5155
        i915_write32___4(dev_priv, __cil_tmp294, fp2);
#line 5156
        intel_crtc->lowfreq_avail = (bool )1;
        }
        {
#line 5157
        __cil_tmp295 = dev->dev_private;
#line 5157
        __cil_tmp296 = (struct drm_i915_private *)__cil_tmp295;
#line 5157
        __cil_tmp297 = __cil_tmp296->info;
#line 5157
        __cil_tmp298 = (unsigned char *)__cil_tmp297;
#line 5157
        __cil_tmp299 = __cil_tmp298 + 2UL;
#line 5157
        __cil_tmp300 = *__cil_tmp299;
#line 5157
        __cil_tmp301 = (unsigned int )__cil_tmp300;
#line 5157
        if (__cil_tmp301 != 0U) {
          {
#line 5158
          drm_ut_debug_printk(4U, "drm", "ironlake_crtc_mode_set", "enabling CxSR downclocking\n");
#line 5159
          pipeconf = pipeconf | 65536U;
          }
        } else {

        }
        }
      } else {
#line 5154
        goto _L___6;
      }
    } else {
#line 5154
      goto _L___6;
    }
  } else {
    _L___6: 
    {
#line 5162
    __cil_tmp302 = pipe * 8;
#line 5162
    __cil_tmp303 = __cil_tmp302 + 811076;
#line 5162
    __cil_tmp304 = (u32 )__cil_tmp303;
#line 5162
    i915_write32___4(dev_priv, __cil_tmp304, fp);
    }
    {
#line 5163
    __cil_tmp305 = dev->dev_private;
#line 5163
    __cil_tmp306 = (struct drm_i915_private *)__cil_tmp305;
#line 5163
    __cil_tmp307 = __cil_tmp306->info;
#line 5163
    __cil_tmp308 = (unsigned char *)__cil_tmp307;
#line 5163
    __cil_tmp309 = __cil_tmp308 + 2UL;
#line 5163
    __cil_tmp310 = *__cil_tmp309;
#line 5163
    __cil_tmp311 = (unsigned int )__cil_tmp310;
#line 5163
    if (__cil_tmp311 != 0U) {
      {
#line 5164
      drm_ut_debug_printk(4U, "drm", "ironlake_crtc_mode_set", "disabling CxSR downclocking\n");
#line 5165
      pipeconf = pipeconf & 4294901759U;
      }
    } else {

    }
    }
  }
  {
#line 5169
  __cil_tmp312 = adjusted_mode->flags;
#line 5169
  __cil_tmp313 = __cil_tmp312 & 16U;
#line 5169
  if (__cil_tmp313 != 0U) {
#line 5170
    pipeconf = pipeconf | 12582912U;
#line 5172
    __cil_tmp314 = adjusted_mode->crtc_vdisplay;
#line 5172
    adjusted_mode->crtc_vdisplay = __cil_tmp314 + -1;
#line 5173
    __cil_tmp315 = adjusted_mode->crtc_vtotal;
#line 5173
    adjusted_mode->crtc_vtotal = __cil_tmp315 + -1;
#line 5174
    __cil_tmp316 = adjusted_mode->crtc_vblank_start;
#line 5174
    adjusted_mode->crtc_vblank_start = __cil_tmp316 + -1;
#line 5175
    __cil_tmp317 = adjusted_mode->crtc_vblank_end;
#line 5175
    adjusted_mode->crtc_vblank_end = __cil_tmp317 + -1;
#line 5176
    __cil_tmp318 = adjusted_mode->crtc_vsync_end;
#line 5176
    adjusted_mode->crtc_vsync_end = __cil_tmp318 + -1;
#line 5177
    __cil_tmp319 = adjusted_mode->crtc_vsync_start;
#line 5177
    adjusted_mode->crtc_vsync_start = __cil_tmp319 + -1;
  } else {
#line 5179
    pipeconf = pipeconf & 4282384383U;
  }
  }
  {
#line 5181
  __cil_tmp320 = pipe + 96;
#line 5181
  __cil_tmp321 = __cil_tmp320 * 4096;
#line 5181
  __cil_tmp322 = (u32 )__cil_tmp321;
#line 5181
  __cil_tmp323 = adjusted_mode->crtc_htotal;
#line 5181
  __cil_tmp324 = __cil_tmp323 + -1;
#line 5181
  __cil_tmp325 = __cil_tmp324 << 16;
#line 5181
  __cil_tmp326 = adjusted_mode->crtc_hdisplay;
#line 5181
  __cil_tmp327 = __cil_tmp326 + -1;
#line 5181
  __cil_tmp328 = __cil_tmp327 | __cil_tmp325;
#line 5181
  __cil_tmp329 = (u32 )__cil_tmp328;
#line 5181
  i915_write32___4(dev_priv, __cil_tmp322, __cil_tmp329);
#line 5184
  __cil_tmp330 = pipe * 4096;
#line 5184
  __cil_tmp331 = __cil_tmp330 + 393220;
#line 5184
  __cil_tmp332 = (u32 )__cil_tmp331;
#line 5184
  __cil_tmp333 = adjusted_mode->crtc_hblank_end;
#line 5184
  __cil_tmp334 = __cil_tmp333 + -1;
#line 5184
  __cil_tmp335 = __cil_tmp334 << 16;
#line 5184
  __cil_tmp336 = adjusted_mode->crtc_hblank_start;
#line 5184
  __cil_tmp337 = __cil_tmp336 + -1;
#line 5184
  __cil_tmp338 = __cil_tmp337 | __cil_tmp335;
#line 5184
  __cil_tmp339 = (u32 )__cil_tmp338;
#line 5184
  i915_write32___4(dev_priv, __cil_tmp332, __cil_tmp339);
#line 5187
  __cil_tmp340 = pipe * 4096;
#line 5187
  __cil_tmp341 = __cil_tmp340 + 393224;
#line 5187
  __cil_tmp342 = (u32 )__cil_tmp341;
#line 5187
  __cil_tmp343 = adjusted_mode->crtc_hsync_end;
#line 5187
  __cil_tmp344 = __cil_tmp343 + -1;
#line 5187
  __cil_tmp345 = __cil_tmp344 << 16;
#line 5187
  __cil_tmp346 = adjusted_mode->crtc_hsync_start;
#line 5187
  __cil_tmp347 = __cil_tmp346 + -1;
#line 5187
  __cil_tmp348 = __cil_tmp347 | __cil_tmp345;
#line 5187
  __cil_tmp349 = (u32 )__cil_tmp348;
#line 5187
  i915_write32___4(dev_priv, __cil_tmp342, __cil_tmp349);
#line 5191
  __cil_tmp350 = pipe * 4096;
#line 5191
  __cil_tmp351 = __cil_tmp350 + 393228;
#line 5191
  __cil_tmp352 = (u32 )__cil_tmp351;
#line 5191
  __cil_tmp353 = adjusted_mode->crtc_vtotal;
#line 5191
  __cil_tmp354 = __cil_tmp353 + -1;
#line 5191
  __cil_tmp355 = __cil_tmp354 << 16;
#line 5191
  __cil_tmp356 = adjusted_mode->crtc_vdisplay;
#line 5191
  __cil_tmp357 = __cil_tmp356 + -1;
#line 5191
  __cil_tmp358 = __cil_tmp357 | __cil_tmp355;
#line 5191
  __cil_tmp359 = (u32 )__cil_tmp358;
#line 5191
  i915_write32___4(dev_priv, __cil_tmp352, __cil_tmp359);
#line 5194
  __cil_tmp360 = pipe * 4096;
#line 5194
  __cil_tmp361 = __cil_tmp360 + 393232;
#line 5194
  __cil_tmp362 = (u32 )__cil_tmp361;
#line 5194
  __cil_tmp363 = adjusted_mode->crtc_vblank_end;
#line 5194
  __cil_tmp364 = __cil_tmp363 + -1;
#line 5194
  __cil_tmp365 = __cil_tmp364 << 16;
#line 5194
  __cil_tmp366 = adjusted_mode->crtc_vblank_start;
#line 5194
  __cil_tmp367 = __cil_tmp366 + -1;
#line 5194
  __cil_tmp368 = __cil_tmp367 | __cil_tmp365;
#line 5194
  __cil_tmp369 = (u32 )__cil_tmp368;
#line 5194
  i915_write32___4(dev_priv, __cil_tmp362, __cil_tmp369);
#line 5197
  __cil_tmp370 = pipe * 4096;
#line 5197
  __cil_tmp371 = __cil_tmp370 + 393236;
#line 5197
  __cil_tmp372 = (u32 )__cil_tmp371;
#line 5197
  __cil_tmp373 = adjusted_mode->crtc_vsync_end;
#line 5197
  __cil_tmp374 = __cil_tmp373 + -1;
#line 5197
  __cil_tmp375 = __cil_tmp374 << 16;
#line 5197
  __cil_tmp376 = adjusted_mode->crtc_vsync_start;
#line 5197
  __cil_tmp377 = __cil_tmp376 + -1;
#line 5197
  __cil_tmp378 = __cil_tmp377 | __cil_tmp375;
#line 5197
  __cil_tmp379 = (u32 )__cil_tmp378;
#line 5197
  i915_write32___4(dev_priv, __cil_tmp372, __cil_tmp379);
#line 5204
  __cil_tmp380 = pipe * 4096;
#line 5204
  __cil_tmp381 = __cil_tmp380 + 393244;
#line 5204
  __cil_tmp382 = (u32 )__cil_tmp381;
#line 5204
  __cil_tmp383 = mode->vdisplay;
#line 5204
  __cil_tmp384 = __cil_tmp383 + -1;
#line 5204
  __cil_tmp385 = mode->hdisplay;
#line 5204
  __cil_tmp386 = __cil_tmp385 + -1;
#line 5204
  __cil_tmp387 = __cil_tmp386 << 16;
#line 5204
  __cil_tmp388 = __cil_tmp387 | __cil_tmp384;
#line 5204
  __cil_tmp389 = (u32 )__cil_tmp388;
#line 5204
  i915_write32___4(dev_priv, __cil_tmp382, __cil_tmp389);
#line 5207
  __cil_tmp390 = pipe * 4096;
#line 5207
  __cil_tmp391 = __cil_tmp390 + 393264;
#line 5207
  __cil_tmp392 = (u32 )__cil_tmp391;
#line 5207
  __cil_tmp393 = m_n.tu - 1U;
#line 5207
  __cil_tmp394 = __cil_tmp393 << 25;
#line 5207
  __cil_tmp395 = __cil_tmp394 | m_n.gmch_m;
#line 5207
  i915_write32___4(dev_priv, __cil_tmp392, __cil_tmp395);
#line 5208
  __cil_tmp396 = pipe * 4096;
#line 5208
  __cil_tmp397 = __cil_tmp396 + 393268;
#line 5208
  __cil_tmp398 = (u32 )__cil_tmp397;
#line 5208
  i915_write32___4(dev_priv, __cil_tmp398, m_n.gmch_n);
#line 5209
  __cil_tmp399 = pipe * 4096;
#line 5209
  __cil_tmp400 = __cil_tmp399 + 393280;
#line 5209
  __cil_tmp401 = (u32 )__cil_tmp400;
#line 5209
  i915_write32___4(dev_priv, __cil_tmp401, m_n.link_m);
#line 5210
  __cil_tmp402 = pipe * 4096;
#line 5210
  __cil_tmp403 = __cil_tmp402 + 393284;
#line 5210
  __cil_tmp404 = (u32 )__cil_tmp403;
#line 5210
  i915_write32___4(dev_priv, __cil_tmp404, m_n.link_n);
  }
  {
#line 5212
  __cil_tmp405 = (struct intel_encoder *)0;
#line 5212
  __cil_tmp406 = (unsigned long )__cil_tmp405;
#line 5212
  __cil_tmp407 = (unsigned long )has_edp_encoder;
#line 5212
  if (__cil_tmp407 != __cil_tmp406) {
    {
#line 5212
    __cil_tmp408 = & has_edp_encoder->base;
#line 5212
    tmp___20 = intel_encoder_is_pch_edp(__cil_tmp408);
    }
#line 5212
    if (tmp___20) {
#line 5212
      tmp___21 = 0;
    } else {
#line 5212
      tmp___21 = 1;
    }
#line 5212
    if (tmp___21) {
      {
#line 5214
      __cil_tmp409 = adjusted_mode->clock;
#line 5214
      ironlake_set_pll_edp(crtc, __cil_tmp409);
      }
    } else {

    }
  } else {

  }
  }
  {
#line 5217
  __cil_tmp410 = pipe * 4096;
#line 5217
  __cil_tmp411 = __cil_tmp410 + 458760;
#line 5217
  __cil_tmp412 = (u32 )__cil_tmp411;
#line 5217
  i915_write32___4(dev_priv, __cil_tmp412, pipeconf);
#line 5218
  __cil_tmp413 = pipe * 4096;
#line 5218
  __cil_tmp414 = __cil_tmp413 + 458760;
#line 5218
  __cil_tmp415 = (unsigned long )__cil_tmp414;
#line 5218
  __cil_tmp416 = dev_priv->regs;
#line 5218
  __cil_tmp417 = (void const volatile   *)__cil_tmp416;
#line 5218
  __cil_tmp418 = __cil_tmp417 + __cil_tmp415;
#line 5218
  readl(__cil_tmp418);
#line 5220
  intel_wait_for_vblank(dev, pipe);
  }
  {
#line 5222
  __cil_tmp419 = dev->dev_private;
#line 5222
  __cil_tmp420 = (struct drm_i915_private *)__cil_tmp419;
#line 5222
  __cil_tmp421 = __cil_tmp420->info;
#line 5222
  __cil_tmp422 = __cil_tmp421->gen;
#line 5222
  __cil_tmp423 = (unsigned char )__cil_tmp422;
#line 5222
  __cil_tmp424 = (unsigned int )__cil_tmp423;
#line 5222
  if (__cil_tmp424 == 5U) {
    {
#line 5224
    temp = i915_read32___6(dev_priv, 282624U);
#line 5225
    __cil_tmp425 = temp | 8192U;
#line 5225
    i915_write32___4(dev_priv, 282624U, __cil_tmp425);
    }
  } else {

  }
  }
  {
#line 5228
  __cil_tmp426 = plane * 4096;
#line 5228
  __cil_tmp427 = __cil_tmp426 + 459136;
#line 5228
  __cil_tmp428 = (u32 )__cil_tmp427;
#line 5228
  i915_write32___4(dev_priv, __cil_tmp428, dspcntr);
#line 5229
  __cil_tmp429 = plane * 4096;
#line 5229
  __cil_tmp430 = __cil_tmp429 + 459136;
#line 5229
  __cil_tmp431 = (unsigned long )__cil_tmp430;
#line 5229
  __cil_tmp432 = dev_priv->regs;
#line 5229
  __cil_tmp433 = (void const volatile   *)__cil_tmp432;
#line 5229
  __cil_tmp434 = __cil_tmp433 + __cil_tmp431;
#line 5229
  readl(__cil_tmp434);
#line 5231
  ret = intel_pipe_set_base(crtc, x, y, old_fb);
#line 5233
  intel_update_watermarks(dev);
  }
#line 5235
  return (ret);
}
}
#line 5238 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_crtc_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode ,
                               struct drm_display_mode *adjusted_mode , int x , int y ,
                               struct drm_framebuffer *old_fb ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  int ret ;
  void *__cil_tmp13 ;
  enum pipe __cil_tmp14 ;
  int (*__cil_tmp15)(struct drm_crtc * , struct drm_display_mode * , struct drm_display_mode * ,
                     int  , int  , struct drm_framebuffer * ) ;

  {
  {
#line 5244
  dev = crtc->dev;
#line 5245
  __cil_tmp13 = dev->dev_private;
#line 5245
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 5246
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5246
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5247
  __cil_tmp14 = intel_crtc->pipe;
#line 5247
  pipe = (int )__cil_tmp14;
#line 5250
  drm_vblank_pre_modeset(dev, pipe);
#line 5252
  __cil_tmp15 = dev_priv->display.crtc_mode_set;
#line 5252
  ret = (*__cil_tmp15)(crtc, mode, adjusted_mode, x, y, old_fb);
#line 5255
  drm_vblank_post_modeset(dev, pipe);
  }
#line 5257
  return (ret);
}
}
#line 5261 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_crtc_load_lut(struct drm_crtc *crtc ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int palreg ;
  int i ;
  void *__cil_tmp8 ;
  enum pipe __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  bool __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  enum pipe __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  void *__cil_tmp24 ;
  struct drm_i915_private *__cil_tmp25 ;
  struct intel_device_info  const  *__cil_tmp26 ;
  u8 __cil_tmp27 ;
  unsigned char __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  enum pipe __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  void *__cil_tmp34 ;
  struct drm_i915_private *__cil_tmp35 ;
  struct intel_device_info  const  *__cil_tmp36 ;
  unsigned char *__cil_tmp37 ;
  unsigned char *__cil_tmp38 ;
  unsigned char __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  enum pipe __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  int __cil_tmp45 ;
  int __cil_tmp46 ;
  u32 __cil_tmp47 ;
  u8 __cil_tmp48 ;
  int __cil_tmp49 ;
  u8 __cil_tmp50 ;
  int __cil_tmp51 ;
  int __cil_tmp52 ;
  u8 __cil_tmp53 ;
  int __cil_tmp54 ;
  int __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  u32 __cil_tmp58 ;

  {
#line 5263
  dev = crtc->dev;
#line 5264
  __cil_tmp8 = dev->dev_private;
#line 5264
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 5265
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5265
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5266
  __cil_tmp9 = intel_crtc->pipe;
#line 5266
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 5266
  __cil_tmp11 = __cil_tmp10 + 20U;
#line 5266
  __cil_tmp12 = __cil_tmp11 * 2048U;
#line 5266
  palreg = (int )__cil_tmp12;
  {
#line 5270
  __cil_tmp13 = crtc->enabled;
#line 5270
  if (! __cil_tmp13) {
#line 5271
    return;
  } else {

  }
  }
  {
#line 5274
  __cil_tmp14 = dev->dev_private;
#line 5274
  __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 5274
  __cil_tmp16 = __cil_tmp15->info;
#line 5274
  __cil_tmp17 = __cil_tmp16->gen;
#line 5274
  __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 5274
  __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 5274
  if (__cil_tmp19 == 5U) {
#line 5275
    __cil_tmp20 = intel_crtc->pipe;
#line 5275
    __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 5275
    __cil_tmp22 = __cil_tmp21 + 148U;
#line 5275
    __cil_tmp23 = __cil_tmp22 * 2048U;
#line 5275
    palreg = (int )__cil_tmp23;
  } else {
    {
#line 5274
    __cil_tmp24 = dev->dev_private;
#line 5274
    __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
#line 5274
    __cil_tmp26 = __cil_tmp25->info;
#line 5274
    __cil_tmp27 = __cil_tmp26->gen;
#line 5274
    __cil_tmp28 = (unsigned char )__cil_tmp27;
#line 5274
    __cil_tmp29 = (unsigned int )__cil_tmp28;
#line 5274
    if (__cil_tmp29 == 6U) {
#line 5275
      __cil_tmp30 = intel_crtc->pipe;
#line 5275
      __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 5275
      __cil_tmp32 = __cil_tmp31 + 148U;
#line 5275
      __cil_tmp33 = __cil_tmp32 * 2048U;
#line 5275
      palreg = (int )__cil_tmp33;
    } else {
      {
#line 5274
      __cil_tmp34 = dev->dev_private;
#line 5274
      __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
#line 5274
      __cil_tmp36 = __cil_tmp35->info;
#line 5274
      __cil_tmp37 = (unsigned char *)__cil_tmp36;
#line 5274
      __cil_tmp38 = __cil_tmp37 + 2UL;
#line 5274
      __cil_tmp39 = *__cil_tmp38;
#line 5274
      __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 5274
      if (__cil_tmp40 != 0U) {
#line 5275
        __cil_tmp41 = intel_crtc->pipe;
#line 5275
        __cil_tmp42 = (unsigned int )__cil_tmp41;
#line 5275
        __cil_tmp43 = __cil_tmp42 + 148U;
#line 5275
        __cil_tmp44 = __cil_tmp43 * 2048U;
#line 5275
        palreg = (int )__cil_tmp44;
      } else {

      }
      }
    }
    }
  }
  }
#line 5277
  i = 0;
#line 5277
  goto ldv_39598;
  ldv_39597: 
  {
#line 5278
  __cil_tmp45 = i * 4;
#line 5278
  __cil_tmp46 = __cil_tmp45 + palreg;
#line 5278
  __cil_tmp47 = (u32 )__cil_tmp46;
#line 5278
  __cil_tmp48 = intel_crtc->lut_b[i];
#line 5278
  __cil_tmp49 = (int )__cil_tmp48;
#line 5278
  __cil_tmp50 = intel_crtc->lut_g[i];
#line 5278
  __cil_tmp51 = (int )__cil_tmp50;
#line 5278
  __cil_tmp52 = __cil_tmp51 << 8;
#line 5278
  __cil_tmp53 = intel_crtc->lut_r[i];
#line 5278
  __cil_tmp54 = (int )__cil_tmp53;
#line 5278
  __cil_tmp55 = __cil_tmp54 << 16;
#line 5278
  __cil_tmp56 = __cil_tmp55 | __cil_tmp52;
#line 5278
  __cil_tmp57 = __cil_tmp56 | __cil_tmp49;
#line 5278
  __cil_tmp58 = (u32 )__cil_tmp57;
#line 5278
  i915_write32___4(dev_priv, __cil_tmp47, __cil_tmp58);
#line 5277
  i = i + 1;
  }
  ldv_39598: ;
#line 5277
  if (i <= 255) {
#line 5278
    goto ldv_39597;
  } else {
#line 5280
    goto ldv_39599;
  }
  ldv_39599: ;
#line 5282
  return;
}
}
#line 5285 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void i845_update_cursor(struct drm_crtc *crtc , u32 base ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  bool visible ;
  u32 cntl ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  bool __cil_tmp12 ;
  int __cil_tmp13 ;

  {
#line 5287
  dev = crtc->dev;
#line 5288
  __cil_tmp9 = dev->dev_private;
#line 5288
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 5289
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5289
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5290
  __cil_tmp10 = base != 0U;
#line 5290
  visible = (bool )__cil_tmp10;
  {
#line 5293
  __cil_tmp11 = (int )visible;
#line 5293
  __cil_tmp12 = intel_crtc->cursor_visible;
#line 5293
  __cil_tmp13 = (int )__cil_tmp12;
#line 5293
  if (__cil_tmp13 == __cil_tmp11) {
#line 5294
    return;
  } else {

  }
  }
  {
#line 5296
  cntl = i915_read32___6(dev_priv, 458880U);
  }
#line 5297
  if ((int )visible) {
    {
#line 5301
    i915_write32___4(dev_priv, 458884U, base);
#line 5303
    cntl = cntl & 4177526783U;
#line 5305
    cntl = cntl | 3288334336U;
    }
  } else {
#line 5309
    cntl = cntl & 1073741823U;
  }
  {
#line 5310
  i915_write32___4(dev_priv, 458880U, cntl);
#line 5312
  intel_crtc->cursor_visible = visible;
  }
#line 5313
  return;
}
}
#line 5315 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void i9xx_update_cursor(struct drm_crtc *crtc , u32 base ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  bool visible ;
  uint32_t cntl ;
  u32 tmp ;
  void *__cil_tmp11 ;
  enum pipe __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  bool __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  int __cil_tmp20 ;
  uint32_t __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  u32 __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  u32 __cil_tmp27 ;

  {
#line 5317
  dev = crtc->dev;
#line 5318
  __cil_tmp11 = dev->dev_private;
#line 5318
  dev_priv = (struct drm_i915_private *)__cil_tmp11;
#line 5319
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5319
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5320
  __cil_tmp12 = intel_crtc->pipe;
#line 5320
  pipe = (int )__cil_tmp12;
#line 5321
  __cil_tmp13 = base != 0U;
#line 5321
  visible = (bool )__cil_tmp13;
  {
#line 5323
  __cil_tmp14 = (int )visible;
#line 5323
  __cil_tmp15 = intel_crtc->cursor_visible;
#line 5323
  __cil_tmp16 = (int )__cil_tmp15;
#line 5323
  if (__cil_tmp16 != __cil_tmp14) {
    {
#line 5324
    __cil_tmp17 = pipe + 7170;
#line 5324
    __cil_tmp18 = __cil_tmp17 * 64;
#line 5324
    __cil_tmp19 = (u32 )__cil_tmp18;
#line 5324
    tmp = i915_read32___6(dev_priv, __cil_tmp19);
#line 5324
    cntl = tmp;
    }
#line 5325
    if (base != 0U) {
#line 5326
      cntl = cntl & 4026531800U;
#line 5327
      cntl = cntl | 67108903U;
#line 5328
      __cil_tmp20 = pipe << 28;
#line 5328
      __cil_tmp21 = (uint32_t )__cil_tmp20;
#line 5328
      cntl = __cil_tmp21 | cntl;
    } else {
#line 5330
      cntl = cntl & 4227858392U;
#line 5331
      cntl = cntl;
    }
    {
#line 5333
    __cil_tmp22 = pipe + 7170;
#line 5333
    __cil_tmp23 = __cil_tmp22 * 64;
#line 5333
    __cil_tmp24 = (u32 )__cil_tmp23;
#line 5333
    i915_write32___4(dev_priv, __cil_tmp24, cntl);
#line 5335
    intel_crtc->cursor_visible = visible;
    }
  } else {

  }
  }
  {
#line 5338
  __cil_tmp25 = pipe * 64;
#line 5338
  __cil_tmp26 = __cil_tmp25 + 458884;
#line 5338
  __cil_tmp27 = (u32 )__cil_tmp26;
#line 5338
  i915_write32___4(dev_priv, __cil_tmp27, base);
  }
#line 5339
  return;
}
}
#line 5342 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_crtc_update_cursor(struct drm_crtc *crtc , bool on ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  int x ;
  int y ;
  u32 base ;
  u32 pos ;
  bool visible ;
  struct drm_framebuffer  const  *__mptr___0 ;
  void *__cil_tmp14 ;
  enum pipe __cil_tmp15 ;
  int16_t __cil_tmp16 ;
  int16_t __cil_tmp17 ;
  bool __cil_tmp18 ;
  struct drm_framebuffer *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  struct drm_framebuffer *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct drm_framebuffer *__cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  int __cil_tmp25 ;
  struct drm_framebuffer *__cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  int16_t __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  u32 __cil_tmp32 ;
  int16_t __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  u32 __cil_tmp37 ;
  int __cil_tmp38 ;
  bool __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  u32 __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  struct drm_framebuffer *__cil_tmp45 ;
  struct intel_framebuffer *__cil_tmp46 ;
  struct drm_i915_gem_object *__cil_tmp47 ;

  {
#line 5345
  dev = crtc->dev;
#line 5346
  __cil_tmp14 = dev->dev_private;
#line 5346
  dev_priv = (struct drm_i915_private *)__cil_tmp14;
#line 5347
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5347
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5348
  __cil_tmp15 = intel_crtc->pipe;
#line 5348
  pipe = (int )__cil_tmp15;
#line 5349
  __cil_tmp16 = intel_crtc->cursor_x;
#line 5349
  x = (int )__cil_tmp16;
#line 5350
  __cil_tmp17 = intel_crtc->cursor_y;
#line 5350
  y = (int )__cil_tmp17;
#line 5354
  pos = 0U;
#line 5356
  if ((int )on) {
    {
#line 5356
    __cil_tmp18 = crtc->enabled;
#line 5356
    if ((int )__cil_tmp18) {
      {
#line 5356
      __cil_tmp19 = (struct drm_framebuffer *)0;
#line 5356
      __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 5356
      __cil_tmp21 = crtc->fb;
#line 5356
      __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 5356
      if (__cil_tmp22 != __cil_tmp20) {
#line 5357
        base = intel_crtc->cursor_addr;
        {
#line 5358
        __cil_tmp23 = crtc->fb;
#line 5358
        __cil_tmp24 = __cil_tmp23->width;
#line 5358
        __cil_tmp25 = (int )__cil_tmp24;
#line 5358
        if (__cil_tmp25 < x) {
#line 5359
          base = 0U;
        } else {

        }
        }
        {
#line 5361
        __cil_tmp26 = crtc->fb;
#line 5361
        __cil_tmp27 = __cil_tmp26->height;
#line 5361
        __cil_tmp28 = (int )__cil_tmp27;
#line 5361
        if (__cil_tmp28 < y) {
#line 5362
          base = 0U;
        } else {

        }
        }
      } else {
#line 5364
        base = 0U;
      }
      }
    } else {
#line 5364
      base = 0U;
    }
    }
  } else {
#line 5364
    base = 0U;
  }
#line 5366
  if (x < 0) {
    {
#line 5367
    __cil_tmp29 = intel_crtc->cursor_width;
#line 5367
    __cil_tmp30 = (int )__cil_tmp29;
#line 5367
    __cil_tmp31 = __cil_tmp30 + x;
#line 5367
    if (__cil_tmp31 < 0) {
#line 5368
      base = 0U;
    } else {

    }
    }
#line 5370
    pos = pos | 32768U;
#line 5371
    x = - x;
  } else {

  }
#line 5373
  __cil_tmp32 = (u32 )x;
#line 5373
  pos = pos | __cil_tmp32;
#line 5375
  if (y < 0) {
    {
#line 5376
    __cil_tmp33 = intel_crtc->cursor_height;
#line 5376
    __cil_tmp34 = (int )__cil_tmp33;
#line 5376
    __cil_tmp35 = __cil_tmp34 + y;
#line 5376
    if (__cil_tmp35 < 0) {
#line 5377
      base = 0U;
    } else {

    }
    }
#line 5379
    pos = pos | 2147483648U;
#line 5380
    y = - y;
  } else {

  }
#line 5382
  __cil_tmp36 = y << 16;
#line 5382
  __cil_tmp37 = (u32 )__cil_tmp36;
#line 5382
  pos = __cil_tmp37 | pos;
#line 5384
  __cil_tmp38 = base != 0U;
#line 5384
  visible = (bool )__cil_tmp38;
#line 5385
  if (! visible) {
    {
#line 5385
    __cil_tmp39 = intel_crtc->cursor_visible;
#line 5385
    if (! __cil_tmp39) {
#line 5386
      return;
    } else {

    }
    }
  } else {

  }
  {
#line 5388
  __cil_tmp40 = pipe * 64;
#line 5388
  __cil_tmp41 = __cil_tmp40 + 458888;
#line 5388
  __cil_tmp42 = (u32 )__cil_tmp41;
#line 5388
  i915_write32___4(dev_priv, __cil_tmp42, pos);
  }
  {
#line 5389
  __cil_tmp43 = dev->pci_device;
#line 5389
  if (__cil_tmp43 == 9570) {
    {
#line 5390
    i845_update_cursor(crtc, base);
    }
  } else {
    {
#line 5389
    __cil_tmp44 = dev->pci_device;
#line 5389
    if (__cil_tmp44 == 9586) {
      {
#line 5390
      i845_update_cursor(crtc, base);
      }
    } else {
      {
#line 5392
      i9xx_update_cursor(crtc, base);
      }
    }
    }
  }
  }
#line 5394
  if ((int )visible) {
    {
#line 5395
    __cil_tmp45 = crtc->fb;
#line 5395
    __mptr___0 = (struct drm_framebuffer  const  *)__cil_tmp45;
#line 5395
    __cil_tmp46 = (struct intel_framebuffer *)__mptr___0;
#line 5395
    __cil_tmp47 = __cil_tmp46->obj;
#line 5395
    intel_mark_busy(dev, __cil_tmp47);
    }
  } else {

  }
#line 5396
  return;
}
}
#line 5398 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_crtc_cursor_set(struct drm_crtc *crtc , struct drm_file *file , uint32_t handle ,
                                 uint32_t width , uint32_t height ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct drm_i915_gem_object *obj ;
  uint32_t addr ;
  int ret ;
  struct drm_gem_object  const  *__mptr___0 ;
  struct drm_gem_object *tmp ;
  int align ;
  int tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp18 ;
  struct mutex *__cil_tmp19 ;
  struct drm_gem_object *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_gem_object *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  uint32_t __cil_tmp24 ;
  uint32_t __cil_tmp25 ;
  size_t __cil_tmp26 ;
  size_t __cil_tmp27 ;
  struct mutex *__cil_tmp28 ;
  struct intel_device_info  const  *__cil_tmp29 ;
  unsigned char *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  unsigned char *__cil_tmp34 ;
  unsigned char *__cil_tmp35 ;
  unsigned char __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  bool __cil_tmp38 ;
  bool __cil_tmp39 ;
  int __cil_tmp40 ;
  enum pipe __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  struct drm_i915_gem_phys_object *__cil_tmp43 ;
  drm_dma_handle_t *__cil_tmp44 ;
  dma_addr_t __cil_tmp45 ;
  void *__cil_tmp46 ;
  struct drm_i915_private *__cil_tmp47 ;
  struct intel_device_info  const  *__cil_tmp48 ;
  u8 __cil_tmp49 ;
  unsigned char __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  uint32_t __cil_tmp52 ;
  unsigned int __cil_tmp53 ;
  struct drm_i915_gem_object *__cil_tmp54 ;
  unsigned long __cil_tmp55 ;
  struct drm_i915_gem_object *__cil_tmp56 ;
  unsigned long __cil_tmp57 ;
  struct intel_device_info  const  *__cil_tmp58 ;
  unsigned char *__cil_tmp59 ;
  unsigned char *__cil_tmp60 ;
  unsigned char __cil_tmp61 ;
  unsigned int __cil_tmp62 ;
  unsigned long __cil_tmp63 ;
  struct drm_i915_gem_object *__cil_tmp64 ;
  unsigned long __cil_tmp65 ;
  struct drm_i915_gem_object *__cil_tmp66 ;
  struct drm_i915_gem_object *__cil_tmp67 ;
  struct drm_i915_gem_object *__cil_tmp68 ;
  struct drm_gem_object *__cil_tmp69 ;
  struct mutex *__cil_tmp70 ;
  bool __cil_tmp71 ;
  struct mutex *__cil_tmp72 ;
  struct drm_gem_object *__cil_tmp73 ;

  {
  {
#line 5403
  dev = crtc->dev;
#line 5404
  __cil_tmp18 = dev->dev_private;
#line 5404
  dev_priv = (struct drm_i915_private *)__cil_tmp18;
#line 5405
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5405
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5410
  drm_ut_debug_printk(4U, "drm", "intel_crtc_cursor_set", "\n");
  }
#line 5413
  if (handle == 0U) {
    {
#line 5414
    drm_ut_debug_printk(4U, "drm", "intel_crtc_cursor_set", "cursor off\n");
#line 5415
    addr = 0U;
#line 5416
    obj = (struct drm_i915_gem_object *)0;
#line 5417
    __cil_tmp19 = & dev->struct_mutex;
#line 5417
    mutex_lock_nested(__cil_tmp19, 0U);
    }
#line 5418
    goto finish;
  } else {

  }
#line 5422
  if (width != 64U) {
    {
#line 5423
    drm_err("intel_crtc_cursor_set", "we currently only support 64x64 cursors\n");
    }
#line 5424
    return (-22);
  } else
#line 5422
  if (height != 64U) {
    {
#line 5423
    drm_err("intel_crtc_cursor_set", "we currently only support 64x64 cursors\n");
    }
#line 5424
    return (-22);
  } else {

  }
  {
#line 5427
  tmp = drm_gem_object_lookup(dev, file, handle);
#line 5427
  __mptr___0 = (struct drm_gem_object  const  *)tmp;
#line 5427
  obj = (struct drm_i915_gem_object *)__mptr___0;
  }
  {
#line 5428
  __cil_tmp20 = (struct drm_gem_object *)0;
#line 5428
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 5428
  __cil_tmp22 = & obj->base;
#line 5428
  __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 5428
  if (__cil_tmp23 == __cil_tmp21) {
#line 5429
    return (-2);
  } else {

  }
  }
  {
#line 5431
  __cil_tmp24 = width * height;
#line 5431
  __cil_tmp25 = __cil_tmp24 * 4U;
#line 5431
  __cil_tmp26 = (size_t )__cil_tmp25;
#line 5431
  __cil_tmp27 = obj->base.size;
#line 5431
  if (__cil_tmp27 < __cil_tmp26) {
    {
#line 5432
    drm_err("intel_crtc_cursor_set", "buffer is to small\n");
#line 5433
    ret = -12;
    }
#line 5434
    goto fail;
  } else {

  }
  }
  {
#line 5438
  __cil_tmp28 = & dev->struct_mutex;
#line 5438
  mutex_lock_nested(__cil_tmp28, 0U);
  }
  {
#line 5439
  __cil_tmp29 = dev_priv->info;
#line 5439
  __cil_tmp30 = (unsigned char *)__cil_tmp29;
#line 5439
  __cil_tmp31 = __cil_tmp30 + 2UL;
#line 5439
  __cil_tmp32 = *__cil_tmp31;
#line 5439
  __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 5439
  if (__cil_tmp33 == 0U) {
    {
#line 5440
    __cil_tmp34 = (unsigned char *)obj;
#line 5440
    __cil_tmp35 = __cil_tmp34 + 225UL;
#line 5440
    __cil_tmp36 = *__cil_tmp35;
#line 5440
    __cil_tmp37 = (unsigned int )__cil_tmp36;
#line 5440
    if (__cil_tmp37 != 0U) {
      {
#line 5441
      drm_err("intel_crtc_cursor_set", "cursor cannot be tiled\n");
#line 5442
      ret = -22;
      }
#line 5443
      goto fail_locked;
    } else {

    }
    }
    {
#line 5446
    __cil_tmp38 = (bool )1;
#line 5446
    ret = i915_gem_object_pin(obj, 4096U, __cil_tmp38);
    }
#line 5447
    if (ret != 0) {
      {
#line 5448
      drm_err("intel_crtc_cursor_set", "failed to pin cursor bo\n");
      }
#line 5449
      goto fail_locked;
    } else {

    }
    {
#line 5452
    __cil_tmp39 = (bool )0;
#line 5452
    ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp39);
    }
#line 5453
    if (ret != 0) {
      {
#line 5454
      drm_err("intel_crtc_cursor_set", "failed to move cursor bo into the GTT\n");
      }
#line 5455
      goto fail_unpin;
    } else {

    }
    {
#line 5458
    ret = i915_gem_object_put_fence(obj);
    }
#line 5459
    if (ret != 0) {
      {
#line 5460
      drm_err("intel_crtc_cursor_set", "failed to move cursor bo into the GTT\n");
      }
#line 5461
      goto fail_unpin;
    } else {

    }
#line 5464
    addr = obj->gtt_offset;
  } else {
    {
#line 5466
    __cil_tmp40 = dev->pci_device;
#line 5466
    if (__cil_tmp40 == 13687) {
#line 5466
      tmp___0 = 16384;
    } else {
#line 5466
      tmp___0 = 256;
    }
    }
#line 5466
    align = tmp___0;
    {
#line 5467
    __cil_tmp41 = intel_crtc->pipe;
#line 5467
    __cil_tmp42 = (unsigned int )__cil_tmp41;
#line 5467
    if (__cil_tmp42 == 0U) {
#line 5467
      tmp___1 = 1;
    } else {
#line 5467
      tmp___1 = 2;
    }
    }
    {
#line 5467
    ret = i915_gem_attach_phys_object(dev, obj, tmp___1, align);
    }
#line 5470
    if (ret != 0) {
      {
#line 5471
      drm_err("intel_crtc_cursor_set", "failed to attach phys object\n");
      }
#line 5472
      goto fail_locked;
    } else {

    }
#line 5474
    __cil_tmp43 = obj->phys_obj;
#line 5474
    __cil_tmp44 = __cil_tmp43->handle;
#line 5474
    __cil_tmp45 = __cil_tmp44->busaddr;
#line 5474
    addr = (uint32_t )__cil_tmp45;
  }
  }
  {
#line 5477
  __cil_tmp46 = dev->dev_private;
#line 5477
  __cil_tmp47 = (struct drm_i915_private *)__cil_tmp46;
#line 5477
  __cil_tmp48 = __cil_tmp47->info;
#line 5477
  __cil_tmp49 = __cil_tmp48->gen;
#line 5477
  __cil_tmp50 = (unsigned char )__cil_tmp49;
#line 5477
  __cil_tmp51 = (unsigned int )__cil_tmp50;
#line 5477
  if (__cil_tmp51 == 2U) {
    {
#line 5478
    __cil_tmp52 = height << 12;
#line 5478
    __cil_tmp53 = __cil_tmp52 | width;
#line 5478
    i915_write32___4(dev_priv, 458912U, __cil_tmp53);
    }
  } else {

  }
  }
  finish: ;
  {
#line 5481
  __cil_tmp54 = (struct drm_i915_gem_object *)0;
#line 5481
  __cil_tmp55 = (unsigned long )__cil_tmp54;
#line 5481
  __cil_tmp56 = intel_crtc->cursor_bo;
#line 5481
  __cil_tmp57 = (unsigned long )__cil_tmp56;
#line 5481
  if (__cil_tmp57 != __cil_tmp55) {
    {
#line 5482
    __cil_tmp58 = dev_priv->info;
#line 5482
    __cil_tmp59 = (unsigned char *)__cil_tmp58;
#line 5482
    __cil_tmp60 = __cil_tmp59 + 2UL;
#line 5482
    __cil_tmp61 = *__cil_tmp60;
#line 5482
    __cil_tmp62 = (unsigned int )__cil_tmp61;
#line 5482
    if (__cil_tmp62 != 0U) {
      {
#line 5483
      __cil_tmp63 = (unsigned long )obj;
#line 5483
      __cil_tmp64 = intel_crtc->cursor_bo;
#line 5483
      __cil_tmp65 = (unsigned long )__cil_tmp64;
#line 5483
      if (__cil_tmp65 != __cil_tmp63) {
        {
#line 5484
        __cil_tmp66 = intel_crtc->cursor_bo;
#line 5484
        i915_gem_detach_phys_object(dev, __cil_tmp66);
        }
      } else {
        {
#line 5486
        __cil_tmp67 = intel_crtc->cursor_bo;
#line 5486
        i915_gem_object_unpin(__cil_tmp67);
        }
      }
      }
    } else {

    }
    }
    {
#line 5487
    __cil_tmp68 = intel_crtc->cursor_bo;
#line 5487
    __cil_tmp69 = & __cil_tmp68->base;
#line 5487
    drm_gem_object_unreference(__cil_tmp69);
    }
  } else {

  }
  }
  {
#line 5490
  __cil_tmp70 = & dev->struct_mutex;
#line 5490
  mutex_unlock(__cil_tmp70);
#line 5492
  intel_crtc->cursor_addr = addr;
#line 5493
  intel_crtc->cursor_bo = obj;
#line 5494
  intel_crtc->cursor_width = (int16_t )width;
#line 5495
  intel_crtc->cursor_height = (int16_t )height;
#line 5497
  __cil_tmp71 = (bool )1;
#line 5497
  intel_crtc_update_cursor(crtc, __cil_tmp71);
  }
#line 5499
  return (0);
  fail_unpin: 
  {
#line 5501
  i915_gem_object_unpin(obj);
  }
  fail_locked: 
  {
#line 5503
  __cil_tmp72 = & dev->struct_mutex;
#line 5503
  mutex_unlock(__cil_tmp72);
  }
  fail: 
  {
#line 5505
  __cil_tmp73 = & obj->base;
#line 5505
  drm_gem_object_unreference_unlocked(__cil_tmp73);
  }
#line 5506
  return (ret);
}
}
#line 5509 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_crtc_cursor_move(struct drm_crtc *crtc , int x , int y ) 
{ struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  bool __cil_tmp6 ;

  {
  {
#line 5511
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5511
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5513
  intel_crtc->cursor_x = (int16_t )x;
#line 5514
  intel_crtc->cursor_y = (int16_t )y;
#line 5516
  __cil_tmp6 = (bool )1;
#line 5516
  intel_crtc_update_cursor(crtc, __cil_tmp6);
  }
#line 5518
  return (0);
}
}
#line 5522 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc , u16 red , u16 green , u16 blue ,
                             int regno ) 
{ struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;

  {
#line 5525
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5525
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5527
  __cil_tmp8 = (int )red;
#line 5527
  __cil_tmp9 = __cil_tmp8 >> 8;
#line 5527
  intel_crtc->lut_r[regno] = (u8 )__cil_tmp9;
#line 5528
  __cil_tmp10 = (int )green;
#line 5528
  __cil_tmp11 = __cil_tmp10 >> 8;
#line 5528
  intel_crtc->lut_g[regno] = (u8 )__cil_tmp11;
#line 5529
  __cil_tmp12 = (int )blue;
#line 5529
  __cil_tmp13 = __cil_tmp12 >> 8;
#line 5529
  intel_crtc->lut_b[regno] = (u8 )__cil_tmp13;
#line 5530
  return;
}
}
#line 5532 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc , u16 *red , u16 *green , u16 *blue ,
                             int regno ) 
{ struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  u8 __cil_tmp8 ;
  u16 __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  u8 __cil_tmp12 ;
  u16 __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  u8 __cil_tmp16 ;
  u16 __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;

  {
#line 5535
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5535
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5537
  __cil_tmp8 = intel_crtc->lut_r[regno];
#line 5537
  __cil_tmp9 = (u16 )__cil_tmp8;
#line 5537
  __cil_tmp10 = (int )__cil_tmp9;
#line 5537
  __cil_tmp11 = __cil_tmp10 << 8U;
#line 5537
  *red = (u16 )__cil_tmp11;
#line 5538
  __cil_tmp12 = intel_crtc->lut_g[regno];
#line 5538
  __cil_tmp13 = (u16 )__cil_tmp12;
#line 5538
  __cil_tmp14 = (int )__cil_tmp13;
#line 5538
  __cil_tmp15 = __cil_tmp14 << 8U;
#line 5538
  *green = (u16 )__cil_tmp15;
#line 5539
  __cil_tmp16 = intel_crtc->lut_b[regno];
#line 5539
  __cil_tmp17 = (u16 )__cil_tmp16;
#line 5539
  __cil_tmp18 = (int )__cil_tmp17;
#line 5539
  __cil_tmp19 = __cil_tmp18 << 8U;
#line 5539
  *blue = (u16 )__cil_tmp19;
#line 5540
  return;
}
}
#line 5542 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_crtc_gamma_set(struct drm_crtc *crtc , u16 *red , u16 *green , u16 *blue ,
                                 uint32_t start , uint32_t size ) 
{ int end ;
  unsigned int tmp ;
  int i ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  uint32_t __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  u16 *__cil_tmp14 ;
  u16 __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  u16 *__cil_tmp19 ;
  u16 __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  u16 *__cil_tmp24 ;
  u16 __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;

  {
  {
#line 5545
  __cil_tmp12 = start + size;
#line 5545
  if (256U < __cil_tmp12) {
#line 5545
    tmp = 256U;
  } else {
#line 5545
    tmp = start + size;
  }
  }
#line 5545
  end = (int )tmp;
#line 5546
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5546
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5548
  i = (int )start;
#line 5548
  goto ldv_39705;
  ldv_39704: 
#line 5549
  __cil_tmp13 = (unsigned long )i;
#line 5549
  __cil_tmp14 = red + __cil_tmp13;
#line 5549
  __cil_tmp15 = *__cil_tmp14;
#line 5549
  __cil_tmp16 = (int )__cil_tmp15;
#line 5549
  __cil_tmp17 = __cil_tmp16 >> 8;
#line 5549
  intel_crtc->lut_r[i] = (u8 )__cil_tmp17;
#line 5550
  __cil_tmp18 = (unsigned long )i;
#line 5550
  __cil_tmp19 = green + __cil_tmp18;
#line 5550
  __cil_tmp20 = *__cil_tmp19;
#line 5550
  __cil_tmp21 = (int )__cil_tmp20;
#line 5550
  __cil_tmp22 = __cil_tmp21 >> 8;
#line 5550
  intel_crtc->lut_g[i] = (u8 )__cil_tmp22;
#line 5551
  __cil_tmp23 = (unsigned long )i;
#line 5551
  __cil_tmp24 = blue + __cil_tmp23;
#line 5551
  __cil_tmp25 = *__cil_tmp24;
#line 5551
  __cil_tmp26 = (int )__cil_tmp25;
#line 5551
  __cil_tmp27 = __cil_tmp26 >> 8;
#line 5551
  intel_crtc->lut_b[i] = (u8 )__cil_tmp27;
#line 5548
  i = i + 1;
  ldv_39705: ;
#line 5548
  if (i < end) {
#line 5549
    goto ldv_39704;
  } else {
#line 5551
    goto ldv_39706;
  }
  ldv_39706: 
  {
#line 5554
  intel_crtc_load_lut(crtc);
  }
#line 5555
  return;
}
}
#line 5572 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_display_mode load_detect_mode  = 
#line 5572
     {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'6', (char )'4',
                                                               (char )'0', (char )'x',
                                                               (char )'4', (char )'8',
                                                               (char )'0', (char )'\000'},
    0, (enum drm_mode_status )0, 16, 31500, 640, 664, 704, 832, 0, 480, 489, 491,
    520, 0, 10U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
    0, 0, 0};
#line 5578 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_framebuffer *intel_framebuffer_create(struct drm_device *dev , struct drm_mode_fb_cmd *mode_cmd ,
                                                        struct drm_i915_gem_object *obj ) 
{ struct intel_framebuffer *intel_fb ;
  int ret ;
  void *tmp ;
  void *tmp___0 ;
  void *tmp___1 ;
  struct intel_framebuffer *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct drm_gem_object *__cil_tmp12 ;
  struct drm_gem_object *__cil_tmp13 ;
  void const   *__cil_tmp14 ;
  long __cil_tmp15 ;

  {
  {
#line 5585
  tmp = kzalloc(96UL, 208U);
#line 5585
  intel_fb = (struct intel_framebuffer *)tmp;
  }
  {
#line 5586
  __cil_tmp9 = (struct intel_framebuffer *)0;
#line 5586
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 5586
  __cil_tmp11 = (unsigned long )intel_fb;
#line 5586
  if (__cil_tmp11 == __cil_tmp10) {
    {
#line 5587
    __cil_tmp12 = & obj->base;
#line 5587
    drm_gem_object_unreference_unlocked(__cil_tmp12);
#line 5588
    tmp___0 = ERR_PTR(-12L);
    }
#line 5588
    return ((struct drm_framebuffer *)tmp___0);
  } else {

  }
  }
  {
#line 5591
  ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  }
#line 5592
  if (ret != 0) {
    {
#line 5593
    __cil_tmp13 = & obj->base;
#line 5593
    drm_gem_object_unreference_unlocked(__cil_tmp13);
#line 5594
    __cil_tmp14 = (void const   *)intel_fb;
#line 5594
    kfree(__cil_tmp14);
#line 5595
    __cil_tmp15 = (long )ret;
#line 5595
    tmp___1 = ERR_PTR(__cil_tmp15);
    }
#line 5595
    return ((struct drm_framebuffer *)tmp___1);
  } else {

  }
#line 5598
  return (& intel_fb->base);
}
}
#line 5602 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static u32 intel_framebuffer_pitch_for_width(int width , int bpp ) 
{ u32 pitch ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  u32 __cil_tmp7 ;

  {
#line 5604
  __cil_tmp4 = width * bpp;
#line 5604
  __cil_tmp5 = __cil_tmp4 + 7;
#line 5604
  __cil_tmp6 = __cil_tmp5 / 8;
#line 5604
  pitch = (u32 )__cil_tmp6;
  {
#line 5605
  __cil_tmp7 = pitch + 63U;
#line 5605
  return (__cil_tmp7 & 4294967232U);
  }
}
}
#line 5609 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static u32 intel_framebuffer_size_for_mode(struct drm_display_mode *mode , int bpp ) 
{ u32 pitch ;
  u32 tmp ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  u32 __cil_tmp7 ;
  u32 __cil_tmp8 ;
  u32 __cil_tmp9 ;

  {
  {
#line 5611
  __cil_tmp5 = mode->hdisplay;
#line 5611
  tmp = intel_framebuffer_pitch_for_width(__cil_tmp5, bpp);
#line 5611
  pitch = tmp;
  }
  {
#line 5612
  __cil_tmp6 = mode->vdisplay;
#line 5612
  __cil_tmp7 = (u32 )__cil_tmp6;
#line 5612
  __cil_tmp8 = __cil_tmp7 * pitch;
#line 5612
  __cil_tmp9 = __cil_tmp8 + 4095U;
#line 5612
  return (__cil_tmp9 & 4294963200U);
  }
}
}
#line 5616 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_framebuffer *intel_framebuffer_create_for_mode(struct drm_device *dev ,
                                                                 struct drm_display_mode *mode ,
                                                                 int depth , int bpp ) 
{ struct drm_i915_gem_object *obj ;
  struct drm_mode_fb_cmd mode_cmd ;
  u32 tmp ;
  void *tmp___0 ;
  struct drm_framebuffer *tmp___1 ;
  size_t __cil_tmp10 ;
  struct drm_i915_gem_object *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;

  {
  {
#line 5623
  tmp = intel_framebuffer_size_for_mode(mode, bpp);
#line 5623
  __cil_tmp10 = (size_t )tmp;
#line 5623
  obj = i915_gem_alloc_object(dev, __cil_tmp10);
  }
  {
#line 5625
  __cil_tmp11 = (struct drm_i915_gem_object *)0;
#line 5625
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 5625
  __cil_tmp13 = (unsigned long )obj;
#line 5625
  if (__cil_tmp13 == __cil_tmp12) {
    {
#line 5626
    tmp___0 = ERR_PTR(-12L);
    }
#line 5626
    return ((struct drm_framebuffer *)tmp___0);
  } else {

  }
  }
  {
#line 5628
  __cil_tmp14 = mode->hdisplay;
#line 5628
  mode_cmd.width = (__u32 )__cil_tmp14;
#line 5629
  __cil_tmp15 = mode->vdisplay;
#line 5629
  mode_cmd.height = (__u32 )__cil_tmp15;
#line 5630
  mode_cmd.depth = (__u32 )depth;
#line 5631
  mode_cmd.bpp = (__u32 )bpp;
#line 5632
  __cil_tmp16 = (int )mode_cmd.width;
#line 5632
  mode_cmd.pitch = intel_framebuffer_pitch_for_width(__cil_tmp16, bpp);
#line 5634
  tmp___1 = intel_framebuffer_create(dev, & mode_cmd, obj);
  }
#line 5634
  return (tmp___1);
}
}
#line 5638 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_framebuffer *mode_fits_in_fbdev(struct drm_device *dev , struct drm_display_mode *mode ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_i915_gem_object *obj ;
  struct drm_framebuffer *fb ;
  u32 tmp ;
  void *__cil_tmp7 ;
  struct intel_fbdev *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct intel_fbdev *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct intel_fbdev *__cil_tmp12 ;
  struct drm_i915_gem_object *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct intel_fbdev *__cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  size_t __cil_tmp24 ;
  size_t __cil_tmp25 ;

  {
#line 5641
  __cil_tmp7 = dev->dev_private;
#line 5641
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
  {
#line 5645
  __cil_tmp8 = (struct intel_fbdev *)0;
#line 5645
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 5645
  __cil_tmp10 = dev_priv->fbdev;
#line 5645
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 5645
  if (__cil_tmp11 == __cil_tmp9) {
#line 5646
    return ((struct drm_framebuffer *)0);
  } else {

  }
  }
#line 5648
  __cil_tmp12 = dev_priv->fbdev;
#line 5648
  obj = __cil_tmp12->ifb.obj;
  {
#line 5649
  __cil_tmp13 = (struct drm_i915_gem_object *)0;
#line 5649
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 5649
  __cil_tmp15 = (unsigned long )obj;
#line 5649
  if (__cil_tmp15 == __cil_tmp14) {
#line 5650
    return ((struct drm_framebuffer *)0);
  } else {

  }
  }
  {
#line 5652
  __cil_tmp16 = dev_priv->fbdev;
#line 5652
  fb = & __cil_tmp16->ifb.base;
#line 5653
  __cil_tmp17 = mode->hdisplay;
#line 5653
  __cil_tmp18 = fb->bits_per_pixel;
#line 5653
  tmp = intel_framebuffer_pitch_for_width(__cil_tmp17, __cil_tmp18);
  }
  {
#line 5653
  __cil_tmp19 = fb->pitch;
#line 5653
  if (__cil_tmp19 < tmp) {
#line 5655
    return ((struct drm_framebuffer *)0);
  } else {

  }
  }
  {
#line 5657
  __cil_tmp20 = fb->pitch;
#line 5657
  __cil_tmp21 = mode->vdisplay;
#line 5657
  __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 5657
  __cil_tmp23 = __cil_tmp22 * __cil_tmp20;
#line 5657
  __cil_tmp24 = (size_t )__cil_tmp23;
#line 5657
  __cil_tmp25 = obj->base.size;
#line 5657
  if (__cil_tmp25 < __cil_tmp24) {
#line 5658
    return ((struct drm_framebuffer *)0);
  } else {

  }
  }
#line 5660
  return (fb);
}
}
#line 5663 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder , struct drm_connector *connector ,
                                struct drm_display_mode *mode , struct intel_load_detect_pipe *old ) 
{ struct intel_crtc *intel_crtc ;
  struct drm_crtc *possible_crtc ;
  struct drm_encoder *encoder ;
  struct drm_crtc *crtc ;
  struct drm_device *dev ;
  struct drm_framebuffer *old_fb ;
  int i ;
  char *tmp ;
  char *tmp___0 ;
  struct drm_crtc  const  *__mptr ;
  struct drm_encoder_helper_funcs *encoder_funcs ;
  struct drm_crtc_helper_funcs *crtc_funcs ;
  struct list_head  const  *__mptr___0 ;
  struct list_head  const  *__mptr___1 ;
  struct drm_crtc  const  *__mptr___2 ;
  long tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  uint32_t __cil_tmp23 ;
  uint32_t __cil_tmp24 ;
  struct drm_crtc *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  struct drm_crtc *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  int __cil_tmp29 ;
  void *__cil_tmp30 ;
  void (*__cil_tmp31)(struct drm_crtc * , int  ) ;
  void *__cil_tmp32 ;
  void (*__cil_tmp33)(struct drm_encoder * , int  ) ;
  struct list_head *__cil_tmp34 ;
  struct drm_crtc *__cil_tmp35 ;
  int __cil_tmp36 ;
  uint32_t __cil_tmp37 ;
  uint32_t __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  bool __cil_tmp40 ;
  struct list_head *__cil_tmp41 ;
  struct drm_crtc *__cil_tmp42 ;
  struct list_head *__cil_tmp43 ;
  unsigned long __cil_tmp44 ;
  struct list_head *__cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  struct drm_crtc *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  unsigned long __cil_tmp49 ;
  struct drm_display_mode *__cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  struct drm_framebuffer *__cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  struct drm_framebuffer *__cil_tmp55 ;
  unsigned long __cil_tmp56 ;
  struct drm_framebuffer *__cil_tmp57 ;
  void const   *__cil_tmp58 ;
  struct drm_framebuffer *__cil_tmp59 ;
  unsigned long __cil_tmp60 ;
  struct drm_framebuffer *__cil_tmp61 ;
  unsigned long __cil_tmp62 ;
  struct drm_framebuffer *__cil_tmp63 ;
  struct drm_framebuffer_funcs  const  *__cil_tmp64 ;
  void (*__cil_tmp65)(struct drm_framebuffer * ) ;
  struct drm_framebuffer *__cil_tmp66 ;
  enum pipe __cil_tmp67 ;
  int __cil_tmp68 ;

  {
  {
#line 5670
  encoder = & intel_encoder->base;
#line 5671
  crtc = (struct drm_crtc *)0;
#line 5672
  dev = encoder->dev;
#line 5674
  i = -1;
#line 5676
  tmp = drm_get_encoder_name(encoder);
#line 5676
  tmp___0 = drm_get_connector_name(connector);
#line 5676
  __cil_tmp23 = connector->base.id;
#line 5676
  __cil_tmp24 = encoder->base.id;
#line 5676
  drm_ut_debug_printk(4U, "drm", "intel_get_load_detect_pipe", "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
                      __cil_tmp23, tmp___0, __cil_tmp24, tmp);
  }
  {
#line 5691
  __cil_tmp25 = (struct drm_crtc *)0;
#line 5691
  __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 5691
  __cil_tmp27 = encoder->crtc;
#line 5691
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 5691
  if (__cil_tmp28 != __cil_tmp26) {
#line 5692
    crtc = encoder->crtc;
#line 5694
    __mptr = (struct drm_crtc  const  *)crtc;
#line 5694
    intel_crtc = (struct intel_crtc *)__mptr;
#line 5695
    old->dpms_mode = intel_crtc->dpms_mode;
#line 5696
    old->load_detect_temp = (bool )0;
    {
#line 5699
    __cil_tmp29 = intel_crtc->dpms_mode;
#line 5699
    if (__cil_tmp29 != 0) {
      {
#line 5703
      __cil_tmp30 = crtc->helper_private;
#line 5703
      crtc_funcs = (struct drm_crtc_helper_funcs *)__cil_tmp30;
#line 5704
      __cil_tmp31 = crtc_funcs->dpms;
#line 5704
      (*__cil_tmp31)(crtc, 0);
#line 5706
      __cil_tmp32 = encoder->helper_private;
#line 5706
      encoder_funcs = (struct drm_encoder_helper_funcs *)__cil_tmp32;
#line 5707
      __cil_tmp33 = encoder_funcs->dpms;
#line 5707
      (*__cil_tmp33)(encoder, 0);
      }
    } else {

    }
    }
#line 5710
    return ((bool )1);
  } else {

  }
  }
#line 5714
  __cil_tmp34 = dev->mode_config.crtc_list.next;
#line 5714
  __mptr___0 = (struct list_head  const  *)__cil_tmp34;
#line 5714
  __cil_tmp35 = (struct drm_crtc *)__mptr___0;
#line 5714
  possible_crtc = __cil_tmp35 + 1152921504606846968UL;
#line 5714
  goto ldv_39765;
  ldv_39764: 
#line 5715
  i = i + 1;
  {
#line 5716
  __cil_tmp36 = 1 << i;
#line 5716
  __cil_tmp37 = (uint32_t )__cil_tmp36;
#line 5716
  __cil_tmp38 = encoder->possible_crtcs;
#line 5716
  __cil_tmp39 = __cil_tmp38 & __cil_tmp37;
#line 5716
  if (__cil_tmp39 == 0U) {
#line 5717
    goto ldv_39762;
  } else {

  }
  }
  {
#line 5718
  __cil_tmp40 = possible_crtc->enabled;
#line 5718
  if (! __cil_tmp40) {
#line 5719
    crtc = possible_crtc;
#line 5720
    goto ldv_39763;
  } else {

  }
  }
  ldv_39762: 
#line 5714
  __cil_tmp41 = possible_crtc->head.next;
#line 5714
  __mptr___1 = (struct list_head  const  *)__cil_tmp41;
#line 5714
  __cil_tmp42 = (struct drm_crtc *)__mptr___1;
#line 5714
  possible_crtc = __cil_tmp42 + 1152921504606846968UL;
  ldv_39765: ;
  {
#line 5714
  __cil_tmp43 = & dev->mode_config.crtc_list;
#line 5714
  __cil_tmp44 = (unsigned long )__cil_tmp43;
#line 5714
  __cil_tmp45 = & possible_crtc->head;
#line 5714
  __cil_tmp46 = (unsigned long )__cil_tmp45;
#line 5714
  if (__cil_tmp46 != __cil_tmp44) {
#line 5715
    goto ldv_39764;
  } else {
#line 5717
    goto ldv_39763;
  }
  }
  ldv_39763: ;
  {
#line 5727
  __cil_tmp47 = (struct drm_crtc *)0;
#line 5727
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 5727
  __cil_tmp49 = (unsigned long )crtc;
#line 5727
  if (__cil_tmp49 == __cil_tmp48) {
    {
#line 5728
    drm_ut_debug_printk(4U, "drm", "intel_get_load_detect_pipe", "no pipe available for load-detect\n");
    }
#line 5729
    return ((bool )0);
  } else {

  }
  }
#line 5732
  encoder->crtc = crtc;
#line 5733
  connector->encoder = encoder;
#line 5735
  __mptr___2 = (struct drm_crtc  const  *)crtc;
#line 5735
  intel_crtc = (struct intel_crtc *)__mptr___2;
#line 5736
  old->dpms_mode = intel_crtc->dpms_mode;
#line 5737
  old->load_detect_temp = (bool )1;
#line 5738
  old->release_fb = (struct drm_framebuffer *)0;
  {
#line 5740
  __cil_tmp50 = (struct drm_display_mode *)0;
#line 5740
  __cil_tmp51 = (unsigned long )__cil_tmp50;
#line 5740
  __cil_tmp52 = (unsigned long )mode;
#line 5740
  if (__cil_tmp52 == __cil_tmp51) {
#line 5741
    mode = & load_detect_mode;
  } else {

  }
  }
  {
#line 5743
  old_fb = crtc->fb;
#line 5752
  crtc->fb = mode_fits_in_fbdev(dev, mode);
  }
  {
#line 5753
  __cil_tmp53 = (struct drm_framebuffer *)0;
#line 5753
  __cil_tmp54 = (unsigned long )__cil_tmp53;
#line 5753
  __cil_tmp55 = crtc->fb;
#line 5753
  __cil_tmp56 = (unsigned long )__cil_tmp55;
#line 5753
  if (__cil_tmp56 == __cil_tmp54) {
    {
#line 5754
    drm_ut_debug_printk(4U, "drm", "intel_get_load_detect_pipe", "creating tmp fb for load-detection\n");
#line 5755
    crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
#line 5756
    old->release_fb = crtc->fb;
    }
  } else {
    {
#line 5758
    drm_ut_debug_printk(4U, "drm", "intel_get_load_detect_pipe", "reusing fbdev for load-detection framebuffer\n");
    }
  }
  }
  {
#line 5759
  __cil_tmp57 = crtc->fb;
#line 5759
  __cil_tmp58 = (void const   *)__cil_tmp57;
#line 5759
  tmp___1 = IS_ERR(__cil_tmp58);
  }
#line 5759
  if (tmp___1 != 0L) {
    {
#line 5760
    drm_ut_debug_printk(4U, "drm", "intel_get_load_detect_pipe", "failed to allocate framebuffer for load-detection\n");
#line 5761
    crtc->fb = old_fb;
    }
#line 5762
    return ((bool )0);
  } else {

  }
  {
#line 5765
  tmp___2 = drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb);
  }
#line 5765
  if (tmp___2) {
#line 5765
    tmp___3 = 0;
  } else {
#line 5765
    tmp___3 = 1;
  }
#line 5765
  if (tmp___3) {
    {
#line 5766
    drm_ut_debug_printk(4U, "drm", "intel_get_load_detect_pipe", "failed to set mode on load-detect pipe\n");
    }
    {
#line 5767
    __cil_tmp59 = (struct drm_framebuffer *)0;
#line 5767
    __cil_tmp60 = (unsigned long )__cil_tmp59;
#line 5767
    __cil_tmp61 = old->release_fb;
#line 5767
    __cil_tmp62 = (unsigned long )__cil_tmp61;
#line 5767
    if (__cil_tmp62 != __cil_tmp60) {
      {
#line 5768
      __cil_tmp63 = old->release_fb;
#line 5768
      __cil_tmp64 = __cil_tmp63->funcs;
#line 5768
      __cil_tmp65 = __cil_tmp64->destroy;
#line 5768
      __cil_tmp66 = old->release_fb;
#line 5768
      (*__cil_tmp65)(__cil_tmp66);
      }
    } else {

    }
    }
#line 5769
    crtc->fb = old_fb;
#line 5770
    return ((bool )0);
  } else {

  }
  {
#line 5774
  __cil_tmp67 = intel_crtc->pipe;
#line 5774
  __cil_tmp68 = (int )__cil_tmp67;
#line 5774
  intel_wait_for_vblank(dev, __cil_tmp68);
  }
#line 5776
  return ((bool )1);
}
}
#line 5779 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder , struct drm_connector *connector ,
                                    struct intel_load_detect_pipe *old ) 
{ struct drm_encoder *encoder ;
  struct drm_device *dev ;
  struct drm_crtc *crtc ;
  struct drm_encoder_helper_funcs *encoder_funcs ;
  struct drm_crtc_helper_funcs *crtc_funcs ;
  char *tmp ;
  char *tmp___0 ;
  void *__cil_tmp11 ;
  void *__cil_tmp12 ;
  uint32_t __cil_tmp13 ;
  uint32_t __cil_tmp14 ;
  bool __cil_tmp15 ;
  struct drm_framebuffer *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_framebuffer *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  struct drm_framebuffer *__cil_tmp20 ;
  struct drm_framebuffer_funcs  const  *__cil_tmp21 ;
  void (*__cil_tmp22)(struct drm_framebuffer * ) ;
  struct drm_framebuffer *__cil_tmp23 ;
  int __cil_tmp24 ;
  void (*__cil_tmp25)(struct drm_encoder * , int  ) ;
  int __cil_tmp26 ;
  void (*__cil_tmp27)(struct drm_crtc * , int  ) ;
  int __cil_tmp28 ;

  {
  {
#line 5783
  encoder = & intel_encoder->base;
#line 5784
  dev = encoder->dev;
#line 5785
  crtc = encoder->crtc;
#line 5786
  __cil_tmp11 = encoder->helper_private;
#line 5786
  encoder_funcs = (struct drm_encoder_helper_funcs *)__cil_tmp11;
#line 5787
  __cil_tmp12 = crtc->helper_private;
#line 5787
  crtc_funcs = (struct drm_crtc_helper_funcs *)__cil_tmp12;
#line 5789
  tmp = drm_get_encoder_name(encoder);
#line 5789
  tmp___0 = drm_get_connector_name(connector);
#line 5789
  __cil_tmp13 = connector->base.id;
#line 5789
  __cil_tmp14 = encoder->base.id;
#line 5789
  drm_ut_debug_printk(4U, "drm", "intel_release_load_detect_pipe", "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
                      __cil_tmp13, tmp___0, __cil_tmp14, tmp);
  }
  {
#line 5793
  __cil_tmp15 = old->load_detect_temp;
#line 5793
  if ((int )__cil_tmp15) {
    {
#line 5794
    connector->encoder = (struct drm_encoder *)0;
#line 5795
    drm_helper_disable_unused_functions(dev);
    }
    {
#line 5797
    __cil_tmp16 = (struct drm_framebuffer *)0;
#line 5797
    __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 5797
    __cil_tmp18 = old->release_fb;
#line 5797
    __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 5797
    if (__cil_tmp19 != __cil_tmp17) {
      {
#line 5798
      __cil_tmp20 = old->release_fb;
#line 5798
      __cil_tmp21 = __cil_tmp20->funcs;
#line 5798
      __cil_tmp22 = __cil_tmp21->destroy;
#line 5798
      __cil_tmp23 = old->release_fb;
#line 5798
      (*__cil_tmp22)(__cil_tmp23);
      }
    } else {

    }
    }
#line 5800
    return;
  } else {

  }
  }
  {
#line 5804
  __cil_tmp24 = old->dpms_mode;
#line 5804
  if (__cil_tmp24 != 0) {
    {
#line 5805
    __cil_tmp25 = encoder_funcs->dpms;
#line 5805
    __cil_tmp26 = old->dpms_mode;
#line 5805
    (*__cil_tmp25)(encoder, __cil_tmp26);
#line 5806
    __cil_tmp27 = crtc_funcs->dpms;
#line 5806
    __cil_tmp28 = old->dpms_mode;
#line 5806
    (*__cil_tmp27)(crtc, __cil_tmp28);
    }
  } else {

  }
  }
#line 5808
  return;
}
}
#line 5811 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_crtc_clock_get(struct drm_device *dev , struct drm_crtc *crtc ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  u32 dpll ;
  u32 tmp ;
  u32 fp ;
  intel_clock_t clock ;
  int tmp___0 ;
  bool is_lvds ;
  u32 tmp___1 ;
  int tmp___2 ;
  void *__cil_tmp15 ;
  enum pipe __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  u32 __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  u32 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  void *__cil_tmp29 ;
  struct drm_i915_private *__cil_tmp30 ;
  struct intel_device_info  const  *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char *__cil_tmp33 ;
  unsigned char __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  int __cil_tmp42 ;
  void *__cil_tmp43 ;
  struct drm_i915_private *__cil_tmp44 ;
  struct intel_device_info  const  *__cil_tmp45 ;
  u8 __cil_tmp46 ;
  unsigned char __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  void *__cil_tmp49 ;
  struct drm_i915_private *__cil_tmp50 ;
  struct intel_device_info  const  *__cil_tmp51 ;
  unsigned char *__cil_tmp52 ;
  unsigned char *__cil_tmp53 ;
  unsigned char __cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  unsigned int __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  int __cil_tmp58 ;
  unsigned int __cil_tmp59 ;
  unsigned int __cil_tmp60 ;
  int __cil_tmp61 ;
  unsigned int __cil_tmp62 ;
  int __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  int __cil_tmp65 ;
  unsigned int __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  int __cil_tmp70 ;
  unsigned int __cil_tmp71 ;
  unsigned int __cil_tmp72 ;
  int __cil_tmp73 ;
  unsigned int __cil_tmp74 ;
  unsigned int __cil_tmp75 ;
  unsigned int __cil_tmp76 ;
  unsigned int __cil_tmp77 ;
  unsigned int __cil_tmp78 ;
  unsigned int __cil_tmp79 ;

  {
  {
#line 5813
  __cil_tmp15 = dev->dev_private;
#line 5813
  dev_priv = (struct drm_i915_private *)__cil_tmp15;
#line 5814
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5814
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5815
  __cil_tmp16 = intel_crtc->pipe;
#line 5815
  pipe = (int )__cil_tmp16;
#line 5816
  __cil_tmp17 = pipe + 6149;
#line 5816
  __cil_tmp18 = __cil_tmp17 * 4;
#line 5816
  __cil_tmp19 = (u32 )__cil_tmp18;
#line 5816
  tmp = i915_read32___6(dev_priv, __cil_tmp19);
#line 5816
  dpll = tmp;
  }
  {
#line 5820
  __cil_tmp20 = dpll & 256U;
#line 5820
  if (__cil_tmp20 == 0U) {
    {
#line 5821
    __cil_tmp21 = pipe + 3080;
#line 5821
    __cil_tmp22 = __cil_tmp21 * 8;
#line 5821
    __cil_tmp23 = (u32 )__cil_tmp22;
#line 5821
    fp = i915_read32___6(dev_priv, __cil_tmp23);
    }
  } else {
    {
#line 5823
    __cil_tmp24 = pipe * 8;
#line 5823
    __cil_tmp25 = __cil_tmp24 + 24644;
#line 5823
    __cil_tmp26 = (u32 )__cil_tmp25;
#line 5823
    fp = i915_read32___6(dev_priv, __cil_tmp26);
    }
  }
  }
#line 5825
  __cil_tmp27 = fp & 16128U;
#line 5825
  __cil_tmp28 = __cil_tmp27 >> 8;
#line 5825
  clock.m1 = (int )__cil_tmp28;
  {
#line 5826
  __cil_tmp29 = dev->dev_private;
#line 5826
  __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
#line 5826
  __cil_tmp31 = __cil_tmp30->info;
#line 5826
  __cil_tmp32 = (unsigned char *)__cil_tmp31;
#line 5826
  __cil_tmp33 = __cil_tmp32 + 1UL;
#line 5826
  __cil_tmp34 = *__cil_tmp33;
#line 5826
  __cil_tmp35 = (unsigned int )__cil_tmp34;
#line 5826
  if (__cil_tmp35 != 0U) {
    {
#line 5827
    __cil_tmp36 = fp & 16711680U;
#line 5827
    __cil_tmp37 = __cil_tmp36 >> 16;
#line 5827
    __cil_tmp38 = (int )__cil_tmp37;
#line 5827
    tmp___0 = ffs(__cil_tmp38);
#line 5827
    clock.n = tmp___0 + -1;
#line 5828
    __cil_tmp39 = (int )fp;
#line 5828
    clock.m2 = __cil_tmp39 & 255;
    }
  } else {
#line 5830
    __cil_tmp40 = fp & 4128768U;
#line 5830
    __cil_tmp41 = __cil_tmp40 >> 16;
#line 5830
    clock.n = (int )__cil_tmp41;
#line 5831
    __cil_tmp42 = (int )fp;
#line 5831
    clock.m2 = __cil_tmp42 & 63;
  }
  }
  {
#line 5834
  __cil_tmp43 = dev->dev_private;
#line 5834
  __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
#line 5834
  __cil_tmp45 = __cil_tmp44->info;
#line 5834
  __cil_tmp46 = __cil_tmp45->gen;
#line 5834
  __cil_tmp47 = (unsigned char )__cil_tmp46;
#line 5834
  __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 5834
  if (__cil_tmp48 != 2U) {
    {
#line 5835
    __cil_tmp49 = dev->dev_private;
#line 5835
    __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
#line 5835
    __cil_tmp51 = __cil_tmp50->info;
#line 5835
    __cil_tmp52 = (unsigned char *)__cil_tmp51;
#line 5835
    __cil_tmp53 = __cil_tmp52 + 1UL;
#line 5835
    __cil_tmp54 = *__cil_tmp53;
#line 5835
    __cil_tmp55 = (unsigned int )__cil_tmp54;
#line 5835
    if (__cil_tmp55 != 0U) {
      {
#line 5836
      __cil_tmp56 = dpll & 16744448U;
#line 5836
      __cil_tmp57 = __cil_tmp56 >> 15;
#line 5836
      __cil_tmp58 = (int )__cil_tmp57;
#line 5836
      clock.p1 = ffs(__cil_tmp58);
      }
    } else {
      {
#line 5839
      __cil_tmp59 = dpll & 16711680U;
#line 5839
      __cil_tmp60 = __cil_tmp59 >> 16;
#line 5839
      __cil_tmp61 = (int )__cil_tmp60;
#line 5839
      clock.p1 = ffs(__cil_tmp61);
      }
    }
    }
    {
#line 5843
    __cil_tmp62 = dpll & 201326592U;
#line 5843
    __cil_tmp63 = (int )__cil_tmp62;
#line 5843
    if (__cil_tmp63 == 67108864) {
#line 5843
      goto case_67108864;
    } else {
      {
#line 5847
      __cil_tmp64 = dpll & 201326592U;
#line 5847
      __cil_tmp65 = (int )__cil_tmp64;
#line 5847
      if (__cil_tmp65 == 134217728) {
#line 5847
        goto case_134217728;
      } else {
#line 5851
        goto switch_default;
#line 5842
        if (0) {
          case_67108864: ;
          {
#line 5844
          __cil_tmp66 = dpll & 16777216U;
#line 5844
          if (__cil_tmp66 != 0U) {
#line 5844
            clock.p2 = 5;
          } else {
#line 5844
            clock.p2 = 10;
          }
          }
#line 5846
          goto ldv_39792;
          case_134217728: ;
          {
#line 5848
          __cil_tmp67 = dpll & 16777216U;
#line 5848
          if (__cil_tmp67 != 0U) {
#line 5848
            clock.p2 = 7;
          } else {
#line 5848
            clock.p2 = 14;
          }
          }
#line 5850
          goto ldv_39792;
          switch_default: 
          {
#line 5852
          __cil_tmp68 = (int )dpll;
#line 5852
          __cil_tmp69 = __cil_tmp68 & 201326592;
#line 5852
          drm_ut_debug_printk(4U, "drm", "intel_crtc_clock_get", "Unknown DPLL mode %08x in programmed mode\n",
                              __cil_tmp69);
          }
#line 5854
          return (0);
        } else {

        }
      }
      }
    }
    }
    ldv_39792: 
    {
#line 5858
    intel_clock(dev, 96000, & clock);
    }
  } else {
#line 5860
    if (pipe == 1) {
      {
#line 5860
      tmp___1 = i915_read32___6(dev_priv, 397696U);
      }
      {
#line 5860
      __cil_tmp70 = (int )tmp___1;
#line 5860
      if (__cil_tmp70 < 0) {
#line 5860
        tmp___2 = 1;
      } else {
#line 5860
        tmp___2 = 0;
      }
      }
    } else {
#line 5860
      tmp___2 = 0;
    }
#line 5860
    is_lvds = (bool )tmp___2;
#line 5862
    if ((int )is_lvds) {
      {
#line 5863
      __cil_tmp71 = dpll & 4128768U;
#line 5863
      __cil_tmp72 = __cil_tmp71 >> 16;
#line 5863
      __cil_tmp73 = (int )__cil_tmp72;
#line 5863
      clock.p1 = ffs(__cil_tmp73);
#line 5865
      clock.p2 = 14;
      }
      {
#line 5867
      __cil_tmp74 = dpll & 24576U;
#line 5867
      if (__cil_tmp74 == 24576U) {
        {
#line 5870
        intel_clock(dev, 66000, & clock);
        }
      } else {
        {
#line 5872
        intel_clock(dev, 48000, & clock);
        }
      }
      }
    } else {
      {
#line 5874
      __cil_tmp75 = dpll & 2097152U;
#line 5874
      if (__cil_tmp75 != 0U) {
#line 5875
        clock.p1 = 2;
      } else {
#line 5877
        __cil_tmp76 = dpll & 2031616U;
#line 5877
        __cil_tmp77 = __cil_tmp76 >> 16;
#line 5877
        __cil_tmp78 = __cil_tmp77 + 2U;
#line 5877
        clock.p1 = (int )__cil_tmp78;
      }
      }
      {
#line 5880
      __cil_tmp79 = dpll & 8388608U;
#line 5880
      if (__cil_tmp79 != 0U) {
#line 5881
        clock.p2 = 4;
      } else {
#line 5883
        clock.p2 = 2;
      }
      }
      {
#line 5885
      intel_clock(dev, 48000, & clock);
      }
    }
  }
  }
#line 5894
  return (clock.dot);
}
}
#line 5898 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev , struct drm_crtc *crtc ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  struct drm_display_mode *mode ;
  int htot ;
  u32 tmp ;
  int hsync ;
  u32 tmp___0 ;
  int vtot ;
  u32 tmp___1 ;
  int vsync ;
  u32 tmp___2 ;
  void *tmp___3 ;
  void *__cil_tmp17 ;
  enum pipe __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  u32 __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  u32 __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  u32 __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  u32 __cil_tmp30 ;
  struct drm_display_mode *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  int __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  int __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  unsigned int __cil_tmp49 ;

  {
  {
#line 5901
  __cil_tmp17 = dev->dev_private;
#line 5901
  dev_priv = (struct drm_i915_private *)__cil_tmp17;
#line 5902
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5902
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5903
  __cil_tmp18 = intel_crtc->pipe;
#line 5903
  pipe = (int )__cil_tmp18;
#line 5905
  __cil_tmp19 = pipe + 96;
#line 5905
  __cil_tmp20 = __cil_tmp19 * 4096;
#line 5905
  __cil_tmp21 = (u32 )__cil_tmp20;
#line 5905
  tmp = i915_read32___6(dev_priv, __cil_tmp21);
#line 5905
  htot = (int )tmp;
#line 5906
  __cil_tmp22 = pipe * 4096;
#line 5906
  __cil_tmp23 = __cil_tmp22 + 393224;
#line 5906
  __cil_tmp24 = (u32 )__cil_tmp23;
#line 5906
  tmp___0 = i915_read32___6(dev_priv, __cil_tmp24);
#line 5906
  hsync = (int )tmp___0;
#line 5907
  __cil_tmp25 = pipe * 4096;
#line 5907
  __cil_tmp26 = __cil_tmp25 + 393228;
#line 5907
  __cil_tmp27 = (u32 )__cil_tmp26;
#line 5907
  tmp___1 = i915_read32___6(dev_priv, __cil_tmp27);
#line 5907
  vtot = (int )tmp___1;
#line 5908
  __cil_tmp28 = pipe * 4096;
#line 5908
  __cil_tmp29 = __cil_tmp28 + 393236;
#line 5908
  __cil_tmp30 = (u32 )__cil_tmp29;
#line 5908
  tmp___2 = i915_read32___6(dev_priv, __cil_tmp30);
#line 5908
  vsync = (int )tmp___2;
#line 5910
  tmp___3 = kzalloc(224UL, 208U);
#line 5910
  mode = (struct drm_display_mode *)tmp___3;
  }
  {
#line 5911
  __cil_tmp31 = (struct drm_display_mode *)0;
#line 5911
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 5911
  __cil_tmp33 = (unsigned long )mode;
#line 5911
  if (__cil_tmp33 == __cil_tmp32) {
#line 5912
    return ((struct drm_display_mode *)0);
  } else {

  }
  }
  {
#line 5914
  mode->clock = intel_crtc_clock_get(dev, crtc);
#line 5915
  __cil_tmp34 = htot & 65535;
#line 5915
  mode->hdisplay = __cil_tmp34 + 1;
#line 5916
  __cil_tmp35 = (unsigned int )htot;
#line 5916
  __cil_tmp36 = __cil_tmp35 >> 16;
#line 5916
  __cil_tmp37 = __cil_tmp36 + 1U;
#line 5916
  mode->htotal = (int )__cil_tmp37;
#line 5917
  __cil_tmp38 = hsync & 65535;
#line 5917
  mode->hsync_start = __cil_tmp38 + 1;
#line 5918
  __cil_tmp39 = (unsigned int )hsync;
#line 5918
  __cil_tmp40 = __cil_tmp39 >> 16;
#line 5918
  __cil_tmp41 = __cil_tmp40 + 1U;
#line 5918
  mode->hsync_end = (int )__cil_tmp41;
#line 5919
  __cil_tmp42 = vtot & 65535;
#line 5919
  mode->vdisplay = __cil_tmp42 + 1;
#line 5920
  __cil_tmp43 = (unsigned int )vtot;
#line 5920
  __cil_tmp44 = __cil_tmp43 >> 16;
#line 5920
  __cil_tmp45 = __cil_tmp44 + 1U;
#line 5920
  mode->vtotal = (int )__cil_tmp45;
#line 5921
  __cil_tmp46 = vsync & 65535;
#line 5921
  mode->vsync_start = __cil_tmp46 + 1;
#line 5922
  __cil_tmp47 = (unsigned int )vsync;
#line 5922
  __cil_tmp48 = __cil_tmp47 >> 16;
#line 5922
  __cil_tmp49 = __cil_tmp48 + 1U;
#line 5922
  mode->vsync_end = (int )__cil_tmp49;
#line 5924
  drm_mode_set_name(mode);
#line 5925
  drm_mode_set_crtcinfo(mode, 0);
  }
#line 5927
  return (mode);
}
}
#line 5933 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_gpu_idle_timer(unsigned long arg ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  unsigned long tmp ;
  int tmp___0 ;
  void *__cil_tmp6 ;
  struct list_head *__cil_tmp7 ;
  struct list_head  const  *__cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  struct timer_list *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct workqueue_struct *__cil_tmp14 ;
  struct work_struct *__cil_tmp15 ;

  {
  {
#line 5935
  dev = (struct drm_device *)arg;
#line 5936
  __cil_tmp6 = dev->dev_private;
#line 5936
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
#line 5938
  __cil_tmp7 = & dev_priv->mm.active_list;
#line 5938
  __cil_tmp8 = (struct list_head  const  *)__cil_tmp7;
#line 5938
  tmp___0 = list_empty(__cil_tmp8);
  }
#line 5938
  if (tmp___0 == 0) {
    {
#line 5940
    __cil_tmp9 = (unsigned int const   )500U;
#line 5940
    __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 5940
    tmp = msecs_to_jiffies(__cil_tmp10);
#line 5940
    __cil_tmp11 = & dev_priv->idle_timer;
#line 5940
    __cil_tmp12 = (unsigned long )jiffies;
#line 5940
    __cil_tmp13 = tmp + __cil_tmp12;
#line 5940
    mod_timer(__cil_tmp11, __cil_tmp13);
    }
#line 5942
    return;
  } else {

  }
  {
#line 5945
  dev_priv->busy = (bool )0;
#line 5946
  __cil_tmp14 = dev_priv->wq;
#line 5946
  __cil_tmp15 = & dev_priv->idle_work;
#line 5946
  queue_work(__cil_tmp14, __cil_tmp15);
  }
#line 5947
  return;
}
}
#line 5951 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_crtc_idle_timer(unsigned long arg ) 
{ struct intel_crtc *intel_crtc ;
  struct drm_crtc *crtc ;
  drm_i915_private_t *dev_priv ;
  struct intel_framebuffer *intel_fb ;
  struct drm_framebuffer  const  *__mptr ;
  unsigned long tmp ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_framebuffer *__cil_tmp10 ;
  struct intel_framebuffer *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_i915_gem_object *__cil_tmp14 ;
  unsigned char *__cil_tmp15 ;
  unsigned char *__cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  struct timer_list *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct workqueue_struct *__cil_tmp24 ;
  struct work_struct *__cil_tmp25 ;

  {
#line 5953
  intel_crtc = (struct intel_crtc *)arg;
#line 5954
  crtc = & intel_crtc->base;
#line 5955
  __cil_tmp8 = crtc->dev;
#line 5955
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 5955
  dev_priv = (drm_i915_private_t *)__cil_tmp9;
#line 5958
  __cil_tmp10 = crtc->fb;
#line 5958
  __mptr = (struct drm_framebuffer  const  *)__cil_tmp10;
#line 5958
  intel_fb = (struct intel_framebuffer *)__mptr;
  {
#line 5959
  __cil_tmp11 = (struct intel_framebuffer *)0;
#line 5959
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 5959
  __cil_tmp13 = (unsigned long )intel_fb;
#line 5959
  if (__cil_tmp13 != __cil_tmp12) {
    {
#line 5959
    __cil_tmp14 = intel_fb->obj;
#line 5959
    __cil_tmp15 = (unsigned char *)__cil_tmp14;
#line 5959
    __cil_tmp16 = __cil_tmp15 + 224UL;
#line 5959
    __cil_tmp17 = *__cil_tmp16;
#line 5959
    __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 5959
    if (__cil_tmp18 != 0U) {
      {
#line 5961
      __cil_tmp19 = (unsigned int const   )1000U;
#line 5961
      __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 5961
      tmp = msecs_to_jiffies(__cil_tmp20);
#line 5961
      __cil_tmp21 = & intel_crtc->idle_timer;
#line 5961
      __cil_tmp22 = (unsigned long )jiffies;
#line 5961
      __cil_tmp23 = tmp + __cil_tmp22;
#line 5961
      mod_timer(__cil_tmp21, __cil_tmp23);
      }
#line 5963
      return;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 5966
  intel_crtc->busy = (bool )0;
#line 5967
  __cil_tmp24 = dev_priv->wq;
#line 5967
  __cil_tmp25 = & dev_priv->idle_work;
#line 5967
  queue_work(__cil_tmp24, __cil_tmp25);
  }
#line 5968
  return;
}
}
#line 5970 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_increase_pllclock(struct drm_crtc *crtc ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  int dpll_reg ;
  int dpll ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  unsigned long tmp___3 ;
  void *__cil_tmp14 ;
  enum pipe __cil_tmp15 ;
  int __cil_tmp16 ;
  void *__cil_tmp17 ;
  struct drm_i915_private *__cil_tmp18 ;
  struct intel_device_info  const  *__cil_tmp19 ;
  u8 __cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  void *__cil_tmp29 ;
  struct drm_i915_private *__cil_tmp30 ;
  struct intel_device_info  const  *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char *__cil_tmp33 ;
  unsigned char __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  bool __cil_tmp36 ;
  u32 __cil_tmp37 ;
  void *__cil_tmp38 ;
  struct drm_i915_private *__cil_tmp39 ;
  struct intel_device_info  const  *__cil_tmp40 ;
  unsigned char *__cil_tmp41 ;
  unsigned char *__cil_tmp42 ;
  unsigned char __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  int __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  u32 __cil_tmp47 ;
  u32 __cil_tmp48 ;
  u32 __cil_tmp49 ;
  int __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  unsigned int __cil_tmp52 ;
  unsigned int __cil_tmp53 ;
  struct timer_list *__cil_tmp54 ;
  unsigned long __cil_tmp55 ;
  unsigned long __cil_tmp56 ;

  {
#line 5972
  dev = crtc->dev;
#line 5973
  __cil_tmp14 = dev->dev_private;
#line 5973
  dev_priv = (drm_i915_private_t *)__cil_tmp14;
#line 5974
  __mptr = (struct drm_crtc  const  *)crtc;
#line 5974
  intel_crtc = (struct intel_crtc *)__mptr;
#line 5975
  __cil_tmp15 = intel_crtc->pipe;
#line 5975
  pipe = (int )__cil_tmp15;
#line 5976
  __cil_tmp16 = pipe + 6149;
#line 5976
  dpll_reg = __cil_tmp16 * 4;
  {
#line 5979
  __cil_tmp17 = dev->dev_private;
#line 5979
  __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
#line 5979
  __cil_tmp19 = __cil_tmp18->info;
#line 5979
  __cil_tmp20 = __cil_tmp19->gen;
#line 5979
  __cil_tmp21 = (unsigned char )__cil_tmp20;
#line 5979
  __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 5979
  if (__cil_tmp22 == 5U) {
#line 5980
    return;
  } else {
    {
#line 5979
    __cil_tmp23 = dev->dev_private;
#line 5979
    __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 5979
    __cil_tmp25 = __cil_tmp24->info;
#line 5979
    __cil_tmp26 = __cil_tmp25->gen;
#line 5979
    __cil_tmp27 = (unsigned char )__cil_tmp26;
#line 5979
    __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 5979
    if (__cil_tmp28 == 6U) {
#line 5980
      return;
    } else {
      {
#line 5979
      __cil_tmp29 = dev->dev_private;
#line 5979
      __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
#line 5979
      __cil_tmp31 = __cil_tmp30->info;
#line 5979
      __cil_tmp32 = (unsigned char *)__cil_tmp31;
#line 5979
      __cil_tmp33 = __cil_tmp32 + 2UL;
#line 5979
      __cil_tmp34 = *__cil_tmp33;
#line 5979
      __cil_tmp35 = (unsigned int )__cil_tmp34;
#line 5979
      if (__cil_tmp35 != 0U) {
#line 5980
        return;
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 5982
  __cil_tmp36 = dev_priv->lvds_downclock_avail;
#line 5982
  if (! __cil_tmp36) {
#line 5983
    return;
  } else {

  }
  }
  {
#line 5985
  __cil_tmp37 = (u32 )dpll_reg;
#line 5985
  tmp = i915_read32___6(dev_priv, __cil_tmp37);
#line 5985
  dpll = (int )tmp;
  }
  {
#line 5986
  __cil_tmp38 = dev->dev_private;
#line 5986
  __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
#line 5986
  __cil_tmp40 = __cil_tmp39->info;
#line 5986
  __cil_tmp41 = (unsigned char *)__cil_tmp40;
#line 5986
  __cil_tmp42 = __cil_tmp41 + 2UL;
#line 5986
  __cil_tmp43 = *__cil_tmp42;
#line 5986
  __cil_tmp44 = (unsigned int )__cil_tmp43;
#line 5986
  if (__cil_tmp44 == 0U) {
    {
#line 5986
    __cil_tmp45 = dpll & 256;
#line 5986
    if (__cil_tmp45 != 0) {
      {
#line 5987
      drm_ut_debug_printk(2U, "drm", "intel_increase_pllclock", "upclocking LVDS\n");
#line 5990
      tmp___0 = i915_read32___6(dev_priv, 397828U);
#line 5990
      __cil_tmp46 = tmp___0 | 2882338816U;
#line 5990
      i915_write32___4(dev_priv, 397828U, __cil_tmp46);
#line 5993
      dpll = dpll & -257;
#line 5994
      __cil_tmp47 = (u32 )dpll_reg;
#line 5994
      __cil_tmp48 = (u32 )dpll;
#line 5994
      i915_write32___4(dev_priv, __cil_tmp47, __cil_tmp48);
#line 5995
      intel_wait_for_vblank(dev, pipe);
#line 5997
      __cil_tmp49 = (u32 )dpll_reg;
#line 5997
      tmp___1 = i915_read32___6(dev_priv, __cil_tmp49);
#line 5997
      dpll = (int )tmp___1;
      }
      {
#line 5998
      __cil_tmp50 = dpll & 256;
#line 5998
      if (__cil_tmp50 != 0) {
        {
#line 5999
        drm_ut_debug_printk(2U, "drm", "intel_increase_pllclock", "failed to upclock LVDS!\n");
        }
      } else {

      }
      }
      {
#line 6002
      tmp___2 = i915_read32___6(dev_priv, 397828U);
#line 6002
      __cil_tmp51 = tmp___2 & 3U;
#line 6002
      i915_write32___4(dev_priv, 397828U, __cil_tmp51);
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 6006
  __cil_tmp52 = (unsigned int const   )1000U;
#line 6006
  __cil_tmp53 = (unsigned int )__cil_tmp52;
#line 6006
  tmp___3 = msecs_to_jiffies(__cil_tmp53);
#line 6006
  __cil_tmp54 = & intel_crtc->idle_timer;
#line 6006
  __cil_tmp55 = (unsigned long )jiffies;
#line 6006
  __cil_tmp56 = tmp___3 + __cil_tmp55;
#line 6006
  mod_timer(__cil_tmp54, __cil_tmp56);
  }
#line 6007
  return;
}
}
#line 6010 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_decrease_pllclock(struct drm_crtc *crtc ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int pipe ;
  int dpll_reg ;
  int dpll ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  void *__cil_tmp13 ;
  enum pipe __cil_tmp14 ;
  int __cil_tmp15 ;
  u32 __cil_tmp16 ;
  void *__cil_tmp17 ;
  struct drm_i915_private *__cil_tmp18 ;
  struct intel_device_info  const  *__cil_tmp19 ;
  u8 __cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  void *__cil_tmp29 ;
  struct drm_i915_private *__cil_tmp30 ;
  struct intel_device_info  const  *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char *__cil_tmp33 ;
  unsigned char __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  bool __cil_tmp36 ;
  void *__cil_tmp37 ;
  struct drm_i915_private *__cil_tmp38 ;
  struct intel_device_info  const  *__cil_tmp39 ;
  unsigned char *__cil_tmp40 ;
  unsigned char *__cil_tmp41 ;
  unsigned char __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  bool __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  u32 __cil_tmp46 ;
  u32 __cil_tmp47 ;
  u32 __cil_tmp48 ;
  int __cil_tmp49 ;
  unsigned int __cil_tmp50 ;

  {
  {
#line 6012
  dev = crtc->dev;
#line 6013
  __cil_tmp13 = dev->dev_private;
#line 6013
  dev_priv = (drm_i915_private_t *)__cil_tmp13;
#line 6014
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6014
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6015
  __cil_tmp14 = intel_crtc->pipe;
#line 6015
  pipe = (int )__cil_tmp14;
#line 6016
  __cil_tmp15 = pipe + 6149;
#line 6016
  dpll_reg = __cil_tmp15 * 4;
#line 6017
  __cil_tmp16 = (u32 )dpll_reg;
#line 6017
  tmp = i915_read32___6(dev_priv, __cil_tmp16);
#line 6017
  dpll = (int )tmp;
  }
  {
#line 6019
  __cil_tmp17 = dev->dev_private;
#line 6019
  __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
#line 6019
  __cil_tmp19 = __cil_tmp18->info;
#line 6019
  __cil_tmp20 = __cil_tmp19->gen;
#line 6019
  __cil_tmp21 = (unsigned char )__cil_tmp20;
#line 6019
  __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 6019
  if (__cil_tmp22 == 5U) {
#line 6020
    return;
  } else {
    {
#line 6019
    __cil_tmp23 = dev->dev_private;
#line 6019
    __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 6019
    __cil_tmp25 = __cil_tmp24->info;
#line 6019
    __cil_tmp26 = __cil_tmp25->gen;
#line 6019
    __cil_tmp27 = (unsigned char )__cil_tmp26;
#line 6019
    __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 6019
    if (__cil_tmp28 == 6U) {
#line 6020
      return;
    } else {
      {
#line 6019
      __cil_tmp29 = dev->dev_private;
#line 6019
      __cil_tmp30 = (struct drm_i915_private *)__cil_tmp29;
#line 6019
      __cil_tmp31 = __cil_tmp30->info;
#line 6019
      __cil_tmp32 = (unsigned char *)__cil_tmp31;
#line 6019
      __cil_tmp33 = __cil_tmp32 + 2UL;
#line 6019
      __cil_tmp34 = *__cil_tmp33;
#line 6019
      __cil_tmp35 = (unsigned int )__cil_tmp34;
#line 6019
      if (__cil_tmp35 != 0U) {
#line 6020
        return;
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 6022
  __cil_tmp36 = dev_priv->lvds_downclock_avail;
#line 6022
  if (! __cil_tmp36) {
#line 6023
    return;
  } else {

  }
  }
  {
#line 6029
  __cil_tmp37 = dev->dev_private;
#line 6029
  __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
#line 6029
  __cil_tmp39 = __cil_tmp38->info;
#line 6029
  __cil_tmp40 = (unsigned char *)__cil_tmp39;
#line 6029
  __cil_tmp41 = __cil_tmp40 + 2UL;
#line 6029
  __cil_tmp42 = *__cil_tmp41;
#line 6029
  __cil_tmp43 = (unsigned int )__cil_tmp42;
#line 6029
  if (__cil_tmp43 == 0U) {
    {
#line 6029
    __cil_tmp44 = intel_crtc->lowfreq_avail;
#line 6029
    if ((int )__cil_tmp44) {
      {
#line 6030
      drm_ut_debug_printk(2U, "drm", "intel_decrease_pllclock", "downclocking LVDS\n");
#line 6033
      tmp___0 = i915_read32___6(dev_priv, 397828U);
#line 6033
      __cil_tmp45 = tmp___0 | 2882338816U;
#line 6033
      i915_write32___4(dev_priv, 397828U, __cil_tmp45);
#line 6036
      dpll = dpll | 256;
#line 6037
      __cil_tmp46 = (u32 )dpll_reg;
#line 6037
      __cil_tmp47 = (u32 )dpll;
#line 6037
      i915_write32___4(dev_priv, __cil_tmp46, __cil_tmp47);
#line 6038
      intel_wait_for_vblank(dev, pipe);
#line 6039
      __cil_tmp48 = (u32 )dpll_reg;
#line 6039
      tmp___1 = i915_read32___6(dev_priv, __cil_tmp48);
#line 6039
      dpll = (int )tmp___1;
      }
      {
#line 6040
      __cil_tmp49 = dpll & 256;
#line 6040
      if (__cil_tmp49 == 0) {
        {
#line 6041
        drm_ut_debug_printk(2U, "drm", "intel_decrease_pllclock", "failed to downclock LVDS!\n");
        }
      } else {

      }
      }
      {
#line 6044
      tmp___2 = i915_read32___6(dev_priv, 397828U);
#line 6044
      __cil_tmp50 = tmp___2 & 3U;
#line 6044
      i915_write32___4(dev_priv, 397828U, __cil_tmp50);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 6046
  return;
}
}
#line 6056 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_idle_update(struct work_struct *work ) 
{ drm_i915_private_t *dev_priv ;
  struct work_struct  const  *__mptr ;
  struct drm_device *dev ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct list_head  const  *__mptr___0 ;
  struct drm_crtc  const  *__mptr___1 ;
  struct list_head  const  *__mptr___2 ;
  drm_i915_private_t *__cil_tmp10 ;
  struct mutex *__cil_tmp11 ;
  struct list_head *__cil_tmp12 ;
  struct drm_crtc *__cil_tmp13 ;
  struct drm_framebuffer *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct drm_framebuffer *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  bool __cil_tmp18 ;
  struct list_head *__cil_tmp19 ;
  struct drm_crtc *__cil_tmp20 ;
  struct list_head *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct list_head *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  struct mutex *__cil_tmp25 ;

  {
#line 6058
  __mptr = (struct work_struct  const  *)work;
#line 6058
  __cil_tmp10 = (drm_i915_private_t *)__mptr;
#line 6058
  dev_priv = __cil_tmp10 + 1152921504606839832UL;
#line 6060
  dev = dev_priv->dev;
#line 6064
  if (i915_powersave == 0U) {
#line 6065
    return;
  } else {

  }
  {
#line 6067
  __cil_tmp11 = & dev->struct_mutex;
#line 6067
  mutex_lock_nested(__cil_tmp11, 0U);
#line 6069
  i915_update_gfx_val(dev_priv);
#line 6071
  __cil_tmp12 = dev->mode_config.crtc_list.next;
#line 6071
  __mptr___0 = (struct list_head  const  *)__cil_tmp12;
#line 6071
  __cil_tmp13 = (struct drm_crtc *)__mptr___0;
#line 6071
  crtc = __cil_tmp13 + 1152921504606846968UL;
  }
#line 6071
  goto ldv_39866;
  ldv_39865: ;
  {
#line 6073
  __cil_tmp14 = (struct drm_framebuffer *)0;
#line 6073
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 6073
  __cil_tmp16 = crtc->fb;
#line 6073
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 6073
  if (__cil_tmp17 == __cil_tmp15) {
#line 6074
    goto ldv_39862;
  } else {

  }
  }
#line 6076
  __mptr___1 = (struct drm_crtc  const  *)crtc;
#line 6076
  intel_crtc = (struct intel_crtc *)__mptr___1;
  {
#line 6077
  __cil_tmp18 = intel_crtc->busy;
#line 6077
  if (! __cil_tmp18) {
    {
#line 6078
    intel_decrease_pllclock(crtc);
    }
  } else {

  }
  }
  ldv_39862: 
#line 6071
  __cil_tmp19 = crtc->head.next;
#line 6071
  __mptr___2 = (struct list_head  const  *)__cil_tmp19;
#line 6071
  __cil_tmp20 = (struct drm_crtc *)__mptr___2;
#line 6071
  crtc = __cil_tmp20 + 1152921504606846968UL;
  ldv_39866: ;
  {
#line 6071
  __cil_tmp21 = & dev->mode_config.crtc_list;
#line 6071
  __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 6071
  __cil_tmp23 = & crtc->head;
#line 6071
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 6071
  if (__cil_tmp24 != __cil_tmp22) {
#line 6072
    goto ldv_39865;
  } else {
#line 6074
    goto ldv_39867;
  }
  }
  ldv_39867: 
  {
#line 6082
  __cil_tmp25 = & dev->struct_mutex;
#line 6082
  mutex_unlock(__cil_tmp25);
  }
#line 6083
  return;
}
}
#line 6095 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_mark_busy(struct drm_device *dev , struct drm_i915_gem_object *obj ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_crtc *crtc ;
  struct intel_framebuffer *intel_fb ;
  struct intel_crtc *intel_crtc ;
  int tmp ;
  unsigned long tmp___0 ;
  struct list_head  const  *__mptr ;
  struct drm_crtc  const  *__mptr___0 ;
  struct drm_framebuffer  const  *__mptr___1 ;
  unsigned long tmp___1 ;
  struct list_head  const  *__mptr___2 ;
  void *__cil_tmp14 ;
  bool __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  struct timer_list *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  struct list_head *__cil_tmp21 ;
  struct drm_crtc *__cil_tmp22 ;
  struct drm_framebuffer *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  struct drm_framebuffer *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  struct drm_framebuffer *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  struct drm_i915_gem_object *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  bool __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  struct timer_list *__cil_tmp34 ;
  unsigned long __cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  struct list_head *__cil_tmp37 ;
  struct drm_crtc *__cil_tmp38 ;
  struct list_head *__cil_tmp39 ;
  unsigned long __cil_tmp40 ;
  struct list_head *__cil_tmp41 ;
  unsigned long __cil_tmp42 ;

  {
  {
#line 6097
  __cil_tmp14 = dev->dev_private;
#line 6097
  dev_priv = (drm_i915_private_t *)__cil_tmp14;
#line 6098
  crtc = (struct drm_crtc *)0;
#line 6102
  tmp = drm_core_check_feature(dev, 8192);
  }
#line 6102
  if (tmp == 0) {
#line 6103
    return;
  } else {

  }
  {
#line 6105
  __cil_tmp15 = dev_priv->busy;
#line 6105
  if (! __cil_tmp15) {
#line 6106
    dev_priv->busy = (bool )1;
  } else {
    {
#line 6108
    __cil_tmp16 = (unsigned int const   )500U;
#line 6108
    __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 6108
    tmp___0 = msecs_to_jiffies(__cil_tmp17);
#line 6108
    __cil_tmp18 = & dev_priv->idle_timer;
#line 6108
    __cil_tmp19 = (unsigned long )jiffies;
#line 6108
    __cil_tmp20 = tmp___0 + __cil_tmp19;
#line 6108
    mod_timer(__cil_tmp18, __cil_tmp20);
    }
  }
  }
#line 6111
  __cil_tmp21 = dev->mode_config.crtc_list.next;
#line 6111
  __mptr = (struct list_head  const  *)__cil_tmp21;
#line 6111
  __cil_tmp22 = (struct drm_crtc *)__mptr;
#line 6111
  crtc = __cil_tmp22 + 1152921504606846968UL;
#line 6111
  goto ldv_39886;
  ldv_39885: ;
  {
#line 6112
  __cil_tmp23 = (struct drm_framebuffer *)0;
#line 6112
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 6112
  __cil_tmp25 = crtc->fb;
#line 6112
  __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 6112
  if (__cil_tmp26 == __cil_tmp24) {
#line 6113
    goto ldv_39880;
  } else {

  }
  }
#line 6115
  __mptr___0 = (struct drm_crtc  const  *)crtc;
#line 6115
  intel_crtc = (struct intel_crtc *)__mptr___0;
#line 6116
  __cil_tmp27 = crtc->fb;
#line 6116
  __mptr___1 = (struct drm_framebuffer  const  *)__cil_tmp27;
#line 6116
  intel_fb = (struct intel_framebuffer *)__mptr___1;
  {
#line 6117
  __cil_tmp28 = (unsigned long )obj;
#line 6117
  __cil_tmp29 = intel_fb->obj;
#line 6117
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 6117
  if (__cil_tmp30 == __cil_tmp28) {
    {
#line 6118
    __cil_tmp31 = intel_crtc->busy;
#line 6118
    if (! __cil_tmp31) {
      {
#line 6120
      intel_increase_pllclock(crtc);
#line 6121
      intel_crtc->busy = (bool )1;
      }
    } else {
      {
#line 6124
      __cil_tmp32 = (unsigned int const   )1000U;
#line 6124
      __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 6124
      tmp___1 = msecs_to_jiffies(__cil_tmp33);
#line 6124
      __cil_tmp34 = & intel_crtc->idle_timer;
#line 6124
      __cil_tmp35 = (unsigned long )jiffies;
#line 6124
      __cil_tmp36 = tmp___1 + __cil_tmp35;
#line 6124
      mod_timer(__cil_tmp34, __cil_tmp36);
      }
    }
    }
  } else {

  }
  }
  ldv_39880: 
#line 6111
  __cil_tmp37 = crtc->head.next;
#line 6111
  __mptr___2 = (struct list_head  const  *)__cil_tmp37;
#line 6111
  __cil_tmp38 = (struct drm_crtc *)__mptr___2;
#line 6111
  crtc = __cil_tmp38 + 1152921504606846968UL;
  ldv_39886: ;
  {
#line 6111
  __cil_tmp39 = & dev->mode_config.crtc_list;
#line 6111
  __cil_tmp40 = (unsigned long )__cil_tmp39;
#line 6111
  __cil_tmp41 = & crtc->head;
#line 6111
  __cil_tmp42 = (unsigned long )__cil_tmp41;
#line 6111
  if (__cil_tmp42 != __cil_tmp40) {
#line 6112
    goto ldv_39885;
  } else {
#line 6114
    goto ldv_39887;
  }
  }
  ldv_39887: ;
#line 6116
  return;
}
}
#line 6131 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_crtc_destroy(struct drm_crtc *crtc ) 
{ struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct drm_device *dev ;
  struct intel_unpin_work *work ;
  unsigned long flags ;
  raw_spinlock_t *tmp ;
  spinlock_t *__cil_tmp8 ;
  spinlock_t *__cil_tmp9 ;
  struct intel_unpin_work *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct work_struct *__cil_tmp13 ;
  void const   *__cil_tmp14 ;
  void const   *__cil_tmp15 ;

  {
  {
#line 6133
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6133
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6134
  dev = crtc->dev;
#line 6138
  __cil_tmp8 = & dev->event_lock;
#line 6138
  tmp = spinlock_check(__cil_tmp8);
#line 6138
  flags = _raw_spin_lock_irqsave(tmp);
#line 6139
  work = intel_crtc->unpin_work;
#line 6140
  intel_crtc->unpin_work = (struct intel_unpin_work *)0;
#line 6141
  __cil_tmp9 = & dev->event_lock;
#line 6141
  spin_unlock_irqrestore(__cil_tmp9, flags);
  }
  {
#line 6143
  __cil_tmp10 = (struct intel_unpin_work *)0;
#line 6143
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 6143
  __cil_tmp12 = (unsigned long )work;
#line 6143
  if (__cil_tmp12 != __cil_tmp11) {
    {
#line 6144
    __cil_tmp13 = & work->work;
#line 6144
    cancel_work_sync(__cil_tmp13);
#line 6145
    __cil_tmp14 = (void const   *)work;
#line 6145
    kfree(__cil_tmp14);
    }
  } else {

  }
  }
  {
#line 6148
  drm_crtc_cleanup(crtc);
#line 6150
  __cil_tmp15 = (void const   *)intel_crtc;
#line 6150
  kfree(__cil_tmp15);
  }
#line 6151
  return;
}
}
#line 6153 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_unpin_work_fn(struct work_struct *__work ) 
{ struct intel_unpin_work *work ;
  struct work_struct  const  *__mptr ;
  struct drm_device *__cil_tmp4 ;
  struct mutex *__cil_tmp5 ;
  struct drm_i915_gem_object *__cil_tmp6 ;
  struct drm_i915_gem_object *__cil_tmp7 ;
  struct drm_gem_object *__cil_tmp8 ;
  struct drm_i915_gem_object *__cil_tmp9 ;
  struct drm_gem_object *__cil_tmp10 ;
  struct drm_device *__cil_tmp11 ;
  struct mutex *__cil_tmp12 ;
  void const   *__cil_tmp13 ;

  {
  {
#line 6156
  __mptr = (struct work_struct  const  *)__work;
#line 6156
  work = (struct intel_unpin_work *)__mptr;
#line 6158
  __cil_tmp4 = work->dev;
#line 6158
  __cil_tmp5 = & __cil_tmp4->struct_mutex;
#line 6158
  mutex_lock_nested(__cil_tmp5, 0U);
#line 6159
  __cil_tmp6 = work->old_fb_obj;
#line 6159
  i915_gem_object_unpin(__cil_tmp6);
#line 6160
  __cil_tmp7 = work->pending_flip_obj;
#line 6160
  __cil_tmp8 = & __cil_tmp7->base;
#line 6160
  drm_gem_object_unreference(__cil_tmp8);
#line 6161
  __cil_tmp9 = work->old_fb_obj;
#line 6161
  __cil_tmp10 = & __cil_tmp9->base;
#line 6161
  drm_gem_object_unreference(__cil_tmp10);
#line 6163
  __cil_tmp11 = work->dev;
#line 6163
  __cil_tmp12 = & __cil_tmp11->struct_mutex;
#line 6163
  mutex_unlock(__cil_tmp12);
#line 6164
  __cil_tmp13 = (void const   *)work;
#line 6164
  kfree(__cil_tmp13);
  }
#line 6165
  return;
}
}
#line 6167 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void do_intel_finish_page_flip(struct drm_device *dev , struct drm_crtc *crtc ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_unpin_work *work ;
  struct drm_i915_gem_object *obj ;
  struct drm_pending_vblank_event *e ;
  struct timeval tnow ;
  struct timeval tvbl ;
  unsigned long flags ;
  raw_spinlock_t *tmp ;
  s64 tmp___0 ;
  s64 tmp___1 ;
  s64 tmp___2 ;
  int tmp___3 ;
  void *__cil_tmp17 ;
  struct intel_crtc *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  spinlock_t *__cil_tmp21 ;
  struct intel_unpin_work *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  spinlock_t *__cil_tmp25 ;
  int __cil_tmp26 ;
  spinlock_t *__cil_tmp27 ;
  struct drm_pending_vblank_event *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  struct drm_pending_vblank_event *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  enum pipe __cil_tmp32 ;
  int __cil_tmp33 ;
  struct timeval  const  *__cil_tmp34 ;
  struct timeval  const  *__cil_tmp35 ;
  s64 __cil_tmp36 ;
  s64 __cil_tmp37 ;
  s64 __cil_tmp38 ;
  s64 __cil_tmp39 ;
  __u32 __cil_tmp40 ;
  struct timeval  const  *__cil_tmp41 ;
  s64 __cil_tmp42 ;
  s64 __cil_tmp43 ;
  s64 __cil_tmp44 ;
  s64 __cil_tmp45 ;
  struct list_head *__cil_tmp46 ;
  struct drm_file *__cil_tmp47 ;
  struct list_head *__cil_tmp48 ;
  struct drm_file *__cil_tmp49 ;
  wait_queue_head_t *__cil_tmp50 ;
  void *__cil_tmp51 ;
  enum pipe __cil_tmp52 ;
  int __cil_tmp53 ;
  spinlock_t *__cil_tmp54 ;
  enum plane __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  atomic_t *__cil_tmp58 ;
  atomic_t const   *__cil_tmp59 ;
  wait_queue_head_t *__cil_tmp60 ;
  void *__cil_tmp61 ;
  struct work_struct *__cil_tmp62 ;
  enum plane __cil_tmp63 ;
  int __cil_tmp64 ;
  struct drm_i915_gem_object *__cil_tmp65 ;

  {
#line 6170
  __cil_tmp17 = dev->dev_private;
#line 6170
  dev_priv = (drm_i915_private_t *)__cil_tmp17;
#line 6171
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6171
  intel_crtc = (struct intel_crtc *)__mptr;
  {
#line 6179
  __cil_tmp18 = (struct intel_crtc *)0;
#line 6179
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 6179
  __cil_tmp20 = (unsigned long )intel_crtc;
#line 6179
  if (__cil_tmp20 == __cil_tmp19) {
#line 6180
    return;
  } else {

  }
  }
  {
#line 6182
  do_gettimeofday(& tnow);
#line 6184
  __cil_tmp21 = & dev->event_lock;
#line 6184
  tmp = spinlock_check(__cil_tmp21);
#line 6184
  flags = _raw_spin_lock_irqsave(tmp);
#line 6185
  work = intel_crtc->unpin_work;
  }
  {
#line 6186
  __cil_tmp22 = (struct intel_unpin_work *)0;
#line 6186
  __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 6186
  __cil_tmp24 = (unsigned long )work;
#line 6186
  if (__cil_tmp24 == __cil_tmp23) {
    {
#line 6187
    __cil_tmp25 = & dev->event_lock;
#line 6187
    spin_unlock_irqrestore(__cil_tmp25, flags);
    }
#line 6188
    return;
  } else {
    {
#line 6186
    __cil_tmp26 = work->pending;
#line 6186
    if (__cil_tmp26 == 0) {
      {
#line 6187
      __cil_tmp27 = & dev->event_lock;
#line 6187
      spin_unlock_irqrestore(__cil_tmp27, flags);
      }
#line 6188
      return;
    } else {

    }
    }
  }
  }
#line 6191
  intel_crtc->unpin_work = (struct intel_unpin_work *)0;
  {
#line 6193
  __cil_tmp28 = (struct drm_pending_vblank_event *)0;
#line 6193
  __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 6193
  __cil_tmp30 = work->event;
#line 6193
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 6193
  if (__cil_tmp31 != __cil_tmp29) {
    {
#line 6194
    e = work->event;
#line 6195
    __cil_tmp32 = intel_crtc->pipe;
#line 6195
    __cil_tmp33 = (int )__cil_tmp32;
#line 6195
    e->event.sequence = drm_vblank_count_and_time(dev, __cil_tmp33, & tvbl);
#line 6209
    __cil_tmp34 = (struct timeval  const  *)(& tnow);
#line 6209
    tmp___1 = timeval_to_ns(__cil_tmp34);
#line 6209
    __cil_tmp35 = (struct timeval  const  *)(& tvbl);
#line 6209
    tmp___2 = timeval_to_ns(__cil_tmp35);
    }
    {
#line 6209
    __cil_tmp36 = crtc->framedur_ns;
#line 6209
    __cil_tmp37 = __cil_tmp36 * 9LL;
#line 6209
    __cil_tmp38 = tmp___1 - tmp___2;
#line 6209
    __cil_tmp39 = __cil_tmp38 * 10LL;
#line 6209
    if (__cil_tmp39 > __cil_tmp37) {
      {
#line 6211
      __cil_tmp40 = e->event.sequence;
#line 6211
      e->event.sequence = __cil_tmp40 + 1U;
#line 6212
      __cil_tmp41 = (struct timeval  const  *)(& tvbl);
#line 6212
      tmp___0 = timeval_to_ns(__cil_tmp41);
#line 6212
      __cil_tmp42 = crtc->framedur_ns;
#line 6212
      __cil_tmp43 = tmp___0 + __cil_tmp42;
#line 6212
      __cil_tmp44 = (s64 const   )__cil_tmp43;
#line 6212
      __cil_tmp45 = (s64 )__cil_tmp44;
#line 6212
      tvbl = ns_to_timeval(__cil_tmp45);
      }
    } else {

    }
    }
    {
#line 6216
    e->event.tv_sec = (__u32 )tvbl.tv_sec;
#line 6217
    e->event.tv_usec = (__u32 )tvbl.tv_usec;
#line 6219
    __cil_tmp46 = & e->base.link;
#line 6219
    __cil_tmp47 = e->base.file_priv;
#line 6219
    __cil_tmp48 = & __cil_tmp47->event_list;
#line 6219
    list_add_tail(__cil_tmp46, __cil_tmp48);
#line 6221
    __cil_tmp49 = e->base.file_priv;
#line 6221
    __cil_tmp50 = & __cil_tmp49->event_wait;
#line 6221
    __cil_tmp51 = (void *)0;
#line 6221
    __wake_up(__cil_tmp50, 1U, 1, __cil_tmp51);
    }
  } else {

  }
  }
  {
#line 6224
  __cil_tmp52 = intel_crtc->pipe;
#line 6224
  __cil_tmp53 = (int )__cil_tmp52;
#line 6224
  drm_vblank_put(dev, __cil_tmp53);
#line 6226
  __cil_tmp54 = & dev->event_lock;
#line 6226
  spin_unlock_irqrestore(__cil_tmp54, flags);
#line 6228
  obj = work->old_fb_obj;
#line 6230
  __cil_tmp55 = intel_crtc->plane;
#line 6230
  __cil_tmp56 = (int )__cil_tmp55;
#line 6230
  __cil_tmp57 = 1 << __cil_tmp56;
#line 6230
  __asm__  volatile   (".section .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.previous\n671:\n\tlock; andl %0,%1": : "r" (~ __cil_tmp57),
                       "m" (obj->pending_flip.counter): "memory");
#line 6232
  __cil_tmp58 = & obj->pending_flip;
#line 6232
  __cil_tmp59 = (atomic_t const   *)__cil_tmp58;
#line 6232
  tmp___3 = atomic_read(__cil_tmp59);
  }
#line 6232
  if (tmp___3 == 0) {
    {
#line 6233
    __cil_tmp60 = & dev_priv->pending_flip_queue;
#line 6233
    __cil_tmp61 = (void *)0;
#line 6233
    __wake_up(__cil_tmp60, 3U, 1, __cil_tmp61);
    }
  } else {

  }
  {
#line 6235
  __cil_tmp62 = & work->work;
#line 6235
  schedule_work(__cil_tmp62);
#line 6237
  __cil_tmp63 = intel_crtc->plane;
#line 6237
  __cil_tmp64 = (int )__cil_tmp63;
#line 6237
  __cil_tmp65 = work->pending_flip_obj;
#line 6237
  trace_i915_flip_complete(__cil_tmp64, __cil_tmp65);
  }
#line 6238
  return;
}
}
#line 6240 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_finish_page_flip(struct drm_device *dev , int pipe ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_crtc *crtc ;
  void *__cil_tmp5 ;

  {
  {
#line 6242
  __cil_tmp5 = dev->dev_private;
#line 6242
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 6243
  crtc = dev_priv->pipe_to_crtc_mapping[pipe];
#line 6245
  do_intel_finish_page_flip(dev, crtc);
  }
#line 6246
  return;
}
}
#line 6248 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_finish_page_flip_plane(struct drm_device *dev , int plane ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_crtc *crtc ;
  void *__cil_tmp5 ;

  {
  {
#line 6250
  __cil_tmp5 = dev->dev_private;
#line 6250
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 6251
  crtc = dev_priv->plane_to_crtc_mapping[plane];
#line 6253
  do_intel_finish_page_flip(dev, crtc);
  }
#line 6254
  return;
}
}
#line 6256 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_prepare_page_flip(struct drm_device *dev , int plane ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  unsigned long flags ;
  raw_spinlock_t *tmp ;
  void *__cil_tmp8 ;
  struct drm_crtc *__cil_tmp9 ;
  spinlock_t *__cil_tmp10 ;
  struct intel_unpin_work *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct intel_unpin_work *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct intel_unpin_work *__cil_tmp15 ;
  struct intel_unpin_work *__cil_tmp16 ;
  int __cil_tmp17 ;
  struct intel_unpin_work *__cil_tmp18 ;
  int __cil_tmp19 ;
  spinlock_t *__cil_tmp20 ;

  {
  {
#line 6258
  __cil_tmp8 = dev->dev_private;
#line 6258
  dev_priv = (drm_i915_private_t *)__cil_tmp8;
#line 6260
  __cil_tmp9 = dev_priv->plane_to_crtc_mapping[plane];
#line 6260
  __mptr = (struct drm_crtc  const  *)__cil_tmp9;
#line 6260
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6263
  __cil_tmp10 = & dev->event_lock;
#line 6263
  tmp = spinlock_check(__cil_tmp10);
#line 6263
  flags = _raw_spin_lock_irqsave(tmp);
  }
  {
#line 6264
  __cil_tmp11 = (struct intel_unpin_work *)0;
#line 6264
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 6264
  __cil_tmp13 = intel_crtc->unpin_work;
#line 6264
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 6264
  if (__cil_tmp14 != __cil_tmp12) {
#line 6265
    __cil_tmp15 = intel_crtc->unpin_work;
#line 6265
    __cil_tmp16 = intel_crtc->unpin_work;
#line 6265
    __cil_tmp17 = __cil_tmp16->pending;
#line 6265
    __cil_tmp15->pending = __cil_tmp17 + 1;
    {
#line 6265
    __cil_tmp18 = intel_crtc->unpin_work;
#line 6265
    __cil_tmp19 = __cil_tmp18->pending;
#line 6265
    if (__cil_tmp19 > 1) {
      {
#line 6266
      drm_err("intel_prepare_page_flip", "Prepared flip multiple times\n");
      }
    } else {
      {
#line 6268
      drm_ut_debug_printk(2U, "drm", "intel_prepare_page_flip", "preparing flip with no unpin work?\n");
      }
    }
    }
  } else {

  }
  }
  {
#line 6270
  __cil_tmp20 = & dev->event_lock;
#line 6270
  spin_unlock_irqrestore(__cil_tmp20, flags);
  }
#line 6271
  return;
}
}
#line 6273 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_gen2_queue_flip(struct drm_device *dev , struct drm_crtc *crtc ,
                                 struct drm_framebuffer *fb , struct drm_i915_gem_object *obj ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  unsigned long offset ;
  u32 flip_mask ;
  int ret ;
  void *__cil_tmp11 ;
  struct intel_ring_buffer (*__cil_tmp12)[3U] ;
  struct intel_ring_buffer *__cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;
  enum plane __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  struct intel_ring_buffer (*__cil_tmp28)[3U] ;
  struct intel_ring_buffer *__cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  struct intel_ring_buffer (*__cil_tmp31)[3U] ;
  struct intel_ring_buffer *__cil_tmp32 ;
  struct intel_ring_buffer (*__cil_tmp33)[3U] ;
  struct intel_ring_buffer *__cil_tmp34 ;
  enum plane __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  struct intel_ring_buffer (*__cil_tmp39)[3U] ;
  struct intel_ring_buffer *__cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  struct intel_ring_buffer (*__cil_tmp42)[3U] ;
  struct intel_ring_buffer *__cil_tmp43 ;
  u32 __cil_tmp44 ;
  uint32_t __cil_tmp45 ;
  uint32_t __cil_tmp46 ;
  struct intel_ring_buffer (*__cil_tmp47)[3U] ;
  struct intel_ring_buffer *__cil_tmp48 ;
  struct intel_ring_buffer (*__cil_tmp49)[3U] ;
  struct intel_ring_buffer *__cil_tmp50 ;

  {
  {
#line 6278
  __cil_tmp11 = dev->dev_private;
#line 6278
  dev_priv = (struct drm_i915_private *)__cil_tmp11;
#line 6279
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6279
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6284
  __cil_tmp12 = & dev_priv->ring;
#line 6284
  __cil_tmp13 = (struct intel_ring_buffer *)__cil_tmp12;
#line 6284
  ret = intel_pin_and_fence_fb_obj(dev, obj, __cil_tmp13);
  }
#line 6285
  if (ret != 0) {
#line 6286
    goto out;
  } else {

  }
  {
#line 6289
  __cil_tmp14 = fb->bits_per_pixel;
#line 6289
  __cil_tmp15 = crtc->x;
#line 6289
  __cil_tmp16 = __cil_tmp15 * __cil_tmp14;
#line 6289
  __cil_tmp17 = __cil_tmp16 / 8;
#line 6289
  __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 6289
  __cil_tmp19 = fb->pitch;
#line 6289
  __cil_tmp20 = crtc->y;
#line 6289
  __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 6289
  __cil_tmp22 = __cil_tmp21 * __cil_tmp19;
#line 6289
  __cil_tmp23 = __cil_tmp22 + __cil_tmp18;
#line 6289
  offset = (unsigned long )__cil_tmp23;
#line 6291
  __cil_tmp24 = & dev_priv->ring;
#line 6291
  __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 6291
  ret = intel_ring_begin(__cil_tmp25, 6);
  }
#line 6292
  if (ret != 0) {
#line 6293
    goto out;
  } else {

  }
  {
#line 6298
  __cil_tmp26 = intel_crtc->plane;
#line 6298
  __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 6298
  if (__cil_tmp27 != 0U) {
#line 6299
    flip_mask = 64U;
  } else {
#line 6301
    flip_mask = 4U;
  }
  }
  {
#line 6302
  __cil_tmp28 = & dev_priv->ring;
#line 6302
  __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
#line 6302
  __cil_tmp30 = flip_mask | 25165824U;
#line 6302
  intel_ring_emit(__cil_tmp29, __cil_tmp30);
#line 6303
  __cil_tmp31 = & dev_priv->ring;
#line 6303
  __cil_tmp32 = (struct intel_ring_buffer *)__cil_tmp31;
#line 6303
  intel_ring_emit(__cil_tmp32, 0U);
#line 6304
  __cil_tmp33 = & dev_priv->ring;
#line 6304
  __cil_tmp34 = (struct intel_ring_buffer *)__cil_tmp33;
#line 6304
  __cil_tmp35 = intel_crtc->plane;
#line 6304
  __cil_tmp36 = (unsigned int )__cil_tmp35;
#line 6304
  __cil_tmp37 = __cil_tmp36 << 20;
#line 6304
  __cil_tmp38 = __cil_tmp37 | 167772162U;
#line 6304
  intel_ring_emit(__cil_tmp34, __cil_tmp38);
#line 6306
  __cil_tmp39 = & dev_priv->ring;
#line 6306
  __cil_tmp40 = (struct intel_ring_buffer *)__cil_tmp39;
#line 6306
  __cil_tmp41 = fb->pitch;
#line 6306
  intel_ring_emit(__cil_tmp40, __cil_tmp41);
#line 6307
  __cil_tmp42 = & dev_priv->ring;
#line 6307
  __cil_tmp43 = (struct intel_ring_buffer *)__cil_tmp42;
#line 6307
  __cil_tmp44 = (u32 )offset;
#line 6307
  __cil_tmp45 = obj->gtt_offset;
#line 6307
  __cil_tmp46 = __cil_tmp45 + __cil_tmp44;
#line 6307
  intel_ring_emit(__cil_tmp43, __cil_tmp46);
#line 6308
  __cil_tmp47 = & dev_priv->ring;
#line 6308
  __cil_tmp48 = (struct intel_ring_buffer *)__cil_tmp47;
#line 6308
  intel_ring_emit(__cil_tmp48, 0U);
#line 6309
  __cil_tmp49 = & dev_priv->ring;
#line 6309
  __cil_tmp50 = (struct intel_ring_buffer *)__cil_tmp49;
#line 6309
  intel_ring_advance(__cil_tmp50);
  }
  out: ;
#line 6311
  return (ret);
}
}
#line 6314 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_gen3_queue_flip(struct drm_device *dev , struct drm_crtc *crtc ,
                                 struct drm_framebuffer *fb , struct drm_i915_gem_object *obj ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  unsigned long offset ;
  u32 flip_mask ;
  int ret ;
  void *__cil_tmp11 ;
  struct intel_ring_buffer (*__cil_tmp12)[3U] ;
  struct intel_ring_buffer *__cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;
  enum plane __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  struct intel_ring_buffer (*__cil_tmp28)[3U] ;
  struct intel_ring_buffer *__cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  struct intel_ring_buffer (*__cil_tmp31)[3U] ;
  struct intel_ring_buffer *__cil_tmp32 ;
  struct intel_ring_buffer (*__cil_tmp33)[3U] ;
  struct intel_ring_buffer *__cil_tmp34 ;
  enum plane __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  struct intel_ring_buffer (*__cil_tmp39)[3U] ;
  struct intel_ring_buffer *__cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  struct intel_ring_buffer (*__cil_tmp42)[3U] ;
  struct intel_ring_buffer *__cil_tmp43 ;
  u32 __cil_tmp44 ;
  uint32_t __cil_tmp45 ;
  uint32_t __cil_tmp46 ;
  struct intel_ring_buffer (*__cil_tmp47)[3U] ;
  struct intel_ring_buffer *__cil_tmp48 ;
  struct intel_ring_buffer (*__cil_tmp49)[3U] ;
  struct intel_ring_buffer *__cil_tmp50 ;

  {
  {
#line 6319
  __cil_tmp11 = dev->dev_private;
#line 6319
  dev_priv = (struct drm_i915_private *)__cil_tmp11;
#line 6320
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6320
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6325
  __cil_tmp12 = & dev_priv->ring;
#line 6325
  __cil_tmp13 = (struct intel_ring_buffer *)__cil_tmp12;
#line 6325
  ret = intel_pin_and_fence_fb_obj(dev, obj, __cil_tmp13);
  }
#line 6326
  if (ret != 0) {
#line 6327
    goto out;
  } else {

  }
  {
#line 6330
  __cil_tmp14 = fb->bits_per_pixel;
#line 6330
  __cil_tmp15 = crtc->x;
#line 6330
  __cil_tmp16 = __cil_tmp15 * __cil_tmp14;
#line 6330
  __cil_tmp17 = __cil_tmp16 / 8;
#line 6330
  __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 6330
  __cil_tmp19 = fb->pitch;
#line 6330
  __cil_tmp20 = crtc->y;
#line 6330
  __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 6330
  __cil_tmp22 = __cil_tmp21 * __cil_tmp19;
#line 6330
  __cil_tmp23 = __cil_tmp22 + __cil_tmp18;
#line 6330
  offset = (unsigned long )__cil_tmp23;
#line 6332
  __cil_tmp24 = & dev_priv->ring;
#line 6332
  __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 6332
  ret = intel_ring_begin(__cil_tmp25, 6);
  }
#line 6333
  if (ret != 0) {
#line 6334
    goto out;
  } else {

  }
  {
#line 6336
  __cil_tmp26 = intel_crtc->plane;
#line 6336
  __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 6336
  if (__cil_tmp27 != 0U) {
#line 6337
    flip_mask = 64U;
  } else {
#line 6339
    flip_mask = 4U;
  }
  }
  {
#line 6340
  __cil_tmp28 = & dev_priv->ring;
#line 6340
  __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
#line 6340
  __cil_tmp30 = flip_mask | 25165824U;
#line 6340
  intel_ring_emit(__cil_tmp29, __cil_tmp30);
#line 6341
  __cil_tmp31 = & dev_priv->ring;
#line 6341
  __cil_tmp32 = (struct intel_ring_buffer *)__cil_tmp31;
#line 6341
  intel_ring_emit(__cil_tmp32, 0U);
#line 6342
  __cil_tmp33 = & dev_priv->ring;
#line 6342
  __cil_tmp34 = (struct intel_ring_buffer *)__cil_tmp33;
#line 6342
  __cil_tmp35 = intel_crtc->plane;
#line 6342
  __cil_tmp36 = (unsigned int )__cil_tmp35;
#line 6342
  __cil_tmp37 = __cil_tmp36 << 20;
#line 6342
  __cil_tmp38 = __cil_tmp37 | 167772161U;
#line 6342
  intel_ring_emit(__cil_tmp34, __cil_tmp38);
#line 6344
  __cil_tmp39 = & dev_priv->ring;
#line 6344
  __cil_tmp40 = (struct intel_ring_buffer *)__cil_tmp39;
#line 6344
  __cil_tmp41 = fb->pitch;
#line 6344
  intel_ring_emit(__cil_tmp40, __cil_tmp41);
#line 6345
  __cil_tmp42 = & dev_priv->ring;
#line 6345
  __cil_tmp43 = (struct intel_ring_buffer *)__cil_tmp42;
#line 6345
  __cil_tmp44 = (u32 )offset;
#line 6345
  __cil_tmp45 = obj->gtt_offset;
#line 6345
  __cil_tmp46 = __cil_tmp45 + __cil_tmp44;
#line 6345
  intel_ring_emit(__cil_tmp43, __cil_tmp46);
#line 6346
  __cil_tmp47 = & dev_priv->ring;
#line 6346
  __cil_tmp48 = (struct intel_ring_buffer *)__cil_tmp47;
#line 6346
  intel_ring_emit(__cil_tmp48, 0U);
#line 6348
  __cil_tmp49 = & dev_priv->ring;
#line 6348
  __cil_tmp50 = (struct intel_ring_buffer *)__cil_tmp49;
#line 6348
  intel_ring_advance(__cil_tmp50);
  }
  out: ;
#line 6350
  return (ret);
}
}
#line 6353 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_gen4_queue_flip(struct drm_device *dev , struct drm_crtc *crtc ,
                                 struct drm_framebuffer *fb , struct drm_i915_gem_object *obj ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  uint32_t pf ;
  uint32_t pipesrc ;
  int ret ;
  u32 tmp ;
  void *__cil_tmp12 ;
  struct intel_ring_buffer (*__cil_tmp13)[3U] ;
  struct intel_ring_buffer *__cil_tmp14 ;
  struct intel_ring_buffer (*__cil_tmp15)[3U] ;
  struct intel_ring_buffer *__cil_tmp16 ;
  struct intel_ring_buffer (*__cil_tmp17)[3U] ;
  struct intel_ring_buffer *__cil_tmp18 ;
  enum plane __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  struct intel_ring_buffer (*__cil_tmp23)[3U] ;
  struct intel_ring_buffer *__cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  struct intel_ring_buffer (*__cil_tmp26)[3U] ;
  struct intel_ring_buffer *__cil_tmp27 ;
  unsigned char __cil_tmp28 ;
  uint32_t __cil_tmp29 ;
  uint32_t __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  enum pipe __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  struct intel_ring_buffer (*__cil_tmp36)[3U] ;
  struct intel_ring_buffer *__cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  struct intel_ring_buffer (*__cil_tmp39)[3U] ;
  struct intel_ring_buffer *__cil_tmp40 ;

  {
  {
#line 6358
  __cil_tmp12 = dev->dev_private;
#line 6358
  dev_priv = (struct drm_i915_private *)__cil_tmp12;
#line 6359
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6359
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6363
  __cil_tmp13 = & dev_priv->ring;
#line 6363
  __cil_tmp14 = (struct intel_ring_buffer *)__cil_tmp13;
#line 6363
  ret = intel_pin_and_fence_fb_obj(dev, obj, __cil_tmp14);
  }
#line 6364
  if (ret != 0) {
#line 6365
    goto out;
  } else {

  }
  {
#line 6367
  __cil_tmp15 = & dev_priv->ring;
#line 6367
  __cil_tmp16 = (struct intel_ring_buffer *)__cil_tmp15;
#line 6367
  ret = intel_ring_begin(__cil_tmp16, 4);
  }
#line 6368
  if (ret != 0) {
#line 6369
    goto out;
  } else {

  }
  {
#line 6375
  __cil_tmp17 = & dev_priv->ring;
#line 6375
  __cil_tmp18 = (struct intel_ring_buffer *)__cil_tmp17;
#line 6375
  __cil_tmp19 = intel_crtc->plane;
#line 6375
  __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 6375
  __cil_tmp21 = __cil_tmp20 << 20;
#line 6375
  __cil_tmp22 = __cil_tmp21 | 167772162U;
#line 6375
  intel_ring_emit(__cil_tmp18, __cil_tmp22);
#line 6377
  __cil_tmp23 = & dev_priv->ring;
#line 6377
  __cil_tmp24 = (struct intel_ring_buffer *)__cil_tmp23;
#line 6377
  __cil_tmp25 = fb->pitch;
#line 6377
  intel_ring_emit(__cil_tmp24, __cil_tmp25);
#line 6378
  __cil_tmp26 = & dev_priv->ring;
#line 6378
  __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
#line 6378
  __cil_tmp28 = obj->tiling_mode;
#line 6378
  __cil_tmp29 = (uint32_t )__cil_tmp28;
#line 6378
  __cil_tmp30 = obj->gtt_offset;
#line 6378
  __cil_tmp31 = __cil_tmp30 | __cil_tmp29;
#line 6378
  intel_ring_emit(__cil_tmp27, __cil_tmp31);
#line 6384
  pf = 0U;
#line 6385
  __cil_tmp32 = intel_crtc->pipe;
#line 6385
  __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 6385
  __cil_tmp34 = __cil_tmp33 * 4096U;
#line 6385
  __cil_tmp35 = __cil_tmp34 + 393244U;
#line 6385
  tmp = i915_read32___6(dev_priv, __cil_tmp35);
#line 6385
  pipesrc = tmp & 268374015U;
#line 6386
  __cil_tmp36 = & dev_priv->ring;
#line 6386
  __cil_tmp37 = (struct intel_ring_buffer *)__cil_tmp36;
#line 6386
  __cil_tmp38 = pf | pipesrc;
#line 6386
  intel_ring_emit(__cil_tmp37, __cil_tmp38);
#line 6387
  __cil_tmp39 = & dev_priv->ring;
#line 6387
  __cil_tmp40 = (struct intel_ring_buffer *)__cil_tmp39;
#line 6387
  intel_ring_advance(__cil_tmp40);
  }
  out: ;
#line 6389
  return (ret);
}
}
#line 6392 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_gen6_queue_flip(struct drm_device *dev , struct drm_crtc *crtc ,
                                 struct drm_framebuffer *fb , struct drm_i915_gem_object *obj ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  uint32_t pf ;
  uint32_t pipesrc ;
  int ret ;
  u32 tmp ;
  u32 tmp___0 ;
  void *__cil_tmp13 ;
  struct intel_ring_buffer (*__cil_tmp14)[3U] ;
  struct intel_ring_buffer *__cil_tmp15 ;
  struct intel_ring_buffer (*__cil_tmp16)[3U] ;
  struct intel_ring_buffer *__cil_tmp17 ;
  struct intel_ring_buffer (*__cil_tmp18)[3U] ;
  struct intel_ring_buffer *__cil_tmp19 ;
  enum plane __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  struct intel_ring_buffer (*__cil_tmp30)[3U] ;
  struct intel_ring_buffer *__cil_tmp31 ;
  uint32_t __cil_tmp32 ;
  enum pipe __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  enum pipe __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  struct intel_ring_buffer (*__cil_tmp41)[3U] ;
  struct intel_ring_buffer *__cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  struct intel_ring_buffer (*__cil_tmp44)[3U] ;
  struct intel_ring_buffer *__cil_tmp45 ;

  {
  {
#line 6397
  __cil_tmp13 = dev->dev_private;
#line 6397
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 6398
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6398
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6402
  __cil_tmp14 = & dev_priv->ring;
#line 6402
  __cil_tmp15 = (struct intel_ring_buffer *)__cil_tmp14;
#line 6402
  ret = intel_pin_and_fence_fb_obj(dev, obj, __cil_tmp15);
  }
#line 6403
  if (ret != 0) {
#line 6404
    goto out;
  } else {

  }
  {
#line 6406
  __cil_tmp16 = & dev_priv->ring;
#line 6406
  __cil_tmp17 = (struct intel_ring_buffer *)__cil_tmp16;
#line 6406
  ret = intel_ring_begin(__cil_tmp17, 4);
  }
#line 6407
  if (ret != 0) {
#line 6408
    goto out;
  } else {

  }
  {
#line 6410
  __cil_tmp18 = & dev_priv->ring;
#line 6410
  __cil_tmp19 = (struct intel_ring_buffer *)__cil_tmp18;
#line 6410
  __cil_tmp20 = intel_crtc->plane;
#line 6410
  __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 6410
  __cil_tmp22 = __cil_tmp21 << 20;
#line 6410
  __cil_tmp23 = __cil_tmp22 | 167772162U;
#line 6410
  intel_ring_emit(__cil_tmp19, __cil_tmp23);
#line 6412
  __cil_tmp24 = & dev_priv->ring;
#line 6412
  __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 6412
  __cil_tmp26 = obj->tiling_mode;
#line 6412
  __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 6412
  __cil_tmp28 = fb->pitch;
#line 6412
  __cil_tmp29 = __cil_tmp28 | __cil_tmp27;
#line 6412
  intel_ring_emit(__cil_tmp25, __cil_tmp29);
#line 6413
  __cil_tmp30 = & dev_priv->ring;
#line 6413
  __cil_tmp31 = (struct intel_ring_buffer *)__cil_tmp30;
#line 6413
  __cil_tmp32 = obj->gtt_offset;
#line 6413
  intel_ring_emit(__cil_tmp31, __cil_tmp32);
#line 6415
  __cil_tmp33 = intel_crtc->pipe;
#line 6415
  __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 6415
  __cil_tmp35 = __cil_tmp34 * 2048U;
#line 6415
  __cil_tmp36 = __cil_tmp35 + 426112U;
#line 6415
  tmp = i915_read32___6(dev_priv, __cil_tmp36);
#line 6415
  pf = tmp & 2147483648U;
#line 6416
  __cil_tmp37 = intel_crtc->pipe;
#line 6416
  __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 6416
  __cil_tmp39 = __cil_tmp38 * 4096U;
#line 6416
  __cil_tmp40 = __cil_tmp39 + 393244U;
#line 6416
  tmp___0 = i915_read32___6(dev_priv, __cil_tmp40);
#line 6416
  pipesrc = tmp___0 & 268374015U;
#line 6417
  __cil_tmp41 = & dev_priv->ring;
#line 6417
  __cil_tmp42 = (struct intel_ring_buffer *)__cil_tmp41;
#line 6417
  __cil_tmp43 = pf | pipesrc;
#line 6417
  intel_ring_emit(__cil_tmp42, __cil_tmp43);
#line 6418
  __cil_tmp44 = & dev_priv->ring;
#line 6418
  __cil_tmp45 = (struct intel_ring_buffer *)__cil_tmp44;
#line 6418
  intel_ring_advance(__cil_tmp45);
  }
  out: ;
#line 6420
  return (ret);
}
}
#line 6429 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_gen7_queue_flip(struct drm_device *dev , struct drm_crtc *crtc ,
                                 struct drm_framebuffer *fb , struct drm_i915_gem_object *obj ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_ring_buffer *ring ;
  int ret ;
  void *__cil_tmp10 ;
  struct intel_ring_buffer (*__cil_tmp11)[3U] ;
  struct intel_ring_buffer *__cil_tmp12 ;
  enum plane __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  uint32_t __cil_tmp21 ;

  {
  {
#line 6434
  __cil_tmp10 = dev->dev_private;
#line 6434
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 6435
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6435
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6436
  __cil_tmp11 = & dev_priv->ring;
#line 6436
  __cil_tmp12 = (struct intel_ring_buffer *)__cil_tmp11;
#line 6436
  ring = __cil_tmp12 + 2UL;
#line 6439
  ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  }
#line 6440
  if (ret != 0) {
#line 6441
    goto out;
  } else {

  }
  {
#line 6443
  ret = intel_ring_begin(ring, 4);
  }
#line 6444
  if (ret != 0) {
#line 6445
    goto out;
  } else {

  }
  {
#line 6447
  __cil_tmp13 = intel_crtc->plane;
#line 6447
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 6447
  __cil_tmp15 = __cil_tmp14 << 19;
#line 6447
  __cil_tmp16 = __cil_tmp15 | 167772161U;
#line 6447
  intel_ring_emit(ring, __cil_tmp16);
#line 6448
  __cil_tmp17 = obj->tiling_mode;
#line 6448
  __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 6448
  __cil_tmp19 = fb->pitch;
#line 6448
  __cil_tmp20 = __cil_tmp19 | __cil_tmp18;
#line 6448
  intel_ring_emit(ring, __cil_tmp20);
#line 6449
  __cil_tmp21 = obj->gtt_offset;
#line 6449
  intel_ring_emit(ring, __cil_tmp21);
#line 6450
  intel_ring_emit(ring, 0U);
#line 6451
  intel_ring_advance(ring);
  }
  out: ;
#line 6453
  return (ret);
}
}
#line 6456 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_default_queue_flip(struct drm_device *dev , struct drm_crtc *crtc ,
                                    struct drm_framebuffer *fb , struct drm_i915_gem_object *obj ) 
{ 

  {
#line 6461
  return (-19);
}
}
#line 6464 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_crtc_page_flip(struct drm_crtc *crtc , struct drm_framebuffer *fb ,
                                struct drm_pending_vblank_event *event ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_framebuffer *intel_fb ;
  struct drm_i915_gem_object *obj ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_unpin_work *work ;
  unsigned long flags ;
  int ret ;
  void *tmp ;
  struct drm_framebuffer  const  *__mptr___0 ;
  struct lock_class_key __key ;
  atomic_long_t __constr_expr_0 ;
  raw_spinlock_t *tmp___0 ;
  struct drm_framebuffer  const  *__mptr___1 ;
  raw_spinlock_t *tmp___1 ;
  void *__cil_tmp20 ;
  struct intel_unpin_work *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct drm_framebuffer *__cil_tmp24 ;
  struct work_struct *__cil_tmp25 ;
  struct lockdep_map *__cil_tmp26 ;
  struct list_head *__cil_tmp27 ;
  spinlock_t *__cil_tmp28 ;
  struct intel_unpin_work *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  struct intel_unpin_work *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  spinlock_t *__cil_tmp33 ;
  void const   *__cil_tmp34 ;
  spinlock_t *__cil_tmp35 ;
  struct mutex *__cil_tmp36 ;
  struct drm_i915_gem_object *__cil_tmp37 ;
  struct drm_gem_object *__cil_tmp38 ;
  struct drm_gem_object *__cil_tmp39 ;
  enum pipe __cil_tmp40 ;
  int __cil_tmp41 ;
  enum plane __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  struct drm_i915_gem_object *__cil_tmp45 ;
  atomic_t *__cil_tmp46 ;
  int (*__cil_tmp47)(struct drm_device * , struct drm_crtc * , struct drm_framebuffer * ,
                     struct drm_i915_gem_object * ) ;
  struct mutex *__cil_tmp48 ;
  enum plane __cil_tmp49 ;
  int __cil_tmp50 ;
  enum plane __cil_tmp51 ;
  int __cil_tmp52 ;
  int __cil_tmp53 ;
  struct drm_i915_gem_object *__cil_tmp54 ;
  atomic_t *__cil_tmp55 ;
  struct drm_i915_gem_object *__cil_tmp56 ;
  struct drm_gem_object *__cil_tmp57 ;
  struct drm_gem_object *__cil_tmp58 ;
  struct mutex *__cil_tmp59 ;
  spinlock_t *__cil_tmp60 ;
  spinlock_t *__cil_tmp61 ;
  void const   *__cil_tmp62 ;

  {
  {
#line 6468
  dev = crtc->dev;
#line 6469
  __cil_tmp20 = dev->dev_private;
#line 6469
  dev_priv = (struct drm_i915_private *)__cil_tmp20;
#line 6472
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6472
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6477
  tmp = kzalloc(120UL, 208U);
#line 6477
  work = (struct intel_unpin_work *)tmp;
  }
  {
#line 6478
  __cil_tmp21 = (struct intel_unpin_work *)0;
#line 6478
  __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 6478
  __cil_tmp23 = (unsigned long )work;
#line 6478
  if (__cil_tmp23 == __cil_tmp22) {
#line 6479
    return (-12);
  } else {

  }
  }
  {
#line 6481
  work->event = event;
#line 6482
  work->dev = crtc->dev;
#line 6483
  __cil_tmp24 = crtc->fb;
#line 6483
  __mptr___0 = (struct drm_framebuffer  const  *)__cil_tmp24;
#line 6483
  intel_fb = (struct intel_framebuffer *)__mptr___0;
#line 6484
  work->old_fb_obj = intel_fb->obj;
#line 6485
  __cil_tmp25 = & work->work;
#line 6485
  __init_work(__cil_tmp25, 0);
#line 6485
  __constr_expr_0.counter = 2097664L;
#line 6485
  work->work.data = __constr_expr_0;
#line 6485
  __cil_tmp26 = & work->work.lockdep_map;
#line 6485
  lockdep_init_map(__cil_tmp26, "(&work->work)", & __key, 0);
#line 6485
  __cil_tmp27 = & work->work.entry;
#line 6485
  INIT_LIST_HEAD(__cil_tmp27);
#line 6485
  work->work.func = & intel_unpin_work_fn;
#line 6488
  __cil_tmp28 = & dev->event_lock;
#line 6488
  tmp___0 = spinlock_check(__cil_tmp28);
#line 6488
  flags = _raw_spin_lock_irqsave(tmp___0);
  }
  {
#line 6489
  __cil_tmp29 = (struct intel_unpin_work *)0;
#line 6489
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 6489
  __cil_tmp31 = intel_crtc->unpin_work;
#line 6489
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 6489
  if (__cil_tmp32 != __cil_tmp30) {
    {
#line 6490
    __cil_tmp33 = & dev->event_lock;
#line 6490
    spin_unlock_irqrestore(__cil_tmp33, flags);
#line 6491
    __cil_tmp34 = (void const   *)work;
#line 6491
    kfree(__cil_tmp34);
#line 6493
    drm_ut_debug_printk(2U, "drm", "intel_crtc_page_flip", "flip queue: crtc already busy\n");
    }
#line 6494
    return (-16);
  } else {

  }
  }
  {
#line 6496
  intel_crtc->unpin_work = work;
#line 6497
  __cil_tmp35 = & dev->event_lock;
#line 6497
  spin_unlock_irqrestore(__cil_tmp35, flags);
#line 6499
  __mptr___1 = (struct drm_framebuffer  const  *)fb;
#line 6499
  intel_fb = (struct intel_framebuffer *)__mptr___1;
#line 6500
  obj = intel_fb->obj;
#line 6502
  __cil_tmp36 = & dev->struct_mutex;
#line 6502
  mutex_lock_nested(__cil_tmp36, 0U);
#line 6505
  __cil_tmp37 = work->old_fb_obj;
#line 6505
  __cil_tmp38 = & __cil_tmp37->base;
#line 6505
  drm_gem_object_reference(__cil_tmp38);
#line 6506
  __cil_tmp39 = & obj->base;
#line 6506
  drm_gem_object_reference(__cil_tmp39);
#line 6508
  crtc->fb = fb;
#line 6510
  __cil_tmp40 = intel_crtc->pipe;
#line 6510
  __cil_tmp41 = (int )__cil_tmp40;
#line 6510
  ret = drm_vblank_get(dev, __cil_tmp41);
  }
#line 6511
  if (ret != 0) {
#line 6512
    goto cleanup_objs;
  } else {

  }
  {
#line 6514
  work->pending_flip_obj = obj;
#line 6516
  work->enable_stall_check = (bool )1;
#line 6521
  __cil_tmp42 = intel_crtc->plane;
#line 6521
  __cil_tmp43 = (int )__cil_tmp42;
#line 6521
  __cil_tmp44 = 1 << __cil_tmp43;
#line 6521
  __cil_tmp45 = work->old_fb_obj;
#line 6521
  __cil_tmp46 = & __cil_tmp45->pending_flip;
#line 6521
  atomic_add(__cil_tmp44, __cil_tmp46);
#line 6523
  __cil_tmp47 = dev_priv->display.queue_flip;
#line 6523
  ret = (*__cil_tmp47)(dev, crtc, fb, obj);
  }
#line 6524
  if (ret != 0) {
#line 6525
    goto cleanup_pending;
  } else {

  }
  {
#line 6527
  __cil_tmp48 = & dev->struct_mutex;
#line 6527
  mutex_unlock(__cil_tmp48);
#line 6529
  __cil_tmp49 = intel_crtc->plane;
#line 6529
  __cil_tmp50 = (int )__cil_tmp49;
#line 6529
  trace_i915_flip_request(__cil_tmp50, obj);
  }
#line 6531
  return (0);
  cleanup_pending: 
  {
#line 6534
  __cil_tmp51 = intel_crtc->plane;
#line 6534
  __cil_tmp52 = (int )__cil_tmp51;
#line 6534
  __cil_tmp53 = 1 << __cil_tmp52;
#line 6534
  __cil_tmp54 = work->old_fb_obj;
#line 6534
  __cil_tmp55 = & __cil_tmp54->pending_flip;
#line 6534
  atomic_sub(__cil_tmp53, __cil_tmp55);
  }
  cleanup_objs: 
  {
#line 6536
  __cil_tmp56 = work->old_fb_obj;
#line 6536
  __cil_tmp57 = & __cil_tmp56->base;
#line 6536
  drm_gem_object_unreference(__cil_tmp57);
#line 6537
  __cil_tmp58 = & obj->base;
#line 6537
  drm_gem_object_unreference(__cil_tmp58);
#line 6538
  __cil_tmp59 = & dev->struct_mutex;
#line 6538
  mutex_unlock(__cil_tmp59);
#line 6540
  __cil_tmp60 = & dev->event_lock;
#line 6540
  tmp___1 = spinlock_check(__cil_tmp60);
#line 6540
  flags = _raw_spin_lock_irqsave(tmp___1);
#line 6541
  intel_crtc->unpin_work = (struct intel_unpin_work *)0;
#line 6542
  __cil_tmp61 = & dev->event_lock;
#line 6542
  spin_unlock_irqrestore(__cil_tmp61, flags);
#line 6544
  __cil_tmp62 = (void const   *)work;
#line 6544
  kfree(__cil_tmp62);
  }
#line 6546
  return (ret);
}
}
#line 6549 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_sanitize_modesetting(struct drm_device *dev , int pipe , int plane ) 
{ struct drm_i915_private *dev_priv ;
  u32 reg ;
  u32 val ;
  void *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  unsigned char *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  int __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  int __cil_tmp31 ;
  enum plane __cil_tmp32 ;
  enum pipe __cil_tmp33 ;
  enum pipe __cil_tmp34 ;

  {
#line 6552
  __cil_tmp7 = dev->dev_private;
#line 6552
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
  {
#line 6555
  __cil_tmp8 = dev->dev_private;
#line 6555
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 6555
  __cil_tmp10 = __cil_tmp9->info;
#line 6555
  __cil_tmp11 = __cil_tmp10->gen;
#line 6555
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 6555
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 6555
  if (__cil_tmp13 == 5U) {
#line 6556
    return;
  } else {
    {
#line 6555
    __cil_tmp14 = dev->dev_private;
#line 6555
    __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 6555
    __cil_tmp16 = __cil_tmp15->info;
#line 6555
    __cil_tmp17 = __cil_tmp16->gen;
#line 6555
    __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 6555
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 6555
    if (__cil_tmp19 == 6U) {
#line 6556
      return;
    } else {
      {
#line 6555
      __cil_tmp20 = dev->dev_private;
#line 6555
      __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 6555
      __cil_tmp22 = __cil_tmp21->info;
#line 6555
      __cil_tmp23 = (unsigned char *)__cil_tmp22;
#line 6555
      __cil_tmp24 = __cil_tmp23 + 2UL;
#line 6555
      __cil_tmp25 = *__cil_tmp24;
#line 6555
      __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 6555
      if (__cil_tmp26 != 0U) {
#line 6556
        return;
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 6569
  __cil_tmp27 = plane * 4096;
#line 6569
  __cil_tmp28 = __cil_tmp27 + 459136;
#line 6569
  reg = (u32 )__cil_tmp28;
#line 6570
  val = i915_read32___6(dev_priv, reg);
  }
  {
#line 6572
  __cil_tmp29 = (int )val;
#line 6572
  if (__cil_tmp29 >= 0) {
#line 6573
    return;
  } else {

  }
  }
  {
#line 6574
  __cil_tmp30 = val & 50331648U;
#line 6574
  __cil_tmp31 = __cil_tmp30 != 0U;
#line 6574
  if (__cil_tmp31 == pipe) {
#line 6575
    return;
  } else {

  }
  }
  {
#line 6578
  pipe = pipe == 0;
#line 6581
  __cil_tmp32 = (enum plane )plane;
#line 6581
  __cil_tmp33 = (enum pipe )pipe;
#line 6581
  intel_disable_plane(dev_priv, __cil_tmp32, __cil_tmp33);
#line 6582
  __cil_tmp34 = (enum pipe )pipe;
#line 6582
  intel_disable_pipe(dev_priv, __cil_tmp34);
  }
#line 6583
  return;
}
}
#line 6585 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_crtc_reset(struct drm_crtc *crtc ) 
{ struct drm_device *dev ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  enum pipe __cil_tmp5 ;
  int __cil_tmp6 ;
  enum plane __cil_tmp7 ;
  int __cil_tmp8 ;

  {
  {
#line 6587
  dev = crtc->dev;
#line 6588
  __mptr = (struct drm_crtc  const  *)crtc;
#line 6588
  intel_crtc = (struct intel_crtc *)__mptr;
#line 6593
  intel_crtc->dpms_mode = -1;
#line 6598
  __cil_tmp5 = intel_crtc->pipe;
#line 6598
  __cil_tmp6 = (int )__cil_tmp5;
#line 6598
  __cil_tmp7 = intel_crtc->plane;
#line 6598
  __cil_tmp8 = (int )__cil_tmp7;
#line 6598
  intel_sanitize_modesetting(dev, __cil_tmp6, __cil_tmp8);
  }
#line 6599
  return;
}
}
#line 6601 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_crtc_helper_funcs intel_helper_funcs  = 
#line 6601
     {& intel_crtc_dpms, (void (*)(struct drm_crtc * ))0, (void (*)(struct drm_crtc * ))0,
    & intel_crtc_mode_fixup, & intel_crtc_mode_set, & intel_pipe_set_base, & intel_pipe_set_base_atomic,
    & intel_crtc_load_lut, & intel_crtc_disable};
#line 6611 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_crtc_funcs  const  intel_crtc_funcs  = 
#line 6611
     {(void (*)(struct drm_crtc * ))0, (void (*)(struct drm_crtc * ))0, & intel_crtc_reset,
    & intel_crtc_cursor_set, & intel_crtc_cursor_move, & intel_crtc_gamma_set, & intel_crtc_destroy,
    & drm_crtc_helper_set_config, & intel_crtc_page_flip};
#line 6621 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_crtc_init(struct drm_device *dev , int pipe ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_crtc *intel_crtc ;
  int i ;
  void *tmp ;
  long tmp___0 ;
  long tmp___1 ;
  struct lock_class_key __key ;
  void *__cil_tmp10 ;
  struct intel_crtc *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_crtc *__cil_tmp14 ;
  struct drm_crtc *__cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  unsigned char *__cil_tmp19 ;
  unsigned char *__cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  int __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  int __cil_tmp31 ;
  long __cil_tmp32 ;
  struct drm_crtc *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  struct drm_crtc *__cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  int __cil_tmp37 ;
  long __cil_tmp38 ;
  struct drm_crtc *__cil_tmp39 ;
  void *__cil_tmp40 ;
  struct drm_i915_private *__cil_tmp41 ;
  struct intel_device_info  const  *__cil_tmp42 ;
  u8 __cil_tmp43 ;
  unsigned char __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  void *__cil_tmp46 ;
  struct drm_i915_private *__cil_tmp47 ;
  struct intel_device_info  const  *__cil_tmp48 ;
  u8 __cil_tmp49 ;
  unsigned char __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  void *__cil_tmp52 ;
  struct drm_i915_private *__cil_tmp53 ;
  struct intel_device_info  const  *__cil_tmp54 ;
  unsigned char *__cil_tmp55 ;
  unsigned char *__cil_tmp56 ;
  unsigned char __cil_tmp57 ;
  unsigned int __cil_tmp58 ;
  struct drm_crtc *__cil_tmp59 ;
  struct drm_crtc_helper_funcs  const  *__cil_tmp60 ;
  struct timer_list *__cil_tmp61 ;
  unsigned long __cil_tmp62 ;

  {
  {
#line 6623
  __cil_tmp10 = dev->dev_private;
#line 6623
  dev_priv = (drm_i915_private_t *)__cil_tmp10;
#line 6627
  tmp = kzalloc(1560UL, 208U);
#line 6627
  intel_crtc = (struct intel_crtc *)tmp;
  }
  {
#line 6628
  __cil_tmp11 = (struct intel_crtc *)0;
#line 6628
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 6628
  __cil_tmp13 = (unsigned long )intel_crtc;
#line 6628
  if (__cil_tmp13 == __cil_tmp12) {
#line 6629
    return;
  } else {

  }
  }
  {
#line 6631
  __cil_tmp14 = & intel_crtc->base;
#line 6631
  drm_crtc_init(dev, __cil_tmp14, & intel_crtc_funcs);
#line 6633
  __cil_tmp15 = & intel_crtc->base;
#line 6633
  drm_mode_crtc_set_gamma_size(__cil_tmp15, 256);
#line 6634
  i = 0;
  }
#line 6634
  goto ldv_40078;
  ldv_40077: 
#line 6635
  intel_crtc->lut_r[i] = (u8 )i;
#line 6636
  intel_crtc->lut_g[i] = (u8 )i;
#line 6637
  intel_crtc->lut_b[i] = (u8 )i;
#line 6634
  i = i + 1;
  ldv_40078: ;
#line 6634
  if (i <= 255) {
#line 6635
    goto ldv_40077;
  } else {
#line 6637
    goto ldv_40079;
  }
  ldv_40079: 
#line 6641
  intel_crtc->pipe = (enum pipe )pipe;
#line 6642
  intel_crtc->plane = (enum plane )pipe;
  {
#line 6643
  __cil_tmp16 = dev->dev_private;
#line 6643
  __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 6643
  __cil_tmp18 = __cil_tmp17->info;
#line 6643
  __cil_tmp19 = (unsigned char *)__cil_tmp18;
#line 6643
  __cil_tmp20 = __cil_tmp19 + 1UL;
#line 6643
  __cil_tmp21 = *__cil_tmp20;
#line 6643
  __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 6643
  if (__cil_tmp22 != 0U) {
    {
#line 6643
    __cil_tmp23 = dev->dev_private;
#line 6643
    __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 6643
    __cil_tmp25 = __cil_tmp24->info;
#line 6643
    __cil_tmp26 = __cil_tmp25->gen;
#line 6643
    __cil_tmp27 = (unsigned char )__cil_tmp26;
#line 6643
    __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 6643
    if (__cil_tmp28 == 3U) {
      {
#line 6644
      drm_ut_debug_printk(4U, "drm", "intel_crtc_init", "swapping pipes & planes for FBC\n");
#line 6645
      __cil_tmp29 = pipe == 0;
#line 6645
      intel_crtc->plane = (enum plane )__cil_tmp29;
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 6648
  __cil_tmp30 = (unsigned int )pipe;
#line 6648
  __cil_tmp31 = __cil_tmp30 > 1U;
#line 6648
  __cil_tmp32 = (long )__cil_tmp31;
#line 6648
  tmp___0 = __builtin_expect(__cil_tmp32, 0L);
  }
#line 6648
  if (tmp___0 != 0L) {
#line 6648
    goto _L;
  } else {
    {
#line 6648
    __cil_tmp33 = (struct drm_crtc *)0;
#line 6648
    __cil_tmp34 = (unsigned long )__cil_tmp33;
#line 6648
    __cil_tmp35 = dev_priv->plane_to_crtc_mapping[(unsigned int )intel_crtc->plane];
#line 6648
    __cil_tmp36 = (unsigned long )__cil_tmp35;
#line 6648
    __cil_tmp37 = __cil_tmp36 != __cil_tmp34;
#line 6648
    __cil_tmp38 = (long )__cil_tmp37;
#line 6648
    tmp___1 = __builtin_expect(__cil_tmp38, 0L);
    }
#line 6648
    if (tmp___1 != 0L) {
      _L: 
#line 6648
      __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"),
                           "i" (6649), "i" (12UL));
      ldv_40083: ;
#line 6648
      goto ldv_40083;
    } else {

    }
  }
  {
#line 6650
  dev_priv->plane_to_crtc_mapping[(unsigned int )intel_crtc->plane] = & intel_crtc->base;
#line 6651
  dev_priv->pipe_to_crtc_mapping[(unsigned int )intel_crtc->pipe] = & intel_crtc->base;
#line 6653
  __cil_tmp39 = & intel_crtc->base;
#line 6653
  intel_crtc_reset(__cil_tmp39);
#line 6654
  intel_crtc->active = (bool )1;
  }
  {
#line 6656
  __cil_tmp40 = dev->dev_private;
#line 6656
  __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
#line 6656
  __cil_tmp42 = __cil_tmp41->info;
#line 6656
  __cil_tmp43 = __cil_tmp42->gen;
#line 6656
  __cil_tmp44 = (unsigned char )__cil_tmp43;
#line 6656
  __cil_tmp45 = (unsigned int )__cil_tmp44;
#line 6656
  if (__cil_tmp45 == 5U) {
#line 6657
    intel_helper_funcs.prepare = & ironlake_crtc_prepare;
#line 6658
    intel_helper_funcs.commit = & ironlake_crtc_commit;
  } else {
    {
#line 6656
    __cil_tmp46 = dev->dev_private;
#line 6656
    __cil_tmp47 = (struct drm_i915_private *)__cil_tmp46;
#line 6656
    __cil_tmp48 = __cil_tmp47->info;
#line 6656
    __cil_tmp49 = __cil_tmp48->gen;
#line 6656
    __cil_tmp50 = (unsigned char )__cil_tmp49;
#line 6656
    __cil_tmp51 = (unsigned int )__cil_tmp50;
#line 6656
    if (__cil_tmp51 == 6U) {
#line 6657
      intel_helper_funcs.prepare = & ironlake_crtc_prepare;
#line 6658
      intel_helper_funcs.commit = & ironlake_crtc_commit;
    } else {
      {
#line 6656
      __cil_tmp52 = dev->dev_private;
#line 6656
      __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
#line 6656
      __cil_tmp54 = __cil_tmp53->info;
#line 6656
      __cil_tmp55 = (unsigned char *)__cil_tmp54;
#line 6656
      __cil_tmp56 = __cil_tmp55 + 2UL;
#line 6656
      __cil_tmp57 = *__cil_tmp56;
#line 6656
      __cil_tmp58 = (unsigned int )__cil_tmp57;
#line 6656
      if (__cil_tmp58 != 0U) {
#line 6657
        intel_helper_funcs.prepare = & ironlake_crtc_prepare;
#line 6658
        intel_helper_funcs.commit = & ironlake_crtc_commit;
      } else {
#line 6660
        intel_helper_funcs.prepare = & i9xx_crtc_prepare;
#line 6661
        intel_helper_funcs.commit = & i9xx_crtc_commit;
      }
      }
    }
    }
  }
  }
  {
#line 6664
  __cil_tmp59 = & intel_crtc->base;
#line 6664
  __cil_tmp60 = (struct drm_crtc_helper_funcs  const  *)(& intel_helper_funcs);
#line 6664
  drm_crtc_helper_add(__cil_tmp59, __cil_tmp60);
#line 6666
  intel_crtc->busy = (bool )0;
#line 6668
  __cil_tmp61 = & intel_crtc->idle_timer;
#line 6668
  __cil_tmp62 = (unsigned long )intel_crtc;
#line 6668
  setup_timer_key(__cil_tmp61, "&intel_crtc->idle_timer", & __key, & intel_crtc_idle_timer,
                  __cil_tmp62);
  }
#line 6670
  return;
}
}
#line 6672 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
int intel_get_pipe_from_crtc_id(struct drm_device *dev , void *data , struct drm_file *file ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id ;
  struct drm_mode_object *drmmode_obj ;
  struct intel_crtc *crtc ;
  struct drm_crtc  const  *__mptr ;
  struct drm_mode_object  const  *__mptr___0 ;
  void *__cil_tmp10 ;
  drm_i915_private_t *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  __u32 __cil_tmp14 ;
  struct drm_mode_object *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_crtc *__cil_tmp18 ;
  struct drm_crtc *__cil_tmp19 ;
  enum pipe __cil_tmp20 ;

  {
#line 6675
  __cil_tmp10 = dev->dev_private;
#line 6675
  dev_priv = (drm_i915_private_t *)__cil_tmp10;
#line 6676
  pipe_from_crtc_id = (struct drm_i915_get_pipe_from_crtc_id *)data;
  {
#line 6680
  __cil_tmp11 = (drm_i915_private_t *)0;
#line 6680
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 6680
  __cil_tmp13 = (unsigned long )dev_priv;
#line 6680
  if (__cil_tmp13 == __cil_tmp12) {
    {
#line 6681
    drm_err("intel_get_pipe_from_crtc_id", "called with no initialization\n");
    }
#line 6682
    return (-22);
  } else {

  }
  }
  {
#line 6685
  __cil_tmp14 = pipe_from_crtc_id->crtc_id;
#line 6685
  drmmode_obj = drm_mode_object_find(dev, __cil_tmp14, 3435973836U);
  }
  {
#line 6688
  __cil_tmp15 = (struct drm_mode_object *)0;
#line 6688
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 6688
  __cil_tmp17 = (unsigned long )drmmode_obj;
#line 6688
  if (__cil_tmp17 == __cil_tmp16) {
    {
#line 6689
    drm_err("intel_get_pipe_from_crtc_id", "no such CRTC id\n");
    }
#line 6690
    return (-22);
  } else {

  }
  }
#line 6693
  __mptr___0 = (struct drm_mode_object  const  *)drmmode_obj;
#line 6693
  __cil_tmp18 = (struct drm_crtc *)__mptr___0;
#line 6693
  __cil_tmp19 = __cil_tmp18 + 1152921504606846952UL;
#line 6693
  __mptr = (struct drm_crtc  const  *)__cil_tmp19;
#line 6693
  crtc = (struct intel_crtc *)__mptr;
#line 6694
  __cil_tmp20 = crtc->pipe;
#line 6694
  pipe_from_crtc_id->pipe = (__u32 )__cil_tmp20;
#line 6696
  return (0);
}
}
#line 6699 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_encoder_clones(struct drm_device *dev , int type_mask ) 
{ struct intel_encoder *encoder ;
  int index_mask ;
  int entry ;
  struct list_head  const  *__mptr ;
  struct list_head  const  *__mptr___0 ;
  struct list_head *__cil_tmp8 ;
  struct intel_encoder *__cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  struct list_head *__cil_tmp13 ;
  struct intel_encoder *__cil_tmp14 ;
  struct list_head *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct list_head *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;

  {
#line 6702
  index_mask = 0;
#line 6703
  entry = 0;
#line 6705
  __cil_tmp8 = dev->mode_config.encoder_list.next;
#line 6705
  __mptr = (struct list_head  const  *)__cil_tmp8;
#line 6705
  __cil_tmp9 = (struct intel_encoder *)__mptr;
#line 6705
  encoder = __cil_tmp9 + 1152921504606846968UL;
#line 6705
  goto ldv_40111;
  ldv_40110: ;
  {
#line 6706
  __cil_tmp10 = encoder->clone_mask;
#line 6706
  __cil_tmp11 = __cil_tmp10 & type_mask;
#line 6706
  if (__cil_tmp11 != 0) {
#line 6707
    __cil_tmp12 = 1 << entry;
#line 6707
    index_mask = __cil_tmp12 | index_mask;
  } else {

  }
  }
#line 6708
  entry = entry + 1;
#line 6705
  __cil_tmp13 = encoder->base.head.next;
#line 6705
  __mptr___0 = (struct list_head  const  *)__cil_tmp13;
#line 6705
  __cil_tmp14 = (struct intel_encoder *)__mptr___0;
#line 6705
  encoder = __cil_tmp14 + 1152921504606846968UL;
  ldv_40111: ;
  {
#line 6705
  __cil_tmp15 = & dev->mode_config.encoder_list;
#line 6705
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 6705
  __cil_tmp17 = & encoder->base.head;
#line 6705
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 6705
  if (__cil_tmp18 != __cil_tmp16) {
#line 6706
    goto ldv_40110;
  } else {
#line 6708
    goto ldv_40112;
  }
  }
  ldv_40112: ;
#line 6711
  return (index_mask);
}
}
#line 6714 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static bool has_edp_a(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  u32 tmp___0 ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  struct drm_i915_private *__cil_tmp7 ;
  struct intel_device_info  const  *__cil_tmp8 ;
  unsigned char *__cil_tmp9 ;
  unsigned char *__cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  unsigned int __cil_tmp20 ;

  {
#line 6716
  __cil_tmp5 = dev->dev_private;
#line 6716
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
  {
#line 6718
  __cil_tmp6 = dev->dev_private;
#line 6718
  __cil_tmp7 = (struct drm_i915_private *)__cil_tmp6;
#line 6718
  __cil_tmp8 = __cil_tmp7->info;
#line 6718
  __cil_tmp9 = (unsigned char *)__cil_tmp8;
#line 6718
  __cil_tmp10 = __cil_tmp9 + 1UL;
#line 6718
  __cil_tmp11 = *__cil_tmp10;
#line 6718
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 6718
  if (__cil_tmp12 == 0U) {
#line 6719
    return ((bool )0);
  } else {

  }
  }
  {
#line 6721
  tmp = i915_read32___6(dev_priv, 409600U);
  }
  {
#line 6721
  __cil_tmp13 = tmp & 4U;
#line 6721
  if (__cil_tmp13 == 0U) {
#line 6722
    return ((bool )0);
  } else {

  }
  }
  {
#line 6724
  __cil_tmp14 = dev->dev_private;
#line 6724
  __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 6724
  __cil_tmp16 = __cil_tmp15->info;
#line 6724
  __cil_tmp17 = __cil_tmp16->gen;
#line 6724
  __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 6724
  __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 6724
  if (__cil_tmp19 == 5U) {
    {
#line 6724
    tmp___0 = i915_read32___6(dev_priv, 270356U);
    }
    {
#line 6724
    __cil_tmp20 = tmp___0 & 16777216U;
#line 6724
    if (__cil_tmp20 != 0U) {
#line 6726
      return ((bool )0);
    } else {

    }
    }
  } else {

  }
  }
#line 6728
  return ((bool )1);
}
}
#line 6731 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_setup_outputs(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_encoder *encoder ;
  bool dpd_is_edp ;
  bool has_lvds ;
  bool tmp ;
  u32 tmp___0 ;
  int found ;
  bool tmp___1 ;
  u32 tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  u32 tmp___5 ;
  u32 tmp___6 ;
  u32 tmp___7 ;
  bool found___0 ;
  u32 tmp___8 ;
  u32 tmp___9 ;
  u32 tmp___10 ;
  u32 tmp___11 ;
  struct list_head  const  *__mptr ;
  int tmp___12 ;
  struct list_head  const  *__mptr___0 ;
  void *__cil_tmp24 ;
  void *__cil_tmp25 ;
  struct drm_i915_private *__cil_tmp26 ;
  struct intel_device_info  const  *__cil_tmp27 ;
  unsigned char *__cil_tmp28 ;
  unsigned char *__cil_tmp29 ;
  unsigned char __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  int __cil_tmp32 ;
  void *__cil_tmp33 ;
  struct drm_i915_private *__cil_tmp34 ;
  struct intel_device_info  const  *__cil_tmp35 ;
  u8 __cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  void *__cil_tmp39 ;
  struct drm_i915_private *__cil_tmp40 ;
  struct intel_device_info  const  *__cil_tmp41 ;
  u8 __cil_tmp42 ;
  unsigned char __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  void *__cil_tmp45 ;
  struct drm_i915_private *__cil_tmp46 ;
  struct intel_device_info  const  *__cil_tmp47 ;
  unsigned char *__cil_tmp48 ;
  unsigned char *__cil_tmp49 ;
  unsigned char __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  void *__cil_tmp52 ;
  struct drm_i915_private *__cil_tmp53 ;
  struct intel_device_info  const  *__cil_tmp54 ;
  u8 __cil_tmp55 ;
  unsigned char __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  void *__cil_tmp58 ;
  struct drm_i915_private *__cil_tmp59 ;
  struct intel_device_info  const  *__cil_tmp60 ;
  u8 __cil_tmp61 ;
  unsigned char __cil_tmp62 ;
  unsigned int __cil_tmp63 ;
  void *__cil_tmp64 ;
  struct drm_i915_private *__cil_tmp65 ;
  struct intel_device_info  const  *__cil_tmp66 ;
  unsigned char *__cil_tmp67 ;
  unsigned char *__cil_tmp68 ;
  unsigned char __cil_tmp69 ;
  unsigned int __cil_tmp70 ;
  unsigned int __cil_tmp71 ;
  void *__cil_tmp72 ;
  struct drm_i915_private *__cil_tmp73 ;
  struct intel_device_info  const  *__cil_tmp74 ;
  u8 __cil_tmp75 ;
  unsigned char __cil_tmp76 ;
  unsigned int __cil_tmp77 ;
  void *__cil_tmp78 ;
  struct drm_i915_private *__cil_tmp79 ;
  struct intel_device_info  const  *__cil_tmp80 ;
  u8 __cil_tmp81 ;
  unsigned char __cil_tmp82 ;
  unsigned int __cil_tmp83 ;
  void *__cil_tmp84 ;
  struct drm_i915_private *__cil_tmp85 ;
  struct intel_device_info  const  *__cil_tmp86 ;
  unsigned char *__cil_tmp87 ;
  unsigned char *__cil_tmp88 ;
  unsigned char __cil_tmp89 ;
  unsigned int __cil_tmp90 ;
  unsigned int __cil_tmp91 ;
  unsigned int __cil_tmp92 ;
  unsigned int __cil_tmp93 ;
  unsigned int __cil_tmp94 ;
  unsigned int __cil_tmp95 ;
  unsigned int __cil_tmp96 ;
  void *__cil_tmp97 ;
  struct drm_i915_private *__cil_tmp98 ;
  struct intel_device_info  const  *__cil_tmp99 ;
  u8 __cil_tmp100 ;
  unsigned char __cil_tmp101 ;
  unsigned int __cil_tmp102 ;
  void *__cil_tmp103 ;
  struct drm_i915_private *__cil_tmp104 ;
  struct intel_device_info  const  *__cil_tmp105 ;
  unsigned char *__cil_tmp106 ;
  unsigned char *__cil_tmp107 ;
  unsigned char __cil_tmp108 ;
  unsigned int __cil_tmp109 ;
  unsigned int __cil_tmp110 ;
  void *__cil_tmp111 ;
  struct drm_i915_private *__cil_tmp112 ;
  struct intel_device_info  const  *__cil_tmp113 ;
  unsigned char *__cil_tmp114 ;
  unsigned char *__cil_tmp115 ;
  unsigned char __cil_tmp116 ;
  unsigned int __cil_tmp117 ;
  void *__cil_tmp118 ;
  struct drm_i915_private *__cil_tmp119 ;
  struct intel_device_info  const  *__cil_tmp120 ;
  u8 __cil_tmp121 ;
  unsigned char __cil_tmp122 ;
  unsigned int __cil_tmp123 ;
  void *__cil_tmp124 ;
  struct drm_i915_private *__cil_tmp125 ;
  struct intel_device_info  const  *__cil_tmp126 ;
  unsigned char *__cil_tmp127 ;
  unsigned char *__cil_tmp128 ;
  unsigned char __cil_tmp129 ;
  unsigned int __cil_tmp130 ;
  void *__cil_tmp131 ;
  struct drm_i915_private *__cil_tmp132 ;
  struct intel_device_info  const  *__cil_tmp133 ;
  u8 __cil_tmp134 ;
  unsigned char __cil_tmp135 ;
  unsigned int __cil_tmp136 ;
  unsigned int __cil_tmp137 ;
  unsigned int __cil_tmp138 ;
  void *__cil_tmp139 ;
  struct drm_i915_private *__cil_tmp140 ;
  struct intel_device_info  const  *__cil_tmp141 ;
  unsigned char *__cil_tmp142 ;
  unsigned char *__cil_tmp143 ;
  unsigned char __cil_tmp144 ;
  unsigned int __cil_tmp145 ;
  void *__cil_tmp146 ;
  struct drm_i915_private *__cil_tmp147 ;
  struct intel_device_info  const  *__cil_tmp148 ;
  u8 __cil_tmp149 ;
  unsigned char __cil_tmp150 ;
  unsigned int __cil_tmp151 ;
  void *__cil_tmp152 ;
  struct drm_i915_private *__cil_tmp153 ;
  struct intel_device_info  const  *__cil_tmp154 ;
  unsigned char *__cil_tmp155 ;
  unsigned char *__cil_tmp156 ;
  unsigned char __cil_tmp157 ;
  unsigned int __cil_tmp158 ;
  void *__cil_tmp159 ;
  struct drm_i915_private *__cil_tmp160 ;
  struct intel_device_info  const  *__cil_tmp161 ;
  u8 __cil_tmp162 ;
  unsigned char __cil_tmp163 ;
  unsigned int __cil_tmp164 ;
  void *__cil_tmp165 ;
  struct drm_i915_private *__cil_tmp166 ;
  struct intel_device_info  const  *__cil_tmp167 ;
  unsigned char *__cil_tmp168 ;
  unsigned char *__cil_tmp169 ;
  unsigned char __cil_tmp170 ;
  unsigned int __cil_tmp171 ;
  void *__cil_tmp172 ;
  struct drm_i915_private *__cil_tmp173 ;
  struct intel_device_info  const  *__cil_tmp174 ;
  u8 __cil_tmp175 ;
  unsigned char __cil_tmp176 ;
  unsigned int __cil_tmp177 ;
  unsigned int __cil_tmp178 ;
  void *__cil_tmp179 ;
  struct drm_i915_private *__cil_tmp180 ;
  struct intel_device_info  const  *__cil_tmp181 ;
  u8 __cil_tmp182 ;
  unsigned char __cil_tmp183 ;
  unsigned int __cil_tmp184 ;
  void *__cil_tmp185 ;
  struct drm_i915_private *__cil_tmp186 ;
  struct intel_device_info  const  *__cil_tmp187 ;
  unsigned char *__cil_tmp188 ;
  unsigned char *__cil_tmp189 ;
  unsigned char __cil_tmp190 ;
  unsigned int __cil_tmp191 ;
  struct list_head *__cil_tmp192 ;
  struct intel_encoder *__cil_tmp193 ;
  int __cil_tmp194 ;
  int __cil_tmp195 ;
  struct list_head *__cil_tmp196 ;
  struct intel_encoder *__cil_tmp197 ;
  struct list_head *__cil_tmp198 ;
  unsigned long __cil_tmp199 ;
  struct list_head *__cil_tmp200 ;
  unsigned long __cil_tmp201 ;

  {
#line 6733
  __cil_tmp24 = dev->dev_private;
#line 6733
  dev_priv = (struct drm_i915_private *)__cil_tmp24;
#line 6735
  dpd_is_edp = (bool )0;
#line 6736
  has_lvds = (bool )0;
  {
#line 6738
  __cil_tmp25 = dev->dev_private;
#line 6738
  __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
#line 6738
  __cil_tmp27 = __cil_tmp26->info;
#line 6738
  __cil_tmp28 = (unsigned char *)__cil_tmp27;
#line 6738
  __cil_tmp29 = __cil_tmp28 + 1UL;
#line 6738
  __cil_tmp30 = *__cil_tmp29;
#line 6738
  __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 6738
  if (__cil_tmp31 != 0U) {
    {
#line 6738
    __cil_tmp32 = dev->pci_device;
#line 6738
    if (__cil_tmp32 != 13687) {
      {
#line 6739
      has_lvds = intel_lvds_init(dev);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 6740
  if (! has_lvds) {
    {
#line 6740
    __cil_tmp33 = dev->dev_private;
#line 6740
    __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
#line 6740
    __cil_tmp35 = __cil_tmp34->info;
#line 6740
    __cil_tmp36 = __cil_tmp35->gen;
#line 6740
    __cil_tmp37 = (unsigned char )__cil_tmp36;
#line 6740
    __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 6740
    if (__cil_tmp38 != 5U) {
      {
#line 6740
      __cil_tmp39 = dev->dev_private;
#line 6740
      __cil_tmp40 = (struct drm_i915_private *)__cil_tmp39;
#line 6740
      __cil_tmp41 = __cil_tmp40->info;
#line 6740
      __cil_tmp42 = __cil_tmp41->gen;
#line 6740
      __cil_tmp43 = (unsigned char )__cil_tmp42;
#line 6740
      __cil_tmp44 = (unsigned int )__cil_tmp43;
#line 6740
      if (__cil_tmp44 != 6U) {
        {
#line 6740
        __cil_tmp45 = dev->dev_private;
#line 6740
        __cil_tmp46 = (struct drm_i915_private *)__cil_tmp45;
#line 6740
        __cil_tmp47 = __cil_tmp46->info;
#line 6740
        __cil_tmp48 = (unsigned char *)__cil_tmp47;
#line 6740
        __cil_tmp49 = __cil_tmp48 + 2UL;
#line 6740
        __cil_tmp50 = *__cil_tmp49;
#line 6740
        __cil_tmp51 = (unsigned int )__cil_tmp50;
#line 6740
        if (__cil_tmp51 == 0U) {
          {
#line 6742
          i915_write32___4(dev_priv, 397872U, 0U);
          }
        } else {

        }
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  {
#line 6745
  __cil_tmp52 = dev->dev_private;
#line 6745
  __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
#line 6745
  __cil_tmp54 = __cil_tmp53->info;
#line 6745
  __cil_tmp55 = __cil_tmp54->gen;
#line 6745
  __cil_tmp56 = (unsigned char )__cil_tmp55;
#line 6745
  __cil_tmp57 = (unsigned int )__cil_tmp56;
#line 6745
  if (__cil_tmp57 == 5U) {
#line 6745
    goto _L;
  } else {
    {
#line 6745
    __cil_tmp58 = dev->dev_private;
#line 6745
    __cil_tmp59 = (struct drm_i915_private *)__cil_tmp58;
#line 6745
    __cil_tmp60 = __cil_tmp59->info;
#line 6745
    __cil_tmp61 = __cil_tmp60->gen;
#line 6745
    __cil_tmp62 = (unsigned char )__cil_tmp61;
#line 6745
    __cil_tmp63 = (unsigned int )__cil_tmp62;
#line 6745
    if (__cil_tmp63 == 6U) {
#line 6745
      goto _L;
    } else {
      {
#line 6745
      __cil_tmp64 = dev->dev_private;
#line 6745
      __cil_tmp65 = (struct drm_i915_private *)__cil_tmp64;
#line 6745
      __cil_tmp66 = __cil_tmp65->info;
#line 6745
      __cil_tmp67 = (unsigned char *)__cil_tmp66;
#line 6745
      __cil_tmp68 = __cil_tmp67 + 2UL;
#line 6745
      __cil_tmp69 = *__cil_tmp68;
#line 6745
      __cil_tmp70 = (unsigned int )__cil_tmp69;
#line 6745
      if (__cil_tmp70 != 0U) {
        _L: 
        {
#line 6746
        dpd_is_edp = intel_dpd_is_edp(dev);
#line 6748
        tmp = has_edp_a(dev);
        }
#line 6748
        if ((int )tmp) {
          {
#line 6749
          intel_dp_init(dev, 409600);
          }
        } else {

        }
#line 6751
        if ((int )dpd_is_edp) {
          {
#line 6751
          tmp___0 = i915_read32___6(dev_priv, 934656U);
          }
          {
#line 6751
          __cil_tmp71 = tmp___0 & 4U;
#line 6751
          if (__cil_tmp71 != 0U) {
            {
#line 6752
            intel_dp_init(dev, 934656);
            }
          } else {

          }
          }
        } else {

        }
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 6755
  intel_crt_init(dev);
  }
  {
#line 6757
  __cil_tmp72 = dev->dev_private;
#line 6757
  __cil_tmp73 = (struct drm_i915_private *)__cil_tmp72;
#line 6757
  __cil_tmp74 = __cil_tmp73->info;
#line 6757
  __cil_tmp75 = __cil_tmp74->gen;
#line 6757
  __cil_tmp76 = (unsigned char )__cil_tmp75;
#line 6757
  __cil_tmp77 = (unsigned int )__cil_tmp76;
#line 6757
  if (__cil_tmp77 == 5U) {
#line 6757
    goto _L___2;
  } else {
    {
#line 6757
    __cil_tmp78 = dev->dev_private;
#line 6757
    __cil_tmp79 = (struct drm_i915_private *)__cil_tmp78;
#line 6757
    __cil_tmp80 = __cil_tmp79->info;
#line 6757
    __cil_tmp81 = __cil_tmp80->gen;
#line 6757
    __cil_tmp82 = (unsigned char )__cil_tmp81;
#line 6757
    __cil_tmp83 = (unsigned int )__cil_tmp82;
#line 6757
    if (__cil_tmp83 == 6U) {
#line 6757
      goto _L___2;
    } else {
      {
#line 6757
      __cil_tmp84 = dev->dev_private;
#line 6757
      __cil_tmp85 = (struct drm_i915_private *)__cil_tmp84;
#line 6757
      __cil_tmp86 = __cil_tmp85->info;
#line 6757
      __cil_tmp87 = (unsigned char *)__cil_tmp86;
#line 6757
      __cil_tmp88 = __cil_tmp87 + 2UL;
#line 6757
      __cil_tmp89 = *__cil_tmp88;
#line 6757
      __cil_tmp90 = (unsigned int )__cil_tmp89;
#line 6757
      if (__cil_tmp90 != 0U) {
        _L___2: 
        {
#line 6760
        tmp___3 = i915_read32___6(dev_priv, 921920U);
        }
        {
#line 6760
        __cil_tmp91 = tmp___3 & 4U;
#line 6760
        if (__cil_tmp91 != 0U) {
          {
#line 6762
          tmp___1 = intel_sdvo_init(dev, 921920);
#line 6762
          found = (int )tmp___1;
          }
#line 6763
          if (found == 0) {
            {
#line 6764
            intel_hdmi_init(dev, 921920);
            }
          } else {

          }
#line 6765
          if (found == 0) {
            {
#line 6765
            tmp___2 = i915_read32___6(dev_priv, 934144U);
            }
            {
#line 6765
            __cil_tmp92 = tmp___2 & 4U;
#line 6765
            if (__cil_tmp92 != 0U) {
              {
#line 6766
              intel_dp_init(dev, 934144);
              }
            } else {

            }
            }
          } else {

          }
        } else {

        }
        }
        {
#line 6769
        tmp___4 = i915_read32___6(dev_priv, 921936U);
        }
        {
#line 6769
        __cil_tmp93 = tmp___4 & 4U;
#line 6769
        if (__cil_tmp93 != 0U) {
          {
#line 6770
          intel_hdmi_init(dev, 921936);
          }
        } else {

        }
        }
        {
#line 6772
        tmp___5 = i915_read32___6(dev_priv, 921952U);
        }
        {
#line 6772
        __cil_tmp94 = tmp___5 & 4U;
#line 6772
        if (__cil_tmp94 != 0U) {
          {
#line 6773
          intel_hdmi_init(dev, 921952);
          }
        } else {

        }
        }
        {
#line 6775
        tmp___6 = i915_read32___6(dev_priv, 934400U);
        }
        {
#line 6775
        __cil_tmp95 = tmp___6 & 4U;
#line 6775
        if (__cil_tmp95 != 0U) {
          {
#line 6776
          intel_dp_init(dev, 934400);
          }
        } else {

        }
        }
#line 6778
        if (! dpd_is_edp) {
          {
#line 6778
          tmp___7 = i915_read32___6(dev_priv, 934656U);
          }
          {
#line 6778
          __cil_tmp96 = tmp___7 & 4U;
#line 6778
          if (__cil_tmp96 != 0U) {
            {
#line 6779
            intel_dp_init(dev, 934656);
            }
          } else {

          }
          }
        } else {

        }
      } else {
        {
#line 6781
        __cil_tmp97 = dev->dev_private;
#line 6781
        __cil_tmp98 = (struct drm_i915_private *)__cil_tmp97;
#line 6781
        __cil_tmp99 = __cil_tmp98->info;
#line 6781
        __cil_tmp100 = __cil_tmp99->gen;
#line 6781
        __cil_tmp101 = (unsigned char )__cil_tmp100;
#line 6781
        __cil_tmp102 = (unsigned int )__cil_tmp101;
#line 6781
        if (__cil_tmp102 != 2U) {
          {
#line 6781
          __cil_tmp103 = dev->dev_private;
#line 6781
          __cil_tmp104 = (struct drm_i915_private *)__cil_tmp103;
#line 6781
          __cil_tmp105 = __cil_tmp104->info;
#line 6781
          __cil_tmp106 = (unsigned char *)__cil_tmp105;
#line 6781
          __cil_tmp107 = __cil_tmp106 + 1UL;
#line 6781
          __cil_tmp108 = *__cil_tmp107;
#line 6781
          __cil_tmp109 = (unsigned int )__cil_tmp108;
#line 6781
          if (__cil_tmp109 == 0U) {
            {
#line 6782
            found___0 = (bool )0;
#line 6784
            tmp___8 = i915_read32___6(dev_priv, 397632U);
            }
            {
#line 6784
            __cil_tmp110 = tmp___8 & 4U;
#line 6784
            if (__cil_tmp110 != 0U) {
              {
#line 6785
              drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing SDVOB\n");
#line 6786
              found___0 = intel_sdvo_init(dev, 397632);
              }
#line 6787
              if (! found___0) {
                {
#line 6787
                __cil_tmp111 = dev->dev_private;
#line 6787
                __cil_tmp112 = (struct drm_i915_private *)__cil_tmp111;
#line 6787
                __cil_tmp113 = __cil_tmp112->info;
#line 6787
                __cil_tmp114 = (unsigned char *)__cil_tmp113;
#line 6787
                __cil_tmp115 = __cil_tmp114 + 1UL;
#line 6787
                __cil_tmp116 = *__cil_tmp115;
#line 6787
                __cil_tmp117 = (unsigned int )__cil_tmp116;
#line 6787
                if (__cil_tmp117 != 0U) {
                  {
#line 6788
                  drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing HDMI on SDVOB\n");
#line 6789
                  intel_hdmi_init(dev, 397632);
                  }
                } else {
                  {
#line 6787
                  __cil_tmp118 = dev->dev_private;
#line 6787
                  __cil_tmp119 = (struct drm_i915_private *)__cil_tmp118;
#line 6787
                  __cil_tmp120 = __cil_tmp119->info;
#line 6787
                  __cil_tmp121 = __cil_tmp120->gen;
#line 6787
                  __cil_tmp122 = (unsigned char )__cil_tmp121;
#line 6787
                  __cil_tmp123 = (unsigned int )__cil_tmp122;
#line 6787
                  if (__cil_tmp123 == 5U) {
                    {
#line 6788
                    drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing HDMI on SDVOB\n");
#line 6789
                    intel_hdmi_init(dev, 397632);
                    }
                  } else {

                  }
                  }
                }
                }
              } else {

              }
#line 6792
              if (! found___0) {
                {
#line 6792
                __cil_tmp124 = dev->dev_private;
#line 6792
                __cil_tmp125 = (struct drm_i915_private *)__cil_tmp124;
#line 6792
                __cil_tmp126 = __cil_tmp125->info;
#line 6792
                __cil_tmp127 = (unsigned char *)__cil_tmp126;
#line 6792
                __cil_tmp128 = __cil_tmp127 + 1UL;
#line 6792
                __cil_tmp129 = *__cil_tmp128;
#line 6792
                __cil_tmp130 = (unsigned int )__cil_tmp129;
#line 6792
                if (__cil_tmp130 != 0U) {
                  {
#line 6793
                  drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing DP_B\n");
#line 6794
                  intel_dp_init(dev, 409856);
                  }
                } else {
                  {
#line 6792
                  __cil_tmp131 = dev->dev_private;
#line 6792
                  __cil_tmp132 = (struct drm_i915_private *)__cil_tmp131;
#line 6792
                  __cil_tmp133 = __cil_tmp132->info;
#line 6792
                  __cil_tmp134 = __cil_tmp133->gen;
#line 6792
                  __cil_tmp135 = (unsigned char )__cil_tmp134;
#line 6792
                  __cil_tmp136 = (unsigned int )__cil_tmp135;
#line 6792
                  if (__cil_tmp136 == 5U) {
                    {
#line 6793
                    drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing DP_B\n");
#line 6794
                    intel_dp_init(dev, 409856);
                    }
                  } else {

                  }
                  }
                }
                }
              } else {

              }
            } else {

            }
            }
            {
#line 6800
            tmp___9 = i915_read32___6(dev_priv, 397632U);
            }
            {
#line 6800
            __cil_tmp137 = tmp___9 & 4U;
#line 6800
            if (__cil_tmp137 != 0U) {
              {
#line 6801
              drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing SDVOC\n");
#line 6802
              found___0 = intel_sdvo_init(dev, 397664);
              }
            } else {

            }
            }
#line 6805
            if (! found___0) {
              {
#line 6805
              tmp___10 = i915_read32___6(dev_priv, 397664U);
              }
              {
#line 6805
              __cil_tmp138 = tmp___10 & 4U;
#line 6805
              if (__cil_tmp138 != 0U) {
                {
#line 6807
                __cil_tmp139 = dev->dev_private;
#line 6807
                __cil_tmp140 = (struct drm_i915_private *)__cil_tmp139;
#line 6807
                __cil_tmp141 = __cil_tmp140->info;
#line 6807
                __cil_tmp142 = (unsigned char *)__cil_tmp141;
#line 6807
                __cil_tmp143 = __cil_tmp142 + 1UL;
#line 6807
                __cil_tmp144 = *__cil_tmp143;
#line 6807
                __cil_tmp145 = (unsigned int )__cil_tmp144;
#line 6807
                if (__cil_tmp145 != 0U) {
                  {
#line 6808
                  drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing HDMI on SDVOC\n");
#line 6809
                  intel_hdmi_init(dev, 397664);
                  }
                } else {
                  {
#line 6807
                  __cil_tmp146 = dev->dev_private;
#line 6807
                  __cil_tmp147 = (struct drm_i915_private *)__cil_tmp146;
#line 6807
                  __cil_tmp148 = __cil_tmp147->info;
#line 6807
                  __cil_tmp149 = __cil_tmp148->gen;
#line 6807
                  __cil_tmp150 = (unsigned char )__cil_tmp149;
#line 6807
                  __cil_tmp151 = (unsigned int )__cil_tmp150;
#line 6807
                  if (__cil_tmp151 == 5U) {
                    {
#line 6808
                    drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing HDMI on SDVOC\n");
#line 6809
                    intel_hdmi_init(dev, 397664);
                    }
                  } else {

                  }
                  }
                }
                }
                {
#line 6811
                __cil_tmp152 = dev->dev_private;
#line 6811
                __cil_tmp153 = (struct drm_i915_private *)__cil_tmp152;
#line 6811
                __cil_tmp154 = __cil_tmp153->info;
#line 6811
                __cil_tmp155 = (unsigned char *)__cil_tmp154;
#line 6811
                __cil_tmp156 = __cil_tmp155 + 1UL;
#line 6811
                __cil_tmp157 = *__cil_tmp156;
#line 6811
                __cil_tmp158 = (unsigned int )__cil_tmp157;
#line 6811
                if (__cil_tmp158 != 0U) {
                  {
#line 6812
                  drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing DP_C\n");
#line 6813
                  intel_dp_init(dev, 410112);
                  }
                } else {
                  {
#line 6811
                  __cil_tmp159 = dev->dev_private;
#line 6811
                  __cil_tmp160 = (struct drm_i915_private *)__cil_tmp159;
#line 6811
                  __cil_tmp161 = __cil_tmp160->info;
#line 6811
                  __cil_tmp162 = __cil_tmp161->gen;
#line 6811
                  __cil_tmp163 = (unsigned char )__cil_tmp162;
#line 6811
                  __cil_tmp164 = (unsigned int )__cil_tmp163;
#line 6811
                  if (__cil_tmp164 == 5U) {
                    {
#line 6812
                    drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing DP_C\n");
#line 6813
                    intel_dp_init(dev, 410112);
                    }
                  } else {

                  }
                  }
                }
                }
              } else {

              }
              }
            } else {

            }
            {
#line 6817
            __cil_tmp165 = dev->dev_private;
#line 6817
            __cil_tmp166 = (struct drm_i915_private *)__cil_tmp165;
#line 6817
            __cil_tmp167 = __cil_tmp166->info;
#line 6817
            __cil_tmp168 = (unsigned char *)__cil_tmp167;
#line 6817
            __cil_tmp169 = __cil_tmp168 + 1UL;
#line 6817
            __cil_tmp170 = *__cil_tmp169;
#line 6817
            __cil_tmp171 = (unsigned int )__cil_tmp170;
#line 6817
            if (__cil_tmp171 != 0U) {
#line 6817
              goto _L___0;
            } else {
              {
#line 6817
              __cil_tmp172 = dev->dev_private;
#line 6817
              __cil_tmp173 = (struct drm_i915_private *)__cil_tmp172;
#line 6817
              __cil_tmp174 = __cil_tmp173->info;
#line 6817
              __cil_tmp175 = __cil_tmp174->gen;
#line 6817
              __cil_tmp176 = (unsigned char )__cil_tmp175;
#line 6817
              __cil_tmp177 = (unsigned int )__cil_tmp176;
#line 6817
              if (__cil_tmp177 == 5U) {
                _L___0: 
                {
#line 6817
                tmp___11 = i915_read32___6(dev_priv, 410368U);
                }
                {
#line 6817
                __cil_tmp178 = tmp___11 & 4U;
#line 6817
                if (__cil_tmp178 != 0U) {
                  {
#line 6819
                  drm_ut_debug_printk(4U, "drm", "intel_setup_outputs", "probing DP_D\n");
#line 6820
                  intel_dp_init(dev, 410368);
                  }
                } else {

                }
                }
              } else {

              }
              }
            }
            }
          } else {
#line 6781
            goto _L___1;
          }
          }
        } else {
          _L___1: 
          {
#line 6822
          __cil_tmp179 = dev->dev_private;
#line 6822
          __cil_tmp180 = (struct drm_i915_private *)__cil_tmp179;
#line 6822
          __cil_tmp181 = __cil_tmp180->info;
#line 6822
          __cil_tmp182 = __cil_tmp181->gen;
#line 6822
          __cil_tmp183 = (unsigned char )__cil_tmp182;
#line 6822
          __cil_tmp184 = (unsigned int )__cil_tmp183;
#line 6822
          if (__cil_tmp184 == 2U) {
            {
#line 6823
            intel_dvo_init(dev);
            }
          } else {

          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
  {
#line 6825
  __cil_tmp185 = dev->dev_private;
#line 6825
  __cil_tmp186 = (struct drm_i915_private *)__cil_tmp185;
#line 6825
  __cil_tmp187 = __cil_tmp186->info;
#line 6825
  __cil_tmp188 = (unsigned char *)__cil_tmp187;
#line 6825
  __cil_tmp189 = __cil_tmp188 + 3UL;
#line 6825
  __cil_tmp190 = *__cil_tmp189;
#line 6825
  __cil_tmp191 = (unsigned int )__cil_tmp190;
#line 6825
  if (__cil_tmp191 != 0U) {
    {
#line 6826
    intel_tv_init(dev);
    }
  } else {

  }
  }
#line 6828
  __cil_tmp192 = dev->mode_config.encoder_list.next;
#line 6828
  __mptr = (struct list_head  const  *)__cil_tmp192;
#line 6828
  __cil_tmp193 = (struct intel_encoder *)__mptr;
#line 6828
  encoder = __cil_tmp193 + 1152921504606846968UL;
#line 6828
  goto ldv_40132;
  ldv_40131: 
  {
#line 6829
  __cil_tmp194 = encoder->crtc_mask;
#line 6829
  encoder->base.possible_crtcs = (uint32_t )__cil_tmp194;
#line 6830
  __cil_tmp195 = encoder->clone_mask;
#line 6830
  tmp___12 = intel_encoder_clones(dev, __cil_tmp195);
#line 6830
  encoder->base.possible_clones = (uint32_t )tmp___12;
#line 6828
  __cil_tmp196 = encoder->base.head.next;
#line 6828
  __mptr___0 = (struct list_head  const  *)__cil_tmp196;
#line 6828
  __cil_tmp197 = (struct intel_encoder *)__mptr___0;
#line 6828
  encoder = __cil_tmp197 + 1152921504606846968UL;
  }
  ldv_40132: ;
  {
#line 6828
  __cil_tmp198 = & dev->mode_config.encoder_list;
#line 6828
  __cil_tmp199 = (unsigned long )__cil_tmp198;
#line 6828
  __cil_tmp200 = & encoder->base.head;
#line 6828
  __cil_tmp201 = (unsigned long )__cil_tmp200;
#line 6828
  if (__cil_tmp201 != __cil_tmp199) {
#line 6829
    goto ldv_40131;
  } else {
#line 6831
    goto ldv_40133;
  }
  }
  ldv_40133: 
  {
#line 6834
  intel_panel_setup_backlight(dev);
#line 6837
  drm_helper_disable_unused_functions(dev);
  }
#line 6838
  return;
}
}
#line 6840 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb ) 
{ struct intel_framebuffer *intel_fb ;
  struct drm_framebuffer  const  *__mptr ;
  struct drm_i915_gem_object *__cil_tmp4 ;
  struct drm_gem_object *__cil_tmp5 ;
  void const   *__cil_tmp6 ;

  {
  {
#line 6842
  __mptr = (struct drm_framebuffer  const  *)fb;
#line 6842
  intel_fb = (struct intel_framebuffer *)__mptr;
#line 6844
  drm_framebuffer_cleanup(fb);
#line 6845
  __cil_tmp4 = intel_fb->obj;
#line 6845
  __cil_tmp5 = & __cil_tmp4->base;
#line 6845
  drm_gem_object_unreference_unlocked(__cil_tmp5);
#line 6847
  __cil_tmp6 = (void const   *)intel_fb;
#line 6847
  kfree(__cil_tmp6);
  }
#line 6848
  return;
}
}
#line 6850 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb , struct drm_file *file ,
                                                unsigned int *handle ) 
{ struct intel_framebuffer *intel_fb ;
  struct drm_framebuffer  const  *__mptr ;
  struct drm_i915_gem_object *obj ;
  int tmp ;
  struct drm_gem_object *__cil_tmp8 ;

  {
  {
#line 6854
  __mptr = (struct drm_framebuffer  const  *)fb;
#line 6854
  intel_fb = (struct intel_framebuffer *)__mptr;
#line 6855
  obj = intel_fb->obj;
#line 6857
  __cil_tmp8 = & obj->base;
#line 6857
  tmp = drm_gem_handle_create(file, __cil_tmp8, handle);
  }
#line 6857
  return (tmp);
}
}
#line 6860 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_framebuffer_funcs  const  intel_fb_funcs  =    {& intel_user_framebuffer_destroy, & intel_user_framebuffer_create_handle, (int (*)(struct drm_framebuffer * ,
                                                                                       struct drm_file * ,
                                                                                       unsigned int  ,
                                                                                       unsigned int  ,
                                                                                       struct drm_clip_rect * ,
                                                                                       unsigned int  ))0};
#line 6865 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
int intel_framebuffer_init(struct drm_device *dev , struct intel_framebuffer *intel_fb ,
                           struct drm_mode_fb_cmd *mode_cmd , struct drm_i915_gem_object *obj ) 
{ int ret ;
  unsigned char *__cil_tmp6 ;
  unsigned char *__cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  __u32 __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  __u32 __cil_tmp12 ;
  int __cil_tmp13 ;
  __u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  __u32 __cil_tmp16 ;
  int __cil_tmp17 ;
  __u32 __cil_tmp18 ;
  int __cil_tmp19 ;
  struct drm_framebuffer *__cil_tmp20 ;
  struct drm_framebuffer *__cil_tmp21 ;

  {
  {
#line 6872
  __cil_tmp6 = (unsigned char *)obj;
#line 6872
  __cil_tmp7 = __cil_tmp6 + 225UL;
#line 6872
  __cil_tmp8 = *__cil_tmp7;
#line 6872
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 6872
  if (__cil_tmp9 == 8U) {
#line 6873
    return (-22);
  } else {

  }
  }
  {
#line 6875
  __cil_tmp10 = mode_cmd->pitch;
#line 6875
  __cil_tmp11 = __cil_tmp10 & 63U;
#line 6875
  if (__cil_tmp11 != 0U) {
#line 6876
    return (-22);
  } else {

  }
  }
  {
#line 6879
  __cil_tmp12 = mode_cmd->bpp;
#line 6879
  __cil_tmp13 = (int )__cil_tmp12;
#line 6879
  if (__cil_tmp13 == 8) {
#line 6879
    goto case_8;
  } else {
    {
#line 6880
    __cil_tmp14 = mode_cmd->bpp;
#line 6880
    __cil_tmp15 = (int )__cil_tmp14;
#line 6880
    if (__cil_tmp15 == 16) {
#line 6880
      goto case_16;
    } else {
      {
#line 6881
      __cil_tmp16 = mode_cmd->bpp;
#line 6881
      __cil_tmp17 = (int )__cil_tmp16;
#line 6881
      if (__cil_tmp17 == 24) {
#line 6881
        goto case_24;
      } else {
        {
#line 6882
        __cil_tmp18 = mode_cmd->bpp;
#line 6882
        __cil_tmp19 = (int )__cil_tmp18;
#line 6882
        if (__cil_tmp19 == 32) {
#line 6882
          goto case_32;
        } else {
#line 6884
          goto switch_default;
#line 6878
          if (0) {
            case_8: ;
            case_16: ;
            case_24: ;
            case_32: ;
#line 6883
            goto ldv_40161;
            switch_default: ;
#line 6885
            return (-22);
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_40161: 
  {
#line 6888
  __cil_tmp20 = & intel_fb->base;
#line 6888
  ret = drm_framebuffer_init(dev, __cil_tmp20, & intel_fb_funcs);
  }
#line 6889
  if (ret != 0) {
    {
#line 6890
    drm_err("intel_framebuffer_init", "framebuffer init failed %d\n", ret);
    }
#line 6891
    return (ret);
  } else {

  }
  {
#line 6894
  __cil_tmp21 = & intel_fb->base;
#line 6894
  drm_helper_mode_fill_fb_struct(__cil_tmp21, mode_cmd);
#line 6895
  intel_fb->obj = obj;
  }
#line 6896
  return (0);
}
}
#line 6900 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_framebuffer *intel_user_framebuffer_create(struct drm_device *dev ,
                                                             struct drm_file *filp ,
                                                             struct drm_mode_fb_cmd *mode_cmd ) 
{ struct drm_i915_gem_object *obj ;
  struct drm_gem_object  const  *__mptr ;
  struct drm_gem_object *tmp ;
  void *tmp___0 ;
  struct drm_framebuffer *tmp___1 ;
  __u32 __cil_tmp9 ;
  struct drm_gem_object *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct drm_gem_object *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;

  {
  {
#line 6906
  __cil_tmp9 = mode_cmd->handle;
#line 6906
  tmp = drm_gem_object_lookup(dev, filp, __cil_tmp9);
#line 6906
  __mptr = (struct drm_gem_object  const  *)tmp;
#line 6906
  obj = (struct drm_i915_gem_object *)__mptr;
  }
  {
#line 6907
  __cil_tmp10 = (struct drm_gem_object *)0;
#line 6907
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 6907
  __cil_tmp12 = & obj->base;
#line 6907
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 6907
  if (__cil_tmp13 == __cil_tmp11) {
    {
#line 6908
    tmp___0 = ERR_PTR(-2L);
    }
#line 6908
    return ((struct drm_framebuffer *)tmp___0);
  } else {

  }
  }
  {
#line 6910
  tmp___1 = intel_framebuffer_create(dev, mode_cmd, obj);
  }
#line 6910
  return (tmp___1);
}
}
#line 6913 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_mode_config_funcs  const  intel_mode_funcs  =    {& intel_user_framebuffer_create, & intel_fb_output_poll_changed};
#line 6919 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static struct drm_i915_gem_object *intel_alloc_context_page(struct drm_device *dev ) 
{ struct drm_i915_gem_object *ctx ;
  int ret ;
  int __ret_warn_on ;
  int tmp ;
  long tmp___0 ;
  struct mutex *__cil_tmp7 ;
  int __cil_tmp8 ;
  long __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  long __cil_tmp13 ;
  struct drm_i915_gem_object *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  bool __cil_tmp17 ;
  bool __cil_tmp18 ;
  struct drm_gem_object *__cil_tmp19 ;
  struct mutex *__cil_tmp20 ;

  {
  {
#line 6924
  __cil_tmp7 = & dev->struct_mutex;
#line 6924
  tmp = mutex_is_locked(__cil_tmp7);
#line 6924
  __ret_warn_on = tmp == 0;
#line 6924
  __cil_tmp8 = __ret_warn_on != 0;
#line 6924
  __cil_tmp9 = (long )__cil_tmp8;
#line 6924
  tmp___0 = __builtin_expect(__cil_tmp9, 0L);
  }
#line 6924
  if (tmp___0 != 0L) {
    {
#line 6924
    __cil_tmp10 = (int const   )6924;
#line 6924
    __cil_tmp11 = (int )__cil_tmp10;
#line 6924
    warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp11);
    }
  } else {

  }
  {
#line 6924
  __cil_tmp12 = __ret_warn_on != 0;
#line 6924
  __cil_tmp13 = (long )__cil_tmp12;
#line 6924
  __builtin_expect(__cil_tmp13, 0L);
#line 6926
  ctx = i915_gem_alloc_object(dev, 4096UL);
  }
  {
#line 6927
  __cil_tmp14 = (struct drm_i915_gem_object *)0;
#line 6927
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 6927
  __cil_tmp16 = (unsigned long )ctx;
#line 6927
  if (__cil_tmp16 == __cil_tmp15) {
    {
#line 6928
    drm_ut_debug_printk(1U, "drm", "intel_alloc_context_page", "failed to alloc power context, RC6 disabled\n");
    }
#line 6929
    return ((struct drm_i915_gem_object *)0);
  } else {

  }
  }
  {
#line 6932
  __cil_tmp17 = (bool )1;
#line 6932
  ret = i915_gem_object_pin(ctx, 4096U, __cil_tmp17);
  }
#line 6933
  if (ret != 0) {
    {
#line 6934
    drm_err("intel_alloc_context_page", "failed to pin power context: %d\n", ret);
    }
#line 6935
    goto err_unref;
  } else {

  }
  {
#line 6938
  __cil_tmp18 = (bool )1;
#line 6938
  ret = i915_gem_object_set_to_gtt_domain(ctx, __cil_tmp18);
  }
#line 6939
  if (ret != 0) {
    {
#line 6940
    drm_err("intel_alloc_context_page", "failed to set-domain on power context: %d\n",
            ret);
    }
#line 6941
    goto err_unpin;
  } else {

  }
#line 6944
  return (ctx);
  err_unpin: 
  {
#line 6947
  i915_gem_object_unpin(ctx);
  }
  err_unref: 
  {
#line 6949
  __cil_tmp19 = & ctx->base;
#line 6949
  drm_gem_object_unreference(__cil_tmp19);
#line 6950
  __cil_tmp20 = & dev->struct_mutex;
#line 6950
  mutex_unlock(__cil_tmp20);
  }
#line 6951
  return ((struct drm_i915_gem_object *)0);
}
}
#line 6954 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
bool ironlake_set_drps(struct drm_device *dev , u8 val ) 
{ struct drm_i915_private *dev_priv ;
  u16 rgvswctl ;
  void *__cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  short __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  u16 __cil_tmp14 ;
  void *__cil_tmp15 ;
  void const volatile   *__cil_tmp16 ;
  void const volatile   *__cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  int __cil_tmp20 ;
  u16 __cil_tmp21 ;

  {
  {
#line 6956
  __cil_tmp5 = dev->dev_private;
#line 6956
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 6959
  rgvswctl = i915_read16___2(dev_priv, 70000U);
  }
  {
#line 6960
  __cil_tmp6 = (int )rgvswctl;
#line 6960
  __cil_tmp7 = __cil_tmp6 & 4096;
#line 6960
  if (__cil_tmp7 != 0) {
    {
#line 6961
    drm_ut_debug_printk(1U, "drm", "ironlake_set_drps", "gpu busy, RCS change rejected\n");
    }
#line 6962
    return ((bool )0);
  } else {

  }
  }
  {
#line 6965
  __cil_tmp8 = (int )val;
#line 6965
  __cil_tmp9 = __cil_tmp8 << 8;
#line 6965
  __cil_tmp10 = (short )__cil_tmp9;
#line 6965
  __cil_tmp11 = (int )__cil_tmp10;
#line 6965
  __cil_tmp12 = __cil_tmp11 | 16512;
#line 6965
  rgvswctl = (u16 )__cil_tmp12;
#line 6967
  __cil_tmp13 = (int )rgvswctl;
#line 6967
  __cil_tmp14 = (u16 )__cil_tmp13;
#line 6967
  i915_write16___0(dev_priv, 70000U, __cil_tmp14);
#line 6968
  __cil_tmp15 = dev_priv->regs;
#line 6968
  __cil_tmp16 = (void const volatile   *)__cil_tmp15;
#line 6968
  __cil_tmp17 = __cil_tmp16 + 70000U;
#line 6968
  readw(__cil_tmp17);
#line 6970
  __cil_tmp18 = (unsigned int )rgvswctl;
#line 6970
  __cil_tmp19 = __cil_tmp18 | 4096U;
#line 6970
  rgvswctl = (u16 )__cil_tmp19;
#line 6971
  __cil_tmp20 = (int )rgvswctl;
#line 6971
  __cil_tmp21 = (u16 )__cil_tmp20;
#line 6971
  i915_write16___0(dev_priv, 70000U, __cil_tmp21);
  }
#line 6973
  return ((bool )1);
}
}
#line 6976 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void ironlake_enable_drps(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 rgvmodectl ;
  u32 tmp ;
  u8 fmax ;
  u8 fmin ;
  u8 fstart ;
  u8 vstart ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  unsigned long timeout__ ;
  unsigned long tmp___3 ;
  int ret__ ;
  struct thread_info *tmp___4 ;
  int pfo_ret__ ;
  int tmp___5 ;
  u32 tmp___6 ;
  u32 tmp___7 ;
  u32 tmp___8 ;
  u32 tmp___9 ;
  unsigned int tmp___10 ;
  u32 tmp___11 ;
  void *__cil_tmp24 ;
  u16 __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  u16 __cil_tmp29 ;
  u16 __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  int __cil_tmp33 ;
  u16 __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  u8 __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  int __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  u32 __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  int __cil_tmp48 ;
  int __cil_tmp49 ;
  int __cil_tmp50 ;
  u32 __cil_tmp51 ;
  void *__cil_tmp52 ;
  void const volatile   *__cil_tmp53 ;
  void const volatile   *__cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  unsigned int __cil_tmp56 ;
  unsigned long __cil_tmp57 ;
  long __cil_tmp58 ;
  long __cil_tmp59 ;
  long __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;
  atomic_t const   *__cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  int __cil_tmp65 ;
  u8 __cil_tmp66 ;
  u32 __cil_tmp67 ;
  u32 __cil_tmp68 ;
  unsigned long __cil_tmp69 ;
  unsigned long __cil_tmp70 ;
  struct timespec *__cil_tmp71 ;

  {
  {
#line 6978
  __cil_tmp24 = dev->dev_private;
#line 6978
  dev_priv = (struct drm_i915_private *)__cil_tmp24;
#line 6979
  tmp = i915_read32___6(dev_priv, 70032U);
#line 6979
  rgvmodectl = tmp;
#line 6983
  tmp___0 = i915_read32___6(dev_priv, 70164U);
#line 6983
  __cil_tmp25 = (u16 )tmp___0;
#line 6983
  __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 6983
  __cil_tmp27 = __cil_tmp26 | 1U;
#line 6983
  __cil_tmp28 = (int )__cil_tmp27;
#line 6983
  __cil_tmp29 = (u16 )__cil_tmp28;
#line 6983
  i915_write16___0(dev_priv, 70164U, __cil_tmp29);
#line 6984
  tmp___1 = i915_read32___6(dev_priv, 69633U);
#line 6984
  __cil_tmp30 = (u16 )tmp___1;
#line 6984
  __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 6984
  __cil_tmp32 = __cil_tmp31 | 1U;
#line 6984
  __cil_tmp33 = (int )__cil_tmp32;
#line 6984
  __cil_tmp34 = (u16 )__cil_tmp33;
#line 6984
  i915_write16___0(dev_priv, 69633U, __cil_tmp34);
#line 6987
  i915_write32___4(dev_priv, 70064U, 100000U);
#line 6988
  i915_write32___4(dev_priv, 70068U, 100000U);
#line 6991
  i915_write32___4(dev_priv, 70044U, 90000U);
#line 6992
  i915_write32___4(dev_priv, 70048U, 80000U);
#line 6994
  i915_write32___4(dev_priv, 70012U, 1U);
#line 6997
  __cil_tmp35 = rgvmodectl & 240U;
#line 6997
  __cil_tmp36 = __cil_tmp35 >> 4;
#line 6997
  fmax = (u8 )__cil_tmp36;
#line 6998
  __cil_tmp37 = (u8 )rgvmodectl;
#line 6998
  __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 6998
  __cil_tmp39 = __cil_tmp38 & 15U;
#line 6998
  fmin = (u8 )__cil_tmp39;
#line 6999
  __cil_tmp40 = rgvmodectl & 3840U;
#line 6999
  __cil_tmp41 = __cil_tmp40 >> 8;
#line 6999
  fstart = (u8 )__cil_tmp41;
#line 7002
  __cil_tmp42 = (int )fstart;
#line 7002
  __cil_tmp43 = __cil_tmp42 + 17476;
#line 7002
  __cil_tmp44 = __cil_tmp43 * 4;
#line 7002
  __cil_tmp45 = (u32 )__cil_tmp44;
#line 7002
  tmp___2 = i915_read32___6(dev_priv, __cil_tmp45);
#line 7002
  __cil_tmp46 = tmp___2 & 2130706432U;
#line 7002
  __cil_tmp47 = __cil_tmp46 >> 24;
#line 7002
  vstart = (u8 )__cil_tmp47;
#line 7005
  dev_priv->fmax = fmax;
#line 7006
  dev_priv->fstart = fstart;
#line 7008
  dev_priv->max_delay = fstart;
#line 7009
  dev_priv->min_delay = fmin;
#line 7010
  dev_priv->cur_delay = fstart;
#line 7012
  __cil_tmp48 = (int )fmax;
#line 7012
  __cil_tmp49 = (int )fmin;
#line 7012
  __cil_tmp50 = (int )fstart;
#line 7012
  drm_ut_debug_printk(2U, "drm", "ironlake_enable_drps", "fmax: %d, fmin: %d, fstart: %d\n",
                      __cil_tmp48, __cil_tmp49, __cil_tmp50);
#line 7015
  i915_write32___4(dev_priv, 70016U, 144U);
#line 7021
  __cil_tmp51 = (u32 )vstart;
#line 7021
  i915_write32___4(dev_priv, 70092U, __cil_tmp51);
#line 7022
  __cil_tmp52 = dev_priv->regs;
#line 7022
  __cil_tmp53 = (void const volatile   *)__cil_tmp52;
#line 7022
  __cil_tmp54 = __cil_tmp53 + 70092U;
#line 7022
  readl(__cil_tmp54);
#line 7024
  rgvmodectl = rgvmodectl | 16384U;
#line 7025
  i915_write32___4(dev_priv, 70032U, rgvmodectl);
#line 7027
  __cil_tmp55 = (unsigned int const   )10U;
#line 7027
  __cil_tmp56 = (unsigned int )__cil_tmp55;
#line 7027
  tmp___3 = msecs_to_jiffies(__cil_tmp56);
#line 7027
  __cil_tmp57 = (unsigned long )jiffies;
#line 7027
  timeout__ = tmp___3 + __cil_tmp57;
#line 7027
  ret__ = 0;
  }
#line 7027
  goto ldv_40218;
  ldv_40217: ;
  {
#line 7027
  __cil_tmp58 = (long )jiffies;
#line 7027
  __cil_tmp59 = (long )timeout__;
#line 7027
  __cil_tmp60 = __cil_tmp59 - __cil_tmp58;
#line 7027
  if (__cil_tmp60 < 0L) {
#line 7027
    ret__ = -110;
#line 7027
    goto ldv_40208;
  } else {

  }
  }
  {
#line 7027
  tmp___4 = current_thread_info();
  }
  {
#line 7027
  __cil_tmp61 = tmp___4->preempt_count;
#line 7027
  __cil_tmp62 = __cil_tmp61 & -268435457;
#line 7027
  if (__cil_tmp62 == 0) {
#line 7027
    if (1) {
#line 7027
      goto case_4;
    } else {
#line 7027
      goto switch_default;
#line 7027
      if (0) {
#line 7027
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 7027
        goto ldv_40211;
#line 7027
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7027
        goto ldv_40211;
        case_4: 
#line 7027
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7027
        goto ldv_40211;
#line 7027
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7027
        goto ldv_40211;
        switch_default: 
        {
#line 7027
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_40211: 
    {
#line 7027
    __cil_tmp63 = (atomic_t const   *)(& kgdb_active);
#line 7027
    tmp___5 = atomic_read(__cil_tmp63);
    }
#line 7027
    if (pfo_ret__ != tmp___5) {
      {
#line 7027
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_40218: 
  {
#line 7027
  tmp___6 = i915_read32___6(dev_priv, 70000U);
  }
  {
#line 7027
  __cil_tmp64 = tmp___6 & 4096U;
#line 7027
  if (__cil_tmp64 != 0U) {
#line 7028
    goto ldv_40217;
  } else {
#line 7030
    goto ldv_40208;
  }
  }
  ldv_40208: ;
#line 7027
  if (ret__ != 0) {
    {
#line 7028
    drm_err("ironlake_enable_drps", "stuck trying to change perf mode\n");
    }
  } else {

  }
  {
#line 7029
  msleep(1U);
#line 7031
  __cil_tmp65 = (int )fstart;
#line 7031
  __cil_tmp66 = (u8 )__cil_tmp65;
#line 7031
  ironlake_set_drps(dev, __cil_tmp66);
#line 7033
  tmp___7 = i915_read32___6(dev_priv, 70372U);
#line 7033
  tmp___8 = i915_read32___6(dev_priv, 70376U);
#line 7033
  tmp___9 = i915_read32___6(dev_priv, 70368U);
#line 7033
  __cil_tmp67 = tmp___7 + tmp___8;
#line 7033
  __cil_tmp68 = __cil_tmp67 + tmp___9;
#line 7033
  dev_priv->last_count1 = (u64 )__cil_tmp68;
#line 7035
  __cil_tmp69 = (unsigned long const   )jiffies;
#line 7035
  __cil_tmp70 = (unsigned long )__cil_tmp69;
#line 7035
  tmp___10 = jiffies_to_msecs(__cil_tmp70);
#line 7035
  dev_priv->last_time1 = (unsigned long )tmp___10;
#line 7036
  tmp___11 = i915_read32___6(dev_priv, 70388U);
#line 7036
  dev_priv->last_count2 = (u64 )tmp___11;
#line 7037
  __cil_tmp71 = & dev_priv->last_time2;
#line 7037
  getrawmonotonic(__cil_tmp71);
  }
#line 7038
  return;
}
}
#line 7040 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void ironlake_disable_drps(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u16 rgvswctl ;
  u16 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  void *__cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  u8 __cil_tmp12 ;
  int __cil_tmp13 ;
  u8 __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  u32 __cil_tmp17 ;

  {
  {
#line 7042
  __cil_tmp8 = dev->dev_private;
#line 7042
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 7043
  tmp = i915_read16___2(dev_priv, 70000U);
#line 7043
  rgvswctl = tmp;
#line 7046
  tmp___0 = i915_read32___6(dev_priv, 70016U);
#line 7046
  __cil_tmp9 = tmp___0 & 4294967279U;
#line 7046
  i915_write32___4(dev_priv, 70016U, __cil_tmp9);
#line 7047
  i915_write32___4(dev_priv, 70020U, 16U);
#line 7048
  tmp___1 = i915_read32___6(dev_priv, 278540U);
#line 7048
  __cil_tmp10 = tmp___1 & 4261412863U;
#line 7048
  i915_write32___4(dev_priv, 278540U, __cil_tmp10);
#line 7049
  i915_write32___4(dev_priv, 278536U, 33554432U);
#line 7050
  tmp___2 = i915_read32___6(dev_priv, 278532U);
#line 7050
  __cil_tmp11 = tmp___2 | 33554432U;
#line 7050
  i915_write32___4(dev_priv, 278532U, __cil_tmp11);
#line 7053
  __cil_tmp12 = dev_priv->fstart;
#line 7053
  __cil_tmp13 = (int )__cil_tmp12;
#line 7053
  __cil_tmp14 = (u8 )__cil_tmp13;
#line 7053
  ironlake_set_drps(dev, __cil_tmp14);
#line 7054
  msleep(1U);
#line 7055
  __cil_tmp15 = (unsigned int )rgvswctl;
#line 7055
  __cil_tmp16 = __cil_tmp15 | 4096U;
#line 7055
  rgvswctl = (u16 )__cil_tmp16;
#line 7056
  __cil_tmp17 = (u32 )rgvswctl;
#line 7056
  i915_write32___4(dev_priv, 70000U, __cil_tmp17);
#line 7057
  msleep(1U);
  }
#line 7058
  return;
}
}
#line 7061 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void gen6_set_rps(struct drm_device *dev , u8 val ) 
{ struct drm_i915_private *dev_priv ;
  u32 swreq ;
  void *__cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;

  {
  {
#line 7063
  __cil_tmp5 = dev->dev_private;
#line 7063
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 7066
  __cil_tmp6 = (int )val;
#line 7066
  __cil_tmp7 = __cil_tmp6 << 25;
#line 7066
  swreq = (u32 )__cil_tmp7;
#line 7067
  i915_write32___4(dev_priv, 40968U, swreq);
  }
#line 7068
  return;
}
}
#line 7070 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void gen6_disable_rps(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  void *__cil_tmp4 ;
  spinlock_t *__cil_tmp5 ;
  spinlock_t *__cil_tmp6 ;

  {
  {
#line 7072
  __cil_tmp4 = dev->dev_private;
#line 7072
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 7074
  i915_write32___4(dev_priv, 40968U, 2147483648U);
#line 7075
  i915_write32___4(dev_priv, 41320U, 4294967295U);
#line 7076
  i915_write32___4(dev_priv, 278572U, 0U);
#line 7078
  __cil_tmp5 = & dev_priv->rps_lock;
#line 7078
  spin_lock_irq(__cil_tmp5);
#line 7079
  dev_priv->pm_iir = 0U;
#line 7080
  __cil_tmp6 = & dev_priv->rps_lock;
#line 7080
  spin_unlock_irq(__cil_tmp6);
#line 7082
  tmp = i915_read32___6(dev_priv, 278568U);
#line 7082
  i915_write32___4(dev_priv, 278568U, tmp);
  }
#line 7083
  return;
}
}
#line 7085 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static unsigned long intel_pxfreq(u32 vidfreq ) 
{ unsigned long freq ;
  int div ;
  int post ;
  int pre ;
  unsigned int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;

  {
#line 7088
  __cil_tmp6 = vidfreq & 4128768U;
#line 7088
  __cil_tmp7 = __cil_tmp6 >> 16;
#line 7088
  div = (int )__cil_tmp7;
#line 7089
  __cil_tmp8 = vidfreq & 12288U;
#line 7089
  __cil_tmp9 = __cil_tmp8 >> 12;
#line 7089
  post = (int )__cil_tmp9;
#line 7090
  __cil_tmp10 = (int )vidfreq;
#line 7090
  pre = __cil_tmp10 & 7;
#line 7092
  if (pre == 0) {
#line 7093
    return (0UL);
  } else {

  }
#line 7095
  __cil_tmp11 = pre << post;
#line 7095
  __cil_tmp12 = div * 133333;
#line 7095
  __cil_tmp13 = __cil_tmp12 / __cil_tmp11;
#line 7095
  freq = (unsigned long )__cil_tmp13;
#line 7097
  return (freq);
}
}
#line 7100 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_init_emon(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 lcfuse ;
  u8 pxw[16U] ;
  int i ;
  u32 pxvidfreq ;
  u32 tmp ;
  unsigned long freq ;
  unsigned long tmp___0 ;
  unsigned long vid ;
  unsigned long val ;
  u32 val___0 ;
  void *__cil_tmp13 ;
  void *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  void const volatile   *__cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  u32 __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  u32 __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  u32 __cil_tmp41 ;
  int __cil_tmp42 ;
  int __cil_tmp43 ;
  u32 __cil_tmp44 ;

  {
  {
#line 7102
  __cil_tmp13 = dev->dev_private;
#line 7102
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 7108
  i915_write32___4(dev_priv, 71168U, 0U);
#line 7109
  __cil_tmp14 = dev_priv->regs;
#line 7109
  __cil_tmp15 = (void const volatile   *)__cil_tmp14;
#line 7109
  __cil_tmp16 = __cil_tmp15 + 71168U;
#line 7109
  readl(__cil_tmp16);
#line 7112
  i915_write32___4(dev_priv, 70220U, 352587008U);
#line 7113
  i915_write32___4(dev_priv, 70224U, 8323072U);
#line 7114
  i915_write32___4(dev_priv, 70228U, 505544708U);
#line 7115
  i915_write32___4(dev_priv, 70232U, 67108868U);
#line 7117
  i = 0;
  }
#line 7117
  goto ldv_40250;
  ldv_40249: 
  {
#line 7118
  __cil_tmp17 = i + 17559;
#line 7118
  __cil_tmp18 = __cil_tmp17 * 4;
#line 7118
  __cil_tmp19 = (u32 )__cil_tmp18;
#line 7118
  i915_write32___4(dev_priv, __cil_tmp19, 0U);
#line 7117
  i = i + 1;
  }
  ldv_40250: ;
#line 7117
  if (i <= 4) {
#line 7118
    goto ldv_40249;
  } else {
#line 7120
    goto ldv_40251;
  }
  ldv_40251: 
#line 7119
  i = 0;
#line 7119
  goto ldv_40253;
  ldv_40252: 
  {
#line 7120
  __cil_tmp20 = i + 17564;
#line 7120
  __cil_tmp21 = __cil_tmp20 * 4;
#line 7120
  __cil_tmp22 = (u32 )__cil_tmp21;
#line 7120
  i915_write32___4(dev_priv, __cil_tmp22, 0U);
#line 7119
  i = i + 1;
  }
  ldv_40253: ;
#line 7119
  if (i <= 2) {
#line 7120
    goto ldv_40252;
  } else {
#line 7122
    goto ldv_40254;
  }
  ldv_40254: 
#line 7123
  i = 0;
#line 7123
  goto ldv_40261;
  ldv_40260: 
  {
#line 7124
  __cil_tmp23 = i + 17476;
#line 7124
  __cil_tmp24 = __cil_tmp23 * 4;
#line 7124
  __cil_tmp25 = (u32 )__cil_tmp24;
#line 7124
  tmp = i915_read32___6(dev_priv, __cil_tmp25);
#line 7124
  pxvidfreq = tmp;
#line 7125
  tmp___0 = intel_pxfreq(pxvidfreq);
#line 7125
  freq = tmp___0;
#line 7126
  __cil_tmp26 = pxvidfreq & 2130706432U;
#line 7126
  __cil_tmp27 = __cil_tmp26 >> 24;
#line 7126
  vid = (unsigned long )__cil_tmp27;
#line 7130
  val = vid * vid;
#line 7131
  __cil_tmp28 = freq / 1000UL;
#line 7131
  val = __cil_tmp28 * val;
#line 7132
  val = val * 255UL;
#line 7133
  val = val / 14516100UL;
  }
#line 7134
  if (val > 255UL) {
    {
#line 7135
    drm_err("intel_init_emon", "bad pxval: %ld\n", val);
    }
  } else {

  }
#line 7136
  pxw[i] = (u8 )val;
#line 7123
  i = i + 1;
  ldv_40261: ;
#line 7123
  if (i <= 15) {
#line 7124
    goto ldv_40260;
  } else {
#line 7126
    goto ldv_40262;
  }
  ldv_40262: 
#line 7139
  pxw[14] = (u8 )0U;
#line 7140
  pxw[15] = (u8 )0U;
#line 7142
  i = 0;
#line 7142
  goto ldv_40265;
  ldv_40264: 
  {
#line 7143
  __cil_tmp29 = (int )pxw[i * 4 + 3];
#line 7143
  __cil_tmp30 = (int )pxw[i * 4 + 2];
#line 7143
  __cil_tmp31 = __cil_tmp30 << 8;
#line 7143
  __cil_tmp32 = (int )pxw[i * 4 + 1];
#line 7143
  __cil_tmp33 = __cil_tmp32 << 16;
#line 7143
  __cil_tmp34 = (int )pxw[i * 4];
#line 7143
  __cil_tmp35 = __cil_tmp34 << 24;
#line 7143
  __cil_tmp36 = __cil_tmp35 | __cil_tmp33;
#line 7143
  __cil_tmp37 = __cil_tmp36 | __cil_tmp31;
#line 7143
  __cil_tmp38 = __cil_tmp37 | __cil_tmp29;
#line 7143
  val___0 = (u32 )__cil_tmp38;
#line 7145
  __cil_tmp39 = i + 17817;
#line 7145
  __cil_tmp40 = __cil_tmp39 * 4;
#line 7145
  __cil_tmp41 = (u32 )__cil_tmp40;
#line 7145
  i915_write32___4(dev_priv, __cil_tmp41, val___0);
#line 7142
  i = i + 1;
  }
  ldv_40265: ;
#line 7142
  if (i <= 3) {
#line 7143
    goto ldv_40264;
  } else {
#line 7145
    goto ldv_40266;
  }
  ldv_40266: 
  {
#line 7149
  i915_write32___4(dev_priv, 71176U, 0U);
#line 7150
  i915_write32___4(dev_priv, 71180U, 0U);
#line 7151
  i915_write32___4(dev_priv, 71184U, 32512U);
#line 7152
  i915_write32___4(dev_priv, 71188U, 14U);
#line 7153
  i915_write32___4(dev_priv, 71192U, 917504U);
#line 7154
  i915_write32___4(dev_priv, 71196U, 1744831232U);
#line 7155
  i915_write32___4(dev_priv, 71200U, 1107296256U);
#line 7156
  i915_write32___4(dev_priv, 71204U, 1310769U);
#line 7157
  i915_write32___4(dev_priv, 71208U, 0U);
#line 7158
  i915_write32___4(dev_priv, 71212U, 0U);
#line 7160
  i = 0;
  }
#line 7160
  goto ldv_40268;
  ldv_40267: 
  {
#line 7161
  __cil_tmp42 = i + 17824;
#line 7161
  __cil_tmp43 = __cil_tmp42 * 4;
#line 7161
  __cil_tmp44 = (u32 )__cil_tmp43;
#line 7161
  i915_write32___4(dev_priv, __cil_tmp44, 0U);
#line 7160
  i = i + 1;
  }
  ldv_40268: ;
#line 7160
  if (i <= 7) {
#line 7161
    goto ldv_40267;
  } else {
#line 7163
    goto ldv_40269;
  }
  ldv_40269: 
  {
#line 7164
  i915_write32___4(dev_priv, 71168U, 2147483673U);
#line 7166
  lcfuse = i915_read32___6(dev_priv, 71360U);
#line 7168
  dev_priv->corr = (u8 )lcfuse;
  }
#line 7169
  return;
}
}
#line 7171 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void gen6_enable_rps(struct drm_i915_private *dev_priv ) 
{ u32 rp_state_cap ;
  u32 tmp ;
  u32 gt_perf_status ;
  u32 tmp___0 ;
  u32 pcu_mbox ;
  u32 rc6_mask ;
  int cur_freq ;
  int min_freq ;
  int max_freq ;
  int i ;
  unsigned long timeout__ ;
  unsigned long tmp___1 ;
  int ret__ ;
  struct thread_info *tmp___2 ;
  int pfo_ret__ ;
  int tmp___3 ;
  u32 tmp___4 ;
  unsigned long timeout_____0 ;
  unsigned long tmp___5 ;
  int ret_____0 ;
  struct thread_info *tmp___6 ;
  int pfo_ret_____0 ;
  int tmp___7 ;
  u32 tmp___8 ;
  unsigned long timeout_____1 ;
  unsigned long tmp___9 ;
  int ret_____1 ;
  struct thread_info *tmp___10 ;
  int pfo_ret_____1 ;
  int tmp___11 ;
  u32 tmp___12 ;
  unsigned long timeout_____2 ;
  unsigned long tmp___13 ;
  int ret_____2 ;
  struct thread_info *tmp___14 ;
  int pfo_ret_____2 ;
  int tmp___15 ;
  u32 tmp___16 ;
  int __ret_warn_on ;
  long tmp___17 ;
  struct drm_device *__cil_tmp42 ;
  struct mutex *__cil_tmp43 ;
  u32 __cil_tmp44 ;
  u32 __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  unsigned long __cil_tmp49 ;
  long __cil_tmp50 ;
  long __cil_tmp51 ;
  long __cil_tmp52 ;
  int __cil_tmp53 ;
  int __cil_tmp54 ;
  atomic_t const   *__cil_tmp55 ;
  int __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  unsigned int __cil_tmp58 ;
  unsigned long __cil_tmp59 ;
  long __cil_tmp60 ;
  long __cil_tmp61 ;
  long __cil_tmp62 ;
  int __cil_tmp63 ;
  int __cil_tmp64 ;
  atomic_t const   *__cil_tmp65 ;
  int __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  unsigned int __cil_tmp68 ;
  int __cil_tmp69 ;
  unsigned int __cil_tmp70 ;
  unsigned int __cil_tmp71 ;
  unsigned int __cil_tmp72 ;
  unsigned int __cil_tmp73 ;
  unsigned long __cil_tmp74 ;
  long __cil_tmp75 ;
  long __cil_tmp76 ;
  long __cil_tmp77 ;
  int __cil_tmp78 ;
  int __cil_tmp79 ;
  atomic_t const   *__cil_tmp80 ;
  int __cil_tmp81 ;
  unsigned int __cil_tmp82 ;
  unsigned int __cil_tmp83 ;
  unsigned long __cil_tmp84 ;
  long __cil_tmp85 ;
  long __cil_tmp86 ;
  long __cil_tmp87 ;
  int __cil_tmp88 ;
  int __cil_tmp89 ;
  atomic_t const   *__cil_tmp90 ;
  int __cil_tmp91 ;
  int __cil_tmp92 ;
  int __cil_tmp93 ;
  u32 __cil_tmp94 ;
  spinlock_t *__cil_tmp95 ;
  u32 __cil_tmp96 ;
  int __cil_tmp97 ;
  long __cil_tmp98 ;
  int __cil_tmp99 ;
  int __cil_tmp100 ;
  int __cil_tmp101 ;
  long __cil_tmp102 ;
  spinlock_t *__cil_tmp103 ;
  struct drm_device *__cil_tmp104 ;
  struct mutex *__cil_tmp105 ;

  {
  {
#line 7173
  tmp = i915_read32___6(dev_priv, 1333656U);
#line 7173
  rp_state_cap = tmp;
#line 7174
  tmp___0 = i915_read32___6(dev_priv, 1333576U);
#line 7174
  gt_perf_status = tmp___0;
#line 7175
  rc6_mask = 0U;
#line 7185
  i915_write32___4(dev_priv, 41108U, 0U);
#line 7186
  __cil_tmp42 = dev_priv->dev;
#line 7186
  __cil_tmp43 = & __cil_tmp42->struct_mutex;
#line 7186
  mutex_lock_nested(__cil_tmp43, 0U);
#line 7187
  gen6_gt_force_wake_get(dev_priv);
#line 7190
  i915_write32___4(dev_priv, 41104U, 0U);
#line 7192
  i915_write32___4(dev_priv, 41112U, 65536000U);
#line 7193
  i915_write32___4(dev_priv, 41116U, 2621470U);
#line 7194
  i915_write32___4(dev_priv, 41120U, 30U);
#line 7195
  i915_write32___4(dev_priv, 41128U, 125000U);
#line 7196
  i915_write32___4(dev_priv, 41132U, 25U);
#line 7198
  i = 0;
  }
#line 7198
  goto ldv_40282;
  ldv_40281: 
  {
#line 7199
  __cil_tmp44 = dev_priv->ring[i].mmio_base;
#line 7199
  __cil_tmp45 = __cil_tmp44 + 84U;
#line 7199
  i915_write32___4(dev_priv, __cil_tmp45, 10U);
#line 7198
  i = i + 1;
  }
  ldv_40282: ;
#line 7198
  if (i <= 2) {
#line 7199
    goto ldv_40281;
  } else {
#line 7201
    goto ldv_40283;
  }
  ldv_40283: 
  {
#line 7201
  i915_write32___4(dev_priv, 41136U, 0U);
#line 7202
  i915_write32___4(dev_priv, 41140U, 1000U);
#line 7203
  i915_write32___4(dev_priv, 41144U, 50000U);
#line 7204
  i915_write32___4(dev_priv, 41148U, 100000U);
#line 7205
  i915_write32___4(dev_priv, 41152U, 64000U);
  }
#line 7207
  if (i915_enable_rc6 != 0U) {
#line 7208
    rc6_mask = 393216U;
  } else {

  }
  {
#line 7211
  __cil_tmp46 = rc6_mask | 2281701376U;
#line 7211
  i915_write32___4(dev_priv, 41104U, __cil_tmp46);
#line 7216
  i915_write32___4(dev_priv, 40968U, 335544320U);
#line 7220
  i915_write32___4(dev_priv, 40972U, 402653184U);
#line 7223
  i915_write32___4(dev_priv, 40976U, 1000000U);
#line 7224
  i915_write32___4(dev_priv, 40980U, 302383104U);
#line 7227
  i915_write32___4(dev_priv, 41004U, 10000U);
#line 7228
  i915_write32___4(dev_priv, 41008U, 1000000U);
#line 7229
  i915_write32___4(dev_priv, 41064U, 100000U);
#line 7230
  i915_write32___4(dev_priv, 41068U, 5000000U);
#line 7231
  i915_write32___4(dev_priv, 41072U, 10U);
#line 7232
  i915_write32___4(dev_priv, 40996U, 2961U);
#line 7240
  __cil_tmp47 = (unsigned int const   )500U;
#line 7240
  __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 7240
  tmp___1 = msecs_to_jiffies(__cil_tmp48);
#line 7240
  __cil_tmp49 = (unsigned long )jiffies;
#line 7240
  timeout__ = tmp___1 + __cil_tmp49;
#line 7240
  ret__ = 0;
  }
#line 7240
  goto ldv_40302;
  ldv_40301: ;
  {
#line 7240
  __cil_tmp50 = (long )jiffies;
#line 7240
  __cil_tmp51 = (long )timeout__;
#line 7240
  __cil_tmp52 = __cil_tmp51 - __cil_tmp50;
#line 7240
  if (__cil_tmp52 < 0L) {
#line 7240
    ret__ = -110;
#line 7240
    goto ldv_40292;
  } else {

  }
  }
  {
#line 7240
  tmp___2 = current_thread_info();
  }
  {
#line 7240
  __cil_tmp53 = tmp___2->preempt_count;
#line 7240
  __cil_tmp54 = __cil_tmp53 & -268435457;
#line 7240
  if (__cil_tmp54 == 0) {
#line 7240
    if (1) {
#line 7240
      goto case_4;
    } else {
#line 7240
      goto switch_default;
#line 7240
      if (0) {
#line 7240
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 7240
        goto ldv_40295;
#line 7240
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7240
        goto ldv_40295;
        case_4: 
#line 7240
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7240
        goto ldv_40295;
#line 7240
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7240
        goto ldv_40295;
        switch_default: 
        {
#line 7240
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_40295: 
    {
#line 7240
    __cil_tmp55 = (atomic_t const   *)(& kgdb_active);
#line 7240
    tmp___3 = atomic_read(__cil_tmp55);
    }
#line 7240
    if (pfo_ret__ != tmp___3) {
      {
#line 7240
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_40302: 
  {
#line 7240
  tmp___4 = i915_read32___6(dev_priv, 1278244U);
  }
  {
#line 7240
  __cil_tmp56 = (int )tmp___4;
#line 7240
  if (__cil_tmp56 < 0) {
#line 7241
    goto ldv_40301;
  } else {
#line 7243
    goto ldv_40292;
  }
  }
  ldv_40292: ;
#line 7240
  if (ret__ != 0) {
    {
#line 7242
    drm_err("gen6_enable_rps", "timeout waiting for pcode mailbox to become idle\n");
    }
  } else {

  }
  {
#line 7244
  i915_write32___4(dev_priv, 1278248U, 0U);
#line 7245
  i915_write32___4(dev_priv, 1278244U, 2147483657U);
#line 7248
  __cil_tmp57 = (unsigned int const   )500U;
#line 7248
  __cil_tmp58 = (unsigned int )__cil_tmp57;
#line 7248
  tmp___5 = msecs_to_jiffies(__cil_tmp58);
#line 7248
  __cil_tmp59 = (unsigned long )jiffies;
#line 7248
  timeout_____0 = tmp___5 + __cil_tmp59;
#line 7248
  ret_____0 = 0;
  }
#line 7248
  goto ldv_40323;
  ldv_40322: ;
  {
#line 7248
  __cil_tmp60 = (long )jiffies;
#line 7248
  __cil_tmp61 = (long )timeout_____0;
#line 7248
  __cil_tmp62 = __cil_tmp61 - __cil_tmp60;
#line 7248
  if (__cil_tmp62 < 0L) {
#line 7248
    ret_____0 = -110;
#line 7248
    goto ldv_40313;
  } else {

  }
  }
  {
#line 7248
  tmp___6 = current_thread_info();
  }
  {
#line 7248
  __cil_tmp63 = tmp___6->preempt_count;
#line 7248
  __cil_tmp64 = __cil_tmp63 & -268435457;
#line 7248
  if (__cil_tmp64 == 0) {
#line 7248
    if (1) {
#line 7248
      goto case_4___0;
    } else {
#line 7248
      goto switch_default___0;
#line 7248
      if (0) {
#line 7248
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret_____0): "m" (cpu_number));
#line 7248
        goto ldv_40316;
#line 7248
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret_____0): "m" (cpu_number));
#line 7248
        goto ldv_40316;
        case_4___0: 
#line 7248
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret_____0): "m" (cpu_number));
#line 7248
        goto ldv_40316;
#line 7248
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret_____0): "m" (cpu_number));
#line 7248
        goto ldv_40316;
        switch_default___0: 
        {
#line 7248
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_40316: 
    {
#line 7248
    __cil_tmp65 = (atomic_t const   *)(& kgdb_active);
#line 7248
    tmp___7 = atomic_read(__cil_tmp65);
    }
#line 7248
    if (pfo_ret_____0 != tmp___7) {
      {
#line 7248
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_40323: 
  {
#line 7248
  tmp___8 = i915_read32___6(dev_priv, 1278244U);
  }
  {
#line 7248
  __cil_tmp66 = (int )tmp___8;
#line 7248
  if (__cil_tmp66 < 0) {
#line 7249
    goto ldv_40322;
  } else {
#line 7251
    goto ldv_40313;
  }
  }
  ldv_40313: ;
#line 7248
  if (ret_____0 != 0) {
    {
#line 7250
    drm_err("gen6_enable_rps", "timeout waiting for pcode mailbox to finish\n");
    }
  } else {

  }
  {
#line 7252
  __cil_tmp67 = rp_state_cap & 16711680U;
#line 7252
  __cil_tmp68 = __cil_tmp67 >> 16;
#line 7252
  min_freq = (int )__cil_tmp68;
#line 7253
  __cil_tmp69 = (int )rp_state_cap;
#line 7253
  max_freq = __cil_tmp69 & 255;
#line 7254
  __cil_tmp70 = gt_perf_status & 65280U;
#line 7254
  __cil_tmp71 = __cil_tmp70 >> 8;
#line 7254
  cur_freq = (int )__cil_tmp71;
#line 7257
  __cil_tmp72 = (unsigned int const   )500U;
#line 7257
  __cil_tmp73 = (unsigned int )__cil_tmp72;
#line 7257
  tmp___9 = msecs_to_jiffies(__cil_tmp73);
#line 7257
  __cil_tmp74 = (unsigned long )jiffies;
#line 7257
  timeout_____1 = tmp___9 + __cil_tmp74;
#line 7257
  ret_____1 = 0;
  }
#line 7257
  goto ldv_40343;
  ldv_40342: ;
  {
#line 7257
  __cil_tmp75 = (long )jiffies;
#line 7257
  __cil_tmp76 = (long )timeout_____1;
#line 7257
  __cil_tmp77 = __cil_tmp76 - __cil_tmp75;
#line 7257
  if (__cil_tmp77 < 0L) {
#line 7257
    ret_____1 = -110;
#line 7257
    goto ldv_40333;
  } else {

  }
  }
  {
#line 7257
  tmp___10 = current_thread_info();
  }
  {
#line 7257
  __cil_tmp78 = tmp___10->preempt_count;
#line 7257
  __cil_tmp79 = __cil_tmp78 & -268435457;
#line 7257
  if (__cil_tmp79 == 0) {
#line 7257
    if (1) {
#line 7257
      goto case_4___1;
    } else {
#line 7257
      goto switch_default___1;
#line 7257
      if (0) {
#line 7257
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret_____1): "m" (cpu_number));
#line 7257
        goto ldv_40336;
#line 7257
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret_____1): "m" (cpu_number));
#line 7257
        goto ldv_40336;
        case_4___1: 
#line 7257
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret_____1): "m" (cpu_number));
#line 7257
        goto ldv_40336;
#line 7257
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret_____1): "m" (cpu_number));
#line 7257
        goto ldv_40336;
        switch_default___1: 
        {
#line 7257
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_40336: 
    {
#line 7257
    __cil_tmp80 = (atomic_t const   *)(& kgdb_active);
#line 7257
    tmp___11 = atomic_read(__cil_tmp80);
    }
#line 7257
    if (pfo_ret_____1 != tmp___11) {
      {
#line 7257
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_40343: 
  {
#line 7257
  tmp___12 = i915_read32___6(dev_priv, 1278244U);
  }
  {
#line 7257
  __cil_tmp81 = (int )tmp___12;
#line 7257
  if (__cil_tmp81 < 0) {
#line 7258
    goto ldv_40342;
  } else {
#line 7260
    goto ldv_40333;
  }
  }
  ldv_40333: ;
#line 7257
  if (ret_____1 != 0) {
    {
#line 7259
    drm_err("gen6_enable_rps", "timeout waiting for pcode mailbox to become idle\n");
    }
  } else {

  }
  {
#line 7260
  i915_write32___4(dev_priv, 1278244U, 12U);
#line 7261
  pcu_mbox = i915_read32___6(dev_priv, 1278248U);
#line 7262
  __cil_tmp82 = (unsigned int const   )500U;
#line 7262
  __cil_tmp83 = (unsigned int )__cil_tmp82;
#line 7262
  tmp___13 = msecs_to_jiffies(__cil_tmp83);
#line 7262
  __cil_tmp84 = (unsigned long )jiffies;
#line 7262
  timeout_____2 = tmp___13 + __cil_tmp84;
#line 7262
  ret_____2 = 0;
  }
#line 7262
  goto ldv_40363;
  ldv_40362: ;
  {
#line 7262
  __cil_tmp85 = (long )jiffies;
#line 7262
  __cil_tmp86 = (long )timeout_____2;
#line 7262
  __cil_tmp87 = __cil_tmp86 - __cil_tmp85;
#line 7262
  if (__cil_tmp87 < 0L) {
#line 7262
    ret_____2 = -110;
#line 7262
    goto ldv_40353;
  } else {

  }
  }
  {
#line 7262
  tmp___14 = current_thread_info();
  }
  {
#line 7262
  __cil_tmp88 = tmp___14->preempt_count;
#line 7262
  __cil_tmp89 = __cil_tmp88 & -268435457;
#line 7262
  if (__cil_tmp89 == 0) {
#line 7262
    if (1) {
#line 7262
      goto case_4___2;
    } else {
#line 7262
      goto switch_default___2;
#line 7262
      if (0) {
#line 7262
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret_____2): "m" (cpu_number));
#line 7262
        goto ldv_40356;
#line 7262
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret_____2): "m" (cpu_number));
#line 7262
        goto ldv_40356;
        case_4___2: 
#line 7262
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret_____2): "m" (cpu_number));
#line 7262
        goto ldv_40356;
#line 7262
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret_____2): "m" (cpu_number));
#line 7262
        goto ldv_40356;
        switch_default___2: 
        {
#line 7262
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_40356: 
    {
#line 7262
    __cil_tmp90 = (atomic_t const   *)(& kgdb_active);
#line 7262
    tmp___15 = atomic_read(__cil_tmp90);
    }
#line 7262
    if (pfo_ret_____2 != tmp___15) {
      {
#line 7262
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_40363: 
  {
#line 7262
  tmp___16 = i915_read32___6(dev_priv, 1278244U);
  }
  {
#line 7262
  __cil_tmp91 = (int )tmp___16;
#line 7262
  if (__cil_tmp91 < 0) {
#line 7263
    goto ldv_40362;
  } else {
#line 7265
    goto ldv_40353;
  }
  }
  ldv_40353: ;
#line 7262
  if (ret_____2 != 0) {
    {
#line 7264
    drm_err("gen6_enable_rps", "timeout waiting for pcode mailbox to finish\n");
    }
  } else {

  }
  {
#line 7265
  __cil_tmp92 = (int )pcu_mbox;
#line 7265
  if (__cil_tmp92 < 0) {
    {
#line 7266
    __cil_tmp93 = (int )pcu_mbox;
#line 7266
    max_freq = __cil_tmp93 & 255;
#line 7267
    __cil_tmp94 = pcu_mbox * 50U;
#line 7267
    drm_ut_debug_printk(2U, "drm", "gen6_enable_rps", "overclocking supported, adjusting frequency max to %dMHz\n",
                        __cil_tmp94);
    }
  } else {

  }
  }
  {
#line 7271
  dev_priv->max_delay = (u8 )max_freq;
#line 7272
  dev_priv->min_delay = (u8 )min_freq;
#line 7273
  dev_priv->cur_delay = (u8 )cur_freq;
#line 7276
  i915_write32___4(dev_priv, 278572U, 50331766U);
#line 7284
  __cil_tmp95 = & dev_priv->rps_lock;
#line 7284
  spin_lock_irq(__cil_tmp95);
#line 7285
  __cil_tmp96 = dev_priv->pm_iir;
#line 7285
  __ret_warn_on = __cil_tmp96 != 0U;
#line 7285
  __cil_tmp97 = __ret_warn_on != 0;
#line 7285
  __cil_tmp98 = (long )__cil_tmp97;
#line 7285
  tmp___17 = __builtin_expect(__cil_tmp98, 0L);
  }
#line 7285
  if (tmp___17 != 0L) {
    {
#line 7285
    __cil_tmp99 = (int const   )7285;
#line 7285
    __cil_tmp100 = (int )__cil_tmp99;
#line 7285
    warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p",
                       __cil_tmp100);
    }
  } else {

  }
  {
#line 7285
  __cil_tmp101 = __ret_warn_on != 0;
#line 7285
  __cil_tmp102 = (long )__cil_tmp101;
#line 7285
  __builtin_expect(__cil_tmp102, 0L);
#line 7286
  i915_write32___4(dev_priv, 278564U, 0U);
#line 7287
  __cil_tmp103 = & dev_priv->rps_lock;
#line 7287
  spin_unlock_irq(__cil_tmp103);
#line 7289
  i915_write32___4(dev_priv, 41320U, 0U);
#line 7291
  gen6_gt_force_wake_put(dev_priv);
#line 7292
  __cil_tmp104 = dev_priv->dev;
#line 7292
  __cil_tmp105 = & __cil_tmp104->struct_mutex;
#line 7292
  mutex_unlock(__cil_tmp105);
  }
#line 7293
  return;
}
}
#line 7295 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void ironlake_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  uint32_t dspclk_gate ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  u32 tmp___5 ;
  void *__cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;

  {
  {
#line 7297
  __cil_tmp11 = dev->dev_private;
#line 7297
  dev_priv = (struct drm_i915_private *)__cil_tmp11;
#line 7298
  dspclk_gate = 268435456U;
#line 7301
  dspclk_gate = dspclk_gate | 896U;
#line 7305
  dspclk_gate = dspclk_gate | 32U;
#line 7307
  i915_write32___4(dev_priv, 286752U, 262146U);
#line 7310
  i915_write32___4(dev_priv, 286756U, 2048U);
#line 7313
  i915_write32___4(dev_priv, 270368U, dspclk_gate);
#line 7322
  tmp = i915_read32___6(dev_priv, 270340U);
#line 7322
  __cil_tmp12 = tmp | 6291456U;
#line 7322
  i915_write32___4(dev_priv, 270340U, __cil_tmp12);
#line 7325
  tmp___0 = i915_read32___6(dev_priv, 270368U);
#line 7325
  __cil_tmp13 = tmp___0 | 32U;
#line 7325
  i915_write32___4(dev_priv, 270368U, __cil_tmp13);
#line 7328
  tmp___1 = i915_read32___6(dev_priv, 282624U);
#line 7328
  __cil_tmp14 = tmp___1 | 32768U;
#line 7328
  i915_write32___4(dev_priv, 282624U, __cil_tmp14);
#line 7331
  i915_write32___4(dev_priv, 282896U, 0U);
#line 7332
  i915_write32___4(dev_priv, 282892U, 0U);
#line 7333
  i915_write32___4(dev_priv, 282888U, 0U);
  }
  {
#line 7342
  __cil_tmp15 = dev->pci_device;
#line 7342
  if (__cil_tmp15 == 70) {
    {
#line 7343
    tmp___2 = i915_read32___6(dev_priv, 270336U);
#line 7343
    __cil_tmp16 = tmp___2 | 4194304U;
#line 7343
    i915_write32___4(dev_priv, 270336U, __cil_tmp16);
#line 7346
    tmp___3 = i915_read32___6(dev_priv, 270340U);
#line 7346
    __cil_tmp17 = tmp___3 | 4194304U;
#line 7346
    i915_write32___4(dev_priv, 270340U, __cil_tmp17);
#line 7349
    tmp___4 = i915_read32___6(dev_priv, 270368U);
#line 7349
    __cil_tmp18 = tmp___4 | 896U;
#line 7349
    i915_write32___4(dev_priv, 270368U, __cil_tmp18);
    }
  } else {

  }
  }
  {
#line 7356
  tmp___5 = i915_read32___6(dev_priv, 270340U);
#line 7356
  __cil_tmp19 = tmp___5 | 33554432U;
#line 7356
  i915_write32___4(dev_priv, 270340U, __cil_tmp19);
#line 7359
  i915_write32___4(dev_priv, 8332U, 1073758208U);
  }
#line 7360
  return;
}
}
#line 7364 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void gen6_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  int pipe ;
  uint32_t dspclk_gate ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  u32 tmp___3 ;
  void *__cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  u32 __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  u32 __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  int __cil_tmp22 ;

  {
  {
#line 7366
  __cil_tmp10 = dev->dev_private;
#line 7366
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 7368
  dspclk_gate = 268435456U;
#line 7370
  i915_write32___4(dev_priv, 270368U, dspclk_gate);
#line 7372
  tmp = i915_read32___6(dev_priv, 270340U);
#line 7372
  __cil_tmp11 = tmp | 33554432U;
#line 7372
  i915_write32___4(dev_priv, 270340U, __cil_tmp11);
#line 7376
  i915_write32___4(dev_priv, 282896U, 0U);
#line 7377
  i915_write32___4(dev_priv, 282892U, 0U);
#line 7378
  i915_write32___4(dev_priv, 282888U, 0U);
#line 7389
  tmp___0 = i915_read32___6(dev_priv, 270336U);
#line 7389
  __cil_tmp12 = tmp___0 | 6291456U;
#line 7389
  i915_write32___4(dev_priv, 270336U, __cil_tmp12);
#line 7392
  tmp___1 = i915_read32___6(dev_priv, 270340U);
#line 7392
  __cil_tmp13 = tmp___1 | 6291456U;
#line 7392
  i915_write32___4(dev_priv, 270340U, __cil_tmp13);
#line 7395
  tmp___2 = i915_read32___6(dev_priv, 270368U);
#line 7395
  __cil_tmp14 = tmp___2 | 160U;
#line 7395
  i915_write32___4(dev_priv, 270368U, __cil_tmp14);
#line 7400
  pipe = 0;
  }
#line 7400
  goto ldv_40379;
  ldv_40378: 
  {
#line 7401
  __cil_tmp15 = pipe * 4096;
#line 7401
  __cil_tmp16 = __cil_tmp15 + 459136;
#line 7401
  __cil_tmp17 = (u32 )__cil_tmp16;
#line 7401
  tmp___3 = i915_read32___6(dev_priv, __cil_tmp17);
#line 7401
  __cil_tmp18 = pipe * 4096;
#line 7401
  __cil_tmp19 = __cil_tmp18 + 459136;
#line 7401
  __cil_tmp20 = (u32 )__cil_tmp19;
#line 7401
  __cil_tmp21 = tmp___3 | 16384U;
#line 7401
  i915_write32___4(dev_priv, __cil_tmp20, __cil_tmp21);
#line 7400
  pipe = pipe + 1;
  }
  ldv_40379: ;
  {
#line 7400
  __cil_tmp22 = dev_priv->num_pipe;
#line 7400
  if (__cil_tmp22 > pipe) {
#line 7401
    goto ldv_40378;
  } else {
#line 7403
    goto ldv_40380;
  }
  }
  ldv_40380: ;
#line 7405
  return;
}
}
#line 7406 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void ivybridge_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  int pipe ;
  uint32_t dspclk_gate ;
  u32 tmp ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  u32 __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  u32 __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 7408
  __cil_tmp6 = dev->dev_private;
#line 7408
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 7410
  dspclk_gate = 268435456U;
#line 7412
  i915_write32___4(dev_priv, 270368U, dspclk_gate);
#line 7414
  i915_write32___4(dev_priv, 282896U, 0U);
#line 7415
  i915_write32___4(dev_priv, 282892U, 0U);
#line 7416
  i915_write32___4(dev_priv, 282888U, 0U);
#line 7418
  i915_write32___4(dev_priv, 270368U, 268435456U);
#line 7420
  pipe = 0;
  }
#line 7420
  goto ldv_40388;
  ldv_40387: 
  {
#line 7421
  __cil_tmp7 = pipe * 4096;
#line 7421
  __cil_tmp8 = __cil_tmp7 + 459136;
#line 7421
  __cil_tmp9 = (u32 )__cil_tmp8;
#line 7421
  tmp = i915_read32___6(dev_priv, __cil_tmp9);
#line 7421
  __cil_tmp10 = pipe * 4096;
#line 7421
  __cil_tmp11 = __cil_tmp10 + 459136;
#line 7421
  __cil_tmp12 = (u32 )__cil_tmp11;
#line 7421
  __cil_tmp13 = tmp | 16384U;
#line 7421
  i915_write32___4(dev_priv, __cil_tmp12, __cil_tmp13);
#line 7420
  pipe = pipe + 1;
  }
  ldv_40388: ;
  {
#line 7420
  __cil_tmp14 = dev_priv->num_pipe;
#line 7420
  if (__cil_tmp14 > pipe) {
#line 7421
    goto ldv_40387;
  } else {
#line 7423
    goto ldv_40389;
  }
  }
  ldv_40389: ;
#line 7425
  return;
}
}
#line 7426 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void g4x_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  uint32_t dspclk_gate ;
  void *__cil_tmp4 ;
  int __cil_tmp5 ;

  {
  {
#line 7428
  __cil_tmp4 = dev->dev_private;
#line 7428
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 7431
  i915_write32___4(dev_priv, 25092U, 0U);
#line 7432
  i915_write32___4(dev_priv, 25096U, 704U);
#line 7435
  i915_write32___4(dev_priv, 25104U, 0U);
#line 7436
  dspclk_gate = 268435468U;
  }
  {
#line 7439
  __cil_tmp5 = dev->pci_device;
#line 7439
  if (__cil_tmp5 == 10818) {
#line 7440
    dspclk_gate = dspclk_gate | 262144U;
  } else {

  }
  }
  {
#line 7441
  i915_write32___4(dev_priv, 25088U, dspclk_gate);
  }
#line 7442
  return;
}
}
#line 7444 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void crestline_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  u16 __cil_tmp4 ;

  {
  {
#line 7446
  __cil_tmp3 = dev->dev_private;
#line 7446
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7448
  i915_write32___4(dev_priv, 25092U, 536870912U);
#line 7449
  i915_write32___4(dev_priv, 25096U, 0U);
#line 7450
  i915_write32___4(dev_priv, 25088U, 0U);
#line 7451
  i915_write32___4(dev_priv, 25104U, 0U);
#line 7452
  __cil_tmp4 = (u16 )0;
#line 7452
  i915_write16___0(dev_priv, 25108U, __cil_tmp4);
  }
#line 7453
  return;
}
}
#line 7455 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void broadwater_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;

  {
  {
#line 7457
  __cil_tmp3 = dev->dev_private;
#line 7457
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7459
  i915_write32___4(dev_priv, 25092U, 1887502336U);
#line 7464
  i915_write32___4(dev_priv, 25096U, 0U);
  }
#line 7465
  return;
}
}
#line 7467 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void gen3_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 dstate ;
  u32 tmp ;
  void *__cil_tmp5 ;

  {
  {
#line 7469
  __cil_tmp5 = dev->dev_private;
#line 7469
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 7470
  tmp = i915_read32___6(dev_priv, 24836U);
#line 7470
  dstate = tmp;
#line 7472
  dstate = dstate | 11U;
#line 7474
  i915_write32___4(dev_priv, 24836U, dstate);
  }
#line 7475
  return;
}
}
#line 7477 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void i85x_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;

  {
  {
#line 7479
  __cil_tmp3 = dev->dev_private;
#line 7479
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7481
  i915_write32___4(dev_priv, 25092U, 1U);
  }
#line 7482
  return;
}
}
#line 7484 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void i830_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;

  {
  {
#line 7486
  __cil_tmp3 = dev->dev_private;
#line 7486
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7488
  i915_write32___4(dev_priv, 25088U, 8U);
  }
#line 7489
  return;
}
}
#line 7491 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void ibx_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;

  {
  {
#line 7493
  __cil_tmp3 = dev->dev_private;
#line 7493
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7500
  i915_write32___4(dev_priv, 794656U, 536870912U);
  }
#line 7501
  return;
}
}
#line 7503 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void cpt_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  void *__cil_tmp4 ;
  unsigned int __cil_tmp5 ;

  {
  {
#line 7505
  __cil_tmp4 = dev->dev_private;
#line 7505
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 7512
  i915_write32___4(dev_priv, 794656U, 536870912U);
#line 7513
  tmp = i915_read32___6(dev_priv, 794628U);
#line 7513
  __cil_tmp5 = tmp | 1U;
#line 7513
  i915_write32___4(dev_priv, 794628U, __cil_tmp5);
  }
#line 7514
  return;
}
}
#line 7517 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void ironlake_teardown_rc6(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  struct drm_i915_gem_object *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct drm_i915_gem_object *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct drm_i915_gem_object *__cil_tmp8 ;
  struct drm_i915_gem_object *__cil_tmp9 ;
  struct drm_gem_object *__cil_tmp10 ;
  struct drm_i915_gem_object *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct drm_i915_gem_object *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct drm_i915_gem_object *__cil_tmp15 ;
  struct drm_i915_gem_object *__cil_tmp16 ;
  struct drm_gem_object *__cil_tmp17 ;

  {
#line 7519
  __cil_tmp3 = dev->dev_private;
#line 7519
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
  {
#line 7521
  __cil_tmp4 = (struct drm_i915_gem_object *)0;
#line 7521
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 7521
  __cil_tmp6 = dev_priv->renderctx;
#line 7521
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 7521
  if (__cil_tmp7 != __cil_tmp5) {
    {
#line 7522
    __cil_tmp8 = dev_priv->renderctx;
#line 7522
    i915_gem_object_unpin(__cil_tmp8);
#line 7523
    __cil_tmp9 = dev_priv->renderctx;
#line 7523
    __cil_tmp10 = & __cil_tmp9->base;
#line 7523
    drm_gem_object_unreference(__cil_tmp10);
#line 7524
    dev_priv->renderctx = (struct drm_i915_gem_object *)0;
    }
  } else {

  }
  }
  {
#line 7527
  __cil_tmp11 = (struct drm_i915_gem_object *)0;
#line 7527
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 7527
  __cil_tmp13 = dev_priv->pwrctx;
#line 7527
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 7527
  if (__cil_tmp14 != __cil_tmp12) {
    {
#line 7528
    __cil_tmp15 = dev_priv->pwrctx;
#line 7528
    i915_gem_object_unpin(__cil_tmp15);
#line 7529
    __cil_tmp16 = dev_priv->pwrctx;
#line 7529
    __cil_tmp17 = & __cil_tmp16->base;
#line 7529
    drm_gem_object_unreference(__cil_tmp17);
#line 7530
    dev_priv->pwrctx = (struct drm_i915_gem_object *)0;
    }
  } else {

  }
  }
#line 7532
  return;
}
}
#line 7534 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void ironlake_disable_rc6(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  unsigned long timeout__ ;
  unsigned long tmp___0 ;
  int ret__ ;
  struct thread_info *tmp___1 ;
  int pfo_ret__ ;
  int tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  u32 tmp___5 ;
  void *__cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  long __cil_tmp18 ;
  long __cil_tmp19 ;
  long __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  atomic_t const   *__cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  void *__cil_tmp25 ;
  void const volatile   *__cil_tmp26 ;
  void const volatile   *__cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  void *__cil_tmp29 ;
  void const volatile   *__cil_tmp30 ;
  void const volatile   *__cil_tmp31 ;

  {
  {
#line 7536
  __cil_tmp13 = dev->dev_private;
#line 7536
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 7538
  tmp___5 = i915_read32___6(dev_priv, 8328U);
  }
#line 7538
  if (tmp___5 != 0U) {
    {
#line 7540
    tmp = i915_read32___6(dev_priv, 70072U);
#line 7540
    __cil_tmp14 = tmp | 8388608U;
#line 7540
    i915_write32___4(dev_priv, 70072U, __cil_tmp14);
#line 7541
    __cil_tmp15 = (unsigned int const   )50U;
#line 7541
    __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 7541
    tmp___0 = msecs_to_jiffies(__cil_tmp16);
#line 7541
    __cil_tmp17 = (unsigned long )jiffies;
#line 7541
    timeout__ = tmp___0 + __cil_tmp17;
#line 7541
    ret__ = 0;
    }
#line 7541
    goto ldv_40450;
    ldv_40449: ;
    {
#line 7541
    __cil_tmp18 = (long )jiffies;
#line 7541
    __cil_tmp19 = (long )timeout__;
#line 7541
    __cil_tmp20 = __cil_tmp19 - __cil_tmp18;
#line 7541
    if (__cil_tmp20 < 0L) {
#line 7541
      ret__ = -110;
#line 7541
      goto ldv_40440;
    } else {

    }
    }
    {
#line 7541
    tmp___1 = current_thread_info();
    }
    {
#line 7541
    __cil_tmp21 = tmp___1->preempt_count;
#line 7541
    __cil_tmp22 = __cil_tmp21 & -268435457;
#line 7541
    if (__cil_tmp22 == 0) {
#line 7541
      if (1) {
#line 7541
        goto case_4;
      } else {
#line 7541
        goto switch_default;
#line 7541
        if (0) {
#line 7541
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 7541
          goto ldv_40443;
#line 7541
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7541
          goto ldv_40443;
          case_4: 
#line 7541
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7541
          goto ldv_40443;
#line 7541
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 7541
          goto ldv_40443;
          switch_default: 
          {
#line 7541
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_40443: 
      {
#line 7541
      __cil_tmp23 = (atomic_t const   *)(& kgdb_active);
#line 7541
      tmp___2 = atomic_read(__cil_tmp23);
      }
#line 7541
      if (pfo_ret__ != tmp___2) {
        {
#line 7541
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_40450: 
    {
#line 7541
    tmp___3 = i915_read32___6(dev_priv, 70072U);
    }
    {
#line 7541
    __cil_tmp24 = tmp___3 & 7340032U;
#line 7541
    if (__cil_tmp24 != 0U) {
#line 7542
      goto ldv_40449;
    } else {
#line 7544
      goto ldv_40440;
    }
    }
    ldv_40440: 
    {
#line 7544
    i915_write32___4(dev_priv, 8328U, 0U);
#line 7545
    __cil_tmp25 = dev_priv->regs;
#line 7545
    __cil_tmp26 = (void const volatile   *)__cil_tmp25;
#line 7545
    __cil_tmp27 = __cil_tmp26 + 8328U;
#line 7545
    readl(__cil_tmp27);
#line 7547
    tmp___4 = i915_read32___6(dev_priv, 70072U);
#line 7547
    __cil_tmp28 = tmp___4 & 4286578687U;
#line 7547
    i915_write32___4(dev_priv, 70072U, __cil_tmp28);
#line 7548
    __cil_tmp29 = dev_priv->regs;
#line 7548
    __cil_tmp30 = (void const volatile   *)__cil_tmp29;
#line 7548
    __cil_tmp31 = __cil_tmp30 + 70072U;
#line 7548
    readl(__cil_tmp31);
    }
  } else {

  }
  {
#line 7551
  ironlake_teardown_rc6(dev);
  }
#line 7552
  return;
}
}
#line 7554 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static int ironlake_setup_rc6(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  struct drm_i915_gem_object *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct drm_i915_gem_object *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct drm_i915_gem_object *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct drm_i915_gem_object *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct drm_i915_gem_object *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_i915_gem_object *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct drm_i915_gem_object *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_i915_gem_object *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;

  {
#line 7556
  __cil_tmp3 = dev->dev_private;
#line 7556
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
  {
#line 7558
  __cil_tmp4 = (struct drm_i915_gem_object *)0;
#line 7558
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 7558
  __cil_tmp6 = dev_priv->renderctx;
#line 7558
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 7558
  if (__cil_tmp7 == __cil_tmp5) {
    {
#line 7559
    dev_priv->renderctx = intel_alloc_context_page(dev);
    }
  } else {

  }
  }
  {
#line 7560
  __cil_tmp8 = (struct drm_i915_gem_object *)0;
#line 7560
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 7560
  __cil_tmp10 = dev_priv->renderctx;
#line 7560
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 7560
  if (__cil_tmp11 == __cil_tmp9) {
#line 7561
    return (-12);
  } else {

  }
  }
  {
#line 7563
  __cil_tmp12 = (struct drm_i915_gem_object *)0;
#line 7563
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 7563
  __cil_tmp14 = dev_priv->pwrctx;
#line 7563
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 7563
  if (__cil_tmp15 == __cil_tmp13) {
    {
#line 7564
    dev_priv->pwrctx = intel_alloc_context_page(dev);
    }
  } else {

  }
  }
  {
#line 7565
  __cil_tmp16 = (struct drm_i915_gem_object *)0;
#line 7565
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 7565
  __cil_tmp18 = dev_priv->pwrctx;
#line 7565
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 7565
  if (__cil_tmp19 == __cil_tmp17) {
    {
#line 7566
    ironlake_teardown_rc6(dev);
    }
#line 7567
    return (-12);
  } else {

  }
  }
#line 7570
  return (0);
}
}
#line 7573 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void ironlake_enable_rc6(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  int ret ;
  u32 tmp ;
  void *__cil_tmp5 ;
  struct mutex *__cil_tmp6 ;
  struct mutex *__cil_tmp7 ;
  struct intel_ring_buffer (*__cil_tmp8)[3U] ;
  struct intel_ring_buffer *__cil_tmp9 ;
  struct mutex *__cil_tmp10 ;
  struct intel_ring_buffer (*__cil_tmp11)[3U] ;
  struct intel_ring_buffer *__cil_tmp12 ;
  struct intel_ring_buffer (*__cil_tmp13)[3U] ;
  struct intel_ring_buffer *__cil_tmp14 ;
  struct intel_ring_buffer (*__cil_tmp15)[3U] ;
  struct intel_ring_buffer *__cil_tmp16 ;
  struct drm_i915_gem_object *__cil_tmp17 ;
  uint32_t __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  struct intel_ring_buffer (*__cil_tmp20)[3U] ;
  struct intel_ring_buffer *__cil_tmp21 ;
  struct intel_ring_buffer (*__cil_tmp22)[3U] ;
  struct intel_ring_buffer *__cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;
  struct intel_ring_buffer (*__cil_tmp26)[3U] ;
  struct intel_ring_buffer *__cil_tmp27 ;
  struct intel_ring_buffer (*__cil_tmp28)[3U] ;
  struct intel_ring_buffer *__cil_tmp29 ;
  struct mutex *__cil_tmp30 ;
  struct drm_i915_gem_object *__cil_tmp31 ;
  uint32_t __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  struct mutex *__cil_tmp35 ;

  {
#line 7575
  __cil_tmp5 = dev->dev_private;
#line 7575
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 7581
  if (i915_enable_rc6 == 0U) {
#line 7582
    return;
  } else {

  }
  {
#line 7584
  __cil_tmp6 = & dev->struct_mutex;
#line 7584
  mutex_lock_nested(__cil_tmp6, 0U);
#line 7585
  ret = ironlake_setup_rc6(dev);
  }
#line 7586
  if (ret != 0) {
    {
#line 7587
    __cil_tmp7 = & dev->struct_mutex;
#line 7587
    mutex_unlock(__cil_tmp7);
    }
#line 7588
    return;
  } else {

  }
  {
#line 7595
  __cil_tmp8 = & dev_priv->ring;
#line 7595
  __cil_tmp9 = (struct intel_ring_buffer *)__cil_tmp8;
#line 7595
  ret = intel_ring_begin(__cil_tmp9, 6);
  }
#line 7596
  if (ret != 0) {
    {
#line 7597
    ironlake_teardown_rc6(dev);
#line 7598
    __cil_tmp10 = & dev->struct_mutex;
#line 7598
    mutex_unlock(__cil_tmp10);
    }
#line 7599
    return;
  } else {

  }
  {
#line 7602
  __cil_tmp11 = & dev_priv->ring;
#line 7602
  __cil_tmp12 = (struct intel_ring_buffer *)__cil_tmp11;
#line 7602
  intel_ring_emit(__cil_tmp12, 92274689U);
#line 7603
  __cil_tmp13 = & dev_priv->ring;
#line 7603
  __cil_tmp14 = (struct intel_ring_buffer *)__cil_tmp13;
#line 7603
  intel_ring_emit(__cil_tmp14, 201326592U);
#line 7604
  __cil_tmp15 = & dev_priv->ring;
#line 7604
  __cil_tmp16 = (struct intel_ring_buffer *)__cil_tmp15;
#line 7604
  __cil_tmp17 = dev_priv->renderctx;
#line 7604
  __cil_tmp18 = __cil_tmp17->gtt_offset;
#line 7604
  __cil_tmp19 = __cil_tmp18 | 269U;
#line 7604
  intel_ring_emit(__cil_tmp16, __cil_tmp19);
#line 7609
  __cil_tmp20 = & dev_priv->ring;
#line 7609
  __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
#line 7609
  intel_ring_emit(__cil_tmp21, 92274688U);
#line 7610
  __cil_tmp22 = & dev_priv->ring;
#line 7610
  __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
#line 7610
  intel_ring_emit(__cil_tmp23, 0U);
#line 7611
  __cil_tmp24 = & dev_priv->ring;
#line 7611
  __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 7611
  intel_ring_emit(__cil_tmp25, 33554432U);
#line 7612
  __cil_tmp26 = & dev_priv->ring;
#line 7612
  __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
#line 7612
  intel_ring_advance(__cil_tmp27);
#line 7619
  __cil_tmp28 = & dev_priv->ring;
#line 7619
  __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
#line 7619
  ret = intel_wait_ring_idle(__cil_tmp29);
  }
#line 7620
  if (ret != 0) {
    {
#line 7621
    drm_err("ironlake_enable_rc6", "failed to enable ironlake power power savings\n");
#line 7622
    ironlake_teardown_rc6(dev);
#line 7623
    __cil_tmp30 = & dev->struct_mutex;
#line 7623
    mutex_unlock(__cil_tmp30);
    }
#line 7624
    return;
  } else {

  }
  {
#line 7627
  __cil_tmp31 = dev_priv->pwrctx;
#line 7627
  __cil_tmp32 = __cil_tmp31->gtt_offset;
#line 7627
  __cil_tmp33 = __cil_tmp32 | 1U;
#line 7627
  i915_write32___4(dev_priv, 8328U, __cil_tmp33);
#line 7628
  tmp = i915_read32___6(dev_priv, 70072U);
#line 7628
  __cil_tmp34 = tmp & 4286578687U;
#line 7628
  i915_write32___4(dev_priv, 70072U, __cil_tmp34);
#line 7629
  __cil_tmp35 = & dev->struct_mutex;
#line 7629
  mutex_unlock(__cil_tmp35);
  }
#line 7630
  return;
}
}
#line 7632 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_init_clock_gating(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  void (*__cil_tmp4)(struct drm_device * ) ;
  void (*__cil_tmp5)(struct drm_device * ) ;
  unsigned long __cil_tmp6 ;
  void (*__cil_tmp7)(struct drm_device * ) ;
  unsigned long __cil_tmp8 ;
  void (*__cil_tmp9)(struct drm_device * ) ;

  {
  {
#line 7634
  __cil_tmp3 = dev->dev_private;
#line 7634
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7636
  __cil_tmp4 = dev_priv->display.init_clock_gating;
#line 7636
  (*__cil_tmp4)(dev);
  }
  {
#line 7638
  __cil_tmp5 = (void (*)(struct drm_device * ))0;
#line 7638
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 7638
  __cil_tmp7 = dev_priv->display.init_pch_clock_gating;
#line 7638
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 7638
  if (__cil_tmp8 != __cil_tmp6) {
    {
#line 7639
    __cil_tmp9 = dev_priv->display.init_pch_clock_gating;
#line 7639
    (*__cil_tmp9)(dev);
    }
  } else {

  }
  }
#line 7640
  return;
}
}
#line 7643 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_init_display(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  char *tmp___2 ;
  struct cxsr_latency  const  *tmp___3 ;
  void *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  void *__cil_tmp15 ;
  struct drm_i915_private *__cil_tmp16 ;
  struct intel_device_info  const  *__cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned char __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  void *__cil_tmp21 ;
  struct drm_i915_private *__cil_tmp22 ;
  struct intel_device_info  const  *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char *__cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  void *__cil_tmp28 ;
  struct drm_i915_private *__cil_tmp29 ;
  struct intel_device_info  const  *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  void *__cil_tmp35 ;
  struct drm_i915_private *__cil_tmp36 ;
  struct intel_device_info  const  *__cil_tmp37 ;
  u8 __cil_tmp38 ;
  unsigned char __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  void *__cil_tmp41 ;
  struct drm_i915_private *__cil_tmp42 ;
  struct intel_device_info  const  *__cil_tmp43 ;
  u8 __cil_tmp44 ;
  unsigned char __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  void *__cil_tmp47 ;
  struct drm_i915_private *__cil_tmp48 ;
  struct intel_device_info  const  *__cil_tmp49 ;
  unsigned char *__cil_tmp50 ;
  unsigned char *__cil_tmp51 ;
  unsigned char __cil_tmp52 ;
  unsigned int __cil_tmp53 ;
  int __cil_tmp54 ;
  void *__cil_tmp55 ;
  struct drm_i915_private *__cil_tmp56 ;
  struct intel_device_info  const  *__cil_tmp57 ;
  unsigned char *__cil_tmp58 ;
  unsigned char *__cil_tmp59 ;
  unsigned char __cil_tmp60 ;
  unsigned int __cil_tmp61 ;
  int __cil_tmp62 ;
  void *__cil_tmp63 ;
  struct drm_i915_private *__cil_tmp64 ;
  struct intel_device_info  const  *__cil_tmp65 ;
  unsigned char *__cil_tmp66 ;
  unsigned char *__cil_tmp67 ;
  unsigned char __cil_tmp68 ;
  unsigned int __cil_tmp69 ;
  int __cil_tmp70 ;
  void *__cil_tmp71 ;
  struct drm_i915_private *__cil_tmp72 ;
  struct intel_device_info  const  *__cil_tmp73 ;
  unsigned char *__cil_tmp74 ;
  unsigned char *__cil_tmp75 ;
  unsigned char __cil_tmp76 ;
  unsigned int __cil_tmp77 ;
  void *__cil_tmp78 ;
  struct drm_i915_private *__cil_tmp79 ;
  struct intel_device_info  const  *__cil_tmp80 ;
  unsigned char *__cil_tmp81 ;
  unsigned char *__cil_tmp82 ;
  unsigned char __cil_tmp83 ;
  unsigned int __cil_tmp84 ;
  int __cil_tmp85 ;
  int __cil_tmp86 ;
  int __cil_tmp87 ;
  int __cil_tmp88 ;
  void *__cil_tmp89 ;
  struct drm_i915_private *__cil_tmp90 ;
  struct intel_device_info  const  *__cil_tmp91 ;
  unsigned char *__cil_tmp92 ;
  unsigned char *__cil_tmp93 ;
  unsigned char __cil_tmp94 ;
  unsigned int __cil_tmp95 ;
  void *__cil_tmp96 ;
  struct drm_i915_private *__cil_tmp97 ;
  struct intel_device_info  const  *__cil_tmp98 ;
  u8 __cil_tmp99 ;
  unsigned char __cil_tmp100 ;
  unsigned int __cil_tmp101 ;
  void *__cil_tmp102 ;
  struct drm_i915_private *__cil_tmp103 ;
  struct intel_device_info  const  *__cil_tmp104 ;
  u8 __cil_tmp105 ;
  unsigned char __cil_tmp106 ;
  unsigned int __cil_tmp107 ;
  void *__cil_tmp108 ;
  struct drm_i915_private *__cil_tmp109 ;
  struct intel_device_info  const  *__cil_tmp110 ;
  unsigned char *__cil_tmp111 ;
  unsigned char *__cil_tmp112 ;
  unsigned char __cil_tmp113 ;
  unsigned int __cil_tmp114 ;
  void *__cil_tmp115 ;
  struct drm_i915_private *__cil_tmp116 ;
  enum intel_pch __cil_tmp117 ;
  unsigned int __cil_tmp118 ;
  void *__cil_tmp119 ;
  struct drm_i915_private *__cil_tmp120 ;
  enum intel_pch __cil_tmp121 ;
  unsigned int __cil_tmp122 ;
  void *__cil_tmp123 ;
  struct drm_i915_private *__cil_tmp124 ;
  struct intel_device_info  const  *__cil_tmp125 ;
  u8 __cil_tmp126 ;
  unsigned char __cil_tmp127 ;
  unsigned int __cil_tmp128 ;
  unsigned int __cil_tmp129 ;
  void *__cil_tmp130 ;
  struct drm_i915_private *__cil_tmp131 ;
  struct intel_device_info  const  *__cil_tmp132 ;
  u8 __cil_tmp133 ;
  unsigned char __cil_tmp134 ;
  unsigned int __cil_tmp135 ;
  unsigned int __cil_tmp136 ;
  void *__cil_tmp137 ;
  struct drm_i915_private *__cil_tmp138 ;
  struct intel_device_info  const  *__cil_tmp139 ;
  unsigned char *__cil_tmp140 ;
  unsigned char *__cil_tmp141 ;
  unsigned char __cil_tmp142 ;
  unsigned int __cil_tmp143 ;
  unsigned int __cil_tmp144 ;
  void *__cil_tmp145 ;
  struct drm_i915_private *__cil_tmp146 ;
  struct intel_device_info  const  *__cil_tmp147 ;
  unsigned char *__cil_tmp148 ;
  unsigned char *__cil_tmp149 ;
  unsigned char __cil_tmp150 ;
  unsigned int __cil_tmp151 ;
  int __cil_tmp152 ;
  int __cil_tmp153 ;
  unsigned int __cil_tmp154 ;
  int __cil_tmp155 ;
  unsigned int __cil_tmp156 ;
  int __cil_tmp157 ;
  unsigned int __cil_tmp158 ;
  int __cil_tmp159 ;
  struct cxsr_latency  const  *__cil_tmp160 ;
  unsigned long __cil_tmp161 ;
  unsigned long __cil_tmp162 ;
  unsigned int __cil_tmp163 ;
  unsigned int __cil_tmp164 ;
  unsigned int __cil_tmp165 ;
  void *__cil_tmp166 ;
  struct drm_i915_private *__cil_tmp167 ;
  struct intel_device_info  const  *__cil_tmp168 ;
  unsigned char *__cil_tmp169 ;
  unsigned char *__cil_tmp170 ;
  unsigned char __cil_tmp171 ;
  unsigned int __cil_tmp172 ;
  void *__cil_tmp173 ;
  struct drm_i915_private *__cil_tmp174 ;
  struct intel_device_info  const  *__cil_tmp175 ;
  u8 __cil_tmp176 ;
  unsigned char __cil_tmp177 ;
  unsigned int __cil_tmp178 ;
  void *__cil_tmp179 ;
  struct drm_i915_private *__cil_tmp180 ;
  struct intel_device_info  const  *__cil_tmp181 ;
  unsigned char *__cil_tmp182 ;
  unsigned char *__cil_tmp183 ;
  unsigned char __cil_tmp184 ;
  unsigned int __cil_tmp185 ;
  void *__cil_tmp186 ;
  struct drm_i915_private *__cil_tmp187 ;
  struct intel_device_info  const  *__cil_tmp188 ;
  unsigned char *__cil_tmp189 ;
  unsigned char *__cil_tmp190 ;
  unsigned char __cil_tmp191 ;
  unsigned int __cil_tmp192 ;
  void *__cil_tmp193 ;
  struct drm_i915_private *__cil_tmp194 ;
  struct intel_device_info  const  *__cil_tmp195 ;
  u8 __cil_tmp196 ;
  unsigned char __cil_tmp197 ;
  unsigned int __cil_tmp198 ;
  int __cil_tmp199 ;
  void *__cil_tmp200 ;
  struct drm_i915_private *__cil_tmp201 ;
  struct intel_device_info  const  *__cil_tmp202 ;
  unsigned char *__cil_tmp203 ;
  unsigned char *__cil_tmp204 ;
  unsigned char __cil_tmp205 ;
  unsigned int __cil_tmp206 ;
  int __cil_tmp207 ;
  void *__cil_tmp208 ;
  struct drm_i915_private *__cil_tmp209 ;
  struct intel_device_info  const  *__cil_tmp210 ;
  u8 __cil_tmp211 ;
  int __cil_tmp212 ;
  void *__cil_tmp213 ;
  struct drm_i915_private *__cil_tmp214 ;
  struct intel_device_info  const  *__cil_tmp215 ;
  u8 __cil_tmp216 ;
  int __cil_tmp217 ;
  void *__cil_tmp218 ;
  struct drm_i915_private *__cil_tmp219 ;
  struct intel_device_info  const  *__cil_tmp220 ;
  u8 __cil_tmp221 ;
  int __cil_tmp222 ;
  void *__cil_tmp223 ;
  struct drm_i915_private *__cil_tmp224 ;
  struct intel_device_info  const  *__cil_tmp225 ;
  u8 __cil_tmp226 ;
  int __cil_tmp227 ;
  void *__cil_tmp228 ;
  struct drm_i915_private *__cil_tmp229 ;
  struct intel_device_info  const  *__cil_tmp230 ;
  u8 __cil_tmp231 ;
  int __cil_tmp232 ;
  void *__cil_tmp233 ;
  struct drm_i915_private *__cil_tmp234 ;
  struct intel_device_info  const  *__cil_tmp235 ;
  u8 __cil_tmp236 ;
  int __cil_tmp237 ;

  {
#line 7645
  __cil_tmp8 = dev->dev_private;
#line 7645
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
  {
#line 7648
  __cil_tmp9 = dev->dev_private;
#line 7648
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 7648
  __cil_tmp11 = __cil_tmp10->info;
#line 7648
  __cil_tmp12 = __cil_tmp11->gen;
#line 7648
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 7648
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 7648
  if (__cil_tmp14 == 5U) {
#line 7649
    dev_priv->display.dpms = & ironlake_crtc_dpms;
#line 7650
    dev_priv->display.crtc_mode_set = & ironlake_crtc_mode_set;
  } else {
    {
#line 7648
    __cil_tmp15 = dev->dev_private;
#line 7648
    __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
#line 7648
    __cil_tmp17 = __cil_tmp16->info;
#line 7648
    __cil_tmp18 = __cil_tmp17->gen;
#line 7648
    __cil_tmp19 = (unsigned char )__cil_tmp18;
#line 7648
    __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 7648
    if (__cil_tmp20 == 6U) {
#line 7649
      dev_priv->display.dpms = & ironlake_crtc_dpms;
#line 7650
      dev_priv->display.crtc_mode_set = & ironlake_crtc_mode_set;
    } else {
      {
#line 7648
      __cil_tmp21 = dev->dev_private;
#line 7648
      __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
#line 7648
      __cil_tmp23 = __cil_tmp22->info;
#line 7648
      __cil_tmp24 = (unsigned char *)__cil_tmp23;
#line 7648
      __cil_tmp25 = __cil_tmp24 + 2UL;
#line 7648
      __cil_tmp26 = *__cil_tmp25;
#line 7648
      __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 7648
      if (__cil_tmp27 != 0U) {
#line 7649
        dev_priv->display.dpms = & ironlake_crtc_dpms;
#line 7650
        dev_priv->display.crtc_mode_set = & ironlake_crtc_mode_set;
      } else {
#line 7652
        dev_priv->display.dpms = & i9xx_crtc_dpms;
#line 7653
        dev_priv->display.crtc_mode_set = & i9xx_crtc_mode_set;
      }
      }
    }
    }
  }
  }
  {
#line 7656
  __cil_tmp28 = dev->dev_private;
#line 7656
  __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
#line 7656
  __cil_tmp30 = __cil_tmp29->info;
#line 7656
  __cil_tmp31 = (unsigned char *)__cil_tmp30;
#line 7656
  __cil_tmp32 = __cil_tmp31 + 2UL;
#line 7656
  __cil_tmp33 = *__cil_tmp32;
#line 7656
  __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 7656
  if (__cil_tmp34 != 0U) {
    {
#line 7657
    __cil_tmp35 = dev->dev_private;
#line 7657
    __cil_tmp36 = (struct drm_i915_private *)__cil_tmp35;
#line 7657
    __cil_tmp37 = __cil_tmp36->info;
#line 7657
    __cil_tmp38 = __cil_tmp37->gen;
#line 7657
    __cil_tmp39 = (unsigned char )__cil_tmp38;
#line 7657
    __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 7657
    if (__cil_tmp40 == 5U) {
#line 7658
      dev_priv->display.fbc_enabled = & ironlake_fbc_enabled;
#line 7659
      dev_priv->display.enable_fbc = & ironlake_enable_fbc;
#line 7660
      dev_priv->display.disable_fbc = & ironlake_disable_fbc;
    } else {
      {
#line 7657
      __cil_tmp41 = dev->dev_private;
#line 7657
      __cil_tmp42 = (struct drm_i915_private *)__cil_tmp41;
#line 7657
      __cil_tmp43 = __cil_tmp42->info;
#line 7657
      __cil_tmp44 = __cil_tmp43->gen;
#line 7657
      __cil_tmp45 = (unsigned char )__cil_tmp44;
#line 7657
      __cil_tmp46 = (unsigned int )__cil_tmp45;
#line 7657
      if (__cil_tmp46 == 6U) {
#line 7658
        dev_priv->display.fbc_enabled = & ironlake_fbc_enabled;
#line 7659
        dev_priv->display.enable_fbc = & ironlake_enable_fbc;
#line 7660
        dev_priv->display.disable_fbc = & ironlake_disable_fbc;
      } else {
        {
#line 7657
        __cil_tmp47 = dev->dev_private;
#line 7657
        __cil_tmp48 = (struct drm_i915_private *)__cil_tmp47;
#line 7657
        __cil_tmp49 = __cil_tmp48->info;
#line 7657
        __cil_tmp50 = (unsigned char *)__cil_tmp49;
#line 7657
        __cil_tmp51 = __cil_tmp50 + 2UL;
#line 7657
        __cil_tmp52 = *__cil_tmp51;
#line 7657
        __cil_tmp53 = (unsigned int )__cil_tmp52;
#line 7657
        if (__cil_tmp53 != 0U) {
#line 7658
          dev_priv->display.fbc_enabled = & ironlake_fbc_enabled;
#line 7659
          dev_priv->display.enable_fbc = & ironlake_enable_fbc;
#line 7660
          dev_priv->display.disable_fbc = & ironlake_disable_fbc;
        } else {
          {
#line 7661
          __cil_tmp54 = dev->pci_device;
#line 7661
          if (__cil_tmp54 == 10818) {
#line 7662
            dev_priv->display.fbc_enabled = & g4x_fbc_enabled;
#line 7663
            dev_priv->display.enable_fbc = & g4x_enable_fbc;
#line 7664
            dev_priv->display.disable_fbc = & g4x_disable_fbc;
          } else {
            {
#line 7665
            __cil_tmp55 = dev->dev_private;
#line 7665
            __cil_tmp56 = (struct drm_i915_private *)__cil_tmp55;
#line 7665
            __cil_tmp57 = __cil_tmp56->info;
#line 7665
            __cil_tmp58 = (unsigned char *)__cil_tmp57;
#line 7665
            __cil_tmp59 = __cil_tmp58 + 2UL;
#line 7665
            __cil_tmp60 = *__cil_tmp59;
#line 7665
            __cil_tmp61 = (unsigned int )__cil_tmp60;
#line 7665
            if (__cil_tmp61 != 0U) {
#line 7666
              dev_priv->display.fbc_enabled = & i8xx_fbc_enabled;
#line 7667
              dev_priv->display.enable_fbc = & i8xx_enable_fbc;
#line 7668
              dev_priv->display.disable_fbc = & i8xx_disable_fbc;
            } else {

            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  } else {

  }
  }
  {
#line 7674
  __cil_tmp62 = dev->pci_device;
#line 7674
  if (__cil_tmp62 == 10098) {
#line 7675
    dev_priv->display.get_display_clock_speed = & i945_get_display_clock_speed;
  } else {
    {
#line 7674
    __cil_tmp63 = dev->dev_private;
#line 7674
    __cil_tmp64 = (struct drm_i915_private *)__cil_tmp63;
#line 7674
    __cil_tmp65 = __cil_tmp64->info;
#line 7674
    __cil_tmp66 = (unsigned char *)__cil_tmp65;
#line 7674
    __cil_tmp67 = __cil_tmp66 + 1UL;
#line 7674
    __cil_tmp68 = *__cil_tmp67;
#line 7674
    __cil_tmp69 = (unsigned int )__cil_tmp68;
#line 7674
    if (__cil_tmp69 != 0U) {
      {
#line 7674
      __cil_tmp70 = dev->pci_device;
#line 7674
      if (__cil_tmp70 != 40977) {
#line 7675
        dev_priv->display.get_display_clock_speed = & i945_get_display_clock_speed;
      } else {
#line 7674
        goto _L;
      }
      }
    } else {
      _L: 
      {
#line 7677
      __cil_tmp71 = dev->dev_private;
#line 7677
      __cil_tmp72 = (struct drm_i915_private *)__cil_tmp71;
#line 7677
      __cil_tmp73 = __cil_tmp72->info;
#line 7677
      __cil_tmp74 = (unsigned char *)__cil_tmp73;
#line 7677
      __cil_tmp75 = __cil_tmp74 + 1UL;
#line 7677
      __cil_tmp76 = *__cil_tmp75;
#line 7677
      __cil_tmp77 = (unsigned int )__cil_tmp76;
#line 7677
      if (__cil_tmp77 != 0U) {
#line 7678
        dev_priv->display.get_display_clock_speed = & i915_get_display_clock_speed;
      } else {
        {
#line 7680
        __cil_tmp78 = dev->dev_private;
#line 7680
        __cil_tmp79 = (struct drm_i915_private *)__cil_tmp78;
#line 7680
        __cil_tmp80 = __cil_tmp79->info;
#line 7680
        __cil_tmp81 = (unsigned char *)__cil_tmp80;
#line 7680
        __cil_tmp82 = __cil_tmp81 + 1UL;
#line 7680
        __cil_tmp83 = *__cil_tmp82;
#line 7680
        __cil_tmp84 = (unsigned int )__cil_tmp83;
#line 7680
        if (__cil_tmp84 != 0U) {
#line 7681
          dev_priv->display.get_display_clock_speed = & i9xx_misc_get_display_clock_speed;
        } else {
          {
#line 7680
          __cil_tmp85 = dev->pci_device;
#line 7680
          if (__cil_tmp85 == 9570) {
#line 7681
            dev_priv->display.get_display_clock_speed = & i9xx_misc_get_display_clock_speed;
          } else {
            {
#line 7680
            __cil_tmp86 = dev->pci_device;
#line 7680
            if (__cil_tmp86 == 40977) {
#line 7681
              dev_priv->display.get_display_clock_speed = & i9xx_misc_get_display_clock_speed;
            } else {
              {
#line 7683
              __cil_tmp87 = dev->pci_device;
#line 7683
              if (__cil_tmp87 == 9618) {
#line 7684
                dev_priv->display.get_display_clock_speed = & i915gm_get_display_clock_speed;
              } else {
                {
#line 7686
                __cil_tmp88 = dev->pci_device;
#line 7686
                if (__cil_tmp88 == 9586) {
#line 7687
                  dev_priv->display.get_display_clock_speed = & i865_get_display_clock_speed;
                } else {
                  {
#line 7689
                  __cil_tmp89 = dev->dev_private;
#line 7689
                  __cil_tmp90 = (struct drm_i915_private *)__cil_tmp89;
#line 7689
                  __cil_tmp91 = __cil_tmp90->info;
#line 7689
                  __cil_tmp92 = (unsigned char *)__cil_tmp91;
#line 7689
                  __cil_tmp93 = __cil_tmp92 + 1UL;
#line 7689
                  __cil_tmp94 = *__cil_tmp93;
#line 7689
                  __cil_tmp95 = (unsigned int )__cil_tmp94;
#line 7689
                  if (__cil_tmp95 != 0U) {
#line 7690
                    dev_priv->display.get_display_clock_speed = & i855_get_display_clock_speed;
                  } else {
#line 7693
                    dev_priv->display.get_display_clock_speed = & i830_get_display_clock_speed;
                  }
                  }
                }
                }
              }
              }
            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
  {
#line 7697
  __cil_tmp96 = dev->dev_private;
#line 7697
  __cil_tmp97 = (struct drm_i915_private *)__cil_tmp96;
#line 7697
  __cil_tmp98 = __cil_tmp97->info;
#line 7697
  __cil_tmp99 = __cil_tmp98->gen;
#line 7697
  __cil_tmp100 = (unsigned char )__cil_tmp99;
#line 7697
  __cil_tmp101 = (unsigned int )__cil_tmp100;
#line 7697
  if (__cil_tmp101 == 5U) {
#line 7697
    goto _L___0;
  } else {
    {
#line 7697
    __cil_tmp102 = dev->dev_private;
#line 7697
    __cil_tmp103 = (struct drm_i915_private *)__cil_tmp102;
#line 7697
    __cil_tmp104 = __cil_tmp103->info;
#line 7697
    __cil_tmp105 = __cil_tmp104->gen;
#line 7697
    __cil_tmp106 = (unsigned char )__cil_tmp105;
#line 7697
    __cil_tmp107 = (unsigned int )__cil_tmp106;
#line 7697
    if (__cil_tmp107 == 6U) {
#line 7697
      goto _L___0;
    } else {
      {
#line 7697
      __cil_tmp108 = dev->dev_private;
#line 7697
      __cil_tmp109 = (struct drm_i915_private *)__cil_tmp108;
#line 7697
      __cil_tmp110 = __cil_tmp109->info;
#line 7697
      __cil_tmp111 = (unsigned char *)__cil_tmp110;
#line 7697
      __cil_tmp112 = __cil_tmp111 + 2UL;
#line 7697
      __cil_tmp113 = *__cil_tmp112;
#line 7697
      __cil_tmp114 = (unsigned int )__cil_tmp113;
#line 7697
      if (__cil_tmp114 != 0U) {
        _L___0: 
        {
#line 7698
        __cil_tmp115 = dev->dev_private;
#line 7698
        __cil_tmp116 = (struct drm_i915_private *)__cil_tmp115;
#line 7698
        __cil_tmp117 = __cil_tmp116->pch_type;
#line 7698
        __cil_tmp118 = (unsigned int )__cil_tmp117;
#line 7698
        if (__cil_tmp118 == 0U) {
#line 7699
          dev_priv->display.init_pch_clock_gating = & ibx_init_clock_gating;
        } else {
          {
#line 7700
          __cil_tmp119 = dev->dev_private;
#line 7700
          __cil_tmp120 = (struct drm_i915_private *)__cil_tmp119;
#line 7700
          __cil_tmp121 = __cil_tmp120->pch_type;
#line 7700
          __cil_tmp122 = (unsigned int )__cil_tmp121;
#line 7700
          if (__cil_tmp122 == 1U) {
#line 7701
            dev_priv->display.init_pch_clock_gating = & cpt_init_clock_gating;
          } else {

          }
          }
        }
        }
        {
#line 7703
        __cil_tmp123 = dev->dev_private;
#line 7703
        __cil_tmp124 = (struct drm_i915_private *)__cil_tmp123;
#line 7703
        __cil_tmp125 = __cil_tmp124->info;
#line 7703
        __cil_tmp126 = __cil_tmp125->gen;
#line 7703
        __cil_tmp127 = (unsigned char )__cil_tmp126;
#line 7703
        __cil_tmp128 = (unsigned int )__cil_tmp127;
#line 7703
        if (__cil_tmp128 == 5U) {
          {
#line 7704
          tmp = i915_read32___6(dev_priv, 70178U);
          }
          {
#line 7704
          __cil_tmp129 = tmp & 63U;
#line 7704
          if (__cil_tmp129 != 0U) {
#line 7705
            dev_priv->display.update_wm = & ironlake_update_wm;
          } else {
            {
#line 7707
            drm_ut_debug_printk(4U, "drm", "intel_init_display", "Failed to get proper latency. Disable CxSR\n");
#line 7709
            dev_priv->display.update_wm = (void (*)(struct drm_device * ))0;
            }
          }
          }
#line 7711
          dev_priv->display.fdi_link_train = & ironlake_fdi_link_train;
#line 7712
          dev_priv->display.init_clock_gating = & ironlake_init_clock_gating;
        } else {
          {
#line 7713
          __cil_tmp130 = dev->dev_private;
#line 7713
          __cil_tmp131 = (struct drm_i915_private *)__cil_tmp130;
#line 7713
          __cil_tmp132 = __cil_tmp131->info;
#line 7713
          __cil_tmp133 = __cil_tmp132->gen;
#line 7713
          __cil_tmp134 = (unsigned char )__cil_tmp133;
#line 7713
          __cil_tmp135 = (unsigned int )__cil_tmp134;
#line 7713
          if (__cil_tmp135 == 6U) {
            {
#line 7714
            tmp___0 = i915_read32___6(dev_priv, 1334544U);
            }
            {
#line 7714
            __cil_tmp136 = tmp___0 & 63U;
#line 7714
            if (__cil_tmp136 != 0U) {
#line 7715
              dev_priv->display.update_wm = & sandybridge_update_wm;
            } else {
              {
#line 7717
              drm_ut_debug_printk(4U, "drm", "intel_init_display", "Failed to read display plane latency. Disable CxSR\n");
#line 7719
              dev_priv->display.update_wm = (void (*)(struct drm_device * ))0;
              }
            }
            }
#line 7721
            dev_priv->display.fdi_link_train = & gen6_fdi_link_train;
#line 7722
            dev_priv->display.init_clock_gating = & gen6_init_clock_gating;
          } else {
            {
#line 7723
            __cil_tmp137 = dev->dev_private;
#line 7723
            __cil_tmp138 = (struct drm_i915_private *)__cil_tmp137;
#line 7723
            __cil_tmp139 = __cil_tmp138->info;
#line 7723
            __cil_tmp140 = (unsigned char *)__cil_tmp139;
#line 7723
            __cil_tmp141 = __cil_tmp140 + 2UL;
#line 7723
            __cil_tmp142 = *__cil_tmp141;
#line 7723
            __cil_tmp143 = (unsigned int )__cil_tmp142;
#line 7723
            if (__cil_tmp143 != 0U) {
              {
#line 7725
              dev_priv->display.fdi_link_train = & ivb_manual_fdi_link_train;
#line 7726
              tmp___1 = i915_read32___6(dev_priv, 1334544U);
              }
              {
#line 7726
              __cil_tmp144 = tmp___1 & 63U;
#line 7726
              if (__cil_tmp144 != 0U) {
#line 7727
                dev_priv->display.update_wm = & sandybridge_update_wm;
              } else {
                {
#line 7729
                drm_ut_debug_printk(4U, "drm", "intel_init_display", "Failed to read display plane latency. Disable CxSR\n");
#line 7731
                dev_priv->display.update_wm = (void (*)(struct drm_device * ))0;
                }
              }
              }
#line 7733
              dev_priv->display.init_clock_gating = & ivybridge_init_clock_gating;
            } else {
#line 7736
              dev_priv->display.update_wm = (void (*)(struct drm_device * ))0;
            }
            }
          }
          }
        }
        }
      } else {
        {
#line 7737
        __cil_tmp145 = dev->dev_private;
#line 7737
        __cil_tmp146 = (struct drm_i915_private *)__cil_tmp145;
#line 7737
        __cil_tmp147 = __cil_tmp146->info;
#line 7737
        __cil_tmp148 = (unsigned char *)__cil_tmp147;
#line 7737
        __cil_tmp149 = __cil_tmp148 + 1UL;
#line 7737
        __cil_tmp150 = *__cil_tmp149;
#line 7737
        __cil_tmp151 = (unsigned int )__cil_tmp150;
#line 7737
        if (__cil_tmp151 != 0U) {
          {
#line 7738
          __cil_tmp152 = dev->pci_device;
#line 7738
          __cil_tmp153 = __cil_tmp152 == 40961;
#line 7738
          __cil_tmp154 = dev_priv->is_ddr3;
#line 7738
          __cil_tmp155 = (int )__cil_tmp154;
#line 7738
          __cil_tmp156 = dev_priv->fsb_freq;
#line 7738
          __cil_tmp157 = (int )__cil_tmp156;
#line 7738
          __cil_tmp158 = dev_priv->mem_freq;
#line 7738
          __cil_tmp159 = (int )__cil_tmp158;
#line 7738
          tmp___3 = intel_get_cxsr_latency(__cil_tmp153, __cil_tmp155, __cil_tmp157,
                                           __cil_tmp159);
          }
          {
#line 7738
          __cil_tmp160 = (struct cxsr_latency  const  *)0;
#line 7738
          __cil_tmp161 = (unsigned long )__cil_tmp160;
#line 7738
          __cil_tmp162 = (unsigned long )tmp___3;
#line 7738
          if (__cil_tmp162 == __cil_tmp161) {
            {
#line 7742
            __cil_tmp163 = dev_priv->is_ddr3;
#line 7742
            if (__cil_tmp163 == 1U) {
#line 7742
              tmp___2 = (char *)"3";
            } else {
#line 7742
              tmp___2 = (char *)"2";
            }
            }
            {
#line 7742
            __cil_tmp164 = dev_priv->fsb_freq;
#line 7742
            __cil_tmp165 = dev_priv->mem_freq;
#line 7742
            printk("<6>[drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR\n",
                   tmp___2, __cil_tmp164, __cil_tmp165);
#line 7748
            pineview_disable_cxsr(dev);
#line 7749
            dev_priv->display.update_wm = (void (*)(struct drm_device * ))0;
            }
          } else {
#line 7751
            dev_priv->display.update_wm = & pineview_update_wm;
          }
          }
#line 7752
          dev_priv->display.init_clock_gating = & gen3_init_clock_gating;
        } else {
          {
#line 7753
          __cil_tmp166 = dev->dev_private;
#line 7753
          __cil_tmp167 = (struct drm_i915_private *)__cil_tmp166;
#line 7753
          __cil_tmp168 = __cil_tmp167->info;
#line 7753
          __cil_tmp169 = (unsigned char *)__cil_tmp168;
#line 7753
          __cil_tmp170 = __cil_tmp169 + 1UL;
#line 7753
          __cil_tmp171 = *__cil_tmp170;
#line 7753
          __cil_tmp172 = (unsigned int )__cil_tmp171;
#line 7753
          if (__cil_tmp172 != 0U) {
#line 7754
            dev_priv->display.update_wm = & g4x_update_wm;
#line 7755
            dev_priv->display.init_clock_gating = & g4x_init_clock_gating;
          } else {
            {
#line 7756
            __cil_tmp173 = dev->dev_private;
#line 7756
            __cil_tmp174 = (struct drm_i915_private *)__cil_tmp173;
#line 7756
            __cil_tmp175 = __cil_tmp174->info;
#line 7756
            __cil_tmp176 = __cil_tmp175->gen;
#line 7756
            __cil_tmp177 = (unsigned char )__cil_tmp176;
#line 7756
            __cil_tmp178 = (unsigned int )__cil_tmp177;
#line 7756
            if (__cil_tmp178 == 4U) {
#line 7757
              dev_priv->display.update_wm = & i965_update_wm;
              {
#line 7758
              __cil_tmp179 = dev->dev_private;
#line 7758
              __cil_tmp180 = (struct drm_i915_private *)__cil_tmp179;
#line 7758
              __cil_tmp181 = __cil_tmp180->info;
#line 7758
              __cil_tmp182 = (unsigned char *)__cil_tmp181;
#line 7758
              __cil_tmp183 = __cil_tmp182 + 2UL;
#line 7758
              __cil_tmp184 = *__cil_tmp183;
#line 7758
              __cil_tmp185 = (unsigned int )__cil_tmp184;
#line 7758
              if (__cil_tmp185 != 0U) {
#line 7759
                dev_priv->display.init_clock_gating = & crestline_init_clock_gating;
              } else {
                {
#line 7760
                __cil_tmp186 = dev->dev_private;
#line 7760
                __cil_tmp187 = (struct drm_i915_private *)__cil_tmp186;
#line 7760
                __cil_tmp188 = __cil_tmp187->info;
#line 7760
                __cil_tmp189 = (unsigned char *)__cil_tmp188;
#line 7760
                __cil_tmp190 = __cil_tmp189 + 2UL;
#line 7760
                __cil_tmp191 = *__cil_tmp190;
#line 7760
                __cil_tmp192 = (unsigned int )__cil_tmp191;
#line 7760
                if (__cil_tmp192 != 0U) {
#line 7761
                  dev_priv->display.init_clock_gating = & broadwater_init_clock_gating;
                } else {

                }
                }
              }
              }
            } else {
              {
#line 7762
              __cil_tmp193 = dev->dev_private;
#line 7762
              __cil_tmp194 = (struct drm_i915_private *)__cil_tmp193;
#line 7762
              __cil_tmp195 = __cil_tmp194->info;
#line 7762
              __cil_tmp196 = __cil_tmp195->gen;
#line 7762
              __cil_tmp197 = (unsigned char )__cil_tmp196;
#line 7762
              __cil_tmp198 = (unsigned int )__cil_tmp197;
#line 7762
              if (__cil_tmp198 == 3U) {
#line 7763
                dev_priv->display.update_wm = & i9xx_update_wm;
#line 7764
                dev_priv->display.get_fifo_size = & i9xx_get_fifo_size;
#line 7765
                dev_priv->display.init_clock_gating = & gen3_init_clock_gating;
              } else {
                {
#line 7766
                __cil_tmp199 = dev->pci_device;
#line 7766
                if (__cil_tmp199 == 9586) {
#line 7767
                  dev_priv->display.update_wm = & i830_update_wm;
#line 7768
                  dev_priv->display.init_clock_gating = & i85x_init_clock_gating;
#line 7769
                  dev_priv->display.get_fifo_size = & i830_get_fifo_size;
                } else {
                  {
#line 7770
                  __cil_tmp200 = dev->dev_private;
#line 7770
                  __cil_tmp201 = (struct drm_i915_private *)__cil_tmp200;
#line 7770
                  __cil_tmp202 = __cil_tmp201->info;
#line 7770
                  __cil_tmp203 = (unsigned char *)__cil_tmp202;
#line 7770
                  __cil_tmp204 = __cil_tmp203 + 1UL;
#line 7770
                  __cil_tmp205 = *__cil_tmp204;
#line 7770
                  __cil_tmp206 = (unsigned int )__cil_tmp205;
#line 7770
                  if (__cil_tmp206 != 0U) {
#line 7771
                    dev_priv->display.update_wm = & i9xx_update_wm;
#line 7772
                    dev_priv->display.get_fifo_size = & i85x_get_fifo_size;
#line 7773
                    dev_priv->display.init_clock_gating = & i85x_init_clock_gating;
                  } else {
#line 7775
                    dev_priv->display.update_wm = & i830_update_wm;
#line 7776
                    dev_priv->display.init_clock_gating = & i830_init_clock_gating;
                    {
#line 7777
                    __cil_tmp207 = dev->pci_device;
#line 7777
                    if (__cil_tmp207 == 9570) {
#line 7778
                      dev_priv->display.get_fifo_size = & i845_get_fifo_size;
                    } else {
#line 7780
                      dev_priv->display.get_fifo_size = & i830_get_fifo_size;
                    }
                    }
                  }
                  }
                }
                }
              }
              }
            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
#line 7784
  dev_priv->display.queue_flip = & intel_default_queue_flip;
  {
#line 7787
  __cil_tmp208 = dev->dev_private;
#line 7787
  __cil_tmp209 = (struct drm_i915_private *)__cil_tmp208;
#line 7787
  __cil_tmp210 = __cil_tmp209->info;
#line 7787
  __cil_tmp211 = __cil_tmp210->gen;
#line 7787
  __cil_tmp212 = (int )__cil_tmp211;
#line 7787
  if (__cil_tmp212 == 2) {
#line 7787
    goto case_2;
  } else {
    {
#line 7791
    __cil_tmp213 = dev->dev_private;
#line 7791
    __cil_tmp214 = (struct drm_i915_private *)__cil_tmp213;
#line 7791
    __cil_tmp215 = __cil_tmp214->info;
#line 7791
    __cil_tmp216 = __cil_tmp215->gen;
#line 7791
    __cil_tmp217 = (int )__cil_tmp216;
#line 7791
    if (__cil_tmp217 == 3) {
#line 7791
      goto case_3;
    } else {
      {
#line 7795
      __cil_tmp218 = dev->dev_private;
#line 7795
      __cil_tmp219 = (struct drm_i915_private *)__cil_tmp218;
#line 7795
      __cil_tmp220 = __cil_tmp219->info;
#line 7795
      __cil_tmp221 = __cil_tmp220->gen;
#line 7795
      __cil_tmp222 = (int )__cil_tmp221;
#line 7795
      if (__cil_tmp222 == 4) {
#line 7795
        goto case_4;
      } else {
        {
#line 7796
        __cil_tmp223 = dev->dev_private;
#line 7796
        __cil_tmp224 = (struct drm_i915_private *)__cil_tmp223;
#line 7796
        __cil_tmp225 = __cil_tmp224->info;
#line 7796
        __cil_tmp226 = __cil_tmp225->gen;
#line 7796
        __cil_tmp227 = (int )__cil_tmp226;
#line 7796
        if (__cil_tmp227 == 5) {
#line 7796
          goto case_5;
        } else {
          {
#line 7800
          __cil_tmp228 = dev->dev_private;
#line 7800
          __cil_tmp229 = (struct drm_i915_private *)__cil_tmp228;
#line 7800
          __cil_tmp230 = __cil_tmp229->info;
#line 7800
          __cil_tmp231 = __cil_tmp230->gen;
#line 7800
          __cil_tmp232 = (int )__cil_tmp231;
#line 7800
          if (__cil_tmp232 == 6) {
#line 7800
            goto case_6;
          } else {
            {
#line 7803
            __cil_tmp233 = dev->dev_private;
#line 7803
            __cil_tmp234 = (struct drm_i915_private *)__cil_tmp233;
#line 7803
            __cil_tmp235 = __cil_tmp234->info;
#line 7803
            __cil_tmp236 = __cil_tmp235->gen;
#line 7803
            __cil_tmp237 = (int )__cil_tmp236;
#line 7803
            if (__cil_tmp237 == 7) {
#line 7803
              goto case_7;
            } else
#line 7786
            if (0) {
              case_2: 
#line 7788
              dev_priv->display.queue_flip = & intel_gen2_queue_flip;
#line 7789
              goto ldv_40472;
              case_3: 
#line 7792
              dev_priv->display.queue_flip = & intel_gen3_queue_flip;
#line 7793
              goto ldv_40472;
              case_4: ;
              case_5: 
#line 7797
              dev_priv->display.queue_flip = & intel_gen4_queue_flip;
#line 7798
              goto ldv_40472;
              case_6: 
#line 7801
              dev_priv->display.queue_flip = & intel_gen6_queue_flip;
#line 7802
              goto ldv_40472;
              case_7: 
#line 7804
              dev_priv->display.queue_flip = & intel_gen7_queue_flip;
#line 7805
              goto ldv_40472;
            } else {

            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_40472: ;
#line 7808
  return;
}
}
#line 7814 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void quirk_pipea_force(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  unsigned long __cil_tmp4 ;

  {
  {
#line 7816
  __cil_tmp3 = dev->dev_private;
#line 7816
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7818
  __cil_tmp4 = dev_priv->quirks;
#line 7818
  dev_priv->quirks = __cil_tmp4 | 1UL;
#line 7819
  drm_ut_debug_printk(2U, "drm", "quirk_pipea_force", "applying pipe a force quirk\n");
  }
#line 7820
  return;
}
}
#line 7825 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void quirk_ssc_force_disable(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  unsigned long __cil_tmp4 ;

  {
#line 7827
  __cil_tmp3 = dev->dev_private;
#line 7827
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
#line 7828
  __cil_tmp4 = dev_priv->quirks;
#line 7828
  dev_priv->quirks = __cil_tmp4 | 2UL;
#line 7829
  return;
}
}
#line 7838 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
struct intel_quirk intel_quirks[9U]  = 
#line 7838
  {      {10818, 4156, 12523, & quirk_pipea_force}, 
        {10158, 4156, 13850, & quirk_pipea_force}, 
        {13687, 4116, 1285, & quirk_pipea_force}, 
        {9618, 4473, 1, & quirk_pipea_force}, 
        {13687, 4116, 1299, & quirk_pipea_force}, 
        {10114, 6058, 8218, & quirk_pipea_force}, 
        {13698, -1, -1, & quirk_pipea_force}, 
        {9570, -1, -1, & quirk_pipea_force}, 
        {70, 6058, 14624, & quirk_ssc_force_disable}};
#line 7864 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void intel_init_quirks(struct drm_device *dev ) 
{ struct pci_dev *d ;
  int i ;
  struct intel_quirk *q ;
  unsigned long __cil_tmp5 ;
  struct intel_quirk *__cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned short __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  unsigned short __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  unsigned short __cil_tmp15 ;
  int __cil_tmp16 ;
  void (*__cil_tmp17)(struct drm_device * ) ;
  int __cil_tmp18 ;
  void (*__cil_tmp19)(struct drm_device * ) ;
  unsigned int __cil_tmp20 ;

  {
#line 7866
  d = dev->pdev;
#line 7869
  i = 0;
#line 7869
  goto ldv_40503;
  ldv_40502: 
#line 7870
  __cil_tmp5 = (unsigned long )i;
#line 7870
  __cil_tmp6 = (struct intel_quirk *)(& intel_quirks);
#line 7870
  q = __cil_tmp6 + __cil_tmp5;
  {
#line 7872
  __cil_tmp7 = q->device;
#line 7872
  __cil_tmp8 = d->device;
#line 7872
  __cil_tmp9 = (int )__cil_tmp8;
#line 7872
  if (__cil_tmp9 == __cil_tmp7) {
    {
#line 7872
    __cil_tmp10 = q->subsystem_vendor;
#line 7872
    __cil_tmp11 = d->subsystem_vendor;
#line 7872
    __cil_tmp12 = (int )__cil_tmp11;
#line 7872
    if (__cil_tmp12 == __cil_tmp10) {
#line 7872
      goto _L;
    } else {
      {
#line 7872
      __cil_tmp13 = q->subsystem_vendor;
#line 7872
      if (__cil_tmp13 == -1) {
        _L: 
        {
#line 7872
        __cil_tmp14 = q->subsystem_device;
#line 7872
        __cil_tmp15 = d->subsystem_device;
#line 7872
        __cil_tmp16 = (int )__cil_tmp15;
#line 7872
        if (__cil_tmp16 == __cil_tmp14) {
          {
#line 7877
          __cil_tmp17 = q->hook;
#line 7877
          (*__cil_tmp17)(dev);
          }
        } else {
          {
#line 7872
          __cil_tmp18 = q->subsystem_device;
#line 7872
          if (__cil_tmp18 == -1) {
            {
#line 7877
            __cil_tmp19 = q->hook;
#line 7877
            (*__cil_tmp19)(dev);
            }
          } else {

          }
          }
        }
        }
      } else {

      }
      }
    }
    }
  } else {

  }
  }
#line 7869
  i = i + 1;
  ldv_40503: ;
  {
#line 7869
  __cil_tmp20 = (unsigned int )i;
#line 7869
  if (__cil_tmp20 <= 8U) {
#line 7870
    goto ldv_40502;
  } else {
#line 7872
    goto ldv_40504;
  }
  }
  ldv_40504: ;
#line 7874
  return;
}
}
#line 7882 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
static void i915_disable_vga(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u8 sr1 ;
  u32 vga_reg ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  struct drm_i915_private *__cil_tmp7 ;
  struct intel_device_info  const  *__cil_tmp8 ;
  u8 __cil_tmp9 ;
  unsigned char __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  void *__cil_tmp12 ;
  struct drm_i915_private *__cil_tmp13 ;
  struct intel_device_info  const  *__cil_tmp14 ;
  u8 __cil_tmp15 ;
  unsigned char __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  void *__cil_tmp18 ;
  struct drm_i915_private *__cil_tmp19 ;
  struct intel_device_info  const  *__cil_tmp20 ;
  unsigned char *__cil_tmp21 ;
  unsigned char *__cil_tmp22 ;
  unsigned char __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  struct pci_dev *__cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  unsigned char __cil_tmp29 ;
  struct pci_dev *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  void *__cil_tmp32 ;
  void const volatile   *__cil_tmp33 ;
  void const volatile   *__cil_tmp34 ;

  {
#line 7884
  __cil_tmp5 = dev->dev_private;
#line 7884
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
  {
#line 7888
  __cil_tmp6 = dev->dev_private;
#line 7888
  __cil_tmp7 = (struct drm_i915_private *)__cil_tmp6;
#line 7888
  __cil_tmp8 = __cil_tmp7->info;
#line 7888
  __cil_tmp9 = __cil_tmp8->gen;
#line 7888
  __cil_tmp10 = (unsigned char )__cil_tmp9;
#line 7888
  __cil_tmp11 = (unsigned int )__cil_tmp10;
#line 7888
  if (__cil_tmp11 == 5U) {
#line 7889
    vga_reg = 266240U;
  } else {
    {
#line 7888
    __cil_tmp12 = dev->dev_private;
#line 7888
    __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
#line 7888
    __cil_tmp14 = __cil_tmp13->info;
#line 7888
    __cil_tmp15 = __cil_tmp14->gen;
#line 7888
    __cil_tmp16 = (unsigned char )__cil_tmp15;
#line 7888
    __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 7888
    if (__cil_tmp17 == 6U) {
#line 7889
      vga_reg = 266240U;
    } else {
      {
#line 7888
      __cil_tmp18 = dev->dev_private;
#line 7888
      __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
#line 7888
      __cil_tmp20 = __cil_tmp19->info;
#line 7888
      __cil_tmp21 = (unsigned char *)__cil_tmp20;
#line 7888
      __cil_tmp22 = __cil_tmp21 + 2UL;
#line 7888
      __cil_tmp23 = *__cil_tmp22;
#line 7888
      __cil_tmp24 = (unsigned int )__cil_tmp23;
#line 7888
      if (__cil_tmp24 != 0U) {
#line 7889
        vga_reg = 266240U;
      } else {
#line 7891
        vga_reg = 463872U;
      }
      }
    }
    }
  }
  }
  {
#line 7893
  __cil_tmp25 = dev->pdev;
#line 7893
  vga_get_uninterruptible(__cil_tmp25, 1U);
#line 7894
  outb((unsigned char)1, 964);
#line 7895
  sr1 = inb(965);
#line 7896
  __cil_tmp26 = (unsigned int )sr1;
#line 7896
  __cil_tmp27 = __cil_tmp26 | 32U;
#line 7896
  __cil_tmp28 = (int )__cil_tmp27;
#line 7896
  __cil_tmp29 = (unsigned char )__cil_tmp28;
#line 7896
  outb(__cil_tmp29, 965);
#line 7897
  __cil_tmp30 = dev->pdev;
#line 7897
  vga_put(__cil_tmp30, 1U);
#line 7898
  __const_udelay(1288500UL);
#line 7900
  i915_write32___4(dev_priv, vga_reg, 2147483648U);
#line 7901
  __cil_tmp31 = (unsigned long )vga_reg;
#line 7901
  __cil_tmp32 = dev_priv->regs;
#line 7901
  __cil_tmp33 = (void const volatile   *)__cil_tmp32;
#line 7901
  __cil_tmp34 = __cil_tmp33 + __cil_tmp31;
#line 7901
  readl(__cil_tmp34);
  }
#line 7902
  return;
}
}
#line 7904 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_modeset_init(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  int i ;
  char *tmp ;
  struct lock_class_key __key ;
  atomic_long_t __constr_expr_0 ;
  struct lock_class_key __key___0 ;
  void *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  void *__cil_tmp15 ;
  struct drm_i915_private *__cil_tmp16 ;
  struct intel_device_info  const  *__cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned char __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  struct drm_agp_head *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  void *__cil_tmp27 ;
  struct drm_i915_private *__cil_tmp28 ;
  struct intel_device_info  const  *__cil_tmp29 ;
  u8 __cil_tmp30 ;
  unsigned char __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  struct work_struct *__cil_tmp33 ;
  struct lockdep_map *__cil_tmp34 ;
  struct list_head *__cil_tmp35 ;
  struct timer_list *__cil_tmp36 ;
  unsigned long __cil_tmp37 ;

  {
  {
#line 7906
  __cil_tmp8 = dev->dev_private;
#line 7906
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 7909
  drm_mode_config_init(dev);
#line 7911
  dev->mode_config.min_width = 0;
#line 7912
  dev->mode_config.min_height = 0;
#line 7914
  dev->mode_config.funcs = (struct drm_mode_config_funcs *)(& intel_mode_funcs);
#line 7916
  intel_init_quirks(dev);
#line 7918
  intel_init_display(dev);
  }
  {
#line 7920
  __cil_tmp9 = dev->dev_private;
#line 7920
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 7920
  __cil_tmp11 = __cil_tmp10->info;
#line 7920
  __cil_tmp12 = __cil_tmp11->gen;
#line 7920
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 7920
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 7920
  if (__cil_tmp14 == 2U) {
#line 7921
    dev->mode_config.max_width = 2048;
#line 7922
    dev->mode_config.max_height = 2048;
  } else {
    {
#line 7923
    __cil_tmp15 = dev->dev_private;
#line 7923
    __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
#line 7923
    __cil_tmp17 = __cil_tmp16->info;
#line 7923
    __cil_tmp18 = __cil_tmp17->gen;
#line 7923
    __cil_tmp19 = (unsigned char )__cil_tmp18;
#line 7923
    __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 7923
    if (__cil_tmp20 == 3U) {
#line 7924
      dev->mode_config.max_width = 4096;
#line 7925
      dev->mode_config.max_height = 4096;
    } else {
#line 7927
      dev->mode_config.max_width = 8192;
#line 7928
      dev->mode_config.max_height = 8192;
    }
    }
  }
  }
#line 7930
  __cil_tmp21 = dev->agp;
#line 7930
  __cil_tmp22 = __cil_tmp21->base;
#line 7930
  dev->mode_config.fb_base = (resource_size_t )__cil_tmp22;
  {
#line 7932
  __cil_tmp23 = dev_priv->num_pipe;
#line 7932
  if (__cil_tmp23 > 1) {
#line 7932
    tmp = (char *)"s";
  } else {
#line 7932
    tmp = (char *)"";
  }
  }
  {
#line 7932
  __cil_tmp24 = dev_priv->num_pipe;
#line 7932
  drm_ut_debug_printk(4U, "drm", "intel_modeset_init", "%d display pipe%s available.\n",
                      __cil_tmp24, tmp);
#line 7935
  i = 0;
  }
#line 7935
  goto ldv_40518;
  ldv_40517: 
  {
#line 7936
  intel_crtc_init(dev, i);
#line 7935
  i = i + 1;
  }
  ldv_40518: ;
  {
#line 7935
  __cil_tmp25 = dev_priv->num_pipe;
#line 7935
  if (__cil_tmp25 > i) {
#line 7936
    goto ldv_40517;
  } else {
#line 7938
    goto ldv_40519;
  }
  }
  ldv_40519: 
  {
#line 7940
  i915_disable_vga(dev);
#line 7941
  intel_setup_outputs(dev);
#line 7943
  intel_init_clock_gating(dev);
  }
  {
#line 7945
  __cil_tmp26 = dev->pci_device;
#line 7945
  if (__cil_tmp26 == 70) {
    {
#line 7946
    ironlake_enable_drps(dev);
#line 7947
    intel_init_emon(dev);
    }
  } else {

  }
  }
  {
#line 7950
  __cil_tmp27 = dev->dev_private;
#line 7950
  __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
#line 7950
  __cil_tmp29 = __cil_tmp28->info;
#line 7950
  __cil_tmp30 = __cil_tmp29->gen;
#line 7950
  __cil_tmp31 = (unsigned char )__cil_tmp30;
#line 7950
  __cil_tmp32 = (unsigned int )__cil_tmp31;
#line 7950
  if (__cil_tmp32 == 6U) {
    {
#line 7951
    gen6_enable_rps(dev_priv);
    }
  } else {

  }
  }
  {
#line 7953
  __cil_tmp33 = & dev_priv->idle_work;
#line 7953
  __init_work(__cil_tmp33, 0);
#line 7953
  __constr_expr_0.counter = 2097664L;
#line 7953
  dev_priv->idle_work.data = __constr_expr_0;
#line 7953
  __cil_tmp34 = & dev_priv->idle_work.lockdep_map;
#line 7953
  lockdep_init_map(__cil_tmp34, "(&dev_priv->idle_work)", & __key, 0);
#line 7953
  __cil_tmp35 = & dev_priv->idle_work.entry;
#line 7953
  INIT_LIST_HEAD(__cil_tmp35);
#line 7953
  dev_priv->idle_work.func = & intel_idle_update;
#line 7954
  __cil_tmp36 = & dev_priv->idle_timer;
#line 7954
  __cil_tmp37 = (unsigned long )dev;
#line 7954
  setup_timer_key(__cil_tmp36, "&dev_priv->idle_timer", & __key___0, & intel_gpu_idle_timer,
                  __cil_tmp37);
  }
#line 7956
  return;
}
}
#line 7958 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_modeset_gem_init(struct drm_device *dev ) 
{ int __cil_tmp2 ;

  {
  {
#line 7960
  __cil_tmp2 = dev->pci_device;
#line 7960
  if (__cil_tmp2 == 70) {
    {
#line 7961
    ironlake_enable_rc6(dev);
    }
  } else {

  }
  }
  {
#line 7963
  intel_setup_overlay(dev);
  }
#line 7964
  return;
}
}
#line 7966 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_modeset_cleanup(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct list_head  const  *__mptr ;
  struct drm_crtc  const  *__mptr___0 ;
  struct list_head  const  *__mptr___1 ;
  struct list_head  const  *__mptr___2 ;
  struct drm_crtc  const  *__mptr___3 ;
  struct list_head  const  *__mptr___4 ;
  void *__cil_tmp11 ;
  struct mutex *__cil_tmp12 ;
  struct list_head *__cil_tmp13 ;
  struct drm_crtc *__cil_tmp14 ;
  struct drm_framebuffer *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct drm_framebuffer *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  struct list_head *__cil_tmp19 ;
  struct drm_crtc *__cil_tmp20 ;
  struct list_head *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct list_head *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  void (*__cil_tmp25)(struct drm_device * ) ;
  unsigned long __cil_tmp26 ;
  void (*__cil_tmp27)(struct drm_device * ) ;
  unsigned long __cil_tmp28 ;
  void (*__cil_tmp29)(struct drm_device * ) ;
  int __cil_tmp30 ;
  void *__cil_tmp31 ;
  struct drm_i915_private *__cil_tmp32 ;
  struct intel_device_info  const  *__cil_tmp33 ;
  u8 __cil_tmp34 ;
  unsigned char __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  int __cil_tmp37 ;
  struct mutex *__cil_tmp38 ;
  struct work_struct *__cil_tmp39 ;
  struct list_head *__cil_tmp40 ;
  struct drm_crtc *__cil_tmp41 ;
  struct timer_list *__cil_tmp42 ;
  struct list_head *__cil_tmp43 ;
  struct drm_crtc *__cil_tmp44 ;
  struct list_head *__cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  struct list_head *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  struct timer_list *__cil_tmp49 ;
  struct work_struct *__cil_tmp50 ;

  {
  {
#line 7968
  __cil_tmp11 = dev->dev_private;
#line 7968
  dev_priv = (struct drm_i915_private *)__cil_tmp11;
#line 7972
  drm_kms_helper_poll_fini(dev);
#line 7973
  __cil_tmp12 = & dev->struct_mutex;
#line 7973
  mutex_lock_nested(__cil_tmp12, 0U);
#line 7975
  intel_unregister_dsm_handler();
#line 7978
  __cil_tmp13 = dev->mode_config.crtc_list.next;
#line 7978
  __mptr = (struct list_head  const  *)__cil_tmp13;
#line 7978
  __cil_tmp14 = (struct drm_crtc *)__mptr;
#line 7978
  crtc = __cil_tmp14 + 1152921504606846968UL;
  }
#line 7978
  goto ldv_40540;
  ldv_40539: ;
  {
#line 7980
  __cil_tmp15 = (struct drm_framebuffer *)0;
#line 7980
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 7980
  __cil_tmp17 = crtc->fb;
#line 7980
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 7980
  if (__cil_tmp18 == __cil_tmp16) {
#line 7981
    goto ldv_40536;
  } else {

  }
  }
  {
#line 7983
  __mptr___0 = (struct drm_crtc  const  *)crtc;
#line 7983
  intel_crtc = (struct intel_crtc *)__mptr___0;
#line 7984
  intel_increase_pllclock(crtc);
  }
  ldv_40536: 
#line 7978
  __cil_tmp19 = crtc->head.next;
#line 7978
  __mptr___1 = (struct list_head  const  *)__cil_tmp19;
#line 7978
  __cil_tmp20 = (struct drm_crtc *)__mptr___1;
#line 7978
  crtc = __cil_tmp20 + 1152921504606846968UL;
  ldv_40540: ;
  {
#line 7978
  __cil_tmp21 = & dev->mode_config.crtc_list;
#line 7978
  __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 7978
  __cil_tmp23 = & crtc->head;
#line 7978
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 7978
  if (__cil_tmp24 != __cil_tmp22) {
#line 7979
    goto ldv_40539;
  } else {
#line 7981
    goto ldv_40541;
  }
  }
  ldv_40541: ;
  {
#line 7987
  __cil_tmp25 = (void (*)(struct drm_device * ))0;
#line 7987
  __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 7987
  __cil_tmp27 = dev_priv->display.disable_fbc;
#line 7987
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 7987
  if (__cil_tmp28 != __cil_tmp26) {
    {
#line 7988
    __cil_tmp29 = dev_priv->display.disable_fbc;
#line 7988
    (*__cil_tmp29)(dev);
    }
  } else {

  }
  }
  {
#line 7990
  __cil_tmp30 = dev->pci_device;
#line 7990
  if (__cil_tmp30 == 70) {
    {
#line 7991
    ironlake_disable_drps(dev);
    }
  } else {

  }
  }
  {
#line 7992
  __cil_tmp31 = dev->dev_private;
#line 7992
  __cil_tmp32 = (struct drm_i915_private *)__cil_tmp31;
#line 7992
  __cil_tmp33 = __cil_tmp32->info;
#line 7992
  __cil_tmp34 = __cil_tmp33->gen;
#line 7992
  __cil_tmp35 = (unsigned char )__cil_tmp34;
#line 7992
  __cil_tmp36 = (unsigned int )__cil_tmp35;
#line 7992
  if (__cil_tmp36 == 6U) {
    {
#line 7993
    gen6_disable_rps(dev);
    }
  } else {

  }
  }
  {
#line 7995
  __cil_tmp37 = dev->pci_device;
#line 7995
  if (__cil_tmp37 == 70) {
    {
#line 7996
    ironlake_disable_rc6(dev);
    }
  } else {

  }
  }
  {
#line 7998
  __cil_tmp38 = & dev->struct_mutex;
#line 7998
  mutex_unlock(__cil_tmp38);
#line 8002
  drm_irq_uninstall(dev);
#line 8003
  __cil_tmp39 = & dev_priv->hotplug_work;
#line 8003
  cancel_work_sync(__cil_tmp39);
#line 8006
  __cil_tmp40 = dev->mode_config.crtc_list.next;
#line 8006
  __mptr___2 = (struct list_head  const  *)__cil_tmp40;
#line 8006
  __cil_tmp41 = (struct drm_crtc *)__mptr___2;
#line 8006
  crtc = __cil_tmp41 + 1152921504606846968UL;
  }
#line 8006
  goto ldv_40549;
  ldv_40548: 
  {
#line 8007
  __mptr___3 = (struct drm_crtc  const  *)crtc;
#line 8007
  intel_crtc = (struct intel_crtc *)__mptr___3;
#line 8008
  __cil_tmp42 = & intel_crtc->idle_timer;
#line 8008
  del_timer_sync(__cil_tmp42);
#line 8006
  __cil_tmp43 = crtc->head.next;
#line 8006
  __mptr___4 = (struct list_head  const  *)__cil_tmp43;
#line 8006
  __cil_tmp44 = (struct drm_crtc *)__mptr___4;
#line 8006
  crtc = __cil_tmp44 + 1152921504606846968UL;
  }
  ldv_40549: ;
  {
#line 8006
  __cil_tmp45 = & dev->mode_config.crtc_list;
#line 8006
  __cil_tmp46 = (unsigned long )__cil_tmp45;
#line 8006
  __cil_tmp47 = & crtc->head;
#line 8006
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 8006
  if (__cil_tmp48 != __cil_tmp46) {
#line 8007
    goto ldv_40548;
  } else {
#line 8009
    goto ldv_40550;
  }
  }
  ldv_40550: 
  {
#line 8010
  __cil_tmp49 = & dev_priv->idle_timer;
#line 8010
  del_timer_sync(__cil_tmp49);
#line 8011
  __cil_tmp50 = & dev_priv->idle_work;
#line 8011
  cancel_work_sync(__cil_tmp50);
#line 8013
  drm_mode_config_cleanup(dev);
  }
#line 8014
  return;
}
}
#line 8019 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
struct drm_encoder *intel_best_encoder(struct drm_connector *connector ) 
{ struct intel_encoder *tmp ;

  {
  {
#line 8021
  tmp = intel_attached_encoder(connector);
  }
#line 8021
  return (& tmp->base);
}
}
#line 8024 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_connector_attach_encoder(struct intel_connector *connector , struct intel_encoder *encoder ) 
{ struct drm_connector *__cil_tmp3 ;
  struct drm_encoder *__cil_tmp4 ;

  {
  {
#line 8027
  connector->encoder = encoder;
#line 8028
  __cil_tmp3 = & connector->base;
#line 8028
  __cil_tmp4 = & encoder->base;
#line 8028
  drm_mode_connector_attach_encoder(__cil_tmp3, __cil_tmp4);
  }
#line 8030
  return;
}
}
#line 8035 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
int intel_modeset_vga_set_state(struct drm_device *dev , bool state ) 
{ struct drm_i915_private *dev_priv ;
  u16 gmch_ctrl ;
  void *__cil_tmp5 ;
  struct pci_dev *__cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  struct pci_dev *__cil_tmp11 ;
  int __cil_tmp12 ;
  u16 __cil_tmp13 ;

  {
  {
#line 8037
  __cil_tmp5 = dev->dev_private;
#line 8037
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 8040
  __cil_tmp6 = dev_priv->bridge_dev;
#line 8040
  pci_read_config_word(__cil_tmp6, 82, & gmch_ctrl);
  }
#line 8041
  if ((int )state) {
#line 8042
    __cil_tmp7 = (unsigned int )gmch_ctrl;
#line 8042
    __cil_tmp8 = __cil_tmp7 & 65533U;
#line 8042
    gmch_ctrl = (u16 )__cil_tmp8;
  } else {
#line 8044
    __cil_tmp9 = (unsigned int )gmch_ctrl;
#line 8044
    __cil_tmp10 = __cil_tmp9 | 2U;
#line 8044
    gmch_ctrl = (u16 )__cil_tmp10;
  }
  {
#line 8045
  __cil_tmp11 = dev_priv->bridge_dev;
#line 8045
  __cil_tmp12 = (int )gmch_ctrl;
#line 8045
  __cil_tmp13 = (u16 )__cil_tmp12;
#line 8045
  pci_write_config_word(__cil_tmp11, 82, __cil_tmp13);
  }
#line 8046
  return (0);
}
}
#line 8084 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_display_error_state *error ;
  int i ;
  void *tmp ;
  void *__cil_tmp6 ;
  struct intel_display_error_state *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  u32 __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  u32 __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  u32 __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  u32 __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  u32 __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  u32 __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  u32 __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  u32 __cil_tmp33 ;
  void *__cil_tmp34 ;
  struct drm_i915_private *__cil_tmp35 ;
  struct intel_device_info  const  *__cil_tmp36 ;
  u8 __cil_tmp37 ;
  unsigned char __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  u32 __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  u32 __cil_tmp45 ;
  int __cil_tmp46 ;
  int __cil_tmp47 ;
  u32 __cil_tmp48 ;
  int __cil_tmp49 ;
  int __cil_tmp50 ;
  u32 __cil_tmp51 ;
  int __cil_tmp52 ;
  int __cil_tmp53 ;
  u32 __cil_tmp54 ;
  int __cil_tmp55 ;
  int __cil_tmp56 ;
  u32 __cil_tmp57 ;
  int __cil_tmp58 ;
  int __cil_tmp59 ;
  u32 __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;
  u32 __cil_tmp63 ;
  int __cil_tmp64 ;
  int __cil_tmp65 ;
  u32 __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  u32 __cil_tmp69 ;

  {
  {
#line 8086
  __cil_tmp6 = dev->dev_private;
#line 8086
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
#line 8090
  tmp = kmalloc(152UL, 32U);
#line 8090
  error = (struct intel_display_error_state *)tmp;
  }
  {
#line 8091
  __cil_tmp7 = (struct intel_display_error_state *)0;
#line 8091
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 8091
  __cil_tmp9 = (unsigned long )error;
#line 8091
  if (__cil_tmp9 == __cil_tmp8) {
#line 8092
    return ((struct intel_display_error_state *)0);
  } else {

  }
  }
#line 8094
  i = 0;
#line 8094
  goto ldv_40596;
  ldv_40595: 
  {
#line 8095
  __cil_tmp10 = i + 7170;
#line 8095
  __cil_tmp11 = __cil_tmp10 * 64;
#line 8095
  __cil_tmp12 = (u32 )__cil_tmp11;
#line 8095
  error->cursor[i].control = i915_read32___6(dev_priv, __cil_tmp12);
#line 8096
  __cil_tmp13 = i * 64;
#line 8096
  __cil_tmp14 = __cil_tmp13 + 458888;
#line 8096
  __cil_tmp15 = (u32 )__cil_tmp14;
#line 8096
  error->cursor[i].position = i915_read32___6(dev_priv, __cil_tmp15);
#line 8097
  __cil_tmp16 = i * 64;
#line 8097
  __cil_tmp17 = __cil_tmp16 + 458884;
#line 8097
  __cil_tmp18 = (u32 )__cil_tmp17;
#line 8097
  error->cursor[i].base = i915_read32___6(dev_priv, __cil_tmp18);
#line 8099
  __cil_tmp19 = i * 4096;
#line 8099
  __cil_tmp20 = __cil_tmp19 + 459136;
#line 8099
  __cil_tmp21 = (u32 )__cil_tmp20;
#line 8099
  error->plane[i].control = i915_read32___6(dev_priv, __cil_tmp21);
#line 8100
  __cil_tmp22 = i * 4096;
#line 8100
  __cil_tmp23 = __cil_tmp22 + 459144;
#line 8100
  __cil_tmp24 = (u32 )__cil_tmp23;
#line 8100
  error->plane[i].stride = i915_read32___6(dev_priv, __cil_tmp24);
#line 8101
  __cil_tmp25 = i * 4096;
#line 8101
  __cil_tmp26 = __cil_tmp25 + 459152;
#line 8101
  __cil_tmp27 = (u32 )__cil_tmp26;
#line 8101
  error->plane[i].size = i915_read32___6(dev_priv, __cil_tmp27);
#line 8102
  __cil_tmp28 = i * 4096;
#line 8102
  __cil_tmp29 = __cil_tmp28 + 459148;
#line 8102
  __cil_tmp30 = (u32 )__cil_tmp29;
#line 8102
  error->plane[i].pos = i915_read32___6(dev_priv, __cil_tmp30);
#line 8103
  __cil_tmp31 = i * 4096;
#line 8103
  __cil_tmp32 = __cil_tmp31 + 459140;
#line 8103
  __cil_tmp33 = (u32 )__cil_tmp32;
#line 8103
  error->plane[i].addr = i915_read32___6(dev_priv, __cil_tmp33);
  }
  {
#line 8104
  __cil_tmp34 = dev->dev_private;
#line 8104
  __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
#line 8104
  __cil_tmp36 = __cil_tmp35->info;
#line 8104
  __cil_tmp37 = __cil_tmp36->gen;
#line 8104
  __cil_tmp38 = (unsigned char )__cil_tmp37;
#line 8104
  __cil_tmp39 = (unsigned int )__cil_tmp38;
#line 8104
  if (__cil_tmp39 > 3U) {
    {
#line 8105
    __cil_tmp40 = i * 4096;
#line 8105
    __cil_tmp41 = __cil_tmp40 + 459164;
#line 8105
    __cil_tmp42 = (u32 )__cil_tmp41;
#line 8105
    error->plane[i].surface = i915_read32___6(dev_priv, __cil_tmp42);
#line 8106
    __cil_tmp43 = i * 4096;
#line 8106
    __cil_tmp44 = __cil_tmp43 + 459172;
#line 8106
    __cil_tmp45 = (u32 )__cil_tmp44;
#line 8106
    error->plane[i].tile_offset = i915_read32___6(dev_priv, __cil_tmp45);
    }
  } else {

  }
  }
  {
#line 8109
  __cil_tmp46 = i * 4096;
#line 8109
  __cil_tmp47 = __cil_tmp46 + 458760;
#line 8109
  __cil_tmp48 = (u32 )__cil_tmp47;
#line 8109
  error->pipe[i].conf = i915_read32___6(dev_priv, __cil_tmp48);
#line 8110
  __cil_tmp49 = i * 4096;
#line 8110
  __cil_tmp50 = __cil_tmp49 + 393244;
#line 8110
  __cil_tmp51 = (u32 )__cil_tmp50;
#line 8110
  error->pipe[i].source = i915_read32___6(dev_priv, __cil_tmp51);
#line 8111
  __cil_tmp52 = i + 96;
#line 8111
  __cil_tmp53 = __cil_tmp52 * 4096;
#line 8111
  __cil_tmp54 = (u32 )__cil_tmp53;
#line 8111
  error->pipe[i].htotal = i915_read32___6(dev_priv, __cil_tmp54);
#line 8112
  __cil_tmp55 = i * 4096;
#line 8112
  __cil_tmp56 = __cil_tmp55 + 393220;
#line 8112
  __cil_tmp57 = (u32 )__cil_tmp56;
#line 8112
  error->pipe[i].hblank = i915_read32___6(dev_priv, __cil_tmp57);
#line 8113
  __cil_tmp58 = i * 4096;
#line 8113
  __cil_tmp59 = __cil_tmp58 + 393224;
#line 8113
  __cil_tmp60 = (u32 )__cil_tmp59;
#line 8113
  error->pipe[i].hsync = i915_read32___6(dev_priv, __cil_tmp60);
#line 8114
  __cil_tmp61 = i * 4096;
#line 8114
  __cil_tmp62 = __cil_tmp61 + 393228;
#line 8114
  __cil_tmp63 = (u32 )__cil_tmp62;
#line 8114
  error->pipe[i].vtotal = i915_read32___6(dev_priv, __cil_tmp63);
#line 8115
  __cil_tmp64 = i * 4096;
#line 8115
  __cil_tmp65 = __cil_tmp64 + 393232;
#line 8115
  __cil_tmp66 = (u32 )__cil_tmp65;
#line 8115
  error->pipe[i].vblank = i915_read32___6(dev_priv, __cil_tmp66);
#line 8116
  __cil_tmp67 = i * 4096;
#line 8116
  __cil_tmp68 = __cil_tmp67 + 393236;
#line 8116
  __cil_tmp69 = (u32 )__cil_tmp68;
#line 8116
  error->pipe[i].vsync = i915_read32___6(dev_priv, __cil_tmp69);
#line 8094
  i = i + 1;
  }
  ldv_40596: ;
#line 8094
  if (i <= 1) {
#line 8095
    goto ldv_40595;
  } else {
#line 8097
    goto ldv_40597;
  }
  ldv_40597: ;
#line 8119
  return (error);
}
}
#line 8123 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_display.c.p"
void intel_display_print_error_state(struct seq_file *m , struct drm_device *dev ,
                                     struct intel_display_error_state *error ) 
{ int i ;
  u32 __cil_tmp5 ;
  u32 __cil_tmp6 ;
  u32 __cil_tmp7 ;
  u32 __cil_tmp8 ;
  u32 __cil_tmp9 ;
  u32 __cil_tmp10 ;
  u32 __cil_tmp11 ;
  u32 __cil_tmp12 ;
  u32 __cil_tmp13 ;
  u32 __cil_tmp14 ;
  u32 __cil_tmp15 ;
  u32 __cil_tmp16 ;
  u32 __cil_tmp17 ;
  void *__cil_tmp18 ;
  struct drm_i915_private *__cil_tmp19 ;
  struct intel_device_info  const  *__cil_tmp20 ;
  u8 __cil_tmp21 ;
  unsigned char __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  u32 __cil_tmp24 ;
  u32 __cil_tmp25 ;
  u32 __cil_tmp26 ;
  u32 __cil_tmp27 ;
  u32 __cil_tmp28 ;

  {
#line 8129
  i = 0;
#line 8129
  goto ldv_40605;
  ldv_40604: 
  {
#line 8130
  seq_printf(m, "Pipe [%d]:\n", i);
#line 8131
  __cil_tmp5 = error->pipe[i].conf;
#line 8131
  seq_printf(m, "  CONF: %08x\n", __cil_tmp5);
#line 8132
  __cil_tmp6 = error->pipe[i].source;
#line 8132
  seq_printf(m, "  SRC: %08x\n", __cil_tmp6);
#line 8133
  __cil_tmp7 = error->pipe[i].htotal;
#line 8133
  seq_printf(m, "  HTOTAL: %08x\n", __cil_tmp7);
#line 8134
  __cil_tmp8 = error->pipe[i].hblank;
#line 8134
  seq_printf(m, "  HBLANK: %08x\n", __cil_tmp8);
#line 8135
  __cil_tmp9 = error->pipe[i].hsync;
#line 8135
  seq_printf(m, "  HSYNC: %08x\n", __cil_tmp9);
#line 8136
  __cil_tmp10 = error->pipe[i].vtotal;
#line 8136
  seq_printf(m, "  VTOTAL: %08x\n", __cil_tmp10);
#line 8137
  __cil_tmp11 = error->pipe[i].vblank;
#line 8137
  seq_printf(m, "  VBLANK: %08x\n", __cil_tmp11);
#line 8138
  __cil_tmp12 = error->pipe[i].vsync;
#line 8138
  seq_printf(m, "  VSYNC: %08x\n", __cil_tmp12);
#line 8140
  seq_printf(m, "Plane [%d]:\n", i);
#line 8141
  __cil_tmp13 = error->plane[i].control;
#line 8141
  seq_printf(m, "  CNTR: %08x\n", __cil_tmp13);
#line 8142
  __cil_tmp14 = error->plane[i].stride;
#line 8142
  seq_printf(m, "  STRIDE: %08x\n", __cil_tmp14);
#line 8143
  __cil_tmp15 = error->plane[i].size;
#line 8143
  seq_printf(m, "  SIZE: %08x\n", __cil_tmp15);
#line 8144
  __cil_tmp16 = error->plane[i].pos;
#line 8144
  seq_printf(m, "  POS: %08x\n", __cil_tmp16);
#line 8145
  __cil_tmp17 = error->plane[i].addr;
#line 8145
  seq_printf(m, "  ADDR: %08x\n", __cil_tmp17);
  }
  {
#line 8146
  __cil_tmp18 = dev->dev_private;
#line 8146
  __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
#line 8146
  __cil_tmp20 = __cil_tmp19->info;
#line 8146
  __cil_tmp21 = __cil_tmp20->gen;
#line 8146
  __cil_tmp22 = (unsigned char )__cil_tmp21;
#line 8146
  __cil_tmp23 = (unsigned int )__cil_tmp22;
#line 8146
  if (__cil_tmp23 > 3U) {
    {
#line 8147
    __cil_tmp24 = error->plane[i].surface;
#line 8147
    seq_printf(m, "  SURF: %08x\n", __cil_tmp24);
#line 8148
    __cil_tmp25 = error->plane[i].tile_offset;
#line 8148
    seq_printf(m, "  TILEOFF: %08x\n", __cil_tmp25);
    }
  } else {

  }
  }
  {
#line 8151
  seq_printf(m, "Cursor [%d]:\n", i);
#line 8152
  __cil_tmp26 = error->cursor[i].control;
#line 8152
  seq_printf(m, "  CNTR: %08x\n", __cil_tmp26);
#line 8153
  __cil_tmp27 = error->cursor[i].position;
#line 8153
  seq_printf(m, "  POS: %08x\n", __cil_tmp27);
#line 8154
  __cil_tmp28 = error->cursor[i].base;
#line 8154
  seq_printf(m, "  BASE: %08x\n", __cil_tmp28);
#line 8129
  i = i + 1;
  }
  ldv_40605: ;
#line 8129
  if (i <= 1) {
#line 8130
    goto ldv_40604;
  } else {
#line 8132
    goto ldv_40606;
  }
  ldv_40606: ;
#line 8134
  return;
}
}
#line 640 "include/drm/drm_crtc.h"
extern void drm_connector_init(struct drm_device * , struct drm_connector * , struct drm_connector_funcs  const  * ,
                               int  ) ;
#line 645
extern void drm_connector_cleanup(struct drm_connector * ) ;
#line 647
extern void drm_encoder_init(struct drm_device * , struct drm_encoder * , struct drm_encoder_funcs  const  * ,
                             int  ) ;
#line 662
extern struct edid *drm_get_edid(struct drm_connector * , struct i2c_adapter * ) ;
#line 1530 "include/drm/drmP.h"
extern int drm_sysfs_connector_add(struct drm_connector * ) ;
#line 1531
extern void drm_sysfs_connector_remove(struct drm_connector * ) ;
#line 107 "include/drm/drm_crtc_helper.h"
extern int drm_helper_probe_single_connector_modes(struct drm_connector * , uint32_t  ,
                                                   uint32_t  ) ;
#line 117
extern void drm_helper_connector_dpms(struct drm_connector * , int  ) ;
#line 128 "include/drm/drm_crtc_helper.h"
__inline static void drm_encoder_helper_add(struct drm_encoder *encoder , struct drm_encoder_helper_funcs  const  *funcs ) 
{ 

  {
#line 131
  encoder->helper_private = (void *)funcs;
#line 132
  return;
}
}
#line 134 "include/drm/drm_crtc_helper.h"
__inline static void drm_connector_helper_add(struct drm_connector *connector , struct drm_connector_helper_funcs  const  *funcs ) 
{ 

  {
#line 137
  connector->helper_private = (void *)funcs;
#line 138
  return;
}
}
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___7(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36469: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36469;
      } else {
#line 390
        goto ldv_36470;
      }
      }
      ldv_36470: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1359 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u8 i915_read8___1(struct drm_i915_private *dev_priv , u32 reg ) 
{ u8 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1359
  val = (u8 )0U;
  {
#line 1359
  __cil_tmp4 = dev_priv->info;
#line 1359
  __cil_tmp5 = __cil_tmp4->gen;
#line 1359
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1359
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1359
  if (__cil_tmp7 > 5U) {
#line 1359
    if (reg <= 262143U) {
#line 1359
      if (reg != 41356U) {
        {
#line 1359
        gen6_gt_force_wake_get(dev_priv);
#line 1359
        __cil_tmp8 = (unsigned long )reg;
#line 1359
        __cil_tmp9 = dev_priv->regs;
#line 1359
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1359
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1359
        val = readb(__cil_tmp11);
#line 1359
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1359
        __cil_tmp12 = (unsigned long )reg;
#line 1359
        __cil_tmp13 = dev_priv->regs;
#line 1359
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1359
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1359
        val = readb(__cil_tmp15);
        }
      }
    } else {
      {
#line 1359
      __cil_tmp16 = (unsigned long )reg;
#line 1359
      __cil_tmp17 = dev_priv->regs;
#line 1359
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1359
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1359
      val = readb(__cil_tmp19);
      }
    }
  } else {
    {
#line 1359
    __cil_tmp20 = (unsigned long )reg;
#line 1359
    __cil_tmp21 = dev_priv->regs;
#line 1359
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1359
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1359
    val = readb(__cil_tmp23);
    }
  }
  }
  {
#line 1359
  __cil_tmp24 = (bool )0;
#line 1359
  __cil_tmp25 = (u64 )val;
#line 1359
  trace_i915_reg_rw___7(__cil_tmp24, reg, __cil_tmp25, 1);
  }
#line 1359
  return (val);
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___7(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___7(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___5(struct drm_i915_private *dev_priv , u32 reg ,
                                      u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___7(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 236 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
int intel_ddc_get_modes(struct drm_connector *connector , struct i2c_adapter *adapter ) ;
#line 237
bool intel_ddc_probe(struct intel_encoder *intel_encoder , int ddc_bus ) ;
#line 59 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static struct intel_crt *intel_attached_crt(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 61
  tmp = intel_attached_encoder(connector);
#line 61
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 61
  return ((struct intel_crt *)__mptr);
}
}
#line 65 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static void intel_crt_dpms(struct drm_encoder *encoder , int mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 temp ;
  u32 reg ;
  void *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  unsigned char *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char __cil_tmp25 ;
  unsigned int __cil_tmp26 ;

  {
#line 67
  dev = encoder->dev;
#line 68
  __cil_tmp7 = dev->dev_private;
#line 68
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
  {
#line 71
  __cil_tmp8 = dev->dev_private;
#line 71
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 71
  __cil_tmp10 = __cil_tmp9->info;
#line 71
  __cil_tmp11 = __cil_tmp10->gen;
#line 71
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 71
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 71
  if (__cil_tmp13 == 5U) {
#line 72
    reg = 921856U;
  } else {
    {
#line 71
    __cil_tmp14 = dev->dev_private;
#line 71
    __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 71
    __cil_tmp16 = __cil_tmp15->info;
#line 71
    __cil_tmp17 = __cil_tmp16->gen;
#line 71
    __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 71
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 71
    if (__cil_tmp19 == 6U) {
#line 72
      reg = 921856U;
    } else {
      {
#line 71
      __cil_tmp20 = dev->dev_private;
#line 71
      __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 71
      __cil_tmp22 = __cil_tmp21->info;
#line 71
      __cil_tmp23 = (unsigned char *)__cil_tmp22;
#line 71
      __cil_tmp24 = __cil_tmp23 + 2UL;
#line 71
      __cil_tmp25 = *__cil_tmp24;
#line 71
      __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 71
      if (__cil_tmp26 != 0U) {
#line 72
        reg = 921856U;
      } else {
#line 74
        reg = 397568U;
      }
      }
    }
    }
  }
  }
  {
#line 76
  temp = i915_read32___7(dev_priv, reg);
#line 77
  temp = temp & 4294964223U;
#line 78
  temp = temp & 2147483647U;
  }
#line 81
  if (mode == 0) {
#line 81
    goto case_0;
  } else
#line 84
  if (mode == 1) {
#line 84
    goto case_1;
  } else
#line 87
  if (mode == 2) {
#line 87
    goto case_2;
  } else
#line 90
  if (mode == 3) {
#line 90
    goto case_3;
  } else
#line 80
  if (0) {
    case_0: 
#line 82
    temp = temp | 2147483648U;
#line 83
    goto ldv_37660;
    case_1: 
#line 85
    temp = temp | 2147484672U;
#line 86
    goto ldv_37660;
    case_2: 
#line 88
    temp = temp | 2147485696U;
#line 89
    goto ldv_37660;
    case_3: 
#line 91
    temp = temp | 3072U;
#line 92
    goto ldv_37660;
  } else {

  }
  ldv_37660: 
  {
#line 95
  i915_write32___5(dev_priv, reg, temp);
  }
#line 96
  return;
}
}
#line 98 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static int intel_crt_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) 
{ struct drm_device *dev ;
  int max_clock ;
  unsigned int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  int __cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  int __cil_tmp14 ;

  {
#line 101
  dev = connector->dev;
#line 103
  max_clock = 0;
  {
#line 104
  __cil_tmp5 = mode->flags;
#line 104
  __cil_tmp6 = __cil_tmp5 & 32U;
#line 104
  if (__cil_tmp6 != 0U) {
#line 105
    return (8);
  } else {

  }
  }
  {
#line 107
  __cil_tmp7 = mode->clock;
#line 107
  if (__cil_tmp7 <= 24999) {
#line 108
    return (16);
  } else {

  }
  }
  {
#line 110
  __cil_tmp8 = dev->dev_private;
#line 110
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 110
  __cil_tmp10 = __cil_tmp9->info;
#line 110
  __cil_tmp11 = __cil_tmp10->gen;
#line 110
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 110
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 110
  if (__cil_tmp13 == 2U) {
#line 111
    max_clock = 350000;
  } else {
#line 113
    max_clock = 400000;
  }
  }
  {
#line 114
  __cil_tmp14 = mode->clock;
#line 114
  if (__cil_tmp14 > max_clock) {
#line 115
    return (15);
  } else {

  }
  }
#line 117
  return (0);
}
}
#line 120 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static bool intel_crt_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                 struct drm_display_mode *adjusted_mode ) 
{ 

  {
#line 124
  return ((bool )1);
}
}
#line 127 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static void intel_crt_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                               struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct drm_i915_private *dev_priv ;
  int dpll_md_reg ;
  u32 adpa ;
  u32 dpll_md ;
  u32 adpa_reg ;
  void *__cil_tmp13 ;
  enum pipe __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  void *__cil_tmp18 ;
  struct drm_i915_private *__cil_tmp19 ;
  struct intel_device_info  const  *__cil_tmp20 ;
  u8 __cil_tmp21 ;
  unsigned char __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  void *__cil_tmp24 ;
  struct drm_i915_private *__cil_tmp25 ;
  struct intel_device_info  const  *__cil_tmp26 ;
  u8 __cil_tmp27 ;
  unsigned char __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  void *__cil_tmp30 ;
  struct drm_i915_private *__cil_tmp31 ;
  struct intel_device_info  const  *__cil_tmp32 ;
  unsigned char *__cil_tmp33 ;
  unsigned char *__cil_tmp34 ;
  unsigned char __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  void *__cil_tmp37 ;
  struct drm_i915_private *__cil_tmp38 ;
  struct intel_device_info  const  *__cil_tmp39 ;
  u8 __cil_tmp40 ;
  unsigned char __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  void *__cil_tmp43 ;
  struct drm_i915_private *__cil_tmp44 ;
  struct intel_device_info  const  *__cil_tmp45 ;
  u8 __cil_tmp46 ;
  unsigned char __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  void *__cil_tmp49 ;
  struct drm_i915_private *__cil_tmp50 ;
  struct intel_device_info  const  *__cil_tmp51 ;
  u8 __cil_tmp52 ;
  unsigned char __cil_tmp53 ;
  unsigned int __cil_tmp54 ;
  void *__cil_tmp55 ;
  struct drm_i915_private *__cil_tmp56 ;
  struct intel_device_info  const  *__cil_tmp57 ;
  unsigned char *__cil_tmp58 ;
  unsigned char *__cil_tmp59 ;
  unsigned char __cil_tmp60 ;
  unsigned int __cil_tmp61 ;
  u32 __cil_tmp62 ;
  u32 __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  unsigned int __cil_tmp65 ;
  int __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  unsigned int __cil_tmp68 ;
  enum pipe __cil_tmp69 ;
  unsigned int __cil_tmp70 ;
  void *__cil_tmp71 ;
  struct drm_i915_private *__cil_tmp72 ;
  enum intel_pch __cil_tmp73 ;
  unsigned int __cil_tmp74 ;
  void *__cil_tmp75 ;
  struct drm_i915_private *__cil_tmp76 ;
  enum intel_pch __cil_tmp77 ;
  unsigned int __cil_tmp78 ;
  void *__cil_tmp79 ;
  struct drm_i915_private *__cil_tmp80 ;
  struct intel_device_info  const  *__cil_tmp81 ;
  u8 __cil_tmp82 ;
  unsigned char __cil_tmp83 ;
  unsigned int __cil_tmp84 ;
  void *__cil_tmp85 ;
  struct drm_i915_private *__cil_tmp86 ;
  struct intel_device_info  const  *__cil_tmp87 ;
  u8 __cil_tmp88 ;
  unsigned char __cil_tmp89 ;
  unsigned int __cil_tmp90 ;
  void *__cil_tmp91 ;
  struct drm_i915_private *__cil_tmp92 ;
  struct intel_device_info  const  *__cil_tmp93 ;
  unsigned char *__cil_tmp94 ;
  unsigned char *__cil_tmp95 ;
  unsigned char __cil_tmp96 ;
  unsigned int __cil_tmp97 ;
  enum pipe __cil_tmp98 ;
  unsigned int __cil_tmp99 ;
  unsigned int __cil_tmp100 ;
  unsigned int __cil_tmp101 ;

  {
#line 132
  dev = encoder->dev;
#line 133
  crtc = encoder->crtc;
#line 134
  __mptr = (struct drm_crtc  const  *)crtc;
#line 134
  intel_crtc = (struct intel_crtc *)__mptr;
#line 135
  __cil_tmp13 = dev->dev_private;
#line 135
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 140
  __cil_tmp14 = intel_crtc->pipe;
#line 140
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 140
  __cil_tmp16 = __cil_tmp15 + 6151U;
#line 140
  __cil_tmp17 = __cil_tmp16 * 4U;
#line 140
  dpll_md_reg = (int )__cil_tmp17;
  {
#line 142
  __cil_tmp18 = dev->dev_private;
#line 142
  __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
#line 142
  __cil_tmp20 = __cil_tmp19->info;
#line 142
  __cil_tmp21 = __cil_tmp20->gen;
#line 142
  __cil_tmp22 = (unsigned char )__cil_tmp21;
#line 142
  __cil_tmp23 = (unsigned int )__cil_tmp22;
#line 142
  if (__cil_tmp23 == 5U) {
#line 143
    adpa_reg = 921856U;
  } else {
    {
#line 142
    __cil_tmp24 = dev->dev_private;
#line 142
    __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
#line 142
    __cil_tmp26 = __cil_tmp25->info;
#line 142
    __cil_tmp27 = __cil_tmp26->gen;
#line 142
    __cil_tmp28 = (unsigned char )__cil_tmp27;
#line 142
    __cil_tmp29 = (unsigned int )__cil_tmp28;
#line 142
    if (__cil_tmp29 == 6U) {
#line 143
      adpa_reg = 921856U;
    } else {
      {
#line 142
      __cil_tmp30 = dev->dev_private;
#line 142
      __cil_tmp31 = (struct drm_i915_private *)__cil_tmp30;
#line 142
      __cil_tmp32 = __cil_tmp31->info;
#line 142
      __cil_tmp33 = (unsigned char *)__cil_tmp32;
#line 142
      __cil_tmp34 = __cil_tmp33 + 2UL;
#line 142
      __cil_tmp35 = *__cil_tmp34;
#line 142
      __cil_tmp36 = (unsigned int )__cil_tmp35;
#line 142
      if (__cil_tmp36 != 0U) {
#line 143
        adpa_reg = 921856U;
      } else {
#line 145
        adpa_reg = 397568U;
      }
      }
    }
    }
  }
  }
  {
#line 151
  __cil_tmp37 = dev->dev_private;
#line 151
  __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
#line 151
  __cil_tmp39 = __cil_tmp38->info;
#line 151
  __cil_tmp40 = __cil_tmp39->gen;
#line 151
  __cil_tmp41 = (unsigned char )__cil_tmp40;
#line 151
  __cil_tmp42 = (unsigned int )__cil_tmp41;
#line 151
  if (__cil_tmp42 > 3U) {
    {
#line 151
    __cil_tmp43 = dev->dev_private;
#line 151
    __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
#line 151
    __cil_tmp45 = __cil_tmp44->info;
#line 151
    __cil_tmp46 = __cil_tmp45->gen;
#line 151
    __cil_tmp47 = (unsigned char )__cil_tmp46;
#line 151
    __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 151
    if (__cil_tmp48 != 5U) {
      {
#line 151
      __cil_tmp49 = dev->dev_private;
#line 151
      __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
#line 151
      __cil_tmp51 = __cil_tmp50->info;
#line 151
      __cil_tmp52 = __cil_tmp51->gen;
#line 151
      __cil_tmp53 = (unsigned char )__cil_tmp52;
#line 151
      __cil_tmp54 = (unsigned int )__cil_tmp53;
#line 151
      if (__cil_tmp54 != 6U) {
        {
#line 151
        __cil_tmp55 = dev->dev_private;
#line 151
        __cil_tmp56 = (struct drm_i915_private *)__cil_tmp55;
#line 151
        __cil_tmp57 = __cil_tmp56->info;
#line 151
        __cil_tmp58 = (unsigned char *)__cil_tmp57;
#line 151
        __cil_tmp59 = __cil_tmp58 + 2UL;
#line 151
        __cil_tmp60 = *__cil_tmp59;
#line 151
        __cil_tmp61 = (unsigned int )__cil_tmp60;
#line 151
        if (__cil_tmp61 == 0U) {
          {
#line 152
          __cil_tmp62 = (u32 )dpll_md_reg;
#line 152
          dpll_md = i915_read32___7(dev_priv, __cil_tmp62);
#line 153
          __cil_tmp63 = (u32 )dpll_md_reg;
#line 153
          __cil_tmp64 = dpll_md & 4294951167U;
#line 153
          i915_write32___5(dev_priv, __cil_tmp63, __cil_tmp64);
          }
        } else {

        }
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
#line 157
  adpa = 15990784U;
  {
#line 158
  __cil_tmp65 = adjusted_mode->flags;
#line 158
  __cil_tmp66 = (int )__cil_tmp65;
#line 158
  if (__cil_tmp66 & 1) {
#line 159
    adpa = adpa | 8U;
  } else {

  }
  }
  {
#line 160
  __cil_tmp67 = adjusted_mode->flags;
#line 160
  __cil_tmp68 = __cil_tmp67 & 4U;
#line 160
  if (__cil_tmp68 != 0U) {
#line 161
    adpa = adpa | 16U;
  } else {

  }
  }
  {
#line 163
  __cil_tmp69 = intel_crtc->pipe;
#line 163
  __cil_tmp70 = (unsigned int )__cil_tmp69;
#line 163
  if (__cil_tmp70 == 0U) {
    {
#line 164
    __cil_tmp71 = dev->dev_private;
#line 164
    __cil_tmp72 = (struct drm_i915_private *)__cil_tmp71;
#line 164
    __cil_tmp73 = __cil_tmp72->pch_type;
#line 164
    __cil_tmp74 = (unsigned int )__cil_tmp73;
#line 164
    if (__cil_tmp74 == 1U) {
#line 165
      adpa = adpa;
    } else {
#line 167
      adpa = adpa;
    }
    }
  } else {
    {
#line 169
    __cil_tmp75 = dev->dev_private;
#line 169
    __cil_tmp76 = (struct drm_i915_private *)__cil_tmp75;
#line 169
    __cil_tmp77 = __cil_tmp76->pch_type;
#line 169
    __cil_tmp78 = (unsigned int )__cil_tmp77;
#line 169
    if (__cil_tmp78 == 1U) {
#line 170
      adpa = adpa | 536870912U;
    } else {
#line 172
      adpa = adpa | 1073741824U;
    }
    }
  }
  }
  {
#line 175
  __cil_tmp79 = dev->dev_private;
#line 175
  __cil_tmp80 = (struct drm_i915_private *)__cil_tmp79;
#line 175
  __cil_tmp81 = __cil_tmp80->info;
#line 175
  __cil_tmp82 = __cil_tmp81->gen;
#line 175
  __cil_tmp83 = (unsigned char )__cil_tmp82;
#line 175
  __cil_tmp84 = (unsigned int )__cil_tmp83;
#line 175
  if (__cil_tmp84 != 5U) {
    {
#line 175
    __cil_tmp85 = dev->dev_private;
#line 175
    __cil_tmp86 = (struct drm_i915_private *)__cil_tmp85;
#line 175
    __cil_tmp87 = __cil_tmp86->info;
#line 175
    __cil_tmp88 = __cil_tmp87->gen;
#line 175
    __cil_tmp89 = (unsigned char )__cil_tmp88;
#line 175
    __cil_tmp90 = (unsigned int )__cil_tmp89;
#line 175
    if (__cil_tmp90 != 6U) {
      {
#line 175
      __cil_tmp91 = dev->dev_private;
#line 175
      __cil_tmp92 = (struct drm_i915_private *)__cil_tmp91;
#line 175
      __cil_tmp93 = __cil_tmp92->info;
#line 175
      __cil_tmp94 = (unsigned char *)__cil_tmp93;
#line 175
      __cil_tmp95 = __cil_tmp94 + 2UL;
#line 175
      __cil_tmp96 = *__cil_tmp95;
#line 175
      __cil_tmp97 = (unsigned int )__cil_tmp96;
#line 175
      if (__cil_tmp97 == 0U) {
        {
#line 176
        __cil_tmp98 = intel_crtc->pipe;
#line 176
        __cil_tmp99 = (unsigned int )__cil_tmp98;
#line 176
        __cil_tmp100 = __cil_tmp99 * 4096U;
#line 176
        __cil_tmp101 = __cil_tmp100 + 393248U;
#line 176
        i915_write32___5(dev_priv, __cil_tmp101, 0U);
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 178
  i915_write32___5(dev_priv, adpa_reg, adpa);
  }
#line 179
  return;
}
}
#line 181 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct intel_crt *crt ;
  struct intel_crt *tmp ;
  struct drm_i915_private *dev_priv ;
  u32 adpa ;
  bool ret ;
  bool turn_off_dac ;
  int tmp___0 ;
  u32 save_adpa ;
  unsigned long timeout__ ;
  unsigned long tmp___1 ;
  int ret__ ;
  struct thread_info *tmp___2 ;
  int pfo_ret__ ;
  int tmp___3 ;
  u32 tmp___4 ;
  void *__cil_tmp18 ;
  bool __cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  u8 __cil_tmp23 ;
  unsigned char __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  void *__cil_tmp26 ;
  struct drm_i915_private *__cil_tmp27 ;
  struct intel_device_info  const  *__cil_tmp28 ;
  u8 __cil_tmp29 ;
  unsigned char __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  void *__cil_tmp32 ;
  struct drm_i915_private *__cil_tmp33 ;
  struct intel_device_info  const  *__cil_tmp34 ;
  unsigned char *__cil_tmp35 ;
  unsigned char *__cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  unsigned long __cil_tmp41 ;
  long __cil_tmp42 ;
  long __cil_tmp43 ;
  long __cil_tmp44 ;
  int __cil_tmp45 ;
  int __cil_tmp46 ;
  atomic_t const   *__cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  void *__cil_tmp49 ;
  void const volatile   *__cil_tmp50 ;
  void const volatile   *__cil_tmp51 ;
  unsigned int __cil_tmp52 ;
  int __cil_tmp53 ;

  {
  {
#line 183
  dev = connector->dev;
#line 184
  tmp = intel_attached_crt(connector);
#line 184
  crt = tmp;
#line 185
  __cil_tmp18 = dev->dev_private;
#line 185
  dev_priv = (struct drm_i915_private *)__cil_tmp18;
  }
  {
#line 190
  __cil_tmp19 = crt->force_hotplug_required;
#line 190
  if ((int )__cil_tmp19) {
    {
#line 191
    __cil_tmp20 = dev->dev_private;
#line 191
    __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 191
    __cil_tmp22 = __cil_tmp21->info;
#line 191
    __cil_tmp23 = __cil_tmp22->gen;
#line 191
    __cil_tmp24 = (unsigned char )__cil_tmp23;
#line 191
    __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 191
    if (__cil_tmp25 == 5U) {
#line 191
      tmp___0 = 1;
    } else {
      {
#line 191
      __cil_tmp26 = dev->dev_private;
#line 191
      __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
#line 191
      __cil_tmp28 = __cil_tmp27->info;
#line 191
      __cil_tmp29 = __cil_tmp28->gen;
#line 191
      __cil_tmp30 = (unsigned char )__cil_tmp29;
#line 191
      __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 191
      if (__cil_tmp31 == 6U) {
#line 191
        tmp___0 = 1;
      } else {
        {
#line 191
        __cil_tmp32 = dev->dev_private;
#line 191
        __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
#line 191
        __cil_tmp34 = __cil_tmp33->info;
#line 191
        __cil_tmp35 = (unsigned char *)__cil_tmp34;
#line 191
        __cil_tmp36 = __cil_tmp35 + 2UL;
#line 191
        __cil_tmp37 = *__cil_tmp36;
#line 191
        __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 191
        if (__cil_tmp38 != 0U) {
#line 191
          tmp___0 = 1;
        } else {
#line 191
          tmp___0 = 0;
        }
        }
      }
      }
    }
    }
    {
#line 191
    turn_off_dac = (bool )tmp___0;
#line 194
    crt->force_hotplug_required = (bool )0;
#line 196
    adpa = i915_read32___7(dev_priv, 921856U);
#line 196
    save_adpa = adpa;
#line 197
    drm_ut_debug_printk(4U, "drm", "intel_ironlake_crt_detect_hotplug", "trigger hotplug detect cycle: adpa=0x%x\n",
                        adpa);
#line 199
    adpa = adpa | 65536U;
    }
#line 200
    if ((int )turn_off_dac) {
#line 201
      adpa = adpa & 2147483647U;
    } else {

    }
    {
#line 203
    i915_write32___5(dev_priv, 921856U, adpa);
#line 205
    __cil_tmp39 = (unsigned int const   )1000U;
#line 205
    __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 205
    tmp___1 = msecs_to_jiffies(__cil_tmp40);
#line 205
    __cil_tmp41 = (unsigned long )jiffies;
#line 205
    timeout__ = tmp___1 + __cil_tmp41;
#line 205
    ret__ = 0;
    }
#line 205
    goto ldv_37719;
    ldv_37718: ;
    {
#line 205
    __cil_tmp42 = (long )jiffies;
#line 205
    __cil_tmp43 = (long )timeout__;
#line 205
    __cil_tmp44 = __cil_tmp43 - __cil_tmp42;
#line 205
    if (__cil_tmp44 < 0L) {
#line 205
      ret__ = -110;
#line 205
      goto ldv_37709;
    } else {

    }
    }
    {
#line 205
    tmp___2 = current_thread_info();
    }
    {
#line 205
    __cil_tmp45 = tmp___2->preempt_count;
#line 205
    __cil_tmp46 = __cil_tmp45 & -268435457;
#line 205
    if (__cil_tmp46 == 0) {
#line 205
      if (1) {
#line 205
        goto case_4;
      } else {
#line 205
        goto switch_default;
#line 205
        if (0) {
#line 205
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 205
          goto ldv_37712;
#line 205
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 205
          goto ldv_37712;
          case_4: 
#line 205
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 205
          goto ldv_37712;
#line 205
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 205
          goto ldv_37712;
          switch_default: 
          {
#line 205
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_37712: 
      {
#line 205
      __cil_tmp47 = (atomic_t const   *)(& kgdb_active);
#line 205
      tmp___3 = atomic_read(__cil_tmp47);
      }
#line 205
      if (pfo_ret__ != tmp___3) {
        {
#line 205
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_37719: 
    {
#line 205
    tmp___4 = i915_read32___7(dev_priv, 921856U);
    }
    {
#line 205
    __cil_tmp48 = tmp___4 & 65536U;
#line 205
    if (__cil_tmp48 != 0U) {
#line 206
      goto ldv_37718;
    } else {
#line 208
      goto ldv_37709;
    }
    }
    ldv_37709: ;
#line 205
    if (ret__ != 0) {
      {
#line 207
      drm_ut_debug_printk(4U, "drm", "intel_ironlake_crt_detect_hotplug", "timed out waiting for FORCE_TRIGGER");
      }
    } else {

    }
#line 209
    if ((int )turn_off_dac) {
      {
#line 210
      i915_write32___5(dev_priv, 921856U, save_adpa);
#line 211
      __cil_tmp49 = dev_priv->regs;
#line 211
      __cil_tmp50 = (void const volatile   *)__cil_tmp49;
#line 211
      __cil_tmp51 = __cil_tmp50 + 921856U;
#line 211
      readl(__cil_tmp51);
      }
    } else {

    }
  } else {

  }
  }
  {
#line 216
  adpa = i915_read32___7(dev_priv, 921856U);
  }
  {
#line 217
  __cil_tmp52 = adpa & 50331648U;
#line 217
  if (__cil_tmp52 != 0U) {
#line 218
    ret = (bool )1;
  } else {
#line 220
    ret = (bool )0;
  }
  }
  {
#line 221
  __cil_tmp53 = (int )ret;
#line 221
  drm_ut_debug_printk(4U, "drm", "intel_ironlake_crt_detect_hotplug", "ironlake hotplug adpa=0x%x, result %d\n",
                      adpa, __cil_tmp53);
  }
#line 223
  return (ret);
}
}
#line 234 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static bool intel_crt_detect_hotplug(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 hotplug_en ;
  u32 orig ;
  u32 stat ;
  bool ret ;
  int i ;
  int tries ;
  bool tmp ;
  unsigned long timeout__ ;
  unsigned long tmp___0 ;
  int ret__ ;
  struct thread_info *tmp___1 ;
  int pfo_ret__ ;
  int tmp___2 ;
  u32 tmp___3 ;
  void *__cil_tmp18 ;
  void *__cil_tmp19 ;
  struct drm_i915_private *__cil_tmp20 ;
  struct intel_device_info  const  *__cil_tmp21 ;
  u8 __cil_tmp22 ;
  unsigned char __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  void *__cil_tmp25 ;
  struct drm_i915_private *__cil_tmp26 ;
  struct intel_device_info  const  *__cil_tmp27 ;
  u8 __cil_tmp28 ;
  unsigned char __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  void *__cil_tmp31 ;
  struct drm_i915_private *__cil_tmp32 ;
  struct intel_device_info  const  *__cil_tmp33 ;
  unsigned char *__cil_tmp34 ;
  unsigned char *__cil_tmp35 ;
  unsigned char __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  void *__cil_tmp38 ;
  struct drm_i915_private *__cil_tmp39 ;
  struct intel_device_info  const  *__cil_tmp40 ;
  unsigned char *__cil_tmp41 ;
  unsigned char *__cil_tmp42 ;
  unsigned char __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  int __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  long __cil_tmp49 ;
  long __cil_tmp50 ;
  long __cil_tmp51 ;
  int __cil_tmp52 ;
  int __cil_tmp53 ;
  atomic_t const   *__cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  unsigned int __cil_tmp56 ;

  {
#line 236
  dev = connector->dev;
#line 237
  __cil_tmp18 = dev->dev_private;
#line 237
  dev_priv = (struct drm_i915_private *)__cil_tmp18;
#line 239
  ret = (bool )0;
#line 240
  tries = 0;
  {
#line 242
  __cil_tmp19 = dev->dev_private;
#line 242
  __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
#line 242
  __cil_tmp21 = __cil_tmp20->info;
#line 242
  __cil_tmp22 = __cil_tmp21->gen;
#line 242
  __cil_tmp23 = (unsigned char )__cil_tmp22;
#line 242
  __cil_tmp24 = (unsigned int )__cil_tmp23;
#line 242
  if (__cil_tmp24 == 5U) {
    {
#line 243
    tmp = intel_ironlake_crt_detect_hotplug(connector);
    }
#line 243
    return (tmp);
  } else {
    {
#line 242
    __cil_tmp25 = dev->dev_private;
#line 242
    __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
#line 242
    __cil_tmp27 = __cil_tmp26->info;
#line 242
    __cil_tmp28 = __cil_tmp27->gen;
#line 242
    __cil_tmp29 = (unsigned char )__cil_tmp28;
#line 242
    __cil_tmp30 = (unsigned int )__cil_tmp29;
#line 242
    if (__cil_tmp30 == 6U) {
      {
#line 243
      tmp = intel_ironlake_crt_detect_hotplug(connector);
      }
#line 243
      return (tmp);
    } else {
      {
#line 242
      __cil_tmp31 = dev->dev_private;
#line 242
      __cil_tmp32 = (struct drm_i915_private *)__cil_tmp31;
#line 242
      __cil_tmp33 = __cil_tmp32->info;
#line 242
      __cil_tmp34 = (unsigned char *)__cil_tmp33;
#line 242
      __cil_tmp35 = __cil_tmp34 + 2UL;
#line 242
      __cil_tmp36 = *__cil_tmp35;
#line 242
      __cil_tmp37 = (unsigned int )__cil_tmp36;
#line 242
      if (__cil_tmp37 != 0U) {
        {
#line 243
        tmp = intel_ironlake_crt_detect_hotplug(connector);
        }
#line 243
        return (tmp);
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 250
  __cil_tmp38 = dev->dev_private;
#line 250
  __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
#line 250
  __cil_tmp40 = __cil_tmp39->info;
#line 250
  __cil_tmp41 = (unsigned char *)__cil_tmp40;
#line 250
  __cil_tmp42 = __cil_tmp41 + 1UL;
#line 250
  __cil_tmp43 = *__cil_tmp42;
#line 250
  __cil_tmp44 = (unsigned int )__cil_tmp43;
#line 250
  if (__cil_tmp44 != 0U) {
    {
#line 250
    __cil_tmp45 = dev->pci_device;
#line 250
    if (__cil_tmp45 != 10818) {
#line 251
      tries = 2;
    } else {
#line 253
      tries = 1;
    }
    }
  } else {
#line 253
    tries = 1;
  }
  }
  {
#line 254
  orig = i915_read32___7(dev_priv, 397584U);
#line 254
  hotplug_en = orig;
#line 255
  hotplug_en = hotplug_en | 8U;
#line 257
  i = 0;
  }
#line 257
  goto ldv_37754;
  ldv_37753: 
  {
#line 259
  i915_write32___5(dev_priv, 397584U, hotplug_en);
#line 261
  __cil_tmp46 = (unsigned int const   )1000U;
#line 261
  __cil_tmp47 = (unsigned int )__cil_tmp46;
#line 261
  tmp___0 = msecs_to_jiffies(__cil_tmp47);
#line 261
  __cil_tmp48 = (unsigned long )jiffies;
#line 261
  timeout__ = tmp___0 + __cil_tmp48;
#line 261
  ret__ = 0;
  }
#line 261
  goto ldv_37750;
  ldv_37749: ;
  {
#line 261
  __cil_tmp49 = (long )jiffies;
#line 261
  __cil_tmp50 = (long )timeout__;
#line 261
  __cil_tmp51 = __cil_tmp50 - __cil_tmp49;
#line 261
  if (__cil_tmp51 < 0L) {
#line 261
    ret__ = -110;
#line 261
    goto ldv_37740;
  } else {

  }
  }
  {
#line 261
  tmp___1 = current_thread_info();
  }
  {
#line 261
  __cil_tmp52 = tmp___1->preempt_count;
#line 261
  __cil_tmp53 = __cil_tmp52 & -268435457;
#line 261
  if (__cil_tmp53 == 0) {
#line 261
    if (1) {
#line 261
      goto case_4;
    } else {
#line 261
      goto switch_default;
#line 261
      if (0) {
#line 261
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 261
        goto ldv_37743;
#line 261
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 261
        goto ldv_37743;
        case_4: 
#line 261
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 261
        goto ldv_37743;
#line 261
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 261
        goto ldv_37743;
        switch_default: 
        {
#line 261
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_37743: 
    {
#line 261
    __cil_tmp54 = (atomic_t const   *)(& kgdb_active);
#line 261
    tmp___2 = atomic_read(__cil_tmp54);
    }
#line 261
    if (pfo_ret__ != tmp___2) {
      {
#line 261
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_37750: 
  {
#line 261
  tmp___3 = i915_read32___7(dev_priv, 397584U);
  }
  {
#line 261
  __cil_tmp55 = tmp___3 & 8U;
#line 261
  if (__cil_tmp55 != 0U) {
#line 262
    goto ldv_37749;
  } else {
#line 264
    goto ldv_37740;
  }
  }
  ldv_37740: ;
#line 261
  if (ret__ != 0) {
    {
#line 264
    drm_ut_debug_printk(4U, "drm", "intel_crt_detect_hotplug", "timed out waiting for FORCE_DETECT to go off");
    }
  } else {

  }
#line 257
  i = i + 1;
  ldv_37754: ;
#line 257
  if (i < tries) {
#line 258
    goto ldv_37753;
  } else {
#line 260
    goto ldv_37755;
  }
  ldv_37755: 
  {
#line 267
  stat = i915_read32___7(dev_priv, 397588U);
  }
  {
#line 268
  __cil_tmp56 = stat & 768U;
#line 268
  if (__cil_tmp56 != 0U) {
#line 269
    ret = (bool )1;
  } else {

  }
  }
  {
#line 272
  i915_write32___5(dev_priv, 397588U, 2048U);
#line 275
  i915_write32___5(dev_priv, 397584U, orig);
  }
#line 277
  return (ret);
}
}
#line 280 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static bool intel_crt_detect_ddc(struct drm_connector *connector ) 
{ struct intel_crt *crt ;
  struct intel_crt *tmp ;
  struct drm_i915_private *dev_priv ;
  struct edid *edid ;
  bool is_digital ;
  bool tmp___0 ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  struct intel_encoder *__cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct intel_gmbus *__cil_tmp15 ;
  struct intel_gmbus *__cil_tmp16 ;
  struct i2c_adapter *__cil_tmp17 ;
  struct edid *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  u8 __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  void const   *__cil_tmp25 ;

  {
  {
#line 282
  tmp = intel_attached_crt(connector);
#line 282
  crt = tmp;
#line 283
  __cil_tmp8 = crt->base.base.dev;
#line 283
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 283
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
  }
  {
#line 286
  __cil_tmp10 = crt->base.type;
#line 286
  if (__cil_tmp10 != 1) {
#line 287
    return ((bool )0);
  } else {

  }
  }
  {
#line 289
  __cil_tmp11 = & crt->base;
#line 289
  __cil_tmp12 = dev_priv->crt_ddc_pin;
#line 289
  tmp___0 = intel_ddc_probe(__cil_tmp11, __cil_tmp12);
  }
#line 289
  if ((int )tmp___0) {
    {
#line 291
    is_digital = (bool )0;
#line 293
    __cil_tmp13 = dev_priv->crt_ddc_pin;
#line 293
    __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 293
    __cil_tmp15 = dev_priv->gmbus;
#line 293
    __cil_tmp16 = __cil_tmp15 + __cil_tmp14;
#line 293
    __cil_tmp17 = & __cil_tmp16->adapter;
#line 293
    edid = drm_get_edid(connector, __cil_tmp17);
    }
    {
#line 302
    __cil_tmp18 = (struct edid *)0;
#line 302
    __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 302
    __cil_tmp20 = (unsigned long )edid;
#line 302
    if (__cil_tmp20 != __cil_tmp19) {
      {
#line 303
      __cil_tmp21 = edid->input;
#line 303
      __cil_tmp22 = (int )__cil_tmp21;
#line 303
      __cil_tmp23 = __cil_tmp22 & 128;
#line 303
      __cil_tmp24 = __cil_tmp23 != 0;
#line 303
      is_digital = (bool )__cil_tmp24;
#line 304
      connector->display_info.raw_edid = (char *)0;
#line 305
      __cil_tmp25 = (void const   *)edid;
#line 305
      kfree(__cil_tmp25);
      }
    } else {

    }
    }
#line 308
    if (! is_digital) {
      {
#line 309
      drm_ut_debug_printk(4U, "drm", "intel_crt_detect_ddc", "CRT detected via DDC:0x50 [EDID]\n");
      }
#line 310
      return ((bool )1);
    } else {
      {
#line 312
      drm_ut_debug_printk(4U, "drm", "intel_crt_detect_ddc", "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
      }
    }
  } else {

  }
#line 316
  return ((bool )0);
}
}
#line 320 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static enum drm_connector_status intel_crt_load_detect(struct intel_crt *crt ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  uint32_t pipe ;
  struct drm_crtc  const  *__mptr ;
  uint32_t save_bclrpat ;
  uint32_t save_vtotal ;
  uint32_t vtotal ;
  uint32_t vactive ;
  uint32_t vsample ;
  uint32_t vblank ;
  uint32_t vblank_start ;
  uint32_t vblank_end ;
  uint32_t dsl ;
  uint32_t bclrpat_reg ;
  uint32_t vtotal_reg ;
  uint32_t vblank_reg ;
  uint32_t vsync_reg ;
  uint32_t pipeconf_reg ;
  uint32_t pipe_dsl_reg ;
  uint8_t st00 ;
  enum drm_connector_status status ;
  uint32_t pipeconf ;
  u32 tmp ;
  bool restore_vblank ;
  int count ;
  int detect ;
  uint32_t vsync ;
  u32 tmp___0 ;
  uint32_t vsync_start ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  void *__cil_tmp33 ;
  struct drm_crtc *__cil_tmp34 ;
  struct intel_crtc *__cil_tmp35 ;
  enum pipe __cil_tmp36 ;
  uint32_t __cil_tmp37 ;
  uint32_t __cil_tmp38 ;
  uint32_t __cil_tmp39 ;
  uint32_t __cil_tmp40 ;
  uint32_t __cil_tmp41 ;
  uint32_t __cil_tmp42 ;
  uint32_t __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  uint32_t __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  void *__cil_tmp49 ;
  struct drm_i915_private *__cil_tmp50 ;
  struct intel_device_info  const  *__cil_tmp51 ;
  u8 __cil_tmp52 ;
  unsigned char __cil_tmp53 ;
  unsigned int __cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  unsigned long __cil_tmp56 ;
  void *__cil_tmp57 ;
  void const volatile   *__cil_tmp58 ;
  void const volatile   *__cil_tmp59 ;
  int __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;
  unsigned int __cil_tmp63 ;
  uint32_t __cil_tmp64 ;
  uint32_t __cil_tmp65 ;
  uint32_t __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  uint32_t __cil_tmp68 ;
  uint32_t __cil_tmp69 ;
  uint32_t __cil_tmp70 ;
  uint32_t __cil_tmp71 ;
  int __cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  int __cil_tmp75 ;

  {
  {
#line 322
  dev = crt->base.base.dev;
#line 323
  __cil_tmp33 = dev->dev_private;
#line 323
  dev_priv = (struct drm_i915_private *)__cil_tmp33;
#line 324
  __cil_tmp34 = crt->base.base.crtc;
#line 324
  __mptr = (struct drm_crtc  const  *)__cil_tmp34;
#line 324
  __cil_tmp35 = (struct intel_crtc *)__mptr;
#line 324
  __cil_tmp36 = __cil_tmp35->pipe;
#line 324
  pipe = (uint32_t )__cil_tmp36;
#line 340
  drm_ut_debug_printk(4U, "drm", "intel_crt_load_detect", "starting load-detect on CRT\n");
#line 342
  __cil_tmp37 = pipe * 4096U;
#line 342
  bclrpat_reg = __cil_tmp37 + 393248U;
#line 343
  __cil_tmp38 = pipe * 4096U;
#line 343
  vtotal_reg = __cil_tmp38 + 393228U;
#line 344
  __cil_tmp39 = pipe * 4096U;
#line 344
  vblank_reg = __cil_tmp39 + 393232U;
#line 345
  __cil_tmp40 = pipe * 4096U;
#line 345
  vsync_reg = __cil_tmp40 + 393236U;
#line 346
  __cil_tmp41 = pipe * 4096U;
#line 346
  pipeconf_reg = __cil_tmp41 + 458760U;
#line 347
  __cil_tmp42 = pipe + 112U;
#line 347
  pipe_dsl_reg = __cil_tmp42 * 4096U;
#line 349
  save_bclrpat = i915_read32___7(dev_priv, bclrpat_reg);
#line 350
  save_vtotal = i915_read32___7(dev_priv, vtotal_reg);
#line 351
  vblank = i915_read32___7(dev_priv, vblank_reg);
#line 353
  __cil_tmp43 = save_vtotal >> 16;
#line 353
  __cil_tmp44 = __cil_tmp43 & 4095U;
#line 353
  vtotal = __cil_tmp44 + 1U;
#line 354
  __cil_tmp45 = save_vtotal & 2047U;
#line 354
  vactive = __cil_tmp45 + 1U;
#line 356
  __cil_tmp46 = vblank & 4095U;
#line 356
  vblank_start = __cil_tmp46 + 1U;
#line 357
  __cil_tmp47 = vblank >> 16;
#line 357
  __cil_tmp48 = __cil_tmp47 & 4095U;
#line 357
  vblank_end = __cil_tmp48 + 1U;
#line 360
  i915_write32___5(dev_priv, bclrpat_reg, 5242960U);
  }
  {
#line 362
  __cil_tmp49 = dev->dev_private;
#line 362
  __cil_tmp50 = (struct drm_i915_private *)__cil_tmp49;
#line 362
  __cil_tmp51 = __cil_tmp50->info;
#line 362
  __cil_tmp52 = __cil_tmp51->gen;
#line 362
  __cil_tmp53 = (unsigned char )__cil_tmp52;
#line 362
  __cil_tmp54 = (unsigned int )__cil_tmp53;
#line 362
  if (__cil_tmp54 != 2U) {
    {
#line 363
    tmp = i915_read32___7(dev_priv, pipeconf_reg);
#line 363
    pipeconf = tmp;
#line 364
    __cil_tmp55 = pipeconf | 33554432U;
#line 364
    i915_write32___5(dev_priv, pipeconf_reg, __cil_tmp55);
#line 365
    __cil_tmp56 = (unsigned long )pipeconf_reg;
#line 365
    __cil_tmp57 = dev_priv->regs;
#line 365
    __cil_tmp58 = (void const volatile   *)__cil_tmp57;
#line 365
    __cil_tmp59 = __cil_tmp58 + __cil_tmp56;
#line 365
    readl(__cil_tmp59);
#line 368
    __cil_tmp60 = (int )pipe;
#line 368
    intel_wait_for_vblank(dev, __cil_tmp60);
#line 369
    st00 = i915_read8___1(dev_priv, 962U);
    }
    {
#line 370
    __cil_tmp61 = (int )st00;
#line 370
    __cil_tmp62 = __cil_tmp61 & 16;
#line 370
    if (__cil_tmp62 != 0) {
#line 370
      status = (enum drm_connector_status )1;
    } else {
#line 370
      status = (enum drm_connector_status )2;
    }
    }
    {
#line 374
    i915_write32___5(dev_priv, pipeconf_reg, pipeconf);
    }
  } else {
#line 376
    restore_vblank = (bool )0;
#line 383
    if (vblank_start <= vactive) {
#line 383
      if (vblank_end >= vtotal) {
        {
#line 384
        tmp___0 = i915_read32___7(dev_priv, vsync_reg);
#line 384
        vsync = tmp___0;
#line 385
        __cil_tmp63 = vsync & 65535U;
#line 385
        vsync_start = __cil_tmp63 + 1U;
#line 387
        vblank_start = vsync_start;
#line 388
        __cil_tmp64 = vblank_end - 1U;
#line 388
        __cil_tmp65 = __cil_tmp64 << 16;
#line 388
        __cil_tmp66 = vblank_start - 1U;
#line 388
        __cil_tmp67 = __cil_tmp66 | __cil_tmp65;
#line 388
        i915_write32___5(dev_priv, vblank_reg, __cil_tmp67);
#line 391
        restore_vblank = (bool )1;
        }
      } else {

      }
    } else {

    }
    {
#line 394
    __cil_tmp68 = vtotal - vblank_end;
#line 394
    __cil_tmp69 = vblank_start - vactive;
#line 394
    if (__cil_tmp69 >= __cil_tmp68) {
#line 395
      __cil_tmp70 = vblank_start + vactive;
#line 395
      vsample = __cil_tmp70 >> 1;
    } else {
#line 397
      __cil_tmp71 = vtotal + vblank_end;
#line 397
      vsample = __cil_tmp71 >> 1;
    }
    }
#line 402
    goto ldv_37797;
    ldv_37796: ;
    ldv_37797: 
    {
#line 402
    tmp___1 = i915_read32___7(dev_priv, pipe_dsl_reg);
    }
#line 402
    if (tmp___1 >= vactive) {
#line 403
      goto ldv_37796;
    } else {
#line 405
      goto ldv_37798;
    }
    ldv_37798: ;
#line 404
    goto ldv_37800;
    ldv_37799: ;
    ldv_37800: 
    {
#line 404
    dsl = i915_read32___7(dev_priv, pipe_dsl_reg);
    }
#line 404
    if (dsl <= vsample) {
#line 405
      goto ldv_37799;
    } else {
#line 407
      goto ldv_37801;
    }
    ldv_37801: 
#line 409
    detect = 0;
#line 410
    count = 0;
    ldv_37802: 
    {
#line 412
    count = count + 1;
#line 414
    st00 = i915_read8___1(dev_priv, 962U);
    }
    {
#line 415
    __cil_tmp72 = (int )st00;
#line 415
    __cil_tmp73 = __cil_tmp72 & 16;
#line 415
    if (__cil_tmp73 != 0) {
#line 416
      detect = detect + 1;
    } else {

    }
    }
    {
#line 417
    tmp___2 = i915_read32___7(dev_priv, pipe_dsl_reg);
    }
#line 417
    if (tmp___2 == dsl) {
#line 418
      goto ldv_37802;
    } else {
#line 420
      goto ldv_37803;
    }
    ldv_37803: ;
#line 420
    if ((int )restore_vblank) {
      {
#line 421
      i915_write32___5(dev_priv, vblank_reg, vblank);
      }
    } else {

    }
    {
#line 428
    __cil_tmp74 = count * 3;
#line 428
    __cil_tmp75 = detect * 4;
#line 428
    if (__cil_tmp75 > __cil_tmp74) {
#line 428
      status = (enum drm_connector_status )1;
    } else {
#line 428
      status = (enum drm_connector_status )2;
    }
    }
  }
  }
  {
#line 434
  i915_write32___5(dev_priv, bclrpat_reg, save_bclrpat);
  }
#line 436
  return (status);
}
}
#line 440 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static enum drm_connector_status intel_crt_detect(struct drm_connector *connector ,
                                                  bool force ) 
{ struct drm_device *dev ;
  struct intel_crt *crt ;
  struct intel_crt *tmp ;
  struct drm_crtc *crtc ;
  enum drm_connector_status status ;
  bool tmp___0 ;
  bool tmp___1 ;
  struct intel_load_detect_pipe tmp___2 ;
  bool tmp___3 ;
  bool tmp___4 ;
  void *__cil_tmp13 ;
  struct drm_i915_private *__cil_tmp14 ;
  struct intel_device_info  const  *__cil_tmp15 ;
  unsigned char *__cil_tmp16 ;
  unsigned char *__cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  struct drm_crtc *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  bool __cil_tmp23 ;
  struct intel_encoder *__cil_tmp24 ;
  struct drm_display_mode *__cil_tmp25 ;
  struct intel_encoder *__cil_tmp26 ;

  {
  {
#line 442
  dev = connector->dev;
#line 443
  tmp = intel_attached_crt(connector);
#line 443
  crt = tmp;
  }
  {
#line 447
  __cil_tmp13 = dev->dev_private;
#line 447
  __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
#line 447
  __cil_tmp15 = __cil_tmp14->info;
#line 447
  __cil_tmp16 = (unsigned char *)__cil_tmp15;
#line 447
  __cil_tmp17 = __cil_tmp16 + 2UL;
#line 447
  __cil_tmp18 = *__cil_tmp17;
#line 447
  __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 447
  if (__cil_tmp19 != 0U) {
    {
#line 448
    tmp___0 = intel_crt_detect_hotplug(connector);
    }
#line 448
    if ((int )tmp___0) {
      {
#line 449
      drm_ut_debug_printk(4U, "drm", "intel_crt_detect", "CRT detected via hotplug\n");
      }
#line 450
      return ((enum drm_connector_status )1);
    } else {
      {
#line 452
      drm_ut_debug_printk(4U, "drm", "intel_crt_detect", "CRT not detected via hotplug\n");
      }
#line 453
      return ((enum drm_connector_status )2);
    }
  } else {

  }
  }
  {
#line 457
  tmp___1 = intel_crt_detect_ddc(connector);
  }
#line 457
  if ((int )tmp___1) {
#line 458
    return ((enum drm_connector_status )1);
  } else {

  }
#line 460
  if (! force) {
#line 461
    return (connector->status);
  } else {

  }
#line 464
  crtc = crt->base.base.crtc;
  {
#line 465
  __cil_tmp20 = (struct drm_crtc *)0;
#line 465
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 465
  __cil_tmp22 = (unsigned long )crtc;
#line 465
  if (__cil_tmp22 != __cil_tmp21) {
    {
#line 465
    __cil_tmp23 = crtc->enabled;
#line 465
    if ((int )__cil_tmp23) {
      {
#line 466
      status = intel_crt_load_detect(crt);
      }
    } else {
#line 465
      goto _L;
    }
    }
  } else {
    _L: 
    {
#line 470
    __cil_tmp24 = & crt->base;
#line 470
    __cil_tmp25 = (struct drm_display_mode *)0;
#line 470
    tmp___4 = intel_get_load_detect_pipe(__cil_tmp24, connector, __cil_tmp25, & tmp___2);
    }
#line 470
    if ((int )tmp___4) {
      {
#line 472
      tmp___3 = intel_crt_detect_ddc(connector);
      }
#line 472
      if ((int )tmp___3) {
#line 473
        status = (enum drm_connector_status )1;
      } else {
        {
#line 475
        status = intel_crt_load_detect(crt);
        }
      }
      {
#line 476
      __cil_tmp26 = & crt->base;
#line 476
      intel_release_load_detect_pipe(__cil_tmp26, connector, & tmp___2);
      }
    } else {
#line 479
      status = (enum drm_connector_status )3;
    }
  }
  }
#line 482
  return (status);
}
}
#line 485 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static void intel_crt_destroy(struct drm_connector *connector ) 
{ void const   *__cil_tmp2 ;

  {
  {
#line 487
  drm_sysfs_connector_remove(connector);
#line 488
  drm_connector_cleanup(connector);
#line 489
  __cil_tmp2 = (void const   *)connector;
#line 489
  kfree(__cil_tmp2);
  }
#line 490
  return;
}
}
#line 492 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static int intel_crt_get_modes(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  int ret ;
  int tmp ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct intel_gmbus *__cil_tmp9 ;
  struct intel_gmbus *__cil_tmp10 ;
  struct i2c_adapter *__cil_tmp11 ;
  void *__cil_tmp12 ;
  struct drm_i915_private *__cil_tmp13 ;
  struct intel_device_info  const  *__cil_tmp14 ;
  unsigned char *__cil_tmp15 ;
  unsigned char *__cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  struct intel_gmbus *__cil_tmp19 ;
  struct intel_gmbus *__cil_tmp20 ;
  struct i2c_adapter *__cil_tmp21 ;

  {
  {
#line 494
  dev = connector->dev;
#line 495
  __cil_tmp6 = dev->dev_private;
#line 495
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 498
  __cil_tmp7 = dev_priv->crt_ddc_pin;
#line 498
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 498
  __cil_tmp9 = dev_priv->gmbus;
#line 498
  __cil_tmp10 = __cil_tmp9 + __cil_tmp8;
#line 498
  __cil_tmp11 = & __cil_tmp10->adapter;
#line 498
  ret = intel_ddc_get_modes(connector, __cil_tmp11);
  }
#line 500
  if (ret != 0) {
#line 501
    return (ret);
  } else {
    {
#line 500
    __cil_tmp12 = dev->dev_private;
#line 500
    __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
#line 500
    __cil_tmp14 = __cil_tmp13->info;
#line 500
    __cil_tmp15 = (unsigned char *)__cil_tmp14;
#line 500
    __cil_tmp16 = __cil_tmp15 + 1UL;
#line 500
    __cil_tmp17 = *__cil_tmp16;
#line 500
    __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 500
    if (__cil_tmp18 == 0U) {
#line 501
      return (ret);
    } else {

    }
    }
  }
  {
#line 504
  __cil_tmp19 = dev_priv->gmbus;
#line 504
  __cil_tmp20 = __cil_tmp19 + 5UL;
#line 504
  __cil_tmp21 = & __cil_tmp20->adapter;
#line 504
  tmp = intel_ddc_get_modes(connector, __cil_tmp21);
  }
#line 504
  return (tmp);
}
}
#line 508 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static int intel_crt_set_property(struct drm_connector *connector , struct drm_property *property ,
                                  uint64_t value ) 
{ 

  {
#line 512
  return (0);
}
}
#line 515 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static void intel_crt_reset(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct intel_crt *crt ;
  struct intel_crt *tmp ;
  void *__cil_tmp5 ;
  struct drm_i915_private *__cil_tmp6 ;
  struct intel_device_info  const  *__cil_tmp7 ;
  u8 __cil_tmp8 ;
  unsigned char __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  void *__cil_tmp11 ;
  struct drm_i915_private *__cil_tmp12 ;
  struct intel_device_info  const  *__cil_tmp13 ;
  u8 __cil_tmp14 ;
  unsigned char __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  void *__cil_tmp17 ;
  struct drm_i915_private *__cil_tmp18 ;
  struct intel_device_info  const  *__cil_tmp19 ;
  unsigned char *__cil_tmp20 ;
  unsigned char *__cil_tmp21 ;
  unsigned char __cil_tmp22 ;
  unsigned int __cil_tmp23 ;

  {
  {
#line 517
  dev = connector->dev;
#line 518
  tmp = intel_attached_crt(connector);
#line 518
  crt = tmp;
  }
  {
#line 520
  __cil_tmp5 = dev->dev_private;
#line 520
  __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
#line 520
  __cil_tmp7 = __cil_tmp6->info;
#line 520
  __cil_tmp8 = __cil_tmp7->gen;
#line 520
  __cil_tmp9 = (unsigned char )__cil_tmp8;
#line 520
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 520
  if (__cil_tmp10 == 5U) {
#line 521
    crt->force_hotplug_required = (bool )1;
  } else {
    {
#line 520
    __cil_tmp11 = dev->dev_private;
#line 520
    __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
#line 520
    __cil_tmp13 = __cil_tmp12->info;
#line 520
    __cil_tmp14 = __cil_tmp13->gen;
#line 520
    __cil_tmp15 = (unsigned char )__cil_tmp14;
#line 520
    __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 520
    if (__cil_tmp16 == 6U) {
#line 521
      crt->force_hotplug_required = (bool )1;
    } else {
      {
#line 520
      __cil_tmp17 = dev->dev_private;
#line 520
      __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
#line 520
      __cil_tmp19 = __cil_tmp18->info;
#line 520
      __cil_tmp20 = (unsigned char *)__cil_tmp19;
#line 520
      __cil_tmp21 = __cil_tmp20 + 2UL;
#line 520
      __cil_tmp22 = *__cil_tmp21;
#line 520
      __cil_tmp23 = (unsigned int )__cil_tmp22;
#line 520
      if (__cil_tmp23 != 0U) {
#line 521
        crt->force_hotplug_required = (bool )1;
      } else {

      }
      }
    }
    }
  }
  }
#line 522
  return;
}
}
#line 528 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static struct drm_encoder_helper_funcs  const  intel_crt_helper_funcs  = 
#line 528
     {& intel_crt_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_crt_mode_fixup, & intel_encoder_prepare, & intel_encoder_commit, & intel_crt_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 536 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static struct drm_connector_funcs  const  intel_crt_connector_funcs  = 
#line 536
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    & intel_crt_reset, & intel_crt_detect, & drm_helper_probe_single_connector_modes,
    & intel_crt_set_property, & intel_crt_destroy, (void (*)(struct drm_connector * ))0};
#line 545 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static struct drm_connector_helper_funcs  const  intel_crt_connector_helper_funcs  =    {& intel_crt_get_modes,
    & intel_crt_mode_valid, & intel_best_encoder};
#line 551 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
static struct drm_encoder_funcs  const  intel_crt_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_encoder_destroy};
#line 555 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_crt.c.p"
void intel_crt_init(struct drm_device *dev ) 
{ struct drm_connector *connector ;
  struct intel_crt *crt ;
  struct intel_connector *intel_connector ;
  struct drm_i915_private *dev_priv ;
  void *tmp ;
  void *tmp___0 ;
  u32 adpa ;
  void *__cil_tmp9 ;
  struct intel_crt *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct intel_connector *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  void const   *__cil_tmp16 ;
  struct drm_connector *__cil_tmp17 ;
  struct drm_encoder *__cil_tmp18 ;
  struct intel_encoder *__cil_tmp19 ;
  struct drm_encoder *__cil_tmp20 ;
  void *__cil_tmp21 ;
  struct drm_i915_private *__cil_tmp22 ;
  struct intel_device_info  const  *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char *__cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  void *__cil_tmp28 ;
  struct drm_i915_private *__cil_tmp29 ;
  struct intel_device_info  const  *__cil_tmp30 ;
  u8 __cil_tmp31 ;
  unsigned char __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  void *__cil_tmp34 ;
  struct drm_i915_private *__cil_tmp35 ;
  struct intel_device_info  const  *__cil_tmp36 ;
  u8 __cil_tmp37 ;
  unsigned char __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  void *__cil_tmp40 ;
  struct drm_i915_private *__cil_tmp41 ;
  struct intel_device_info  const  *__cil_tmp42 ;
  unsigned char *__cil_tmp43 ;
  unsigned char *__cil_tmp44 ;
  unsigned char __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  void *__cil_tmp47 ;
  void const volatile   *__cil_tmp48 ;
  void const volatile   *__cil_tmp49 ;
  u32 __cil_tmp50 ;

  {
  {
#line 560
  __cil_tmp9 = dev->dev_private;
#line 560
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 562
  tmp = kzalloc(104UL, 208U);
#line 562
  crt = (struct intel_crt *)tmp;
  }
  {
#line 563
  __cil_tmp10 = (struct intel_crt *)0;
#line 563
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 563
  __cil_tmp12 = (unsigned long )crt;
#line 563
  if (__cil_tmp12 == __cil_tmp11) {
#line 564
    return;
  } else {

  }
  }
  {
#line 566
  tmp___0 = kzalloc(1576UL, 208U);
#line 566
  intel_connector = (struct intel_connector *)tmp___0;
  }
  {
#line 567
  __cil_tmp13 = (struct intel_connector *)0;
#line 567
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 567
  __cil_tmp15 = (unsigned long )intel_connector;
#line 567
  if (__cil_tmp15 == __cil_tmp14) {
    {
#line 568
    __cil_tmp16 = (void const   *)crt;
#line 568
    kfree(__cil_tmp16);
    }
#line 569
    return;
  } else {

  }
  }
  {
#line 572
  connector = & intel_connector->base;
#line 573
  __cil_tmp17 = & intel_connector->base;
#line 573
  drm_connector_init(dev, __cil_tmp17, & intel_crt_connector_funcs, 1);
#line 576
  __cil_tmp18 = & crt->base.base;
#line 576
  drm_encoder_init(dev, __cil_tmp18, & intel_crt_enc_funcs, 1);
#line 579
  __cil_tmp19 = & crt->base;
#line 579
  intel_connector_attach_encoder(intel_connector, __cil_tmp19);
#line 581
  crt->base.type = 1;
#line 582
  crt->base.clone_mask = 832;
#line 585
  crt->base.crtc_mask = 3;
#line 586
  connector->interlace_allowed = (bool )1;
#line 587
  connector->doublescan_allowed = (bool )0;
#line 589
  __cil_tmp20 = & crt->base.base;
#line 589
  drm_encoder_helper_add(__cil_tmp20, & intel_crt_helper_funcs);
#line 590
  drm_connector_helper_add(connector, & intel_crt_connector_helper_funcs);
#line 592
  drm_sysfs_connector_add(connector);
  }
  {
#line 594
  __cil_tmp21 = dev->dev_private;
#line 594
  __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
#line 594
  __cil_tmp23 = __cil_tmp22->info;
#line 594
  __cil_tmp24 = (unsigned char *)__cil_tmp23;
#line 594
  __cil_tmp25 = __cil_tmp24 + 2UL;
#line 594
  __cil_tmp26 = *__cil_tmp25;
#line 594
  __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 594
  if (__cil_tmp27 != 0U) {
#line 595
    connector->polled = (uint8_t )1U;
  } else {
#line 597
    connector->polled = (uint8_t )2U;
  }
  }
#line 602
  crt->force_hotplug_required = (bool )0;
  {
#line 603
  __cil_tmp28 = dev->dev_private;
#line 603
  __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
#line 603
  __cil_tmp30 = __cil_tmp29->info;
#line 603
  __cil_tmp31 = __cil_tmp30->gen;
#line 603
  __cil_tmp32 = (unsigned char )__cil_tmp31;
#line 603
  __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 603
  if (__cil_tmp33 == 5U) {
#line 603
    goto _L;
  } else {
    {
#line 603
    __cil_tmp34 = dev->dev_private;
#line 603
    __cil_tmp35 = (struct drm_i915_private *)__cil_tmp34;
#line 603
    __cil_tmp36 = __cil_tmp35->info;
#line 603
    __cil_tmp37 = __cil_tmp36->gen;
#line 603
    __cil_tmp38 = (unsigned char )__cil_tmp37;
#line 603
    __cil_tmp39 = (unsigned int )__cil_tmp38;
#line 603
    if (__cil_tmp39 == 6U) {
#line 603
      goto _L;
    } else {
      {
#line 603
      __cil_tmp40 = dev->dev_private;
#line 603
      __cil_tmp41 = (struct drm_i915_private *)__cil_tmp40;
#line 603
      __cil_tmp42 = __cil_tmp41->info;
#line 603
      __cil_tmp43 = (unsigned char *)__cil_tmp42;
#line 603
      __cil_tmp44 = __cil_tmp43 + 2UL;
#line 603
      __cil_tmp45 = *__cil_tmp44;
#line 603
      __cil_tmp46 = (unsigned int )__cil_tmp45;
#line 603
      if (__cil_tmp46 != 0U) {
        _L: 
        {
#line 606
        adpa = i915_read32___7(dev_priv, 921856U);
#line 607
        adpa = adpa & 4227923967U;
#line 608
        adpa = adpa | 15990784U;
#line 609
        i915_write32___5(dev_priv, 921856U, adpa);
#line 610
        __cil_tmp47 = dev_priv->regs;
#line 610
        __cil_tmp48 = (void const volatile   *)__cil_tmp47;
#line 610
        __cil_tmp49 = __cil_tmp48 + 921856U;
#line 610
        readl(__cil_tmp49);
#line 612
        drm_ut_debug_printk(4U, "drm", "intel_crt_init", "pch crt adpa set to 0x%x\n",
                            adpa);
#line 613
        crt->force_hotplug_required = (bool )1;
        }
      } else {

      }
      }
    }
    }
  }
  }
#line 616
  __cil_tmp50 = dev_priv->hotplug_supported_mask;
#line 616
  dev_priv->hotplug_supported_mask = __cil_tmp50 | 2048U;
#line 617
  return;
}
}
#line 7 "include/acpi/button.h"
extern int acpi_lid_notifier_register(struct notifier_block * ) ;
#line 8
extern int acpi_lid_notifier_unregister(struct notifier_block * ) ;
#line 9
extern int acpi_lid_open(void) ;
#line 96 "include/linux/dmi.h"
extern int dmi_check_system(struct dmi_system_id  const  * ) ;
#line 664 "include/drm/drm_crtc.h"
extern int drm_add_edid_modes(struct drm_connector * , struct edid * ) ;
#line 665
extern void drm_mode_probed_add(struct drm_connector * , struct drm_display_mode * ) ;
#line 667
extern struct drm_display_mode *drm_mode_duplicate(struct drm_device * , struct drm_display_mode  const  * ) ;
#line 699
extern int drm_mode_connector_update_edid_property(struct drm_connector * , struct edid * ) ;
#line 719
extern int drm_connector_attach_property(struct drm_connector * , struct drm_property * ,
                                         uint64_t  ) ;
#line 729
extern int drm_mode_create_scaling_mode_property(struct drm_device * ) ;
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___8(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36460: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36460;
      } else {
#line 390
        goto ldv_36461;
      }
      }
      ldv_36461: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___8(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___8(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___6(struct drm_i915_private *dev_priv , u32 reg ,
                                      u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___8(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 260 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode , struct drm_display_mode *adjusted_mode ) ;
#line 262
void intel_pch_panel_fitting(struct drm_device *dev , int fitting_mode , struct drm_display_mode *mode ,
                             struct drm_display_mode *adjusted_mode ) ;
#line 270
void intel_panel_enable_backlight(struct drm_device *dev ) ;
#line 271
void intel_panel_disable_backlight(struct drm_device *dev ) ;
#line 272
enum drm_connector_status intel_panel_detect(struct drm_device *dev ) ;
#line 65 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder ) 
{ struct drm_encoder  const  *__mptr ;

  {
#line 67
  __mptr = (struct drm_encoder  const  *)encoder;
#line 67
  return ((struct intel_lvds *)__mptr);
}
}
#line 70 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 72
  tmp = intel_attached_encoder(connector);
#line 72
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 72
  return ((struct intel_lvds *)__mptr);
}
}
#line 79 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_enable(struct intel_lvds *intel_lvds ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 ctl_reg ;
  u32 lvds_reg ;
  u32 tmp ;
  unsigned long timeout__ ;
  unsigned long tmp___0 ;
  int ret__ ;
  struct thread_info *tmp___1 ;
  int pfo_ret__ ;
  int tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  void *__cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  u8 __cil_tmp19 ;
  unsigned char __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  void *__cil_tmp22 ;
  struct drm_i915_private *__cil_tmp23 ;
  struct intel_device_info  const  *__cil_tmp24 ;
  u8 __cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  void *__cil_tmp28 ;
  struct drm_i915_private *__cil_tmp29 ;
  struct intel_device_info  const  *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  bool __cil_tmp36 ;
  u32 __cil_tmp37 ;
  u32 __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  unsigned long __cil_tmp41 ;
  long __cil_tmp42 ;
  long __cil_tmp43 ;
  long __cil_tmp44 ;
  int __cil_tmp45 ;
  int __cil_tmp46 ;
  atomic_t const   *__cil_tmp47 ;
  int __cil_tmp48 ;
  u32 __cil_tmp49 ;
  u32 __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  void *__cil_tmp53 ;
  void const volatile   *__cil_tmp54 ;
  void const volatile   *__cil_tmp55 ;

  {
#line 81
  dev = intel_lvds->base.base.dev;
#line 82
  __cil_tmp15 = dev->dev_private;
#line 82
  dev_priv = (struct drm_i915_private *)__cil_tmp15;
  {
#line 85
  __cil_tmp16 = dev->dev_private;
#line 85
  __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 85
  __cil_tmp18 = __cil_tmp17->info;
#line 85
  __cil_tmp19 = __cil_tmp18->gen;
#line 85
  __cil_tmp20 = (unsigned char )__cil_tmp19;
#line 85
  __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 85
  if (__cil_tmp21 == 5U) {
#line 86
    ctl_reg = 815620U;
#line 87
    lvds_reg = 921984U;
  } else {
    {
#line 85
    __cil_tmp22 = dev->dev_private;
#line 85
    __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
#line 85
    __cil_tmp24 = __cil_tmp23->info;
#line 85
    __cil_tmp25 = __cil_tmp24->gen;
#line 85
    __cil_tmp26 = (unsigned char )__cil_tmp25;
#line 85
    __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 85
    if (__cil_tmp27 == 6U) {
#line 86
      ctl_reg = 815620U;
#line 87
      lvds_reg = 921984U;
    } else {
      {
#line 85
      __cil_tmp28 = dev->dev_private;
#line 85
      __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
#line 85
      __cil_tmp30 = __cil_tmp29->info;
#line 85
      __cil_tmp31 = (unsigned char *)__cil_tmp30;
#line 85
      __cil_tmp32 = __cil_tmp31 + 2UL;
#line 85
      __cil_tmp33 = *__cil_tmp32;
#line 85
      __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 85
      if (__cil_tmp34 != 0U) {
#line 86
        ctl_reg = 815620U;
#line 87
        lvds_reg = 921984U;
      } else {
#line 89
        ctl_reg = 397828U;
#line 90
        lvds_reg = 397696U;
      }
      }
    }
    }
  }
  }
  {
#line 93
  tmp = i915_read32___8(dev_priv, lvds_reg);
#line 93
  __cil_tmp35 = tmp | 2147483648U;
#line 93
  i915_write32___6(dev_priv, lvds_reg, __cil_tmp35);
  }
  {
#line 95
  __cil_tmp36 = intel_lvds->pfit_dirty;
#line 95
  if ((int )__cil_tmp36) {
    {
#line 102
    __cil_tmp37 = intel_lvds->pfit_control;
#line 102
    __cil_tmp38 = intel_lvds->pfit_pgm_ratios;
#line 102
    drm_ut_debug_printk(4U, "drm", "intel_lvds_enable", "applying panel-fitter: %x, %x\n",
                        __cil_tmp37, __cil_tmp38);
#line 105
    __cil_tmp39 = (unsigned int const   )1000U;
#line 105
    __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 105
    tmp___0 = msecs_to_jiffies(__cil_tmp40);
#line 105
    __cil_tmp41 = (unsigned long )jiffies;
#line 105
    timeout__ = tmp___0 + __cil_tmp41;
#line 105
    ret__ = 0;
    }
#line 105
    goto ldv_40175;
    ldv_40174: ;
    {
#line 105
    __cil_tmp42 = (long )jiffies;
#line 105
    __cil_tmp43 = (long )timeout__;
#line 105
    __cil_tmp44 = __cil_tmp43 - __cil_tmp42;
#line 105
    if (__cil_tmp44 < 0L) {
#line 105
      ret__ = -110;
#line 105
      goto ldv_40165;
    } else {

    }
    }
    {
#line 105
    tmp___1 = current_thread_info();
    }
    {
#line 105
    __cil_tmp45 = tmp___1->preempt_count;
#line 105
    __cil_tmp46 = __cil_tmp45 & -268435457;
#line 105
    if (__cil_tmp46 == 0) {
#line 105
      if (1) {
#line 105
        goto case_4;
      } else {
#line 105
        goto switch_default;
#line 105
        if (0) {
#line 105
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 105
          goto ldv_40168;
#line 105
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 105
          goto ldv_40168;
          case_4: 
#line 105
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 105
          goto ldv_40168;
#line 105
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 105
          goto ldv_40168;
          switch_default: 
          {
#line 105
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_40168: 
      {
#line 105
      __cil_tmp47 = (atomic_t const   *)(& kgdb_active);
#line 105
      tmp___2 = atomic_read(__cil_tmp47);
      }
#line 105
      if (pfo_ret__ != tmp___2) {
        {
#line 105
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_40175: 
    {
#line 105
    tmp___3 = i915_read32___8(dev_priv, 397824U);
    }
    {
#line 105
    __cil_tmp48 = (int )tmp___3;
#line 105
    if (__cil_tmp48 < 0) {
#line 106
      goto ldv_40174;
    } else {
#line 108
      goto ldv_40165;
    }
    }
    ldv_40165: ;
#line 105
    if (ret__ != 0) {
      {
#line 106
      drm_err("intel_lvds_enable", "timed out waiting for panel to power off\n");
      }
    } else {
      {
#line 108
      __cil_tmp49 = intel_lvds->pfit_pgm_ratios;
#line 108
      i915_write32___6(dev_priv, 397876U, __cil_tmp49);
#line 109
      __cil_tmp50 = intel_lvds->pfit_control;
#line 109
      i915_write32___6(dev_priv, 397872U, __cil_tmp50);
#line 110
      intel_lvds->pfit_dirty = (bool )0;
      }
    }
  } else {

  }
  }
  {
#line 114
  tmp___4 = i915_read32___8(dev_priv, ctl_reg);
#line 114
  __cil_tmp51 = tmp___4 | 1U;
#line 114
  i915_write32___6(dev_priv, ctl_reg, __cil_tmp51);
#line 115
  __cil_tmp52 = (unsigned long )lvds_reg;
#line 115
  __cil_tmp53 = dev_priv->regs;
#line 115
  __cil_tmp54 = (void const volatile   *)__cil_tmp53;
#line 115
  __cil_tmp55 = __cil_tmp54 + __cil_tmp52;
#line 115
  readl(__cil_tmp55);
#line 117
  intel_panel_enable_backlight(dev);
  }
#line 118
  return;
}
}
#line 120 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_disable(struct intel_lvds *intel_lvds ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 ctl_reg ;
  u32 lvds_reg ;
  u32 tmp ;
  unsigned long timeout__ ;
  unsigned long tmp___0 ;
  int ret__ ;
  struct thread_info *tmp___1 ;
  int pfo_ret__ ;
  int tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  void *__cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  u8 __cil_tmp19 ;
  unsigned char __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  void *__cil_tmp22 ;
  struct drm_i915_private *__cil_tmp23 ;
  struct intel_device_info  const  *__cil_tmp24 ;
  u8 __cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  void *__cil_tmp28 ;
  struct drm_i915_private *__cil_tmp29 ;
  struct intel_device_info  const  *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  u32 __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  long __cil_tmp40 ;
  long __cil_tmp41 ;
  long __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  atomic_t const   *__cil_tmp45 ;
  int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  void *__cil_tmp49 ;
  void const volatile   *__cil_tmp50 ;
  void const volatile   *__cil_tmp51 ;

  {
#line 122
  dev = intel_lvds->base.base.dev;
#line 123
  __cil_tmp15 = dev->dev_private;
#line 123
  dev_priv = (struct drm_i915_private *)__cil_tmp15;
  {
#line 126
  __cil_tmp16 = dev->dev_private;
#line 126
  __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 126
  __cil_tmp18 = __cil_tmp17->info;
#line 126
  __cil_tmp19 = __cil_tmp18->gen;
#line 126
  __cil_tmp20 = (unsigned char )__cil_tmp19;
#line 126
  __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 126
  if (__cil_tmp21 == 5U) {
#line 127
    ctl_reg = 815620U;
#line 128
    lvds_reg = 921984U;
  } else {
    {
#line 126
    __cil_tmp22 = dev->dev_private;
#line 126
    __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
#line 126
    __cil_tmp24 = __cil_tmp23->info;
#line 126
    __cil_tmp25 = __cil_tmp24->gen;
#line 126
    __cil_tmp26 = (unsigned char )__cil_tmp25;
#line 126
    __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 126
    if (__cil_tmp27 == 6U) {
#line 127
      ctl_reg = 815620U;
#line 128
      lvds_reg = 921984U;
    } else {
      {
#line 126
      __cil_tmp28 = dev->dev_private;
#line 126
      __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
#line 126
      __cil_tmp30 = __cil_tmp29->info;
#line 126
      __cil_tmp31 = (unsigned char *)__cil_tmp30;
#line 126
      __cil_tmp32 = __cil_tmp31 + 2UL;
#line 126
      __cil_tmp33 = *__cil_tmp32;
#line 126
      __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 126
      if (__cil_tmp34 != 0U) {
#line 127
        ctl_reg = 815620U;
#line 128
        lvds_reg = 921984U;
      } else {
#line 130
        ctl_reg = 397828U;
#line 131
        lvds_reg = 397696U;
      }
      }
    }
    }
  }
  }
  {
#line 134
  intel_panel_disable_backlight(dev);
#line 136
  tmp = i915_read32___8(dev_priv, ctl_reg);
#line 136
  __cil_tmp35 = tmp & 4294967294U;
#line 136
  i915_write32___6(dev_priv, ctl_reg, __cil_tmp35);
  }
  {
#line 138
  __cil_tmp36 = intel_lvds->pfit_control;
#line 138
  if (__cil_tmp36 != 0U) {
    {
#line 139
    __cil_tmp37 = (unsigned int const   )1000U;
#line 139
    __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 139
    tmp___0 = msecs_to_jiffies(__cil_tmp38);
#line 139
    __cil_tmp39 = (unsigned long )jiffies;
#line 139
    timeout__ = tmp___0 + __cil_tmp39;
#line 139
    ret__ = 0;
    }
#line 139
    goto ldv_40202;
    ldv_40201: ;
    {
#line 139
    __cil_tmp40 = (long )jiffies;
#line 139
    __cil_tmp41 = (long )timeout__;
#line 139
    __cil_tmp42 = __cil_tmp41 - __cil_tmp40;
#line 139
    if (__cil_tmp42 < 0L) {
#line 139
      ret__ = -110;
#line 139
      goto ldv_40192;
    } else {

    }
    }
    {
#line 139
    tmp___1 = current_thread_info();
    }
    {
#line 139
    __cil_tmp43 = tmp___1->preempt_count;
#line 139
    __cil_tmp44 = __cil_tmp43 & -268435457;
#line 139
    if (__cil_tmp44 == 0) {
#line 139
      if (1) {
#line 139
        goto case_4;
      } else {
#line 139
        goto switch_default;
#line 139
        if (0) {
#line 139
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 139
          goto ldv_40195;
#line 139
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 139
          goto ldv_40195;
          case_4: 
#line 139
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 139
          goto ldv_40195;
#line 139
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 139
          goto ldv_40195;
          switch_default: 
          {
#line 139
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_40195: 
      {
#line 139
      __cil_tmp45 = (atomic_t const   *)(& kgdb_active);
#line 139
      tmp___2 = atomic_read(__cil_tmp45);
      }
#line 139
      if (pfo_ret__ != tmp___2) {
        {
#line 139
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_40202: 
    {
#line 139
    tmp___3 = i915_read32___8(dev_priv, 397824U);
    }
    {
#line 139
    __cil_tmp46 = (int )tmp___3;
#line 139
    if (__cil_tmp46 < 0) {
#line 140
      goto ldv_40201;
    } else {
#line 142
      goto ldv_40192;
    }
    }
    ldv_40192: ;
#line 139
    if (ret__ != 0) {
      {
#line 140
      drm_err("intel_lvds_disable", "timed out waiting for panel to power off\n");
      }
    } else {

    }
    {
#line 142
    i915_write32___6(dev_priv, 397872U, 0U);
#line 143
    intel_lvds->pfit_dirty = (bool )1;
    }
  } else {

  }
  }
  {
#line 146
  tmp___4 = i915_read32___8(dev_priv, lvds_reg);
#line 146
  __cil_tmp47 = tmp___4 & 2147483647U;
#line 146
  i915_write32___6(dev_priv, lvds_reg, __cil_tmp47);
#line 147
  __cil_tmp48 = (unsigned long )lvds_reg;
#line 147
  __cil_tmp49 = dev_priv->regs;
#line 147
  __cil_tmp50 = (void const volatile   *)__cil_tmp49;
#line 147
  __cil_tmp51 = __cil_tmp50 + __cil_tmp48;
#line 147
  readl(__cil_tmp51);
  }
#line 148
  return;
}
}
#line 150 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_dpms(struct drm_encoder *encoder , int mode ) 
{ struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;

  {
  {
#line 152
  tmp = to_intel_lvds(encoder);
#line 152
  intel_lvds = tmp;
  }
#line 154
  if (mode == 0) {
    {
#line 155
    intel_lvds_enable(intel_lvds);
    }
  } else {
    {
#line 157
    intel_lvds_disable(intel_lvds);
    }
  }
#line 158
  return;
}
}
#line 162 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static int intel_lvds_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) 
{ struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;
  struct drm_display_mode *fixed_mode ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;

  {
  {
#line 165
  tmp = intel_attached_lvds(connector);
#line 165
  intel_lvds = tmp;
#line 166
  fixed_mode = intel_lvds->fixed_mode;
  }
  {
#line 168
  __cil_tmp6 = fixed_mode->hdisplay;
#line 168
  __cil_tmp7 = mode->hdisplay;
#line 168
  if (__cil_tmp7 > __cil_tmp6) {
#line 169
    return (29);
  } else {

  }
  }
  {
#line 170
  __cil_tmp8 = fixed_mode->vdisplay;
#line 170
  __cil_tmp9 = mode->vdisplay;
#line 170
  if (__cil_tmp9 > __cil_tmp8) {
#line 171
    return (29);
  } else {

  }
  }
#line 173
  return (0);
}
}
#line 177 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void centre_horizontally(struct drm_display_mode *mode , int width ) 
{ u32 border ;
  u32 sync_pos ;
  u32 blank_width ;
  u32 sync_width ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  u32 __cil_tmp13 ;
  u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  u32 __cil_tmp20 ;
  u32 __cil_tmp21 ;
  int __cil_tmp22 ;
  u32 __cil_tmp23 ;
  u32 __cil_tmp24 ;
  int __cil_tmp25 ;
  u32 __cil_tmp26 ;
  u32 __cil_tmp27 ;
  int __cil_tmp28 ;
  u32 __cil_tmp29 ;
  u32 __cil_tmp30 ;

  {
#line 183
  __cil_tmp7 = mode->crtc_hsync_start;
#line 183
  __cil_tmp8 = mode->crtc_hsync_end;
#line 183
  __cil_tmp9 = __cil_tmp8 - __cil_tmp7;
#line 183
  sync_width = (u32 )__cil_tmp9;
#line 184
  __cil_tmp10 = mode->crtc_hblank_start;
#line 184
  __cil_tmp11 = mode->crtc_hblank_end;
#line 184
  __cil_tmp12 = __cil_tmp11 - __cil_tmp10;
#line 184
  blank_width = (u32 )__cil_tmp12;
#line 185
  __cil_tmp13 = blank_width - sync_width;
#line 185
  __cil_tmp14 = __cil_tmp13 + 1U;
#line 185
  sync_pos = __cil_tmp14 / 2U;
#line 187
  __cil_tmp15 = mode->hdisplay;
#line 187
  __cil_tmp16 = __cil_tmp15 - width;
#line 187
  __cil_tmp17 = __cil_tmp16 + 1;
#line 187
  __cil_tmp18 = __cil_tmp17 / 2;
#line 187
  border = (u32 )__cil_tmp18;
#line 188
  __cil_tmp19 = border & 1U;
#line 188
  border = __cil_tmp19 + border;
#line 190
  mode->crtc_hdisplay = width;
#line 191
  __cil_tmp20 = (u32 )width;
#line 191
  __cil_tmp21 = __cil_tmp20 + border;
#line 191
  mode->crtc_hblank_start = (int )__cil_tmp21;
#line 192
  __cil_tmp22 = mode->crtc_hblank_start;
#line 192
  __cil_tmp23 = (u32 )__cil_tmp22;
#line 192
  __cil_tmp24 = __cil_tmp23 + blank_width;
#line 192
  mode->crtc_hblank_end = (int )__cil_tmp24;
#line 194
  __cil_tmp25 = mode->crtc_hblank_start;
#line 194
  __cil_tmp26 = (u32 )__cil_tmp25;
#line 194
  __cil_tmp27 = __cil_tmp26 + sync_pos;
#line 194
  mode->crtc_hsync_start = (int )__cil_tmp27;
#line 195
  __cil_tmp28 = mode->crtc_hsync_start;
#line 195
  __cil_tmp29 = (u32 )__cil_tmp28;
#line 195
  __cil_tmp30 = __cil_tmp29 + sync_width;
#line 195
  mode->crtc_hsync_end = (int )__cil_tmp30;
#line 196
  return;
}
}
#line 199 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void centre_vertically(struct drm_display_mode *mode , int height ) 
{ u32 border ;
  u32 sync_pos ;
  u32 blank_width ;
  u32 sync_width ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  u32 __cil_tmp13 ;
  u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  u32 __cil_tmp20 ;
  int __cil_tmp21 ;
  u32 __cil_tmp22 ;
  u32 __cil_tmp23 ;
  int __cil_tmp24 ;
  u32 __cil_tmp25 ;
  u32 __cil_tmp26 ;
  int __cil_tmp27 ;
  u32 __cil_tmp28 ;
  u32 __cil_tmp29 ;

  {
#line 205
  __cil_tmp7 = mode->crtc_vsync_start;
#line 205
  __cil_tmp8 = mode->crtc_vsync_end;
#line 205
  __cil_tmp9 = __cil_tmp8 - __cil_tmp7;
#line 205
  sync_width = (u32 )__cil_tmp9;
#line 206
  __cil_tmp10 = mode->crtc_vblank_start;
#line 206
  __cil_tmp11 = mode->crtc_vblank_end;
#line 206
  __cil_tmp12 = __cil_tmp11 - __cil_tmp10;
#line 206
  blank_width = (u32 )__cil_tmp12;
#line 207
  __cil_tmp13 = blank_width - sync_width;
#line 207
  __cil_tmp14 = __cil_tmp13 + 1U;
#line 207
  sync_pos = __cil_tmp14 / 2U;
#line 209
  __cil_tmp15 = mode->vdisplay;
#line 209
  __cil_tmp16 = __cil_tmp15 - height;
#line 209
  __cil_tmp17 = __cil_tmp16 + 1;
#line 209
  __cil_tmp18 = __cil_tmp17 / 2;
#line 209
  border = (u32 )__cil_tmp18;
#line 211
  mode->crtc_vdisplay = height;
#line 212
  __cil_tmp19 = (u32 )height;
#line 212
  __cil_tmp20 = __cil_tmp19 + border;
#line 212
  mode->crtc_vblank_start = (int )__cil_tmp20;
#line 213
  __cil_tmp21 = mode->crtc_vblank_start;
#line 213
  __cil_tmp22 = (u32 )__cil_tmp21;
#line 213
  __cil_tmp23 = __cil_tmp22 + blank_width;
#line 213
  mode->crtc_vblank_end = (int )__cil_tmp23;
#line 215
  __cil_tmp24 = mode->crtc_vblank_start;
#line 215
  __cil_tmp25 = (u32 )__cil_tmp24;
#line 215
  __cil_tmp26 = __cil_tmp25 + sync_pos;
#line 215
  mode->crtc_vsync_start = (int )__cil_tmp26;
#line 216
  __cil_tmp27 = mode->crtc_vsync_start;
#line 216
  __cil_tmp28 = (u32 )__cil_tmp27;
#line 216
  __cil_tmp29 = __cil_tmp28 + sync_width;
#line 216
  mode->crtc_vsync_end = (int )__cil_tmp29;
#line 217
  return;
}
}
#line 219 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
__inline static u32 panel_fitter_scaling(u32 source , u32 target ) 
{ u32 ratio ;
  u32 __cil_tmp4 ;
  u32 __cil_tmp5 ;
  u32 __cil_tmp6 ;

  {
#line 228
  __cil_tmp4 = source * 4096U;
#line 228
  ratio = __cil_tmp4 / target;
  {
#line 229
  __cil_tmp5 = ratio * 4096U;
#line 229
  __cil_tmp6 = __cil_tmp5 + 2048U;
#line 229
  return (__cil_tmp6 / 4096U);
  }
}
}
#line 232 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static bool intel_lvds_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                  struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;
  struct drm_encoder *tmp_encoder ;
  u32 pfit_control ;
  u32 pfit_pgm_ratios ;
  u32 border ;
  int pipe ;
  struct list_head  const  *__mptr___0 ;
  struct list_head  const  *__mptr___1 ;
  u32 scaled_width ;
  u32 scaled_height ;
  u32 scaled_width___0 ;
  u32 scaled_height___0 ;
  u32 bits ;
  u32 tmp___0 ;
  u32 bits___0 ;
  u32 tmp___1 ;
  void *__cil_tmp25 ;
  struct drm_crtc *__cil_tmp26 ;
  void *__cil_tmp27 ;
  struct drm_i915_private *__cil_tmp28 ;
  struct intel_device_info  const  *__cil_tmp29 ;
  u8 __cil_tmp30 ;
  unsigned char __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  enum pipe __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  struct list_head *__cil_tmp35 ;
  struct drm_encoder *__cil_tmp36 ;
  unsigned long __cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  struct drm_crtc *__cil_tmp39 ;
  unsigned long __cil_tmp40 ;
  struct drm_crtc *__cil_tmp41 ;
  unsigned long __cil_tmp42 ;
  struct list_head *__cil_tmp43 ;
  struct drm_encoder *__cil_tmp44 ;
  struct list_head *__cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  struct list_head *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  struct drm_display_mode *__cil_tmp49 ;
  void *__cil_tmp50 ;
  struct drm_i915_private *__cil_tmp51 ;
  struct intel_device_info  const  *__cil_tmp52 ;
  u8 __cil_tmp53 ;
  unsigned char __cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  int __cil_tmp56 ;
  void *__cil_tmp57 ;
  struct drm_i915_private *__cil_tmp58 ;
  struct intel_device_info  const  *__cil_tmp59 ;
  u8 __cil_tmp60 ;
  unsigned char __cil_tmp61 ;
  unsigned int __cil_tmp62 ;
  int __cil_tmp63 ;
  void *__cil_tmp64 ;
  struct drm_i915_private *__cil_tmp65 ;
  struct intel_device_info  const  *__cil_tmp66 ;
  unsigned char *__cil_tmp67 ;
  unsigned char *__cil_tmp68 ;
  unsigned char __cil_tmp69 ;
  unsigned int __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  int __cil_tmp75 ;
  void *__cil_tmp76 ;
  struct drm_i915_private *__cil_tmp77 ;
  struct intel_device_info  const  *__cil_tmp78 ;
  u8 __cil_tmp79 ;
  unsigned char __cil_tmp80 ;
  unsigned int __cil_tmp81 ;
  enum pipe __cil_tmp82 ;
  unsigned int __cil_tmp83 ;
  unsigned int __cil_tmp84 ;
  int __cil_tmp85 ;
  int __cil_tmp86 ;
  u32 __cil_tmp87 ;
  int __cil_tmp88 ;
  int __cil_tmp89 ;
  int __cil_tmp90 ;
  int __cil_tmp91 ;
  int __cil_tmp92 ;
  int __cil_tmp93 ;
  void *__cil_tmp94 ;
  struct drm_i915_private *__cil_tmp95 ;
  struct intel_device_info  const  *__cil_tmp96 ;
  u8 __cil_tmp97 ;
  unsigned char __cil_tmp98 ;
  unsigned int __cil_tmp99 ;
  int __cil_tmp100 ;
  int __cil_tmp101 ;
  int __cil_tmp102 ;
  int __cil_tmp103 ;
  int __cil_tmp104 ;
  int __cil_tmp105 ;
  int __cil_tmp106 ;
  int __cil_tmp107 ;
  int __cil_tmp108 ;
  int __cil_tmp109 ;
  int __cil_tmp110 ;
  int __cil_tmp111 ;
  int __cil_tmp112 ;
  int __cil_tmp113 ;
  int __cil_tmp114 ;
  u32 __cil_tmp115 ;
  u32 __cil_tmp116 ;
  int __cil_tmp117 ;
  int __cil_tmp118 ;
  int __cil_tmp119 ;
  int __cil_tmp120 ;
  u32 __cil_tmp121 ;
  int __cil_tmp122 ;
  u32 __cil_tmp123 ;
  u32 __cil_tmp124 ;
  u32 __cil_tmp125 ;
  unsigned int __cil_tmp126 ;
  int __cil_tmp127 ;
  u32 __cil_tmp128 ;
  u32 __cil_tmp129 ;
  int __cil_tmp130 ;
  int __cil_tmp131 ;
  int __cil_tmp132 ;
  int __cil_tmp133 ;
  u32 __cil_tmp134 ;
  int __cil_tmp135 ;
  u32 __cil_tmp136 ;
  u32 __cil_tmp137 ;
  u32 __cil_tmp138 ;
  unsigned int __cil_tmp139 ;
  int __cil_tmp140 ;
  int __cil_tmp141 ;
  int __cil_tmp142 ;
  int __cil_tmp143 ;
  void *__cil_tmp144 ;
  struct drm_i915_private *__cil_tmp145 ;
  struct intel_device_info  const  *__cil_tmp146 ;
  u8 __cil_tmp147 ;
  unsigned char __cil_tmp148 ;
  unsigned int __cil_tmp149 ;
  int __cil_tmp150 ;
  void *__cil_tmp151 ;
  struct drm_i915_private *__cil_tmp152 ;
  struct intel_device_info  const  *__cil_tmp153 ;
  u8 __cil_tmp154 ;
  unsigned char __cil_tmp155 ;
  unsigned int __cil_tmp156 ;
  unsigned char *__cil_tmp157 ;
  unsigned char *__cil_tmp158 ;
  unsigned char __cil_tmp159 ;
  unsigned int __cil_tmp160 ;
  u32 __cil_tmp161 ;
  u32 __cil_tmp162 ;

  {
  {
#line 236
  dev = encoder->dev;
#line 237
  __cil_tmp25 = dev->dev_private;
#line 237
  dev_priv = (struct drm_i915_private *)__cil_tmp25;
#line 238
  __cil_tmp26 = encoder->crtc;
#line 238
  __mptr = (struct drm_crtc  const  *)__cil_tmp26;
#line 238
  intel_crtc = (struct intel_crtc *)__mptr;
#line 239
  tmp = to_intel_lvds(encoder);
#line 239
  intel_lvds = tmp;
#line 241
  pfit_control = 0U;
#line 241
  pfit_pgm_ratios = 0U;
#line 241
  border = 0U;
  }
  {
#line 245
  __cil_tmp27 = dev->dev_private;
#line 245
  __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
#line 245
  __cil_tmp29 = __cil_tmp28->info;
#line 245
  __cil_tmp30 = __cil_tmp29->gen;
#line 245
  __cil_tmp31 = (unsigned char )__cil_tmp30;
#line 245
  __cil_tmp32 = (unsigned int )__cil_tmp31;
#line 245
  if (__cil_tmp32 <= 3U) {
    {
#line 245
    __cil_tmp33 = intel_crtc->pipe;
#line 245
    __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 245
    if (__cil_tmp34 == 0U) {
      {
#line 246
      drm_err("intel_lvds_mode_fixup", "Can\'t support LVDS on pipe A\n");
      }
#line 247
      return ((bool )0);
    } else {

    }
    }
  } else {

  }
  }
#line 251
  __cil_tmp35 = dev->mode_config.encoder_list.next;
#line 251
  __mptr___0 = (struct list_head  const  *)__cil_tmp35;
#line 251
  __cil_tmp36 = (struct drm_encoder *)__mptr___0;
#line 251
  tmp_encoder = __cil_tmp36 + 1152921504606846968UL;
#line 251
  goto ldv_40259;
  ldv_40258: ;
  {
#line 252
  __cil_tmp37 = (unsigned long )encoder;
#line 252
  __cil_tmp38 = (unsigned long )tmp_encoder;
#line 252
  if (__cil_tmp38 != __cil_tmp37) {
    {
#line 252
    __cil_tmp39 = encoder->crtc;
#line 252
    __cil_tmp40 = (unsigned long )__cil_tmp39;
#line 252
    __cil_tmp41 = tmp_encoder->crtc;
#line 252
    __cil_tmp42 = (unsigned long )__cil_tmp41;
#line 252
    if (__cil_tmp42 == __cil_tmp40) {
      {
#line 253
      drm_err("intel_lvds_mode_fixup", "Can\'t enable LVDS and another encoder on the same pipe\n");
      }
#line 255
      return ((bool )0);
    } else {

    }
    }
  } else {

  }
  }
#line 251
  __cil_tmp43 = tmp_encoder->head.next;
#line 251
  __mptr___1 = (struct list_head  const  *)__cil_tmp43;
#line 251
  __cil_tmp44 = (struct drm_encoder *)__mptr___1;
#line 251
  tmp_encoder = __cil_tmp44 + 1152921504606846968UL;
  ldv_40259: ;
  {
#line 251
  __cil_tmp45 = & dev->mode_config.encoder_list;
#line 251
  __cil_tmp46 = (unsigned long )__cil_tmp45;
#line 251
  __cil_tmp47 = & tmp_encoder->head;
#line 251
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 251
  if (__cil_tmp48 != __cil_tmp46) {
#line 252
    goto ldv_40258;
  } else {
#line 254
    goto ldv_40260;
  }
  }
  ldv_40260: 
  {
#line 265
  __cil_tmp49 = intel_lvds->fixed_mode;
#line 265
  intel_fixed_panel_mode(__cil_tmp49, adjusted_mode);
  }
  {
#line 267
  __cil_tmp50 = dev->dev_private;
#line 267
  __cil_tmp51 = (struct drm_i915_private *)__cil_tmp50;
#line 267
  __cil_tmp52 = __cil_tmp51->info;
#line 267
  __cil_tmp53 = __cil_tmp52->gen;
#line 267
  __cil_tmp54 = (unsigned char )__cil_tmp53;
#line 267
  __cil_tmp55 = (unsigned int )__cil_tmp54;
#line 267
  if (__cil_tmp55 == 5U) {
    {
#line 268
    __cil_tmp56 = intel_lvds->fitting_mode;
#line 268
    intel_pch_panel_fitting(dev, __cil_tmp56, mode, adjusted_mode);
    }
#line 270
    return ((bool )1);
  } else {
    {
#line 267
    __cil_tmp57 = dev->dev_private;
#line 267
    __cil_tmp58 = (struct drm_i915_private *)__cil_tmp57;
#line 267
    __cil_tmp59 = __cil_tmp58->info;
#line 267
    __cil_tmp60 = __cil_tmp59->gen;
#line 267
    __cil_tmp61 = (unsigned char )__cil_tmp60;
#line 267
    __cil_tmp62 = (unsigned int )__cil_tmp61;
#line 267
    if (__cil_tmp62 == 6U) {
      {
#line 268
      __cil_tmp63 = intel_lvds->fitting_mode;
#line 268
      intel_pch_panel_fitting(dev, __cil_tmp63, mode, adjusted_mode);
      }
#line 270
      return ((bool )1);
    } else {
      {
#line 267
      __cil_tmp64 = dev->dev_private;
#line 267
      __cil_tmp65 = (struct drm_i915_private *)__cil_tmp64;
#line 267
      __cil_tmp66 = __cil_tmp65->info;
#line 267
      __cil_tmp67 = (unsigned char *)__cil_tmp66;
#line 267
      __cil_tmp68 = __cil_tmp67 + 2UL;
#line 267
      __cil_tmp69 = *__cil_tmp68;
#line 267
      __cil_tmp70 = (unsigned int )__cil_tmp69;
#line 267
      if (__cil_tmp70 != 0U) {
        {
#line 268
        __cil_tmp71 = intel_lvds->fitting_mode;
#line 268
        intel_pch_panel_fitting(dev, __cil_tmp71, mode, adjusted_mode);
        }
#line 270
        return ((bool )1);
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 274
  __cil_tmp72 = mode->hdisplay;
#line 274
  __cil_tmp73 = adjusted_mode->hdisplay;
#line 274
  if (__cil_tmp73 == __cil_tmp72) {
    {
#line 274
    __cil_tmp74 = mode->vdisplay;
#line 274
    __cil_tmp75 = adjusted_mode->vdisplay;
#line 274
    if (__cil_tmp75 == __cil_tmp74) {
#line 276
      goto out;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 279
  __cil_tmp76 = dev->dev_private;
#line 279
  __cil_tmp77 = (struct drm_i915_private *)__cil_tmp76;
#line 279
  __cil_tmp78 = __cil_tmp77->info;
#line 279
  __cil_tmp79 = __cil_tmp78->gen;
#line 279
  __cil_tmp80 = (unsigned char )__cil_tmp79;
#line 279
  __cil_tmp81 = (unsigned int )__cil_tmp80;
#line 279
  if (__cil_tmp81 > 3U) {
#line 280
    __cil_tmp82 = intel_crtc->pipe;
#line 280
    __cil_tmp83 = (unsigned int )__cil_tmp82;
#line 280
    __cil_tmp84 = __cil_tmp83 << 29;
#line 280
    pfit_control = __cil_tmp84 | pfit_control;
  } else {

  }
  }
#line 289
  pipe = 0;
#line 289
  goto ldv_40263;
  ldv_40262: 
  {
#line 290
  __cil_tmp85 = pipe * 4096;
#line 290
  __cil_tmp86 = __cil_tmp85 + 393248;
#line 290
  __cil_tmp87 = (u32 )__cil_tmp86;
#line 290
  i915_write32___6(dev_priv, __cil_tmp87, 0U);
#line 289
  pipe = pipe + 1;
  }
  ldv_40263: ;
  {
#line 289
  __cil_tmp88 = dev_priv->num_pipe;
#line 289
  if (__cil_tmp88 > pipe) {
#line 290
    goto ldv_40262;
  } else {
#line 292
    goto ldv_40264;
  }
  }
  ldv_40264: ;
  {
#line 293
  __cil_tmp89 = intel_lvds->fitting_mode;
#line 293
  if (__cil_tmp89 == 2) {
#line 293
    goto case_2;
  } else {
    {
#line 303
    __cil_tmp90 = intel_lvds->fitting_mode;
#line 303
    if (__cil_tmp90 == 3) {
#line 303
      goto case_3;
    } else {
      {
#line 357
      __cil_tmp91 = intel_lvds->fitting_mode;
#line 357
      if (__cil_tmp91 == 1) {
#line 357
        goto case_1;
      } else {
#line 375
        goto switch_default;
#line 292
        if (0) {
          case_2: 
          {
#line 298
          __cil_tmp92 = mode->hdisplay;
#line 298
          centre_horizontally(adjusted_mode, __cil_tmp92);
#line 299
          __cil_tmp93 = mode->vdisplay;
#line 299
          centre_vertically(adjusted_mode, __cil_tmp93);
#line 300
          border = 32768U;
          }
#line 301
          goto ldv_40266;
          case_3: ;
          {
#line 305
          __cil_tmp94 = dev->dev_private;
#line 305
          __cil_tmp95 = (struct drm_i915_private *)__cil_tmp94;
#line 305
          __cil_tmp96 = __cil_tmp95->info;
#line 305
          __cil_tmp97 = __cil_tmp96->gen;
#line 305
          __cil_tmp98 = (unsigned char )__cil_tmp97;
#line 305
          __cil_tmp99 = (unsigned int )__cil_tmp98;
#line 305
          if (__cil_tmp99 > 3U) {
#line 306
            __cil_tmp100 = mode->vdisplay;
#line 306
            __cil_tmp101 = adjusted_mode->hdisplay;
#line 306
            __cil_tmp102 = __cil_tmp101 * __cil_tmp100;
#line 306
            scaled_width = (u32 )__cil_tmp102;
#line 307
            __cil_tmp103 = adjusted_mode->vdisplay;
#line 307
            __cil_tmp104 = mode->hdisplay;
#line 307
            __cil_tmp105 = __cil_tmp104 * __cil_tmp103;
#line 307
            scaled_height = (u32 )__cil_tmp105;
#line 310
            if (scaled_width > scaled_height) {
#line 311
              pfit_control = pfit_control | 2281701376U;
            } else
#line 312
            if (scaled_width < scaled_height) {
#line 313
              pfit_control = pfit_control | 2348810240U;
            } else {
              {
#line 314
              __cil_tmp106 = mode->hdisplay;
#line 314
              __cil_tmp107 = adjusted_mode->hdisplay;
#line 314
              if (__cil_tmp107 != __cil_tmp106) {
#line 315
                pfit_control = pfit_control | 2147483648U;
              } else {

              }
              }
            }
          } else {
#line 317
            __cil_tmp108 = mode->vdisplay;
#line 317
            __cil_tmp109 = adjusted_mode->hdisplay;
#line 317
            __cil_tmp110 = __cil_tmp109 * __cil_tmp108;
#line 317
            scaled_width___0 = (u32 )__cil_tmp110;
#line 318
            __cil_tmp111 = adjusted_mode->vdisplay;
#line 318
            __cil_tmp112 = mode->hdisplay;
#line 318
            __cil_tmp113 = __cil_tmp112 * __cil_tmp111;
#line 318
            scaled_height___0 = (u32 )__cil_tmp113;
#line 324
            if (scaled_width___0 > scaled_height___0) {
              {
#line 325
              __cil_tmp114 = mode->vdisplay;
#line 325
              __cil_tmp115 = (u32 )__cil_tmp114;
#line 325
              __cil_tmp116 = scaled_height___0 / __cil_tmp115;
#line 325
              __cil_tmp117 = (int )__cil_tmp116;
#line 325
              centre_horizontally(adjusted_mode, __cil_tmp117);
#line 327
              border = 32768U;
              }
              {
#line 328
              __cil_tmp118 = adjusted_mode->vdisplay;
#line 328
              __cil_tmp119 = mode->vdisplay;
#line 328
              if (__cil_tmp119 != __cil_tmp118) {
                {
#line 329
                __cil_tmp120 = mode->vdisplay;
#line 329
                __cil_tmp121 = (u32 )__cil_tmp120;
#line 329
                __cil_tmp122 = adjusted_mode->vdisplay;
#line 329
                __cil_tmp123 = (u32 )__cil_tmp122;
#line 329
                tmp___0 = panel_fitter_scaling(__cil_tmp121, __cil_tmp123);
#line 329
                bits = tmp___0;
#line 330
                __cil_tmp124 = bits << 20;
#line 330
                __cil_tmp125 = bits << 4;
#line 330
                __cil_tmp126 = __cil_tmp125 | __cil_tmp124;
#line 330
                pfit_pgm_ratios = __cil_tmp126 | pfit_pgm_ratios;
#line 332
                pfit_control = pfit_control | 2147484736U;
                }
              } else {

              }
              }
            } else
#line 336
            if (scaled_width___0 < scaled_height___0) {
              {
#line 337
              __cil_tmp127 = mode->hdisplay;
#line 337
              __cil_tmp128 = (u32 )__cil_tmp127;
#line 337
              __cil_tmp129 = scaled_width___0 / __cil_tmp128;
#line 337
              __cil_tmp130 = (int )__cil_tmp129;
#line 337
              centre_vertically(adjusted_mode, __cil_tmp130);
#line 339
              border = 32768U;
              }
              {
#line 340
              __cil_tmp131 = adjusted_mode->hdisplay;
#line 340
              __cil_tmp132 = mode->hdisplay;
#line 340
              if (__cil_tmp132 != __cil_tmp131) {
                {
#line 341
                __cil_tmp133 = mode->hdisplay;
#line 341
                __cil_tmp134 = (u32 )__cil_tmp133;
#line 341
                __cil_tmp135 = adjusted_mode->hdisplay;
#line 341
                __cil_tmp136 = (u32 )__cil_tmp135;
#line 341
                tmp___1 = panel_fitter_scaling(__cil_tmp134, __cil_tmp136);
#line 341
                bits___0 = tmp___1;
#line 342
                __cil_tmp137 = bits___0 << 20;
#line 342
                __cil_tmp138 = bits___0 << 4;
#line 342
                __cil_tmp139 = __cil_tmp138 | __cil_tmp137;
#line 342
                pfit_pgm_ratios = __cil_tmp139 | pfit_pgm_ratios;
#line 344
                pfit_control = pfit_control | 2147484736U;
                }
              } else {

              }
              }
            } else {
#line 350
              pfit_control = pfit_control | 2147485280U;
            }
          }
          }
#line 355
          goto ldv_40266;
          case_1: ;
          {
#line 362
          __cil_tmp140 = adjusted_mode->vdisplay;
#line 362
          __cil_tmp141 = mode->vdisplay;
#line 362
          if (__cil_tmp141 != __cil_tmp140) {
#line 362
            goto _L;
          } else {
            {
#line 362
            __cil_tmp142 = adjusted_mode->hdisplay;
#line 362
            __cil_tmp143 = mode->hdisplay;
#line 362
            if (__cil_tmp143 != __cil_tmp142) {
              _L: 
#line 364
              pfit_control = pfit_control | 2147483648U;
              {
#line 365
              __cil_tmp144 = dev->dev_private;
#line 365
              __cil_tmp145 = (struct drm_i915_private *)__cil_tmp144;
#line 365
              __cil_tmp146 = __cil_tmp145->info;
#line 365
              __cil_tmp147 = __cil_tmp146->gen;
#line 365
              __cil_tmp148 = (unsigned char )__cil_tmp147;
#line 365
              __cil_tmp149 = (unsigned int )__cil_tmp148;
#line 365
              if (__cil_tmp149 > 3U) {
#line 366
                pfit_control = pfit_control;
              } else {
#line 368
                pfit_control = pfit_control | 1632U;
              }
              }
            } else {

            }
            }
          }
          }
#line 373
          goto ldv_40266;
          switch_default: ;
#line 376
          goto ldv_40266;
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_40266: ;
  out: ;
  {
#line 381
  __cil_tmp150 = (int )pfit_control;
#line 381
  if (__cil_tmp150 >= 0) {
#line 382
    pfit_control = 0U;
#line 383
    pfit_pgm_ratios = 0U;
  } else {

  }
  }
  {
#line 387
  __cil_tmp151 = dev->dev_private;
#line 387
  __cil_tmp152 = (struct drm_i915_private *)__cil_tmp151;
#line 387
  __cil_tmp153 = __cil_tmp152->info;
#line 387
  __cil_tmp154 = __cil_tmp153->gen;
#line 387
  __cil_tmp155 = (unsigned char )__cil_tmp154;
#line 387
  __cil_tmp156 = (unsigned int )__cil_tmp155;
#line 387
  if (__cil_tmp156 <= 3U) {
    {
#line 387
    __cil_tmp157 = (unsigned char *)dev_priv;
#line 387
    __cil_tmp158 = __cil_tmp157 + 2072UL;
#line 387
    __cil_tmp159 = *__cil_tmp158;
#line 387
    __cil_tmp160 = (unsigned int )__cil_tmp159;
#line 387
    if (__cil_tmp160 != 0U) {
#line 388
      pfit_control = pfit_control | 8U;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 390
  __cil_tmp161 = intel_lvds->pfit_control;
#line 390
  if (__cil_tmp161 != pfit_control) {
#line 392
    intel_lvds->pfit_control = pfit_control;
#line 393
    intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
#line 394
    intel_lvds->pfit_dirty = (bool )1;
  } else {
    {
#line 390
    __cil_tmp162 = intel_lvds->pfit_pgm_ratios;
#line 390
    if (__cil_tmp162 != pfit_pgm_ratios) {
#line 392
      intel_lvds->pfit_control = pfit_control;
#line 393
      intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
#line 394
      intel_lvds->pfit_dirty = (bool )1;
    } else {

    }
    }
  }
  }
#line 396
  dev_priv->lvds_border_bits = border;
#line 404
  return ((bool )1);
}
}
#line 407 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_prepare(struct drm_encoder *encoder ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  void *__cil_tmp9 ;
  void *__cil_tmp10 ;
  struct drm_i915_private *__cil_tmp11 ;
  struct intel_device_info  const  *__cil_tmp12 ;
  u8 __cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  void *__cil_tmp17 ;
  struct drm_i915_private *__cil_tmp18 ;
  struct intel_device_info  const  *__cil_tmp19 ;
  u8 __cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  void *__cil_tmp24 ;
  struct drm_i915_private *__cil_tmp25 ;
  struct intel_device_info  const  *__cil_tmp26 ;
  unsigned char *__cil_tmp27 ;
  unsigned char *__cil_tmp28 ;
  unsigned char __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  bool __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;

  {
  {
#line 409
  dev = encoder->dev;
#line 410
  __cil_tmp9 = dev->dev_private;
#line 410
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 411
  tmp = to_intel_lvds(encoder);
#line 411
  intel_lvds = tmp;
  }
  {
#line 424
  __cil_tmp10 = dev->dev_private;
#line 424
  __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
#line 424
  __cil_tmp12 = __cil_tmp11->info;
#line 424
  __cil_tmp13 = __cil_tmp12->gen;
#line 424
  __cil_tmp14 = (unsigned char )__cil_tmp13;
#line 424
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 424
  if (__cil_tmp15 == 5U) {
    {
#line 425
    tmp___0 = i915_read32___8(dev_priv, 815620U);
#line 425
    __cil_tmp16 = tmp___0 | 2882338816U;
#line 425
    i915_write32___6(dev_priv, 815620U, __cil_tmp16);
    }
  } else {
    {
#line 424
    __cil_tmp17 = dev->dev_private;
#line 424
    __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
#line 424
    __cil_tmp19 = __cil_tmp18->info;
#line 424
    __cil_tmp20 = __cil_tmp19->gen;
#line 424
    __cil_tmp21 = (unsigned char )__cil_tmp20;
#line 424
    __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 424
    if (__cil_tmp22 == 6U) {
      {
#line 425
      tmp___0 = i915_read32___8(dev_priv, 815620U);
#line 425
      __cil_tmp23 = tmp___0 | 2882338816U;
#line 425
      i915_write32___6(dev_priv, 815620U, __cil_tmp23);
      }
    } else {
      {
#line 424
      __cil_tmp24 = dev->dev_private;
#line 424
      __cil_tmp25 = (struct drm_i915_private *)__cil_tmp24;
#line 424
      __cil_tmp26 = __cil_tmp25->info;
#line 424
      __cil_tmp27 = (unsigned char *)__cil_tmp26;
#line 424
      __cil_tmp28 = __cil_tmp27 + 2UL;
#line 424
      __cil_tmp29 = *__cil_tmp28;
#line 424
      __cil_tmp30 = (unsigned int )__cil_tmp29;
#line 424
      if (__cil_tmp30 != 0U) {
        {
#line 425
        tmp___0 = i915_read32___8(dev_priv, 815620U);
#line 425
        __cil_tmp31 = tmp___0 | 2882338816U;
#line 425
        i915_write32___6(dev_priv, 815620U, __cil_tmp31);
        }
      } else {
        {
#line 427
        __cil_tmp32 = intel_lvds->pfit_dirty;
#line 427
        if ((int )__cil_tmp32) {
          {
#line 428
          tmp___1 = i915_read32___8(dev_priv, 397828U);
#line 428
          __cil_tmp33 = tmp___1 & 1412628478U;
#line 428
          __cil_tmp34 = __cil_tmp33 | 2882338816U;
#line 428
          i915_write32___6(dev_priv, 397828U, __cil_tmp34);
          }
        } else {
          {
#line 432
          tmp___2 = i915_read32___8(dev_priv, 397828U);
#line 432
          __cil_tmp35 = tmp___2 | 2882338816U;
#line 432
          i915_write32___6(dev_priv, 397828U, __cil_tmp35);
          }
        }
        }
      }
      }
    }
    }
  }
  }
#line 433
  return;
}
}
#line 437 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_commit(struct drm_encoder *encoder ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;
  u32 val ;
  u32 tmp___0 ;
  u32 val___0 ;
  u32 tmp___1 ;
  void *__cil_tmp10 ;
  void *__cil_tmp11 ;
  struct drm_i915_private *__cil_tmp12 ;
  struct intel_device_info  const  *__cil_tmp13 ;
  u8 __cil_tmp14 ;
  unsigned char __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  void *__cil_tmp17 ;
  struct drm_i915_private *__cil_tmp18 ;
  struct intel_device_info  const  *__cil_tmp19 ;
  u8 __cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  unsigned char *__cil_tmp26 ;
  unsigned char *__cil_tmp27 ;
  unsigned char __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  unsigned int __cil_tmp33 ;

  {
  {
#line 439
  dev = encoder->dev;
#line 440
  __cil_tmp10 = dev->dev_private;
#line 440
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 441
  tmp = to_intel_lvds(encoder);
#line 441
  intel_lvds = tmp;
  }
  {
#line 446
  __cil_tmp11 = dev->dev_private;
#line 446
  __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
#line 446
  __cil_tmp13 = __cil_tmp12->info;
#line 446
  __cil_tmp14 = __cil_tmp13->gen;
#line 446
  __cil_tmp15 = (unsigned char )__cil_tmp14;
#line 446
  __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 446
  if (__cil_tmp16 == 5U) {
#line 446
    goto _L;
  } else {
    {
#line 446
    __cil_tmp17 = dev->dev_private;
#line 446
    __cil_tmp18 = (struct drm_i915_private *)__cil_tmp17;
#line 446
    __cil_tmp19 = __cil_tmp18->info;
#line 446
    __cil_tmp20 = __cil_tmp19->gen;
#line 446
    __cil_tmp21 = (unsigned char )__cil_tmp20;
#line 446
    __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 446
    if (__cil_tmp22 == 6U) {
#line 446
      goto _L;
    } else {
      {
#line 446
      __cil_tmp23 = dev->dev_private;
#line 446
      __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 446
      __cil_tmp25 = __cil_tmp24->info;
#line 446
      __cil_tmp26 = (unsigned char *)__cil_tmp25;
#line 446
      __cil_tmp27 = __cil_tmp26 + 2UL;
#line 446
      __cil_tmp28 = *__cil_tmp27;
#line 446
      __cil_tmp29 = (unsigned int )__cil_tmp28;
#line 446
      if (__cil_tmp29 != 0U) {
        _L: 
        {
#line 447
        tmp___0 = i915_read32___8(dev_priv, 815620U);
#line 447
        val = tmp___0;
        }
        {
#line 448
        __cil_tmp30 = val & 2882338816U;
#line 448
        if (__cil_tmp30 == 2882338816U) {
          {
#line 449
          __cil_tmp31 = val & 3U;
#line 449
          i915_write32___6(dev_priv, 815620U, __cil_tmp31);
          }
        } else {

        }
        }
      } else {
        {
#line 451
        tmp___1 = i915_read32___8(dev_priv, 397828U);
#line 451
        val___0 = tmp___1;
        }
        {
#line 452
        __cil_tmp32 = val___0 & 2882338816U;
#line 452
        if (__cil_tmp32 == 2882338816U) {
          {
#line 453
          __cil_tmp33 = val___0 & 3U;
#line 453
          i915_write32___6(dev_priv, 397828U, __cil_tmp33);
          }
        } else {

        }
        }
      }
      }
    }
    }
  }
  }
  {
#line 459
  intel_lvds_enable(intel_lvds);
  }
#line 460
  return;
}
}
#line 462 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                struct drm_display_mode *adjusted_mode ) 
{ 

  {
#line 464
  return;
}
}
#line 481 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector ,
                                                   bool force ) 
{ struct drm_device *dev ;
  enum drm_connector_status status ;
  unsigned int __cil_tmp5 ;

  {
  {
#line 483
  dev = connector->dev;
#line 486
  status = intel_panel_detect(dev);
  }
  {
#line 487
  __cil_tmp5 = (unsigned int )status;
#line 487
  if (__cil_tmp5 != 3U) {
#line 488
    return (status);
  } else {

  }
  }
#line 490
  return ((enum drm_connector_status )1);
}
}
#line 496 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static int intel_lvds_get_modes(struct drm_connector *connector ) 
{ struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;
  struct drm_device *dev ;
  struct drm_display_mode *mode ;
  int tmp___0 ;
  struct edid *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct edid *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct edid *__cil_tmp11 ;
  struct drm_display_mode *__cil_tmp12 ;
  struct drm_display_mode  const  *__cil_tmp13 ;
  struct drm_display_mode *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;

  {
  {
#line 498
  tmp = intel_attached_lvds(connector);
#line 498
  intel_lvds = tmp;
#line 499
  dev = connector->dev;
  }
  {
#line 502
  __cil_tmp7 = (struct edid *)0;
#line 502
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 502
  __cil_tmp9 = intel_lvds->edid;
#line 502
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 502
  if (__cil_tmp10 != __cil_tmp8) {
    {
#line 503
    __cil_tmp11 = intel_lvds->edid;
#line 503
    tmp___0 = drm_add_edid_modes(connector, __cil_tmp11);
    }
#line 503
    return (tmp___0);
  } else {

  }
  }
  {
#line 505
  __cil_tmp12 = intel_lvds->fixed_mode;
#line 505
  __cil_tmp13 = (struct drm_display_mode  const  *)__cil_tmp12;
#line 505
  mode = drm_mode_duplicate(dev, __cil_tmp13);
  }
  {
#line 506
  __cil_tmp14 = (struct drm_display_mode *)0;
#line 506
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 506
  __cil_tmp16 = (unsigned long )mode;
#line 506
  if (__cil_tmp16 == __cil_tmp15) {
#line 507
    return (0);
  } else {

  }
  }
  {
#line 509
  drm_mode_probed_add(connector, mode);
  }
#line 510
  return (1);
}
}
#line 513 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static int intel_no_modeset_on_lid_dmi_callback(struct dmi_system_id  const  *id ) 
{ char const   *__cil_tmp2 ;

  {
  {
#line 515
  __cil_tmp2 = id->ident;
#line 515
  drm_ut_debug_printk(4U, "drm", "intel_no_modeset_on_lid_dmi_callback", "Skipping forced modeset for %s\n",
                      __cil_tmp2);
  }
#line 516
  return (1);
}
}
#line 520 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct dmi_system_id  const  intel_no_modeset_on_lid[2U]  = {      {& intel_no_modeset_on_lid_dmi_callback, "Toshiba Tecra A11", {{(unsigned char)4,
                                                                     {(char )'T',
                                                                      (char )'O',
                                                                      (char )'S',
                                                                      (char )'H',
                                                                      (char )'I',
                                                                      (char )'B',
                                                                      (char )'A',
                                                                      (char )'\000'}},
                                                                    {(unsigned char)5,
                                                                     {(char )'T',
                                                                      (char )'E',
                                                                      (char )'C',
                                                                      (char )'R',
                                                                      (char )'A',
                                                                      (char )' ',
                                                                      (char )'A',
                                                                      (char )'1',
                                                                      (char )'1',
                                                                      (char )'\000'}},
                                                                    {(unsigned char)0,
                                                                     {(char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0, (char)0,
                                                                      (char)0}}, {(unsigned char)0,
                                                                                  {(char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0,
                                                                                   (char)0}}},
      (void *)0}, 
        {(int (*)(struct dmi_system_id  const  * ))0, (char const   *)0, {{(unsigned char)0,
                                                                        {(char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
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      (void *)0}};
#line 542 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static int intel_lid_notify(struct notifier_block *nb , unsigned long val , void *unused ) 
{ struct drm_i915_private *dev_priv ;
  struct notifier_block  const  *__mptr ;
  struct drm_device *dev ;
  struct drm_connector *connector ;
  int tmp ;
  int tmp___0 ;
  struct drm_i915_private *__cil_tmp10 ;
  int __cil_tmp11 ;
  struct drm_connector *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct drm_connector_funcs  const  *__cil_tmp15 ;
  enum drm_connector_status (*__cil_tmp16)(struct drm_connector * , bool  ) ;
  bool __cil_tmp17 ;
  struct dmi_system_id  const  *__cil_tmp18 ;
  bool __cil_tmp19 ;
  struct mutex *__cil_tmp20 ;
  struct mutex *__cil_tmp21 ;

  {
#line 546
  __mptr = (struct notifier_block  const  *)nb;
#line 546
  __cil_tmp10 = (struct drm_i915_private *)__mptr;
#line 546
  dev_priv = __cil_tmp10 + 1152921504606844856UL;
#line 547
  dev = dev_priv->dev;
#line 548
  connector = dev_priv->int_lvds_connector;
  {
#line 550
  __cil_tmp11 = dev->switch_power_state;
#line 550
  if (__cil_tmp11 != 0) {
#line 551
    return (1);
  } else {

  }
  }
  {
#line 557
  __cil_tmp12 = (struct drm_connector *)0;
#line 557
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 557
  __cil_tmp14 = (unsigned long )connector;
#line 557
  if (__cil_tmp14 != __cil_tmp13) {
    {
#line 558
    __cil_tmp15 = connector->funcs;
#line 558
    __cil_tmp16 = __cil_tmp15->detect;
#line 558
    __cil_tmp17 = (bool )0;
#line 558
    connector->status = (*__cil_tmp16)(connector, __cil_tmp17);
    }
  } else {

  }
  }
  {
#line 562
  __cil_tmp18 = (struct dmi_system_id  const  *)(& intel_no_modeset_on_lid);
#line 562
  tmp = dmi_check_system(__cil_tmp18);
  }
#line 562
  if (tmp != 0) {
#line 563
    return (1);
  } else {

  }
  {
#line 564
  tmp___0 = acpi_lid_open();
  }
#line 564
  if (tmp___0 == 0) {
#line 565
    dev_priv->modeset_on_lid = (bool )1;
#line 566
    return (1);
  } else {

  }
  {
#line 569
  __cil_tmp19 = dev_priv->modeset_on_lid;
#line 569
  if (! __cil_tmp19) {
#line 570
    return (1);
  } else {

  }
  }
  {
#line 572
  dev_priv->modeset_on_lid = (bool )0;
#line 574
  __cil_tmp20 = & dev->mode_config.mutex;
#line 574
  mutex_lock_nested(__cil_tmp20, 0U);
#line 575
  drm_helper_resume_force_mode(dev);
#line 576
  __cil_tmp21 = & dev->mode_config.mutex;
#line 576
  mutex_unlock(__cil_tmp21);
  }
#line 578
  return (1);
}
}
#line 588 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_lvds_destroy(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  void *__cil_tmp4 ;
  int (*__cil_tmp5)(struct notifier_block * , unsigned long  , void * ) ;
  unsigned long __cil_tmp6 ;
  int (*__cil_tmp7)(struct notifier_block * , unsigned long  , void * ) ;
  unsigned long __cil_tmp8 ;
  struct notifier_block *__cil_tmp9 ;
  void const   *__cil_tmp10 ;

  {
#line 590
  dev = connector->dev;
#line 591
  __cil_tmp4 = dev->dev_private;
#line 591
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
  {
#line 593
  __cil_tmp5 = (int (*)(struct notifier_block * , unsigned long  , void * ))0;
#line 593
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 593
  __cil_tmp7 = dev_priv->lid_notifier.notifier_call;
#line 593
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 593
  if (__cil_tmp8 != __cil_tmp6) {
    {
#line 594
    __cil_tmp9 = & dev_priv->lid_notifier;
#line 594
    acpi_lid_notifier_unregister(__cil_tmp9);
    }
  } else {

  }
  }
  {
#line 595
  drm_sysfs_connector_remove(connector);
#line 596
  drm_connector_cleanup(connector);
#line 597
  __cil_tmp10 = (void const   *)connector;
#line 597
  kfree(__cil_tmp10);
  }
#line 598
  return;
}
}
#line 600 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static int intel_lvds_set_property(struct drm_connector *connector , struct drm_property *property ,
                                   uint64_t value ) 
{ struct intel_lvds *intel_lvds ;
  struct intel_lvds *tmp ;
  struct drm_device *dev ;
  struct drm_crtc *crtc ;
  unsigned long __cil_tmp8 ;
  struct drm_property *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  int __cil_tmp11 ;
  uint64_t __cil_tmp12 ;
  struct drm_crtc *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  bool __cil_tmp16 ;
  struct drm_display_mode *__cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  struct drm_framebuffer *__cil_tmp20 ;

  {
  {
#line 604
  tmp = intel_attached_lvds(connector);
#line 604
  intel_lvds = tmp;
#line 605
  dev = connector->dev;
  }
  {
#line 607
  __cil_tmp8 = (unsigned long )property;
#line 607
  __cil_tmp9 = dev->mode_config.scaling_mode_property;
#line 607
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 607
  if (__cil_tmp10 == __cil_tmp8) {
#line 608
    crtc = intel_lvds->base.base.crtc;
#line 610
    if (value == 0ULL) {
      {
#line 611
      drm_ut_debug_printk(4U, "drm", "intel_lvds_set_property", "no scaling not supported\n");
      }
#line 612
      return (-22);
    } else {

    }
    {
#line 615
    __cil_tmp11 = intel_lvds->fitting_mode;
#line 615
    __cil_tmp12 = (uint64_t )__cil_tmp11;
#line 615
    if (__cil_tmp12 == value) {
#line 617
      return (0);
    } else {

    }
    }
#line 619
    intel_lvds->fitting_mode = (int )value;
    {
#line 620
    __cil_tmp13 = (struct drm_crtc *)0;
#line 620
    __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 620
    __cil_tmp15 = (unsigned long )crtc;
#line 620
    if (__cil_tmp15 != __cil_tmp14) {
      {
#line 620
      __cil_tmp16 = crtc->enabled;
#line 620
      if ((int )__cil_tmp16) {
        {
#line 625
        __cil_tmp17 = & crtc->mode;
#line 625
        __cil_tmp18 = crtc->x;
#line 625
        __cil_tmp19 = crtc->y;
#line 625
        __cil_tmp20 = crtc->fb;
#line 625
        drm_crtc_helper_set_mode(crtc, __cil_tmp17, __cil_tmp18, __cil_tmp19, __cil_tmp20);
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
#line 630
  return (0);
}
}
#line 633 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct drm_encoder_helper_funcs  const  intel_lvds_helper_funcs  = 
#line 633
     {& intel_lvds_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_lvds_mode_fixup, & intel_lvds_prepare, & intel_lvds_commit, & intel_lvds_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 641 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct drm_connector_helper_funcs  const  intel_lvds_connector_helper_funcs  =    {& intel_lvds_get_modes,
    & intel_lvds_mode_valid, & intel_best_encoder};
#line 647 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct drm_connector_funcs  const  intel_lvds_connector_funcs  = 
#line 647
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    (void (*)(struct drm_connector * ))0, & intel_lvds_detect, & drm_helper_probe_single_connector_modes,
    & intel_lvds_set_property, & intel_lvds_destroy, (void (*)(struct drm_connector * ))0};
#line 655 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct drm_encoder_funcs  const  intel_lvds_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_encoder_destroy};
#line 659 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static int intel_no_lvds_dmi_callback(struct dmi_system_id  const  *id ) 
{ char const   *__cil_tmp2 ;

  {
  {
#line 661
  __cil_tmp2 = id->ident;
#line 661
  drm_ut_debug_printk(4U, "drm", "intel_no_lvds_dmi_callback", "Skipping LVDS initialization for %s\n",
                      __cil_tmp2);
  }
#line 662
  return (1);
}
}
#line 666 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static struct dmi_system_id  const  intel_no_lvds[11U]  = 
#line 666
  {      {& intel_no_lvds_dmi_callback, "Apple Mac Mini (Core series)", {{(unsigned char)4,
                                                                      {(char )'A',
                                                                       (char )'p',
                                                                       (char )'p',
                                                                       (char )'l',
                                                                       (char )'e',
                                                                       (char )'\000'}},
                                                                     {(unsigned char)5,
                                                                      {(char )'M',
                                                                       (char )'a',
                                                                       (char )'c',
                                                                       (char )'m',
                                                                       (char )'i',
                                                                       (char )'n',
                                                                       (char )'i',
                                                                       (char )'1',
                                                                       (char )',',
                                                                       (char )'1',
                                                                       (char )'\000'}},
                                                                     {(unsigned char)0,
                                                                      {(char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0}},
                                                                     {(unsigned char)0,
                                                                      {(char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0, (char)0,
                                                                       (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "Apple Mac Mini (Core 2 series)", {{(unsigned char)4,
                                                                        {(char )'A',
                                                                         (char )'p',
                                                                         (char )'p',
                                                                         (char )'l',
                                                                         (char )'e',
                                                                         (char )'\000'}},
                                                                       {(unsigned char)5,
                                                                        {(char )'M',
                                                                         (char )'a',
                                                                         (char )'c',
                                                                         (char )'m',
                                                                         (char )'i',
                                                                         (char )'n',
                                                                         (char )'i',
                                                                         (char )'2',
                                                                         (char )',',
                                                                         (char )'1',
                                                                         (char )'\000'}},
                                                                       {(unsigned char)0,
                                                                        {(char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0}},
                                                                       {(unsigned char)0,
                                                                        {(char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0,
                                                                         (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "MSI IM-945GSE-A", {{(unsigned char)4, {(char )'M',
                                                                            (char )'S',
                                                                            (char )'I',
                                                                            (char )'\000'}},
                                                        {(unsigned char)5, {(char )'A',
                                                                            (char )'9',
                                                                            (char )'8',
                                                                            (char )'3',
                                                                            (char )'0',
                                                                            (char )'I',
                                                                            (char )'M',
                                                                            (char )'S',
                                                                            (char )'\000'}},
                                                        {(unsigned char)0, {(char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0}},
                                                        {(unsigned char)0, {(char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0,
                                                                            (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "Dell Studio Hybrid", {{(unsigned char)4, {(char )'D',
                                                                               (char )'e',
                                                                               (char )'l',
                                                                               (char )'l',
                                                                               (char )' ',
                                                                               (char )'I',
                                                                               (char )'n',
                                                                               (char )'c',
                                                                               (char )'.',
                                                                               (char )'\000'}},
                                                           {(unsigned char)5, {(char )'S',
                                                                               (char )'t',
                                                                               (char )'u',
                                                                               (char )'d',
                                                                               (char )'i',
                                                                               (char )'o',
                                                                               (char )' ',
                                                                               (char )'H',
                                                                               (char )'y',
                                                                               (char )'b',
                                                                               (char )'r',
                                                                               (char )'i',
                                                                               (char )'d',
                                                                               (char )' ',
                                                                               (char )'1',
                                                                               (char )'4',
                                                                               (char )'0',
                                                                               (char )'g',
                                                                               (char )'\000'}},
                                                           {(unsigned char)0, {(char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0}},
                                                           {(unsigned char)0, {(char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0,
                                                                               (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "AOpen Mini PC", {{(unsigned char)4, {(char )'A',
                                                                          (char )'O',
                                                                          (char )'p',
                                                                          (char )'e',
                                                                          (char )'n',
                                                                          (char )'\000'}},
                                                      {(unsigned char)5, {(char )'i',
                                                                          (char )'9',
                                                                          (char )'6',
                                                                          (char )'5',
                                                                          (char )'G',
                                                                          (char )'M',
                                                                          (char )'x',
                                                                          (char )'-',
                                                                          (char )'I',
                                                                          (char )'F',
                                                                          (char )'\000'}},
                                                      {(unsigned char)0, {(char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0}},
                                                      {(unsigned char)0, {(char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0,
                                                                          (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "AOpen Mini PC MP915", {{(unsigned char)9, {(char )'A',
                                                                                (char )'O',
                                                                                (char )'p',
                                                                                (char )'e',
                                                                                (char )'n',
                                                                                (char )'\000'}},
                                                            {(unsigned char)10, {(char )'i',
                                                                                 (char )'9',
                                                                                 (char )'1',
                                                                                 (char )'5',
                                                                                 (char )'G',
                                                                                 (char )'M',
                                                                                 (char )'x',
                                                                                 (char )'-',
                                                                                 (char )'F',
                                                                                 (char )'\000'}},
                                                            {(unsigned char)0, {(char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0}},
                                                            {(unsigned char)0, {(char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0,
                                                                                (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "AOpen i915GMm-HFS", {{(unsigned char)9, {(char )'A',
                                                                              (char )'O',
                                                                              (char )'p',
                                                                              (char )'e',
                                                                              (char )'n',
                                                                              (char )'\000'}},
                                                          {(unsigned char)10, {(char )'i',
                                                                               (char )'9',
                                                                               (char )'1',
                                                                               (char )'5',
                                                                               (char )'G',
                                                                               (char )'M',
                                                                               (char )'m',
                                                                               (char )'-',
                                                                               (char )'H',
                                                                               (char )'F',
                                                                               (char )'S',
                                                                               (char )'\000'}},
                                                          {(unsigned char)0, {(char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0}},
                                                          {(unsigned char)0, {(char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "Aopen i945GTt-VFA", {{(unsigned char)6, {(char )'A',
                                                                              (char )'O',
                                                                              (char )'0',
                                                                              (char )'0',
                                                                              (char )'0',
                                                                              (char )'0',
                                                                              (char )'1',
                                                                              (char )'J',
                                                                              (char )'W',
                                                                              (char )'\000'}},
                                                          {(unsigned char)0, {(char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0}},
                                                          {(unsigned char)0, {(char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0}},
                                                          {(unsigned char)0, {(char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0,
                                                                              (char)0}}},
      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "Clientron U800", {{(unsigned char)4, {(char )'C',
                                                                           (char )'l',
                                                                           (char )'i',
                                                                           (char )'e',
                                                                           (char )'n',
                                                                           (char )'t',
                                                                           (char )'r',
                                                                           (char )'o',
                                                                           (char )'n',
                                                                           (char )'\000'}},
                                                       {(unsigned char)5, {(char )'U',
                                                                           (char )'8',
                                                                           (char )'0',
                                                                           (char )'0',
                                                                           (char )'\000'}},
                                                       {(unsigned char)0, {(char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
                                                                           (char)0,
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      (void *)0}, 
        {& intel_no_lvds_dmi_callback, "Asus EeeBox PC EB1007", {{(unsigned char)4, {(char )'A',
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                                                                                  (char )'e',
                                                                                  (char )'r',
                                                                                  (char )' ',
                                                                                  (char )'I',
                                                                                  (char )'N',
                                                                                  (char )'C',
                                                                                  (char )'.',
                                                                                  (char )'\000'}},
                                                              {(unsigned char)5, {(char )'E',
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                                                                                  (char )'1',
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                                                                                  (char )'\000'}},
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      (void *)0}};
#line 757 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static void intel_find_lvds_downclock(struct drm_device *dev , struct drm_display_mode *fixed_mode ,
                                      struct drm_connector *connector ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_display_mode *scan ;
  int temp_downclock ;
  struct list_head  const  *__mptr ;
  struct list_head  const  *__mptr___0 ;
  void *__cil_tmp9 ;
  struct list_head *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  struct list_head *__cil_tmp28 ;
  struct list_head *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  struct list_head *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;

  {
#line 761
  __cil_tmp9 = dev->dev_private;
#line 761
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 765
  temp_downclock = fixed_mode->clock;
#line 766
  __cil_tmp10 = connector->probed_modes.next;
#line 766
  __mptr = (struct list_head  const  *)__cil_tmp10;
#line 766
  scan = (struct drm_display_mode *)__mptr;
#line 766
  goto ldv_40358;
  ldv_40357: ;
  {
#line 774
  __cil_tmp11 = fixed_mode->hdisplay;
#line 774
  __cil_tmp12 = scan->hdisplay;
#line 774
  if (__cil_tmp12 == __cil_tmp11) {
    {
#line 774
    __cil_tmp13 = fixed_mode->hsync_start;
#line 774
    __cil_tmp14 = scan->hsync_start;
#line 774
    if (__cil_tmp14 == __cil_tmp13) {
      {
#line 774
      __cil_tmp15 = fixed_mode->hsync_end;
#line 774
      __cil_tmp16 = scan->hsync_end;
#line 774
      if (__cil_tmp16 == __cil_tmp15) {
        {
#line 774
        __cil_tmp17 = fixed_mode->htotal;
#line 774
        __cil_tmp18 = scan->htotal;
#line 774
        if (__cil_tmp18 == __cil_tmp17) {
          {
#line 774
          __cil_tmp19 = fixed_mode->vdisplay;
#line 774
          __cil_tmp20 = scan->vdisplay;
#line 774
          if (__cil_tmp20 == __cil_tmp19) {
            {
#line 774
            __cil_tmp21 = fixed_mode->vsync_start;
#line 774
            __cil_tmp22 = scan->vsync_start;
#line 774
            if (__cil_tmp22 == __cil_tmp21) {
              {
#line 774
              __cil_tmp23 = fixed_mode->vsync_end;
#line 774
              __cil_tmp24 = scan->vsync_end;
#line 774
              if (__cil_tmp24 == __cil_tmp23) {
                {
#line 774
                __cil_tmp25 = fixed_mode->vtotal;
#line 774
                __cil_tmp26 = scan->vtotal;
#line 774
                if (__cil_tmp26 == __cil_tmp25) {
                  {
#line 782
                  __cil_tmp27 = scan->clock;
#line 782
                  if (__cil_tmp27 < temp_downclock) {
#line 787
                    temp_downclock = scan->clock;
                  } else {

                  }
                  }
                } else {

                }
                }
              } else {

              }
              }
            } else {

            }
            }
          } else {

          }
          }
        } else {

        }
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
#line 766
  __cil_tmp28 = scan->head.next;
#line 766
  __mptr___0 = (struct list_head  const  *)__cil_tmp28;
#line 766
  scan = (struct drm_display_mode *)__mptr___0;
  ldv_40358: ;
  {
#line 766
  __cil_tmp29 = & connector->probed_modes;
#line 766
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 766
  __cil_tmp31 = & scan->head;
#line 766
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 766
  if (__cil_tmp32 != __cil_tmp30) {
#line 767
    goto ldv_40357;
  } else {
#line 769
    goto ldv_40359;
  }
  }
  ldv_40359: ;
  {
#line 791
  __cil_tmp33 = fixed_mode->clock;
#line 791
  if (__cil_tmp33 > temp_downclock) {
#line 791
    if (i915_lvds_downclock != 0U) {
      {
#line 793
      dev_priv->lvds_downclock_avail = (bool )1;
#line 794
      dev_priv->lvds_downclock = temp_downclock;
#line 795
      __cil_tmp34 = fixed_mode->clock;
#line 795
      drm_ut_debug_printk(4U, "drm", "intel_find_lvds_downclock", "LVDS downclock is found in EDID. Normal clock %dKhz, downclock %dKhz\n",
                          __cil_tmp34, temp_downclock);
      }
    } else {

    }
  } else {

  }
  }
#line 797
  return;
}
}
#line 808 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
static bool lvds_is_present_in_vbt(struct drm_device *dev , u8 *i2c_pin ) 
{ struct drm_i915_private *dev_priv ;
  int i ;
  struct child_device_config *child ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct child_device_config *__cil_tmp9 ;
  u16 __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  u16 __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  u8 __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  u16 __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  void *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  void *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  int __cil_tmp22 ;

  {
#line 811
  __cil_tmp6 = dev->dev_private;
#line 811
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
  {
#line 814
  __cil_tmp7 = dev_priv->child_dev_num;
#line 814
  if (__cil_tmp7 == 0) {
#line 815
    return ((bool )1);
  } else {

  }
  }
#line 817
  i = 0;
#line 817
  goto ldv_40370;
  ldv_40369: 
#line 818
  __cil_tmp8 = (unsigned long )i;
#line 818
  __cil_tmp9 = dev_priv->child_dev;
#line 818
  child = __cil_tmp9 + __cil_tmp8;
  {
#line 824
  __cil_tmp10 = child->device_type;
#line 824
  __cil_tmp11 = (unsigned int )__cil_tmp10;
#line 824
  if (__cil_tmp11 != 4130U) {
    {
#line 824
    __cil_tmp12 = child->device_type;
#line 824
    __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 824
    if (__cil_tmp13 != 34U) {
#line 826
      goto ldv_40368;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 828
  __cil_tmp14 = child->i2c_pin;
#line 828
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 828
  if (__cil_tmp15 != 0U) {
#line 829
    *i2c_pin = child->i2c_pin;
  } else {

  }
  }
  {
#line 836
  __cil_tmp16 = child->addin_offset;
#line 836
  __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 836
  if (__cil_tmp17 != 0U) {
#line 837
    return ((bool )1);
  } else {

  }
  }
  {
#line 844
  __cil_tmp18 = (void *)0;
#line 844
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 844
  __cil_tmp20 = dev_priv->opregion.vbt;
#line 844
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 844
  if (__cil_tmp21 != __cil_tmp19) {
#line 845
    return ((bool )1);
  } else {

  }
  }
  ldv_40368: 
#line 817
  i = i + 1;
  ldv_40370: ;
  {
#line 817
  __cil_tmp22 = dev_priv->child_dev_num;
#line 817
  if (__cil_tmp22 > i) {
#line 818
    goto ldv_40369;
  } else {
#line 820
    goto ldv_40371;
  }
  }
  ldv_40371: ;
#line 848
  return ((bool )0);
}
}
#line 858 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_lvds.c.p"
bool intel_lvds_init(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_lvds *intel_lvds ;
  struct intel_encoder *intel_encoder ;
  struct intel_connector *intel_connector ;
  struct drm_connector *connector ;
  struct drm_encoder *encoder ;
  struct drm_display_mode *scan ;
  struct drm_crtc *crtc ;
  u32 lvds ;
  int pipe ;
  u8 pin ;
  int tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  u32 tmp___2 ;
  void *tmp___3 ;
  void *tmp___4 ;
  int tmp___5 ;
  struct list_head  const  *__mptr ;
  struct list_head  const  *__mptr___0 ;
  u32 pwm ;
  u32 tmp___6 ;
  int tmp___7 ;
  void *__cil_tmp25 ;
  struct dmi_system_id  const  *__cil_tmp26 ;
  void *__cil_tmp27 ;
  struct drm_i915_private *__cil_tmp28 ;
  struct intel_device_info  const  *__cil_tmp29 ;
  u8 __cil_tmp30 ;
  unsigned char __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  void *__cil_tmp33 ;
  struct drm_i915_private *__cil_tmp34 ;
  struct intel_device_info  const  *__cil_tmp35 ;
  u8 __cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  void *__cil_tmp39 ;
  struct drm_i915_private *__cil_tmp40 ;
  struct intel_device_info  const  *__cil_tmp41 ;
  unsigned char *__cil_tmp42 ;
  unsigned char *__cil_tmp43 ;
  unsigned char __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  bool __cil_tmp47 ;
  struct intel_lvds *__cil_tmp48 ;
  unsigned long __cil_tmp49 ;
  unsigned long __cil_tmp50 ;
  struct intel_connector *__cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  unsigned long __cil_tmp53 ;
  void const   *__cil_tmp54 ;
  void *__cil_tmp55 ;
  struct drm_i915_private *__cil_tmp56 ;
  struct intel_device_info  const  *__cil_tmp57 ;
  u8 __cil_tmp58 ;
  unsigned char __cil_tmp59 ;
  unsigned int __cil_tmp60 ;
  void *__cil_tmp61 ;
  struct drm_i915_private *__cil_tmp62 ;
  struct intel_device_info  const  *__cil_tmp63 ;
  u8 __cil_tmp64 ;
  unsigned char __cil_tmp65 ;
  unsigned int __cil_tmp66 ;
  void *__cil_tmp67 ;
  struct drm_i915_private *__cil_tmp68 ;
  struct intel_device_info  const  *__cil_tmp69 ;
  unsigned char *__cil_tmp70 ;
  unsigned char *__cil_tmp71 ;
  unsigned char __cil_tmp72 ;
  unsigned int __cil_tmp73 ;
  struct drm_connector *__cil_tmp74 ;
  struct drm_encoder *__cil_tmp75 ;
  void *__cil_tmp76 ;
  struct drm_i915_private *__cil_tmp77 ;
  struct intel_device_info  const  *__cil_tmp78 ;
  u8 __cil_tmp79 ;
  unsigned char __cil_tmp80 ;
  unsigned int __cil_tmp81 ;
  int __cil_tmp82 ;
  struct drm_connector *__cil_tmp83 ;
  struct drm_property *__cil_tmp84 ;
  unsigned long __cil_tmp85 ;
  struct intel_gmbus *__cil_tmp86 ;
  struct intel_gmbus *__cil_tmp87 ;
  struct i2c_adapter *__cil_tmp88 ;
  struct edid *__cil_tmp89 ;
  unsigned long __cil_tmp90 ;
  struct edid *__cil_tmp91 ;
  unsigned long __cil_tmp92 ;
  struct edid *__cil_tmp93 ;
  struct edid *__cil_tmp94 ;
  struct edid *__cil_tmp95 ;
  void const   *__cil_tmp96 ;
  struct edid *__cil_tmp97 ;
  unsigned long __cil_tmp98 ;
  struct edid *__cil_tmp99 ;
  unsigned long __cil_tmp100 ;
  struct list_head *__cil_tmp101 ;
  int __cil_tmp102 ;
  int __cil_tmp103 ;
  struct drm_display_mode  const  *__cil_tmp104 ;
  struct drm_display_mode *__cil_tmp105 ;
  struct list_head *__cil_tmp106 ;
  struct list_head *__cil_tmp107 ;
  unsigned long __cil_tmp108 ;
  struct list_head *__cil_tmp109 ;
  unsigned long __cil_tmp110 ;
  struct drm_display_mode *__cil_tmp111 ;
  unsigned long __cil_tmp112 ;
  struct drm_display_mode *__cil_tmp113 ;
  unsigned long __cil_tmp114 ;
  struct drm_display_mode *__cil_tmp115 ;
  struct drm_display_mode  const  *__cil_tmp116 ;
  struct drm_display_mode *__cil_tmp117 ;
  unsigned long __cil_tmp118 ;
  struct drm_display_mode *__cil_tmp119 ;
  unsigned long __cil_tmp120 ;
  struct drm_display_mode *__cil_tmp121 ;
  struct drm_display_mode *__cil_tmp122 ;
  int __cil_tmp123 ;
  void *__cil_tmp124 ;
  struct drm_i915_private *__cil_tmp125 ;
  struct intel_device_info  const  *__cil_tmp126 ;
  u8 __cil_tmp127 ;
  unsigned char __cil_tmp128 ;
  unsigned int __cil_tmp129 ;
  void *__cil_tmp130 ;
  struct drm_i915_private *__cil_tmp131 ;
  struct intel_device_info  const  *__cil_tmp132 ;
  u8 __cil_tmp133 ;
  unsigned char __cil_tmp134 ;
  unsigned int __cil_tmp135 ;
  void *__cil_tmp136 ;
  struct drm_i915_private *__cil_tmp137 ;
  struct intel_device_info  const  *__cil_tmp138 ;
  unsigned char *__cil_tmp139 ;
  unsigned char *__cil_tmp140 ;
  unsigned char __cil_tmp141 ;
  unsigned int __cil_tmp142 ;
  unsigned int __cil_tmp143 ;
  struct drm_crtc *__cil_tmp144 ;
  unsigned long __cil_tmp145 ;
  unsigned long __cil_tmp146 ;
  int __cil_tmp147 ;
  struct drm_display_mode *__cil_tmp148 ;
  unsigned long __cil_tmp149 ;
  struct drm_display_mode *__cil_tmp150 ;
  unsigned long __cil_tmp151 ;
  struct drm_display_mode *__cil_tmp152 ;
  struct drm_display_mode *__cil_tmp153 ;
  int __cil_tmp154 ;
  struct drm_display_mode *__cil_tmp155 ;
  unsigned long __cil_tmp156 ;
  struct drm_display_mode *__cil_tmp157 ;
  unsigned long __cil_tmp158 ;
  void *__cil_tmp159 ;
  struct drm_i915_private *__cil_tmp160 ;
  struct intel_device_info  const  *__cil_tmp161 ;
  u8 __cil_tmp162 ;
  unsigned char __cil_tmp163 ;
  unsigned int __cil_tmp164 ;
  void *__cil_tmp165 ;
  struct drm_i915_private *__cil_tmp166 ;
  struct intel_device_info  const  *__cil_tmp167 ;
  u8 __cil_tmp168 ;
  unsigned char __cil_tmp169 ;
  unsigned int __cil_tmp170 ;
  void *__cil_tmp171 ;
  struct drm_i915_private *__cil_tmp172 ;
  struct intel_device_info  const  *__cil_tmp173 ;
  unsigned char *__cil_tmp174 ;
  unsigned char *__cil_tmp175 ;
  unsigned char __cil_tmp176 ;
  unsigned int __cil_tmp177 ;
  unsigned int __cil_tmp178 ;
  unsigned int __cil_tmp179 ;
  unsigned int __cil_tmp180 ;
  unsigned int __cil_tmp181 ;
  struct notifier_block *__cil_tmp182 ;
  void const   *__cil_tmp183 ;
  void const   *__cil_tmp184 ;

  {
  {
#line 860
  __cil_tmp25 = dev->dev_private;
#line 860
  dev_priv = (struct drm_i915_private *)__cil_tmp25;
#line 873
  __cil_tmp26 = (struct dmi_system_id  const  *)(& intel_no_lvds);
#line 873
  tmp = dmi_check_system(__cil_tmp26);
  }
#line 873
  if (tmp != 0) {
#line 874
    return ((bool )0);
  } else {

  }
  {
#line 876
  pin = (u8 )3U;
#line 877
  tmp___0 = lvds_is_present_in_vbt(dev, & pin);
  }
#line 877
  if (tmp___0) {
#line 877
    tmp___1 = 0;
  } else {
#line 877
    tmp___1 = 1;
  }
#line 877
  if (tmp___1) {
    {
#line 878
    drm_ut_debug_printk(4U, "drm", "intel_lvds_init", "LVDS is not present in VBT\n");
    }
#line 879
    return ((bool )0);
  } else {

  }
  {
#line 882
  __cil_tmp27 = dev->dev_private;
#line 882
  __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
#line 882
  __cil_tmp29 = __cil_tmp28->info;
#line 882
  __cil_tmp30 = __cil_tmp29->gen;
#line 882
  __cil_tmp31 = (unsigned char )__cil_tmp30;
#line 882
  __cil_tmp32 = (unsigned int )__cil_tmp31;
#line 882
  if (__cil_tmp32 == 5U) {
#line 882
    goto _L;
  } else {
    {
#line 882
    __cil_tmp33 = dev->dev_private;
#line 882
    __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
#line 882
    __cil_tmp35 = __cil_tmp34->info;
#line 882
    __cil_tmp36 = __cil_tmp35->gen;
#line 882
    __cil_tmp37 = (unsigned char )__cil_tmp36;
#line 882
    __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 882
    if (__cil_tmp38 == 6U) {
#line 882
      goto _L;
    } else {
      {
#line 882
      __cil_tmp39 = dev->dev_private;
#line 882
      __cil_tmp40 = (struct drm_i915_private *)__cil_tmp39;
#line 882
      __cil_tmp41 = __cil_tmp40->info;
#line 882
      __cil_tmp42 = (unsigned char *)__cil_tmp41;
#line 882
      __cil_tmp43 = __cil_tmp42 + 2UL;
#line 882
      __cil_tmp44 = *__cil_tmp43;
#line 882
      __cil_tmp45 = (unsigned int )__cil_tmp44;
#line 882
      if (__cil_tmp45 != 0U) {
        _L: 
        {
#line 883
        tmp___2 = i915_read32___8(dev_priv, 921984U);
        }
        {
#line 883
        __cil_tmp46 = tmp___2 & 2U;
#line 883
        if (__cil_tmp46 == 0U) {
#line 884
          return ((bool )0);
        } else {

        }
        }
        {
#line 885
        __cil_tmp47 = dev_priv->edp.support;
#line 885
        if ((int )__cil_tmp47) {
          {
#line 886
          drm_ut_debug_printk(4U, "drm", "intel_lvds_init", "disable LVDS for eDP support\n");
          }
#line 887
          return ((bool )0);
        } else {

        }
        }
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 891
  tmp___3 = kzalloc(128UL, 208U);
#line 891
  intel_lvds = (struct intel_lvds *)tmp___3;
  }
  {
#line 892
  __cil_tmp48 = (struct intel_lvds *)0;
#line 892
  __cil_tmp49 = (unsigned long )__cil_tmp48;
#line 892
  __cil_tmp50 = (unsigned long )intel_lvds;
#line 892
  if (__cil_tmp50 == __cil_tmp49) {
#line 893
    return ((bool )0);
  } else {

  }
  }
  {
#line 896
  tmp___4 = kzalloc(1576UL, 208U);
#line 896
  intel_connector = (struct intel_connector *)tmp___4;
  }
  {
#line 897
  __cil_tmp51 = (struct intel_connector *)0;
#line 897
  __cil_tmp52 = (unsigned long )__cil_tmp51;
#line 897
  __cil_tmp53 = (unsigned long )intel_connector;
#line 897
  if (__cil_tmp53 == __cil_tmp52) {
    {
#line 898
    __cil_tmp54 = (void const   *)intel_lvds;
#line 898
    kfree(__cil_tmp54);
    }
#line 899
    return ((bool )0);
  } else {

  }
  }
  {
#line 902
  __cil_tmp55 = dev->dev_private;
#line 902
  __cil_tmp56 = (struct drm_i915_private *)__cil_tmp55;
#line 902
  __cil_tmp57 = __cil_tmp56->info;
#line 902
  __cil_tmp58 = __cil_tmp57->gen;
#line 902
  __cil_tmp59 = (unsigned char )__cil_tmp58;
#line 902
  __cil_tmp60 = (unsigned int )__cil_tmp59;
#line 902
  if (__cil_tmp60 != 5U) {
    {
#line 902
    __cil_tmp61 = dev->dev_private;
#line 902
    __cil_tmp62 = (struct drm_i915_private *)__cil_tmp61;
#line 902
    __cil_tmp63 = __cil_tmp62->info;
#line 902
    __cil_tmp64 = __cil_tmp63->gen;
#line 902
    __cil_tmp65 = (unsigned char )__cil_tmp64;
#line 902
    __cil_tmp66 = (unsigned int )__cil_tmp65;
#line 902
    if (__cil_tmp66 != 6U) {
      {
#line 902
      __cil_tmp67 = dev->dev_private;
#line 902
      __cil_tmp68 = (struct drm_i915_private *)__cil_tmp67;
#line 902
      __cil_tmp69 = __cil_tmp68->info;
#line 902
      __cil_tmp70 = (unsigned char *)__cil_tmp69;
#line 902
      __cil_tmp71 = __cil_tmp70 + 2UL;
#line 902
      __cil_tmp72 = *__cil_tmp71;
#line 902
      __cil_tmp73 = (unsigned int )__cil_tmp72;
#line 902
      if (__cil_tmp73 == 0U) {
        {
#line 903
        intel_lvds->pfit_control = i915_read32___8(dev_priv, 397872U);
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 906
  intel_encoder = & intel_lvds->base;
#line 907
  encoder = & intel_encoder->base;
#line 908
  connector = & intel_connector->base;
#line 909
  __cil_tmp74 = & intel_connector->base;
#line 909
  drm_connector_init(dev, __cil_tmp74, & intel_lvds_connector_funcs, 7);
#line 912
  __cil_tmp75 = & intel_encoder->base;
#line 912
  drm_encoder_init(dev, __cil_tmp75, & intel_lvds_enc_funcs, 3);
#line 915
  intel_connector_attach_encoder(intel_connector, intel_encoder);
#line 916
  intel_encoder->type = 4;
#line 918
  intel_encoder->clone_mask = 16384;
#line 919
  intel_encoder->crtc_mask = 2;
  }
  {
#line 920
  __cil_tmp76 = dev->dev_private;
#line 920
  __cil_tmp77 = (struct drm_i915_private *)__cil_tmp76;
#line 920
  __cil_tmp78 = __cil_tmp77->info;
#line 920
  __cil_tmp79 = __cil_tmp78->gen;
#line 920
  __cil_tmp80 = (unsigned char )__cil_tmp79;
#line 920
  __cil_tmp81 = (unsigned int )__cil_tmp80;
#line 920
  if (__cil_tmp81 > 4U) {
#line 921
    __cil_tmp82 = intel_encoder->crtc_mask;
#line 921
    intel_encoder->crtc_mask = __cil_tmp82 | 1;
  } else {

  }
  }
  {
#line 922
  drm_encoder_helper_add(encoder, & intel_lvds_helper_funcs);
#line 923
  drm_connector_helper_add(connector, & intel_lvds_connector_helper_funcs);
#line 924
  connector->display_info.subpixel_order = (enum subpixel_order )1;
#line 925
  connector->interlace_allowed = (bool )0;
#line 926
  connector->doublescan_allowed = (bool )0;
#line 929
  drm_mode_create_scaling_mode_property(dev);
#line 934
  __cil_tmp83 = & intel_connector->base;
#line 934
  __cil_tmp84 = dev->mode_config.scaling_mode_property;
#line 934
  drm_connector_attach_property(__cil_tmp83, __cil_tmp84, 3ULL);
#line 937
  intel_lvds->fitting_mode = 3;
#line 952
  __cil_tmp85 = (unsigned long )pin;
#line 952
  __cil_tmp86 = dev_priv->gmbus;
#line 952
  __cil_tmp87 = __cil_tmp86 + __cil_tmp85;
#line 952
  __cil_tmp88 = & __cil_tmp87->adapter;
#line 952
  intel_lvds->edid = drm_get_edid(connector, __cil_tmp88);
  }
  {
#line 954
  __cil_tmp89 = (struct edid *)0;
#line 954
  __cil_tmp90 = (unsigned long )__cil_tmp89;
#line 954
  __cil_tmp91 = intel_lvds->edid;
#line 954
  __cil_tmp92 = (unsigned long )__cil_tmp91;
#line 954
  if (__cil_tmp92 != __cil_tmp90) {
    {
#line 955
    __cil_tmp93 = intel_lvds->edid;
#line 955
    tmp___5 = drm_add_edid_modes(connector, __cil_tmp93);
    }
#line 955
    if (tmp___5 != 0) {
      {
#line 957
      __cil_tmp94 = intel_lvds->edid;
#line 957
      drm_mode_connector_update_edid_property(connector, __cil_tmp94);
      }
    } else {
      {
#line 960
      __cil_tmp95 = intel_lvds->edid;
#line 960
      __cil_tmp96 = (void const   *)__cil_tmp95;
#line 960
      kfree(__cil_tmp96);
#line 961
      intel_lvds->edid = (struct edid *)0;
      }
    }
  } else {

  }
  }
  {
#line 964
  __cil_tmp97 = (struct edid *)0;
#line 964
  __cil_tmp98 = (unsigned long )__cil_tmp97;
#line 964
  __cil_tmp99 = intel_lvds->edid;
#line 964
  __cil_tmp100 = (unsigned long )__cil_tmp99;
#line 964
  if (__cil_tmp100 == __cil_tmp98) {
#line 969
    connector->display_info.min_vfreq = 0U;
#line 970
    connector->display_info.max_vfreq = 200U;
#line 971
    connector->display_info.min_hfreq = 0U;
#line 972
    connector->display_info.max_hfreq = 200U;
  } else {

  }
  }
#line 975
  __cil_tmp101 = connector->probed_modes.next;
#line 975
  __mptr = (struct list_head  const  *)__cil_tmp101;
#line 975
  scan = (struct drm_display_mode *)__mptr;
#line 975
  goto ldv_40393;
  ldv_40392: ;
  {
#line 976
  __cil_tmp102 = scan->type;
#line 976
  __cil_tmp103 = __cil_tmp102 & 8;
#line 976
  if (__cil_tmp103 != 0) {
    {
#line 977
    __cil_tmp104 = (struct drm_display_mode  const  *)scan;
#line 977
    intel_lvds->fixed_mode = drm_mode_duplicate(dev, __cil_tmp104);
#line 979
    __cil_tmp105 = intel_lvds->fixed_mode;
#line 979
    intel_find_lvds_downclock(dev, __cil_tmp105, connector);
    }
#line 982
    goto out;
  } else {

  }
  }
#line 975
  __cil_tmp106 = scan->head.next;
#line 975
  __mptr___0 = (struct list_head  const  *)__cil_tmp106;
#line 975
  scan = (struct drm_display_mode *)__mptr___0;
  ldv_40393: ;
  {
#line 975
  __cil_tmp107 = & connector->probed_modes;
#line 975
  __cil_tmp108 = (unsigned long )__cil_tmp107;
#line 975
  __cil_tmp109 = & scan->head;
#line 975
  __cil_tmp110 = (unsigned long )__cil_tmp109;
#line 975
  if (__cil_tmp110 != __cil_tmp108) {
#line 976
    goto ldv_40392;
  } else {
#line 978
    goto ldv_40394;
  }
  }
  ldv_40394: ;
  {
#line 987
  __cil_tmp111 = (struct drm_display_mode *)0;
#line 987
  __cil_tmp112 = (unsigned long )__cil_tmp111;
#line 987
  __cil_tmp113 = dev_priv->lfp_lvds_vbt_mode;
#line 987
  __cil_tmp114 = (unsigned long )__cil_tmp113;
#line 987
  if (__cil_tmp114 != __cil_tmp112) {
    {
#line 988
    __cil_tmp115 = dev_priv->lfp_lvds_vbt_mode;
#line 988
    __cil_tmp116 = (struct drm_display_mode  const  *)__cil_tmp115;
#line 988
    intel_lvds->fixed_mode = drm_mode_duplicate(dev, __cil_tmp116);
    }
    {
#line 990
    __cil_tmp117 = (struct drm_display_mode *)0;
#line 990
    __cil_tmp118 = (unsigned long )__cil_tmp117;
#line 990
    __cil_tmp119 = intel_lvds->fixed_mode;
#line 990
    __cil_tmp120 = (unsigned long )__cil_tmp119;
#line 990
    if (__cil_tmp120 != __cil_tmp118) {
#line 991
      __cil_tmp121 = intel_lvds->fixed_mode;
#line 991
      __cil_tmp122 = intel_lvds->fixed_mode;
#line 991
      __cil_tmp123 = __cil_tmp122->type;
#line 991
      __cil_tmp121->type = __cil_tmp123 | 8;
#line 993
      goto out;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1004
  __cil_tmp124 = dev->dev_private;
#line 1004
  __cil_tmp125 = (struct drm_i915_private *)__cil_tmp124;
#line 1004
  __cil_tmp126 = __cil_tmp125->info;
#line 1004
  __cil_tmp127 = __cil_tmp126->gen;
#line 1004
  __cil_tmp128 = (unsigned char )__cil_tmp127;
#line 1004
  __cil_tmp129 = (unsigned int )__cil_tmp128;
#line 1004
  if (__cil_tmp129 == 5U) {
#line 1005
    goto failed;
  } else {
    {
#line 1004
    __cil_tmp130 = dev->dev_private;
#line 1004
    __cil_tmp131 = (struct drm_i915_private *)__cil_tmp130;
#line 1004
    __cil_tmp132 = __cil_tmp131->info;
#line 1004
    __cil_tmp133 = __cil_tmp132->gen;
#line 1004
    __cil_tmp134 = (unsigned char )__cil_tmp133;
#line 1004
    __cil_tmp135 = (unsigned int )__cil_tmp134;
#line 1004
    if (__cil_tmp135 == 6U) {
#line 1005
      goto failed;
    } else {
      {
#line 1004
      __cil_tmp136 = dev->dev_private;
#line 1004
      __cil_tmp137 = (struct drm_i915_private *)__cil_tmp136;
#line 1004
      __cil_tmp138 = __cil_tmp137->info;
#line 1004
      __cil_tmp139 = (unsigned char *)__cil_tmp138;
#line 1004
      __cil_tmp140 = __cil_tmp139 + 2UL;
#line 1004
      __cil_tmp141 = *__cil_tmp140;
#line 1004
      __cil_tmp142 = (unsigned int )__cil_tmp141;
#line 1004
      if (__cil_tmp142 != 0U) {
#line 1005
        goto failed;
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 1007
  lvds = i915_read32___8(dev_priv, 397696U);
#line 1008
  __cil_tmp143 = lvds & 1073741824U;
#line 1008
  pipe = __cil_tmp143 != 0U;
#line 1009
  crtc = intel_get_crtc_for_pipe(dev, pipe);
  }
  {
#line 1011
  __cil_tmp144 = (struct drm_crtc *)0;
#line 1011
  __cil_tmp145 = (unsigned long )__cil_tmp144;
#line 1011
  __cil_tmp146 = (unsigned long )crtc;
#line 1011
  if (__cil_tmp146 != __cil_tmp145) {
    {
#line 1011
    __cil_tmp147 = (int )lvds;
#line 1011
    if (__cil_tmp147 < 0) {
      {
#line 1012
      intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc);
      }
      {
#line 1013
      __cil_tmp148 = (struct drm_display_mode *)0;
#line 1013
      __cil_tmp149 = (unsigned long )__cil_tmp148;
#line 1013
      __cil_tmp150 = intel_lvds->fixed_mode;
#line 1013
      __cil_tmp151 = (unsigned long )__cil_tmp150;
#line 1013
      if (__cil_tmp151 != __cil_tmp149) {
#line 1014
        __cil_tmp152 = intel_lvds->fixed_mode;
#line 1014
        __cil_tmp153 = intel_lvds->fixed_mode;
#line 1014
        __cil_tmp154 = __cil_tmp153->type;
#line 1014
        __cil_tmp152->type = __cil_tmp154 | 8;
#line 1016
        goto out;
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1021
  __cil_tmp155 = (struct drm_display_mode *)0;
#line 1021
  __cil_tmp156 = (unsigned long )__cil_tmp155;
#line 1021
  __cil_tmp157 = intel_lvds->fixed_mode;
#line 1021
  __cil_tmp158 = (unsigned long )__cil_tmp157;
#line 1021
  if (__cil_tmp158 == __cil_tmp156) {
#line 1022
    goto failed;
  } else {

  }
  }
  out: ;
  {
#line 1025
  __cil_tmp159 = dev->dev_private;
#line 1025
  __cil_tmp160 = (struct drm_i915_private *)__cil_tmp159;
#line 1025
  __cil_tmp161 = __cil_tmp160->info;
#line 1025
  __cil_tmp162 = __cil_tmp161->gen;
#line 1025
  __cil_tmp163 = (unsigned char )__cil_tmp162;
#line 1025
  __cil_tmp164 = (unsigned int )__cil_tmp163;
#line 1025
  if (__cil_tmp164 == 5U) {
#line 1025
    goto _L___0;
  } else {
    {
#line 1025
    __cil_tmp165 = dev->dev_private;
#line 1025
    __cil_tmp166 = (struct drm_i915_private *)__cil_tmp165;
#line 1025
    __cil_tmp167 = __cil_tmp166->info;
#line 1025
    __cil_tmp168 = __cil_tmp167->gen;
#line 1025
    __cil_tmp169 = (unsigned char )__cil_tmp168;
#line 1025
    __cil_tmp170 = (unsigned int )__cil_tmp169;
#line 1025
    if (__cil_tmp170 == 6U) {
#line 1025
      goto _L___0;
    } else {
      {
#line 1025
      __cil_tmp171 = dev->dev_private;
#line 1025
      __cil_tmp172 = (struct drm_i915_private *)__cil_tmp171;
#line 1025
      __cil_tmp173 = __cil_tmp172->info;
#line 1025
      __cil_tmp174 = (unsigned char *)__cil_tmp173;
#line 1025
      __cil_tmp175 = __cil_tmp174 + 2UL;
#line 1025
      __cil_tmp176 = *__cil_tmp175;
#line 1025
      __cil_tmp177 = (unsigned int )__cil_tmp176;
#line 1025
      if (__cil_tmp177 != 0U) {
        _L___0: 
        {
#line 1028
        tmp___6 = i915_read32___8(dev_priv, 921984U);
#line 1028
        __cil_tmp178 = tmp___6 & 1073741824U;
#line 1028
        pipe = __cil_tmp178 != 0U;
#line 1031
        pwm = i915_read32___8(dev_priv, 295504U);
        }
#line 1032
        if (pipe == 0) {
          {
#line 1032
          __cil_tmp179 = pwm & 536870912U;
#line 1032
          if (__cil_tmp179 != 0U) {
            {
#line 1033
            __cil_tmp180 = pwm & 2147483647U;
#line 1033
            i915_write32___6(dev_priv, 295504U, __cil_tmp180);
            }
          } else {

          }
          }
        } else {

        }
#line 1034
        if (pipe != 0) {
#line 1035
          pwm = pwm | 536870912U;
        } else {
#line 1037
          pwm = pwm & 3758096383U;
        }
        {
#line 1038
        __cil_tmp181 = pwm | 2147483648U;
#line 1038
        i915_write32___6(dev_priv, 295504U, __cil_tmp181);
#line 1040
        pwm = i915_read32___8(dev_priv, 819792U);
#line 1041
        pwm = pwm | 2147483648U;
#line 1042
        i915_write32___6(dev_priv, 819792U, pwm);
        }
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 1044
  dev_priv->lid_notifier.notifier_call = & intel_lid_notify;
#line 1045
  __cil_tmp182 = & dev_priv->lid_notifier;
#line 1045
  tmp___7 = acpi_lid_notifier_register(__cil_tmp182);
  }
#line 1045
  if (tmp___7 != 0) {
    {
#line 1046
    drm_ut_debug_printk(4U, "drm", "intel_lvds_init", "lid notifier registration failed\n");
#line 1047
    dev_priv->lid_notifier.notifier_call = (int (*)(struct notifier_block * , unsigned long  ,
                                                    void * ))0;
    }
  } else {

  }
  {
#line 1050
  dev_priv->int_lvds_connector = connector;
#line 1051
  drm_sysfs_connector_add(connector);
  }
#line 1052
  return ((bool )1);
  failed: 
  {
#line 1055
  drm_ut_debug_printk(4U, "drm", "intel_lvds_init", "No LVDS modes found, disabling.\n");
#line 1056
  drm_connector_cleanup(connector);
#line 1057
  drm_encoder_cleanup(encoder);
#line 1058
  __cil_tmp183 = (void const   *)intel_lvds;
#line 1058
  kfree(__cil_tmp183);
#line 1059
  __cil_tmp184 = (void const   *)intel_connector;
#line 1059
  kfree(__cil_tmp184);
  }
#line 1060
  return ((bool )0);
}
}
#line 60 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/string_64.h"
extern int memcmp(void const   * , void const   * , size_t  ) ;
#line 808 "include/linux/pci.h"
extern void *pci_map_rom(struct pci_dev * , size_t * ) ;
#line 809
extern void pci_unmap_rom(struct pci_dev * , void * ) ;
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___9(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36546: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36546;
      } else {
#line 390
        goto ldv_36547;
      }
      }
      ldv_36547: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___9(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___9(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___7(struct drm_i915_private *dev_priv , u32 reg ,
                                      u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___9(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 44 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static int panel_type  ;
#line 47 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void *find_section(struct bdb_header *bdb , int section_id ) 
{ u8 *base ;
  int index ;
  u16 total ;
  u16 current_size ;
  u8 current_id ;
  u16 __cil_tmp8 ;
  int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  u8 *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  u16 *__cil_tmp13 ;
  u16 *__cil_tmp14 ;
  int __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;

  {
#line 49
  base = (u8 *)bdb;
#line 50
  index = 0;
#line 55
  __cil_tmp8 = bdb->header_size;
#line 55
  __cil_tmp9 = (int )__cil_tmp8;
#line 55
  index = __cil_tmp9 + index;
#line 56
  total = bdb->bdb_size;
#line 59
  goto ldv_37077;
  ldv_37076: 
#line 60
  __cil_tmp10 = (unsigned long )index;
#line 60
  __cil_tmp11 = base + __cil_tmp10;
#line 60
  current_id = *__cil_tmp11;
#line 61
  index = index + 1;
#line 62
  __cil_tmp12 = (unsigned long )index;
#line 62
  __cil_tmp13 = (u16 *)base;
#line 62
  __cil_tmp14 = __cil_tmp13 + __cil_tmp12;
#line 62
  current_size = *__cil_tmp14;
#line 63
  index = index + 2;
  {
#line 64
  __cil_tmp15 = (int )current_id;
#line 64
  if (__cil_tmp15 == section_id) {
    {
#line 65
    __cil_tmp16 = (unsigned long )index;
#line 65
    __cil_tmp17 = (void *)base;
#line 65
    return (__cil_tmp17 + __cil_tmp16);
    }
  } else {

  }
  }
#line 66
  __cil_tmp18 = (int )current_size;
#line 66
  index = __cil_tmp18 + index;
  ldv_37077: ;
  {
#line 59
  __cil_tmp19 = (int )total;
#line 59
  if (__cil_tmp19 > index) {
#line 60
    goto ldv_37076;
  } else {
#line 62
    goto ldv_37078;
  }
  }
  ldv_37078: ;
#line 69
  return ((void *)0);
}
}
#line 73 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static u16 get_blocksize(void *p ) 
{ u16 *block_ptr ;
  u16 block_size ;
  u16 *__cil_tmp4 ;

  {
#line 77
  __cil_tmp4 = (u16 *)p;
#line 77
  block_ptr = __cil_tmp4 + 1152921504606846974UL;
#line 78
  block_size = *block_ptr;
#line 79
  return (block_size);
}
}
#line 83 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode , struct lvds_dvo_timing *dvo_timing ) 
{ u8 __cil_tmp3 ;
  int __cil_tmp4 ;
  unsigned char __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  u8 __cil_tmp8 ;
  int __cil_tmp9 ;
  unsigned char __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  u8 __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  u8 __cil_tmp18 ;
  int __cil_tmp19 ;
  unsigned char __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  u8 __cil_tmp25 ;
  int __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  unsigned char __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  unsigned char __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  u8 __cil_tmp36 ;
  int __cil_tmp37 ;
  unsigned char __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  int __cil_tmp42 ;
  u16 __cil_tmp43 ;
  int __cil_tmp44 ;
  unsigned char *__cil_tmp45 ;
  unsigned char *__cil_tmp46 ;
  unsigned char __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  unsigned int __cil_tmp49 ;
  unsigned int __cil_tmp50 ;
  unsigned char *__cil_tmp51 ;
  unsigned char *__cil_tmp52 ;
  unsigned char __cil_tmp53 ;
  unsigned int __cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  unsigned int __cil_tmp56 ;
  int __cil_tmp57 ;
  int __cil_tmp58 ;
  int __cil_tmp59 ;
  int __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;

  {
#line 86
  __cil_tmp3 = dvo_timing->hactive_lo;
#line 86
  __cil_tmp4 = (int )__cil_tmp3;
#line 86
  __cil_tmp5 = dvo_timing->hactive_hi;
#line 86
  __cil_tmp6 = (int )__cil_tmp5;
#line 86
  __cil_tmp7 = __cil_tmp6 << 8;
#line 86
  panel_fixed_mode->hdisplay = __cil_tmp7 | __cil_tmp4;
#line 88
  __cil_tmp8 = dvo_timing->hsync_off_lo;
#line 88
  __cil_tmp9 = (int )__cil_tmp8;
#line 88
  __cil_tmp10 = dvo_timing->hsync_off_hi;
#line 88
  __cil_tmp11 = (int )__cil_tmp10;
#line 88
  __cil_tmp12 = __cil_tmp11 << 8;
#line 88
  __cil_tmp13 = __cil_tmp12 | __cil_tmp9;
#line 88
  __cil_tmp14 = panel_fixed_mode->hdisplay;
#line 88
  panel_fixed_mode->hsync_start = __cil_tmp14 + __cil_tmp13;
#line 90
  __cil_tmp15 = dvo_timing->hsync_pulse_width;
#line 90
  __cil_tmp16 = (int )__cil_tmp15;
#line 90
  __cil_tmp17 = panel_fixed_mode->hsync_start;
#line 90
  panel_fixed_mode->hsync_end = __cil_tmp17 + __cil_tmp16;
#line 92
  __cil_tmp18 = dvo_timing->hblank_lo;
#line 92
  __cil_tmp19 = (int )__cil_tmp18;
#line 92
  __cil_tmp20 = dvo_timing->hblank_hi;
#line 92
  __cil_tmp21 = (int )__cil_tmp20;
#line 92
  __cil_tmp22 = __cil_tmp21 << 8;
#line 92
  __cil_tmp23 = __cil_tmp22 | __cil_tmp19;
#line 92
  __cil_tmp24 = panel_fixed_mode->hdisplay;
#line 92
  panel_fixed_mode->htotal = __cil_tmp24 + __cil_tmp23;
#line 95
  __cil_tmp25 = dvo_timing->vactive_lo;
#line 95
  __cil_tmp26 = (int )__cil_tmp25;
#line 95
  __cil_tmp27 = dvo_timing->vactive_hi;
#line 95
  __cil_tmp28 = (int )__cil_tmp27;
#line 95
  __cil_tmp29 = __cil_tmp28 << 8;
#line 95
  panel_fixed_mode->vdisplay = __cil_tmp29 | __cil_tmp26;
#line 97
  __cil_tmp30 = dvo_timing->vsync_off;
#line 97
  __cil_tmp31 = (int )__cil_tmp30;
#line 97
  __cil_tmp32 = panel_fixed_mode->vdisplay;
#line 97
  panel_fixed_mode->vsync_start = __cil_tmp32 + __cil_tmp31;
#line 99
  __cil_tmp33 = dvo_timing->vsync_pulse_width;
#line 99
  __cil_tmp34 = (int )__cil_tmp33;
#line 99
  __cil_tmp35 = panel_fixed_mode->vsync_start;
#line 99
  panel_fixed_mode->vsync_end = __cil_tmp35 + __cil_tmp34;
#line 101
  __cil_tmp36 = dvo_timing->vblank_lo;
#line 101
  __cil_tmp37 = (int )__cil_tmp36;
#line 101
  __cil_tmp38 = dvo_timing->vblank_hi;
#line 101
  __cil_tmp39 = (int )__cil_tmp38;
#line 101
  __cil_tmp40 = __cil_tmp39 << 8;
#line 101
  __cil_tmp41 = __cil_tmp40 | __cil_tmp37;
#line 101
  __cil_tmp42 = panel_fixed_mode->vdisplay;
#line 101
  panel_fixed_mode->vtotal = __cil_tmp42 + __cil_tmp41;
#line 103
  __cil_tmp43 = dvo_timing->clock;
#line 103
  __cil_tmp44 = (int )__cil_tmp43;
#line 103
  panel_fixed_mode->clock = __cil_tmp44 * 10;
#line 104
  panel_fixed_mode->type = 8;
  {
#line 106
  __cil_tmp45 = (unsigned char *)dvo_timing;
#line 106
  __cil_tmp46 = __cil_tmp45 + 17UL;
#line 106
  __cil_tmp47 = *__cil_tmp46;
#line 106
  __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 106
  if (__cil_tmp48 != 0U) {
#line 107
    __cil_tmp49 = panel_fixed_mode->flags;
#line 107
    panel_fixed_mode->flags = __cil_tmp49 | 1U;
  } else {
#line 109
    __cil_tmp50 = panel_fixed_mode->flags;
#line 109
    panel_fixed_mode->flags = __cil_tmp50 | 2U;
  }
  }
  {
#line 111
  __cil_tmp51 = (unsigned char *)dvo_timing;
#line 111
  __cil_tmp52 = __cil_tmp51 + 17UL;
#line 111
  __cil_tmp53 = *__cil_tmp52;
#line 111
  __cil_tmp54 = (unsigned int )__cil_tmp53;
#line 111
  if (__cil_tmp54 != 0U) {
#line 112
    __cil_tmp55 = panel_fixed_mode->flags;
#line 112
    panel_fixed_mode->flags = __cil_tmp55 | 4U;
  } else {
#line 114
    __cil_tmp56 = panel_fixed_mode->flags;
#line 114
    panel_fixed_mode->flags = __cil_tmp56 | 8U;
  }
  }
  {
#line 117
  __cil_tmp57 = panel_fixed_mode->htotal;
#line 117
  __cil_tmp58 = panel_fixed_mode->hsync_end;
#line 117
  if (__cil_tmp58 > __cil_tmp57) {
#line 118
    __cil_tmp59 = panel_fixed_mode->hsync_end;
#line 118
    panel_fixed_mode->htotal = __cil_tmp59 + 1;
  } else {

  }
  }
  {
#line 119
  __cil_tmp60 = panel_fixed_mode->vtotal;
#line 119
  __cil_tmp61 = panel_fixed_mode->vsync_end;
#line 119
  if (__cil_tmp61 > __cil_tmp60) {
#line 120
    __cil_tmp62 = panel_fixed_mode->vsync_end;
#line 120
    panel_fixed_mode->vtotal = __cil_tmp62 + 1;
  } else {

  }
  }
  {
#line 122
  drm_mode_set_name(panel_fixed_mode);
  }
#line 123
  return;
}
}
#line 127 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_lfp_panel_data(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct bdb_lvds_options *lvds_options ;
  struct bdb_lvds_lfp_data *lvds_lfp_data ;
  struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs ;
  struct bdb_lvds_lfp_data_entry *entry ;
  struct lvds_dvo_timing *dvo_timing ;
  struct drm_display_mode *panel_fixed_mode ;
  int lfp_data_size ;
  int dvo_timing_offset ;
  int i ;
  int temp_downclock ;
  struct drm_display_mode *temp_mode ;
  void *tmp ;
  void *tmp___0 ;
  void *tmp___1 ;
  void *tmp___2 ;
  void *tmp___3 ;
  struct bdb_lvds_options *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  u8 __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  u8 __cil_tmp24 ;
  struct bdb_lvds_lfp_data *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  struct bdb_lvds_lfp_data_ptrs *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  u16 __cil_tmp31 ;
  int __cil_tmp32 ;
  u16 __cil_tmp33 ;
  int __cil_tmp34 ;
  u8 __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  struct bdb_lvds_lfp_data_entry (*__cil_tmp39)[16U] ;
  struct bdb_lvds_lfp_data_entry *__cil_tmp40 ;
  u16 __cil_tmp41 ;
  int __cil_tmp42 ;
  u16 __cil_tmp43 ;
  int __cil_tmp44 ;
  unsigned long __cil_tmp45 ;
  struct lvds_dvo_timing *__cil_tmp46 ;
  struct drm_display_mode *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  unsigned long __cil_tmp49 ;
  int __cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  struct bdb_lvds_lfp_data_entry (*__cil_tmp52)[16U] ;
  struct bdb_lvds_lfp_data_entry *__cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  struct lvds_dvo_timing *__cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  int __cil_tmp58 ;
  int __cil_tmp59 ;
  int __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;
  int __cil_tmp63 ;
  int __cil_tmp64 ;
  int __cil_tmp65 ;
  int __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  int __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  void *__cil_tmp73 ;
  void const   *__cil_tmp74 ;
  int __cil_tmp75 ;
  int __cil_tmp76 ;

  {
  {
#line 140
  tmp = find_section(bdb, 40);
#line 140
  lvds_options = (struct bdb_lvds_options *)tmp;
  }
  {
#line 141
  __cil_tmp19 = (struct bdb_lvds_options *)0;
#line 141
  __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 141
  __cil_tmp21 = (unsigned long )lvds_options;
#line 141
  if (__cil_tmp21 == __cil_tmp20) {
#line 142
    return;
  } else {

  }
  }
#line 144
  dev_priv->lvds_dither = lvds_options->pixel_dither;
  {
#line 145
  __cil_tmp22 = lvds_options->panel_type;
#line 145
  __cil_tmp23 = (unsigned int )__cil_tmp22;
#line 145
  if (__cil_tmp23 == 255U) {
#line 146
    return;
  } else {

  }
  }
  {
#line 148
  __cil_tmp24 = lvds_options->panel_type;
#line 148
  panel_type = (int )__cil_tmp24;
#line 150
  tmp___0 = find_section(bdb, 42);
#line 150
  lvds_lfp_data = (struct bdb_lvds_lfp_data *)tmp___0;
  }
  {
#line 151
  __cil_tmp25 = (struct bdb_lvds_lfp_data *)0;
#line 151
  __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 151
  __cil_tmp27 = (unsigned long )lvds_lfp_data;
#line 151
  if (__cil_tmp27 == __cil_tmp26) {
#line 152
    return;
  } else {

  }
  }
  {
#line 154
  tmp___1 = find_section(bdb, 41);
#line 154
  lvds_lfp_data_ptrs = (struct bdb_lvds_lfp_data_ptrs *)tmp___1;
  }
  {
#line 155
  __cil_tmp28 = (struct bdb_lvds_lfp_data_ptrs *)0;
#line 155
  __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 155
  __cil_tmp30 = (unsigned long )lvds_lfp_data_ptrs;
#line 155
  if (__cil_tmp30 == __cil_tmp29) {
#line 156
    return;
  } else {

  }
  }
  {
#line 158
  dev_priv->lvds_vbt = (unsigned char)1;
#line 160
  __cil_tmp31 = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
#line 160
  __cil_tmp32 = (int )__cil_tmp31;
#line 160
  __cil_tmp33 = lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset;
#line 160
  __cil_tmp34 = (int )__cil_tmp33;
#line 160
  lfp_data_size = __cil_tmp34 - __cil_tmp32;
#line 162
  __cil_tmp35 = lvds_options->panel_type;
#line 162
  __cil_tmp36 = (int )__cil_tmp35;
#line 162
  __cil_tmp37 = __cil_tmp36 * lfp_data_size;
#line 162
  __cil_tmp38 = (unsigned long )__cil_tmp37;
#line 162
  __cil_tmp39 = & lvds_lfp_data->data;
#line 162
  __cil_tmp40 = (struct bdb_lvds_lfp_data_entry *)__cil_tmp39;
#line 162
  entry = __cil_tmp40 + __cil_tmp38;
#line 165
  __cil_tmp41 = lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
#line 165
  __cil_tmp42 = (int )__cil_tmp41;
#line 165
  __cil_tmp43 = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
#line 165
  __cil_tmp44 = (int )__cil_tmp43;
#line 165
  dvo_timing_offset = __cil_tmp44 - __cil_tmp42;
#line 173
  __cil_tmp45 = (unsigned long )dvo_timing_offset;
#line 173
  __cil_tmp46 = (struct lvds_dvo_timing *)entry;
#line 173
  dvo_timing = __cil_tmp46 + __cil_tmp45;
#line 176
  tmp___2 = kzalloc(224UL, 208U);
#line 176
  panel_fixed_mode = (struct drm_display_mode *)tmp___2;
  }
  {
#line 177
  __cil_tmp47 = (struct drm_display_mode *)0;
#line 177
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 177
  __cil_tmp49 = (unsigned long )panel_fixed_mode;
#line 177
  if (__cil_tmp49 == __cil_tmp48) {
#line 178
    return;
  } else {

  }
  }
  {
#line 180
  fill_detail_timing_data(panel_fixed_mode, dvo_timing);
#line 182
  dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
#line 184
  drm_ut_debug_printk(4U, "drm", "parse_lfp_panel_data", "Found panel mode in BIOS VBT tables:\n");
#line 185
  drm_mode_debug_printmodeline(panel_fixed_mode);
#line 187
  tmp___3 = kzalloc(224UL, 208U);
#line 187
  temp_mode = (struct drm_display_mode *)tmp___3;
#line 188
  temp_downclock = panel_fixed_mode->clock;
#line 193
  i = 0;
  }
#line 193
  goto ldv_37105;
  ldv_37104: 
  {
#line 194
  __cil_tmp50 = lfp_data_size * i;
#line 194
  __cil_tmp51 = (unsigned long )__cil_tmp50;
#line 194
  __cil_tmp52 = & lvds_lfp_data->data;
#line 194
  __cil_tmp53 = (struct bdb_lvds_lfp_data_entry *)__cil_tmp52;
#line 194
  entry = __cil_tmp53 + __cil_tmp51;
#line 196
  __cil_tmp54 = (unsigned long )dvo_timing_offset;
#line 196
  __cil_tmp55 = (struct lvds_dvo_timing *)entry;
#line 196
  dvo_timing = __cil_tmp55 + __cil_tmp54;
#line 199
  fill_detail_timing_data(temp_mode, dvo_timing);
  }
  {
#line 201
  __cil_tmp56 = panel_fixed_mode->hdisplay;
#line 201
  __cil_tmp57 = temp_mode->hdisplay;
#line 201
  if (__cil_tmp57 == __cil_tmp56) {
    {
#line 201
    __cil_tmp58 = panel_fixed_mode->hsync_start;
#line 201
    __cil_tmp59 = temp_mode->hsync_start;
#line 201
    if (__cil_tmp59 == __cil_tmp58) {
      {
#line 201
      __cil_tmp60 = panel_fixed_mode->hsync_end;
#line 201
      __cil_tmp61 = temp_mode->hsync_end;
#line 201
      if (__cil_tmp61 == __cil_tmp60) {
        {
#line 201
        __cil_tmp62 = panel_fixed_mode->htotal;
#line 201
        __cil_tmp63 = temp_mode->htotal;
#line 201
        if (__cil_tmp63 == __cil_tmp62) {
          {
#line 201
          __cil_tmp64 = panel_fixed_mode->vdisplay;
#line 201
          __cil_tmp65 = temp_mode->vdisplay;
#line 201
          if (__cil_tmp65 == __cil_tmp64) {
            {
#line 201
            __cil_tmp66 = panel_fixed_mode->vsync_start;
#line 201
            __cil_tmp67 = temp_mode->vsync_start;
#line 201
            if (__cil_tmp67 == __cil_tmp66) {
              {
#line 201
              __cil_tmp68 = panel_fixed_mode->vsync_end;
#line 201
              __cil_tmp69 = temp_mode->vsync_end;
#line 201
              if (__cil_tmp69 == __cil_tmp68) {
                {
#line 201
                __cil_tmp70 = panel_fixed_mode->vtotal;
#line 201
                __cil_tmp71 = temp_mode->vtotal;
#line 201
                if (__cil_tmp71 == __cil_tmp70) {
                  {
#line 201
                  __cil_tmp72 = temp_mode->clock;
#line 201
                  if (__cil_tmp72 < temp_downclock) {
#line 214
                    temp_downclock = temp_mode->clock;
                  } else {

                  }
                  }
                } else {

                }
                }
              } else {

              }
              }
            } else {

            }
            }
          } else {

          }
          }
        } else {

        }
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 217
  __cil_tmp73 = (void *)temp_mode;
#line 217
  memset(__cil_tmp73, 0, 224UL);
#line 193
  i = i + 1;
  }
  ldv_37105: ;
#line 193
  if (i <= 15) {
#line 194
    goto ldv_37104;
  } else {
#line 196
    goto ldv_37106;
  }
  ldv_37106: 
  {
#line 219
  __cil_tmp74 = (void const   *)temp_mode;
#line 219
  kfree(__cil_tmp74);
  }
  {
#line 220
  __cil_tmp75 = panel_fixed_mode->clock;
#line 220
  if (__cil_tmp75 > temp_downclock) {
#line 220
    if (i915_lvds_downclock != 0U) {
      {
#line 222
      dev_priv->lvds_downclock_avail = (bool )1;
#line 223
      dev_priv->lvds_downclock = temp_downclock;
#line 224
      __cil_tmp76 = panel_fixed_mode->clock;
#line 224
      drm_ut_debug_printk(4U, "drm", "parse_lfp_panel_data", "LVDS downclock is found in VBT. Normal Clock %dKHz, downclock %dKHz\n",
                          temp_downclock, __cil_tmp76);
      }
    } else {

    }
  } else {

  }
  }
#line 228
  return;
}
}
#line 233 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_sdvo_panel_data(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct lvds_dvo_timing *dvo_timing ;
  struct drm_display_mode *panel_fixed_mode ;
  int index ;
  struct bdb_sdvo_lvds_options *sdvo_lvds_options ;
  void *tmp ;
  void *tmp___0 ;
  void *tmp___1 ;
  struct bdb_sdvo_lvds_options *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  u8 __cil_tmp13 ;
  struct lvds_dvo_timing *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct drm_display_mode *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  struct lvds_dvo_timing *__cil_tmp21 ;

  {
#line 240
  index = i915_vbt_sdvo_panel_type;
#line 241
  if (index == -1) {
    {
#line 244
    tmp = find_section(bdb, 22);
#line 244
    sdvo_lvds_options = (struct bdb_sdvo_lvds_options *)tmp;
    }
    {
#line 245
    __cil_tmp10 = (struct bdb_sdvo_lvds_options *)0;
#line 245
    __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 245
    __cil_tmp12 = (unsigned long )sdvo_lvds_options;
#line 245
    if (__cil_tmp12 == __cil_tmp11) {
#line 246
      return;
    } else {

    }
    }
#line 248
    __cil_tmp13 = sdvo_lvds_options->panel_type;
#line 248
    index = (int )__cil_tmp13;
  } else {

  }
  {
#line 251
  tmp___0 = find_section(bdb, 23);
#line 251
  dvo_timing = (struct lvds_dvo_timing *)tmp___0;
  }
  {
#line 252
  __cil_tmp14 = (struct lvds_dvo_timing *)0;
#line 252
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 252
  __cil_tmp16 = (unsigned long )dvo_timing;
#line 252
  if (__cil_tmp16 == __cil_tmp15) {
#line 253
    return;
  } else {

  }
  }
  {
#line 255
  tmp___1 = kzalloc(224UL, 208U);
#line 255
  panel_fixed_mode = (struct drm_display_mode *)tmp___1;
  }
  {
#line 256
  __cil_tmp17 = (struct drm_display_mode *)0;
#line 256
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 256
  __cil_tmp19 = (unsigned long )panel_fixed_mode;
#line 256
  if (__cil_tmp19 == __cil_tmp18) {
#line 257
    return;
  } else {

  }
  }
  {
#line 259
  __cil_tmp20 = (unsigned long )index;
#line 259
  __cil_tmp21 = dvo_timing + __cil_tmp20;
#line 259
  fill_detail_timing_data(panel_fixed_mode, __cil_tmp21);
#line 261
  dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;
#line 263
  drm_ut_debug_printk(4U, "drm", "parse_sdvo_panel_data", "Found SDVO panel mode in BIOS VBT tables:\n");
#line 264
  drm_mode_debug_printmodeline(panel_fixed_mode);
  }
#line 265
  return;
}
}
#line 267 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static int intel_bios_ssc_frequency(struct drm_device *dev , bool alternate ) 
{ int tmp ;
  int tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp6 ;
  struct drm_i915_private *__cil_tmp7 ;
  struct intel_device_info  const  *__cil_tmp8 ;
  u8 __cil_tmp9 ;
  int __cil_tmp10 ;
  void *__cil_tmp11 ;
  struct drm_i915_private *__cil_tmp12 ;
  struct intel_device_info  const  *__cil_tmp13 ;
  u8 __cil_tmp14 ;
  int __cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  u8 __cil_tmp19 ;
  int __cil_tmp20 ;

  {
  {
#line 271
  __cil_tmp6 = dev->dev_private;
#line 271
  __cil_tmp7 = (struct drm_i915_private *)__cil_tmp6;
#line 271
  __cil_tmp8 = __cil_tmp7->info;
#line 271
  __cil_tmp9 = __cil_tmp8->gen;
#line 271
  __cil_tmp10 = (int )__cil_tmp9;
#line 271
  if (__cil_tmp10 == 2) {
#line 271
    goto case_2;
  } else {
    {
#line 273
    __cil_tmp11 = dev->dev_private;
#line 273
    __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
#line 273
    __cil_tmp13 = __cil_tmp12->info;
#line 273
    __cil_tmp14 = __cil_tmp13->gen;
#line 273
    __cil_tmp15 = (int )__cil_tmp14;
#line 273
    if (__cil_tmp15 == 3) {
#line 273
      goto case_3;
    } else {
      {
#line 274
      __cil_tmp16 = dev->dev_private;
#line 274
      __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 274
      __cil_tmp18 = __cil_tmp17->info;
#line 274
      __cil_tmp19 = __cil_tmp18->gen;
#line 274
      __cil_tmp20 = (int )__cil_tmp19;
#line 274
      if (__cil_tmp20 == 4) {
#line 274
        goto case_4;
      } else {
#line 276
        goto switch_default;
#line 270
        if (0) {
          case_2: ;
#line 272
          if ((int )alternate) {
#line 272
            tmp = 66;
          } else {
#line 272
            tmp = 48;
          }
#line 272
          return (tmp);
          case_3: ;
          case_4: ;
#line 275
          if ((int )alternate) {
#line 275
            tmp___0 = 100;
          } else {
#line 275
            tmp___0 = 96;
          }
#line 275
          return (tmp___0);
          switch_default: ;
#line 277
          if ((int )alternate) {
#line 277
            tmp___1 = 100;
          } else {
#line 277
            tmp___1 = 120;
          }
#line 277
          return (tmp___1);
        } else {

        }
      }
      }
    }
    }
  }
  }
}
}
#line 282 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_general_features(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct drm_device *dev ;
  struct bdb_general_features *general ;
  void *tmp ;
  struct bdb_general_features *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned char *__cil_tmp9 ;
  unsigned char *__cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  int __cil_tmp13 ;
  bool __cil_tmp14 ;

  {
  {
#line 285
  dev = dev_priv->dev;
#line 288
  tmp = find_section(bdb, 1);
#line 288
  general = (struct bdb_general_features *)tmp;
  }
  {
#line 289
  __cil_tmp6 = (struct bdb_general_features *)0;
#line 289
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 289
  __cil_tmp8 = (unsigned long )general;
#line 289
  if (__cil_tmp8 != __cil_tmp7) {
    {
#line 290
    dev_priv->int_tv_support = general->int_tv_support;
#line 291
    dev_priv->int_crt_support = general->int_crt_support;
#line 292
    dev_priv->lvds_use_ssc = general->enable_ssc;
#line 293
    __cil_tmp9 = (unsigned char *)general;
#line 293
    __cil_tmp10 = __cil_tmp9 + 1UL;
#line 293
    __cil_tmp11 = *__cil_tmp10;
#line 293
    __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 293
    __cil_tmp13 = __cil_tmp12 != 0U;
#line 293
    __cil_tmp14 = (bool )__cil_tmp13;
#line 293
    dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, __cil_tmp14);
    }
  } else {

  }
  }
#line 296
  return;
}
}
#line 299 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_general_definitions(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct bdb_general_definitions *general ;
  void *tmp ;
  u16 block_size ;
  u16 tmp___0 ;
  int bus_pin ;
  struct bdb_general_definitions *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  u8 __cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 304
  tmp = find_section(bdb, 2);
#line 304
  general = (struct bdb_general_definitions *)tmp;
  }
  {
#line 305
  __cil_tmp8 = (struct bdb_general_definitions *)0;
#line 305
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 305
  __cil_tmp10 = (unsigned long )general;
#line 305
  if (__cil_tmp10 != __cil_tmp9) {
    {
#line 306
    __cil_tmp11 = (void *)general;
#line 306
    tmp___0 = get_blocksize(__cil_tmp11);
#line 306
    block_size = tmp___0;
    }
    {
#line 307
    __cil_tmp12 = (unsigned int )block_size;
#line 307
    if (__cil_tmp12 > 4U) {
      {
#line 308
      __cil_tmp13 = general->crt_ddc_gmbus_pin;
#line 308
      bus_pin = (int )__cil_tmp13;
#line 309
      drm_ut_debug_printk(4U, "drm", "parse_general_definitions", "crt_ddc_bus_pin: %d\n",
                          bus_pin);
      }
#line 310
      if (bus_pin > 0) {
#line 310
        if (bus_pin <= 6) {
#line 311
          dev_priv->crt_ddc_pin = bus_pin;
        } else {

        }
      } else {

      }
    } else {
      {
#line 313
      __cil_tmp14 = (int )block_size;
#line 313
      drm_ut_debug_printk(4U, "drm", "parse_general_definitions", "BDB_GD too small (%d). Invalid.\n",
                          __cil_tmp14);
      }
    }
    }
  } else {

  }
  }
#line 315
  return;
}
}
#line 320 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_sdvo_device_mapping(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct sdvo_device_mapping *p_mapping ;
  struct bdb_general_definitions *p_defs ;
  struct child_device_config *p_child ;
  int i ;
  int child_device_num ;
  int count ;
  u16 block_size ;
  void *tmp ;
  char *tmp___0 ;
  struct bdb_general_definitions *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  u8 __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  void *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct child_device_config (*__cil_tmp22)[0U] ;
  struct child_device_config *__cil_tmp23 ;
  u16 __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  u8 __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  u8 __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  u8 __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  u8 __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  u8 __cil_tmp36 ;
  int __cil_tmp37 ;
  u8 __cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  unsigned long __cil_tmp40 ;
  struct sdvo_device_mapping (*__cil_tmp41)[2U] ;
  struct sdvo_device_mapping *__cil_tmp42 ;
  u8 __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  u8 __cil_tmp45 ;
  int __cil_tmp46 ;
  u8 __cil_tmp47 ;
  int __cil_tmp48 ;
  u8 __cil_tmp49 ;
  int __cil_tmp50 ;
  u8 __cil_tmp51 ;
  int __cil_tmp52 ;
  u8 __cil_tmp53 ;
  int __cil_tmp54 ;
  u8 __cil_tmp55 ;
  int __cil_tmp56 ;
  u8 __cil_tmp57 ;
  unsigned int __cil_tmp58 ;

  {
  {
#line 329
  tmp = find_section(bdb, 2);
#line 329
  p_defs = (struct bdb_general_definitions *)tmp;
  }
  {
#line 330
  __cil_tmp12 = (struct bdb_general_definitions *)0;
#line 330
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 330
  __cil_tmp14 = (unsigned long )p_defs;
#line 330
  if (__cil_tmp14 == __cil_tmp13) {
    {
#line 331
    drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "No general definition block is found, unable to construct sdvo mapping.\n");
    }
#line 332
    return;
  } else {

  }
  }
  {
#line 339
  __cil_tmp15 = p_defs->child_dev_size;
#line 339
  __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 339
  if (__cil_tmp16 != 33U) {
    {
#line 341
    drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "different child size is found. Invalid.\n");
    }
#line 342
    return;
  } else {

  }
  }
  {
#line 345
  __cil_tmp17 = (void *)p_defs;
#line 345
  block_size = get_blocksize(__cil_tmp17);
#line 347
  __cil_tmp18 = (unsigned long )block_size;
#line 347
  __cil_tmp19 = __cil_tmp18 - 5UL;
#line 347
  __cil_tmp20 = __cil_tmp19 / 33UL;
#line 347
  child_device_num = (int )__cil_tmp20;
#line 349
  count = 0;
#line 350
  i = 0;
  }
#line 350
  goto ldv_37152;
  ldv_37151: 
#line 351
  __cil_tmp21 = (unsigned long )i;
#line 351
  __cil_tmp22 = & p_defs->devices;
#line 351
  __cil_tmp23 = (struct child_device_config *)__cil_tmp22;
#line 351
  p_child = __cil_tmp23 + __cil_tmp21;
  {
#line 352
  __cil_tmp24 = p_child->device_type;
#line 352
  __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 352
  if (__cil_tmp25 == 0U) {
#line 354
    goto ldv_37150;
  } else {

  }
  }
  {
#line 356
  __cil_tmp26 = p_child->slave_addr;
#line 356
  __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 356
  if (__cil_tmp27 != 112U) {
    {
#line 356
    __cil_tmp28 = p_child->slave_addr;
#line 356
    __cil_tmp29 = (unsigned int )__cil_tmp28;
#line 356
    if (__cil_tmp29 != 114U) {
#line 362
      goto ldv_37150;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 364
  __cil_tmp30 = p_child->dvo_port;
#line 364
  __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 364
  if (__cil_tmp31 != 1U) {
    {
#line 364
    __cil_tmp32 = p_child->dvo_port;
#line 364
    __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 364
    if (__cil_tmp33 != 2U) {
      {
#line 367
      drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "Incorrect SDVO port. Skip it \n");
      }
#line 368
      goto ldv_37150;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 370
  __cil_tmp34 = p_child->dvo_port;
#line 370
  __cil_tmp35 = (unsigned int )__cil_tmp34;
#line 370
  if (__cil_tmp35 == 1U) {
#line 370
    tmp___0 = (char *)"SDVOB";
  } else {
#line 370
    tmp___0 = (char *)"SDVOC";
  }
  }
  {
#line 370
  __cil_tmp36 = p_child->slave_addr;
#line 370
  __cil_tmp37 = (int )__cil_tmp36;
#line 370
  drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "the SDVO device with slave addr %2x is found on %s port\n",
                      __cil_tmp37, tmp___0);
#line 375
  __cil_tmp38 = p_child->dvo_port;
#line 375
  __cil_tmp39 = (unsigned long )__cil_tmp38;
#line 375
  __cil_tmp40 = __cil_tmp39 + 1152921504606846975UL;
#line 375
  __cil_tmp41 = & dev_priv->sdvo_mappings;
#line 375
  __cil_tmp42 = (struct sdvo_device_mapping *)__cil_tmp41;
#line 375
  p_mapping = __cil_tmp42 + __cil_tmp40;
  }
  {
#line 376
  __cil_tmp43 = p_mapping->initialized;
#line 376
  __cil_tmp44 = (unsigned int )__cil_tmp43;
#line 376
  if (__cil_tmp44 == 0U) {
    {
#line 377
    p_mapping->dvo_port = p_child->dvo_port;
#line 378
    p_mapping->slave_addr = p_child->slave_addr;
#line 379
    p_mapping->dvo_wiring = p_child->dvo_wiring;
#line 380
    p_mapping->ddc_pin = p_child->ddc_pin;
#line 381
    p_mapping->i2c_pin = p_child->i2c_pin;
#line 382
    p_mapping->i2c_speed = p_child->i2c_speed;
#line 383
    p_mapping->initialized = (u8 )1U;
#line 384
    __cil_tmp45 = p_mapping->dvo_port;
#line 384
    __cil_tmp46 = (int )__cil_tmp45;
#line 384
    __cil_tmp47 = p_mapping->slave_addr;
#line 384
    __cil_tmp48 = (int )__cil_tmp47;
#line 384
    __cil_tmp49 = p_mapping->dvo_wiring;
#line 384
    __cil_tmp50 = (int )__cil_tmp49;
#line 384
    __cil_tmp51 = p_mapping->ddc_pin;
#line 384
    __cil_tmp52 = (int )__cil_tmp51;
#line 384
    __cil_tmp53 = p_mapping->i2c_pin;
#line 384
    __cil_tmp54 = (int )__cil_tmp53;
#line 384
    __cil_tmp55 = p_mapping->i2c_speed;
#line 384
    __cil_tmp56 = (int )__cil_tmp55;
#line 384
    drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d, i2c_speed=%d\n",
                        __cil_tmp46, __cil_tmp48, __cil_tmp50, __cil_tmp52, __cil_tmp54,
                        __cil_tmp56);
    }
  } else {
    {
#line 392
    drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "Maybe one SDVO port is shared by two SDVO device.\n");
    }
  }
  }
  {
#line 395
  __cil_tmp57 = p_child->slave2_addr;
#line 395
  __cil_tmp58 = (unsigned int )__cil_tmp57;
#line 395
  if (__cil_tmp58 != 0U) {
    {
#line 398
    drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs.\n");
    }
  } else {

  }
  }
#line 401
  count = count + 1;
  ldv_37150: 
#line 350
  i = i + 1;
  ldv_37152: ;
#line 350
  if (i < child_device_num) {
#line 351
    goto ldv_37151;
  } else {
#line 353
    goto ldv_37153;
  }
  ldv_37153: ;
#line 404
  if (count == 0) {
    {
#line 406
    drm_ut_debug_printk(4U, "drm", "parse_sdvo_device_mapping", "No SDVO device info is found in VBT\n");
    }
  } else {

  }
#line 408
  return;
}
}
#line 412 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_driver_features(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct drm_device *dev ;
  struct bdb_driver_features *driver___0 ;
  void *tmp ;
  struct bdb_driver_features *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  int __cil_tmp9 ;
  unsigned char *__cil_tmp10 ;
  unsigned char *__cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned char *__cil_tmp14 ;
  unsigned char *__cil_tmp15 ;
  unsigned char __cil_tmp16 ;
  unsigned int __cil_tmp17 ;

  {
  {
#line 415
  dev = dev_priv->dev;
#line 418
  tmp = find_section(bdb, 12);
#line 418
  driver___0 = (struct bdb_driver_features *)tmp;
  }
  {
#line 419
  __cil_tmp6 = (struct bdb_driver_features *)0;
#line 419
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 419
  __cil_tmp8 = (unsigned long )driver___0;
#line 419
  if (__cil_tmp8 == __cil_tmp7) {
#line 420
    return;
  } else {

  }
  }
  {
#line 422
  __cil_tmp9 = dev->pci_device;
#line 422
  if (__cil_tmp9 == 70) {
    {
#line 422
    __cil_tmp10 = (unsigned char *)driver___0;
#line 422
    __cil_tmp11 = __cil_tmp10 + 8UL;
#line 422
    __cil_tmp12 = *__cil_tmp11;
#line 422
    __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 422
    if (__cil_tmp13 == 24U) {
#line 424
      dev_priv->edp.support = (bool )1;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 426
  __cil_tmp14 = (unsigned char *)driver___0;
#line 426
  __cil_tmp15 = __cil_tmp14 + 7UL;
#line 426
  __cil_tmp16 = *__cil_tmp15;
#line 426
  __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 426
  if (__cil_tmp17 != 0U) {
#line 427
    dev_priv->render_reclock_avail = (bool )1;
  } else {

  }
  }
#line 428
  return;
}
}
#line 431 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_edp(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct bdb_edp *edp ;
  struct edp_power_seq *edp_pps ;
  struct edp_link_params *edp_link_params ;
  void *tmp ;
  struct bdb_edp *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct drm_device *__cil_tmp10 ;
  int __cil_tmp11 ;
  bool __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  u32 __cil_tmp15 ;
  u32 __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  u32 __cil_tmp20 ;
  u32 __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  u32 __cil_tmp25 ;
  u32 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  struct edp_power_seq (*__cil_tmp30)[16U] ;
  struct edp_power_seq *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  struct edp_link_params (*__cil_tmp33)[16U] ;
  struct edp_link_params *__cil_tmp34 ;
  unsigned char *__cil_tmp35 ;
  unsigned char *__cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned char __cil_tmp39 ;
  int __cil_tmp40 ;
  unsigned char __cil_tmp41 ;
  int __cil_tmp42 ;
  unsigned char __cil_tmp43 ;
  int __cil_tmp44 ;
  unsigned char __cil_tmp45 ;
  int __cil_tmp46 ;
  unsigned char __cil_tmp47 ;
  int __cil_tmp48 ;
  unsigned char __cil_tmp49 ;
  int __cil_tmp50 ;
  unsigned char __cil_tmp51 ;
  int __cil_tmp52 ;
  unsigned char __cil_tmp53 ;
  int __cil_tmp54 ;
  unsigned char __cil_tmp55 ;
  int __cil_tmp56 ;
  unsigned char __cil_tmp57 ;
  int __cil_tmp58 ;
  unsigned char __cil_tmp59 ;
  int __cil_tmp60 ;

  {
  {
#line 437
  tmp = find_section(bdb, 27);
#line 437
  edp = (struct bdb_edp *)tmp;
  }
  {
#line 438
  __cil_tmp7 = (struct bdb_edp *)0;
#line 438
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 438
  __cil_tmp9 = (unsigned long )edp;
#line 438
  if (__cil_tmp9 == __cil_tmp8) {
    {
#line 439
    __cil_tmp10 = dev_priv->dev;
#line 439
    __cil_tmp11 = __cil_tmp10->pci_device;
#line 439
    if (__cil_tmp11 == 70) {
      {
#line 439
      __cil_tmp12 = dev_priv->edp.support;
#line 439
      if ((int )__cil_tmp12) {
        {
#line 440
        __cil_tmp13 = dev_priv->edp.bpp;
#line 440
        drm_ut_debug_printk(4U, "drm", "parse_edp", "No eDP BDB found but eDP panel supported, assume %dbpp panel color depth.\n",
                            __cil_tmp13);
        }
      } else {

      }
      }
    } else {

    }
    }
#line 445
    return;
  } else {

  }
  }
  {
#line 449
  __cil_tmp14 = panel_type * 2;
#line 449
  __cil_tmp15 = edp->color_depth;
#line 449
  __cil_tmp16 = __cil_tmp15 >> __cil_tmp14;
#line 449
  __cil_tmp17 = __cil_tmp16 & 3U;
#line 449
  __cil_tmp18 = (int )__cil_tmp17;
#line 449
  if (__cil_tmp18 == 0) {
#line 449
    goto case_0;
  } else {
    {
#line 452
    __cil_tmp19 = panel_type * 2;
#line 452
    __cil_tmp20 = edp->color_depth;
#line 452
    __cil_tmp21 = __cil_tmp20 >> __cil_tmp19;
#line 452
    __cil_tmp22 = __cil_tmp21 & 3U;
#line 452
    __cil_tmp23 = (int )__cil_tmp22;
#line 452
    if (__cil_tmp23 == 1) {
#line 452
      goto case_1;
    } else {
      {
#line 455
      __cil_tmp24 = panel_type * 2;
#line 455
      __cil_tmp25 = edp->color_depth;
#line 455
      __cil_tmp26 = __cil_tmp25 >> __cil_tmp24;
#line 455
      __cil_tmp27 = __cil_tmp26 & 3U;
#line 455
      __cil_tmp28 = (int )__cil_tmp27;
#line 455
      if (__cil_tmp28 == 2) {
#line 455
        goto case_2;
      } else
#line 448
      if (0) {
        case_0: 
#line 450
        dev_priv->edp.bpp = 18;
#line 451
        goto ldv_37169;
        case_1: 
#line 453
        dev_priv->edp.bpp = 24;
#line 454
        goto ldv_37169;
        case_2: 
#line 456
        dev_priv->edp.bpp = 30;
#line 457
        goto ldv_37169;
      } else {

      }
      }
    }
    }
  }
  }
  ldv_37169: 
#line 461
  __cil_tmp29 = (unsigned long )panel_type;
#line 461
  __cil_tmp30 = & edp->power_seqs;
#line 461
  __cil_tmp31 = (struct edp_power_seq *)__cil_tmp30;
#line 461
  edp_pps = __cil_tmp31 + __cil_tmp29;
#line 462
  __cil_tmp32 = (unsigned long )panel_type;
#line 462
  __cil_tmp33 = & edp->link_params;
#line 462
  __cil_tmp34 = (struct edp_link_params *)__cil_tmp33;
#line 462
  edp_link_params = __cil_tmp34 + __cil_tmp32;
#line 464
  dev_priv->edp.pps = *edp_pps;
  {
#line 466
  __cil_tmp35 = (unsigned char *)edp_link_params;
#line 466
  __cil_tmp36 = __cil_tmp35 + 0UL;
#line 466
  __cil_tmp37 = *__cil_tmp36;
#line 466
  __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 466
  if (__cil_tmp38 != 0U) {
#line 466
    dev_priv->edp.rate = 10;
  } else {
#line 466
    dev_priv->edp.rate = 6;
  }
  }
  {
#line 469
  __cil_tmp39 = edp_link_params->lanes;
#line 469
  __cil_tmp40 = (int )__cil_tmp39;
#line 469
  if (__cil_tmp40 == 0) {
#line 469
    goto case_0___0;
  } else {
    {
#line 472
    __cil_tmp41 = edp_link_params->lanes;
#line 472
    __cil_tmp42 = (int )__cil_tmp41;
#line 472
    if (__cil_tmp42 == 1) {
#line 472
      goto case_1___0;
    } else {
      {
#line 475
      __cil_tmp43 = edp_link_params->lanes;
#line 475
      __cil_tmp44 = (int )__cil_tmp43;
#line 475
      if (__cil_tmp44 == 3) {
#line 475
        goto case_3;
      } else {
#line 476
        goto switch_default;
#line 468
        if (0) {
          case_0___0: 
#line 470
          dev_priv->edp.lanes = 1;
#line 471
          goto ldv_37173;
          case_1___0: 
#line 473
          dev_priv->edp.lanes = 2;
#line 474
          goto ldv_37173;
          case_3: ;
          switch_default: 
#line 477
          dev_priv->edp.lanes = 4;
#line 478
          goto ldv_37173;
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_37173: ;
  {
#line 481
  __cil_tmp45 = edp_link_params->preemphasis;
#line 481
  __cil_tmp46 = (int )__cil_tmp45;
#line 481
  if (__cil_tmp46 == 0) {
#line 481
    goto case_0___1;
  } else {
    {
#line 484
    __cil_tmp47 = edp_link_params->preemphasis;
#line 484
    __cil_tmp48 = (int )__cil_tmp47;
#line 484
    if (__cil_tmp48 == 1) {
#line 484
      goto case_1___1;
    } else {
      {
#line 487
      __cil_tmp49 = edp_link_params->preemphasis;
#line 487
      __cil_tmp50 = (int )__cil_tmp49;
#line 487
      if (__cil_tmp50 == 2) {
#line 487
        goto case_2___0;
      } else {
        {
#line 490
        __cil_tmp51 = edp_link_params->preemphasis;
#line 490
        __cil_tmp52 = (int )__cil_tmp51;
#line 490
        if (__cil_tmp52 == 3) {
#line 490
          goto case_3___0;
        } else
#line 480
        if (0) {
          case_0___1: 
#line 482
          dev_priv->edp.preemphasis = 0;
#line 483
          goto ldv_37178;
          case_1___1: 
#line 485
          dev_priv->edp.preemphasis = 8;
#line 486
          goto ldv_37178;
          case_2___0: 
#line 488
          dev_priv->edp.preemphasis = 16;
#line 489
          goto ldv_37178;
          case_3___0: 
#line 491
          dev_priv->edp.preemphasis = 24;
#line 492
          goto ldv_37178;
        } else {

        }
        }
      }
      }
    }
    }
  }
  }
  ldv_37178: ;
  {
#line 495
  __cil_tmp53 = edp_link_params->vswing;
#line 495
  __cil_tmp54 = (int )__cil_tmp53;
#line 495
  if (__cil_tmp54 == 0) {
#line 495
    goto case_0___2;
  } else {
    {
#line 498
    __cil_tmp55 = edp_link_params->vswing;
#line 498
    __cil_tmp56 = (int )__cil_tmp55;
#line 498
    if (__cil_tmp56 == 1) {
#line 498
      goto case_1___2;
    } else {
      {
#line 501
      __cil_tmp57 = edp_link_params->vswing;
#line 501
      __cil_tmp58 = (int )__cil_tmp57;
#line 501
      if (__cil_tmp58 == 2) {
#line 501
        goto case_2___1;
      } else {
        {
#line 504
        __cil_tmp59 = edp_link_params->vswing;
#line 504
        __cil_tmp60 = (int )__cil_tmp59;
#line 504
        if (__cil_tmp60 == 3) {
#line 504
          goto case_3___1;
        } else
#line 494
        if (0) {
          case_0___2: 
#line 496
          dev_priv->edp.vswing = 0;
#line 497
          goto ldv_37183;
          case_1___2: 
#line 499
          dev_priv->edp.vswing = 1;
#line 500
          goto ldv_37183;
          case_2___1: 
#line 502
          dev_priv->edp.vswing = 2;
#line 503
          goto ldv_37183;
          case_3___1: 
#line 505
          dev_priv->edp.vswing = 3;
#line 506
          goto ldv_37183;
        } else {

        }
        }
      }
      }
    }
    }
  }
  }
  ldv_37183: ;
#line 509
  return;
}
}
#line 511 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void parse_device_mapping(struct drm_i915_private *dev_priv , struct bdb_header *bdb ) 
{ struct bdb_general_definitions *p_defs ;
  struct child_device_config *p_child ;
  struct child_device_config *child_dev_ptr ;
  int i ;
  int child_device_num ;
  int count ;
  u16 block_size ;
  void *tmp ;
  void *tmp___0 ;
  size_t __len ;
  void *__ret ;
  struct bdb_general_definitions *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  void *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct child_device_config (*__cil_tmp24)[0U] ;
  struct child_device_config *__cil_tmp25 ;
  u16 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  struct child_device_config *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  struct child_device_config *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  struct child_device_config (*__cil_tmp35)[0U] ;
  struct child_device_config *__cil_tmp36 ;
  u16 __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  struct child_device_config *__cil_tmp40 ;
  void *__cil_tmp41 ;
  void const   *__cil_tmp42 ;
  void *__cil_tmp43 ;
  void const   *__cil_tmp44 ;

  {
  {
#line 519
  tmp = find_section(bdb, 2);
#line 519
  p_defs = (struct bdb_general_definitions *)tmp;
  }
  {
#line 520
  __cil_tmp14 = (struct bdb_general_definitions *)0;
#line 520
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 520
  __cil_tmp16 = (unsigned long )p_defs;
#line 520
  if (__cil_tmp16 == __cil_tmp15) {
    {
#line 521
    drm_ut_debug_printk(4U, "drm", "parse_device_mapping", "No general definition block is found, no devices defined.\n");
    }
#line 522
    return;
  } else {

  }
  }
  {
#line 529
  __cil_tmp17 = p_defs->child_dev_size;
#line 529
  __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 529
  if (__cil_tmp18 != 33U) {
    {
#line 531
    drm_ut_debug_printk(4U, "drm", "parse_device_mapping", "different child size is found. Invalid.\n");
    }
#line 532
    return;
  } else {

  }
  }
  {
#line 535
  __cil_tmp19 = (void *)p_defs;
#line 535
  block_size = get_blocksize(__cil_tmp19);
#line 537
  __cil_tmp20 = (unsigned long )block_size;
#line 537
  __cil_tmp21 = __cil_tmp20 - 5UL;
#line 537
  __cil_tmp22 = __cil_tmp21 / 33UL;
#line 537
  child_device_num = (int )__cil_tmp22;
#line 539
  count = 0;
#line 541
  i = 0;
  }
#line 541
  goto ldv_37201;
  ldv_37200: 
#line 542
  __cil_tmp23 = (unsigned long )i;
#line 542
  __cil_tmp24 = & p_defs->devices;
#line 542
  __cil_tmp25 = (struct child_device_config *)__cil_tmp24;
#line 542
  p_child = __cil_tmp25 + __cil_tmp23;
  {
#line 543
  __cil_tmp26 = p_child->device_type;
#line 543
  __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 543
  if (__cil_tmp27 == 0U) {
#line 545
    goto ldv_37199;
  } else {

  }
  }
#line 547
  count = count + 1;
  ldv_37199: 
#line 541
  i = i + 1;
  ldv_37201: ;
#line 541
  if (i < child_device_num) {
#line 542
    goto ldv_37200;
  } else {
#line 544
    goto ldv_37202;
  }
  ldv_37202: ;
#line 549
  if (count == 0) {
    {
#line 550
    drm_ut_debug_printk(4U, "drm", "parse_device_mapping", "no child dev is parsed from VBT \n");
    }
#line 551
    return;
  } else {

  }
  {
#line 553
  __cil_tmp28 = (unsigned long )count;
#line 553
  __cil_tmp29 = __cil_tmp28 * 33UL;
#line 553
  tmp___0 = kzalloc(__cil_tmp29, 208U);
#line 553
  dev_priv->child_dev = (struct child_device_config *)tmp___0;
  }
  {
#line 554
  __cil_tmp30 = (struct child_device_config *)0;
#line 554
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 554
  __cil_tmp32 = dev_priv->child_dev;
#line 554
  __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 554
  if (__cil_tmp33 == __cil_tmp31) {
    {
#line 555
    drm_ut_debug_printk(4U, "drm", "parse_device_mapping", "No memory space for child device\n");
    }
#line 556
    return;
  } else {

  }
  }
#line 559
  dev_priv->child_dev_num = count;
#line 560
  count = 0;
#line 561
  i = 0;
#line 561
  goto ldv_37208;
  ldv_37207: 
#line 562
  __cil_tmp34 = (unsigned long )i;
#line 562
  __cil_tmp35 = & p_defs->devices;
#line 562
  __cil_tmp36 = (struct child_device_config *)__cil_tmp35;
#line 562
  p_child = __cil_tmp36 + __cil_tmp34;
  {
#line 563
  __cil_tmp37 = p_child->device_type;
#line 563
  __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 563
  if (__cil_tmp38 == 0U) {
#line 565
    goto ldv_37203;
  } else {

  }
  }
#line 567
  __cil_tmp39 = (unsigned long )count;
#line 567
  __cil_tmp40 = dev_priv->child_dev;
#line 567
  child_dev_ptr = __cil_tmp40 + __cil_tmp39;
#line 568
  count = count + 1;
#line 569
  __len = 33UL;
#line 569
  if (__len > 63UL) {
    {
#line 569
    __cil_tmp41 = (void *)child_dev_ptr;
#line 569
    __cil_tmp42 = (void const   *)p_child;
#line 569
    __ret = __memcpy(__cil_tmp41, __cil_tmp42, __len);
    }
  } else {
    {
#line 569
    __cil_tmp43 = (void *)child_dev_ptr;
#line 569
    __cil_tmp44 = (void const   *)p_child;
#line 569
    __ret = __builtin_memcpy(__cil_tmp43, __cil_tmp44, __len);
    }
  }
  ldv_37203: 
#line 561
  i = i + 1;
  ldv_37208: ;
#line 561
  if (i < child_device_num) {
#line 562
    goto ldv_37207;
  } else {
#line 564
    goto ldv_37209;
  }
  ldv_37209: ;
#line 572
  return;
}
}
#line 576 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
static void init_vbt_defaults(struct drm_i915_private *dev_priv ) 
{ struct drm_device *dev ;
  bool __cil_tmp3 ;
  int __cil_tmp4 ;

  {
  {
#line 578
  dev = dev_priv->dev;
#line 580
  dev_priv->crt_ddc_pin = 2;
#line 583
  dev_priv->lvds_dither = (unsigned char)1;
#line 584
  dev_priv->lvds_vbt = (unsigned char)0;
#line 587
  dev_priv->sdvo_lvds_vbt_mode = (struct drm_display_mode *)0;
#line 590
  dev_priv->int_tv_support = (unsigned char)1;
#line 591
  dev_priv->int_crt_support = (unsigned char)1;
#line 594
  dev_priv->lvds_use_ssc = (unsigned char)1;
#line 595
  __cil_tmp3 = (bool )1;
#line 595
  dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, __cil_tmp3);
#line 596
  __cil_tmp4 = dev_priv->lvds_ssc_freq;
#line 596
  drm_ut_debug_printk(1U, "drm", "init_vbt_defaults", "Set default to SSC at %dMHz\n",
                      __cil_tmp4);
#line 599
  dev_priv->edp.bpp = 18;
  }
#line 600
  return;
}
}
#line 612 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
bool intel_parse_bios(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct pci_dev *pdev ;
  struct bdb_header *bdb ;
  u8 *bios ;
  struct vbt_header *vbt ;
  int tmp ;
  struct vbt_header *vbt___0 ;
  size_t size ;
  int i ;
  void *tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp13 ;
  void *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  void *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  void *__cil_tmp18 ;
  u8 (*__cil_tmp19)[20U] ;
  void const   *__cil_tmp20 ;
  void const   *__cil_tmp21 ;
  u8 (*__cil_tmp22)[20U] ;
  u8 *__cil_tmp23 ;
  u32 __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct bdb_header *__cil_tmp26 ;
  struct bdb_header *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  u8 *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  void const   *__cil_tmp34 ;
  void const   *__cil_tmp35 ;
  void const   *__cil_tmp36 ;
  unsigned long __cil_tmp37 ;
  struct vbt_header *__cil_tmp38 ;
  int __cil_tmp39 ;
  size_t __cil_tmp40 ;
  struct vbt_header *__cil_tmp41 ;
  unsigned long __cil_tmp42 ;
  unsigned long __cil_tmp43 ;
  void *__cil_tmp44 ;
  u32 __cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  unsigned long __cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  u8 *__cil_tmp49 ;
  u8 *__cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  void *__cil_tmp53 ;

  {
  {
#line 614
  __cil_tmp13 = dev->dev_private;
#line 614
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 615
  pdev = dev->pdev;
#line 616
  bdb = (struct bdb_header *)0;
#line 617
  bios = (u8 *)0;
#line 619
  init_vbt_defaults(dev_priv);
  }
  {
#line 622
  __cil_tmp14 = (void *)0;
#line 622
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 622
  __cil_tmp16 = dev_priv->opregion.vbt;
#line 622
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 622
  if (__cil_tmp17 != __cil_tmp15) {
    {
#line 623
    __cil_tmp18 = dev_priv->opregion.vbt;
#line 623
    vbt = (struct vbt_header *)__cil_tmp18;
#line 624
    __cil_tmp19 = & vbt->signature;
#line 624
    __cil_tmp20 = (void const   *)__cil_tmp19;
#line 624
    __cil_tmp21 = (void const   *)"$VBT";
#line 624
    tmp = memcmp(__cil_tmp20, __cil_tmp21, 4UL);
    }
#line 624
    if (tmp == 0) {
      {
#line 625
      __cil_tmp22 = & vbt->signature;
#line 625
      __cil_tmp23 = (u8 *)__cil_tmp22;
#line 625
      drm_ut_debug_printk(2U, "drm", "intel_parse_bios", "Using VBT from OpRegion: %20s\n",
                          __cil_tmp23);
#line 627
      __cil_tmp24 = vbt->bdb_offset;
#line 627
      __cil_tmp25 = (unsigned long )__cil_tmp24;
#line 627
      __cil_tmp26 = (struct bdb_header *)vbt;
#line 627
      bdb = __cil_tmp26 + __cil_tmp25;
      }
    } else {
#line 629
      dev_priv->opregion.vbt = (void *)0;
    }
  } else {

  }
  }
  {
#line 632
  __cil_tmp27 = (struct bdb_header *)0;
#line 632
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 632
  __cil_tmp29 = (unsigned long )bdb;
#line 632
  if (__cil_tmp29 == __cil_tmp28) {
    {
#line 633
    vbt___0 = (struct vbt_header *)0;
#line 637
    tmp___0 = pci_map_rom(pdev, & size);
#line 637
    bios = (u8 *)tmp___0;
    }
    {
#line 638
    __cil_tmp30 = (u8 *)0;
#line 638
    __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 638
    __cil_tmp32 = (unsigned long )bios;
#line 638
    if (__cil_tmp32 == __cil_tmp31) {
#line 639
      return ((bool )1);
    } else {

    }
    }
#line 642
    i = 0;
#line 642
    goto ldv_37229;
    ldv_37228: 
    {
#line 643
    __cil_tmp33 = (unsigned long )i;
#line 643
    __cil_tmp34 = (void const   *)bios;
#line 643
    __cil_tmp35 = __cil_tmp34 + __cil_tmp33;
#line 643
    __cil_tmp36 = (void const   *)"$VBT";
#line 643
    tmp___1 = memcmp(__cil_tmp35, __cil_tmp36, 4UL);
    }
#line 643
    if (tmp___1 == 0) {
#line 644
      __cil_tmp37 = (unsigned long )i;
#line 644
      __cil_tmp38 = (struct vbt_header *)bios;
#line 644
      vbt___0 = __cil_tmp38 + __cil_tmp37;
#line 645
      goto ldv_37227;
    } else {

    }
#line 642
    i = i + 1;
    ldv_37229: ;
    {
#line 642
    __cil_tmp39 = i + 4;
#line 642
    __cil_tmp40 = (size_t )__cil_tmp39;
#line 642
    if (__cil_tmp40 < size) {
#line 643
      goto ldv_37228;
    } else {
#line 645
      goto ldv_37227;
    }
    }
    ldv_37227: ;
    {
#line 649
    __cil_tmp41 = (struct vbt_header *)0;
#line 649
    __cil_tmp42 = (unsigned long )__cil_tmp41;
#line 649
    __cil_tmp43 = (unsigned long )vbt___0;
#line 649
    if (__cil_tmp43 == __cil_tmp42) {
      {
#line 650
      drm_err("intel_parse_bios", "VBT signature missing\n");
#line 651
      __cil_tmp44 = (void *)bios;
#line 651
      pci_unmap_rom(pdev, __cil_tmp44);
      }
#line 652
      return ((bool )1);
    } else {

    }
    }
#line 655
    __cil_tmp45 = vbt___0->bdb_offset;
#line 655
    __cil_tmp46 = (unsigned long )__cil_tmp45;
#line 655
    __cil_tmp47 = (unsigned long )i;
#line 655
    __cil_tmp48 = __cil_tmp47 + __cil_tmp46;
#line 655
    __cil_tmp49 = bios + __cil_tmp48;
#line 655
    bdb = (struct bdb_header *)__cil_tmp49;
  } else {

  }
  }
  {
#line 659
  parse_general_features(dev_priv, bdb);
#line 660
  parse_general_definitions(dev_priv, bdb);
#line 661
  parse_lfp_panel_data(dev_priv, bdb);
#line 662
  parse_sdvo_panel_data(dev_priv, bdb);
#line 663
  parse_sdvo_device_mapping(dev_priv, bdb);
#line 664
  parse_device_mapping(dev_priv, bdb);
#line 665
  parse_driver_features(dev_priv, bdb);
#line 666
  parse_edp(dev_priv, bdb);
  }
  {
#line 668
  __cil_tmp50 = (u8 *)0;
#line 668
  __cil_tmp51 = (unsigned long )__cil_tmp50;
#line 668
  __cil_tmp52 = (unsigned long )bios;
#line 668
  if (__cil_tmp52 != __cil_tmp51) {
    {
#line 669
    __cil_tmp53 = (void *)bios;
#line 669
    pci_unmap_rom(pdev, __cil_tmp53);
    }
  } else {

  }
  }
#line 671
  return ((bool )0);
}
}
#line 677 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_bios.c.p"
void intel_setup_bios(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  u32 tmp___0 ;
  void *__cil_tmp5 ;

  {
  {
#line 679
  __cil_tmp5 = dev->dev_private;
#line 679
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 682
  tmp = i915_read32___9(dev_priv, 397832U);
  }
#line 682
  if (tmp == 0U) {
    {
#line 682
    tmp___0 = i915_read32___9(dev_priv, 397836U);
    }
#line 682
    if (tmp___0 == 0U) {
      {
#line 684
      i915_write32___7(dev_priv, 397832U, 26216400U);
#line 687
      i915_write32___7(dev_priv, 397836U, 22939600U);
      }
    } else {

    }
  } else {

  }
#line 689
  return;
}
}
#line 27 "include/linux/string.h"
extern char *strncpy(char * , char const   * , __kernel_size_t  ) ;
#line 431 "include/linux/i2c.h"
extern int i2c_del_adapter(struct i2c_adapter * ) ;
#line 701 "include/drm/drm_crtc.h"
extern int drm_connector_property_set_value(struct drm_connector * , struct drm_property * ,
                                            uint64_t  ) ;
#line 789
extern bool drm_detect_monitor_audio(struct edid * ) ;
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___10(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36374: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36374;
      } else {
#line 390
        goto ldv_36375;
      }
      }
      ldv_36375: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___10(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___10(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___8(struct drm_i915_private *dev_priv , u32 reg ,
                                      u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___10(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 239 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
void intel_attach_force_audio_property(struct drm_connector *connector ) ;
#line 240
void intel_attach_broadcast_rgb_property(struct drm_connector *connector ) ;
#line 186 "include/drm/drm_dp_helper.h"
extern int i2c_dp_aux_add_bus(struct i2c_adapter * ) ;
#line 78 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool is_edp(struct intel_dp *intel_dp ) 
{ int __cil_tmp2 ;
  int __cil_tmp3 ;

  {
  {
#line 80
  __cil_tmp2 = intel_dp->base.type;
#line 80
  __cil_tmp3 = __cil_tmp2 == 8;
#line 80
  return ((bool )__cil_tmp3);
  }
}
}
#line 91 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool is_pch_edp(struct intel_dp *intel_dp ) 
{ 

  {
#line 93
  return (intel_dp->is_pch_edp);
}
}
#line 96 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder ) 
{ struct drm_encoder  const  *__mptr ;

  {
#line 98
  __mptr = (struct drm_encoder  const  *)encoder;
#line 98
  return ((struct intel_dp *)__mptr);
}
}
#line 101 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static struct intel_dp *intel_attached_dp(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 103
  tmp = intel_attached_encoder(connector);
#line 103
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 103
  return ((struct intel_dp *)__mptr);
}
}
#line 114 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
bool intel_encoder_is_pch_edp(struct drm_encoder *encoder ) 
{ struct intel_dp *intel_dp ;
  bool tmp ;
  struct drm_encoder *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;

  {
  {
#line 118
  __cil_tmp4 = (struct drm_encoder *)0;
#line 118
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 118
  __cil_tmp6 = (unsigned long )encoder;
#line 118
  if (__cil_tmp6 == __cil_tmp5) {
#line 119
    return ((bool )0);
  } else {

  }
  }
  {
#line 121
  intel_dp = enc_to_intel_dp(encoder);
#line 123
  tmp = is_pch_edp(intel_dp);
  }
#line 123
  return (tmp);
}
}
#line 126
static void intel_dp_start_link_train(struct intel_dp *intel_dp ) ;
#line 127
static void intel_dp_complete_link_train(struct intel_dp *intel_dp ) ;
#line 128
static void intel_dp_link_down(struct intel_dp *intel_dp ) ;
#line 131 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
void intel_edp_link_config(struct intel_encoder *intel_encoder , int *lane_num , int *link_bw ) 
{ struct intel_dp *intel_dp ;
  struct intel_encoder  const  *__mptr ;
  uint8_t __cil_tmp6 ;
  uint8_t __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  uint8_t __cil_tmp9 ;
  unsigned int __cil_tmp10 ;

  {
#line 134
  __mptr = (struct intel_encoder  const  *)intel_encoder;
#line 134
  intel_dp = (struct intel_dp *)__mptr;
#line 136
  __cil_tmp6 = intel_dp->lane_count;
#line 136
  *lane_num = (int )__cil_tmp6;
  {
#line 137
  __cil_tmp7 = intel_dp->link_bw;
#line 137
  __cil_tmp8 = (unsigned int )__cil_tmp7;
#line 137
  if (__cil_tmp8 == 6U) {
#line 138
    *link_bw = 162000;
  } else {
    {
#line 139
    __cil_tmp9 = intel_dp->link_bw;
#line 139
    __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 139
    if (__cil_tmp10 == 10U) {
#line 140
      *link_bw = 270000;
    } else {

    }
    }
  }
  }
#line 141
  return;
}
}
#line 144 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_max_lane_count(struct intel_dp *intel_dp ) 
{ int max_lane_count ;
  uint8_t __cil_tmp3 ;
  unsigned int __cil_tmp4 ;
  uint8_t __cil_tmp5 ;
  int __cil_tmp6 ;

  {
#line 146
  max_lane_count = 4;
  {
#line 148
  __cil_tmp3 = intel_dp->dpcd[0];
#line 148
  __cil_tmp4 = (unsigned int )__cil_tmp3;
#line 148
  if (__cil_tmp4 > 16U) {
#line 149
    __cil_tmp5 = intel_dp->dpcd[2];
#line 149
    __cil_tmp6 = (int )__cil_tmp5;
#line 149
    max_lane_count = __cil_tmp6 & 31;
#line 151
    if (max_lane_count == 1) {
#line 151
      goto case_1;
    } else
#line 151
    if (max_lane_count == 2) {
#line 151
      goto case_2;
    } else
#line 151
    if (max_lane_count == 4) {
#line 151
      goto case_4;
    } else {
#line 153
      goto switch_default;
#line 150
      if (0) {
        case_1: ;
        case_2: ;
        case_4: ;
#line 152
        goto ldv_37615;
        switch_default: 
#line 154
        max_lane_count = 4;
      } else {

      }
    }
    ldv_37615: ;
  } else {

  }
  }
#line 157
  return (max_lane_count);
}
}
#line 161 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_max_link_bw(struct intel_dp *intel_dp ) 
{ int max_link_bw ;
  uint8_t __cil_tmp3 ;

  {
#line 163
  __cil_tmp3 = intel_dp->dpcd[1];
#line 163
  max_link_bw = (int )__cil_tmp3;
#line 166
  if (max_link_bw == 6) {
#line 166
    goto case_6;
  } else
#line 167
  if (max_link_bw == 10) {
#line 167
    goto case_10;
  } else {
#line 169
    goto switch_default;
#line 165
    if (0) {
      case_6: ;
      case_10: ;
#line 168
      goto ldv_37623;
      switch_default: 
#line 170
      max_link_bw = 6;
#line 171
      goto ldv_37623;
    } else {

    }
  }
  ldv_37623: ;
#line 173
  return (max_link_bw);
}
}
#line 177 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_link_clock(uint8_t link_bw ) 
{ unsigned int __cil_tmp2 ;

  {
  {
#line 179
  __cil_tmp2 = (unsigned int )link_bw;
#line 179
  if (__cil_tmp2 == 10U) {
#line 180
    return (270000);
  } else {
#line 182
    return (162000);
  }
  }
}
}
#line 187 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_link_required(struct drm_device *dev , struct intel_dp *intel_dp ,
                                  int pixel_clock ) 
{ struct drm_i915_private *dev_priv ;
  bool tmp ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;

  {
  {
#line 189
  __cil_tmp6 = dev->dev_private;
#line 189
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 191
  tmp = is_edp(intel_dp);
  }
#line 191
  if ((int )tmp) {
    {
#line 192
    __cil_tmp7 = dev_priv->edp.bpp;
#line 192
    __cil_tmp8 = __cil_tmp7 * pixel_clock;
#line 192
    __cil_tmp9 = __cil_tmp8 + 7;
#line 192
    return (__cil_tmp9 / 8);
    }
  } else {
#line 194
    return (pixel_clock * 3);
  }
}
}
#line 198 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_max_data_rate(int max_link_clock , int max_lanes ) 
{ int __cil_tmp3 ;
  int __cil_tmp4 ;

  {
  {
#line 200
  __cil_tmp3 = max_link_clock * max_lanes;
#line 200
  __cil_tmp4 = __cil_tmp3 * 8;
#line 200
  return (__cil_tmp4 / 10);
  }
}
}
#line 204 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  int max_link_clock ;
  int tmp___0 ;
  int tmp___1 ;
  int max_lanes ;
  int tmp___2 ;
  bool tmp___3 ;
  bool tmp___4 ;
  int tmp___5 ;
  int tmp___6 ;
  int tmp___7 ;
  void *__cil_tmp17 ;
  uint8_t __cil_tmp18 ;
  int __cil_tmp19 ;
  uint8_t __cil_tmp20 ;
  struct drm_display_mode *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct drm_display_mode *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  struct drm_display_mode *__cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  struct drm_display_mode *__cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  struct drm_device *__cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;

  {
  {
#line 207
  tmp = intel_attached_dp(connector);
#line 207
  intel_dp = tmp;
#line 208
  dev = connector->dev;
#line 209
  __cil_tmp17 = dev->dev_private;
#line 209
  dev_priv = (struct drm_i915_private *)__cil_tmp17;
#line 210
  tmp___0 = intel_dp_max_link_bw(intel_dp);
#line 210
  __cil_tmp18 = (uint8_t )tmp___0;
#line 210
  __cil_tmp19 = (int )__cil_tmp18;
#line 210
  __cil_tmp20 = (uint8_t )__cil_tmp19;
#line 210
  tmp___1 = intel_dp_link_clock(__cil_tmp20);
#line 210
  max_link_clock = tmp___1;
#line 211
  tmp___2 = intel_dp_max_lane_count(intel_dp);
#line 211
  max_lanes = tmp___2;
#line 213
  tmp___3 = is_edp(intel_dp);
  }
#line 213
  if ((int )tmp___3) {
    {
#line 213
    __cil_tmp21 = (struct drm_display_mode *)0;
#line 213
    __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 213
    __cil_tmp23 = dev_priv->panel_fixed_mode;
#line 213
    __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 213
    if (__cil_tmp24 != __cil_tmp22) {
      {
#line 214
      __cil_tmp25 = dev_priv->panel_fixed_mode;
#line 214
      __cil_tmp26 = __cil_tmp25->hdisplay;
#line 214
      __cil_tmp27 = mode->hdisplay;
#line 214
      if (__cil_tmp27 > __cil_tmp26) {
#line 215
        return (29);
      } else {

      }
      }
      {
#line 217
      __cil_tmp28 = dev_priv->panel_fixed_mode;
#line 217
      __cil_tmp29 = __cil_tmp28->vdisplay;
#line 217
      __cil_tmp30 = mode->vdisplay;
#line 217
      if (__cil_tmp30 > __cil_tmp29) {
#line 218
        return (29);
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  {
#line 223
  tmp___4 = is_edp(intel_dp);
  }
#line 223
  if (tmp___4) {
#line 223
    tmp___5 = 0;
  } else {
#line 223
    tmp___5 = 1;
  }
#line 223
  if (tmp___5) {
    {
#line 223
    __cil_tmp31 = connector->dev;
#line 223
    __cil_tmp32 = mode->clock;
#line 223
    tmp___6 = intel_dp_link_required(__cil_tmp31, intel_dp, __cil_tmp32);
#line 223
    tmp___7 = intel_dp_max_data_rate(max_link_clock, max_lanes);
    }
#line 223
    if (tmp___6 > tmp___7) {
#line 226
      return (15);
    } else {

    }
  } else {

  }
  {
#line 228
  __cil_tmp33 = mode->clock;
#line 228
  if (__cil_tmp33 <= 9999) {
#line 229
    return (16);
  } else {

  }
  }
#line 231
  return (0);
}
}
#line 235 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint32_t pack_aux(uint8_t *src , int src_bytes ) 
{ int i ;
  uint32_t v ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  uint8_t *__cil_tmp8 ;
  uint8_t __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  unsigned int __cil_tmp11 ;

  {
#line 238
  v = 0U;
#line 240
  if (src_bytes > 4) {
#line 241
    src_bytes = 4;
  } else {

  }
#line 242
  i = 0;
#line 242
  goto ldv_37654;
  ldv_37653: 
#line 243
  __cil_tmp5 = 3 - i;
#line 243
  __cil_tmp6 = __cil_tmp5 * 8;
#line 243
  __cil_tmp7 = (unsigned long )i;
#line 243
  __cil_tmp8 = src + __cil_tmp7;
#line 243
  __cil_tmp9 = *__cil_tmp8;
#line 243
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 243
  __cil_tmp11 = __cil_tmp10 << __cil_tmp6;
#line 243
  v = __cil_tmp11 | v;
#line 242
  i = i + 1;
  ldv_37654: ;
#line 242
  if (i < src_bytes) {
#line 243
    goto ldv_37653;
  } else {
#line 245
    goto ldv_37655;
  }
  ldv_37655: ;
#line 244
  return (v);
}
}
#line 248 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void unpack_aux(uint32_t src , uint8_t *dst , int dst_bytes ) 
{ int i ;
  unsigned long __cil_tmp5 ;
  uint8_t *__cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  uint32_t __cil_tmp9 ;

  {
#line 251
  if (dst_bytes > 4) {
#line 252
    dst_bytes = 4;
  } else {

  }
#line 253
  i = 0;
#line 253
  goto ldv_37663;
  ldv_37662: 
#line 254
  __cil_tmp5 = (unsigned long )i;
#line 254
  __cil_tmp6 = dst + __cil_tmp5;
#line 254
  __cil_tmp7 = 3 - i;
#line 254
  __cil_tmp8 = __cil_tmp7 * 8;
#line 254
  __cil_tmp9 = src >> __cil_tmp8;
#line 254
  *__cil_tmp6 = (uint8_t )__cil_tmp9;
#line 253
  i = i + 1;
  ldv_37663: ;
#line 253
  if (i < dst_bytes) {
#line 254
    goto ldv_37662;
  } else {
#line 256
    goto ldv_37664;
  }
  ldv_37664: ;
#line 258
  return;
}
}
#line 259 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_hrawclk(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  uint32_t clkcfg ;
  void *__cil_tmp4 ;
  unsigned int __cil_tmp5 ;
  int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  int __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  int __cil_tmp20 ;

  {
  {
#line 261
  __cil_tmp4 = dev->dev_private;
#line 261
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 264
  clkcfg = i915_read32___10(dev_priv, 68608U);
  }
  {
#line 266
  __cil_tmp5 = clkcfg & 7U;
#line 266
  __cil_tmp6 = (int )__cil_tmp5;
#line 266
  if (__cil_tmp6 == 5) {
#line 266
    goto case_5;
  } else {
    {
#line 268
    __cil_tmp7 = clkcfg & 7U;
#line 268
    __cil_tmp8 = (int )__cil_tmp7;
#line 268
    if (__cil_tmp8 == 1) {
#line 268
      goto case_1;
    } else {
      {
#line 270
      __cil_tmp9 = clkcfg & 7U;
#line 270
      __cil_tmp10 = (int )__cil_tmp9;
#line 270
      if (__cil_tmp10 == 3) {
#line 270
        goto case_3;
      } else {
        {
#line 272
        __cil_tmp11 = clkcfg & 7U;
#line 272
        __cil_tmp12 = (int )__cil_tmp11;
#line 272
        if (__cil_tmp12 == 2) {
#line 272
          goto case_2;
        } else {
          {
#line 274
          __cil_tmp13 = clkcfg & 7U;
#line 274
          __cil_tmp14 = (int )__cil_tmp13;
#line 274
          if (__cil_tmp14 == 6) {
#line 274
            goto case_6;
          } else {
            {
#line 276
            __cil_tmp15 = clkcfg & 7U;
#line 276
            __cil_tmp16 = (int )__cil_tmp15;
#line 276
            if (__cil_tmp16 == 7) {
#line 276
              goto case_7;
            } else {
              {
#line 279
              __cil_tmp17 = clkcfg & 7U;
#line 279
              __cil_tmp18 = (int )__cil_tmp17;
#line 279
              if (__cil_tmp18 == 4) {
#line 279
                goto case_4;
              } else {
                {
#line 280
                __cil_tmp19 = clkcfg & 7U;
#line 280
                __cil_tmp20 = (int )__cil_tmp19;
#line 280
                if (__cil_tmp20 == 0) {
#line 280
                  goto case_0;
                } else {
#line 282
                  goto switch_default;
#line 265
                  if (0) {
                    case_5: ;
#line 267
                    return (100);
                    case_1: ;
#line 269
                    return (133);
                    case_3: ;
#line 271
                    return (166);
                    case_2: ;
#line 273
                    return (200);
                    case_6: ;
#line 275
                    return (266);
                    case_7: ;
#line 277
                    return (333);
                    case_4: ;
                    case_0: ;
#line 281
                    return (400);
                    switch_default: ;
#line 283
                    return (133);
                  } else {

                  }
                }
                }
              }
              }
            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
}
}
#line 288 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_aux_ch(struct intel_dp *intel_dp , uint8_t *send , int send_bytes ,
                           uint8_t *recv , int recv_size ) 
{ uint32_t output_reg ;
  struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  uint32_t ch_ctl ;
  uint32_t ch_data ;
  int i ;
  int recv_bytes ;
  uint32_t status ;
  uint32_t aux_clock_divider ;
  int try ;
  int precharge ;
  int tmp ;
  bool tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  uint32_t tmp___5 ;
  u32 tmp___6 ;
  void *__cil_tmp25 ;
  void *__cil_tmp26 ;
  struct drm_i915_private *__cil_tmp27 ;
  struct intel_device_info  const  *__cil_tmp28 ;
  u8 __cil_tmp29 ;
  unsigned char __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  void *__cil_tmp32 ;
  struct drm_i915_private *__cil_tmp33 ;
  struct intel_device_info  const  *__cil_tmp34 ;
  u8 __cil_tmp35 ;
  unsigned char __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  void *__cil_tmp38 ;
  struct drm_i915_private *__cil_tmp39 ;
  struct intel_device_info  const  *__cil_tmp40 ;
  u8 __cil_tmp41 ;
  unsigned char __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  void *__cil_tmp44 ;
  struct drm_i915_private *__cil_tmp45 ;
  struct intel_device_info  const  *__cil_tmp46 ;
  unsigned char *__cil_tmp47 ;
  unsigned char *__cil_tmp48 ;
  unsigned char __cil_tmp49 ;
  unsigned int __cil_tmp50 ;
  int __cil_tmp51 ;
  void *__cil_tmp52 ;
  struct drm_i915_private *__cil_tmp53 ;
  struct intel_device_info  const  *__cil_tmp54 ;
  u8 __cil_tmp55 ;
  unsigned char __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  int __cil_tmp58 ;
  unsigned long __cil_tmp59 ;
  uint8_t *__cil_tmp60 ;
  int __cil_tmp61 ;
  uint32_t __cil_tmp62 ;
  uint32_t __cil_tmp63 ;
  int __cil_tmp64 ;
  int __cil_tmp65 ;
  int __cil_tmp66 ;
  int __cil_tmp67 ;
  uint32_t __cil_tmp68 ;
  unsigned int __cil_tmp69 ;
  unsigned int __cil_tmp70 ;
  int __cil_tmp71 ;
  unsigned int __cil_tmp72 ;
  unsigned int __cil_tmp73 ;
  unsigned int __cil_tmp74 ;
  unsigned int __cil_tmp75 ;
  unsigned int __cil_tmp76 ;
  unsigned int __cil_tmp77 ;
  unsigned int __cil_tmp78 ;
  uint32_t __cil_tmp79 ;
  uint32_t __cil_tmp80 ;
  unsigned long __cil_tmp81 ;
  uint8_t *__cil_tmp82 ;
  int __cil_tmp83 ;

  {
  {
#line 292
  output_reg = intel_dp->output_reg;
#line 293
  dev = intel_dp->base.base.dev;
#line 294
  __cil_tmp25 = dev->dev_private;
#line 294
  dev_priv = (struct drm_i915_private *)__cil_tmp25;
#line 295
  ch_ctl = output_reg + 16U;
#line 296
  ch_data = ch_ctl + 4U;
#line 310
  tmp___0 = is_edp(intel_dp);
  }
#line 310
  if ((int )tmp___0) {
    {
#line 310
    tmp___1 = is_pch_edp(intel_dp);
    }
#line 310
    if (tmp___1) {
#line 310
      tmp___2 = 0;
    } else {
#line 310
      tmp___2 = 1;
    }
#line 310
    if (tmp___2) {
      {
#line 311
      __cil_tmp26 = dev->dev_private;
#line 311
      __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
#line 311
      __cil_tmp28 = __cil_tmp27->info;
#line 311
      __cil_tmp29 = __cil_tmp28->gen;
#line 311
      __cil_tmp30 = (unsigned char )__cil_tmp29;
#line 311
      __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 311
      if (__cil_tmp31 == 6U) {
#line 312
        aux_clock_divider = 200U;
      } else {
#line 314
        aux_clock_divider = 225U;
      }
      }
    } else {
#line 310
      goto _L;
    }
  } else {
    _L: 
    {
#line 315
    __cil_tmp32 = dev->dev_private;
#line 315
    __cil_tmp33 = (struct drm_i915_private *)__cil_tmp32;
#line 315
    __cil_tmp34 = __cil_tmp33->info;
#line 315
    __cil_tmp35 = __cil_tmp34->gen;
#line 315
    __cil_tmp36 = (unsigned char )__cil_tmp35;
#line 315
    __cil_tmp37 = (unsigned int )__cil_tmp36;
#line 315
    if (__cil_tmp37 == 5U) {
#line 316
      aux_clock_divider = 62U;
    } else {
      {
#line 315
      __cil_tmp38 = dev->dev_private;
#line 315
      __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
#line 315
      __cil_tmp40 = __cil_tmp39->info;
#line 315
      __cil_tmp41 = __cil_tmp40->gen;
#line 315
      __cil_tmp42 = (unsigned char )__cil_tmp41;
#line 315
      __cil_tmp43 = (unsigned int )__cil_tmp42;
#line 315
      if (__cil_tmp43 == 6U) {
#line 316
        aux_clock_divider = 62U;
      } else {
        {
#line 315
        __cil_tmp44 = dev->dev_private;
#line 315
        __cil_tmp45 = (struct drm_i915_private *)__cil_tmp44;
#line 315
        __cil_tmp46 = __cil_tmp45->info;
#line 315
        __cil_tmp47 = (unsigned char *)__cil_tmp46;
#line 315
        __cil_tmp48 = __cil_tmp47 + 2UL;
#line 315
        __cil_tmp49 = *__cil_tmp48;
#line 315
        __cil_tmp50 = (unsigned int )__cil_tmp49;
#line 315
        if (__cil_tmp50 != 0U) {
#line 316
          aux_clock_divider = 62U;
        } else {
          {
#line 318
          tmp = intel_hrawclk(dev);
#line 318
          __cil_tmp51 = tmp / 2;
#line 318
          aux_clock_divider = (uint32_t )__cil_tmp51;
          }
        }
        }
      }
      }
    }
    }
  }
  {
#line 320
  __cil_tmp52 = dev->dev_private;
#line 320
  __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
#line 320
  __cil_tmp54 = __cil_tmp53->info;
#line 320
  __cil_tmp55 = __cil_tmp54->gen;
#line 320
  __cil_tmp56 = (unsigned char )__cil_tmp55;
#line 320
  __cil_tmp57 = (unsigned int )__cil_tmp56;
#line 320
  if (__cil_tmp57 == 6U) {
#line 321
    precharge = 3;
  } else {
#line 323
    precharge = 5;
  }
  }
  {
#line 325
  tmp___4 = i915_read32___10(dev_priv, ch_ctl);
  }
  {
#line 325
  __cil_tmp58 = (int )tmp___4;
#line 325
  if (__cil_tmp58 < 0) {
    {
#line 326
    tmp___3 = i915_read32___10(dev_priv, ch_ctl);
#line 326
    drm_err("intel_dp_aux_ch", "dp_aux_ch not started status 0x%08x\n", tmp___3);
    }
#line 328
    return (-16);
  } else {

  }
  }
#line 332
  try = 0;
#line 332
  goto ldv_37705;
  ldv_37704: 
#line 334
  i = 0;
#line 334
  goto ldv_37699;
  ldv_37698: 
  {
#line 335
  __cil_tmp59 = (unsigned long )i;
#line 335
  __cil_tmp60 = send + __cil_tmp59;
#line 335
  __cil_tmp61 = send_bytes - i;
#line 335
  tmp___5 = pack_aux(__cil_tmp60, __cil_tmp61);
#line 335
  __cil_tmp62 = (uint32_t )i;
#line 335
  __cil_tmp63 = ch_data + __cil_tmp62;
#line 335
  i915_write32___8(dev_priv, __cil_tmp63, tmp___5);
#line 334
  i = i + 4;
  }
  ldv_37699: ;
#line 334
  if (i < send_bytes) {
#line 335
    goto ldv_37698;
  } else {
#line 337
    goto ldv_37700;
  }
  ldv_37700: 
  {
#line 339
  __cil_tmp64 = precharge << 16;
#line 339
  __cil_tmp65 = send_bytes << 20;
#line 339
  __cil_tmp66 = __cil_tmp65 | (-0x7FFFFFFF-1);
#line 339
  __cil_tmp67 = __cil_tmp66 | __cil_tmp64;
#line 339
  __cil_tmp68 = (uint32_t )__cil_tmp67;
#line 339
  __cil_tmp69 = __cil_tmp68 | aux_clock_divider;
#line 339
  __cil_tmp70 = __cil_tmp69 | 1375731712U;
#line 339
  i915_write32___8(dev_priv, ch_ctl, __cil_tmp70);
  }
  ldv_37702: 
  {
#line 349
  status = i915_read32___10(dev_priv, ch_ctl);
  }
  {
#line 350
  __cil_tmp71 = (int )status;
#line 350
  if (__cil_tmp71 >= 0) {
#line 351
    goto ldv_37701;
  } else {

  }
  }
  {
#line 352
  __const_udelay(429500UL);
  }
#line 353
  goto ldv_37702;
  ldv_37701: 
  {
#line 356
  __cil_tmp72 = status | 1375731712U;
#line 356
  i915_write32___8(dev_priv, ch_ctl, __cil_tmp72);
  }
  {
#line 361
  __cil_tmp73 = status & 1073741824U;
#line 361
  if (__cil_tmp73 != 0U) {
#line 362
    goto ldv_37703;
  } else {

  }
  }
#line 332
  try = try + 1;
  ldv_37705: ;
#line 332
  if (try <= 4) {
#line 333
    goto ldv_37704;
  } else {
#line 335
    goto ldv_37703;
  }
  ldv_37703: ;
  {
#line 365
  __cil_tmp74 = status & 1073741824U;
#line 365
  if (__cil_tmp74 == 0U) {
    {
#line 366
    drm_err("intel_dp_aux_ch", "dp_aux_ch not done status 0x%08x\n", status);
    }
#line 367
    return (-16);
  } else {

  }
  }
  {
#line 373
  __cil_tmp75 = status & 33554432U;
#line 373
  if (__cil_tmp75 != 0U) {
    {
#line 374
    drm_err("intel_dp_aux_ch", "dp_aux_ch receive error status 0x%08x\n", status);
    }
#line 375
    return (-5);
  } else {

  }
  }
  {
#line 380
  __cil_tmp76 = status & 268435456U;
#line 380
  if (__cil_tmp76 != 0U) {
    {
#line 381
    drm_ut_debug_printk(4U, "drm", "intel_dp_aux_ch", "dp_aux_ch timeout status 0x%08x\n",
                        status);
    }
#line 382
    return (-110);
  } else {

  }
  }
#line 386
  __cil_tmp77 = status & 32505856U;
#line 386
  __cil_tmp78 = __cil_tmp77 >> 20;
#line 386
  recv_bytes = (int )__cil_tmp78;
#line 388
  if (recv_bytes > recv_size) {
#line 389
    recv_bytes = recv_size;
  } else {

  }
#line 391
  i = 0;
#line 391
  goto ldv_37707;
  ldv_37706: 
  {
#line 392
  __cil_tmp79 = (uint32_t )i;
#line 392
  __cil_tmp80 = ch_data + __cil_tmp79;
#line 392
  tmp___6 = i915_read32___10(dev_priv, __cil_tmp80);
#line 392
  __cil_tmp81 = (unsigned long )i;
#line 392
  __cil_tmp82 = recv + __cil_tmp81;
#line 392
  __cil_tmp83 = recv_bytes - i;
#line 392
  unpack_aux(tmp___6, __cil_tmp82, __cil_tmp83);
#line 391
  i = i + 4;
  }
  ldv_37707: ;
#line 391
  if (i < recv_bytes) {
#line 392
    goto ldv_37706;
  } else {
#line 394
    goto ldv_37708;
  }
  ldv_37708: ;
#line 395
  return (recv_bytes);
}
}
#line 400 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_aux_native_write(struct intel_dp *intel_dp , uint16_t address ,
                                     uint8_t *send , int send_bytes ) 
{ int ret ;
  uint8_t msg[20U] ;
  int msg_bytes ;
  uint8_t ack ;
  size_t __len ;
  void *__ret ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  uint8_t __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  void *__cil_tmp16 ;
  void *__cil_tmp17 ;
  void const   *__cil_tmp18 ;
  uint8_t *__cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;

  {
#line 408
  if (send_bytes > 16) {
#line 409
    return (-1);
  } else {

  }
  {
#line 410
  msg[0] = (uint8_t )128U;
#line 411
  __cil_tmp11 = (int )address;
#line 411
  __cil_tmp12 = __cil_tmp11 >> 8;
#line 411
  msg[1] = (uint8_t )__cil_tmp12;
#line 412
  msg[2] = (uint8_t )address;
#line 413
  __cil_tmp13 = (uint8_t )send_bytes;
#line 413
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 413
  __cil_tmp15 = __cil_tmp14 + 255U;
#line 413
  msg[3] = (uint8_t )__cil_tmp15;
#line 414
  __len = (size_t )send_bytes;
#line 414
  __cil_tmp16 = (void *)(& msg);
#line 414
  __cil_tmp17 = __cil_tmp16 + 4U;
#line 414
  __cil_tmp18 = (void const   *)send;
#line 414
  __ret = __builtin_memcpy(__cil_tmp17, __cil_tmp18, __len);
#line 415
  msg_bytes = send_bytes + 4;
  }
  ldv_37723: 
  {
#line 417
  __cil_tmp19 = (uint8_t *)(& msg);
#line 417
  ret = intel_dp_aux_ch(intel_dp, __cil_tmp19, msg_bytes, & ack, 1);
  }
#line 418
  if (ret < 0) {
#line 419
    return (ret);
  } else {

  }
  {
#line 420
  __cil_tmp20 = (int )ack;
#line 420
  __cil_tmp21 = __cil_tmp20 & 48;
#line 420
  if (__cil_tmp21 == 0) {
#line 421
    goto ldv_37722;
  } else {
    {
#line 422
    __cil_tmp22 = (int )ack;
#line 422
    __cil_tmp23 = __cil_tmp22 & 48;
#line 422
    if (__cil_tmp23 == 32) {
      {
#line 423
      __const_udelay(429500UL);
      }
    } else {
#line 425
      return (-5);
    }
    }
  }
  }
#line 426
  goto ldv_37723;
  ldv_37722: ;
#line 427
  return (send_bytes);
}
}
#line 432 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_aux_native_write_1(struct intel_dp *intel_dp , uint16_t address ,
                                       uint8_t byte ) 
{ int tmp ;
  int __cil_tmp5 ;
  uint16_t __cil_tmp6 ;

  {
  {
#line 435
  __cil_tmp5 = (int )address;
#line 435
  __cil_tmp6 = (uint16_t )__cil_tmp5;
#line 435
  tmp = intel_dp_aux_native_write(intel_dp, __cil_tmp6, & byte, 1);
  }
#line 435
  return (tmp);
}
}
#line 440 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_aux_native_read(struct intel_dp *intel_dp , uint16_t address ,
                                    uint8_t *recv , int recv_bytes ) 
{ uint8_t msg[4U] ;
  int msg_bytes ;
  uint8_t reply[20U] ;
  int reply_bytes ;
  uint8_t ack ;
  int ret ;
  size_t __len ;
  void *__ret ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  uint8_t __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  uint8_t *__cil_tmp18 ;
  uint8_t *__cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  void *__cil_tmp23 ;
  void const   *__cil_tmp24 ;
  void const   *__cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;

  {
#line 450
  msg[0] = (uint8_t )144U;
#line 451
  __cil_tmp13 = (int )address;
#line 451
  __cil_tmp14 = __cil_tmp13 >> 8;
#line 451
  msg[1] = (uint8_t )__cil_tmp14;
#line 452
  msg[2] = (uint8_t )address;
#line 453
  __cil_tmp15 = (uint8_t )recv_bytes;
#line 453
  __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 453
  __cil_tmp17 = __cil_tmp16 + 255U;
#line 453
  msg[3] = (uint8_t )__cil_tmp17;
#line 455
  msg_bytes = 4;
#line 456
  reply_bytes = recv_bytes + 1;
  ldv_37744: 
  {
#line 459
  __cil_tmp18 = (uint8_t *)(& msg);
#line 459
  __cil_tmp19 = (uint8_t *)(& reply);
#line 459
  ret = intel_dp_aux_ch(intel_dp, __cil_tmp18, msg_bytes, __cil_tmp19, reply_bytes);
  }
#line 461
  if (ret == 0) {
#line 462
    return (-71);
  } else {

  }
#line 463
  if (ret < 0) {
#line 464
    return (ret);
  } else {

  }
#line 465
  ack = reply[0];
  {
#line 466
  __cil_tmp20 = (int )ack;
#line 466
  __cil_tmp21 = __cil_tmp20 & 48;
#line 466
  if (__cil_tmp21 == 0) {
    {
#line 467
    __cil_tmp22 = ret + -1;
#line 467
    __len = (size_t )__cil_tmp22;
#line 467
    __cil_tmp23 = (void *)recv;
#line 467
    __cil_tmp24 = (void const   *)(& reply);
#line 467
    __cil_tmp25 = __cil_tmp24 + 1U;
#line 467
    __ret = __builtin_memcpy(__cil_tmp23, __cil_tmp25, __len);
    }
#line 468
    return (ret + -1);
  } else {
    {
#line 470
    __cil_tmp26 = (int )ack;
#line 470
    __cil_tmp27 = __cil_tmp26 & 48;
#line 470
    if (__cil_tmp27 == 32) {
      {
#line 471
      __const_udelay(429500UL);
      }
    } else {
#line 473
      return (-5);
    }
    }
  }
  }
#line 474
  goto ldv_37744;
}
}
#line 478 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_i2c_aux_ch(struct i2c_adapter *adapter , int mode , uint8_t write_byte ,
                               uint8_t *read_byte ) 
{ struct i2c_algo_dp_aux_data *algo_data ;
  struct intel_dp *intel_dp ;
  struct i2c_adapter  const  *__mptr ;
  uint16_t address ;
  uint8_t msg[5U] ;
  uint8_t reply[2U] ;
  unsigned int retry ;
  int msg_bytes ;
  int reply_bytes ;
  int ret ;
  void *__cil_tmp15 ;
  struct intel_dp *__cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  uint8_t *__cil_tmp23 ;
  uint8_t *__cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  int __cil_tmp38 ;

  {
#line 481
  __cil_tmp15 = adapter->algo_data;
#line 481
  algo_data = (struct i2c_algo_dp_aux_data *)__cil_tmp15;
#line 482
  __mptr = (struct i2c_adapter  const  *)adapter;
#line 482
  __cil_tmp16 = (struct intel_dp *)__mptr;
#line 482
  intel_dp = __cil_tmp16 + 1152921504606846840UL;
#line 485
  address = algo_data->address;
  {
#line 494
  __cil_tmp17 = mode & 4;
#line 494
  if (__cil_tmp17 != 0) {
#line 495
    msg[0] = (uint8_t )16U;
  } else {
#line 497
    msg[0] = (uint8_t )0U;
  }
  }
  {
#line 499
  __cil_tmp18 = mode & 8;
#line 499
  if (__cil_tmp18 == 0) {
#line 500
    __cil_tmp19 = (unsigned int )msg[0];
#line 500
    __cil_tmp20 = __cil_tmp19 | 64U;
#line 500
    msg[0] = (uint8_t )__cil_tmp20;
  } else {

  }
  }
#line 502
  __cil_tmp21 = (int )address;
#line 502
  __cil_tmp22 = __cil_tmp21 >> 8;
#line 502
  msg[1] = (uint8_t )__cil_tmp22;
#line 503
  msg[2] = (uint8_t )address;
#line 506
  if (mode == 2) {
#line 506
    goto case_2;
  } else
#line 512
  if (mode == 4) {
#line 512
    goto case_4;
  } else {
#line 517
    goto switch_default;
#line 505
    if (0) {
      case_2: 
#line 507
      msg[3] = (uint8_t )0U;
#line 508
      msg[4] = write_byte;
#line 509
      msg_bytes = 5;
#line 510
      reply_bytes = 1;
#line 511
      goto ldv_37763;
      case_4: 
#line 513
      msg[3] = (uint8_t )0U;
#line 514
      msg_bytes = 4;
#line 515
      reply_bytes = 2;
#line 516
      goto ldv_37763;
      switch_default: 
#line 518
      msg_bytes = 3;
#line 519
      reply_bytes = 1;
#line 520
      goto ldv_37763;
    } else {

    }
  }
  ldv_37763: 
#line 523
  retry = 0U;
#line 523
  goto ldv_37779;
  ldv_37778: 
  {
#line 524
  __cil_tmp23 = (uint8_t *)(& msg);
#line 524
  __cil_tmp24 = (uint8_t *)(& reply);
#line 524
  ret = intel_dp_aux_ch(intel_dp, __cil_tmp23, msg_bytes, __cil_tmp24, reply_bytes);
  }
#line 527
  if (ret < 0) {
    {
#line 528
    drm_ut_debug_printk(4U, "drm", "intel_dp_i2c_aux_ch", "aux_ch failed %d\n", ret);
    }
#line 529
    return (ret);
  } else {

  }
  {
#line 533
  __cil_tmp25 = (int )reply[0];
#line 533
  __cil_tmp26 = __cil_tmp25 & 48;
#line 533
  if (__cil_tmp26 == 0) {
#line 533
    goto case_0;
  } else {
    {
#line 538
    __cil_tmp27 = (int )reply[0];
#line 538
    __cil_tmp28 = __cil_tmp27 & 48;
#line 538
    if (__cil_tmp28 == 16) {
#line 538
      goto case_16;
    } else {
      {
#line 541
      __cil_tmp29 = (int )reply[0];
#line 541
      __cil_tmp30 = __cil_tmp29 & 48;
#line 541
      if (__cil_tmp30 == 32) {
#line 541
        goto case_32;
      } else {
#line 544
        goto switch_default___0;
#line 532
        if (0) {
          case_0: ;
#line 537
          goto ldv_37768;
          case_16: 
          {
#line 539
          drm_ut_debug_printk(4U, "drm", "intel_dp_i2c_aux_ch", "aux_ch native nack\n");
          }
#line 540
          return (-121);
          case_32: 
          {
#line 542
          __const_udelay(429500UL);
          }
#line 543
          goto ldv_37771;
          switch_default___0: 
          {
#line 545
          __cil_tmp31 = (int )reply[0];
#line 545
          drm_err("intel_dp_i2c_aux_ch", "aux_ch invalid native reply 0x%02x\n", __cil_tmp31);
          }
#line 547
          return (-121);
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_37768: ;
  {
#line 551
  __cil_tmp32 = (int )reply[0];
#line 551
  __cil_tmp33 = __cil_tmp32 & 192;
#line 551
  if (__cil_tmp33 == 0) {
#line 551
    goto case_0___0;
  } else {
    {
#line 556
    __cil_tmp34 = (int )reply[0];
#line 556
    __cil_tmp35 = __cil_tmp34 & 192;
#line 556
    if (__cil_tmp35 == 64) {
#line 556
      goto case_64;
    } else {
      {
#line 559
      __cil_tmp36 = (int )reply[0];
#line 559
      __cil_tmp37 = __cil_tmp36 & 192;
#line 559
      if (__cil_tmp37 == 128) {
#line 559
        goto case_128;
      } else {
#line 563
        goto switch_default___1;
#line 550
        if (0) {
          case_0___0: ;
#line 552
          if (mode == 4) {
#line 553
            *read_byte = reply[1];
          } else {

          }
#line 555
          return (reply_bytes + -1);
          case_64: 
          {
#line 557
          drm_ut_debug_printk(4U, "drm", "intel_dp_i2c_aux_ch", "aux_i2c nack\n");
          }
#line 558
          return (-121);
          case_128: 
          {
#line 560
          drm_ut_debug_printk(4U, "drm", "intel_dp_i2c_aux_ch", "aux_i2c defer\n");
#line 561
          __const_udelay(429500UL);
          }
#line 562
          goto ldv_37776;
          switch_default___1: 
          {
#line 564
          __cil_tmp38 = (int )reply[0];
#line 564
          drm_err("intel_dp_i2c_aux_ch", "aux_i2c invalid reply 0x%02x\n", __cil_tmp38);
          }
#line 565
          return (-121);
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_37776: ;
  ldv_37771: 
#line 523
  retry = retry + 1U;
  ldv_37779: ;
#line 523
  if (retry <= 4U) {
#line 524
    goto ldv_37778;
  } else {
#line 526
    goto ldv_37780;
  }
  ldv_37780: 
  {
#line 569
  drm_err("intel_dp_i2c_aux_ch", "too many retries, giving up\n");
  }
#line 570
  return (-121);
}
}
#line 574 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_i2c_init(struct intel_dp *intel_dp , struct intel_connector *intel_connector ,
                             char const   *name ) 
{ int tmp ;
  struct i2c_adapter *__cil_tmp5 ;
  void *__cil_tmp6 ;
  char (*__cil_tmp7)[48U] ;
  char *__cil_tmp8 ;
  struct i2c_algo_dp_aux_data *__cil_tmp9 ;
  struct i2c_adapter *__cil_tmp10 ;

  {
  {
#line 577
  drm_ut_debug_printk(4U, "drm", "intel_dp_i2c_init", "i2c_init %s\n", name);
#line 578
  intel_dp->algo.running = (bool )0;
#line 579
  intel_dp->algo.address = (u16 )0U;
#line 580
  intel_dp->algo.aux_ch = & intel_dp_i2c_aux_ch;
#line 582
  __cil_tmp5 = & intel_dp->adapter;
#line 582
  __cil_tmp6 = (void *)__cil_tmp5;
#line 582
  memset(__cil_tmp6, 0, 1640UL);
#line 583
  intel_dp->adapter.owner = & __this_module;
#line 584
  intel_dp->adapter.class = 8U;
#line 585
  __cil_tmp7 = & intel_dp->adapter.name;
#line 585
  __cil_tmp8 = (char *)__cil_tmp7;
#line 585
  strncpy(__cil_tmp8, name, 47UL);
#line 586
  intel_dp->adapter.name[47UL] = (char)0;
#line 587
  __cil_tmp9 = & intel_dp->algo;
#line 587
  intel_dp->adapter.algo_data = (void *)__cil_tmp9;
#line 588
  intel_dp->adapter.dev.parent = & intel_connector->base.kdev;
#line 590
  __cil_tmp10 = & intel_dp->adapter;
#line 590
  tmp = i2c_dp_aux_add_bus(__cil_tmp10);
  }
#line 590
  return (tmp);
}
}
#line 594 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_dp_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  int lane_count ;
  int clock ;
  int max_lane_count ;
  int tmp___0 ;
  int max_clock ;
  int tmp___1 ;
  int bws[2U] ;
  bool tmp___2 ;
  int link_avail ;
  int tmp___3 ;
  int tmp___4 ;
  int tmp___5 ;
  bool tmp___6 ;
  void *__cil_tmp21 ;
  struct drm_display_mode *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct drm_display_mode *__cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct drm_display_mode *__cil_tmp26 ;
  struct drm_display_mode *__cil_tmp27 ;
  uint8_t __cil_tmp28 ;
  int __cil_tmp29 ;
  uint8_t __cil_tmp30 ;
  struct drm_device *__cil_tmp31 ;
  int __cil_tmp32 ;
  uint8_t __cil_tmp33 ;
  int __cil_tmp34 ;
  uint8_t __cil_tmp35 ;
  uint8_t __cil_tmp36 ;
  int __cil_tmp37 ;
  uint8_t __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  uint8_t __cil_tmp41 ;
  int __cil_tmp42 ;
  uint8_t __cil_tmp43 ;
  uint8_t __cil_tmp44 ;
  int __cil_tmp45 ;
  uint8_t __cil_tmp46 ;
  int __cil_tmp47 ;
  int __cil_tmp48 ;

  {
  {
#line 597
  dev = encoder->dev;
#line 598
  __cil_tmp21 = dev->dev_private;
#line 598
  dev_priv = (struct drm_i915_private *)__cil_tmp21;
#line 599
  tmp = enc_to_intel_dp(encoder);
#line 599
  intel_dp = tmp;
#line 601
  tmp___0 = intel_dp_max_lane_count(intel_dp);
#line 601
  max_lane_count = tmp___0;
#line 602
  tmp___1 = intel_dp_max_link_bw(intel_dp);
#line 602
  max_clock = tmp___1 == 10;
#line 603
  bws[0] = 6;
#line 603
  bws[1] = 10;
#line 605
  tmp___2 = is_edp(intel_dp);
  }
#line 605
  if ((int )tmp___2) {
    {
#line 605
    __cil_tmp22 = (struct drm_display_mode *)0;
#line 605
    __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 605
    __cil_tmp24 = dev_priv->panel_fixed_mode;
#line 605
    __cil_tmp25 = (unsigned long )__cil_tmp24;
#line 605
    if (__cil_tmp25 != __cil_tmp23) {
      {
#line 606
      __cil_tmp26 = dev_priv->panel_fixed_mode;
#line 606
      intel_fixed_panel_mode(__cil_tmp26, adjusted_mode);
#line 607
      intel_pch_panel_fitting(dev, 1, mode, adjusted_mode);
#line 613
      __cil_tmp27 = dev_priv->panel_fixed_mode;
#line 613
      mode->clock = __cil_tmp27->clock;
      }
    } else {

    }
    }
  } else {

  }
#line 616
  lane_count = 1;
#line 616
  goto ldv_37806;
  ldv_37805: 
#line 617
  clock = 0;
#line 617
  goto ldv_37803;
  ldv_37802: 
  {
#line 618
  __cil_tmp28 = (uint8_t )bws[clock];
#line 618
  __cil_tmp29 = (int )__cil_tmp28;
#line 618
  __cil_tmp30 = (uint8_t )__cil_tmp29;
#line 618
  tmp___3 = intel_dp_link_clock(__cil_tmp30);
#line 618
  tmp___4 = intel_dp_max_data_rate(tmp___3, lane_count);
#line 618
  link_avail = tmp___4;
#line 620
  __cil_tmp31 = encoder->dev;
#line 620
  __cil_tmp32 = mode->clock;
#line 620
  tmp___5 = intel_dp_link_required(__cil_tmp31, intel_dp, __cil_tmp32);
  }
#line 620
  if (tmp___5 <= link_avail) {
    {
#line 622
    intel_dp->link_bw = (uint8_t )bws[clock];
#line 623
    intel_dp->lane_count = (uint8_t )lane_count;
#line 624
    __cil_tmp33 = intel_dp->link_bw;
#line 624
    __cil_tmp34 = (int )__cil_tmp33;
#line 624
    __cil_tmp35 = (uint8_t )__cil_tmp34;
#line 624
    adjusted_mode->clock = intel_dp_link_clock(__cil_tmp35);
#line 625
    __cil_tmp36 = intel_dp->link_bw;
#line 625
    __cil_tmp37 = (int )__cil_tmp36;
#line 625
    __cil_tmp38 = intel_dp->lane_count;
#line 625
    __cil_tmp39 = (int )__cil_tmp38;
#line 625
    __cil_tmp40 = adjusted_mode->clock;
#line 625
    drm_ut_debug_printk(4U, "drm", "intel_dp_mode_fixup", "Display port link bw %02x lane count %d clock %d\n",
                        __cil_tmp37, __cil_tmp39, __cil_tmp40);
    }
#line 629
    return ((bool )1);
  } else {

  }
#line 617
  clock = clock + 1;
  ldv_37803: ;
#line 617
  if (clock <= max_clock) {
#line 618
    goto ldv_37802;
  } else {
#line 620
    goto ldv_37804;
  }
  ldv_37804: 
#line 616
  lane_count = lane_count << 1;
  ldv_37806: ;
#line 616
  if (lane_count <= max_lane_count) {
#line 617
    goto ldv_37805;
  } else {
#line 619
    goto ldv_37807;
  }
  ldv_37807: 
  {
#line 634
  tmp___6 = is_edp(intel_dp);
  }
#line 634
  if ((int )tmp___6) {
    {
#line 636
    intel_dp->lane_count = (uint8_t )max_lane_count;
#line 637
    intel_dp->link_bw = (uint8_t )bws[max_clock];
#line 638
    __cil_tmp41 = intel_dp->link_bw;
#line 638
    __cil_tmp42 = (int )__cil_tmp41;
#line 638
    __cil_tmp43 = (uint8_t )__cil_tmp42;
#line 638
    adjusted_mode->clock = intel_dp_link_clock(__cil_tmp43);
#line 639
    __cil_tmp44 = intel_dp->link_bw;
#line 639
    __cil_tmp45 = (int )__cil_tmp44;
#line 639
    __cil_tmp46 = intel_dp->lane_count;
#line 639
    __cil_tmp47 = (int )__cil_tmp46;
#line 639
    __cil_tmp48 = adjusted_mode->clock;
#line 639
    drm_ut_debug_printk(4U, "drm", "intel_dp_mode_fixup", "Force picking display port link bw %02x lane count %d clock %d\n",
                        __cil_tmp45, __cil_tmp47, __cil_tmp48);
    }
#line 644
    return ((bool )1);
  } else {

  }
#line 647
  return ((bool )0);
}
}
#line 659 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_reduce_ratio(uint32_t *num , uint32_t *den ) 
{ uint32_t __cil_tmp3 ;
  uint32_t __cil_tmp4 ;
  uint32_t __cil_tmp5 ;
  uint32_t __cil_tmp6 ;

  {
#line 661
  goto ldv_37819;
  ldv_37818: 
#line 662
  __cil_tmp3 = *num;
#line 662
  *num = __cil_tmp3 >> 1;
#line 663
  __cil_tmp4 = *den;
#line 663
  *den = __cil_tmp4 >> 1;
  ldv_37819: ;
  {
#line 661
  __cil_tmp5 = *num;
#line 661
  if (__cil_tmp5 > 16777215U) {
#line 662
    goto ldv_37818;
  } else {
    {
#line 661
    __cil_tmp6 = *den;
#line 661
    if (__cil_tmp6 > 16777215U) {
#line 662
      goto ldv_37818;
    } else {
#line 664
      goto ldv_37820;
    }
    }
  }
  }
  ldv_37820: ;
#line 666
  return;
}
}
#line 668 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_compute_m_n(int bpp , int nlanes , int pixel_clock , int link_clock ,
                                 struct intel_dp_m_n *m_n ) 
{ int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  uint32_t *__cil_tmp9 ;
  uint32_t *__cil_tmp10 ;
  uint32_t *__cil_tmp11 ;
  uint32_t *__cil_tmp12 ;

  {
  {
#line 674
  m_n->tu = 64U;
#line 675
  __cil_tmp6 = pixel_clock * bpp;
#line 675
  __cil_tmp7 = __cil_tmp6 >> 3;
#line 675
  m_n->gmch_m = (uint32_t )__cil_tmp7;
#line 676
  __cil_tmp8 = link_clock * nlanes;
#line 676
  m_n->gmch_n = (uint32_t )__cil_tmp8;
#line 677
  __cil_tmp9 = & m_n->gmch_m;
#line 677
  __cil_tmp10 = & m_n->gmch_n;
#line 677
  intel_reduce_ratio(__cil_tmp9, __cil_tmp10);
#line 678
  m_n->link_m = (uint32_t )pixel_clock;
#line 679
  m_n->link_n = (uint32_t )link_clock;
#line 680
  __cil_tmp11 = & m_n->link_m;
#line 680
  __cil_tmp12 = & m_n->link_n;
#line 680
  intel_reduce_ratio(__cil_tmp11, __cil_tmp12);
  }
#line 681
  return;
}
}
#line 684 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
void intel_dp_set_m_n(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_mode_config *mode_config ;
  struct drm_encoder *encoder ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int lane_count ;
  int bpp ;
  struct intel_dp_m_n m_n ;
  int pipe ;
  struct list_head  const  *__mptr___0 ;
  struct intel_dp *intel_dp ;
  bool tmp ;
  struct list_head  const  *__mptr___1 ;
  void *__cil_tmp18 ;
  enum pipe __cil_tmp19 ;
  struct list_head *__cil_tmp20 ;
  struct drm_encoder *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct drm_crtc *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  int __cil_tmp25 ;
  uint8_t __cil_tmp26 ;
  struct list_head *__cil_tmp27 ;
  struct drm_encoder *__cil_tmp28 ;
  struct list_head *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  struct list_head *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  void *__cil_tmp35 ;
  struct drm_i915_private *__cil_tmp36 ;
  struct intel_device_info  const  *__cil_tmp37 ;
  u8 __cil_tmp38 ;
  unsigned char __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  int __cil_tmp41 ;
  int __cil_tmp42 ;
  u32 __cil_tmp43 ;
  uint32_t __cil_tmp44 ;
  uint32_t __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  int __cil_tmp47 ;
  int __cil_tmp48 ;
  u32 __cil_tmp49 ;
  int __cil_tmp50 ;
  int __cil_tmp51 ;
  u32 __cil_tmp52 ;
  int __cil_tmp53 ;
  int __cil_tmp54 ;
  u32 __cil_tmp55 ;
  void *__cil_tmp56 ;
  struct drm_i915_private *__cil_tmp57 ;
  struct intel_device_info  const  *__cil_tmp58 ;
  u8 __cil_tmp59 ;
  unsigned char __cil_tmp60 ;
  unsigned int __cil_tmp61 ;
  int __cil_tmp62 ;
  int __cil_tmp63 ;
  u32 __cil_tmp64 ;
  uint32_t __cil_tmp65 ;
  uint32_t __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  u32 __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  u32 __cil_tmp73 ;
  int __cil_tmp74 ;
  int __cil_tmp75 ;
  u32 __cil_tmp76 ;
  void *__cil_tmp77 ;
  struct drm_i915_private *__cil_tmp78 ;
  struct intel_device_info  const  *__cil_tmp79 ;
  unsigned char *__cil_tmp80 ;
  unsigned char *__cil_tmp81 ;
  unsigned char __cil_tmp82 ;
  unsigned int __cil_tmp83 ;
  int __cil_tmp84 ;
  int __cil_tmp85 ;
  u32 __cil_tmp86 ;
  uint32_t __cil_tmp87 ;
  uint32_t __cil_tmp88 ;
  unsigned int __cil_tmp89 ;
  int __cil_tmp90 ;
  int __cil_tmp91 ;
  u32 __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  u32 __cil_tmp95 ;
  int __cil_tmp96 ;
  int __cil_tmp97 ;
  u32 __cil_tmp98 ;
  int __cil_tmp99 ;
  int __cil_tmp100 ;
  u32 __cil_tmp101 ;
  uint32_t __cil_tmp102 ;
  uint32_t __cil_tmp103 ;
  unsigned int __cil_tmp104 ;
  int __cil_tmp105 ;
  int __cil_tmp106 ;
  u32 __cil_tmp107 ;
  int __cil_tmp108 ;
  int __cil_tmp109 ;
  u32 __cil_tmp110 ;
  int __cil_tmp111 ;
  int __cil_tmp112 ;
  u32 __cil_tmp113 ;

  {
#line 687
  dev = crtc->dev;
#line 688
  mode_config = & dev->mode_config;
#line 690
  __cil_tmp18 = dev->dev_private;
#line 690
  dev_priv = (struct drm_i915_private *)__cil_tmp18;
#line 691
  __mptr = (struct drm_crtc  const  *)crtc;
#line 691
  intel_crtc = (struct intel_crtc *)__mptr;
#line 692
  lane_count = 4;
#line 692
  bpp = 24;
#line 694
  __cil_tmp19 = intel_crtc->pipe;
#line 694
  pipe = (int )__cil_tmp19;
#line 699
  __cil_tmp20 = mode_config->encoder_list.next;
#line 699
  __mptr___0 = (struct list_head  const  *)__cil_tmp20;
#line 699
  __cil_tmp21 = (struct drm_encoder *)__mptr___0;
#line 699
  encoder = __cil_tmp21 + 1152921504606846968UL;
#line 699
  goto ldv_37852;
  ldv_37851: ;
  {
#line 702
  __cil_tmp22 = (unsigned long )crtc;
#line 702
  __cil_tmp23 = encoder->crtc;
#line 702
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 702
  if (__cil_tmp24 != __cil_tmp22) {
#line 703
    goto ldv_37849;
  } else {

  }
  }
  {
#line 705
  intel_dp = enc_to_intel_dp(encoder);
  }
  {
#line 706
  __cil_tmp25 = intel_dp->base.type;
#line 706
  if (__cil_tmp25 == 7) {
#line 707
    __cil_tmp26 = intel_dp->lane_count;
#line 707
    lane_count = (int )__cil_tmp26;
#line 708
    goto ldv_37850;
  } else {
    {
#line 709
    tmp = is_edp(intel_dp);
    }
#line 709
    if ((int )tmp) {
#line 710
      lane_count = dev_priv->edp.lanes;
#line 711
      bpp = dev_priv->edp.bpp;
#line 712
      goto ldv_37850;
    } else {

    }
  }
  }
  ldv_37849: 
#line 699
  __cil_tmp27 = encoder->head.next;
#line 699
  __mptr___1 = (struct list_head  const  *)__cil_tmp27;
#line 699
  __cil_tmp28 = (struct drm_encoder *)__mptr___1;
#line 699
  encoder = __cil_tmp28 + 1152921504606846968UL;
  ldv_37852: ;
  {
#line 699
  __cil_tmp29 = & mode_config->encoder_list;
#line 699
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 699
  __cil_tmp31 = & encoder->head;
#line 699
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 699
  if (__cil_tmp32 != __cil_tmp30) {
#line 700
    goto ldv_37851;
  } else {
#line 702
    goto ldv_37850;
  }
  }
  ldv_37850: 
  {
#line 721
  __cil_tmp33 = mode->clock;
#line 721
  __cil_tmp34 = adjusted_mode->clock;
#line 721
  intel_dp_compute_m_n(bpp, lane_count, __cil_tmp33, __cil_tmp34, & m_n);
  }
  {
#line 724
  __cil_tmp35 = dev->dev_private;
#line 724
  __cil_tmp36 = (struct drm_i915_private *)__cil_tmp35;
#line 724
  __cil_tmp37 = __cil_tmp36->info;
#line 724
  __cil_tmp38 = __cil_tmp37->gen;
#line 724
  __cil_tmp39 = (unsigned char )__cil_tmp38;
#line 724
  __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 724
  if (__cil_tmp40 == 5U) {
    {
#line 725
    __cil_tmp41 = pipe * 4096;
#line 725
    __cil_tmp42 = __cil_tmp41 + 917552;
#line 725
    __cil_tmp43 = (u32 )__cil_tmp42;
#line 725
    __cil_tmp44 = m_n.tu - 1U;
#line 725
    __cil_tmp45 = __cil_tmp44 << 25;
#line 725
    __cil_tmp46 = __cil_tmp45 | m_n.gmch_m;
#line 725
    i915_write32___8(dev_priv, __cil_tmp43, __cil_tmp46);
#line 728
    __cil_tmp47 = pipe * 4096;
#line 728
    __cil_tmp48 = __cil_tmp47 + 917556;
#line 728
    __cil_tmp49 = (u32 )__cil_tmp48;
#line 728
    i915_write32___8(dev_priv, __cil_tmp49, m_n.gmch_n);
#line 729
    __cil_tmp50 = pipe * 4096;
#line 729
    __cil_tmp51 = __cil_tmp50 + 917568;
#line 729
    __cil_tmp52 = (u32 )__cil_tmp51;
#line 729
    i915_write32___8(dev_priv, __cil_tmp52, m_n.link_m);
#line 730
    __cil_tmp53 = pipe * 4096;
#line 730
    __cil_tmp54 = __cil_tmp53 + 917572;
#line 730
    __cil_tmp55 = (u32 )__cil_tmp54;
#line 730
    i915_write32___8(dev_priv, __cil_tmp55, m_n.link_n);
    }
  } else {
    {
#line 724
    __cil_tmp56 = dev->dev_private;
#line 724
    __cil_tmp57 = (struct drm_i915_private *)__cil_tmp56;
#line 724
    __cil_tmp58 = __cil_tmp57->info;
#line 724
    __cil_tmp59 = __cil_tmp58->gen;
#line 724
    __cil_tmp60 = (unsigned char )__cil_tmp59;
#line 724
    __cil_tmp61 = (unsigned int )__cil_tmp60;
#line 724
    if (__cil_tmp61 == 6U) {
      {
#line 725
      __cil_tmp62 = pipe * 4096;
#line 725
      __cil_tmp63 = __cil_tmp62 + 917552;
#line 725
      __cil_tmp64 = (u32 )__cil_tmp63;
#line 725
      __cil_tmp65 = m_n.tu - 1U;
#line 725
      __cil_tmp66 = __cil_tmp65 << 25;
#line 725
      __cil_tmp67 = __cil_tmp66 | m_n.gmch_m;
#line 725
      i915_write32___8(dev_priv, __cil_tmp64, __cil_tmp67);
#line 728
      __cil_tmp68 = pipe * 4096;
#line 728
      __cil_tmp69 = __cil_tmp68 + 917556;
#line 728
      __cil_tmp70 = (u32 )__cil_tmp69;
#line 728
      i915_write32___8(dev_priv, __cil_tmp70, m_n.gmch_n);
#line 729
      __cil_tmp71 = pipe * 4096;
#line 729
      __cil_tmp72 = __cil_tmp71 + 917568;
#line 729
      __cil_tmp73 = (u32 )__cil_tmp72;
#line 729
      i915_write32___8(dev_priv, __cil_tmp73, m_n.link_m);
#line 730
      __cil_tmp74 = pipe * 4096;
#line 730
      __cil_tmp75 = __cil_tmp74 + 917572;
#line 730
      __cil_tmp76 = (u32 )__cil_tmp75;
#line 730
      i915_write32___8(dev_priv, __cil_tmp76, m_n.link_n);
      }
    } else {
      {
#line 724
      __cil_tmp77 = dev->dev_private;
#line 724
      __cil_tmp78 = (struct drm_i915_private *)__cil_tmp77;
#line 724
      __cil_tmp79 = __cil_tmp78->info;
#line 724
      __cil_tmp80 = (unsigned char *)__cil_tmp79;
#line 724
      __cil_tmp81 = __cil_tmp80 + 2UL;
#line 724
      __cil_tmp82 = *__cil_tmp81;
#line 724
      __cil_tmp83 = (unsigned int )__cil_tmp82;
#line 724
      if (__cil_tmp83 != 0U) {
        {
#line 725
        __cil_tmp84 = pipe * 4096;
#line 725
        __cil_tmp85 = __cil_tmp84 + 917552;
#line 725
        __cil_tmp86 = (u32 )__cil_tmp85;
#line 725
        __cil_tmp87 = m_n.tu - 1U;
#line 725
        __cil_tmp88 = __cil_tmp87 << 25;
#line 725
        __cil_tmp89 = __cil_tmp88 | m_n.gmch_m;
#line 725
        i915_write32___8(dev_priv, __cil_tmp86, __cil_tmp89);
#line 728
        __cil_tmp90 = pipe * 4096;
#line 728
        __cil_tmp91 = __cil_tmp90 + 917556;
#line 728
        __cil_tmp92 = (u32 )__cil_tmp91;
#line 728
        i915_write32___8(dev_priv, __cil_tmp92, m_n.gmch_n);
#line 729
        __cil_tmp93 = pipe * 4096;
#line 729
        __cil_tmp94 = __cil_tmp93 + 917568;
#line 729
        __cil_tmp95 = (u32 )__cil_tmp94;
#line 729
        i915_write32___8(dev_priv, __cil_tmp95, m_n.link_m);
#line 730
        __cil_tmp96 = pipe * 4096;
#line 730
        __cil_tmp97 = __cil_tmp96 + 917572;
#line 730
        __cil_tmp98 = (u32 )__cil_tmp97;
#line 730
        i915_write32___8(dev_priv, __cil_tmp98, m_n.link_n);
        }
      } else {
        {
#line 732
        __cil_tmp99 = pipe * 4096;
#line 732
        __cil_tmp100 = __cil_tmp99 + 458832;
#line 732
        __cil_tmp101 = (u32 )__cil_tmp100;
#line 732
        __cil_tmp102 = m_n.tu - 1U;
#line 732
        __cil_tmp103 = __cil_tmp102 << 25;
#line 732
        __cil_tmp104 = __cil_tmp103 | m_n.gmch_m;
#line 732
        i915_write32___8(dev_priv, __cil_tmp101, __cil_tmp104);
#line 735
        __cil_tmp105 = pipe * 4096;
#line 735
        __cil_tmp106 = __cil_tmp105 + 458836;
#line 735
        __cil_tmp107 = (u32 )__cil_tmp106;
#line 735
        i915_write32___8(dev_priv, __cil_tmp107, m_n.gmch_n);
#line 736
        __cil_tmp108 = pipe * 4096;
#line 736
        __cil_tmp109 = __cil_tmp108 + 458848;
#line 736
        __cil_tmp110 = (u32 )__cil_tmp109;
#line 736
        i915_write32___8(dev_priv, __cil_tmp110, m_n.link_m);
#line 737
        __cil_tmp111 = pipe * 4096;
#line 737
        __cil_tmp112 = __cil_tmp111 + 458852;
#line 737
        __cil_tmp113 = (u32 )__cil_tmp112;
#line 737
        i915_write32___8(dev_priv, __cil_tmp113, m_n.link_n);
        }
      }
      }
    }
    }
  }
  }
#line 739
  return;
}
}
#line 742 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                              struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  uint32_t __cil_tmp15 ;
  uint32_t __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  int __cil_tmp18 ;
  uint32_t __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  uint32_t __cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  enum intel_pch __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  uint32_t __cil_tmp27 ;
  uint32_t __cil_tmp28 ;
  uint32_t __cil_tmp29 ;
  uint8_t __cil_tmp30 ;
  int __cil_tmp31 ;
  uint8_t __cil_tmp32 ;
  int __cil_tmp33 ;
  uint8_t __cil_tmp34 ;
  int __cil_tmp35 ;
  uint32_t __cil_tmp36 ;
  uint32_t __cil_tmp37 ;
  bool __cil_tmp38 ;
  uint32_t __cil_tmp39 ;
  uint8_t (*__cil_tmp40)[9U] ;
  void *__cil_tmp41 ;
  uint8_t __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  uint8_t __cil_tmp44 ;
  signed char __cil_tmp45 ;
  int __cil_tmp46 ;
  uint8_t __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  unsigned int __cil_tmp49 ;
  uint32_t __cil_tmp50 ;
  enum pipe __cil_tmp51 ;
  unsigned int __cil_tmp52 ;
  void *__cil_tmp53 ;
  struct drm_i915_private *__cil_tmp54 ;
  enum intel_pch __cil_tmp55 ;
  unsigned int __cil_tmp56 ;
  uint32_t __cil_tmp57 ;
  uint32_t __cil_tmp58 ;
  int __cil_tmp59 ;
  uint32_t __cil_tmp60 ;

  {
  {
#line 745
  dev = encoder->dev;
#line 746
  tmp = enc_to_intel_dp(encoder);
#line 746
  intel_dp = tmp;
#line 747
  crtc = intel_dp->base.base.crtc;
#line 748
  __mptr = (struct drm_crtc  const  *)crtc;
#line 748
  intel_crtc = (struct intel_crtc *)__mptr;
#line 750
  intel_dp->DP = 0U;
#line 751
  __cil_tmp15 = intel_dp->color_range;
#line 751
  __cil_tmp16 = intel_dp->DP;
#line 751
  intel_dp->DP = __cil_tmp16 | __cil_tmp15;
  }
  {
#line 753
  __cil_tmp17 = adjusted_mode->flags;
#line 753
  __cil_tmp18 = (int )__cil_tmp17;
#line 753
  if (__cil_tmp18 & 1) {
#line 754
    __cil_tmp19 = intel_dp->DP;
#line 754
    intel_dp->DP = __cil_tmp19 | 8U;
  } else {

  }
  }
  {
#line 755
  __cil_tmp20 = adjusted_mode->flags;
#line 755
  __cil_tmp21 = __cil_tmp20 & 4U;
#line 755
  if (__cil_tmp21 != 0U) {
#line 756
    __cil_tmp22 = intel_dp->DP;
#line 756
    intel_dp->DP = __cil_tmp22 | 16U;
  } else {

  }
  }
  {
#line 758
  __cil_tmp23 = dev->dev_private;
#line 758
  __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 758
  __cil_tmp25 = __cil_tmp24->pch_type;
#line 758
  __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 758
  if (__cil_tmp26 == 1U) {
    {
#line 758
    tmp___0 = is_edp(intel_dp);
    }
#line 758
    if (tmp___0) {
#line 758
      tmp___1 = 0;
    } else {
#line 758
      tmp___1 = 1;
    }
#line 758
    if (tmp___1) {
#line 759
      __cil_tmp27 = intel_dp->DP;
#line 759
      intel_dp->DP = __cil_tmp27 | 768U;
    } else {
#line 761
      __cil_tmp28 = intel_dp->DP;
#line 761
      intel_dp->DP = __cil_tmp28 | 805306368U;
    }
  } else {
#line 761
    __cil_tmp29 = intel_dp->DP;
#line 761
    intel_dp->DP = __cil_tmp29 | 805306368U;
  }
  }
  {
#line 764
  __cil_tmp30 = intel_dp->lane_count;
#line 764
  __cil_tmp31 = (int )__cil_tmp30;
#line 764
  if (__cil_tmp31 == 1) {
#line 764
    goto case_1;
  } else {
    {
#line 767
    __cil_tmp32 = intel_dp->lane_count;
#line 767
    __cil_tmp33 = (int )__cil_tmp32;
#line 767
    if (__cil_tmp33 == 2) {
#line 767
      goto case_2;
    } else {
      {
#line 770
      __cil_tmp34 = intel_dp->lane_count;
#line 770
      __cil_tmp35 = (int )__cil_tmp34;
#line 770
      if (__cil_tmp35 == 4) {
#line 770
        goto case_4;
      } else
#line 763
      if (0) {
        case_1: 
#line 765
        intel_dp->DP = intel_dp->DP;
#line 766
        goto ldv_37865;
        case_2: 
#line 768
        __cil_tmp36 = intel_dp->DP;
#line 768
        intel_dp->DP = __cil_tmp36 | 524288U;
#line 769
        goto ldv_37865;
        case_4: 
#line 771
        __cil_tmp37 = intel_dp->DP;
#line 771
        intel_dp->DP = __cil_tmp37 | 1572864U;
#line 772
        goto ldv_37865;
      } else {

      }
      }
    }
    }
  }
  }
  ldv_37865: ;
  {
#line 774
  __cil_tmp38 = intel_dp->has_audio;
#line 774
  if ((int )__cil_tmp38) {
#line 775
    __cil_tmp39 = intel_dp->DP;
#line 775
    intel_dp->DP = __cil_tmp39 | 64U;
  } else {

  }
  }
  {
#line 777
  __cil_tmp40 = & intel_dp->link_configuration;
#line 777
  __cil_tmp41 = (void *)__cil_tmp40;
#line 777
  memset(__cil_tmp41, 0, 9UL);
#line 778
  intel_dp->link_configuration[0] = intel_dp->link_bw;
#line 779
  intel_dp->link_configuration[1] = intel_dp->lane_count;
  }
  {
#line 784
  __cil_tmp42 = intel_dp->dpcd[0];
#line 784
  __cil_tmp43 = (unsigned int )__cil_tmp42;
#line 784
  if (__cil_tmp43 > 16U) {
    {
#line 784
    __cil_tmp44 = intel_dp->dpcd[2];
#line 784
    __cil_tmp45 = (signed char )__cil_tmp44;
#line 784
    __cil_tmp46 = (int )__cil_tmp45;
#line 784
    if (__cil_tmp46 < 0) {
#line 786
      __cil_tmp47 = intel_dp->link_configuration[1];
#line 786
      __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 786
      __cil_tmp49 = __cil_tmp48 | 128U;
#line 786
      intel_dp->link_configuration[1] = (uint8_t )__cil_tmp49;
#line 787
      __cil_tmp50 = intel_dp->DP;
#line 787
      intel_dp->DP = __cil_tmp50 | 262144U;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 791
  __cil_tmp51 = intel_crtc->pipe;
#line 791
  __cil_tmp52 = (unsigned int )__cil_tmp51;
#line 791
  if (__cil_tmp52 == 1U) {
    {
#line 791
    __cil_tmp53 = dev->dev_private;
#line 791
    __cil_tmp54 = (struct drm_i915_private *)__cil_tmp53;
#line 791
    __cil_tmp55 = __cil_tmp54->pch_type;
#line 791
    __cil_tmp56 = (unsigned int )__cil_tmp55;
#line 791
    if (__cil_tmp56 != 1U) {
#line 792
      __cil_tmp57 = intel_dp->DP;
#line 792
      intel_dp->DP = __cil_tmp57 | 1073741824U;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 794
  tmp___2 = is_edp(intel_dp);
  }
#line 794
  if ((int )tmp___2) {
    {
#line 794
    tmp___3 = is_pch_edp(intel_dp);
    }
#line 794
    if (tmp___3) {
#line 794
      tmp___4 = 0;
    } else {
#line 794
      tmp___4 = 1;
    }
#line 794
    if (tmp___4) {
#line 796
      __cil_tmp58 = intel_dp->DP;
#line 796
      intel_dp->DP = __cil_tmp58 | 16384U;
      {
#line 797
      __cil_tmp59 = adjusted_mode->clock;
#line 797
      if (__cil_tmp59 <= 199999) {
#line 798
        __cil_tmp60 = intel_dp->DP;
#line 798
        intel_dp->DP = __cil_tmp60 | 65536U;
      } else {
#line 800
        intel_dp->DP = intel_dp->DP;
      }
      }
    } else {

    }
  } else {

  }
#line 802
  return;
}
}
#line 804 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 pp ;
  u32 tmp ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  void *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  void const volatile   *__cil_tmp12 ;

  {
  {
#line 806
  dev = intel_dp->base.base.dev;
#line 807
  __cil_tmp6 = dev->dev_private;
#line 807
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 814
  tmp = i915_read32___10(dev_priv, 815616U);
  }
  {
#line 814
  __cil_tmp7 = (int )tmp;
#line 814
  if (__cil_tmp7 >= 0) {
    {
#line 815
    __cil_tmp8 = dev_priv->panel_t3;
#line 815
    __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 815
    msleep(__cil_tmp9);
    }
  } else {

  }
  }
  {
#line 817
  pp = i915_read32___10(dev_priv, 815620U);
#line 818
  pp = pp | 8U;
#line 819
  i915_write32___8(dev_priv, 815620U, pp);
#line 820
  __cil_tmp10 = dev_priv->regs;
#line 820
  __cil_tmp11 = (void const volatile   *)__cil_tmp10;
#line 820
  __cil_tmp12 = __cil_tmp11 + 815620U;
#line 820
  readl(__cil_tmp12);
  }
#line 821
  return;
}
}
#line 823 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 pp ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;
  void const volatile   *__cil_tmp8 ;
  int __cil_tmp9 ;
  unsigned int __cil_tmp10 ;

  {
  {
#line 825
  dev = intel_dp->base.base.dev;
#line 826
  __cil_tmp5 = dev->dev_private;
#line 826
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 829
  pp = i915_read32___10(dev_priv, 815620U);
#line 830
  pp = pp & 4294967287U;
#line 831
  i915_write32___8(dev_priv, 815620U, pp);
#line 832
  __cil_tmp6 = dev_priv->regs;
#line 832
  __cil_tmp7 = (void const volatile   *)__cil_tmp6;
#line 832
  __cil_tmp8 = __cil_tmp7 + 815620U;
#line 832
  readl(__cil_tmp8);
#line 835
  __cil_tmp9 = dev_priv->panel_t12;
#line 835
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 835
  msleep(__cil_tmp10);
  }
#line 836
  return;
}
}
#line 839 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool ironlake_edp_panel_on(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 pp ;
  u32 idle_on_mask ;
  u32 tmp ;
  u32 tmp___0 ;
  unsigned long timeout__ ;
  unsigned long tmp___1 ;
  int ret__ ;
  struct thread_info *tmp___2 ;
  int pfo_ret__ ;
  int tmp___3 ;
  u32 tmp___4 ;
  void *__cil_tmp15 ;
  int __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  void *__cil_tmp20 ;
  void const volatile   *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  long __cil_tmp26 ;
  long __cil_tmp27 ;
  long __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  atomic_t const   *__cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  void *__cil_tmp33 ;
  void const volatile   *__cil_tmp34 ;
  void const volatile   *__cil_tmp35 ;

  {
  {
#line 841
  dev = intel_dp->base.base.dev;
#line 842
  __cil_tmp15 = dev->dev_private;
#line 842
  dev_priv = (struct drm_i915_private *)__cil_tmp15;
#line 843
  idle_on_mask = 2147483656U;
#line 845
  tmp = i915_read32___10(dev_priv, 815616U);
  }
  {
#line 845
  __cil_tmp16 = (int )tmp;
#line 845
  if (__cil_tmp16 < 0) {
#line 846
    return ((bool )1);
  } else {

  }
  }
  {
#line 848
  pp = i915_read32___10(dev_priv, 815620U);
#line 851
  pp = pp & 4294967293U;
#line 852
  i915_write32___8(dev_priv, 815620U, pp);
#line 853
  __cil_tmp17 = dev_priv->regs;
#line 853
  __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 853
  __cil_tmp19 = __cil_tmp18 + 815620U;
#line 853
  readl(__cil_tmp19);
#line 855
  pp = pp | 2882338817U;
#line 856
  i915_write32___8(dev_priv, 815620U, pp);
#line 857
  __cil_tmp20 = dev_priv->regs;
#line 857
  __cil_tmp21 = (void const volatile   *)__cil_tmp20;
#line 857
  __cil_tmp22 = __cil_tmp21 + 815620U;
#line 857
  readl(__cil_tmp22);
#line 859
  __cil_tmp23 = (unsigned int const   )5000U;
#line 859
  __cil_tmp24 = (unsigned int )__cil_tmp23;
#line 859
  tmp___1 = msecs_to_jiffies(__cil_tmp24);
#line 859
  __cil_tmp25 = (unsigned long )jiffies;
#line 859
  timeout__ = tmp___1 + __cil_tmp25;
#line 859
  ret__ = 0;
  }
#line 859
  goto ldv_37905;
  ldv_37904: ;
  {
#line 859
  __cil_tmp26 = (long )jiffies;
#line 859
  __cil_tmp27 = (long )timeout__;
#line 859
  __cil_tmp28 = __cil_tmp27 - __cil_tmp26;
#line 859
  if (__cil_tmp28 < 0L) {
#line 859
    ret__ = -110;
#line 859
    goto ldv_37895;
  } else {

  }
  }
  {
#line 859
  tmp___2 = current_thread_info();
  }
  {
#line 859
  __cil_tmp29 = tmp___2->preempt_count;
#line 859
  __cil_tmp30 = __cil_tmp29 & -268435457;
#line 859
  if (__cil_tmp30 == 0) {
#line 859
    if (1) {
#line 859
      goto case_4;
    } else {
#line 859
      goto switch_default;
#line 859
      if (0) {
#line 859
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 859
        goto ldv_37898;
#line 859
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 859
        goto ldv_37898;
        case_4: 
#line 859
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 859
        goto ldv_37898;
#line 859
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 859
        goto ldv_37898;
        switch_default: 
        {
#line 859
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_37898: 
    {
#line 859
    __cil_tmp31 = (atomic_t const   *)(& kgdb_active);
#line 859
    tmp___3 = atomic_read(__cil_tmp31);
    }
#line 859
    if (pfo_ret__ != tmp___3) {
      {
#line 859
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_37905: 
  {
#line 859
  tmp___4 = i915_read32___10(dev_priv, 815616U);
  }
  {
#line 859
  __cil_tmp32 = tmp___4 & idle_on_mask;
#line 859
  if (__cil_tmp32 != idle_on_mask) {
#line 860
    goto ldv_37904;
  } else {
#line 862
    goto ldv_37895;
  }
  }
  ldv_37895: ;
#line 859
  if (ret__ != 0) {
    {
#line 861
    tmp___0 = i915_read32___10(dev_priv, 815616U);
#line 861
    drm_err("ironlake_edp_panel_on", "panel on wait timed out: 0x%08x\n", tmp___0);
    }
  } else {

  }
  {
#line 864
  pp = pp | 2U;
#line 865
  i915_write32___8(dev_priv, 815620U, pp);
#line 866
  __cil_tmp33 = dev_priv->regs;
#line 866
  __cil_tmp34 = (void const volatile   *)__cil_tmp33;
#line 866
  __cil_tmp35 = __cil_tmp34 + 815620U;
#line 866
  readl(__cil_tmp35);
  }
#line 868
  return ((bool )0);
}
}
#line 871 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_panel_off(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 pp ;
  u32 idle_off_mask ;
  u32 tmp ;
  unsigned long timeout__ ;
  unsigned long tmp___0 ;
  int ret__ ;
  struct thread_info *tmp___1 ;
  int pfo_ret__ ;
  int tmp___2 ;
  u32 tmp___3 ;
  void *__cil_tmp13 ;
  void *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  void const volatile   *__cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  long __cil_tmp23 ;
  long __cil_tmp24 ;
  long __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  atomic_t const   *__cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  void *__cil_tmp30 ;
  void const volatile   *__cil_tmp31 ;
  void const volatile   *__cil_tmp32 ;

  {
  {
#line 873
  __cil_tmp13 = dev->dev_private;
#line 873
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 874
  idle_off_mask = 3087007759U;
#line 877
  pp = i915_read32___10(dev_priv, 815620U);
#line 880
  pp = pp & 4294967293U;
#line 881
  i915_write32___8(dev_priv, 815620U, pp);
#line 882
  __cil_tmp14 = dev_priv->regs;
#line 882
  __cil_tmp15 = (void const volatile   *)__cil_tmp14;
#line 882
  __cil_tmp16 = __cil_tmp15 + 815620U;
#line 882
  readl(__cil_tmp16);
#line 884
  pp = pp & 4294967294U;
#line 885
  i915_write32___8(dev_priv, 815620U, pp);
#line 886
  __cil_tmp17 = dev_priv->regs;
#line 886
  __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 886
  __cil_tmp19 = __cil_tmp18 + 815620U;
#line 886
  readl(__cil_tmp19);
#line 888
  __cil_tmp20 = (unsigned int const   )5000U;
#line 888
  __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 888
  tmp___0 = msecs_to_jiffies(__cil_tmp21);
#line 888
  __cil_tmp22 = (unsigned long )jiffies;
#line 888
  timeout__ = tmp___0 + __cil_tmp22;
#line 888
  ret__ = 0;
  }
#line 888
  goto ldv_37932;
  ldv_37931: ;
  {
#line 888
  __cil_tmp23 = (long )jiffies;
#line 888
  __cil_tmp24 = (long )timeout__;
#line 888
  __cil_tmp25 = __cil_tmp24 - __cil_tmp23;
#line 888
  if (__cil_tmp25 < 0L) {
#line 888
    ret__ = -110;
#line 888
    goto ldv_37922;
  } else {

  }
  }
  {
#line 888
  tmp___1 = current_thread_info();
  }
  {
#line 888
  __cil_tmp26 = tmp___1->preempt_count;
#line 888
  __cil_tmp27 = __cil_tmp26 & -268435457;
#line 888
  if (__cil_tmp27 == 0) {
#line 888
    if (1) {
#line 888
      goto case_4;
    } else {
#line 888
      goto switch_default;
#line 888
      if (0) {
#line 888
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 888
        goto ldv_37925;
#line 888
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 888
        goto ldv_37925;
        case_4: 
#line 888
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 888
        goto ldv_37925;
#line 888
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 888
        goto ldv_37925;
        switch_default: 
        {
#line 888
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_37925: 
    {
#line 888
    __cil_tmp28 = (atomic_t const   *)(& kgdb_active);
#line 888
    tmp___2 = atomic_read(__cil_tmp28);
    }
#line 888
    if (pfo_ret__ != tmp___2) {
      {
#line 888
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_37932: 
  {
#line 888
  tmp___3 = i915_read32___10(dev_priv, 815616U);
  }
  {
#line 888
  __cil_tmp29 = tmp___3 & idle_off_mask;
#line 888
  if (__cil_tmp29 != 0U) {
#line 889
    goto ldv_37931;
  } else {
#line 891
    goto ldv_37922;
  }
  }
  ldv_37922: ;
#line 888
  if (ret__ != 0) {
    {
#line 889
    tmp = i915_read32___10(dev_priv, 815616U);
#line 889
    drm_err("ironlake_edp_panel_off", "panel off wait timed out: 0x%08x\n", tmp);
    }
  } else {

  }
  {
#line 892
  pp = pp | 2U;
#line 893
  i915_write32___8(dev_priv, 815620U, pp);
#line 894
  __cil_tmp30 = dev_priv->regs;
#line 894
  __cil_tmp31 = (void const volatile   *)__cil_tmp30;
#line 894
  __cil_tmp32 = __cil_tmp31 + 815620U;
#line 894
  readl(__cil_tmp32);
  }
#line 895
  return;
}
}
#line 897 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_backlight_on(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 pp ;
  void *__cil_tmp4 ;

  {
  {
#line 899
  __cil_tmp4 = dev->dev_private;
#line 899
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 902
  drm_ut_debug_printk(4U, "drm", "ironlake_edp_backlight_on", "\n");
#line 909
  msleep(300U);
#line 910
  pp = i915_read32___10(dev_priv, 815620U);
#line 911
  pp = pp | 4U;
#line 912
  i915_write32___8(dev_priv, 815620U, pp);
  }
#line 913
  return;
}
}
#line 915 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_backlight_off(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 pp ;
  void *__cil_tmp4 ;

  {
  {
#line 917
  __cil_tmp4 = dev->dev_private;
#line 917
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 920
  drm_ut_debug_printk(4U, "drm", "ironlake_edp_backlight_off", "\n");
#line 921
  pp = i915_read32___10(dev_priv, 815620U);
#line 922
  pp = pp & 4294967291U;
#line 923
  i915_write32___8(dev_priv, 815620U, pp);
  }
#line 924
  return;
}
}
#line 926 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_pll_on(struct drm_encoder *encoder ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 dpa_ctl ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;
  void const volatile   *__cil_tmp8 ;

  {
  {
#line 928
  dev = encoder->dev;
#line 929
  __cil_tmp5 = dev->dev_private;
#line 929
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 932
  drm_ut_debug_printk(4U, "drm", "ironlake_edp_pll_on", "\n");
#line 933
  dpa_ctl = i915_read32___10(dev_priv, 409600U);
#line 934
  dpa_ctl = dpa_ctl | 16384U;
#line 935
  i915_write32___8(dev_priv, 409600U, dpa_ctl);
#line 936
  __cil_tmp6 = dev_priv->regs;
#line 936
  __cil_tmp7 = (void const volatile   *)__cil_tmp6;
#line 936
  __cil_tmp8 = __cil_tmp7 + 409600U;
#line 936
  readl(__cil_tmp8);
#line 937
  __const_udelay(859000UL);
  }
#line 938
  return;
}
}
#line 940 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void ironlake_edp_pll_off(struct drm_encoder *encoder ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 dpa_ctl ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;
  void const volatile   *__cil_tmp8 ;

  {
  {
#line 942
  dev = encoder->dev;
#line 943
  __cil_tmp5 = dev->dev_private;
#line 943
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 946
  dpa_ctl = i915_read32___10(dev_priv, 409600U);
#line 947
  dpa_ctl = dpa_ctl & 4294950911U;
#line 948
  i915_write32___8(dev_priv, 409600U, dpa_ctl);
#line 949
  __cil_tmp6 = dev_priv->regs;
#line 949
  __cil_tmp7 = (void const volatile   *)__cil_tmp6;
#line 949
  __cil_tmp8 = __cil_tmp7 + 409600U;
#line 949
  readl(__cil_tmp8);
#line 950
  __const_udelay(859000UL);
  }
#line 951
  return;
}
}
#line 954 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_sink_dpms(struct intel_dp *intel_dp , int mode ) 
{ int ret ;
  int i ;
  uint8_t __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  uint16_t __cil_tmp7 ;
  uint8_t __cil_tmp8 ;
  uint16_t __cil_tmp9 ;
  uint8_t __cil_tmp10 ;

  {
  {
#line 959
  __cil_tmp5 = intel_dp->dpcd[0];
#line 959
  __cil_tmp6 = (unsigned int )__cil_tmp5;
#line 959
  if (__cil_tmp6 <= 16U) {
#line 960
    return;
  } else {

  }
  }
#line 962
  if (mode != 0) {
    {
#line 963
    __cil_tmp7 = (uint16_t )1536;
#line 963
    __cil_tmp8 = (uint8_t )2;
#line 963
    ret = intel_dp_aux_native_write_1(intel_dp, __cil_tmp7, __cil_tmp8);
    }
#line 965
    if (ret != 1) {
      {
#line 966
      drm_ut_debug_printk(2U, "drm", "intel_dp_sink_dpms", "failed to write sink power state\n");
      }
    } else {

    }
  } else {
#line 972
    i = 0;
#line 972
    goto ldv_37969;
    ldv_37968: 
    {
#line 973
    __cil_tmp9 = (uint16_t )1536;
#line 973
    __cil_tmp10 = (uint8_t )1;
#line 973
    ret = intel_dp_aux_native_write_1(intel_dp, __cil_tmp9, __cil_tmp10);
    }
#line 976
    if (ret == 1) {
#line 977
      goto ldv_37967;
    } else {

    }
    {
#line 978
    msleep(1U);
#line 972
    i = i + 1;
    }
    ldv_37969: ;
#line 972
    if (i <= 2) {
#line 973
      goto ldv_37968;
    } else {
#line 975
      goto ldv_37967;
    }
    ldv_37967: ;
  }
#line 978
  return;
}
}
#line 983 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_prepare(struct drm_encoder *encoder ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_device *dev ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;

  {
  {
#line 985
  tmp = enc_to_intel_dp(encoder);
#line 985
  intel_dp = tmp;
#line 986
  dev = encoder->dev;
#line 989
  intel_dp_sink_dpms(intel_dp, 0);
#line 991
  tmp___2 = is_edp(intel_dp);
  }
#line 991
  if ((int )tmp___2) {
    {
#line 992
    ironlake_edp_backlight_off(dev);
#line 993
    ironlake_edp_panel_off(dev);
#line 994
    tmp___0 = is_pch_edp(intel_dp);
    }
#line 994
    if (tmp___0) {
#line 994
      tmp___1 = 0;
    } else {
#line 994
      tmp___1 = 1;
    }
#line 994
    if (tmp___1) {
      {
#line 995
      ironlake_edp_pll_on(encoder);
      }
    } else {
      {
#line 997
      ironlake_edp_pll_off(encoder);
      }
    }
  } else {

  }
  {
#line 999
  intel_dp_link_down(intel_dp);
  }
#line 1000
  return;
}
}
#line 1002 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_commit(struct drm_encoder *encoder ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_device *dev ;
  bool tmp___0 ;
  bool tmp___1 ;
  bool tmp___2 ;

  {
  {
#line 1004
  tmp = enc_to_intel_dp(encoder);
#line 1004
  intel_dp = tmp;
#line 1005
  dev = encoder->dev;
#line 1007
  tmp___0 = is_edp(intel_dp);
  }
#line 1007
  if ((int )tmp___0) {
    {
#line 1008
    ironlake_edp_panel_vdd_on(intel_dp);
    }
  } else {

  }
  {
#line 1010
  intel_dp_start_link_train(intel_dp);
#line 1012
  tmp___1 = is_edp(intel_dp);
  }
#line 1012
  if ((int )tmp___1) {
    {
#line 1013
    ironlake_edp_panel_on(intel_dp);
#line 1014
    ironlake_edp_panel_vdd_off(intel_dp);
    }
  } else {

  }
  {
#line 1017
  intel_dp_complete_link_train(intel_dp);
#line 1019
  tmp___2 = is_edp(intel_dp);
  }
#line 1019
  if ((int )tmp___2) {
    {
#line 1020
    ironlake_edp_backlight_on(dev);
    }
  } else {

  }
#line 1021
  return;
}
}
#line 1024 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_dpms(struct drm_encoder *encoder , int mode ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  uint32_t dp_reg ;
  u32 tmp___0 ;
  bool tmp___1 ;
  bool tmp___2 ;
  bool tmp___3 ;
  bool tmp___4 ;
  int tmp___5 ;
  bool tmp___6 ;
  bool tmp___7 ;
  bool tmp___8 ;
  void *__cil_tmp17 ;
  uint32_t __cil_tmp18 ;
  int __cil_tmp19 ;

  {
  {
#line 1026
  tmp = enc_to_intel_dp(encoder);
#line 1026
  intel_dp = tmp;
#line 1027
  dev = encoder->dev;
#line 1028
  __cil_tmp17 = dev->dev_private;
#line 1028
  dev_priv = (struct drm_i915_private *)__cil_tmp17;
#line 1029
  __cil_tmp18 = intel_dp->output_reg;
#line 1029
  tmp___0 = i915_read32___10(dev_priv, __cil_tmp18);
#line 1029
  dp_reg = tmp___0;
  }
#line 1031
  if (mode != 0) {
    {
#line 1032
    tmp___1 = is_edp(intel_dp);
    }
#line 1032
    if ((int )tmp___1) {
      {
#line 1033
      ironlake_edp_backlight_off(dev);
      }
    } else {

    }
    {
#line 1034
    intel_dp_sink_dpms(intel_dp, mode);
#line 1035
    intel_dp_link_down(intel_dp);
#line 1036
    tmp___2 = is_edp(intel_dp);
    }
#line 1036
    if ((int )tmp___2) {
      {
#line 1037
      ironlake_edp_panel_off(dev);
      }
    } else {

    }
    {
#line 1038
    tmp___3 = is_edp(intel_dp);
    }
#line 1038
    if ((int )tmp___3) {
      {
#line 1038
      tmp___4 = is_pch_edp(intel_dp);
      }
#line 1038
      if (tmp___4) {
#line 1038
        tmp___5 = 0;
      } else {
#line 1038
        tmp___5 = 1;
      }
#line 1038
      if (tmp___5) {
        {
#line 1039
        ironlake_edp_pll_off(encoder);
        }
      } else {

      }
    } else {

    }
  } else {
    {
#line 1041
    tmp___6 = is_edp(intel_dp);
    }
#line 1041
    if ((int )tmp___6) {
      {
#line 1042
      ironlake_edp_panel_vdd_on(intel_dp);
      }
    } else {

    }
    {
#line 1043
    intel_dp_sink_dpms(intel_dp, mode);
    }
    {
#line 1044
    __cil_tmp19 = (int )dp_reg;
#line 1044
    if (__cil_tmp19 >= 0) {
      {
#line 1045
      intel_dp_start_link_train(intel_dp);
#line 1046
      tmp___7 = is_edp(intel_dp);
      }
#line 1046
      if ((int )tmp___7) {
        {
#line 1047
        ironlake_edp_panel_on(intel_dp);
#line 1048
        ironlake_edp_panel_vdd_off(intel_dp);
        }
      } else {

      }
      {
#line 1050
      intel_dp_complete_link_train(intel_dp);
      }
    } else {

    }
    }
    {
#line 1052
    tmp___8 = is_edp(intel_dp);
    }
#line 1052
    if ((int )tmp___8) {
      {
#line 1053
      ironlake_edp_backlight_on(dev);
      }
    } else {

    }
  }
#line 1055
  return;
}
}
#line 1062 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_dp_aux_native_read_retry(struct intel_dp *intel_dp , uint16_t address ,
                                           uint8_t *recv , int recv_bytes ) 
{ int ret ;
  int i ;
  int __cil_tmp7 ;
  uint16_t __cil_tmp8 ;

  {
#line 1071
  i = 0;
#line 1071
  goto ldv_37997;
  ldv_37996: 
  {
#line 1072
  __cil_tmp7 = (int )address;
#line 1072
  __cil_tmp8 = (uint16_t )__cil_tmp7;
#line 1072
  ret = intel_dp_aux_native_read(intel_dp, __cil_tmp8, recv, recv_bytes);
  }
#line 1074
  if (ret == recv_bytes) {
#line 1075
    return ((bool )1);
  } else {

  }
  {
#line 1076
  msleep(1U);
#line 1071
  i = i + 1;
  }
  ldv_37997: ;
#line 1071
  if (i <= 2) {
#line 1072
    goto ldv_37996;
  } else {
#line 1074
    goto ldv_37998;
  }
  ldv_37998: ;
#line 1079
  return ((bool )0);
}
}
#line 1087 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_dp_get_link_status(struct intel_dp *intel_dp ) 
{ bool tmp ;
  uint16_t __cil_tmp3 ;
  uint8_t (*__cil_tmp4)[6U] ;
  uint8_t *__cil_tmp5 ;

  {
  {
#line 1089
  __cil_tmp3 = (uint16_t )514;
#line 1089
  __cil_tmp4 = & intel_dp->link_status;
#line 1089
  __cil_tmp5 = (uint8_t *)__cil_tmp4;
#line 1089
  tmp = intel_dp_aux_native_read_retry(intel_dp, __cil_tmp3, __cil_tmp5, 6);
  }
#line 1089
  return (tmp);
}
}
#line 1096 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint8_t intel_dp_link_status(uint8_t *link_status , int r ) 
{ unsigned long __cil_tmp3 ;
  unsigned long __cil_tmp4 ;
  uint8_t *__cil_tmp5 ;

  {
  {
#line 1099
  __cil_tmp3 = (unsigned long )r;
#line 1099
  __cil_tmp4 = __cil_tmp3 + 1152921504606846462UL;
#line 1099
  __cil_tmp5 = link_status + __cil_tmp4;
#line 1099
  return (*__cil_tmp5);
  }
}
}
#line 1103 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint8_t intel_get_adjust_request_voltage(uint8_t *link_status , int lane ) 
{ int i ;
  int s ;
  int tmp ;
  uint8_t l ;
  uint8_t tmp___0 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  uint8_t __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;

  {
#line 1106
  __cil_tmp8 = lane >> 1;
#line 1106
  i = __cil_tmp8 + 518;
#line 1107
  if (lane & 1) {
#line 1107
    tmp = 4;
  } else {
#line 1107
    tmp = 0;
  }
  {
#line 1107
  s = tmp;
#line 1110
  tmp___0 = intel_dp_link_status(link_status, i);
#line 1110
  l = tmp___0;
  }
  {
#line 1112
  __cil_tmp9 = (int )l;
#line 1112
  __cil_tmp10 = __cil_tmp9 >> s;
#line 1112
  __cil_tmp11 = (uint8_t )__cil_tmp10;
#line 1112
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1112
  __cil_tmp13 = __cil_tmp12 & 3U;
#line 1112
  return ((uint8_t )__cil_tmp13);
  }
}
}
#line 1116 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint8_t intel_get_adjust_request_pre_emphasis(uint8_t *link_status , int lane ) 
{ int i ;
  int s ;
  int tmp ;
  uint8_t l ;
  uint8_t tmp___0 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  uint8_t __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;

  {
#line 1119
  __cil_tmp8 = lane >> 1;
#line 1119
  i = __cil_tmp8 + 518;
#line 1120
  if (lane & 1) {
#line 1120
    tmp = 6;
  } else {
#line 1120
    tmp = 2;
  }
  {
#line 1120
  s = tmp;
#line 1123
  tmp___0 = intel_dp_link_status(link_status, i);
#line 1123
  l = tmp___0;
  }
  {
#line 1125
  __cil_tmp9 = (int )l;
#line 1125
  __cil_tmp10 = __cil_tmp9 >> s;
#line 1125
  __cil_tmp11 = (uint8_t )__cil_tmp10;
#line 1125
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1125
  __cil_tmp13 = __cil_tmp12 & 3U;
#line 1125
  __cil_tmp14 = __cil_tmp13 << 3U;
#line 1125
  return ((uint8_t )__cil_tmp14);
  }
}
}
#line 1148 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint8_t intel_dp_pre_emphasis_max(uint8_t voltage_swing ) 
{ int __cil_tmp2 ;
  int __cil_tmp3 ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;

  {
  {
#line 1151
  __cil_tmp2 = (int )voltage_swing;
#line 1151
  __cil_tmp3 = __cil_tmp2 & 3;
#line 1151
  if (__cil_tmp3 == 0) {
#line 1151
    goto case_0;
  } else {
    {
#line 1153
    __cil_tmp4 = (int )voltage_swing;
#line 1153
    __cil_tmp5 = __cil_tmp4 & 3;
#line 1153
    if (__cil_tmp5 == 1) {
#line 1153
      goto case_1;
    } else {
      {
#line 1155
      __cil_tmp6 = (int )voltage_swing;
#line 1155
      __cil_tmp7 = __cil_tmp6 & 3;
#line 1155
      if (__cil_tmp7 == 2) {
#line 1155
        goto case_2;
      } else {
        {
#line 1157
        __cil_tmp8 = (int )voltage_swing;
#line 1157
        __cil_tmp9 = __cil_tmp8 & 3;
#line 1157
        if (__cil_tmp9 == 3) {
#line 1157
          goto case_3;
        } else {
#line 1158
          goto switch_default;
#line 1150
          if (0) {
            case_0: ;
#line 1152
            return ((uint8_t )16U);
            case_1: ;
#line 1154
            return ((uint8_t )16U);
            case_2: ;
#line 1156
            return ((uint8_t )8U);
            case_3: ;
            switch_default: ;
#line 1159
            return ((uint8_t )0U);
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
}
}
#line 1164 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_get_adjust_train(struct intel_dp *intel_dp ) 
{ uint8_t v ;
  uint8_t p ;
  int lane ;
  uint8_t this_v ;
  uint8_t tmp ;
  uint8_t this_p ;
  uint8_t tmp___0 ;
  uint8_t tmp___1 ;
  uint8_t tmp___2 ;
  uint8_t (*__cil_tmp11)[6U] ;
  uint8_t *__cil_tmp12 ;
  uint8_t (*__cil_tmp13)[6U] ;
  uint8_t *__cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  uint8_t __cil_tmp19 ;
  int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  int __cil_tmp22 ;
  uint8_t __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  uint8_t __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;

  {
#line 1166
  v = (uint8_t )0U;
#line 1167
  p = (uint8_t )0U;
#line 1170
  lane = 0;
#line 1170
  goto ldv_38037;
  ldv_38036: 
  {
#line 1171
  __cil_tmp11 = & intel_dp->link_status;
#line 1171
  __cil_tmp12 = (uint8_t *)__cil_tmp11;
#line 1171
  tmp = intel_get_adjust_request_voltage(__cil_tmp12, lane);
#line 1171
  this_v = tmp;
#line 1172
  __cil_tmp13 = & intel_dp->link_status;
#line 1172
  __cil_tmp14 = (uint8_t *)__cil_tmp13;
#line 1172
  tmp___0 = intel_get_adjust_request_pre_emphasis(__cil_tmp14, lane);
#line 1172
  this_p = tmp___0;
  }
  {
#line 1174
  __cil_tmp15 = (int )v;
#line 1174
  __cil_tmp16 = (int )this_v;
#line 1174
  if (__cil_tmp16 > __cil_tmp15) {
#line 1175
    v = this_v;
  } else {

  }
  }
  {
#line 1176
  __cil_tmp17 = (int )p;
#line 1176
  __cil_tmp18 = (int )this_p;
#line 1176
  if (__cil_tmp18 > __cil_tmp17) {
#line 1177
    p = this_p;
  } else {

  }
  }
#line 1170
  lane = lane + 1;
  ldv_38037: ;
  {
#line 1170
  __cil_tmp19 = intel_dp->lane_count;
#line 1170
  __cil_tmp20 = (int )__cil_tmp19;
#line 1170
  if (__cil_tmp20 > lane) {
#line 1171
    goto ldv_38036;
  } else {
#line 1173
    goto ldv_38038;
  }
  }
  ldv_38038: ;
  {
#line 1180
  __cil_tmp21 = (unsigned int )v;
#line 1180
  if (__cil_tmp21 > 1U) {
#line 1181
    v = (uint8_t )6U;
  } else {

  }
  }
  {
#line 1183
  __cil_tmp22 = (int )v;
#line 1183
  __cil_tmp23 = (uint8_t )__cil_tmp22;
#line 1183
  tmp___2 = intel_dp_pre_emphasis_max(__cil_tmp23);
  }
  {
#line 1183
  __cil_tmp24 = (int )p;
#line 1183
  __cil_tmp25 = (int )tmp___2;
#line 1183
  if (__cil_tmp25 <= __cil_tmp24) {
    {
#line 1184
    __cil_tmp26 = (int )v;
#line 1184
    __cil_tmp27 = (uint8_t )__cil_tmp26;
#line 1184
    tmp___1 = intel_dp_pre_emphasis_max(__cil_tmp27);
#line 1184
    __cil_tmp28 = (unsigned int )tmp___1;
#line 1184
    __cil_tmp29 = __cil_tmp28 | 32U;
#line 1184
    p = (uint8_t )__cil_tmp29;
    }
  } else {

  }
  }
#line 1186
  lane = 0;
#line 1186
  goto ldv_38040;
  ldv_38039: 
#line 1187
  __cil_tmp30 = (int )p;
#line 1187
  __cil_tmp31 = (int )v;
#line 1187
  __cil_tmp32 = __cil_tmp31 | __cil_tmp30;
#line 1187
  intel_dp->train_set[lane] = (uint8_t )__cil_tmp32;
#line 1186
  lane = lane + 1;
  ldv_38040: ;
#line 1186
  if (lane <= 3) {
#line 1187
    goto ldv_38039;
  } else {
#line 1189
    goto ldv_38041;
  }
  ldv_38041: ;
#line 1191
  return;
}
}
#line 1191 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint32_t intel_dp_signal_levels(uint8_t train_set , int lane_count ) 
{ uint32_t signal_levels ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;

  {
#line 1193
  signal_levels = 0U;
  {
#line 1196
  __cil_tmp4 = (int )train_set;
#line 1196
  __cil_tmp5 = __cil_tmp4 & 3;
#line 1196
  if (__cil_tmp5 == 0) {
#line 1196
    goto case_0;
  } else {
    {
#line 1200
    __cil_tmp6 = (int )train_set;
#line 1200
    __cil_tmp7 = __cil_tmp6 & 3;
#line 1200
    if (__cil_tmp7 == 1) {
#line 1200
      goto case_1;
    } else {
      {
#line 1203
      __cil_tmp8 = (int )train_set;
#line 1203
      __cil_tmp9 = __cil_tmp8 & 3;
#line 1203
      if (__cil_tmp9 == 2) {
#line 1203
        goto case_2;
      } else {
        {
#line 1206
        __cil_tmp10 = (int )train_set;
#line 1206
        __cil_tmp11 = __cil_tmp10 & 3;
#line 1206
        if (__cil_tmp11 == 3) {
#line 1206
          goto case_3;
        } else {
#line 1197
          goto switch_default;
#line 1195
          if (0) {
            case_0: ;
            switch_default: 
#line 1198
            signal_levels = signal_levels;
#line 1199
            goto ldv_38049;
            case_1: 
#line 1201
            signal_levels = signal_levels | 33554432U;
#line 1202
            goto ldv_38049;
            case_2: 
#line 1204
            signal_levels = signal_levels | 67108864U;
#line 1205
            goto ldv_38049;
            case_3: 
#line 1207
            signal_levels = signal_levels | 100663296U;
#line 1208
            goto ldv_38049;
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_38049: ;
  {
#line 1211
  __cil_tmp12 = (int )train_set;
#line 1211
  __cil_tmp13 = __cil_tmp12 & 24;
#line 1211
  if (__cil_tmp13 == 0) {
#line 1211
    goto case_0___0;
  } else {
    {
#line 1215
    __cil_tmp14 = (int )train_set;
#line 1215
    __cil_tmp15 = __cil_tmp14 & 24;
#line 1215
    if (__cil_tmp15 == 8) {
#line 1215
      goto case_8;
    } else {
      {
#line 1218
      __cil_tmp16 = (int )train_set;
#line 1218
      __cil_tmp17 = __cil_tmp16 & 24;
#line 1218
      if (__cil_tmp17 == 16) {
#line 1218
        goto case_16;
      } else {
        {
#line 1221
        __cil_tmp18 = (int )train_set;
#line 1221
        __cil_tmp19 = __cil_tmp18 & 24;
#line 1221
        if (__cil_tmp19 == 24) {
#line 1221
          goto case_24;
        } else {
#line 1212
          goto switch_default___0;
#line 1210
          if (0) {
            case_0___0: ;
            switch_default___0: 
#line 1213
            signal_levels = signal_levels;
#line 1214
            goto ldv_38055;
            case_8: 
#line 1216
            signal_levels = signal_levels | 4194304U;
#line 1217
            goto ldv_38055;
            case_16: 
#line 1219
            signal_levels = signal_levels | 8388608U;
#line 1220
            goto ldv_38055;
            case_24: 
#line 1222
            signal_levels = signal_levels | 12582912U;
#line 1223
            goto ldv_38055;
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_38055: ;
#line 1225
  return (signal_levels);
}
}
#line 1230 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint32_t intel_gen6_edp_signal_levels(uint8_t train_set ) 
{ int signal_levels ;
  int __cil_tmp3 ;

  {
#line 1232
  __cil_tmp3 = (int )train_set;
#line 1232
  signal_levels = __cil_tmp3 & 27;
#line 1235
  if (signal_levels == 0) {
#line 1235
    goto case_0;
  } else
#line 1236
  if (signal_levels == 1) {
#line 1236
    goto case_1;
  } else
#line 1238
  if (signal_levels == 8) {
#line 1238
    goto case_8;
  } else
#line 1240
  if (signal_levels == 16) {
#line 1240
    goto case_16;
  } else
#line 1241
  if (signal_levels == 17) {
#line 1241
    goto case_17;
  } else
#line 1243
  if (signal_levels == 9) {
#line 1243
    goto case_9;
  } else
#line 1244
  if (signal_levels == 10) {
#line 1244
    goto case_10;
  } else
#line 1246
  if (signal_levels == 2) {
#line 1246
    goto case_2;
  } else
#line 1247
  if (signal_levels == 3) {
#line 1247
    goto case_3;
  } else {
#line 1249
    goto switch_default;
#line 1234
    if (0) {
      case_0: ;
      case_1: ;
#line 1237
      return (0U);
      case_8: ;
#line 1239
      return (4194304U);
      case_16: ;
      case_17: ;
#line 1242
      return (243269632U);
      case_9: ;
      case_10: ;
#line 1245
      return (239075328U);
      case_2: ;
      case_3: ;
#line 1248
      return (234881024U);
      switch_default: 
      {
#line 1250
      drm_ut_debug_printk(4U, "drm", "intel_gen6_edp_signal_levels", "Unsupported voltage swing/pre-emphasis level:0x%x\n",
                          signal_levels);
      }
#line 1252
      return (0U);
    } else {

    }
  }
}
}
#line 1257 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static uint8_t intel_get_lane_status(uint8_t *link_status , int lane ) 
{ int i ;
  int s ;
  uint8_t l ;
  uint8_t tmp ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  uint8_t __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;

  {
  {
#line 1260
  __cil_tmp7 = lane >> 1;
#line 1260
  i = __cil_tmp7 + 514;
#line 1261
  __cil_tmp8 = lane & 1;
#line 1261
  s = __cil_tmp8 * 4;
#line 1262
  tmp = intel_dp_link_status(link_status, i);
#line 1262
  l = tmp;
  }
  {
#line 1264
  __cil_tmp9 = (int )l;
#line 1264
  __cil_tmp10 = __cil_tmp9 >> s;
#line 1264
  __cil_tmp11 = (uint8_t )__cil_tmp10;
#line 1264
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1264
  __cil_tmp13 = __cil_tmp12 & 15U;
#line 1264
  return ((uint8_t )__cil_tmp13);
  }
}
}
#line 1269 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_clock_recovery_ok(uint8_t *link_status , int lane_count ) 
{ int lane ;
  uint8_t lane_status ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;

  {
#line 1274
  lane = 0;
#line 1274
  goto ldv_38088;
  ldv_38087: 
  {
#line 1275
  lane_status = intel_get_lane_status(link_status, lane);
  }
  {
#line 1276
  __cil_tmp5 = (int )lane_status;
#line 1276
  __cil_tmp6 = __cil_tmp5 & 1;
#line 1276
  if (__cil_tmp6 == 0) {
#line 1277
    return ((bool )0);
  } else {

  }
  }
#line 1274
  lane = lane + 1;
  ldv_38088: ;
#line 1274
  if (lane < lane_count) {
#line 1275
    goto ldv_38087;
  } else {
#line 1277
    goto ldv_38089;
  }
  ldv_38089: ;
#line 1279
  return ((bool )1);
}
}
#line 1287 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_channel_eq_ok(struct intel_dp *intel_dp ) 
{ uint8_t lane_align ;
  uint8_t lane_status ;
  int lane ;
  uint8_t (*__cil_tmp5)[6U] ;
  uint8_t *__cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  uint8_t (*__cil_tmp9)[6U] ;
  uint8_t *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  uint8_t __cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 1293
  __cil_tmp5 = & intel_dp->link_status;
#line 1293
  __cil_tmp6 = (uint8_t *)__cil_tmp5;
#line 1293
  lane_align = intel_dp_link_status(__cil_tmp6, 516);
  }
  {
#line 1295
  __cil_tmp7 = (int )lane_align;
#line 1295
  __cil_tmp8 = __cil_tmp7 & 1;
#line 1295
  if (__cil_tmp8 == 0) {
#line 1296
    return ((bool )0);
  } else {

  }
  }
#line 1297
  lane = 0;
#line 1297
  goto ldv_38097;
  ldv_38096: 
  {
#line 1298
  __cil_tmp9 = & intel_dp->link_status;
#line 1298
  __cil_tmp10 = (uint8_t *)__cil_tmp9;
#line 1298
  lane_status = intel_get_lane_status(__cil_tmp10, lane);
  }
  {
#line 1299
  __cil_tmp11 = (int )lane_status;
#line 1299
  __cil_tmp12 = __cil_tmp11 & 7;
#line 1299
  if (__cil_tmp12 != 7) {
#line 1300
    return ((bool )0);
  } else {

  }
  }
#line 1297
  lane = lane + 1;
  ldv_38097: ;
  {
#line 1297
  __cil_tmp13 = intel_dp->lane_count;
#line 1297
  __cil_tmp14 = (int )__cil_tmp13;
#line 1297
  if (__cil_tmp14 > lane) {
#line 1298
    goto ldv_38096;
  } else {
#line 1300
    goto ldv_38098;
  }
  }
  ldv_38098: ;
#line 1302
  return ((bool )1);
}
}
#line 1306 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_dp_set_link_train(struct intel_dp *intel_dp , uint32_t dp_reg_value ,
                                    uint8_t dp_train_pat ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  int ret ;
  void *__cil_tmp7 ;
  uint32_t __cil_tmp8 ;
  uint32_t __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void const volatile   *__cil_tmp12 ;
  void const volatile   *__cil_tmp13 ;
  uint16_t __cil_tmp14 ;
  int __cil_tmp15 ;
  uint8_t __cil_tmp16 ;
  uint16_t __cil_tmp17 ;
  uint8_t (*__cil_tmp18)[4U] ;
  uint8_t *__cil_tmp19 ;

  {
  {
#line 1310
  dev = intel_dp->base.base.dev;
#line 1311
  __cil_tmp7 = dev->dev_private;
#line 1311
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
#line 1314
  __cil_tmp8 = intel_dp->output_reg;
#line 1314
  i915_write32___8(dev_priv, __cil_tmp8, dp_reg_value);
#line 1315
  __cil_tmp9 = intel_dp->output_reg;
#line 1315
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 1315
  __cil_tmp11 = dev_priv->regs;
#line 1315
  __cil_tmp12 = (void const volatile   *)__cil_tmp11;
#line 1315
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1315
  readl(__cil_tmp13);
#line 1317
  __cil_tmp14 = (uint16_t )258;
#line 1317
  __cil_tmp15 = (int )dp_train_pat;
#line 1317
  __cil_tmp16 = (uint8_t )__cil_tmp15;
#line 1317
  intel_dp_aux_native_write_1(intel_dp, __cil_tmp14, __cil_tmp16);
#line 1321
  __cil_tmp17 = (uint16_t )259;
#line 1321
  __cil_tmp18 = & intel_dp->train_set;
#line 1321
  __cil_tmp19 = (uint8_t *)__cil_tmp18;
#line 1321
  ret = intel_dp_aux_native_write(intel_dp, __cil_tmp17, __cil_tmp19, 4);
  }
#line 1324
  if (ret != 4) {
#line 1325
    return ((bool )0);
  } else {

  }
#line 1327
  return ((bool )1);
}
}
#line 1332 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_start_link_train(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  int i ;
  uint8_t voltage ;
  bool clock_recovery ;
  int tries ;
  u32 reg ;
  uint32_t DP ;
  bool tmp ;
  int tmp___0 ;
  uint32_t signal_levels ;
  bool tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  bool tmp___4 ;
  int tmp___5 ;
  bool tmp___6 ;
  int tmp___7 ;
  bool tmp___8 ;
  void *__cil_tmp23 ;
  struct drm_crtc *__cil_tmp24 ;
  uint32_t __cil_tmp25 ;
  uint32_t __cil_tmp26 ;
  uint32_t __cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  void *__cil_tmp29 ;
  void const volatile   *__cil_tmp30 ;
  void const volatile   *__cil_tmp31 ;
  enum pipe __cil_tmp32 ;
  int __cil_tmp33 ;
  uint16_t __cil_tmp34 ;
  uint8_t (*__cil_tmp35)[9U] ;
  uint8_t *__cil_tmp36 ;
  void *__cil_tmp37 ;
  struct drm_i915_private *__cil_tmp38 ;
  enum intel_pch __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  uint8_t (*__cil_tmp41)[4U] ;
  void *__cil_tmp42 ;
  void *__cil_tmp43 ;
  struct drm_i915_private *__cil_tmp44 ;
  struct intel_device_info  const  *__cil_tmp45 ;
  u8 __cil_tmp46 ;
  unsigned char __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  uint8_t __cil_tmp49 ;
  int __cil_tmp50 ;
  uint8_t __cil_tmp51 ;
  unsigned int __cil_tmp52 ;
  uint8_t __cil_tmp53 ;
  int __cil_tmp54 ;
  uint8_t __cil_tmp55 ;
  uint8_t __cil_tmp56 ;
  int __cil_tmp57 ;
  unsigned int __cil_tmp58 ;
  uint8_t __cil_tmp59 ;
  int __cil_tmp60 ;
  uint8_t __cil_tmp61 ;
  uint8_t __cil_tmp62 ;
  int __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  void *__cil_tmp65 ;
  struct drm_i915_private *__cil_tmp66 ;
  enum intel_pch __cil_tmp67 ;
  unsigned int __cil_tmp68 ;
  uint8_t __cil_tmp69 ;
  uint8_t (*__cil_tmp70)[6U] ;
  uint8_t *__cil_tmp71 ;
  uint8_t __cil_tmp72 ;
  int __cil_tmp73 ;
  uint8_t __cil_tmp74 ;
  int __cil_tmp75 ;
  int __cil_tmp76 ;
  uint8_t __cil_tmp77 ;
  int __cil_tmp78 ;
  uint8_t __cil_tmp79 ;
  int __cil_tmp80 ;
  int __cil_tmp81 ;
  uint8_t __cil_tmp82 ;
  int __cil_tmp83 ;
  int __cil_tmp84 ;
  uint8_t __cil_tmp85 ;
  unsigned int __cil_tmp86 ;
  unsigned int __cil_tmp87 ;

  {
  {
#line 1334
  dev = intel_dp->base.base.dev;
#line 1335
  __cil_tmp23 = dev->dev_private;
#line 1335
  dev_priv = (struct drm_i915_private *)__cil_tmp23;
#line 1336
  __cil_tmp24 = intel_dp->base.base.crtc;
#line 1336
  __mptr = (struct drm_crtc  const  *)__cil_tmp24;
#line 1336
  intel_crtc = (struct intel_crtc *)__mptr;
#line 1339
  clock_recovery = (bool )0;
#line 1342
  DP = intel_dp->DP;
#line 1345
  __cil_tmp25 = intel_dp->output_reg;
#line 1345
  __cil_tmp26 = intel_dp->DP;
#line 1345
  i915_write32___8(dev_priv, __cil_tmp25, __cil_tmp26);
#line 1346
  __cil_tmp27 = intel_dp->output_reg;
#line 1346
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 1346
  __cil_tmp29 = dev_priv->regs;
#line 1346
  __cil_tmp30 = (void const volatile   *)__cil_tmp29;
#line 1346
  __cil_tmp31 = __cil_tmp30 + __cil_tmp28;
#line 1346
  readl(__cil_tmp31);
#line 1347
  __cil_tmp32 = intel_crtc->pipe;
#line 1347
  __cil_tmp33 = (int )__cil_tmp32;
#line 1347
  intel_wait_for_vblank(dev, __cil_tmp33);
#line 1350
  __cil_tmp34 = (uint16_t )256;
#line 1350
  __cil_tmp35 = & intel_dp->link_configuration;
#line 1350
  __cil_tmp36 = (uint8_t *)__cil_tmp35;
#line 1350
  intel_dp_aux_native_write(intel_dp, __cil_tmp34, __cil_tmp36, 9);
#line 1354
  DP = DP | 2147483648U;
  }
  {
#line 1355
  __cil_tmp37 = dev->dev_private;
#line 1355
  __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
#line 1355
  __cil_tmp39 = __cil_tmp38->pch_type;
#line 1355
  __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 1355
  if (__cil_tmp40 == 1U) {
    {
#line 1355
    tmp = is_edp(intel_dp);
    }
#line 1355
    if (tmp) {
#line 1355
      tmp___0 = 0;
    } else {
#line 1355
      tmp___0 = 1;
    }
#line 1355
    if (tmp___0) {
#line 1356
      DP = DP & 4294965503U;
    } else {
#line 1358
      DP = DP & 3489660927U;
    }
  } else {
#line 1358
    DP = DP & 3489660927U;
  }
  }
  {
#line 1359
  __cil_tmp41 = & intel_dp->train_set;
#line 1359
  __cil_tmp42 = (void *)__cil_tmp41;
#line 1359
  memset(__cil_tmp42, 0, 4UL);
#line 1360
  voltage = (uint8_t )255U;
#line 1361
  tries = 0;
#line 1362
  clock_recovery = (bool )0;
  }
  ldv_38126: ;
  {
#line 1366
  __cil_tmp43 = dev->dev_private;
#line 1366
  __cil_tmp44 = (struct drm_i915_private *)__cil_tmp43;
#line 1366
  __cil_tmp45 = __cil_tmp44->info;
#line 1366
  __cil_tmp46 = __cil_tmp45->gen;
#line 1366
  __cil_tmp47 = (unsigned char )__cil_tmp46;
#line 1366
  __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 1366
  if (__cil_tmp48 == 6U) {
    {
#line 1366
    tmp___1 = is_edp(intel_dp);
    }
#line 1366
    if ((int )tmp___1) {
      {
#line 1367
      __cil_tmp49 = intel_dp->train_set[0];
#line 1367
      __cil_tmp50 = (int )__cil_tmp49;
#line 1367
      __cil_tmp51 = (uint8_t )__cil_tmp50;
#line 1367
      signal_levels = intel_gen6_edp_signal_levels(__cil_tmp51);
#line 1368
      __cil_tmp52 = DP & 4030726143U;
#line 1368
      DP = __cil_tmp52 | signal_levels;
      }
    } else {
      {
#line 1370
      __cil_tmp53 = intel_dp->train_set[0];
#line 1370
      __cil_tmp54 = (int )__cil_tmp53;
#line 1370
      __cil_tmp55 = (uint8_t )__cil_tmp54;
#line 1370
      __cil_tmp56 = intel_dp->lane_count;
#line 1370
      __cil_tmp57 = (int )__cil_tmp56;
#line 1370
      signal_levels = intel_dp_signal_levels(__cil_tmp55, __cil_tmp57);
#line 1371
      __cil_tmp58 = DP & 4030726143U;
#line 1371
      DP = __cil_tmp58 | signal_levels;
      }
    }
  } else {
    {
#line 1370
    __cil_tmp59 = intel_dp->train_set[0];
#line 1370
    __cil_tmp60 = (int )__cil_tmp59;
#line 1370
    __cil_tmp61 = (uint8_t )__cil_tmp60;
#line 1370
    __cil_tmp62 = intel_dp->lane_count;
#line 1370
    __cil_tmp63 = (int )__cil_tmp62;
#line 1370
    signal_levels = intel_dp_signal_levels(__cil_tmp61, __cil_tmp63);
#line 1371
    __cil_tmp64 = DP & 4030726143U;
#line 1371
    DP = __cil_tmp64 | signal_levels;
    }
  }
  }
  {
#line 1374
  __cil_tmp65 = dev->dev_private;
#line 1374
  __cil_tmp66 = (struct drm_i915_private *)__cil_tmp65;
#line 1374
  __cil_tmp67 = __cil_tmp66->pch_type;
#line 1374
  __cil_tmp68 = (unsigned int )__cil_tmp67;
#line 1374
  if (__cil_tmp68 == 1U) {
    {
#line 1374
    tmp___2 = is_edp(intel_dp);
    }
#line 1374
    if (tmp___2) {
#line 1374
      tmp___3 = 0;
    } else {
#line 1374
      tmp___3 = 1;
    }
#line 1374
    if (tmp___3) {
#line 1375
      reg = DP;
    } else {
#line 1377
      reg = DP;
    }
  } else {
#line 1377
    reg = DP;
  }
  }
  {
#line 1379
  __cil_tmp69 = (uint8_t )1;
#line 1379
  tmp___4 = intel_dp_set_link_train(intel_dp, reg, __cil_tmp69);
  }
#line 1379
  if (tmp___4) {
#line 1379
    tmp___5 = 0;
  } else {
#line 1379
    tmp___5 = 1;
  }
#line 1379
  if (tmp___5) {
#line 1381
    goto ldv_38122;
  } else {

  }
  {
#line 1384
  __const_udelay(429500UL);
#line 1385
  tmp___6 = intel_dp_get_link_status(intel_dp);
  }
#line 1385
  if (tmp___6) {
#line 1385
    tmp___7 = 0;
  } else {
#line 1385
    tmp___7 = 1;
  }
#line 1385
  if (tmp___7) {
#line 1386
    goto ldv_38122;
  } else {

  }
  {
#line 1388
  __cil_tmp70 = & intel_dp->link_status;
#line 1388
  __cil_tmp71 = (uint8_t *)__cil_tmp70;
#line 1388
  __cil_tmp72 = intel_dp->lane_count;
#line 1388
  __cil_tmp73 = (int )__cil_tmp72;
#line 1388
  tmp___8 = intel_clock_recovery_ok(__cil_tmp71, __cil_tmp73);
  }
#line 1388
  if ((int )tmp___8) {
#line 1389
    clock_recovery = (bool )1;
#line 1390
    goto ldv_38122;
  } else {

  }
#line 1394
  i = 0;
#line 1394
  goto ldv_38125;
  ldv_38124: ;
  {
#line 1395
  __cil_tmp74 = intel_dp->train_set[i];
#line 1395
  __cil_tmp75 = (int )__cil_tmp74;
#line 1395
  __cil_tmp76 = __cil_tmp75 & 4;
#line 1395
  if (__cil_tmp76 == 0) {
#line 1396
    goto ldv_38123;
  } else {

  }
  }
#line 1394
  i = i + 1;
  ldv_38125: ;
  {
#line 1394
  __cil_tmp77 = intel_dp->lane_count;
#line 1394
  __cil_tmp78 = (int )__cil_tmp77;
#line 1394
  if (__cil_tmp78 > i) {
#line 1395
    goto ldv_38124;
  } else {
#line 1397
    goto ldv_38123;
  }
  }
  ldv_38123: ;
  {
#line 1397
  __cil_tmp79 = intel_dp->lane_count;
#line 1397
  __cil_tmp80 = (int )__cil_tmp79;
#line 1397
  if (__cil_tmp80 == i) {
#line 1398
    goto ldv_38122;
  } else {

  }
  }
  {
#line 1401
  __cil_tmp81 = (int )voltage;
#line 1401
  __cil_tmp82 = intel_dp->train_set[0];
#line 1401
  __cil_tmp83 = (int )__cil_tmp82;
#line 1401
  __cil_tmp84 = __cil_tmp83 & 3;
#line 1401
  if (__cil_tmp84 == __cil_tmp81) {
#line 1402
    tries = tries + 1;
#line 1403
    if (tries == 5) {
#line 1404
      goto ldv_38122;
    } else {

    }
  } else {
#line 1406
    tries = 0;
  }
  }
  {
#line 1407
  __cil_tmp85 = intel_dp->train_set[0];
#line 1407
  __cil_tmp86 = (unsigned int )__cil_tmp85;
#line 1407
  __cil_tmp87 = __cil_tmp86 & 3U;
#line 1407
  voltage = (uint8_t )__cil_tmp87;
#line 1410
  intel_get_adjust_train(intel_dp);
  }
#line 1411
  goto ldv_38126;
  ldv_38122: 
#line 1413
  intel_dp->DP = DP;
#line 1414
  return;
}
}
#line 1417 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_complete_link_train(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  bool channel_eq ;
  int tries ;
  int cr_tries ;
  u32 reg ;
  uint32_t DP ;
  uint32_t signal_levels ;
  bool tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  bool tmp___4 ;
  int tmp___5 ;
  bool tmp___6 ;
  int tmp___7 ;
  bool tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  void *__cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  uint8_t __cil_tmp29 ;
  int __cil_tmp30 ;
  uint8_t __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  uint8_t __cil_tmp33 ;
  int __cil_tmp34 ;
  uint8_t __cil_tmp35 ;
  uint8_t __cil_tmp36 ;
  int __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  uint8_t __cil_tmp39 ;
  int __cil_tmp40 ;
  uint8_t __cil_tmp41 ;
  uint8_t __cil_tmp42 ;
  int __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  void *__cil_tmp45 ;
  struct drm_i915_private *__cil_tmp46 ;
  enum intel_pch __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  uint8_t __cil_tmp49 ;
  uint8_t (*__cil_tmp50)[6U] ;
  uint8_t *__cil_tmp51 ;
  uint8_t __cil_tmp52 ;
  int __cil_tmp53 ;
  void *__cil_tmp54 ;
  struct drm_i915_private *__cil_tmp55 ;
  enum intel_pch __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  uint32_t __cil_tmp58 ;
  uint32_t __cil_tmp59 ;
  unsigned long __cil_tmp60 ;
  void *__cil_tmp61 ;
  void const volatile   *__cil_tmp62 ;
  void const volatile   *__cil_tmp63 ;
  uint16_t __cil_tmp64 ;
  uint8_t __cil_tmp65 ;

  {
#line 1419
  dev = intel_dp->base.base.dev;
#line 1420
  __cil_tmp22 = dev->dev_private;
#line 1420
  dev_priv = (struct drm_i915_private *)__cil_tmp22;
#line 1421
  channel_eq = (bool )0;
#line 1424
  DP = intel_dp->DP;
#line 1427
  tries = 0;
#line 1428
  cr_tries = 0;
#line 1429
  channel_eq = (bool )0;
  ldv_38141: ;
#line 1434
  if (cr_tries > 5) {
    {
#line 1435
    drm_err("intel_dp_complete_link_train", "failed to train DP, aborting\n");
#line 1436
    intel_dp_link_down(intel_dp);
    }
#line 1437
    goto ldv_38139;
  } else {

  }
  {
#line 1440
  __cil_tmp23 = dev->dev_private;
#line 1440
  __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 1440
  __cil_tmp25 = __cil_tmp24->info;
#line 1440
  __cil_tmp26 = __cil_tmp25->gen;
#line 1440
  __cil_tmp27 = (unsigned char )__cil_tmp26;
#line 1440
  __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 1440
  if (__cil_tmp28 == 6U) {
    {
#line 1440
    tmp = is_edp(intel_dp);
    }
#line 1440
    if ((int )tmp) {
      {
#line 1441
      __cil_tmp29 = intel_dp->train_set[0];
#line 1441
      __cil_tmp30 = (int )__cil_tmp29;
#line 1441
      __cil_tmp31 = (uint8_t )__cil_tmp30;
#line 1441
      signal_levels = intel_gen6_edp_signal_levels(__cil_tmp31);
#line 1442
      __cil_tmp32 = DP & 4030726143U;
#line 1442
      DP = __cil_tmp32 | signal_levels;
      }
    } else {
      {
#line 1444
      __cil_tmp33 = intel_dp->train_set[0];
#line 1444
      __cil_tmp34 = (int )__cil_tmp33;
#line 1444
      __cil_tmp35 = (uint8_t )__cil_tmp34;
#line 1444
      __cil_tmp36 = intel_dp->lane_count;
#line 1444
      __cil_tmp37 = (int )__cil_tmp36;
#line 1444
      signal_levels = intel_dp_signal_levels(__cil_tmp35, __cil_tmp37);
#line 1445
      __cil_tmp38 = DP & 4030726143U;
#line 1445
      DP = __cil_tmp38 | signal_levels;
      }
    }
  } else {
    {
#line 1444
    __cil_tmp39 = intel_dp->train_set[0];
#line 1444
    __cil_tmp40 = (int )__cil_tmp39;
#line 1444
    __cil_tmp41 = (uint8_t )__cil_tmp40;
#line 1444
    __cil_tmp42 = intel_dp->lane_count;
#line 1444
    __cil_tmp43 = (int )__cil_tmp42;
#line 1444
    signal_levels = intel_dp_signal_levels(__cil_tmp41, __cil_tmp43);
#line 1445
    __cil_tmp44 = DP & 4030726143U;
#line 1445
    DP = __cil_tmp44 | signal_levels;
    }
  }
  }
  {
#line 1448
  __cil_tmp45 = dev->dev_private;
#line 1448
  __cil_tmp46 = (struct drm_i915_private *)__cil_tmp45;
#line 1448
  __cil_tmp47 = __cil_tmp46->pch_type;
#line 1448
  __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 1448
  if (__cil_tmp48 == 1U) {
    {
#line 1448
    tmp___0 = is_edp(intel_dp);
    }
#line 1448
    if (tmp___0) {
#line 1448
      tmp___1 = 0;
    } else {
#line 1448
      tmp___1 = 1;
    }
#line 1448
    if (tmp___1) {
#line 1449
      reg = DP | 256U;
    } else {
#line 1451
      reg = DP | 268435456U;
    }
  } else {
#line 1451
    reg = DP | 268435456U;
  }
  }
  {
#line 1454
  __cil_tmp49 = (uint8_t )2;
#line 1454
  tmp___2 = intel_dp_set_link_train(intel_dp, reg, __cil_tmp49);
  }
#line 1454
  if (tmp___2) {
#line 1454
    tmp___3 = 0;
  } else {
#line 1454
    tmp___3 = 1;
  }
#line 1454
  if (tmp___3) {
#line 1456
    goto ldv_38139;
  } else {

  }
  {
#line 1458
  __const_udelay(1718000UL);
#line 1459
  tmp___4 = intel_dp_get_link_status(intel_dp);
  }
#line 1459
  if (tmp___4) {
#line 1459
    tmp___5 = 0;
  } else {
#line 1459
    tmp___5 = 1;
  }
#line 1459
  if (tmp___5) {
#line 1460
    goto ldv_38139;
  } else {

  }
  {
#line 1463
  __cil_tmp50 = & intel_dp->link_status;
#line 1463
  __cil_tmp51 = (uint8_t *)__cil_tmp50;
#line 1463
  __cil_tmp52 = intel_dp->lane_count;
#line 1463
  __cil_tmp53 = (int )__cil_tmp52;
#line 1463
  tmp___6 = intel_clock_recovery_ok(__cil_tmp51, __cil_tmp53);
  }
#line 1463
  if (tmp___6) {
#line 1463
    tmp___7 = 0;
  } else {
#line 1463
    tmp___7 = 1;
  }
#line 1463
  if (tmp___7) {
    {
#line 1464
    intel_dp_start_link_train(intel_dp);
#line 1465
    cr_tries = cr_tries + 1;
    }
#line 1466
    goto ldv_38140;
  } else {

  }
  {
#line 1469
  tmp___8 = intel_channel_eq_ok(intel_dp);
  }
#line 1469
  if ((int )tmp___8) {
#line 1470
    channel_eq = (bool )1;
#line 1471
    goto ldv_38139;
  } else {

  }
#line 1475
  if (tries > 5) {
    {
#line 1476
    intel_dp_link_down(intel_dp);
#line 1477
    intel_dp_start_link_train(intel_dp);
#line 1478
    tries = 0;
#line 1479
    cr_tries = cr_tries + 1;
    }
#line 1480
    goto ldv_38140;
  } else {

  }
  {
#line 1484
  intel_get_adjust_train(intel_dp);
#line 1485
  tries = tries + 1;
  }
  ldv_38140: ;
#line 1486
  goto ldv_38141;
  ldv_38139: ;
  {
#line 1488
  __cil_tmp54 = dev->dev_private;
#line 1488
  __cil_tmp55 = (struct drm_i915_private *)__cil_tmp54;
#line 1488
  __cil_tmp56 = __cil_tmp55->pch_type;
#line 1488
  __cil_tmp57 = (unsigned int )__cil_tmp56;
#line 1488
  if (__cil_tmp57 == 1U) {
    {
#line 1488
    tmp___9 = is_edp(intel_dp);
    }
#line 1488
    if (tmp___9) {
#line 1488
      tmp___10 = 0;
    } else {
#line 1488
      tmp___10 = 1;
    }
#line 1488
    if (tmp___10) {
#line 1489
      reg = DP | 768U;
    } else {
#line 1491
      reg = DP | 805306368U;
    }
  } else {
#line 1491
    reg = DP | 805306368U;
  }
  }
  {
#line 1493
  __cil_tmp58 = intel_dp->output_reg;
#line 1493
  i915_write32___8(dev_priv, __cil_tmp58, reg);
#line 1494
  __cil_tmp59 = intel_dp->output_reg;
#line 1494
  __cil_tmp60 = (unsigned long )__cil_tmp59;
#line 1494
  __cil_tmp61 = dev_priv->regs;
#line 1494
  __cil_tmp62 = (void const volatile   *)__cil_tmp61;
#line 1494
  __cil_tmp63 = __cil_tmp62 + __cil_tmp60;
#line 1494
  readl(__cil_tmp63);
#line 1495
  __cil_tmp64 = (uint16_t )258;
#line 1495
  __cil_tmp65 = (uint8_t )0;
#line 1495
  intel_dp_aux_native_write_1(intel_dp, __cil_tmp64, __cil_tmp65);
  }
#line 1496
  return;
}
}
#line 1500 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_link_down(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  uint32_t DP ;
  u32 tmp ;
  bool tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  struct drm_crtc *crtc ;
  struct drm_crtc  const  *__mptr ;
  u32 tmp___4 ;
  void *__cil_tmp13 ;
  uint32_t __cil_tmp14 ;
  int __cil_tmp15 ;
  uint32_t __cil_tmp16 ;
  uint32_t __cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  void *__cil_tmp19 ;
  void const volatile   *__cil_tmp20 ;
  void const volatile   *__cil_tmp21 ;
  void *__cil_tmp22 ;
  struct drm_i915_private *__cil_tmp23 ;
  enum intel_pch __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  uint32_t __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  uint32_t __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  uint32_t __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  uint32_t __cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  void *__cil_tmp34 ;
  void const volatile   *__cil_tmp35 ;
  void const volatile   *__cil_tmp36 ;
  void *__cil_tmp37 ;
  struct drm_i915_private *__cil_tmp38 ;
  enum intel_pch __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  uint32_t __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  uint32_t __cil_tmp43 ;
  struct drm_crtc *__cil_tmp44 ;
  unsigned long __cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  uint32_t __cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  void *__cil_tmp49 ;
  void const volatile   *__cil_tmp50 ;
  void const volatile   *__cil_tmp51 ;
  struct intel_crtc *__cil_tmp52 ;
  enum pipe __cil_tmp53 ;
  int __cil_tmp54 ;
  uint32_t __cil_tmp55 ;
  unsigned int __cil_tmp56 ;
  uint32_t __cil_tmp57 ;
  unsigned long __cil_tmp58 ;
  void *__cil_tmp59 ;
  void const volatile   *__cil_tmp60 ;
  void const volatile   *__cil_tmp61 ;

  {
  {
#line 1502
  dev = intel_dp->base.base.dev;
#line 1503
  __cil_tmp13 = dev->dev_private;
#line 1503
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 1504
  DP = intel_dp->DP;
#line 1506
  __cil_tmp14 = intel_dp->output_reg;
#line 1506
  tmp = i915_read32___10(dev_priv, __cil_tmp14);
  }
  {
#line 1506
  __cil_tmp15 = (int )tmp;
#line 1506
  if (__cil_tmp15 >= 0) {
#line 1507
    return;
  } else {

  }
  }
  {
#line 1509
  drm_ut_debug_printk(4U, "drm", "intel_dp_link_down", "\n");
#line 1511
  tmp___0 = is_edp(intel_dp);
  }
#line 1511
  if ((int )tmp___0) {
    {
#line 1512
    DP = DP & 4294950911U;
#line 1513
    __cil_tmp16 = intel_dp->output_reg;
#line 1513
    i915_write32___8(dev_priv, __cil_tmp16, DP);
#line 1514
    __cil_tmp17 = intel_dp->output_reg;
#line 1514
    __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 1514
    __cil_tmp19 = dev_priv->regs;
#line 1514
    __cil_tmp20 = (void const volatile   *)__cil_tmp19;
#line 1514
    __cil_tmp21 = __cil_tmp20 + __cil_tmp18;
#line 1514
    readl(__cil_tmp21);
#line 1515
    __const_udelay(429500UL);
    }
  } else {

  }
  {
#line 1518
  __cil_tmp22 = dev->dev_private;
#line 1518
  __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
#line 1518
  __cil_tmp24 = __cil_tmp23->pch_type;
#line 1518
  __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 1518
  if (__cil_tmp25 == 1U) {
    {
#line 1518
    tmp___1 = is_edp(intel_dp);
    }
#line 1518
    if (tmp___1) {
#line 1518
      tmp___2 = 0;
    } else {
#line 1518
      tmp___2 = 1;
    }
#line 1518
    if (tmp___2) {
      {
#line 1519
      DP = DP & 4294965503U;
#line 1520
      __cil_tmp26 = intel_dp->output_reg;
#line 1520
      __cil_tmp27 = DP | 512U;
#line 1520
      i915_write32___8(dev_priv, __cil_tmp26, __cil_tmp27);
      }
    } else {
      {
#line 1522
      DP = DP & 3489660927U;
#line 1523
      __cil_tmp28 = intel_dp->output_reg;
#line 1523
      __cil_tmp29 = DP | 536870912U;
#line 1523
      i915_write32___8(dev_priv, __cil_tmp28, __cil_tmp29);
      }
    }
  } else {
    {
#line 1522
    DP = DP & 3489660927U;
#line 1523
    __cil_tmp30 = intel_dp->output_reg;
#line 1523
    __cil_tmp31 = DP | 536870912U;
#line 1523
    i915_write32___8(dev_priv, __cil_tmp30, __cil_tmp31);
    }
  }
  }
  {
#line 1525
  __cil_tmp32 = intel_dp->output_reg;
#line 1525
  __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 1525
  __cil_tmp34 = dev_priv->regs;
#line 1525
  __cil_tmp35 = (void const volatile   *)__cil_tmp34;
#line 1525
  __cil_tmp36 = __cil_tmp35 + __cil_tmp33;
#line 1525
  readl(__cil_tmp36);
#line 1527
  msleep(17U);
#line 1529
  tmp___3 = is_edp(intel_dp);
  }
#line 1529
  if ((int )tmp___3) {
#line 1530
    DP = DP | 805306368U;
  } else {

  }
  {
#line 1532
  __cil_tmp37 = dev->dev_private;
#line 1532
  __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
#line 1532
  __cil_tmp39 = __cil_tmp38->pch_type;
#line 1532
  __cil_tmp40 = (unsigned int )__cil_tmp39;
#line 1532
  if (__cil_tmp40 != 1U) {
    {
#line 1532
    __cil_tmp41 = intel_dp->output_reg;
#line 1532
    tmp___4 = i915_read32___10(dev_priv, __cil_tmp41);
    }
    {
#line 1532
    __cil_tmp42 = tmp___4 & 1073741824U;
#line 1532
    if (__cil_tmp42 != 0U) {
      {
#line 1534
      crtc = intel_dp->base.base.crtc;
#line 1544
      DP = DP & 3221225471U;
#line 1545
      __cil_tmp43 = intel_dp->output_reg;
#line 1545
      i915_write32___8(dev_priv, __cil_tmp43, DP);
      }
      {
#line 1550
      __cil_tmp44 = (struct drm_crtc *)0;
#line 1550
      __cil_tmp45 = (unsigned long )__cil_tmp44;
#line 1550
      __cil_tmp46 = (unsigned long )crtc;
#line 1550
      if (__cil_tmp46 == __cil_tmp45) {
        {
#line 1559
        __cil_tmp47 = intel_dp->output_reg;
#line 1559
        __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 1559
        __cil_tmp49 = dev_priv->regs;
#line 1559
        __cil_tmp50 = (void const volatile   *)__cil_tmp49;
#line 1559
        __cil_tmp51 = __cil_tmp50 + __cil_tmp48;
#line 1559
        readl(__cil_tmp51);
#line 1560
        msleep(50U);
        }
      } else {
        {
#line 1562
        __mptr = (struct drm_crtc  const  *)crtc;
#line 1562
        __cil_tmp52 = (struct intel_crtc *)__mptr;
#line 1562
        __cil_tmp53 = __cil_tmp52->pipe;
#line 1562
        __cil_tmp54 = (int )__cil_tmp53;
#line 1562
        intel_wait_for_vblank(dev, __cil_tmp54);
        }
      }
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1565
  __cil_tmp55 = intel_dp->output_reg;
#line 1565
  __cil_tmp56 = DP & 2147483647U;
#line 1565
  i915_write32___8(dev_priv, __cil_tmp55, __cil_tmp56);
#line 1566
  __cil_tmp57 = intel_dp->output_reg;
#line 1566
  __cil_tmp58 = (unsigned long )__cil_tmp57;
#line 1566
  __cil_tmp59 = dev_priv->regs;
#line 1566
  __cil_tmp60 = (void const volatile   *)__cil_tmp59;
#line 1566
  __cil_tmp61 = __cil_tmp60 + __cil_tmp58;
#line 1566
  readl(__cil_tmp61);
  }
#line 1567
  return;
}
}
#line 1579 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_check_link_status(struct intel_dp *intel_dp ) 
{ int ret ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  struct drm_crtc *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct drm_crtc *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  uint16_t __cil_tmp11 ;
  uint8_t (*__cil_tmp12)[4U] ;
  uint8_t *__cil_tmp13 ;

  {
  {
#line 1583
  __cil_tmp7 = (struct drm_crtc *)0;
#line 1583
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1583
  __cil_tmp9 = intel_dp->base.base.crtc;
#line 1583
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 1583
  if (__cil_tmp10 == __cil_tmp8) {
#line 1584
    return;
  } else {

  }
  }
  {
#line 1586
  tmp = intel_dp_get_link_status(intel_dp);
  }
#line 1586
  if (tmp) {
#line 1586
    tmp___0 = 0;
  } else {
#line 1586
    tmp___0 = 1;
  }
#line 1586
  if (tmp___0) {
    {
#line 1587
    intel_dp_link_down(intel_dp);
    }
#line 1588
    return;
  } else {

  }
  {
#line 1592
  __cil_tmp11 = (uint16_t )0;
#line 1592
  __cil_tmp12 = & intel_dp->dpcd;
#line 1592
  __cil_tmp13 = (uint8_t *)__cil_tmp12;
#line 1592
  ret = intel_dp_aux_native_read(intel_dp, __cil_tmp11, __cil_tmp13, 4);
  }
#line 1595
  if (ret != 4) {
    {
#line 1596
    intel_dp_link_down(intel_dp);
    }
#line 1597
    return;
  } else {

  }
  {
#line 1600
  tmp___1 = intel_channel_eq_ok(intel_dp);
  }
#line 1600
  if (tmp___1) {
#line 1600
    tmp___2 = 0;
  } else {
#line 1600
    tmp___2 = 1;
  }
#line 1600
  if (tmp___2) {
    {
#line 1601
    intel_dp_start_link_train(intel_dp);
#line 1602
    intel_dp_complete_link_train(intel_dp);
    }
  } else {

  }
#line 1604
  return;
}
}
#line 1607 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static enum drm_connector_status ironlake_dp_detect(struct intel_dp *intel_dp ) 
{ enum drm_connector_status status ;
  bool ret ;
  bool tmp ;
  struct drm_device *__cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  uint16_t __cil_tmp7 ;
  uint8_t (*__cil_tmp8)[4U] ;
  uint8_t *__cil_tmp9 ;
  uint8_t __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  uint8_t __cil_tmp12 ;
  int __cil_tmp13 ;
  uint8_t __cil_tmp14 ;
  int __cil_tmp15 ;
  uint8_t __cil_tmp16 ;
  int __cil_tmp17 ;
  uint8_t __cil_tmp18 ;
  int __cil_tmp19 ;

  {
  {
#line 1613
  tmp = is_edp(intel_dp);
  }
#line 1613
  if ((int )tmp) {
    {
#line 1614
    __cil_tmp5 = intel_dp->base.base.dev;
#line 1614
    status = intel_panel_detect(__cil_tmp5);
    }
    {
#line 1615
    __cil_tmp6 = (unsigned int )status;
#line 1615
    if (__cil_tmp6 == 3U) {
#line 1616
      status = (enum drm_connector_status )1;
    } else {

    }
    }
#line 1617
    return (status);
  } else {

  }
  {
#line 1620
  status = (enum drm_connector_status )2;
#line 1621
  __cil_tmp7 = (uint16_t )0;
#line 1621
  __cil_tmp8 = & intel_dp->dpcd;
#line 1621
  __cil_tmp9 = (uint8_t *)__cil_tmp8;
#line 1621
  ret = intel_dp_aux_native_read_retry(intel_dp, __cil_tmp7, __cil_tmp9, 4);
  }
#line 1624
  if ((int )ret) {
    {
#line 1624
    __cil_tmp10 = intel_dp->dpcd[0];
#line 1624
    __cil_tmp11 = (unsigned int )__cil_tmp10;
#line 1624
    if (__cil_tmp11 != 0U) {
#line 1625
      status = (enum drm_connector_status )1;
    } else {

    }
    }
  } else {

  }
  {
#line 1626
  __cil_tmp12 = intel_dp->dpcd[0];
#line 1626
  __cil_tmp13 = (int )__cil_tmp12;
#line 1626
  __cil_tmp14 = intel_dp->dpcd[1];
#line 1626
  __cil_tmp15 = (int )__cil_tmp14;
#line 1626
  __cil_tmp16 = intel_dp->dpcd[2];
#line 1626
  __cil_tmp17 = (int )__cil_tmp16;
#line 1626
  __cil_tmp18 = intel_dp->dpcd[3];
#line 1626
  __cil_tmp19 = (int )__cil_tmp18;
#line 1626
  drm_ut_debug_printk(4U, "drm", "ironlake_dp_detect", "DPCD: %hx%hx%hx%hx\n", __cil_tmp13,
                      __cil_tmp15, __cil_tmp17, __cil_tmp19);
  }
#line 1628
  return (status);
}
}
#line 1632 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static enum drm_connector_status g4x_dp_detect(struct intel_dp *intel_dp ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  enum drm_connector_status status ;
  uint32_t temp ;
  uint32_t bit ;
  int tmp ;
  void *__cil_tmp8 ;
  uint32_t __cil_tmp9 ;
  int __cil_tmp10 ;
  uint32_t __cil_tmp11 ;
  int __cil_tmp12 ;
  uint32_t __cil_tmp13 ;
  int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  uint16_t __cil_tmp16 ;
  uint8_t (*__cil_tmp17)[4U] ;
  uint8_t *__cil_tmp18 ;
  uint8_t __cil_tmp19 ;
  unsigned int __cil_tmp20 ;

  {
#line 1634
  dev = intel_dp->base.base.dev;
#line 1635
  __cil_tmp8 = dev->dev_private;
#line 1635
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
  {
#line 1640
  __cil_tmp9 = intel_dp->output_reg;
#line 1640
  __cil_tmp10 = (int )__cil_tmp9;
#line 1640
  if (__cil_tmp10 == 409856) {
#line 1640
    goto case_409856;
  } else {
    {
#line 1643
    __cil_tmp11 = intel_dp->output_reg;
#line 1643
    __cil_tmp12 = (int )__cil_tmp11;
#line 1643
    if (__cil_tmp12 == 410112) {
#line 1643
      goto case_410112;
    } else {
      {
#line 1646
      __cil_tmp13 = intel_dp->output_reg;
#line 1646
      __cil_tmp14 = (int )__cil_tmp13;
#line 1646
      if (__cil_tmp14 == 410368) {
#line 1646
        goto case_410368;
      } else {
#line 1649
        goto switch_default;
#line 1639
        if (0) {
          case_409856: 
#line 1641
          bit = 536870912U;
#line 1642
          goto ldv_38171;
          case_410112: 
#line 1644
          bit = 268435456U;
#line 1645
          goto ldv_38171;
          case_410368: 
#line 1647
          bit = 134217728U;
#line 1648
          goto ldv_38171;
          switch_default: ;
#line 1650
          return ((enum drm_connector_status )3);
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_38171: 
  {
#line 1653
  temp = i915_read32___10(dev_priv, 397588U);
  }
  {
#line 1655
  __cil_tmp15 = temp & bit;
#line 1655
  if (__cil_tmp15 == 0U) {
#line 1656
    return ((enum drm_connector_status )2);
  } else {

  }
  }
  {
#line 1658
  status = (enum drm_connector_status )2;
#line 1659
  __cil_tmp16 = (uint16_t )0;
#line 1659
  __cil_tmp17 = & intel_dp->dpcd;
#line 1659
  __cil_tmp18 = (uint8_t *)__cil_tmp17;
#line 1659
  tmp = intel_dp_aux_native_read(intel_dp, __cil_tmp16, __cil_tmp18, 4);
  }
#line 1659
  if (tmp == 4) {
    {
#line 1662
    __cil_tmp19 = intel_dp->dpcd[0];
#line 1662
    __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 1662
    if (__cil_tmp20 != 0U) {
#line 1663
      status = (enum drm_connector_status )1;
    } else {

    }
    }
  } else {

  }
#line 1666
  return (status);
}
}
#line 1676 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static enum drm_connector_status intel_dp_detect(struct drm_connector *connector ,
                                                 bool force ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_device *dev ;
  enum drm_connector_status status ;
  struct edid *edid ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  unsigned char *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  struct i2c_adapter *__cil_tmp31 ;
  struct edid *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  void const   *__cil_tmp35 ;

  {
  {
#line 1678
  tmp = intel_attached_dp(connector);
#line 1678
  intel_dp = tmp;
#line 1679
  dev = intel_dp->base.base.dev;
#line 1681
  edid = (struct edid *)0;
#line 1683
  intel_dp->has_audio = (bool )0;
  }
  {
#line 1685
  __cil_tmp8 = dev->dev_private;
#line 1685
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 1685
  __cil_tmp10 = __cil_tmp9->info;
#line 1685
  __cil_tmp11 = __cil_tmp10->gen;
#line 1685
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 1685
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 1685
  if (__cil_tmp13 == 5U) {
    {
#line 1686
    status = ironlake_dp_detect(intel_dp);
    }
  } else {
    {
#line 1685
    __cil_tmp14 = dev->dev_private;
#line 1685
    __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 1685
    __cil_tmp16 = __cil_tmp15->info;
#line 1685
    __cil_tmp17 = __cil_tmp16->gen;
#line 1685
    __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 1685
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 1685
    if (__cil_tmp19 == 6U) {
      {
#line 1686
      status = ironlake_dp_detect(intel_dp);
      }
    } else {
      {
#line 1685
      __cil_tmp20 = dev->dev_private;
#line 1685
      __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 1685
      __cil_tmp22 = __cil_tmp21->info;
#line 1685
      __cil_tmp23 = (unsigned char *)__cil_tmp22;
#line 1685
      __cil_tmp24 = __cil_tmp23 + 2UL;
#line 1685
      __cil_tmp25 = *__cil_tmp24;
#line 1685
      __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 1685
      if (__cil_tmp26 != 0U) {
        {
#line 1686
        status = ironlake_dp_detect(intel_dp);
        }
      } else {
        {
#line 1688
        status = g4x_dp_detect(intel_dp);
        }
      }
      }
    }
    }
  }
  }
  {
#line 1689
  __cil_tmp27 = (unsigned int )status;
#line 1689
  if (__cil_tmp27 != 1U) {
#line 1690
    return (status);
  } else {

  }
  }
  {
#line 1692
  __cil_tmp28 = intel_dp->force_audio;
#line 1692
  if (__cil_tmp28 != 0) {
#line 1693
    __cil_tmp29 = intel_dp->force_audio;
#line 1693
    __cil_tmp30 = __cil_tmp29 > 0;
#line 1693
    intel_dp->has_audio = (bool )__cil_tmp30;
  } else {
    {
#line 1695
    __cil_tmp31 = & intel_dp->adapter;
#line 1695
    edid = drm_get_edid(connector, __cil_tmp31);
    }
    {
#line 1696
    __cil_tmp32 = (struct edid *)0;
#line 1696
    __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 1696
    __cil_tmp34 = (unsigned long )edid;
#line 1696
    if (__cil_tmp34 != __cil_tmp33) {
      {
#line 1697
      intel_dp->has_audio = drm_detect_monitor_audio(edid);
#line 1698
      connector->display_info.raw_edid = (char *)0;
#line 1699
      __cil_tmp35 = (void const   *)edid;
#line 1699
      kfree(__cil_tmp35);
      }
    } else {

    }
    }
  }
  }
#line 1703
  return ((enum drm_connector_status )1);
}
}
#line 1706 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_get_modes(struct drm_connector *connector ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  int ret ;
  struct drm_display_mode *newmode ;
  struct list_head  const  *__mptr ;
  struct list_head  const  *__mptr___0 ;
  bool tmp___0 ;
  struct drm_display_mode *mode ;
  bool tmp___1 ;
  void *__cil_tmp13 ;
  struct i2c_adapter *__cil_tmp14 ;
  struct drm_display_mode *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct drm_display_mode *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  struct list_head *__cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  struct drm_display_mode  const  *__cil_tmp22 ;
  struct list_head *__cil_tmp23 ;
  struct list_head *__cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct list_head *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  struct drm_display_mode *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  struct drm_display_mode *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  struct drm_display_mode *__cil_tmp32 ;
  struct drm_display_mode  const  *__cil_tmp33 ;

  {
  {
#line 1708
  tmp = intel_attached_dp(connector);
#line 1708
  intel_dp = tmp;
#line 1709
  dev = intel_dp->base.base.dev;
#line 1710
  __cil_tmp13 = dev->dev_private;
#line 1710
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 1716
  __cil_tmp14 = & intel_dp->adapter;
#line 1716
  ret = intel_ddc_get_modes(connector, __cil_tmp14);
  }
#line 1717
  if (ret != 0) {
    {
#line 1718
    tmp___0 = is_edp(intel_dp);
    }
#line 1718
    if ((int )tmp___0) {
      {
#line 1718
      __cil_tmp15 = (struct drm_display_mode *)0;
#line 1718
      __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 1718
      __cil_tmp17 = dev_priv->panel_fixed_mode;
#line 1718
      __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 1718
      if (__cil_tmp18 == __cil_tmp16) {
#line 1720
        __cil_tmp19 = connector->probed_modes.next;
#line 1720
        __mptr = (struct list_head  const  *)__cil_tmp19;
#line 1720
        newmode = (struct drm_display_mode *)__mptr;
#line 1720
        goto ldv_38197;
        ldv_38196: ;
        {
#line 1722
        __cil_tmp20 = newmode->type;
#line 1722
        __cil_tmp21 = __cil_tmp20 & 8;
#line 1722
        if (__cil_tmp21 != 0) {
          {
#line 1723
          __cil_tmp22 = (struct drm_display_mode  const  *)newmode;
#line 1723
          dev_priv->panel_fixed_mode = drm_mode_duplicate(dev, __cil_tmp22);
          }
#line 1725
          goto ldv_38195;
        } else {

        }
        }
#line 1720
        __cil_tmp23 = newmode->head.next;
#line 1720
        __mptr___0 = (struct list_head  const  *)__cil_tmp23;
#line 1720
        newmode = (struct drm_display_mode *)__mptr___0;
        ldv_38197: ;
        {
#line 1720
        __cil_tmp24 = & connector->probed_modes;
#line 1720
        __cil_tmp25 = (unsigned long )__cil_tmp24;
#line 1720
        __cil_tmp26 = & newmode->head;
#line 1720
        __cil_tmp27 = (unsigned long )__cil_tmp26;
#line 1720
        if (__cil_tmp27 != __cil_tmp25) {
#line 1721
          goto ldv_38196;
        } else {
#line 1723
          goto ldv_38195;
        }
        }
        ldv_38195: ;
      } else {

      }
      }
    } else {

    }
#line 1730
    return (ret);
  } else {

  }
  {
#line 1734
  tmp___1 = is_edp(intel_dp);
  }
#line 1734
  if ((int )tmp___1) {
    {
#line 1735
    __cil_tmp28 = (struct drm_display_mode *)0;
#line 1735
    __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 1735
    __cil_tmp30 = dev_priv->panel_fixed_mode;
#line 1735
    __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 1735
    if (__cil_tmp31 != __cil_tmp29) {
      {
#line 1737
      __cil_tmp32 = dev_priv->panel_fixed_mode;
#line 1737
      __cil_tmp33 = (struct drm_display_mode  const  *)__cil_tmp32;
#line 1737
      mode = drm_mode_duplicate(dev, __cil_tmp33);
#line 1738
      drm_mode_probed_add(connector, mode);
      }
#line 1739
      return (1);
    } else {

    }
    }
  } else {

  }
#line 1742
  return (0);
}
}
#line 1746 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static bool intel_dp_detect_audio(struct drm_connector *connector ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct edid *edid ;
  bool has_audio ;
  struct i2c_adapter *__cil_tmp6 ;
  struct edid *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  void const   *__cil_tmp10 ;

  {
  {
#line 1748
  tmp = intel_attached_dp(connector);
#line 1748
  intel_dp = tmp;
#line 1750
  has_audio = (bool )0;
#line 1752
  __cil_tmp6 = & intel_dp->adapter;
#line 1752
  edid = drm_get_edid(connector, __cil_tmp6);
  }
  {
#line 1753
  __cil_tmp7 = (struct edid *)0;
#line 1753
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1753
  __cil_tmp9 = (unsigned long )edid;
#line 1753
  if (__cil_tmp9 != __cil_tmp8) {
    {
#line 1754
    has_audio = drm_detect_monitor_audio(edid);
#line 1756
    connector->display_info.raw_edid = (char *)0;
#line 1757
    __cil_tmp10 = (void const   *)edid;
#line 1757
    kfree(__cil_tmp10);
    }
  } else {

  }
  }
#line 1760
  return (has_audio);
}
}
#line 1764 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static int intel_dp_set_property(struct drm_connector *connector , struct drm_property *property ,
                                 uint64_t val ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  int ret ;
  int i ;
  bool has_audio ;
  struct drm_crtc *crtc ;
  struct drm_device *__cil_tmp11 ;
  void *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_property *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  bool __cil_tmp19 ;
  int __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_property *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  uint32_t __cil_tmp24 ;
  int __cil_tmp25 ;
  uint64_t __cil_tmp26 ;
  struct drm_crtc *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  struct drm_crtc *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  struct drm_display_mode *__cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  struct drm_framebuffer *__cil_tmp34 ;

  {
  {
#line 1768
  __cil_tmp11 = connector->dev;
#line 1768
  __cil_tmp12 = __cil_tmp11->dev_private;
#line 1768
  dev_priv = (struct drm_i915_private *)__cil_tmp12;
#line 1769
  tmp = intel_attached_dp(connector);
#line 1769
  intel_dp = tmp;
#line 1772
  ret = drm_connector_property_set_value(connector, property, val);
  }
#line 1773
  if (ret != 0) {
#line 1774
    return (ret);
  } else {

  }
  {
#line 1776
  __cil_tmp13 = (unsigned long )property;
#line 1776
  __cil_tmp14 = dev_priv->force_audio_property;
#line 1776
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 1776
  if (__cil_tmp15 == __cil_tmp13) {
#line 1777
    i = (int )val;
    {
#line 1780
    __cil_tmp16 = intel_dp->force_audio;
#line 1780
    if (__cil_tmp16 == i) {
#line 1781
      return (0);
    } else {

    }
    }
#line 1783
    intel_dp->force_audio = i;
#line 1785
    if (i == 0) {
      {
#line 1786
      has_audio = intel_dp_detect_audio(connector);
      }
    } else {
#line 1788
      __cil_tmp17 = i > 0;
#line 1788
      has_audio = (bool )__cil_tmp17;
    }
    {
#line 1790
    __cil_tmp18 = (int )has_audio;
#line 1790
    __cil_tmp19 = intel_dp->has_audio;
#line 1790
    __cil_tmp20 = (int )__cil_tmp19;
#line 1790
    if (__cil_tmp20 == __cil_tmp18) {
#line 1791
      return (0);
    } else {

    }
    }
#line 1793
    intel_dp->has_audio = has_audio;
#line 1794
    goto done;
  } else {

  }
  }
  {
#line 1797
  __cil_tmp21 = (unsigned long )property;
#line 1797
  __cil_tmp22 = dev_priv->broadcast_rgb_property;
#line 1797
  __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 1797
  if (__cil_tmp23 == __cil_tmp21) {
    {
#line 1798
    __cil_tmp24 = intel_dp->color_range;
#line 1798
    __cil_tmp25 = __cil_tmp24 != 0U;
#line 1798
    __cil_tmp26 = (uint64_t )__cil_tmp25;
#line 1798
    if (__cil_tmp26 == val) {
#line 1799
      return (0);
    } else {

    }
    }
#line 1801
    if (val != 0ULL) {
#line 1801
      intel_dp->color_range = 256U;
    } else {
#line 1801
      intel_dp->color_range = 0U;
    }
#line 1802
    goto done;
  } else {

  }
  }
#line 1805
  return (-22);
  done: ;
  {
#line 1808
  __cil_tmp27 = (struct drm_crtc *)0;
#line 1808
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 1808
  __cil_tmp29 = intel_dp->base.base.crtc;
#line 1808
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 1808
  if (__cil_tmp30 != __cil_tmp28) {
    {
#line 1809
    crtc = intel_dp->base.base.crtc;
#line 1810
    __cil_tmp31 = & crtc->mode;
#line 1810
    __cil_tmp32 = crtc->x;
#line 1810
    __cil_tmp33 = crtc->y;
#line 1810
    __cil_tmp34 = crtc->fb;
#line 1810
    drm_crtc_helper_set_mode(crtc, __cil_tmp31, __cil_tmp32, __cil_tmp33, __cil_tmp34);
    }
  } else {

  }
  }
#line 1815
  return (0);
}
}
#line 1819 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_destroy(struct drm_connector *connector ) 
{ void const   *__cil_tmp2 ;

  {
  {
#line 1821
  drm_sysfs_connector_remove(connector);
#line 1822
  drm_connector_cleanup(connector);
#line 1823
  __cil_tmp2 = (void const   *)connector;
#line 1823
  kfree(__cil_tmp2);
  }
#line 1824
  return;
}
}
#line 1826 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_encoder_destroy(struct drm_encoder *encoder ) 
{ struct intel_dp *intel_dp ;
  struct intel_dp *tmp ;
  struct i2c_adapter *__cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 1828
  tmp = enc_to_intel_dp(encoder);
#line 1828
  intel_dp = tmp;
#line 1830
  __cil_tmp4 = & intel_dp->adapter;
#line 1830
  i2c_del_adapter(__cil_tmp4);
#line 1831
  drm_encoder_cleanup(encoder);
#line 1832
  __cil_tmp5 = (void const   *)intel_dp;
#line 1832
  kfree(__cil_tmp5);
  }
#line 1833
  return;
}
}
#line 1835 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static struct drm_encoder_helper_funcs  const  intel_dp_helper_funcs  = 
#line 1835
     {& intel_dp_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_dp_mode_fixup, & intel_dp_prepare, & intel_dp_commit, & intel_dp_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 1843 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static struct drm_connector_funcs  const  intel_dp_connector_funcs  = 
#line 1843
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    (void (*)(struct drm_connector * ))0, & intel_dp_detect, & drm_helper_probe_single_connector_modes,
    & intel_dp_set_property, & intel_dp_destroy, (void (*)(struct drm_connector * ))0};
#line 1851 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static struct drm_connector_helper_funcs  const  intel_dp_connector_helper_funcs  =    {& intel_dp_get_modes,
    & intel_dp_mode_valid, & intel_best_encoder};
#line 1857 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static struct drm_encoder_funcs  const  intel_dp_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_dp_encoder_destroy};
#line 1862 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_hot_plug(struct intel_encoder *intel_encoder ) 
{ struct intel_dp *intel_dp ;
  struct intel_encoder  const  *__mptr ;

  {
  {
#line 1864
  __mptr = (struct intel_encoder  const  *)intel_encoder;
#line 1864
  intel_dp = (struct intel_dp *)__mptr;
#line 1866
  intel_dp_check_link_status(intel_dp);
  }
#line 1867
  return;
}
}
#line 1871 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
int intel_trans_dp_port_sel(struct drm_crtc *crtc ) 
{ struct drm_device *dev ;
  struct drm_mode_config *mode_config ;
  struct drm_encoder *encoder ;
  struct list_head  const  *__mptr ;
  struct intel_dp *intel_dp ;
  struct list_head  const  *__mptr___0 ;
  struct list_head *__cil_tmp8 ;
  struct drm_encoder *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct drm_crtc *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  int __cil_tmp13 ;
  uint32_t __cil_tmp14 ;
  struct list_head *__cil_tmp15 ;
  struct drm_encoder *__cil_tmp16 ;
  struct list_head *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  struct list_head *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;

  {
#line 1873
  dev = crtc->dev;
#line 1874
  mode_config = & dev->mode_config;
#line 1877
  __cil_tmp8 = mode_config->encoder_list.next;
#line 1877
  __mptr = (struct list_head  const  *)__cil_tmp8;
#line 1877
  __cil_tmp9 = (struct drm_encoder *)__mptr;
#line 1877
  encoder = __cil_tmp9 + 1152921504606846968UL;
#line 1877
  goto ldv_38247;
  ldv_38246: ;
  {
#line 1880
  __cil_tmp10 = (unsigned long )crtc;
#line 1880
  __cil_tmp11 = encoder->crtc;
#line 1880
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 1880
  if (__cil_tmp12 != __cil_tmp10) {
#line 1881
    goto ldv_38245;
  } else {

  }
  }
  {
#line 1883
  intel_dp = enc_to_intel_dp(encoder);
  }
  {
#line 1884
  __cil_tmp13 = intel_dp->base.type;
#line 1884
  if (__cil_tmp13 == 7) {
    {
#line 1885
    __cil_tmp14 = intel_dp->output_reg;
#line 1885
    return ((int )__cil_tmp14);
    }
  } else {

  }
  }
  ldv_38245: 
#line 1877
  __cil_tmp15 = encoder->head.next;
#line 1877
  __mptr___0 = (struct list_head  const  *)__cil_tmp15;
#line 1877
  __cil_tmp16 = (struct drm_encoder *)__mptr___0;
#line 1877
  encoder = __cil_tmp16 + 1152921504606846968UL;
  ldv_38247: ;
  {
#line 1877
  __cil_tmp17 = & mode_config->encoder_list;
#line 1877
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 1877
  __cil_tmp19 = & encoder->head;
#line 1877
  __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 1877
  if (__cil_tmp20 != __cil_tmp18) {
#line 1878
    goto ldv_38246;
  } else {
#line 1880
    goto ldv_38248;
  }
  }
  ldv_38248: ;
#line 1888
  return (-1);
}
}
#line 1892 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
bool intel_dpd_is_edp(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct child_device_config *p_child ;
  int i ;
  void *__cil_tmp5 ;
  int __cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct child_device_config *__cil_tmp8 ;
  u8 __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  u16 __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  int __cil_tmp13 ;

  {
#line 1894
  __cil_tmp5 = dev->dev_private;
#line 1894
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
  {
#line 1898
  __cil_tmp6 = dev_priv->child_dev_num;
#line 1898
  if (__cil_tmp6 == 0) {
#line 1899
    return ((bool )0);
  } else {

  }
  }
#line 1901
  i = 0;
#line 1901
  goto ldv_38256;
  ldv_38255: 
#line 1902
  __cil_tmp7 = (unsigned long )i;
#line 1902
  __cil_tmp8 = dev_priv->child_dev;
#line 1902
  p_child = __cil_tmp8 + __cil_tmp7;
  {
#line 1904
  __cil_tmp9 = p_child->dvo_port;
#line 1904
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 1904
  if (__cil_tmp10 == 9U) {
    {
#line 1904
    __cil_tmp11 = p_child->device_type;
#line 1904
    __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1904
    if (__cil_tmp12 == 30918U) {
#line 1906
      return ((bool )1);
    } else {

    }
    }
  } else {

  }
  }
#line 1901
  i = i + 1;
  ldv_38256: ;
  {
#line 1901
  __cil_tmp13 = dev_priv->child_dev_num;
#line 1901
  if (__cil_tmp13 > i) {
#line 1902
    goto ldv_38255;
  } else {
#line 1904
    goto ldv_38257;
  }
  }
  ldv_38257: ;
#line 1908
  return ((bool )0);
}
}
#line 1912 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
static void intel_dp_add_properties(struct intel_dp *intel_dp , struct drm_connector *connector ) 
{ 

  {
  {
#line 1914
  intel_attach_force_audio_property(connector);
#line 1915
  intel_attach_broadcast_rgb_property(connector);
  }
#line 1916
  return;
}
}
#line 1919 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dp.c.p"
void intel_dp_init(struct drm_device *dev , int output_reg ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_connector *connector ;
  struct intel_dp *intel_dp ;
  struct intel_encoder *intel_encoder ;
  struct intel_connector *intel_connector ;
  char const   *name ;
  int type ;
  void *tmp ;
  void *tmp___0 ;
  bool tmp___1 ;
  bool tmp___2 ;
  bool tmp___3 ;
  int ret ;
  u32 pp_on ;
  u32 pp_div ;
  bool tmp___4 ;
  bool tmp___5 ;
  u32 temp ;
  u32 tmp___6 ;
  void *__cil_tmp22 ;
  struct intel_dp *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct intel_connector *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  void const   *__cil_tmp29 ;
  void *__cil_tmp30 ;
  struct drm_i915_private *__cil_tmp31 ;
  struct intel_device_info  const  *__cil_tmp32 ;
  u8 __cil_tmp33 ;
  unsigned char __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  void *__cil_tmp36 ;
  struct drm_i915_private *__cil_tmp37 ;
  struct intel_device_info  const  *__cil_tmp38 ;
  u8 __cil_tmp39 ;
  unsigned char __cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  void *__cil_tmp42 ;
  struct drm_i915_private *__cil_tmp43 ;
  struct intel_device_info  const  *__cil_tmp44 ;
  unsigned char *__cil_tmp45 ;
  unsigned char *__cil_tmp46 ;
  unsigned char __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  struct drm_encoder *__cil_tmp49 ;
  struct drm_encoder *__cil_tmp50 ;
  u32 __cil_tmp51 ;
  u32 __cil_tmp52 ;
  u32 __cil_tmp53 ;
  unsigned int __cil_tmp54 ;
  unsigned int __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  int __cil_tmp58 ;
  uint16_t __cil_tmp59 ;
  uint8_t (*__cil_tmp60)[4U] ;
  uint8_t *__cil_tmp61 ;
  uint8_t __cil_tmp62 ;
  unsigned int __cil_tmp63 ;
  uint8_t __cil_tmp64 ;
  int __cil_tmp65 ;
  int __cil_tmp66 ;
  int __cil_tmp67 ;
  struct drm_encoder *__cil_tmp68 ;
  struct drm_connector *__cil_tmp69 ;
  struct drm_display_mode *__cil_tmp70 ;
  unsigned long __cil_tmp71 ;
  struct drm_display_mode *__cil_tmp72 ;
  unsigned long __cil_tmp73 ;
  struct drm_display_mode *__cil_tmp74 ;
  struct drm_display_mode  const  *__cil_tmp75 ;
  struct drm_display_mode *__cil_tmp76 ;
  unsigned long __cil_tmp77 ;
  struct drm_display_mode *__cil_tmp78 ;
  unsigned long __cil_tmp79 ;
  struct drm_display_mode *__cil_tmp80 ;
  struct drm_display_mode *__cil_tmp81 ;
  int __cil_tmp82 ;
  void *__cil_tmp83 ;
  struct drm_i915_private *__cil_tmp84 ;
  struct intel_device_info  const  *__cil_tmp85 ;
  unsigned char *__cil_tmp86 ;
  unsigned char *__cil_tmp87 ;
  unsigned char __cil_tmp88 ;
  unsigned int __cil_tmp89 ;
  int __cil_tmp90 ;
  unsigned int __cil_tmp91 ;
  unsigned int __cil_tmp92 ;

  {
  {
#line 1921
  __cil_tmp22 = dev->dev_private;
#line 1921
  dev_priv = (struct drm_i915_private *)__cil_tmp22;
#line 1926
  name = (char const   *)0;
#line 1929
  tmp = kzalloc(1808UL, 208U);
#line 1929
  intel_dp = (struct intel_dp *)tmp;
  }
  {
#line 1930
  __cil_tmp23 = (struct intel_dp *)0;
#line 1930
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 1930
  __cil_tmp25 = (unsigned long )intel_dp;
#line 1930
  if (__cil_tmp25 == __cil_tmp24) {
#line 1931
    return;
  } else {

  }
  }
  {
#line 1933
  intel_dp->output_reg = (uint32_t )output_reg;
#line 1935
  tmp___0 = kzalloc(1576UL, 208U);
#line 1935
  intel_connector = (struct intel_connector *)tmp___0;
  }
  {
#line 1936
  __cil_tmp26 = (struct intel_connector *)0;
#line 1936
  __cil_tmp27 = (unsigned long )__cil_tmp26;
#line 1936
  __cil_tmp28 = (unsigned long )intel_connector;
#line 1936
  if (__cil_tmp28 == __cil_tmp27) {
    {
#line 1937
    __cil_tmp29 = (void const   *)intel_dp;
#line 1937
    kfree(__cil_tmp29);
    }
#line 1938
    return;
  } else {

  }
  }
#line 1940
  intel_encoder = & intel_dp->base;
  {
#line 1942
  __cil_tmp30 = dev->dev_private;
#line 1942
  __cil_tmp31 = (struct drm_i915_private *)__cil_tmp30;
#line 1942
  __cil_tmp32 = __cil_tmp31->info;
#line 1942
  __cil_tmp33 = __cil_tmp32->gen;
#line 1942
  __cil_tmp34 = (unsigned char )__cil_tmp33;
#line 1942
  __cil_tmp35 = (unsigned int )__cil_tmp34;
#line 1942
  if (__cil_tmp35 == 5U) {
#line 1942
    goto _L;
  } else {
    {
#line 1942
    __cil_tmp36 = dev->dev_private;
#line 1942
    __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
#line 1942
    __cil_tmp38 = __cil_tmp37->info;
#line 1942
    __cil_tmp39 = __cil_tmp38->gen;
#line 1942
    __cil_tmp40 = (unsigned char )__cil_tmp39;
#line 1942
    __cil_tmp41 = (unsigned int )__cil_tmp40;
#line 1942
    if (__cil_tmp41 == 6U) {
#line 1942
      goto _L;
    } else {
      {
#line 1942
      __cil_tmp42 = dev->dev_private;
#line 1942
      __cil_tmp43 = (struct drm_i915_private *)__cil_tmp42;
#line 1942
      __cil_tmp44 = __cil_tmp43->info;
#line 1942
      __cil_tmp45 = (unsigned char *)__cil_tmp44;
#line 1942
      __cil_tmp46 = __cil_tmp45 + 2UL;
#line 1942
      __cil_tmp47 = *__cil_tmp46;
#line 1942
      __cil_tmp48 = (unsigned int )__cil_tmp47;
#line 1942
      if (__cil_tmp48 != 0U) {
        _L: 
#line 1942
        if (output_reg == 934656) {
          {
#line 1943
          tmp___1 = intel_dpd_is_edp(dev);
          }
#line 1943
          if ((int )tmp___1) {
#line 1944
            intel_dp->is_pch_edp = (bool )1;
          } else {

          }
        } else {

        }
      } else {

      }
      }
    }
    }
  }
  }
#line 1946
  if (output_reg == 409600) {
#line 1947
    type = 14;
#line 1948
    intel_encoder->type = 8;
  } else {
    {
#line 1946
    tmp___2 = is_pch_edp(intel_dp);
    }
#line 1946
    if ((int )tmp___2) {
#line 1947
      type = 14;
#line 1948
      intel_encoder->type = 8;
    } else {
#line 1950
      type = 10;
#line 1951
      intel_encoder->type = 7;
    }
  }
  {
#line 1954
  connector = & intel_connector->base;
#line 1955
  drm_connector_init(dev, connector, & intel_dp_connector_funcs, type);
#line 1956
  drm_connector_helper_add(connector, & intel_dp_connector_helper_funcs);
#line 1958
  connector->polled = (uint8_t )1U;
  }
#line 1960
  if (output_reg == 409856) {
#line 1961
    intel_encoder->clone_mask = 2048;
  } else
#line 1960
  if (output_reg == 934144) {
#line 1961
    intel_encoder->clone_mask = 2048;
  } else
#line 1962
  if (output_reg == 410112) {
#line 1963
    intel_encoder->clone_mask = 4096;
  } else
#line 1962
  if (output_reg == 934400) {
#line 1963
    intel_encoder->clone_mask = 4096;
  } else
#line 1964
  if (output_reg == 410368) {
#line 1965
    intel_encoder->clone_mask = 8192;
  } else
#line 1964
  if (output_reg == 934656) {
#line 1965
    intel_encoder->clone_mask = 8192;
  } else {

  }
  {
#line 1967
  tmp___3 = is_edp(intel_dp);
  }
#line 1967
  if ((int )tmp___3) {
#line 1968
    intel_encoder->clone_mask = 131072;
  } else {

  }
  {
#line 1970
  intel_encoder->crtc_mask = 3;
#line 1971
  connector->interlace_allowed = (bool )1;
#line 1972
  connector->doublescan_allowed = (bool )0;
#line 1974
  __cil_tmp49 = & intel_encoder->base;
#line 1974
  drm_encoder_init(dev, __cil_tmp49, & intel_dp_enc_funcs, 2);
#line 1976
  __cil_tmp50 = & intel_encoder->base;
#line 1976
  drm_encoder_helper_add(__cil_tmp50, & intel_dp_helper_funcs);
#line 1978
  intel_connector_attach_encoder(intel_connector, intel_encoder);
#line 1979
  drm_sysfs_connector_add(connector);
  }
#line 1983
  if (output_reg == 409600) {
#line 1983
    goto case_409600;
  } else
#line 1986
  if (output_reg == 409856) {
#line 1986
    goto case_409856;
  } else
#line 1987
  if (output_reg == 934144) {
#line 1987
    goto case_934144;
  } else
#line 1992
  if (output_reg == 410112) {
#line 1992
    goto case_410112;
  } else
#line 1993
  if (output_reg == 934400) {
#line 1993
    goto case_934400;
  } else
#line 1998
  if (output_reg == 410368) {
#line 1998
    goto case_410368;
  } else
#line 1999
  if (output_reg == 934656) {
#line 1999
    goto case_934656;
  } else
#line 1982
  if (0) {
    case_409600: 
#line 1984
    name = "DPDDC-A";
#line 1985
    goto ldv_38274;
    case_409856: ;
    case_934144: 
#line 1988
    __cil_tmp51 = dev_priv->hotplug_supported_mask;
#line 1988
    dev_priv->hotplug_supported_mask = __cil_tmp51 | 536870912U;
#line 1990
    name = "DPDDC-B";
#line 1991
    goto ldv_38274;
    case_410112: ;
    case_934400: 
#line 1994
    __cil_tmp52 = dev_priv->hotplug_supported_mask;
#line 1994
    dev_priv->hotplug_supported_mask = __cil_tmp52 | 268435456U;
#line 1996
    name = "DPDDC-C";
#line 1997
    goto ldv_38274;
    case_410368: ;
    case_934656: 
#line 2000
    __cil_tmp53 = dev_priv->hotplug_supported_mask;
#line 2000
    dev_priv->hotplug_supported_mask = __cil_tmp53 | 134217728U;
#line 2002
    name = "DPDDC-D";
#line 2003
    goto ldv_38274;
  } else {

  }
  ldv_38274: 
  {
#line 2006
  intel_dp_i2c_init(intel_dp, intel_connector, name);
#line 2009
  tmp___4 = is_edp(intel_dp);
  }
#line 2009
  if ((int )tmp___4) {
    {
#line 2013
    pp_on = i915_read32___10(dev_priv, 815624U);
#line 2014
    pp_div = i915_read32___10(dev_priv, 815632U);
#line 2017
    __cil_tmp54 = pp_on & 536805376U;
#line 2017
    __cil_tmp55 = __cil_tmp54 >> 16;
#line 2017
    dev_priv->panel_t3 = (int )__cil_tmp55;
#line 2018
    __cil_tmp56 = dev_priv->panel_t3;
#line 2018
    dev_priv->panel_t3 = __cil_tmp56 / 10;
#line 2019
    __cil_tmp57 = (int )pp_div;
#line 2019
    dev_priv->panel_t12 = __cil_tmp57 & 15;
#line 2020
    __cil_tmp58 = dev_priv->panel_t12;
#line 2020
    dev_priv->panel_t12 = __cil_tmp58 * 100;
#line 2022
    ironlake_edp_panel_vdd_on(intel_dp);
#line 2023
    __cil_tmp59 = (uint16_t )0;
#line 2023
    __cil_tmp60 = & intel_dp->dpcd;
#line 2023
    __cil_tmp61 = (uint8_t *)__cil_tmp60;
#line 2023
    ret = intel_dp_aux_native_read(intel_dp, __cil_tmp59, __cil_tmp61, 4);
#line 2026
    ironlake_edp_panel_vdd_off(intel_dp);
    }
#line 2027
    if (ret == 4) {
      {
#line 2028
      __cil_tmp62 = intel_dp->dpcd[0];
#line 2028
      __cil_tmp63 = (unsigned int )__cil_tmp62;
#line 2028
      if (__cil_tmp63 > 16U) {
#line 2029
        __cil_tmp64 = intel_dp->dpcd[3];
#line 2029
        __cil_tmp65 = (int )__cil_tmp64;
#line 2029
        __cil_tmp66 = __cil_tmp65 & 64;
#line 2029
        __cil_tmp67 = __cil_tmp66 != 0;
#line 2029
        dev_priv->no_aux_handshake = (bool )__cil_tmp67;
      } else {
        {
#line 2034
        printk("<6>[drm] failed to retrieve link info, disabling eDP\n");
#line 2035
        __cil_tmp68 = & intel_dp->base.base;
#line 2035
        intel_dp_encoder_destroy(__cil_tmp68);
#line 2036
        __cil_tmp69 = & intel_connector->base;
#line 2036
        intel_dp_destroy(__cil_tmp69);
        }
#line 2037
        return;
      }
      }
    } else {

    }
  } else {

  }
  {
#line 2041
  intel_encoder->hot_plug = & intel_dp_hot_plug;
#line 2043
  tmp___5 = is_edp(intel_dp);
  }
#line 2043
  if ((int )tmp___5) {
    {
#line 2045
    __cil_tmp70 = (struct drm_display_mode *)0;
#line 2045
    __cil_tmp71 = (unsigned long )__cil_tmp70;
#line 2045
    __cil_tmp72 = dev_priv->lfp_lvds_vbt_mode;
#line 2045
    __cil_tmp73 = (unsigned long )__cil_tmp72;
#line 2045
    if (__cil_tmp73 != __cil_tmp71) {
      {
#line 2046
      __cil_tmp74 = dev_priv->lfp_lvds_vbt_mode;
#line 2046
      __cil_tmp75 = (struct drm_display_mode  const  *)__cil_tmp74;
#line 2046
      dev_priv->panel_fixed_mode = drm_mode_duplicate(dev, __cil_tmp75);
      }
      {
#line 2048
      __cil_tmp76 = (struct drm_display_mode *)0;
#line 2048
      __cil_tmp77 = (unsigned long )__cil_tmp76;
#line 2048
      __cil_tmp78 = dev_priv->panel_fixed_mode;
#line 2048
      __cil_tmp79 = (unsigned long )__cil_tmp78;
#line 2048
      if (__cil_tmp79 != __cil_tmp77) {
#line 2049
        __cil_tmp80 = dev_priv->panel_fixed_mode;
#line 2049
        __cil_tmp81 = dev_priv->panel_fixed_mode;
#line 2049
        __cil_tmp82 = __cil_tmp81->type;
#line 2049
        __cil_tmp80->type = __cil_tmp82 | 8;
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  {
#line 2055
  intel_dp_add_properties(intel_dp, connector);
  }
  {
#line 2061
  __cil_tmp83 = dev->dev_private;
#line 2061
  __cil_tmp84 = (struct drm_i915_private *)__cil_tmp83;
#line 2061
  __cil_tmp85 = __cil_tmp84->info;
#line 2061
  __cil_tmp86 = (unsigned char *)__cil_tmp85;
#line 2061
  __cil_tmp87 = __cil_tmp86 + 1UL;
#line 2061
  __cil_tmp88 = *__cil_tmp87;
#line 2061
  __cil_tmp89 = (unsigned int )__cil_tmp88;
#line 2061
  if (__cil_tmp89 != 0U) {
    {
#line 2061
    __cil_tmp90 = dev->pci_device;
#line 2061
    if (__cil_tmp90 != 10818) {
      {
#line 2062
      tmp___6 = i915_read32___10(dev_priv, 85352U);
#line 2062
      temp = tmp___6;
#line 2063
      __cil_tmp91 = temp & 4294967280U;
#line 2063
      __cil_tmp92 = __cil_tmp91 | 13U;
#line 2063
      i915_write32___8(dev_priv, 85352U, __cil_tmp92);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 2065
  return;
}
}
#line 788 "include/drm/drm_crtc.h"
extern bool drm_detect_hdmi_monitor(struct edid * ) ;
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___11(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36349: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36349;
      } else {
#line 390
        goto ldv_36350;
      }
      }
      ldv_36350: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___11(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___11(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___9(struct drm_i915_private *dev_priv , u32 reg ,
                                      u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___11(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 244 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
void intel_dip_infoframe_csum(struct dip_infoframe *avi_if ) ;
#line 58 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder ) 
{ struct drm_encoder  const  *__mptr ;

  {
#line 60
  __mptr = (struct drm_encoder  const  *)encoder;
#line 60
  return ((struct intel_hdmi *)__mptr);
}
}
#line 63 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 65
  tmp = intel_attached_encoder(connector);
#line 65
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 65
  return ((struct intel_hdmi *)__mptr);
}
}
#line 69 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
void intel_dip_infoframe_csum(struct dip_infoframe *avi_if ) 
{ uint8_t *data ;
  uint8_t sum ;
  unsigned int i ;
  int __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  uint8_t *__cil_tmp7 ;
  uint8_t __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;

  {
#line 71
  data = (uint8_t *)avi_if;
#line 72
  sum = (uint8_t )0U;
#line 75
  avi_if->checksum = (uint8_t )0U;
#line 76
  avi_if->ecc = (uint8_t )0U;
#line 78
  i = 0U;
#line 78
  goto ldv_37668;
  ldv_37667: 
#line 79
  __cil_tmp5 = (int )sum;
#line 79
  __cil_tmp6 = (unsigned long )i;
#line 79
  __cil_tmp7 = data + __cil_tmp6;
#line 79
  __cil_tmp8 = *__cil_tmp7;
#line 79
  __cil_tmp9 = (int )__cil_tmp8;
#line 79
  __cil_tmp10 = __cil_tmp9 + __cil_tmp5;
#line 79
  sum = (uint8_t )__cil_tmp10;
#line 78
  i = i + 1U;
  ldv_37668: ;
#line 78
  if (i <= 31U) {
#line 79
    goto ldv_37667;
  } else {
#line 81
    goto ldv_37669;
  }
  ldv_37669: 
#line 81
  __cil_tmp11 = (int )sum;
#line 81
  __cil_tmp12 = - __cil_tmp11;
#line 81
  avi_if->checksum = (uint8_t )__cil_tmp12;
#line 82
  return;
}
}
#line 84 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder ) 
{ struct dip_infoframe avi_if ;
  uint32_t *data ;
  struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  u32 port ;
  unsigned int i ;
  void *__cil_tmp10 ;
  bool __cil_tmp11 ;
  u32 __cil_tmp12 ;
  u32 __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  uint32_t __cil_tmp15 ;
  unsigned int __cil_tmp16 ;

  {
  {
#line 86
  avi_if.type = (uint8_t )130U;
#line 86
  avi_if.ver = (uint8_t )2U;
#line 86
  avi_if.len = (uint8_t )13U;
#line 86
  avi_if.ecc = (unsigned char)0;
#line 86
  avi_if.checksum = (unsigned char)0;
#line 86
  avi_if.body.payload[0] = (unsigned char)0;
#line 86
  avi_if.body.payload[1] = (unsigned char)0;
#line 86
  avi_if.body.payload[2] = (unsigned char)0;
#line 86
  avi_if.body.payload[3] = (unsigned char)0;
#line 86
  avi_if.body.payload[4] = (unsigned char)0;
#line 86
  avi_if.body.payload[5] = (unsigned char)0;
#line 86
  avi_if.body.payload[6] = (unsigned char)0;
#line 86
  avi_if.body.payload[7] = (unsigned char)0;
#line 86
  avi_if.body.payload[8] = (unsigned char)0;
#line 86
  avi_if.body.payload[9] = (unsigned char)0;
#line 86
  avi_if.body.payload[10] = (unsigned char)0;
#line 86
  avi_if.body.payload[11] = (unsigned char)0;
#line 86
  avi_if.body.payload[12] = (unsigned char)0;
#line 86
  avi_if.body.payload[13] = (unsigned char)0;
#line 86
  avi_if.body.payload[14] = (unsigned char)0;
#line 86
  avi_if.body.payload[15] = (unsigned char)0;
#line 86
  avi_if.body.payload[16] = (unsigned char)0;
#line 86
  avi_if.body.payload[17] = (unsigned char)0;
#line 86
  avi_if.body.payload[18] = (unsigned char)0;
#line 86
  avi_if.body.payload[19] = (unsigned char)0;
#line 86
  avi_if.body.payload[20] = (unsigned char)0;
#line 86
  avi_if.body.payload[21] = (unsigned char)0;
#line 86
  avi_if.body.payload[22] = (unsigned char)0;
#line 86
  avi_if.body.payload[23] = (unsigned char)0;
#line 86
  avi_if.body.payload[24] = (unsigned char)0;
#line 86
  avi_if.body.payload[25] = (unsigned char)0;
#line 86
  avi_if.body.payload[26] = (unsigned char)0;
#line 91
  data = (uint32_t *)(& avi_if);
#line 92
  dev = encoder->dev;
#line 93
  __cil_tmp10 = dev->dev_private;
#line 93
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 94
  tmp = enc_to_intel_hdmi(encoder);
#line 94
  intel_hdmi = tmp;
  }
  {
#line 98
  __cil_tmp11 = intel_hdmi->has_hdmi_sink;
#line 98
  if (! __cil_tmp11) {
#line 99
    return;
  } else {

  }
  }
  {
#line 102
  __cil_tmp12 = intel_hdmi->sdvox_reg;
#line 102
  if (__cil_tmp12 == 397632U) {
#line 103
    port = 536870912U;
  } else {
    {
#line 104
    __cil_tmp13 = intel_hdmi->sdvox_reg;
#line 104
    if (__cil_tmp13 == 397664U) {
#line 105
      port = 1073741824U;
    } else {
#line 107
      return;
    }
    }
  }
  }
  {
#line 109
  __cil_tmp14 = port | 2147549184U;
#line 109
  i915_write32___9(dev_priv, 397680U, __cil_tmp14);
#line 112
  intel_dip_infoframe_csum(& avi_if);
#line 113
  i = 0U;
  }
#line 113
  goto ldv_37681;
  ldv_37680: 
  {
#line 114
  __cil_tmp15 = *data;
#line 114
  i915_write32___9(dev_priv, 397688U, __cil_tmp15);
#line 115
  data = data + 1;
#line 113
  i = i + 4U;
  }
  ldv_37681: ;
#line 113
  if (i <= 31U) {
#line 114
    goto ldv_37680;
  } else {
#line 116
    goto ldv_37682;
  }
  ldv_37682: 
  {
#line 118
  __cil_tmp16 = port | 2149646336U;
#line 118
  i915_write32___9(dev_priv, 397680U, __cil_tmp16);
  }
#line 119
  return;
}
}
#line 123 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static void intel_hdmi_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  u32 sdvox ;
  void *__cil_tmp12 ;
  uint32_t __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  int __cil_tmp17 ;
  bool __cil_tmp18 ;
  void *__cil_tmp19 ;
  struct drm_i915_private *__cil_tmp20 ;
  enum intel_pch __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  bool __cil_tmp23 ;
  enum pipe __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  void *__cil_tmp26 ;
  struct drm_i915_private *__cil_tmp27 ;
  enum intel_pch __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  u32 __cil_tmp30 ;
  u32 __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  void *__cil_tmp33 ;
  void const volatile   *__cil_tmp34 ;
  void const volatile   *__cil_tmp35 ;

  {
  {
#line 127
  dev = encoder->dev;
#line 128
  __cil_tmp12 = dev->dev_private;
#line 128
  dev_priv = (struct drm_i915_private *)__cil_tmp12;
#line 129
  crtc = encoder->crtc;
#line 130
  __mptr = (struct drm_crtc  const  *)crtc;
#line 130
  intel_crtc = (struct intel_crtc *)__mptr;
#line 131
  tmp = enc_to_intel_hdmi(encoder);
#line 131
  intel_hdmi = tmp;
#line 134
  sdvox = 2176U;
#line 135
  __cil_tmp13 = intel_hdmi->color_range;
#line 135
  sdvox = __cil_tmp13 | sdvox;
  }
  {
#line 136
  __cil_tmp14 = adjusted_mode->flags;
#line 136
  __cil_tmp15 = __cil_tmp14 & 4U;
#line 136
  if (__cil_tmp15 != 0U) {
#line 137
    sdvox = sdvox | 16U;
  } else {

  }
  }
  {
#line 138
  __cil_tmp16 = adjusted_mode->flags;
#line 138
  __cil_tmp17 = (int )__cil_tmp16;
#line 138
  if (__cil_tmp17 & 1) {
#line 139
    sdvox = sdvox | 8U;
  } else {

  }
  }
  {
#line 142
  __cil_tmp18 = intel_hdmi->has_hdmi_sink;
#line 142
  if ((int )__cil_tmp18) {
    {
#line 142
    __cil_tmp19 = dev->dev_private;
#line 142
    __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
#line 142
    __cil_tmp21 = __cil_tmp20->pch_type;
#line 142
    __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 142
    if (__cil_tmp22 == 1U) {
#line 143
      sdvox = sdvox | 512U;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 145
  __cil_tmp23 = intel_hdmi->has_audio;
#line 145
  if ((int )__cil_tmp23) {
#line 146
    sdvox = sdvox | 64U;
#line 147
    sdvox = sdvox | 512U;
  } else {

  }
  }
  {
#line 150
  __cil_tmp24 = intel_crtc->pipe;
#line 150
  __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 150
  if (__cil_tmp25 == 1U) {
    {
#line 151
    __cil_tmp26 = dev->dev_private;
#line 151
    __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
#line 151
    __cil_tmp28 = __cil_tmp27->pch_type;
#line 151
    __cil_tmp29 = (unsigned int )__cil_tmp28;
#line 151
    if (__cil_tmp29 == 1U) {
#line 152
      sdvox = sdvox | 536870912U;
    } else {
#line 154
      sdvox = sdvox | 1073741824U;
    }
    }
  } else {

  }
  }
  {
#line 157
  __cil_tmp30 = intel_hdmi->sdvox_reg;
#line 157
  i915_write32___9(dev_priv, __cil_tmp30, sdvox);
#line 158
  __cil_tmp31 = intel_hdmi->sdvox_reg;
#line 158
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 158
  __cil_tmp33 = dev_priv->regs;
#line 158
  __cil_tmp34 = (void const volatile   *)__cil_tmp33;
#line 158
  __cil_tmp35 = __cil_tmp34 + __cil_tmp32;
#line 158
  readl(__cil_tmp35);
#line 160
  intel_hdmi_set_avi_infoframe(encoder);
  }
#line 161
  return;
}
}
#line 163 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static void intel_hdmi_dpms(struct drm_encoder *encoder , int mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  u32 temp ;
  void *__cil_tmp8 ;
  u32 __cil_tmp9 ;
  void *__cil_tmp10 ;
  struct drm_i915_private *__cil_tmp11 ;
  struct intel_device_info  const  *__cil_tmp12 ;
  u8 __cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  u32 __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  u32 __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  void *__cil_tmp20 ;
  void const volatile   *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  u32 __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  u32 __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  void *__cil_tmp33 ;
  void const volatile   *__cil_tmp34 ;
  void const volatile   *__cil_tmp35 ;
  void *__cil_tmp36 ;
  struct drm_i915_private *__cil_tmp37 ;
  struct intel_device_info  const  *__cil_tmp38 ;
  unsigned char *__cil_tmp39 ;
  unsigned char *__cil_tmp40 ;
  unsigned char __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  u32 __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  u32 __cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  void *__cil_tmp47 ;
  void const volatile   *__cil_tmp48 ;
  void const volatile   *__cil_tmp49 ;
  u32 __cil_tmp50 ;
  u32 __cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  void *__cil_tmp53 ;
  void const volatile   *__cil_tmp54 ;
  void const volatile   *__cil_tmp55 ;
  void *__cil_tmp56 ;
  struct drm_i915_private *__cil_tmp57 ;
  struct intel_device_info  const  *__cil_tmp58 ;
  u8 __cil_tmp59 ;
  unsigned char __cil_tmp60 ;
  unsigned int __cil_tmp61 ;
  u32 __cil_tmp62 ;
  u32 __cil_tmp63 ;
  unsigned long __cil_tmp64 ;
  void *__cil_tmp65 ;
  void const volatile   *__cil_tmp66 ;
  void const volatile   *__cil_tmp67 ;
  void *__cil_tmp68 ;
  struct drm_i915_private *__cil_tmp69 ;
  struct intel_device_info  const  *__cil_tmp70 ;
  u8 __cil_tmp71 ;
  unsigned char __cil_tmp72 ;
  unsigned int __cil_tmp73 ;
  u32 __cil_tmp74 ;
  u32 __cil_tmp75 ;
  unsigned long __cil_tmp76 ;
  void *__cil_tmp77 ;
  void const volatile   *__cil_tmp78 ;
  void const volatile   *__cil_tmp79 ;
  void *__cil_tmp80 ;
  struct drm_i915_private *__cil_tmp81 ;
  struct intel_device_info  const  *__cil_tmp82 ;
  unsigned char *__cil_tmp83 ;
  unsigned char *__cil_tmp84 ;
  unsigned char __cil_tmp85 ;
  unsigned int __cil_tmp86 ;
  u32 __cil_tmp87 ;
  u32 __cil_tmp88 ;
  unsigned long __cil_tmp89 ;
  void *__cil_tmp90 ;
  void const volatile   *__cil_tmp91 ;
  void const volatile   *__cil_tmp92 ;

  {
  {
#line 165
  dev = encoder->dev;
#line 166
  __cil_tmp8 = dev->dev_private;
#line 166
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 167
  tmp = enc_to_intel_hdmi(encoder);
#line 167
  intel_hdmi = tmp;
#line 170
  __cil_tmp9 = intel_hdmi->sdvox_reg;
#line 170
  temp = i915_read32___11(dev_priv, __cil_tmp9);
  }
  {
#line 175
  __cil_tmp10 = dev->dev_private;
#line 175
  __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
#line 175
  __cil_tmp12 = __cil_tmp11->info;
#line 175
  __cil_tmp13 = __cil_tmp12->gen;
#line 175
  __cil_tmp14 = (unsigned char )__cil_tmp13;
#line 175
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 175
  if (__cil_tmp15 == 5U) {
    {
#line 176
    __cil_tmp16 = intel_hdmi->sdvox_reg;
#line 176
    __cil_tmp17 = temp & 2147483647U;
#line 176
    i915_write32___9(dev_priv, __cil_tmp16, __cil_tmp17);
#line 177
    __cil_tmp18 = intel_hdmi->sdvox_reg;
#line 177
    __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 177
    __cil_tmp20 = dev_priv->regs;
#line 177
    __cil_tmp21 = (void const volatile   *)__cil_tmp20;
#line 177
    __cil_tmp22 = __cil_tmp21 + __cil_tmp19;
#line 177
    readl(__cil_tmp22);
    }
  } else {
    {
#line 175
    __cil_tmp23 = dev->dev_private;
#line 175
    __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 175
    __cil_tmp25 = __cil_tmp24->info;
#line 175
    __cil_tmp26 = __cil_tmp25->gen;
#line 175
    __cil_tmp27 = (unsigned char )__cil_tmp26;
#line 175
    __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 175
    if (__cil_tmp28 == 6U) {
      {
#line 176
      __cil_tmp29 = intel_hdmi->sdvox_reg;
#line 176
      __cil_tmp30 = temp & 2147483647U;
#line 176
      i915_write32___9(dev_priv, __cil_tmp29, __cil_tmp30);
#line 177
      __cil_tmp31 = intel_hdmi->sdvox_reg;
#line 177
      __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 177
      __cil_tmp33 = dev_priv->regs;
#line 177
      __cil_tmp34 = (void const volatile   *)__cil_tmp33;
#line 177
      __cil_tmp35 = __cil_tmp34 + __cil_tmp32;
#line 177
      readl(__cil_tmp35);
      }
    } else {
      {
#line 175
      __cil_tmp36 = dev->dev_private;
#line 175
      __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
#line 175
      __cil_tmp38 = __cil_tmp37->info;
#line 175
      __cil_tmp39 = (unsigned char *)__cil_tmp38;
#line 175
      __cil_tmp40 = __cil_tmp39 + 2UL;
#line 175
      __cil_tmp41 = *__cil_tmp40;
#line 175
      __cil_tmp42 = (unsigned int )__cil_tmp41;
#line 175
      if (__cil_tmp42 != 0U) {
        {
#line 176
        __cil_tmp43 = intel_hdmi->sdvox_reg;
#line 176
        __cil_tmp44 = temp & 2147483647U;
#line 176
        i915_write32___9(dev_priv, __cil_tmp43, __cil_tmp44);
#line 177
        __cil_tmp45 = intel_hdmi->sdvox_reg;
#line 177
        __cil_tmp46 = (unsigned long )__cil_tmp45;
#line 177
        __cil_tmp47 = dev_priv->regs;
#line 177
        __cil_tmp48 = (void const volatile   *)__cil_tmp47;
#line 177
        __cil_tmp49 = __cil_tmp48 + __cil_tmp46;
#line 177
        readl(__cil_tmp49);
        }
      } else {

      }
      }
    }
    }
  }
  }
#line 180
  if (mode != 0) {
#line 181
    temp = temp & 2147483647U;
  } else {
#line 183
    temp = temp | 2147483648U;
  }
  {
#line 186
  __cil_tmp50 = intel_hdmi->sdvox_reg;
#line 186
  i915_write32___9(dev_priv, __cil_tmp50, temp);
#line 187
  __cil_tmp51 = intel_hdmi->sdvox_reg;
#line 187
  __cil_tmp52 = (unsigned long )__cil_tmp51;
#line 187
  __cil_tmp53 = dev_priv->regs;
#line 187
  __cil_tmp54 = (void const volatile   *)__cil_tmp53;
#line 187
  __cil_tmp55 = __cil_tmp54 + __cil_tmp52;
#line 187
  readl(__cil_tmp55);
  }
  {
#line 192
  __cil_tmp56 = dev->dev_private;
#line 192
  __cil_tmp57 = (struct drm_i915_private *)__cil_tmp56;
#line 192
  __cil_tmp58 = __cil_tmp57->info;
#line 192
  __cil_tmp59 = __cil_tmp58->gen;
#line 192
  __cil_tmp60 = (unsigned char )__cil_tmp59;
#line 192
  __cil_tmp61 = (unsigned int )__cil_tmp60;
#line 192
  if (__cil_tmp61 == 5U) {
    {
#line 193
    __cil_tmp62 = intel_hdmi->sdvox_reg;
#line 193
    i915_write32___9(dev_priv, __cil_tmp62, temp);
#line 194
    __cil_tmp63 = intel_hdmi->sdvox_reg;
#line 194
    __cil_tmp64 = (unsigned long )__cil_tmp63;
#line 194
    __cil_tmp65 = dev_priv->regs;
#line 194
    __cil_tmp66 = (void const volatile   *)__cil_tmp65;
#line 194
    __cil_tmp67 = __cil_tmp66 + __cil_tmp64;
#line 194
    readl(__cil_tmp67);
    }
  } else {
    {
#line 192
    __cil_tmp68 = dev->dev_private;
#line 192
    __cil_tmp69 = (struct drm_i915_private *)__cil_tmp68;
#line 192
    __cil_tmp70 = __cil_tmp69->info;
#line 192
    __cil_tmp71 = __cil_tmp70->gen;
#line 192
    __cil_tmp72 = (unsigned char )__cil_tmp71;
#line 192
    __cil_tmp73 = (unsigned int )__cil_tmp72;
#line 192
    if (__cil_tmp73 == 6U) {
      {
#line 193
      __cil_tmp74 = intel_hdmi->sdvox_reg;
#line 193
      i915_write32___9(dev_priv, __cil_tmp74, temp);
#line 194
      __cil_tmp75 = intel_hdmi->sdvox_reg;
#line 194
      __cil_tmp76 = (unsigned long )__cil_tmp75;
#line 194
      __cil_tmp77 = dev_priv->regs;
#line 194
      __cil_tmp78 = (void const volatile   *)__cil_tmp77;
#line 194
      __cil_tmp79 = __cil_tmp78 + __cil_tmp76;
#line 194
      readl(__cil_tmp79);
      }
    } else {
      {
#line 192
      __cil_tmp80 = dev->dev_private;
#line 192
      __cil_tmp81 = (struct drm_i915_private *)__cil_tmp80;
#line 192
      __cil_tmp82 = __cil_tmp81->info;
#line 192
      __cil_tmp83 = (unsigned char *)__cil_tmp82;
#line 192
      __cil_tmp84 = __cil_tmp83 + 2UL;
#line 192
      __cil_tmp85 = *__cil_tmp84;
#line 192
      __cil_tmp86 = (unsigned int )__cil_tmp85;
#line 192
      if (__cil_tmp86 != 0U) {
        {
#line 193
        __cil_tmp87 = intel_hdmi->sdvox_reg;
#line 193
        i915_write32___9(dev_priv, __cil_tmp87, temp);
#line 194
        __cil_tmp88 = intel_hdmi->sdvox_reg;
#line 194
        __cil_tmp89 = (unsigned long )__cil_tmp88;
#line 194
        __cil_tmp90 = dev_priv->regs;
#line 194
        __cil_tmp91 = (void const volatile   *)__cil_tmp90;
#line 194
        __cil_tmp92 = __cil_tmp91 + __cil_tmp89;
#line 194
        readl(__cil_tmp92);
        }
      } else {

      }
      }
    }
    }
  }
  }
#line 196
  return;
}
}
#line 198 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static int intel_hdmi_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) 
{ int __cil_tmp3 ;
  int __cil_tmp4 ;
  unsigned int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;

  {
  {
#line 201
  __cil_tmp3 = mode->clock;
#line 201
  if (__cil_tmp3 > 165000) {
#line 202
    return (15);
  } else {

  }
  }
  {
#line 203
  __cil_tmp4 = mode->clock;
#line 203
  if (__cil_tmp4 <= 19999) {
#line 204
    return (16);
  } else {

  }
  }
  {
#line 206
  __cil_tmp5 = mode->flags;
#line 206
  __cil_tmp6 = __cil_tmp5 & 32U;
#line 206
  if (__cil_tmp6 != 0U) {
#line 207
    return (8);
  } else {

  }
  }
#line 209
  return (0);
}
}
#line 212 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                  struct drm_display_mode *adjusted_mode ) 
{ 

  {
#line 216
  return ((bool )1);
}
}
#line 220 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static enum drm_connector_status intel_hdmi_detect(struct drm_connector *connector ,
                                                   bool force ) 
{ struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  struct drm_i915_private *dev_priv ;
  struct edid *edid ;
  enum drm_connector_status status ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct intel_gmbus *__cil_tmp12 ;
  struct intel_gmbus *__cil_tmp13 ;
  struct i2c_adapter *__cil_tmp14 ;
  struct edid *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  u8 __cil_tmp18 ;
  signed char __cil_tmp19 ;
  int __cil_tmp20 ;
  void const   *__cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;

  {
  {
#line 222
  tmp = intel_attached_hdmi(connector);
#line 222
  intel_hdmi = tmp;
#line 223
  __cil_tmp8 = connector->dev;
#line 223
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 223
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 225
  status = (enum drm_connector_status )2;
#line 227
  intel_hdmi->has_hdmi_sink = (bool )0;
#line 228
  intel_hdmi->has_audio = (bool )0;
#line 229
  __cil_tmp10 = intel_hdmi->ddc_bus;
#line 229
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 229
  __cil_tmp12 = dev_priv->gmbus;
#line 229
  __cil_tmp13 = __cil_tmp12 + __cil_tmp11;
#line 229
  __cil_tmp14 = & __cil_tmp13->adapter;
#line 229
  edid = drm_get_edid(connector, __cil_tmp14);
  }
  {
#line 232
  __cil_tmp15 = (struct edid *)0;
#line 232
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 232
  __cil_tmp17 = (unsigned long )edid;
#line 232
  if (__cil_tmp17 != __cil_tmp16) {
    {
#line 233
    __cil_tmp18 = edid->input;
#line 233
    __cil_tmp19 = (signed char )__cil_tmp18;
#line 233
    __cil_tmp20 = (int )__cil_tmp19;
#line 233
    if (__cil_tmp20 < 0) {
      {
#line 234
      status = (enum drm_connector_status )1;
#line 235
      intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
#line 236
      intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
      }
    } else {

    }
    }
    {
#line 238
    connector->display_info.raw_edid = (char *)0;
#line 239
    __cil_tmp21 = (void const   *)edid;
#line 239
    kfree(__cil_tmp21);
    }
  } else {

  }
  }
  {
#line 242
  __cil_tmp22 = (unsigned int )status;
#line 242
  if (__cil_tmp22 == 1U) {
    {
#line 243
    __cil_tmp23 = intel_hdmi->force_audio;
#line 243
    if (__cil_tmp23 != 0) {
#line 244
      __cil_tmp24 = intel_hdmi->force_audio;
#line 244
      __cil_tmp25 = __cil_tmp24 > 0;
#line 244
      intel_hdmi->has_audio = (bool )__cil_tmp25;
    } else {

    }
    }
  } else {

  }
  }
#line 247
  return (status);
}
}
#line 250 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static int intel_hdmi_get_modes(struct drm_connector *connector ) 
{ struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  struct drm_i915_private *dev_priv ;
  int tmp___0 ;
  struct drm_device *__cil_tmp6 ;
  void *__cil_tmp7 ;
  int __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct intel_gmbus *__cil_tmp10 ;
  struct intel_gmbus *__cil_tmp11 ;
  struct i2c_adapter *__cil_tmp12 ;

  {
  {
#line 252
  tmp = intel_attached_hdmi(connector);
#line 252
  intel_hdmi = tmp;
#line 253
  __cil_tmp6 = connector->dev;
#line 253
  __cil_tmp7 = __cil_tmp6->dev_private;
#line 253
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
#line 259
  __cil_tmp8 = intel_hdmi->ddc_bus;
#line 259
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 259
  __cil_tmp10 = dev_priv->gmbus;
#line 259
  __cil_tmp11 = __cil_tmp10 + __cil_tmp9;
#line 259
  __cil_tmp12 = & __cil_tmp11->adapter;
#line 259
  tmp___0 = intel_ddc_get_modes(connector, __cil_tmp12);
  }
#line 259
  return (tmp___0);
}
}
#line 264 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static bool intel_hdmi_detect_audio(struct drm_connector *connector ) 
{ struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  struct drm_i915_private *dev_priv ;
  struct edid *edid ;
  bool has_audio ;
  struct drm_device *__cil_tmp7 ;
  void *__cil_tmp8 ;
  int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct intel_gmbus *__cil_tmp11 ;
  struct intel_gmbus *__cil_tmp12 ;
  struct i2c_adapter *__cil_tmp13 ;
  struct edid *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  u8 __cil_tmp17 ;
  signed char __cil_tmp18 ;
  int __cil_tmp19 ;
  void const   *__cil_tmp20 ;

  {
  {
#line 266
  tmp = intel_attached_hdmi(connector);
#line 266
  intel_hdmi = tmp;
#line 267
  __cil_tmp7 = connector->dev;
#line 267
  __cil_tmp8 = __cil_tmp7->dev_private;
#line 267
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 269
  has_audio = (bool )0;
#line 271
  __cil_tmp9 = intel_hdmi->ddc_bus;
#line 271
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 271
  __cil_tmp11 = dev_priv->gmbus;
#line 271
  __cil_tmp12 = __cil_tmp11 + __cil_tmp10;
#line 271
  __cil_tmp13 = & __cil_tmp12->adapter;
#line 271
  edid = drm_get_edid(connector, __cil_tmp13);
  }
  {
#line 273
  __cil_tmp14 = (struct edid *)0;
#line 273
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 273
  __cil_tmp16 = (unsigned long )edid;
#line 273
  if (__cil_tmp16 != __cil_tmp15) {
    {
#line 274
    __cil_tmp17 = edid->input;
#line 274
    __cil_tmp18 = (signed char )__cil_tmp17;
#line 274
    __cil_tmp19 = (int )__cil_tmp18;
#line 274
    if (__cil_tmp19 < 0) {
      {
#line 275
      has_audio = drm_detect_monitor_audio(edid);
      }
    } else {

    }
    }
    {
#line 277
    connector->display_info.raw_edid = (char *)0;
#line 278
    __cil_tmp20 = (void const   *)edid;
#line 278
    kfree(__cil_tmp20);
    }
  } else {

  }
  }
#line 281
  return (has_audio);
}
}
#line 285 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static int intel_hdmi_set_property(struct drm_connector *connector , struct drm_property *property ,
                                   uint64_t val ) 
{ struct intel_hdmi *intel_hdmi ;
  struct intel_hdmi *tmp ;
  struct drm_i915_private *dev_priv ;
  int ret ;
  int i ;
  bool has_audio ;
  struct drm_crtc *crtc ;
  struct drm_device *__cil_tmp11 ;
  void *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_property *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  bool __cil_tmp19 ;
  int __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_property *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  uint32_t __cil_tmp24 ;
  int __cil_tmp25 ;
  uint64_t __cil_tmp26 ;
  struct drm_crtc *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  struct drm_crtc *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  struct drm_display_mode *__cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  struct drm_framebuffer *__cil_tmp34 ;

  {
  {
#line 289
  tmp = intel_attached_hdmi(connector);
#line 289
  intel_hdmi = tmp;
#line 290
  __cil_tmp11 = connector->dev;
#line 290
  __cil_tmp12 = __cil_tmp11->dev_private;
#line 290
  dev_priv = (struct drm_i915_private *)__cil_tmp12;
#line 293
  ret = drm_connector_property_set_value(connector, property, val);
  }
#line 294
  if (ret != 0) {
#line 295
    return (ret);
  } else {

  }
  {
#line 297
  __cil_tmp13 = (unsigned long )property;
#line 297
  __cil_tmp14 = dev_priv->force_audio_property;
#line 297
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 297
  if (__cil_tmp15 == __cil_tmp13) {
#line 298
    i = (int )val;
    {
#line 301
    __cil_tmp16 = intel_hdmi->force_audio;
#line 301
    if (__cil_tmp16 == i) {
#line 302
      return (0);
    } else {

    }
    }
#line 304
    intel_hdmi->force_audio = i;
#line 306
    if (i == 0) {
      {
#line 307
      has_audio = intel_hdmi_detect_audio(connector);
      }
    } else {
#line 309
      __cil_tmp17 = i > 0;
#line 309
      has_audio = (bool )__cil_tmp17;
    }
    {
#line 311
    __cil_tmp18 = (int )has_audio;
#line 311
    __cil_tmp19 = intel_hdmi->has_audio;
#line 311
    __cil_tmp20 = (int )__cil_tmp19;
#line 311
    if (__cil_tmp20 == __cil_tmp18) {
#line 312
      return (0);
    } else {

    }
    }
#line 314
    intel_hdmi->has_audio = has_audio;
#line 315
    goto done;
  } else {

  }
  }
  {
#line 318
  __cil_tmp21 = (unsigned long )property;
#line 318
  __cil_tmp22 = dev_priv->broadcast_rgb_property;
#line 318
  __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 318
  if (__cil_tmp23 == __cil_tmp21) {
    {
#line 319
    __cil_tmp24 = intel_hdmi->color_range;
#line 319
    __cil_tmp25 = __cil_tmp24 != 0U;
#line 319
    __cil_tmp26 = (uint64_t )__cil_tmp25;
#line 319
    if (__cil_tmp26 == val) {
#line 320
      return (0);
    } else {

    }
    }
#line 322
    if (val != 0ULL) {
#line 322
      intel_hdmi->color_range = 256U;
    } else {
#line 322
      intel_hdmi->color_range = 0U;
    }
#line 323
    goto done;
  } else {

  }
  }
#line 326
  return (-22);
  done: ;
  {
#line 329
  __cil_tmp27 = (struct drm_crtc *)0;
#line 329
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 329
  __cil_tmp29 = intel_hdmi->base.base.crtc;
#line 329
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 329
  if (__cil_tmp30 != __cil_tmp28) {
    {
#line 330
    crtc = intel_hdmi->base.base.crtc;
#line 331
    __cil_tmp31 = & crtc->mode;
#line 331
    __cil_tmp32 = crtc->x;
#line 331
    __cil_tmp33 = crtc->y;
#line 331
    __cil_tmp34 = crtc->fb;
#line 331
    drm_crtc_helper_set_mode(crtc, __cil_tmp31, __cil_tmp32, __cil_tmp33, __cil_tmp34);
    }
  } else {

  }
  }
#line 336
  return (0);
}
}
#line 339 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static void intel_hdmi_destroy(struct drm_connector *connector ) 
{ void const   *__cil_tmp2 ;

  {
  {
#line 341
  drm_sysfs_connector_remove(connector);
#line 342
  drm_connector_cleanup(connector);
#line 343
  __cil_tmp2 = (void const   *)connector;
#line 343
  kfree(__cil_tmp2);
  }
#line 344
  return;
}
}
#line 346 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static struct drm_encoder_helper_funcs  const  intel_hdmi_helper_funcs  = 
#line 346
     {& intel_hdmi_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_hdmi_mode_fixup, & intel_encoder_prepare, & intel_encoder_commit, & intel_hdmi_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 354 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static struct drm_connector_funcs  const  intel_hdmi_connector_funcs  = 
#line 354
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    (void (*)(struct drm_connector * ))0, & intel_hdmi_detect, & drm_helper_probe_single_connector_modes,
    & intel_hdmi_set_property, & intel_hdmi_destroy, (void (*)(struct drm_connector * ))0};
#line 362 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static struct drm_connector_helper_funcs  const  intel_hdmi_connector_helper_funcs  =    {& intel_hdmi_get_modes,
    & intel_hdmi_mode_valid, & intel_best_encoder};
#line 368 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static struct drm_encoder_funcs  const  intel_hdmi_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_encoder_destroy};
#line 373 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
static void intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi , struct drm_connector *connector ) 
{ 

  {
  {
#line 375
  intel_attach_force_audio_property(connector);
#line 376
  intel_attach_broadcast_rgb_property(connector);
  }
#line 377
  return;
}
}
#line 379 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
void intel_hdmi_init(struct drm_device *dev , int sdvox_reg ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_connector *connector ;
  struct intel_encoder *intel_encoder ;
  struct intel_connector *intel_connector ;
  struct intel_hdmi *intel_hdmi ;
  void *tmp ;
  void *tmp___0 ;
  u32 temp ;
  u32 tmp___1 ;
  void *__cil_tmp12 ;
  struct intel_hdmi *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct intel_connector *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  void const   *__cil_tmp19 ;
  struct drm_encoder *__cil_tmp20 ;
  u32 __cil_tmp21 ;
  u32 __cil_tmp22 ;
  u32 __cil_tmp23 ;
  u32 __cil_tmp24 ;
  u32 __cil_tmp25 ;
  struct drm_encoder *__cil_tmp26 ;
  void *__cil_tmp27 ;
  struct drm_i915_private *__cil_tmp28 ;
  struct intel_device_info  const  *__cil_tmp29 ;
  unsigned char *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned int __cil_tmp36 ;

  {
  {
#line 381
  __cil_tmp12 = dev->dev_private;
#line 381
  dev_priv = (struct drm_i915_private *)__cil_tmp12;
#line 387
  tmp = kzalloc(120UL, 208U);
#line 387
  intel_hdmi = (struct intel_hdmi *)tmp;
  }
  {
#line 388
  __cil_tmp13 = (struct intel_hdmi *)0;
#line 388
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 388
  __cil_tmp15 = (unsigned long )intel_hdmi;
#line 388
  if (__cil_tmp15 == __cil_tmp14) {
#line 389
    return;
  } else {

  }
  }
  {
#line 391
  tmp___0 = kzalloc(1576UL, 208U);
#line 391
  intel_connector = (struct intel_connector *)tmp___0;
  }
  {
#line 392
  __cil_tmp16 = (struct intel_connector *)0;
#line 392
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 392
  __cil_tmp18 = (unsigned long )intel_connector;
#line 392
  if (__cil_tmp18 == __cil_tmp17) {
    {
#line 393
    __cil_tmp19 = (void const   *)intel_hdmi;
#line 393
    kfree(__cil_tmp19);
    }
#line 394
    return;
  } else {

  }
  }
  {
#line 397
  intel_encoder = & intel_hdmi->base;
#line 398
  __cil_tmp20 = & intel_encoder->base;
#line 398
  drm_encoder_init(dev, __cil_tmp20, & intel_hdmi_enc_funcs, 2);
#line 401
  connector = & intel_connector->base;
#line 402
  drm_connector_init(dev, connector, & intel_hdmi_connector_funcs, 11);
#line 404
  drm_connector_helper_add(connector, & intel_hdmi_connector_helper_funcs);
#line 406
  intel_encoder->type = 6;
#line 408
  connector->polled = (uint8_t )1U;
#line 409
  connector->interlace_allowed = (bool )0;
#line 410
  connector->doublescan_allowed = (bool )0;
#line 411
  intel_encoder->crtc_mask = 3;
  }
#line 414
  if (sdvox_reg == 397632) {
#line 415
    intel_encoder->clone_mask = 2;
#line 416
    intel_hdmi->ddc_bus = 5;
#line 417
    __cil_tmp21 = dev_priv->hotplug_supported_mask;
#line 417
    dev_priv->hotplug_supported_mask = __cil_tmp21 | 536870912U;
  } else
#line 418
  if (sdvox_reg == 397664) {
#line 419
    intel_encoder->clone_mask = 4;
#line 420
    intel_hdmi->ddc_bus = 4;
#line 421
    __cil_tmp22 = dev_priv->hotplug_supported_mask;
#line 421
    dev_priv->hotplug_supported_mask = __cil_tmp22 | 268435456U;
  } else
#line 422
  if (sdvox_reg == 921920) {
#line 423
    intel_encoder->clone_mask = 8;
#line 424
    intel_hdmi->ddc_bus = 5;
#line 425
    __cil_tmp23 = dev_priv->hotplug_supported_mask;
#line 425
    dev_priv->hotplug_supported_mask = __cil_tmp23 | 536870912U;
  } else
#line 426
  if (sdvox_reg == 921936) {
#line 427
    intel_encoder->clone_mask = 16;
#line 428
    intel_hdmi->ddc_bus = 4;
#line 429
    __cil_tmp24 = dev_priv->hotplug_supported_mask;
#line 429
    dev_priv->hotplug_supported_mask = __cil_tmp24 | 268435456U;
  } else
#line 430
  if (sdvox_reg == 921952) {
#line 431
    intel_encoder->clone_mask = 32;
#line 432
    intel_hdmi->ddc_bus = 7;
#line 433
    __cil_tmp25 = dev_priv->hotplug_supported_mask;
#line 433
    dev_priv->hotplug_supported_mask = __cil_tmp25 | 134217728U;
  } else {

  }
  {
#line 436
  intel_hdmi->sdvox_reg = (u32 )sdvox_reg;
#line 438
  __cil_tmp26 = & intel_encoder->base;
#line 438
  drm_encoder_helper_add(__cil_tmp26, & intel_hdmi_helper_funcs);
#line 440
  intel_hdmi_add_properties(intel_hdmi, connector);
#line 442
  intel_connector_attach_encoder(intel_connector, intel_encoder);
#line 443
  drm_sysfs_connector_add(connector);
  }
  {
#line 449
  __cil_tmp27 = dev->dev_private;
#line 449
  __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
#line 449
  __cil_tmp29 = __cil_tmp28->info;
#line 449
  __cil_tmp30 = (unsigned char *)__cil_tmp29;
#line 449
  __cil_tmp31 = __cil_tmp30 + 1UL;
#line 449
  __cil_tmp32 = *__cil_tmp31;
#line 449
  __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 449
  if (__cil_tmp33 != 0U) {
    {
#line 449
    __cil_tmp34 = dev->pci_device;
#line 449
    if (__cil_tmp34 != 10818) {
      {
#line 450
      tmp___1 = i915_read32___11(dev_priv, 85352U);
#line 450
      temp = tmp___1;
#line 451
      __cil_tmp35 = temp & 4294967280U;
#line 451
      __cil_tmp36 = __cil_tmp35 | 13U;
#line 451
      i915_write32___9(dev_priv, 85352U, __cil_tmp36);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 453
  return;
}
}
#line 486 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_hdmi.c.p"
void main(void) 
{ struct drm_encoder *var_group1 ;
  int var_intel_hdmi_dpms_5_p1 ;
  struct drm_display_mode *var_group2 ;
  struct drm_display_mode *var_intel_hdmi_mode_fixup_7_p2 ;
  struct drm_display_mode *var_intel_hdmi_mode_set_4_p2 ;
  struct drm_connector *var_group3 ;
  bool var_intel_hdmi_detect_8_p1 ;
  struct drm_property *var_group4 ;
  uint64_t var_intel_hdmi_set_property_11_p2 ;
  int tmp ;
  int tmp___0 ;
  int __cil_tmp12 ;
  bool __cil_tmp13 ;

  {
  {
#line 538
  LDV_IN_INTERRUPT = 1;
#line 547
  ldv_initialize();
  }
#line 555
  goto ldv_37798;
  ldv_37797: 
  {
#line 558
  tmp = nondet_int();
  }
#line 560
  if (tmp == 0) {
#line 560
    goto case_0;
  } else
#line 576
  if (tmp == 1) {
#line 576
    goto case_1;
  } else
#line 592
  if (tmp == 2) {
#line 592
    goto case_2;
  } else
#line 608
  if (tmp == 3) {
#line 608
    goto case_3;
  } else
#line 624
  if (tmp == 4) {
#line 624
    goto case_4;
  } else
#line 640
  if (tmp == 5) {
#line 640
    goto case_5;
  } else
#line 656
  if (tmp == 6) {
#line 656
    goto case_6;
  } else
#line 672
  if (tmp == 7) {
#line 672
    goto case_7;
  } else {
#line 688
    goto switch_default;
#line 558
    if (0) {
      case_0: 
      {
#line 568
      intel_hdmi_dpms(var_group1, var_intel_hdmi_dpms_5_p1);
      }
#line 575
      goto ldv_37788;
      case_1: 
      {
#line 584
      intel_hdmi_mode_fixup(var_group1, var_group2, var_intel_hdmi_mode_fixup_7_p2);
      }
#line 591
      goto ldv_37788;
      case_2: 
      {
#line 600
      intel_hdmi_mode_set(var_group1, var_group2, var_intel_hdmi_mode_set_4_p2);
      }
#line 607
      goto ldv_37788;
      case_3: 
      {
#line 616
      __cil_tmp12 = (int )var_intel_hdmi_detect_8_p1;
#line 616
      __cil_tmp13 = (bool )__cil_tmp12;
#line 616
      intel_hdmi_detect(var_group3, __cil_tmp13);
      }
#line 623
      goto ldv_37788;
      case_4: 
      {
#line 632
      intel_hdmi_set_property(var_group3, var_group4, var_intel_hdmi_set_property_11_p2);
      }
#line 639
      goto ldv_37788;
      case_5: 
      {
#line 648
      intel_hdmi_destroy(var_group3);
      }
#line 655
      goto ldv_37788;
      case_6: 
      {
#line 664
      intel_hdmi_get_modes(var_group3);
      }
#line 671
      goto ldv_37788;
      case_7: 
      {
#line 680
      intel_hdmi_mode_valid(var_group3, var_group2);
      }
#line 687
      goto ldv_37788;
      switch_default: ;
#line 688
      goto ldv_37788;
    } else {

    }
  }
  ldv_37788: ;
  ldv_37798: 
  {
#line 555
  tmp___0 = nondet_int();
  }
#line 555
  if (tmp___0 != 0) {
#line 556
    goto ldv_37797;
  } else {
#line 558
    goto ldv_37799;
  }
  ldv_37799: 
  {
#line 697
  ldv_check_final_state();
  }
#line 700
  return;
}
}
#line 24 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/arch_hweight.h"
__inline static unsigned int __arch_hweight32(unsigned int w ) 
{ unsigned int res ;

  {
#line 26
  res = 0U;
#line 28
  __asm__  ("661:\n\tcall __sw_hweight32\n662:\n.section .altinstructions,\"a\"\n .balign 8 \n .quad 661b\n .quad 663f\n\t .word (4*32+23)\n\t .byte 662b-661b\n\t .byte 664f-663f\n.previous\n.section .discard,\"aw\",@progbits\n\t .byte 0xff + (664f-663f) - (662b-661b)\n.previous\n.section .altinstr_replacement, \"ax\"\n663:\n\t.byte 0xf3,0x40,0x0f,0xb8,0xc7\n664:\n.previous": "=a" (res): "D" (w));
#line 32
  return (res);
}
}
#line 35 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/arch_hweight.h"
__inline static unsigned int __arch_hweight16(unsigned int w ) 
{ unsigned int tmp ;
  unsigned int __cil_tmp3 ;

  {
  {
#line 37
  __cil_tmp3 = w & 65535U;
#line 37
  tmp = __arch_hweight32(__cil_tmp3);
  }
#line 37
  return (tmp);
}
}
#line 66 "include/linux/i2c.h"
extern int i2c_transfer(struct i2c_adapter * , struct i2c_msg * , int  ) ;
#line 430
extern int i2c_add_adapter(struct i2c_adapter * ) ;
#line 685 "include/drm/drm_crtc.h"
extern void drm_mode_destroy(struct drm_device * , struct drm_display_mode * ) ;
#line 721
extern struct drm_property *drm_property_create(struct drm_device * , int  , char const   * ,
                                                int  ) ;
#line 723
extern void drm_property_destroy(struct drm_device * , struct drm_property * ) ;
#line 724
extern int drm_property_add_enum(struct drm_property * , int  , uint64_t  , char const   * ) ;
#line 1248 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
void intel_gmbus_set_speed(struct i2c_adapter *adapter , int speed ) ;
#line 1249
void intel_gmbus_force_bit(struct i2c_adapter *adapter , bool force_bit ) ;
#line 115 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
__inline static void intel_mode_set_pixel_multiplier(struct drm_display_mode *mode ,
                                                     int multiplier ) 
{ int __cil_tmp3 ;
  int __cil_tmp4 ;

  {
#line 118
  __cil_tmp3 = mode->clock;
#line 118
  mode->clock = __cil_tmp3 * multiplier;
#line 119
  __cil_tmp4 = mode->private_flags;
#line 119
  mode->private_flags = __cil_tmp4 | multiplier;
#line 120
  return;
}
}
#line 62 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static char const   *tv_format_names[19U]  = 
#line 62 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
  {      "NTSC_M",      "NTSC_J",      "NTSC_443",      "PAL_B", 
        "PAL_D",      "PAL_G",      "PAL_H",      "PAL_I", 
        "PAL_M",      "PAL_N",      "PAL_NC",      "PAL_60", 
        "SECAM_B",      "SECAM_D",      "SECAM_G",      "SECAM_K", 
        "SECAM_K1",      "SECAM_L",      "SECAM_60"};
#line 200 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder ) 
{ struct drm_encoder  const  *__mptr ;

  {
#line 202
  __mptr = (struct drm_encoder  const  *)encoder;
#line 202
  return ((struct intel_sdvo *)__mptr);
}
}
#line 205 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 207
  tmp = intel_attached_encoder(connector);
#line 207
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 207
  return ((struct intel_sdvo *)__mptr);
}
}
#line 211 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector ) 
{ struct intel_connector  const  *__mptr ;
  struct drm_connector  const  *__mptr___0 ;
  struct intel_connector *__cil_tmp4 ;

  {
#line 213
  __mptr___0 = (struct drm_connector  const  *)connector;
#line 213
  __cil_tmp4 = (struct intel_connector *)__mptr___0;
#line 213
  __mptr = (struct intel_connector  const  *)__cil_tmp4;
#line 213
  return ((struct intel_sdvo_connector *)__mptr);
}
}
#line 217
static bool intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo , uint16_t flags ) ;
#line 219
static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo , struct intel_sdvo_connector *intel_sdvo_connector ,
                                          int type ) ;
#line 223
static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo , struct intel_sdvo_connector *intel_sdvo_connector ) ;
#line 231 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo , u32 val ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 bval ;
  u32 cval ;
  int i ;
  void *__cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  u32 __cil_tmp11 ;
  int __cil_tmp12 ;
  u32 __cil_tmp13 ;
  int __cil_tmp14 ;

  {
#line 233
  dev = intel_sdvo->base.base.dev;
#line 234
  __cil_tmp8 = dev->dev_private;
#line 234
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 235
  bval = val;
#line 235
  cval = val;
  {
#line 238
  __cil_tmp9 = intel_sdvo->sdvo_reg;
#line 238
  if (__cil_tmp9 == 921920) {
    {
#line 239
    __cil_tmp10 = intel_sdvo->sdvo_reg;
#line 239
    __cil_tmp11 = (u32 )__cil_tmp10;
#line 239
    i915_write32___9(dev_priv, __cil_tmp11, val);
#line 240
    __cil_tmp12 = intel_sdvo->sdvo_reg;
#line 240
    __cil_tmp13 = (u32 )__cil_tmp12;
#line 240
    i915_read32___11(dev_priv, __cil_tmp13);
    }
#line 241
    return;
  } else {

  }
  }
  {
#line 244
  __cil_tmp14 = intel_sdvo->sdvo_reg;
#line 244
  if (__cil_tmp14 == 397632) {
    {
#line 245
    cval = i915_read32___11(dev_priv, 397664U);
    }
  } else {
    {
#line 247
    bval = i915_read32___11(dev_priv, 397632U);
    }
  }
  }
#line 254
  i = 0;
#line 254
  goto ldv_38028;
  ldv_38027: 
  {
#line 256
  i915_write32___9(dev_priv, 397632U, bval);
#line 257
  i915_read32___11(dev_priv, 397632U);
#line 258
  i915_write32___9(dev_priv, 397664U, cval);
#line 259
  i915_read32___11(dev_priv, 397664U);
#line 254
  i = i + 1;
  }
  ldv_38028: ;
#line 254
  if (i <= 1) {
#line 255
    goto ldv_38027;
  } else {
#line 257
    goto ldv_38029;
  }
  ldv_38029: ;
#line 259
  return;
}
}
#line 263 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo , u8 addr , u8 *ch ) 
{ struct i2c_msg msgs[2U] ;
  int ret ;
  u8 __cil_tmp6 ;
  u8 __cil_tmp7 ;
  struct i2c_adapter *__cil_tmp8 ;
  struct i2c_msg *__cil_tmp9 ;

  {
  {
#line 265
  __cil_tmp6 = intel_sdvo->slave_addr;
#line 265
  msgs[0].addr = (unsigned short )__cil_tmp6;
#line 265
  msgs[0].flags = (__u16 )0U;
#line 265
  msgs[0].len = (__u16 )1U;
#line 265
  msgs[0].buf = & addr;
#line 265
  __cil_tmp7 = intel_sdvo->slave_addr;
#line 265
  msgs[1].addr = (unsigned short )__cil_tmp7;
#line 265
  msgs[1].flags = (__u16 )1U;
#line 265
  msgs[1].len = (__u16 )1U;
#line 265
  msgs[1].buf = ch;
#line 281
  __cil_tmp8 = intel_sdvo->i2c;
#line 281
  __cil_tmp9 = (struct i2c_msg *)(& msgs);
#line 281
  ret = i2c_transfer(__cil_tmp8, __cil_tmp9, 2);
  }
#line 281
  if (ret == 2) {
#line 282
    return ((bool )1);
  } else {

  }
  {
#line 284
  drm_ut_debug_printk(4U, "drm", "intel_sdvo_read_byte", "i2c transfer returned %d\n",
                      ret);
  }
#line 285
  return ((bool )0);
}
}
#line 293 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct _sdvo_cmd_name  const  sdvo_cmd_names[107U]  = 
#line 293
  {      {(u8 )1U, "SDVO_CMD_RESET"}, 
        {(u8 )2U, "SDVO_CMD_GET_DEVICE_CAPS"}, 
        {(u8 )134U, "SDVO_CMD_GET_FIRMWARE_REV"}, 
        {(u8 )3U, "SDVO_CMD_GET_TRAINED_INPUTS"}, 
        {(u8 )4U, "SDVO_CMD_GET_ACTIVE_OUTPUTS"}, 
        {(u8 )5U, "SDVO_CMD_SET_ACTIVE_OUTPUTS"}, 
        {(u8 )6U, "SDVO_CMD_GET_IN_OUT_MAP"}, 
        {(u8 )7U, "SDVO_CMD_SET_IN_OUT_MAP"}, 
        {(u8 )11U, "SDVO_CMD_GET_ATTACHED_DISPLAYS"}, 
        {(u8 )12U, "SDVO_CMD_GET_HOT_PLUG_SUPPORT"}, 
        {(u8 )13U, "SDVO_CMD_SET_ACTIVE_HOT_PLUG"}, 
        {(u8 )14U, "SDVO_CMD_GET_ACTIVE_HOT_PLUG"}, 
        {(u8 )15U, "SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE"}, 
        {(u8 )16U, "SDVO_CMD_SET_TARGET_INPUT"}, 
        {(u8 )17U, "SDVO_CMD_SET_TARGET_OUTPUT"}, 
        {(u8 )18U, "SDVO_CMD_GET_INPUT_TIMINGS_PART1"}, 
        {(u8 )19U, "SDVO_CMD_GET_INPUT_TIMINGS_PART2"}, 
        {(u8 )20U, "SDVO_CMD_SET_INPUT_TIMINGS_PART1"}, 
        {(u8 )21U, "SDVO_CMD_SET_INPUT_TIMINGS_PART2"}, 
        {(u8 )20U, "SDVO_CMD_SET_INPUT_TIMINGS_PART1"}, 
        {(u8 )22U, "SDVO_CMD_SET_OUTPUT_TIMINGS_PART1"}, 
        {(u8 )23U, "SDVO_CMD_SET_OUTPUT_TIMINGS_PART2"}, 
        {(u8 )24U, "SDVO_CMD_GET_OUTPUT_TIMINGS_PART1"}, 
        {(u8 )25U, "SDVO_CMD_GET_OUTPUT_TIMINGS_PART2"}, 
        {(u8 )26U, "SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING"}, 
        {(u8 )27U, "SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1"}, 
        {(u8 )28U, "SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2"}, 
        {(u8 )29U, "SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE"}, 
        {(u8 )30U, "SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE"}, 
        {(u8 )31U, "SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS"}, 
        {(u8 )32U, "SDVO_CMD_GET_CLOCK_RATE_MULT"}, 
        {(u8 )33U, "SDVO_CMD_SET_CLOCK_RATE_MULT"}, 
        {(u8 )39U, "SDVO_CMD_GET_SUPPORTED_TV_FORMATS"}, 
        {(u8 )40U, "SDVO_CMD_GET_TV_FORMAT"}, 
        {(u8 )41U, "SDVO_CMD_SET_TV_FORMAT"}, 
        {(u8 )42U, "SDVO_CMD_GET_SUPPORTED_POWER_STATES"}, 
        {(u8 )43U, "SDVO_CMD_GET_POWER_STATE"}, 
        {(u8 )44U, "SDVO_CMD_SET_ENCODER_POWER_STATE"}, 
        {(u8 )125U, "SDVO_CMD_SET_DISPLAY_POWER_STATE"}, 
        {(u8 )122U, "SDVO_CMD_SET_CONTROL_BUS_SWITCH"}, 
        {(u8 )131U, "SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT"}, 
        {(u8 )133U, "SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT"}, 
        {(u8 )132U, "SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS"}, 
        {(u8 )103U, "SDVO_CMD_GET_MAX_HPOS"}, 
        {(u8 )104U, "SDVO_CMD_GET_HPOS"}, 
        {(u8 )105U, "SDVO_CMD_SET_HPOS"}, 
        {(u8 )106U, "SDVO_CMD_GET_MAX_VPOS"}, 
        {(u8 )107U, "SDVO_CMD_GET_VPOS"}, 
        {(u8 )108U, "SDVO_CMD_SET_VPOS"}, 
        {(u8 )85U, "SDVO_CMD_GET_MAX_SATURATION"}, 
        {(u8 )86U, "SDVO_CMD_GET_SATURATION"}, 
        {(u8 )87U, "SDVO_CMD_SET_SATURATION"}, 
        {(u8 )88U, "SDVO_CMD_GET_MAX_HUE"}, 
        {(u8 )89U, "SDVO_CMD_GET_HUE"}, 
        {(u8 )90U, "SDVO_CMD_SET_HUE"}, 
        {(u8 )94U, "SDVO_CMD_GET_MAX_CONTRAST"}, 
        {(u8 )95U, "SDVO_CMD_GET_CONTRAST"}, 
        {(u8 )96U, "SDVO_CMD_SET_CONTRAST"}, 
        {(u8 )91U, "SDVO_CMD_GET_MAX_BRIGHTNESS"}, 
        {(u8 )92U, "SDVO_CMD_GET_BRIGHTNESS"}, 
        {(u8 )93U, "SDVO_CMD_SET_BRIGHTNESS"}, 
        {(u8 )97U, "SDVO_CMD_GET_MAX_OVERSCAN_H"}, 
        {(u8 )98U, "SDVO_CMD_GET_OVERSCAN_H"}, 
        {(u8 )99U, "SDVO_CMD_SET_OVERSCAN_H"}, 
        {(u8 )100U, "SDVO_CMD_GET_MAX_OVERSCAN_V"}, 
        {(u8 )101U, "SDVO_CMD_GET_OVERSCAN_V"}, 
        {(u8 )102U, "SDVO_CMD_SET_OVERSCAN_V"}, 
        {(u8 )77U, "SDVO_CMD_GET_MAX_FLICKER_FILTER"}, 
        {(u8 )78U, "SDVO_CMD_GET_FLICKER_FILTER"}, 
        {(u8 )79U, "SDVO_CMD_SET_FLICKER_FILTER"}, 
        {(u8 )123U, "SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE"}, 
        {(u8 )80U, "SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE"}, 
        {(u8 )81U, "SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE"}, 
        {(u8 )82U, "SDVO_CMD_GET_MAX_FLICKER_FILTER_2D"}, 
        {(u8 )83U, "SDVO_CMD_GET_FLICKER_FILTER_2D"}, 
        {(u8 )84U, "SDVO_CMD_SET_FLICKER_FILTER_2D"}, 
        {(u8 )109U, "SDVO_CMD_GET_MAX_SHARPNESS"}, 
        {(u8 )110U, "SDVO_CMD_GET_SHARPNESS"}, 
        {(u8 )111U, "SDVO_CMD_SET_SHARPNESS"}, 
        {(u8 )112U, "SDVO_CMD_GET_DOT_CRAWL"}, 
        {(u8 )113U, "SDVO_CMD_SET_DOT_CRAWL"}, 
        {(u8 )116U, "SDVO_CMD_GET_MAX_TV_CHROMA_FILTER"}, 
        {(u8 )117U, "SDVO_CMD_GET_TV_CHROMA_FILTER"}, 
        {(u8 )118U, "SDVO_CMD_SET_TV_CHROMA_FILTER"}, 
        {(u8 )119U, "SDVO_CMD_GET_MAX_TV_LUMA_FILTER"}, 
        {(u8 )120U, "SDVO_CMD_GET_TV_LUMA_FILTER"}, 
        {(u8 )121U, "SDVO_CMD_SET_TV_LUMA_FILTER"}, 
        {(u8 )157U, "SDVO_CMD_GET_SUPP_ENCODE"}, 
        {(u8 )158U, "SDVO_CMD_GET_ENCODE"}, 
        {(u8 )159U, "SDVO_CMD_SET_ENCODE"}, 
        {(u8 )139U, "SDVO_CMD_SET_PIXEL_REPLI"}, 
        {(u8 )140U, "SDVO_CMD_GET_PIXEL_REPLI"}, 
        {(u8 )141U, "SDVO_CMD_GET_COLORIMETRY_CAP"}, 
        {(u8 )142U, "SDVO_CMD_SET_COLORIMETRY"}, 
        {(u8 )143U, "SDVO_CMD_GET_COLORIMETRY"}, 
        {(u8 )144U, "SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER"}, 
        {(u8 )145U, "SDVO_CMD_SET_AUDIO_STAT"}, 
        {(u8 )146U, "SDVO_CMD_GET_AUDIO_STAT"}, 
        {(u8 )148U, "SDVO_CMD_GET_HBUF_INDEX"}, 
        {(u8 )147U, "SDVO_CMD_SET_HBUF_INDEX"}, 
        {(u8 )149U, "SDVO_CMD_GET_HBUF_INFO"}, 
        {(u8 )151U, "SDVO_CMD_GET_HBUF_AV_SPLIT"}, 
        {(u8 )150U, "SDVO_CMD_SET_HBUF_AV_SPLIT"}, 
        {(u8 )155U, "SDVO_CMD_GET_HBUF_TXRATE"}, 
        {(u8 )154U, "SDVO_CMD_SET_HBUF_TXRATE"}, 
        {(u8 )152U, "SDVO_CMD_SET_HBUF_DATA"}, 
        {(u8 )153U, "SDVO_CMD_GET_HBUF_DATA"}};
#line 410 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo , u8 cmd , void const   *args ,
                                   int args_len ) 
{ int i ;
  char *tmp ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  char const   *__cil_tmp10 ;
  char const   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  u8 *__cil_tmp13 ;
  u8 *__cil_tmp14 ;
  u8 __cil_tmp15 ;
  int __cil_tmp16 ;
  char const   *__cil_tmp17 ;
  char const   *__cil_tmp18 ;
  int __cil_tmp19 ;
  unsigned char __cil_tmp20 ;
  int __cil_tmp21 ;
  char const   *__cil_tmp22 ;
  char const   *__cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  char const   *__cil_tmp25 ;
  char const   *__cil_tmp26 ;
  int __cil_tmp27 ;
  char const   *__cil_tmp28 ;
  char const   *__cil_tmp29 ;

  {
  {
#line 415
  __cil_tmp7 = intel_sdvo->sdvo_reg;
#line 415
  if (__cil_tmp7 == 397632) {
#line 415
    tmp = (char *)"SDVOB";
  } else {
    {
#line 415
    __cil_tmp8 = intel_sdvo->sdvo_reg;
#line 415
    if (__cil_tmp8 == 921920) {
#line 415
      tmp = (char *)"SDVOB";
    } else {
#line 415
      tmp = (char *)"SDVOC";
    }
    }
  }
  }
  {
#line 415
  __cil_tmp9 = (int )cmd;
#line 415
  drm_ut_debug_printk(4U, "drm", "intel_sdvo_debug_write", "%s: W: %02X ", tmp, __cil_tmp9);
#line 417
  i = 0;
  }
#line 417
  goto ldv_38051;
  ldv_38050: 
  {
#line 418
  __cil_tmp10 = (char const   *)0;
#line 418
  __cil_tmp11 = (char const   *)0;
#line 418
  __cil_tmp12 = (unsigned long )i;
#line 418
  __cil_tmp13 = (u8 *)args;
#line 418
  __cil_tmp14 = __cil_tmp13 + __cil_tmp12;
#line 418
  __cil_tmp15 = *__cil_tmp14;
#line 418
  __cil_tmp16 = (int )__cil_tmp15;
#line 418
  drm_ut_debug_printk(4U, __cil_tmp10, __cil_tmp11, "%02X ", __cil_tmp16);
#line 417
  i = i + 1;
  }
  ldv_38051: ;
#line 417
  if (i < args_len) {
#line 418
    goto ldv_38050;
  } else {
#line 420
    goto ldv_38052;
  }
  ldv_38052: ;
#line 419
  goto ldv_38054;
  ldv_38053: 
  {
#line 420
  __cil_tmp17 = (char const   *)0;
#line 420
  __cil_tmp18 = (char const   *)0;
#line 420
  drm_ut_debug_printk(4U, __cil_tmp17, __cil_tmp18, "   ");
#line 419
  i = i + 1;
  }
  ldv_38054: ;
#line 419
  if (i <= 7) {
#line 420
    goto ldv_38053;
  } else {
#line 422
    goto ldv_38055;
  }
  ldv_38055: 
#line 421
  i = 0;
#line 421
  goto ldv_38060;
  ldv_38059: ;
  {
#line 422
  __cil_tmp19 = (int )cmd;
#line 422
  __cil_tmp20 = (unsigned char )sdvo_cmd_names[i].cmd;
#line 422
  __cil_tmp21 = (int )__cil_tmp20;
#line 422
  if (__cil_tmp21 == __cil_tmp19) {
    {
#line 423
    __cil_tmp22 = (char const   *)0;
#line 423
    __cil_tmp23 = (char const   *)0;
#line 423
    drm_ut_debug_printk(4U, __cil_tmp22, __cil_tmp23, "(%s)", sdvo_cmd_names[i].name);
    }
#line 424
    goto ldv_38058;
  } else {

  }
  }
#line 421
  i = i + 1;
  ldv_38060: ;
  {
#line 421
  __cil_tmp24 = (unsigned int )i;
#line 421
  if (__cil_tmp24 <= 106U) {
#line 422
    goto ldv_38059;
  } else {
#line 424
    goto ldv_38058;
  }
  }
  ldv_38058: ;
#line 427
  if (i == 107) {
    {
#line 428
    __cil_tmp25 = (char const   *)0;
#line 428
    __cil_tmp26 = (char const   *)0;
#line 428
    __cil_tmp27 = (int )cmd;
#line 428
    drm_ut_debug_printk(4U, __cil_tmp25, __cil_tmp26, "(%02X)", __cil_tmp27);
    }
  } else {

  }
  {
#line 429
  __cil_tmp28 = (char const   *)0;
#line 429
  __cil_tmp29 = (char const   *)0;
#line 429
  drm_ut_debug_printk(4U, __cil_tmp28, __cil_tmp29, "\n");
  }
#line 430
  return;
}
}
#line 432 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static char const   *cmd_status_names[7U]  = {      "Power on",      "Success",      "Not supported",      "Invalid arg", 
        "Pending",      "Target not specified",      "Scaling not supported"};
#line 442 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo , u8 cmd , void const   *args ,
                                 int args_len ) 
{ u8 *buf ;
  unsigned long __lengthofbuf ;
  void *tmp ;
  u8 status ;
  struct i2c_msg *msgs ;
  unsigned long __lengthofmsgs ;
  void *tmp___0 ;
  int i ;
  int ret ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  long __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  int __cil_tmp18 ;
  long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  int __cil_tmp21 ;
  u8 __cil_tmp22 ;
  struct i2c_msg *__cil_tmp23 ;
  u8 __cil_tmp24 ;
  struct i2c_msg *__cil_tmp25 ;
  struct i2c_msg *__cil_tmp26 ;
  struct i2c_msg *__cil_tmp27 ;
  int __cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  __u8 *__cil_tmp30 ;
  int __cil_tmp31 ;
  u8 *__cil_tmp32 ;
  u8 __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  u8 *__cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  u8 *__cil_tmp40 ;
  u8 *__cil_tmp41 ;
  struct i2c_msg *__cil_tmp42 ;
  u8 __cil_tmp43 ;
  struct i2c_msg *__cil_tmp44 ;
  struct i2c_msg *__cil_tmp45 ;
  struct i2c_msg *__cil_tmp46 ;
  int __cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  __u8 *__cil_tmp49 ;
  int __cil_tmp50 ;
  u8 *__cil_tmp51 ;
  int __cil_tmp52 ;
  int __cil_tmp53 ;
  u8 *__cil_tmp54 ;
  int __cil_tmp55 ;
  struct i2c_msg *__cil_tmp56 ;
  u8 __cil_tmp57 ;
  int __cil_tmp58 ;
  struct i2c_msg *__cil_tmp59 ;
  int __cil_tmp60 ;
  struct i2c_msg *__cil_tmp61 ;
  int __cil_tmp62 ;
  struct i2c_msg *__cil_tmp63 ;
  int __cil_tmp64 ;
  struct i2c_msg *__cil_tmp65 ;
  u8 __cil_tmp66 ;
  int __cil_tmp67 ;
  struct i2c_msg *__cil_tmp68 ;
  int __cil_tmp69 ;
  struct i2c_msg *__cil_tmp70 ;
  int __cil_tmp71 ;
  struct i2c_msg *__cil_tmp72 ;
  struct i2c_adapter *__cil_tmp73 ;
  struct i2c_msg *__cil_tmp74 ;
  int __cil_tmp75 ;
  int __cil_tmp76 ;
  int __cil_tmp77 ;

  {
  {
#line 445
  __cil_tmp14 = args_len + 1;
#line 445
  __cil_tmp15 = __cil_tmp14 * 2;
#line 445
  __cil_tmp16 = (long )__cil_tmp15;
#line 445
  __lengthofbuf = (unsigned long )__cil_tmp16;
#line 445
  __cil_tmp17 = 1UL * __lengthofbuf;
#line 445
  tmp = __builtin_alloca(__cil_tmp17);
#line 445
  buf = (u8 *)tmp;
#line 446
  __cil_tmp18 = args_len + 3;
#line 446
  __cil_tmp19 = (long )__cil_tmp18;
#line 446
  __lengthofmsgs = (unsigned long )__cil_tmp19;
#line 446
  __cil_tmp20 = 16UL * __lengthofmsgs;
#line 446
  tmp___0 = __builtin_alloca(__cil_tmp20);
#line 446
  msgs = (struct i2c_msg *)tmp___0;
#line 449
  __cil_tmp21 = (int )cmd;
#line 449
  __cil_tmp22 = (u8 )__cil_tmp21;
#line 449
  intel_sdvo_debug_write(intel_sdvo, __cil_tmp22, args, args_len);
#line 451
  i = 0;
  }
#line 451
  goto ldv_38076;
  ldv_38075: 
#line 452
  __cil_tmp23 = msgs + i;
#line 452
  __cil_tmp24 = intel_sdvo->slave_addr;
#line 452
  __cil_tmp23->addr = (__u16 )__cil_tmp24;
#line 453
  __cil_tmp25 = msgs + i;
#line 453
  __cil_tmp25->flags = (__u16 )0U;
#line 454
  __cil_tmp26 = msgs + i;
#line 454
  __cil_tmp26->len = (__u16 )2U;
#line 455
  __cil_tmp27 = msgs + i;
#line 455
  __cil_tmp28 = i * 2;
#line 455
  __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 455
  __cil_tmp30 = (__u8 *)(& buf);
#line 455
  __cil_tmp27->buf = __cil_tmp30 + __cil_tmp29;
#line 456
  __cil_tmp31 = i * 2;
#line 456
  __cil_tmp32 = buf + __cil_tmp31;
#line 456
  __cil_tmp33 = (u8 )i;
#line 456
  __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 456
  __cil_tmp35 = 7U - __cil_tmp34;
#line 456
  *__cil_tmp32 = (u8 )__cil_tmp35;
#line 457
  __cil_tmp36 = i * 2;
#line 457
  __cil_tmp37 = __cil_tmp36 + 1;
#line 457
  __cil_tmp38 = buf + __cil_tmp37;
#line 457
  __cil_tmp39 = (unsigned long )i;
#line 457
  __cil_tmp40 = (u8 *)args;
#line 457
  __cil_tmp41 = __cil_tmp40 + __cil_tmp39;
#line 457
  *__cil_tmp38 = *__cil_tmp41;
#line 451
  i = i + 1;
  ldv_38076: ;
#line 451
  if (i < args_len) {
#line 452
    goto ldv_38075;
  } else {
#line 454
    goto ldv_38077;
  }
  ldv_38077: 
  {
#line 459
  __cil_tmp42 = msgs + i;
#line 459
  __cil_tmp43 = intel_sdvo->slave_addr;
#line 459
  __cil_tmp42->addr = (__u16 )__cil_tmp43;
#line 460
  __cil_tmp44 = msgs + i;
#line 460
  __cil_tmp44->flags = (__u16 )0U;
#line 461
  __cil_tmp45 = msgs + i;
#line 461
  __cil_tmp45->len = (__u16 )2U;
#line 462
  __cil_tmp46 = msgs + i;
#line 462
  __cil_tmp47 = i * 2;
#line 462
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 462
  __cil_tmp49 = (__u8 *)(& buf);
#line 462
  __cil_tmp46->buf = __cil_tmp49 + __cil_tmp48;
#line 463
  __cil_tmp50 = i * 2;
#line 463
  __cil_tmp51 = buf + __cil_tmp50;
#line 463
  *__cil_tmp51 = (u8 )8U;
#line 464
  __cil_tmp52 = i * 2;
#line 464
  __cil_tmp53 = __cil_tmp52 + 1;
#line 464
  __cil_tmp54 = buf + __cil_tmp53;
#line 464
  *__cil_tmp54 = cmd;
#line 467
  status = (u8 )9U;
#line 468
  __cil_tmp55 = i + 1;
#line 468
  __cil_tmp56 = msgs + __cil_tmp55;
#line 468
  __cil_tmp57 = intel_sdvo->slave_addr;
#line 468
  __cil_tmp56->addr = (__u16 )__cil_tmp57;
#line 469
  __cil_tmp58 = i + 1;
#line 469
  __cil_tmp59 = msgs + __cil_tmp58;
#line 469
  __cil_tmp59->flags = (__u16 )0U;
#line 470
  __cil_tmp60 = i + 1;
#line 470
  __cil_tmp61 = msgs + __cil_tmp60;
#line 470
  __cil_tmp61->len = (__u16 )1U;
#line 471
  __cil_tmp62 = i + 1;
#line 471
  __cil_tmp63 = msgs + __cil_tmp62;
#line 471
  __cil_tmp63->buf = & status;
#line 473
  __cil_tmp64 = i + 2;
#line 473
  __cil_tmp65 = msgs + __cil_tmp64;
#line 473
  __cil_tmp66 = intel_sdvo->slave_addr;
#line 473
  __cil_tmp65->addr = (__u16 )__cil_tmp66;
#line 474
  __cil_tmp67 = i + 2;
#line 474
  __cil_tmp68 = msgs + __cil_tmp67;
#line 474
  __cil_tmp68->flags = (__u16 )1U;
#line 475
  __cil_tmp69 = i + 2;
#line 475
  __cil_tmp70 = msgs + __cil_tmp69;
#line 475
  __cil_tmp70->len = (__u16 )1U;
#line 476
  __cil_tmp71 = i + 2;
#line 476
  __cil_tmp72 = msgs + __cil_tmp71;
#line 476
  __cil_tmp72->buf = & status;
#line 478
  __cil_tmp73 = intel_sdvo->i2c;
#line 478
  __cil_tmp74 = (struct i2c_msg *)(& msgs);
#line 478
  __cil_tmp75 = i + 3;
#line 478
  ret = i2c_transfer(__cil_tmp73, __cil_tmp74, __cil_tmp75);
  }
#line 479
  if (ret < 0) {
    {
#line 480
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_write_cmd", "I2c transfer returned %d\n",
                        ret);
    }
#line 481
    return ((bool )0);
  } else {

  }
  {
#line 483
  __cil_tmp76 = i + 3;
#line 483
  if (__cil_tmp76 != ret) {
    {
#line 485
    __cil_tmp77 = i + 3;
#line 485
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_write_cmd", "I2c transfer returned %d/%d\n",
                        ret, __cil_tmp77);
    }
#line 486
    return ((bool )0);
  } else {

  }
  }
#line 489
  return ((bool )1);
}
}
#line 492 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo , void *response ,
                                     int response_len ) 
{ u8 retry ;
  u8 status ;
  int i ;
  char *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  u8 tmp___4 ;
  bool tmp___5 ;
  int tmp___6 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  u8 __cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  char const   *__cil_tmp24 ;
  char const   *__cil_tmp25 ;
  char const   *__cil_tmp26 ;
  char const   *__cil_tmp27 ;
  int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  u8 __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  int __cil_tmp33 ;
  u8 __cil_tmp34 ;
  unsigned long __cil_tmp35 ;
  u8 *__cil_tmp36 ;
  u8 *__cil_tmp37 ;
  char const   *__cil_tmp38 ;
  char const   *__cil_tmp39 ;
  unsigned long __cil_tmp40 ;
  u8 *__cil_tmp41 ;
  u8 *__cil_tmp42 ;
  u8 __cil_tmp43 ;
  int __cil_tmp44 ;
  char const   *__cil_tmp45 ;
  char const   *__cil_tmp46 ;
  char const   *__cil_tmp47 ;
  char const   *__cil_tmp48 ;

  {
#line 495
  retry = (u8 )5U;
  {
#line 499
  __cil_tmp15 = intel_sdvo->sdvo_reg;
#line 499
  if (__cil_tmp15 == 397632) {
#line 499
    tmp = (char *)"SDVOB";
  } else {
    {
#line 499
    __cil_tmp16 = intel_sdvo->sdvo_reg;
#line 499
    if (__cil_tmp16 == 921920) {
#line 499
      tmp = (char *)"SDVOB";
    } else {
#line 499
      tmp = (char *)"SDVOC";
    }
    }
  }
  }
  {
#line 499
  drm_ut_debug_printk(4U, "drm", "intel_sdvo_read_response", "%s: R: ", tmp);
#line 509
  __cil_tmp17 = (u8 )9;
#line 509
  tmp___0 = intel_sdvo_read_byte(intel_sdvo, __cil_tmp17, & status);
  }
#line 509
  if (tmp___0) {
#line 509
    tmp___1 = 0;
  } else {
#line 509
    tmp___1 = 1;
  }
#line 509
  if (tmp___1) {
#line 512
    goto log_fail;
  } else {

  }
#line 514
  goto ldv_38090;
  ldv_38089: 
  {
#line 515
  __const_udelay(64425UL);
#line 516
  __cil_tmp18 = (u8 )9;
#line 516
  tmp___2 = intel_sdvo_read_byte(intel_sdvo, __cil_tmp18, & status);
  }
#line 516
  if (tmp___2) {
#line 516
    tmp___3 = 0;
  } else {
#line 516
    tmp___3 = 1;
  }
#line 516
  if (tmp___3) {
#line 519
    goto log_fail;
  } else {

  }
  ldv_38090: ;
  {
#line 514
  __cil_tmp19 = (unsigned int )status;
#line 514
  if (__cil_tmp19 == 4U) {
#line 514
    tmp___4 = retry;
#line 514
    __cil_tmp20 = (int )retry;
#line 514
    __cil_tmp21 = __cil_tmp20 - 1;
#line 514
    retry = (u8 )__cil_tmp21;
    {
#line 514
    __cil_tmp22 = (unsigned int )tmp___4;
#line 514
    if (__cil_tmp22 != 0U) {
#line 515
      goto ldv_38089;
    } else {
#line 517
      goto ldv_38091;
    }
    }
  } else {
#line 517
    goto ldv_38091;
  }
  }
  ldv_38091: ;
  {
#line 522
  __cil_tmp23 = (unsigned int )status;
#line 522
  if (__cil_tmp23 <= 6U) {
    {
#line 523
    __cil_tmp24 = (char const   *)0;
#line 523
    __cil_tmp25 = (char const   *)0;
#line 523
    drm_ut_debug_printk(4U, __cil_tmp24, __cil_tmp25, "(%s)", cmd_status_names[(int )status]);
    }
  } else {
    {
#line 525
    __cil_tmp26 = (char const   *)0;
#line 525
    __cil_tmp27 = (char const   *)0;
#line 525
    __cil_tmp28 = (int )status;
#line 525
    drm_ut_debug_printk(4U, __cil_tmp26, __cil_tmp27, "(??? %d)", __cil_tmp28);
    }
  }
  }
  {
#line 527
  __cil_tmp29 = (unsigned int )status;
#line 527
  if (__cil_tmp29 != 1U) {
#line 528
    goto log_fail;
  } else {

  }
  }
#line 531
  i = 0;
#line 531
  goto ldv_38093;
  ldv_38092: 
  {
#line 532
  __cil_tmp30 = (u8 )i;
#line 532
  __cil_tmp31 = (unsigned int )__cil_tmp30;
#line 532
  __cil_tmp32 = __cil_tmp31 + 10U;
#line 532
  __cil_tmp33 = (int )__cil_tmp32;
#line 532
  __cil_tmp34 = (u8 )__cil_tmp33;
#line 532
  __cil_tmp35 = (unsigned long )i;
#line 532
  __cil_tmp36 = (u8 *)response;
#line 532
  __cil_tmp37 = __cil_tmp36 + __cil_tmp35;
#line 532
  tmp___5 = intel_sdvo_read_byte(intel_sdvo, __cil_tmp34, __cil_tmp37);
  }
#line 532
  if (tmp___5) {
#line 532
    tmp___6 = 0;
  } else {
#line 532
    tmp___6 = 1;
  }
#line 532
  if (tmp___6) {
#line 535
    goto log_fail;
  } else {

  }
  {
#line 536
  __cil_tmp38 = (char const   *)0;
#line 536
  __cil_tmp39 = (char const   *)0;
#line 536
  __cil_tmp40 = (unsigned long )i;
#line 536
  __cil_tmp41 = (u8 *)response;
#line 536
  __cil_tmp42 = __cil_tmp41 + __cil_tmp40;
#line 536
  __cil_tmp43 = *__cil_tmp42;
#line 536
  __cil_tmp44 = (int )__cil_tmp43;
#line 536
  drm_ut_debug_printk(4U, __cil_tmp38, __cil_tmp39, " %02X", __cil_tmp44);
#line 531
  i = i + 1;
  }
  ldv_38093: ;
#line 531
  if (i < response_len) {
#line 532
    goto ldv_38092;
  } else {
#line 534
    goto ldv_38094;
  }
  ldv_38094: 
  {
#line 538
  __cil_tmp45 = (char const   *)0;
#line 538
  __cil_tmp46 = (char const   *)0;
#line 538
  drm_ut_debug_printk(4U, __cil_tmp45, __cil_tmp46, "\n");
  }
#line 539
  return ((bool )1);
  log_fail: 
  {
#line 542
  __cil_tmp47 = (char const   *)0;
#line 542
  __cil_tmp48 = (char const   *)0;
#line 542
  drm_ut_debug_printk(4U, __cil_tmp47, __cil_tmp48, "... failed\n");
  }
#line 543
  return ((bool )0);
}
}
#line 546 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode ) 
{ int __cil_tmp2 ;
  int __cil_tmp3 ;

  {
  {
#line 548
  __cil_tmp2 = mode->clock;
#line 548
  if (__cil_tmp2 > 99999) {
#line 549
    return (1);
  } else {
    {
#line 550
    __cil_tmp3 = mode->clock;
#line 550
    if (__cil_tmp3 > 49999) {
#line 551
      return (2);
    } else {
#line 553
      return (4);
    }
    }
  }
  }
}
}
#line 556 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo , u8 ddc_bus ) 
{ bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 560
  __cil_tmp4 = (u8 )122;
#line 560
  __cil_tmp5 = (void const   *)(& ddc_bus);
#line 560
  tmp = intel_sdvo_write_cmd(intel_sdvo, __cil_tmp4, __cil_tmp5, 1);
  }
#line 560
  return (tmp);
}
}
#line 565 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo , u8 cmd , void const   *data ,
                                 int len ) 
{ bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int __cil_tmp8 ;
  u8 __cil_tmp9 ;
  void *__cil_tmp10 ;

  {
  {
#line 567
  __cil_tmp8 = (int )cmd;
#line 567
  __cil_tmp9 = (u8 )__cil_tmp8;
#line 567
  tmp = intel_sdvo_write_cmd(intel_sdvo, __cil_tmp9, data, len);
  }
#line 567
  if (tmp) {
#line 567
    tmp___0 = 0;
  } else {
#line 567
    tmp___0 = 1;
  }
#line 567
  if (tmp___0) {
#line 568
    return ((bool )0);
  } else {

  }
  {
#line 570
  __cil_tmp10 = (void *)0;
#line 570
  tmp___1 = intel_sdvo_read_response(intel_sdvo, __cil_tmp10, 0);
  }
#line 570
  return (tmp___1);
}
}
#line 574 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_get_value(struct intel_sdvo *intel_sdvo , u8 cmd , void *value ,
                                 int len ) 
{ bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int __cil_tmp8 ;
  u8 __cil_tmp9 ;
  void const   *__cil_tmp10 ;

  {
  {
#line 576
  __cil_tmp8 = (int )cmd;
#line 576
  __cil_tmp9 = (u8 )__cil_tmp8;
#line 576
  __cil_tmp10 = (void const   *)0;
#line 576
  tmp = intel_sdvo_write_cmd(intel_sdvo, __cil_tmp9, __cil_tmp10, 0);
  }
#line 576
  if (tmp) {
#line 576
    tmp___0 = 0;
  } else {
#line 576
    tmp___0 = 1;
  }
#line 576
  if (tmp___0) {
#line 577
    return ((bool )0);
  } else {

  }
  {
#line 579
  tmp___1 = intel_sdvo_read_response(intel_sdvo, value, len);
  }
#line 579
  return (tmp___1);
}
}
#line 582 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo ) 
{ struct intel_sdvo_set_target_input_args targets ;
  bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 584
  targets.target_1 = (unsigned char)0;
#line 584
  targets.pad = (unsigned char)0;
#line 585
  __cil_tmp4 = (u8 )16;
#line 585
  __cil_tmp5 = (void const   *)(& targets);
#line 585
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 1);
  }
#line 585
  return (tmp);
}
}
#line 596 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo , bool *input_1 ,
                                          bool *input_2 ) 
{ struct intel_sdvo_get_trained_inputs_response response ;
  bool tmp ;
  int tmp___0 ;
  u8 __cil_tmp7 ;
  void *__cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;

  {
  {
#line 601
  __cil_tmp7 = (u8 )3;
#line 601
  __cil_tmp8 = (void *)(& response);
#line 601
  tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp7, __cil_tmp8, 1);
  }
#line 601
  if (tmp) {
#line 601
    tmp___0 = 0;
  } else {
#line 601
    tmp___0 = 1;
  }
#line 601
  if (tmp___0) {
#line 603
    return ((bool )0);
  } else {

  }
#line 605
  __cil_tmp9 = (int )response.input0_trained;
#line 605
  __cil_tmp10 = __cil_tmp9 != 0;
#line 605
  *input_1 = (bool )__cil_tmp10;
#line 606
  __cil_tmp11 = (int )response.input1_trained;
#line 606
  __cil_tmp12 = __cil_tmp11 != 0;
#line 606
  *input_2 = (bool )__cil_tmp12;
#line 607
  return ((bool )1);
}
}
#line 610 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo , u16 outputs ) 
{ bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 613
  __cil_tmp4 = (u8 )5;
#line 613
  __cil_tmp5 = (void const   *)(& outputs);
#line 613
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 2);
  }
#line 613
  return (tmp);
}
}
#line 642 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo ,
                                                   int *clock_min , int *clock_max ) 
{ struct intel_sdvo_pixel_clock_range clocks ;
  bool tmp ;
  int tmp___0 ;
  u8 __cil_tmp7 ;
  void *__cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;

  {
  {
#line 649
  __cil_tmp7 = (u8 )29;
#line 649
  __cil_tmp8 = (void *)(& clocks);
#line 649
  tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp7, __cil_tmp8, 4);
  }
#line 649
  if (tmp) {
#line 649
    tmp___0 = 0;
  } else {
#line 649
    tmp___0 = 1;
  }
#line 649
  if (tmp___0) {
#line 652
    return ((bool )0);
  } else {

  }
#line 655
  __cil_tmp9 = (int )clocks.min;
#line 655
  *clock_min = __cil_tmp9 * 10;
#line 656
  __cil_tmp10 = (int )clocks.max;
#line 656
  *clock_max = __cil_tmp10 * 10;
#line 657
  return ((bool )1);
}
}
#line 660 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo , u16 outputs ) 
{ bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 663
  __cil_tmp4 = (u8 )17;
#line 663
  __cil_tmp5 = (void const   *)(& outputs);
#line 663
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 2);
  }
#line 663
  return (tmp);
}
}
#line 668 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo , u8 cmd , struct intel_sdvo_dtd *dtd ) 
{ bool tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  int __cil_tmp7 ;
  u8 __cil_tmp8 ;
  struct __anonstruct_part1_191 *__cil_tmp9 ;
  void const   *__cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  int __cil_tmp13 ;
  u8 __cil_tmp14 ;
  struct __anonstruct_part2_192 *__cil_tmp15 ;
  void const   *__cil_tmp16 ;

  {
  {
#line 671
  __cil_tmp7 = (int )cmd;
#line 671
  __cil_tmp8 = (u8 )__cil_tmp7;
#line 671
  __cil_tmp9 = & dtd->part1;
#line 671
  __cil_tmp10 = (void const   *)__cil_tmp9;
#line 671
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp8, __cil_tmp10, 8);
  }
#line 671
  if ((int )tmp) {
    {
#line 671
    __cil_tmp11 = (unsigned int )cmd;
#line 671
    __cil_tmp12 = __cil_tmp11 + 1U;
#line 671
    __cil_tmp13 = (int )__cil_tmp12;
#line 671
    __cil_tmp14 = (u8 )__cil_tmp13;
#line 671
    __cil_tmp15 = & dtd->part2;
#line 671
    __cil_tmp16 = (void const   *)__cil_tmp15;
#line 671
    tmp___0 = intel_sdvo_set_value(intel_sdvo, __cil_tmp14, __cil_tmp16, 8);
    }
#line 671
    if ((int )tmp___0) {
#line 671
      tmp___1 = 1;
    } else {
#line 671
      tmp___1 = 0;
    }
  } else {
#line 671
    tmp___1 = 0;
  }
#line 671
  return ((bool )tmp___1);
}
}
#line 675 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo , struct intel_sdvo_dtd *dtd ) 
{ bool tmp ;
  u8 __cil_tmp4 ;

  {
  {
#line 678
  __cil_tmp4 = (u8 )20;
#line 678
  tmp = intel_sdvo_set_timing(intel_sdvo, __cil_tmp4, dtd);
  }
#line 678
  return (tmp);
}
}
#line 682 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo , struct intel_sdvo_dtd *dtd ) 
{ bool tmp ;
  u8 __cil_tmp4 ;

  {
  {
#line 685
  __cil_tmp4 = (u8 )22;
#line 685
  tmp = intel_sdvo_set_timing(intel_sdvo, __cil_tmp4, dtd);
  }
#line 685
  return (tmp);
}
}
#line 690 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo ,
                                                     uint16_t clock , uint16_t width ,
                                                     uint16_t height ) 
{ struct intel_sdvo_preferred_input_timing_args args ;
  bool tmp ;
  void *__cil_tmp7 ;
  bool __cil_tmp8 ;
  int __cil_tmp9 ;
  struct drm_display_mode *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  struct drm_display_mode *__cil_tmp13 ;
  int __cil_tmp14 ;
  u8 __cil_tmp15 ;
  void const   *__cil_tmp16 ;

  {
  {
#line 697
  __cil_tmp7 = (void *)(& args);
#line 697
  memset(__cil_tmp7, 0, 7UL);
#line 698
  args.clock = clock;
#line 699
  args.width = width;
#line 700
  args.height = height;
#line 701
  args.interlace = (unsigned char)0;
  }
  {
#line 703
  __cil_tmp8 = intel_sdvo->is_lvds;
#line 703
  if ((int )__cil_tmp8) {
    {
#line 703
    __cil_tmp9 = (int )width;
#line 703
    __cil_tmp10 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 703
    __cil_tmp11 = __cil_tmp10->hdisplay;
#line 703
    if (__cil_tmp11 != __cil_tmp9) {
#line 706
      args.scaled = (unsigned char)1;
    } else {
      {
#line 703
      __cil_tmp12 = (int )height;
#line 703
      __cil_tmp13 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 703
      __cil_tmp14 = __cil_tmp13->vdisplay;
#line 703
      if (__cil_tmp14 != __cil_tmp12) {
#line 706
        args.scaled = (unsigned char)1;
      } else {

      }
      }
    }
    }
  } else {

  }
  }
  {
#line 708
  __cil_tmp15 = (u8 )26;
#line 708
  __cil_tmp16 = (void const   *)(& args);
#line 708
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp15, __cil_tmp16, 7);
  }
#line 708
  return (tmp);
}
}
#line 713 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo ,
                                                  struct intel_sdvo_dtd *dtd ) 
{ bool tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  u8 __cil_tmp6 ;
  struct __anonstruct_part1_191 *__cil_tmp7 ;
  void *__cil_tmp8 ;
  u8 __cil_tmp9 ;
  struct __anonstruct_part2_192 *__cil_tmp10 ;
  void *__cil_tmp11 ;

  {
  {
#line 718
  __cil_tmp6 = (u8 )27;
#line 718
  __cil_tmp7 = & dtd->part1;
#line 718
  __cil_tmp8 = (void *)__cil_tmp7;
#line 718
  tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp6, __cil_tmp8, 8);
  }
#line 718
  if ((int )tmp) {
    {
#line 718
    __cil_tmp9 = (u8 )28;
#line 718
    __cil_tmp10 = & dtd->part2;
#line 718
    __cil_tmp11 = (void *)__cil_tmp10;
#line 718
    tmp___0 = intel_sdvo_get_value(intel_sdvo, __cil_tmp9, __cil_tmp11, 8);
    }
#line 718
    if ((int )tmp___0) {
#line 718
      tmp___1 = 1;
    } else {
#line 718
      tmp___1 = 0;
    }
  } else {
#line 718
    tmp___1 = 0;
  }
#line 718
  return ((bool )tmp___1);
}
}
#line 724 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo , u8 val ) 
{ bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 726
  __cil_tmp4 = (u8 )33;
#line 726
  __cil_tmp5 = (void const   *)(& val);
#line 726
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 1);
  }
#line 726
  return (tmp);
}
}
#line 729 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd , struct drm_display_mode  const  *mode ) 
{ uint16_t width ;
  uint16_t height ;
  uint16_t h_blank_len ;
  uint16_t h_sync_len ;
  uint16_t v_blank_len ;
  uint16_t v_sync_len ;
  uint16_t h_sync_offset ;
  uint16_t v_sync_offset ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  uint16_t __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  uint16_t __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  uint16_t __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  uint16_t __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  uint16_t __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  uint16_t __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  uint16_t __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  uint16_t __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  uint16_t __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  uint16_t __cil_tmp45 ;
  int __cil_tmp46 ;
  int __cil_tmp47 ;
  int __cil_tmp48 ;
  uint16_t __cil_tmp49 ;
  int __cil_tmp50 ;
  int __cil_tmp51 ;
  uint16_t __cil_tmp52 ;
  int __cil_tmp53 ;
  int __cil_tmp54 ;
  int __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  int __cil_tmp58 ;
  int __cil_tmp59 ;
  signed char __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;
  int __cil_tmp63 ;
  int __cil_tmp64 ;
  int __cil_tmp65 ;
  signed char __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  int __cil_tmp70 ;
  signed char __cil_tmp71 ;
  int __cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  int __cil_tmp75 ;
  int __cil_tmp76 ;
  signed char __cil_tmp77 ;
  int __cil_tmp78 ;
  int __cil_tmp79 ;
  signed char __cil_tmp80 ;
  int __cil_tmp81 ;
  int __cil_tmp82 ;
  int __cil_tmp83 ;
  int __cil_tmp84 ;
  signed char __cil_tmp85 ;
  int __cil_tmp86 ;
  int __cil_tmp87 ;
  int __cil_tmp88 ;
  int __cil_tmp89 ;
  int __cil_tmp90 ;
  signed char __cil_tmp91 ;
  int __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  int __cil_tmp95 ;
  signed char __cil_tmp96 ;
  int __cil_tmp97 ;
  int __cil_tmp98 ;
  int __cil_tmp99 ;
  int __cil_tmp100 ;
  signed char __cil_tmp101 ;
  int __cil_tmp102 ;
  int __cil_tmp103 ;
  int __cil_tmp104 ;
  int __cil_tmp105 ;
  signed char __cil_tmp106 ;
  int __cil_tmp107 ;
  int __cil_tmp108 ;
  int __cil_tmp109 ;
  int __cil_tmp110 ;
  unsigned int __cil_tmp111 ;
  int __cil_tmp112 ;
  u8 __cil_tmp113 ;
  unsigned int __cil_tmp114 ;
  unsigned int __cil_tmp115 ;
  unsigned int __cil_tmp116 ;
  unsigned int __cil_tmp117 ;
  unsigned int __cil_tmp118 ;
  u8 __cil_tmp119 ;
  unsigned int __cil_tmp120 ;
  unsigned int __cil_tmp121 ;
  u8 __cil_tmp122 ;
  unsigned int __cil_tmp123 ;
  unsigned int __cil_tmp124 ;

  {
#line 736
  __cil_tmp11 = mode->crtc_hdisplay;
#line 736
  width = (uint16_t )__cil_tmp11;
#line 737
  __cil_tmp12 = mode->crtc_vdisplay;
#line 737
  height = (uint16_t )__cil_tmp12;
#line 740
  __cil_tmp13 = mode->crtc_hblank_start;
#line 740
  __cil_tmp14 = (uint16_t )__cil_tmp13;
#line 740
  __cil_tmp15 = (int )__cil_tmp14;
#line 740
  __cil_tmp16 = mode->crtc_hblank_end;
#line 740
  __cil_tmp17 = (uint16_t )__cil_tmp16;
#line 740
  __cil_tmp18 = (int )__cil_tmp17;
#line 740
  __cil_tmp19 = __cil_tmp18 - __cil_tmp15;
#line 740
  h_blank_len = (uint16_t )__cil_tmp19;
#line 741
  __cil_tmp20 = mode->crtc_hsync_start;
#line 741
  __cil_tmp21 = (uint16_t )__cil_tmp20;
#line 741
  __cil_tmp22 = (int )__cil_tmp21;
#line 741
  __cil_tmp23 = mode->crtc_hsync_end;
#line 741
  __cil_tmp24 = (uint16_t )__cil_tmp23;
#line 741
  __cil_tmp25 = (int )__cil_tmp24;
#line 741
  __cil_tmp26 = __cil_tmp25 - __cil_tmp22;
#line 741
  h_sync_len = (uint16_t )__cil_tmp26;
#line 743
  __cil_tmp27 = mode->crtc_vblank_start;
#line 743
  __cil_tmp28 = (uint16_t )__cil_tmp27;
#line 743
  __cil_tmp29 = (int )__cil_tmp28;
#line 743
  __cil_tmp30 = mode->crtc_vblank_end;
#line 743
  __cil_tmp31 = (uint16_t )__cil_tmp30;
#line 743
  __cil_tmp32 = (int )__cil_tmp31;
#line 743
  __cil_tmp33 = __cil_tmp32 - __cil_tmp29;
#line 743
  v_blank_len = (uint16_t )__cil_tmp33;
#line 744
  __cil_tmp34 = mode->crtc_vsync_start;
#line 744
  __cil_tmp35 = (uint16_t )__cil_tmp34;
#line 744
  __cil_tmp36 = (int )__cil_tmp35;
#line 744
  __cil_tmp37 = mode->crtc_vsync_end;
#line 744
  __cil_tmp38 = (uint16_t )__cil_tmp37;
#line 744
  __cil_tmp39 = (int )__cil_tmp38;
#line 744
  __cil_tmp40 = __cil_tmp39 - __cil_tmp36;
#line 744
  v_sync_len = (uint16_t )__cil_tmp40;
#line 746
  __cil_tmp41 = mode->crtc_hblank_start;
#line 746
  __cil_tmp42 = (uint16_t )__cil_tmp41;
#line 746
  __cil_tmp43 = (int )__cil_tmp42;
#line 746
  __cil_tmp44 = mode->crtc_hsync_start;
#line 746
  __cil_tmp45 = (uint16_t )__cil_tmp44;
#line 746
  __cil_tmp46 = (int )__cil_tmp45;
#line 746
  __cil_tmp47 = __cil_tmp46 - __cil_tmp43;
#line 746
  h_sync_offset = (uint16_t )__cil_tmp47;
#line 747
  __cil_tmp48 = mode->crtc_vblank_start;
#line 747
  __cil_tmp49 = (uint16_t )__cil_tmp48;
#line 747
  __cil_tmp50 = (int )__cil_tmp49;
#line 747
  __cil_tmp51 = mode->crtc_vsync_start;
#line 747
  __cil_tmp52 = (uint16_t )__cil_tmp51;
#line 747
  __cil_tmp53 = (int )__cil_tmp52;
#line 747
  __cil_tmp54 = __cil_tmp53 - __cil_tmp50;
#line 747
  v_sync_offset = (uint16_t )__cil_tmp54;
#line 749
  __cil_tmp55 = mode->clock;
#line 749
  __cil_tmp56 = (int )__cil_tmp55;
#line 749
  __cil_tmp57 = __cil_tmp56 / 10;
#line 749
  dtd->part1.clock = (u16 )__cil_tmp57;
#line 750
  dtd->part1.h_active = (u8 )width;
#line 751
  dtd->part1.h_blank = (u8 )h_blank_len;
#line 752
  __cil_tmp58 = (int )h_blank_len;
#line 752
  __cil_tmp59 = __cil_tmp58 >> 8;
#line 752
  __cil_tmp60 = (signed char )__cil_tmp59;
#line 752
  __cil_tmp61 = (int )__cil_tmp60;
#line 752
  __cil_tmp62 = __cil_tmp61 & 15;
#line 752
  __cil_tmp63 = (int )width;
#line 752
  __cil_tmp64 = __cil_tmp63 >> 8;
#line 752
  __cil_tmp65 = __cil_tmp64 << 4;
#line 752
  __cil_tmp66 = (signed char )__cil_tmp65;
#line 752
  __cil_tmp67 = (int )__cil_tmp66;
#line 752
  __cil_tmp68 = __cil_tmp67 | __cil_tmp62;
#line 752
  dtd->part1.h_high = (u8 )__cil_tmp68;
#line 754
  dtd->part1.v_active = (u8 )height;
#line 755
  dtd->part1.v_blank = (u8 )v_blank_len;
#line 756
  __cil_tmp69 = (int )v_blank_len;
#line 756
  __cil_tmp70 = __cil_tmp69 >> 8;
#line 756
  __cil_tmp71 = (signed char )__cil_tmp70;
#line 756
  __cil_tmp72 = (int )__cil_tmp71;
#line 756
  __cil_tmp73 = __cil_tmp72 & 15;
#line 756
  __cil_tmp74 = (int )height;
#line 756
  __cil_tmp75 = __cil_tmp74 >> 8;
#line 756
  __cil_tmp76 = __cil_tmp75 << 4;
#line 756
  __cil_tmp77 = (signed char )__cil_tmp76;
#line 756
  __cil_tmp78 = (int )__cil_tmp77;
#line 756
  __cil_tmp79 = __cil_tmp78 | __cil_tmp73;
#line 756
  dtd->part1.v_high = (u8 )__cil_tmp79;
#line 759
  dtd->part2.h_sync_off = (u8 )h_sync_offset;
#line 760
  dtd->part2.h_sync_width = (u8 )h_sync_len;
#line 761
  __cil_tmp80 = (signed char )v_sync_len;
#line 761
  __cil_tmp81 = (int )__cil_tmp80;
#line 761
  __cil_tmp82 = __cil_tmp81 & 15;
#line 761
  __cil_tmp83 = (int )v_sync_offset;
#line 761
  __cil_tmp84 = __cil_tmp83 << 4;
#line 761
  __cil_tmp85 = (signed char )__cil_tmp84;
#line 761
  __cil_tmp86 = (int )__cil_tmp85;
#line 761
  __cil_tmp87 = __cil_tmp86 | __cil_tmp82;
#line 761
  dtd->part2.v_sync_off_width = (u8 )__cil_tmp87;
#line 763
  __cil_tmp88 = (int )v_sync_len;
#line 763
  __cil_tmp89 = __cil_tmp88 & 48;
#line 763
  __cil_tmp90 = __cil_tmp89 >> 4;
#line 763
  __cil_tmp91 = (signed char )__cil_tmp90;
#line 763
  __cil_tmp92 = (int )__cil_tmp91;
#line 763
  __cil_tmp93 = (int )v_sync_offset;
#line 763
  __cil_tmp94 = __cil_tmp93 & 48;
#line 763
  __cil_tmp95 = __cil_tmp94 >> 2;
#line 763
  __cil_tmp96 = (signed char )__cil_tmp95;
#line 763
  __cil_tmp97 = (int )__cil_tmp96;
#line 763
  __cil_tmp98 = (int )h_sync_len;
#line 763
  __cil_tmp99 = __cil_tmp98 & 768;
#line 763
  __cil_tmp100 = __cil_tmp99 >> 4;
#line 763
  __cil_tmp101 = (signed char )__cil_tmp100;
#line 763
  __cil_tmp102 = (int )__cil_tmp101;
#line 763
  __cil_tmp103 = (int )h_sync_offset;
#line 763
  __cil_tmp104 = __cil_tmp103 & 768;
#line 763
  __cil_tmp105 = __cil_tmp104 >> 2;
#line 763
  __cil_tmp106 = (signed char )__cil_tmp105;
#line 763
  __cil_tmp107 = (int )__cil_tmp106;
#line 763
  __cil_tmp108 = __cil_tmp107 | __cil_tmp102;
#line 763
  __cil_tmp109 = __cil_tmp108 | __cil_tmp97;
#line 763
  __cil_tmp110 = __cil_tmp109 | __cil_tmp92;
#line 763
  dtd->part2.sync_off_width_high = (u8 )__cil_tmp110;
#line 767
  dtd->part2.dtd_flags = (u8 )24U;
  {
#line 768
  __cil_tmp111 = mode->flags;
#line 768
  __cil_tmp112 = (int )__cil_tmp111;
#line 768
  if (__cil_tmp112 & 1) {
#line 769
    __cil_tmp113 = dtd->part2.dtd_flags;
#line 769
    __cil_tmp114 = (unsigned int )__cil_tmp113;
#line 769
    __cil_tmp115 = __cil_tmp114 | 2U;
#line 769
    dtd->part2.dtd_flags = (u8 )__cil_tmp115;
  } else {

  }
  }
  {
#line 770
  __cil_tmp116 = mode->flags;
#line 770
  __cil_tmp117 = (unsigned int )__cil_tmp116;
#line 770
  __cil_tmp118 = __cil_tmp117 & 4U;
#line 770
  if (__cil_tmp118 != 0U) {
#line 771
    __cil_tmp119 = dtd->part2.dtd_flags;
#line 771
    __cil_tmp120 = (unsigned int )__cil_tmp119;
#line 771
    __cil_tmp121 = __cil_tmp120 | 4U;
#line 771
    dtd->part2.dtd_flags = (u8 )__cil_tmp121;
  } else {

  }
  }
#line 773
  dtd->part2.sdvo_flags = (u8 )0U;
#line 774
  __cil_tmp122 = (u8 )v_sync_offset;
#line 774
  __cil_tmp123 = (unsigned int )__cil_tmp122;
#line 774
  __cil_tmp124 = __cil_tmp123 & 192U;
#line 774
  dtd->part2.v_sync_off_high = (u8 )__cil_tmp124;
#line 775
  dtd->part2.reserved = (u8 )0U;
#line 776
  return;
}
}
#line 778 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *mode , struct intel_sdvo_dtd  const  *dtd ) 
{ u8 __cil_tmp3 ;
  u8 __cil_tmp4 ;
  unsigned char __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  u8 __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  u8 __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  u8 __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  u8 __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  u8 __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  u8 __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  u8 __cil_tmp35 ;
  u8 __cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  int __cil_tmp42 ;
  u8 __cil_tmp43 ;
  unsigned char __cil_tmp44 ;
  int __cil_tmp45 ;
  int __cil_tmp46 ;
  int __cil_tmp47 ;
  int __cil_tmp48 ;
  u8 __cil_tmp49 ;
  int __cil_tmp50 ;
  int __cil_tmp51 ;
  int __cil_tmp52 ;
  int __cil_tmp53 ;
  u8 __cil_tmp54 ;
  int __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  u8 __cil_tmp58 ;
  int __cil_tmp59 ;
  int __cil_tmp60 ;
  int __cil_tmp61 ;
  u8 __cil_tmp62 ;
  int __cil_tmp63 ;
  int __cil_tmp64 ;
  int __cil_tmp65 ;
  int __cil_tmp66 ;
  u8 __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  u8 __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  u16 __cil_tmp75 ;
  int __cil_tmp76 ;
  unsigned int __cil_tmp77 ;
  u8 __cil_tmp78 ;
  int __cil_tmp79 ;
  int __cil_tmp80 ;
  unsigned int __cil_tmp81 ;
  u8 __cil_tmp82 ;
  int __cil_tmp83 ;
  int __cil_tmp84 ;
  unsigned int __cil_tmp85 ;

  {
#line 781
  __cil_tmp3 = dtd->part1.h_active;
#line 781
  mode->hdisplay = (int )__cil_tmp3;
#line 782
  __cil_tmp4 = dtd->part1.h_high;
#line 782
  __cil_tmp5 = (unsigned char )__cil_tmp4;
#line 782
  __cil_tmp6 = (int )__cil_tmp5;
#line 782
  __cil_tmp7 = __cil_tmp6 >> 4;
#line 782
  __cil_tmp8 = __cil_tmp7 & 15;
#line 782
  __cil_tmp9 = __cil_tmp8 << 8;
#line 782
  __cil_tmp10 = mode->hdisplay;
#line 782
  mode->hdisplay = __cil_tmp10 + __cil_tmp9;
#line 783
  __cil_tmp11 = dtd->part2.h_sync_off;
#line 783
  __cil_tmp12 = (int )__cil_tmp11;
#line 783
  __cil_tmp13 = mode->hdisplay;
#line 783
  mode->hsync_start = __cil_tmp13 + __cil_tmp12;
#line 784
  __cil_tmp14 = dtd->part2.sync_off_width_high;
#line 784
  __cil_tmp15 = (int )__cil_tmp14;
#line 784
  __cil_tmp16 = __cil_tmp15 & 192;
#line 784
  __cil_tmp17 = __cil_tmp16 << 2;
#line 784
  __cil_tmp18 = mode->hsync_start;
#line 784
  mode->hsync_start = __cil_tmp18 + __cil_tmp17;
#line 785
  __cil_tmp19 = dtd->part2.h_sync_width;
#line 785
  __cil_tmp20 = (int )__cil_tmp19;
#line 785
  __cil_tmp21 = mode->hsync_start;
#line 785
  mode->hsync_end = __cil_tmp21 + __cil_tmp20;
#line 786
  __cil_tmp22 = dtd->part2.sync_off_width_high;
#line 786
  __cil_tmp23 = (int )__cil_tmp22;
#line 786
  __cil_tmp24 = __cil_tmp23 & 48;
#line 786
  __cil_tmp25 = __cil_tmp24 << 4;
#line 786
  __cil_tmp26 = mode->hsync_end;
#line 786
  mode->hsync_end = __cil_tmp26 + __cil_tmp25;
#line 787
  __cil_tmp27 = dtd->part1.h_blank;
#line 787
  __cil_tmp28 = (int )__cil_tmp27;
#line 787
  __cil_tmp29 = mode->hdisplay;
#line 787
  mode->htotal = __cil_tmp29 + __cil_tmp28;
#line 788
  __cil_tmp30 = dtd->part1.h_high;
#line 788
  __cil_tmp31 = (int )__cil_tmp30;
#line 788
  __cil_tmp32 = __cil_tmp31 & 15;
#line 788
  __cil_tmp33 = __cil_tmp32 << 8;
#line 788
  __cil_tmp34 = mode->htotal;
#line 788
  mode->htotal = __cil_tmp34 + __cil_tmp33;
#line 790
  __cil_tmp35 = dtd->part1.v_active;
#line 790
  mode->vdisplay = (int )__cil_tmp35;
#line 791
  __cil_tmp36 = dtd->part1.v_high;
#line 791
  __cil_tmp37 = (unsigned char )__cil_tmp36;
#line 791
  __cil_tmp38 = (int )__cil_tmp37;
#line 791
  __cil_tmp39 = __cil_tmp38 >> 4;
#line 791
  __cil_tmp40 = __cil_tmp39 & 15;
#line 791
  __cil_tmp41 = __cil_tmp40 << 8;
#line 791
  __cil_tmp42 = mode->vdisplay;
#line 791
  mode->vdisplay = __cil_tmp42 + __cil_tmp41;
#line 792
  mode->vsync_start = mode->vdisplay;
#line 793
  __cil_tmp43 = dtd->part2.v_sync_off_width;
#line 793
  __cil_tmp44 = (unsigned char )__cil_tmp43;
#line 793
  __cil_tmp45 = (int )__cil_tmp44;
#line 793
  __cil_tmp46 = __cil_tmp45 >> 4;
#line 793
  __cil_tmp47 = __cil_tmp46 & 15;
#line 793
  __cil_tmp48 = mode->vsync_start;
#line 793
  mode->vsync_start = __cil_tmp48 + __cil_tmp47;
#line 794
  __cil_tmp49 = dtd->part2.sync_off_width_high;
#line 794
  __cil_tmp50 = (int )__cil_tmp49;
#line 794
  __cil_tmp51 = __cil_tmp50 & 12;
#line 794
  __cil_tmp52 = __cil_tmp51 << 2;
#line 794
  __cil_tmp53 = mode->vsync_start;
#line 794
  mode->vsync_start = __cil_tmp53 + __cil_tmp52;
#line 795
  __cil_tmp54 = dtd->part2.v_sync_off_high;
#line 795
  __cil_tmp55 = (int )__cil_tmp54;
#line 795
  __cil_tmp56 = __cil_tmp55 & 192;
#line 795
  __cil_tmp57 = mode->vsync_start;
#line 795
  mode->vsync_start = __cil_tmp57 + __cil_tmp56;
#line 796
  __cil_tmp58 = dtd->part2.v_sync_off_width;
#line 796
  __cil_tmp59 = (int )__cil_tmp58;
#line 796
  __cil_tmp60 = __cil_tmp59 & 15;
#line 796
  __cil_tmp61 = mode->vsync_start;
#line 796
  mode->vsync_end = __cil_tmp61 + __cil_tmp60;
#line 798
  __cil_tmp62 = dtd->part2.sync_off_width_high;
#line 798
  __cil_tmp63 = (int )__cil_tmp62;
#line 798
  __cil_tmp64 = __cil_tmp63 & 3;
#line 798
  __cil_tmp65 = __cil_tmp64 << 4;
#line 798
  __cil_tmp66 = mode->vsync_end;
#line 798
  mode->vsync_end = __cil_tmp66 + __cil_tmp65;
#line 799
  __cil_tmp67 = dtd->part1.v_blank;
#line 799
  __cil_tmp68 = (int )__cil_tmp67;
#line 799
  __cil_tmp69 = mode->vdisplay;
#line 799
  mode->vtotal = __cil_tmp69 + __cil_tmp68;
#line 800
  __cil_tmp70 = dtd->part1.v_high;
#line 800
  __cil_tmp71 = (int )__cil_tmp70;
#line 800
  __cil_tmp72 = __cil_tmp71 & 15;
#line 800
  __cil_tmp73 = __cil_tmp72 << 8;
#line 800
  __cil_tmp74 = mode->vtotal;
#line 800
  mode->vtotal = __cil_tmp74 + __cil_tmp73;
#line 802
  __cil_tmp75 = dtd->part1.clock;
#line 802
  __cil_tmp76 = (int )__cil_tmp75;
#line 802
  mode->clock = __cil_tmp76 * 10;
#line 804
  __cil_tmp77 = mode->flags;
#line 804
  mode->flags = __cil_tmp77 & 4294967290U;
  {
#line 805
  __cil_tmp78 = dtd->part2.dtd_flags;
#line 805
  __cil_tmp79 = (int )__cil_tmp78;
#line 805
  __cil_tmp80 = __cil_tmp79 & 2;
#line 805
  if (__cil_tmp80 != 0) {
#line 806
    __cil_tmp81 = mode->flags;
#line 806
    mode->flags = __cil_tmp81 | 1U;
  } else {

  }
  }
  {
#line 807
  __cil_tmp82 = dtd->part2.dtd_flags;
#line 807
  __cil_tmp83 = (int )__cil_tmp82;
#line 807
  __cil_tmp84 = __cil_tmp83 & 4;
#line 807
  if (__cil_tmp84 != 0) {
#line 808
    __cil_tmp85 = mode->flags;
#line 808
    mode->flags = __cil_tmp85 | 4U;
  } else {

  }
  }
#line 809
  return;
}
}
#line 811 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo ) 
{ struct intel_sdvo_encode encode ;
  bool tmp ;
  u8 __cil_tmp4 ;
  void *__cil_tmp5 ;

  {
  {
#line 816
  __cil_tmp4 = (u8 )157;
#line 816
  __cil_tmp5 = (void *)(& encode);
#line 816
  tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 2);
  }
#line 816
  return (tmp);
}
}
#line 821 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo , uint8_t mode ) 
{ bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 824
  __cil_tmp4 = (u8 )159;
#line 824
  __cil_tmp5 = (void const   *)(& mode);
#line 824
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 1);
  }
#line 824
  return (tmp);
}
}
#line 827 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo , uint8_t mode ) 
{ bool tmp ;
  u8 __cil_tmp4 ;
  void const   *__cil_tmp5 ;

  {
  {
#line 830
  __cil_tmp4 = (u8 )142;
#line 830
  __cil_tmp5 = (void const   *)(& mode);
#line 830
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp4, __cil_tmp5, 1);
  }
#line 830
  return (tmp);
}
}
#line 863 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo ) 
{ struct dip_infoframe avi_if ;
  uint8_t tx_rate ;
  uint8_t set_buf_index[2U] ;
  uint64_t *data ;
  unsigned int i ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  u8 __cil_tmp12 ;
  void const   *__cil_tmp13 ;
  u8 __cil_tmp14 ;
  void const   *__cil_tmp15 ;
  u8 __cil_tmp16 ;
  void const   *__cil_tmp17 ;

  {
  {
#line 865
  avi_if.type = (uint8_t )130U;
#line 865
  avi_if.ver = (uint8_t )2U;
#line 865
  avi_if.len = (uint8_t )13U;
#line 865
  avi_if.ecc = (unsigned char)0;
#line 865
  avi_if.checksum = (unsigned char)0;
#line 865
  avi_if.body.payload[0] = (unsigned char)0;
#line 865
  avi_if.body.payload[1] = (unsigned char)0;
#line 865
  avi_if.body.payload[2] = (unsigned char)0;
#line 865
  avi_if.body.payload[3] = (unsigned char)0;
#line 865
  avi_if.body.payload[4] = (unsigned char)0;
#line 865
  avi_if.body.payload[5] = (unsigned char)0;
#line 865
  avi_if.body.payload[6] = (unsigned char)0;
#line 865
  avi_if.body.payload[7] = (unsigned char)0;
#line 865
  avi_if.body.payload[8] = (unsigned char)0;
#line 865
  avi_if.body.payload[9] = (unsigned char)0;
#line 865
  avi_if.body.payload[10] = (unsigned char)0;
#line 865
  avi_if.body.payload[11] = (unsigned char)0;
#line 865
  avi_if.body.payload[12] = (unsigned char)0;
#line 865
  avi_if.body.payload[13] = (unsigned char)0;
#line 865
  avi_if.body.payload[14] = (unsigned char)0;
#line 865
  avi_if.body.payload[15] = (unsigned char)0;
#line 865
  avi_if.body.payload[16] = (unsigned char)0;
#line 865
  avi_if.body.payload[17] = (unsigned char)0;
#line 865
  avi_if.body.payload[18] = (unsigned char)0;
#line 865
  avi_if.body.payload[19] = (unsigned char)0;
#line 865
  avi_if.body.payload[20] = (unsigned char)0;
#line 865
  avi_if.body.payload[21] = (unsigned char)0;
#line 865
  avi_if.body.payload[22] = (unsigned char)0;
#line 865
  avi_if.body.payload[23] = (unsigned char)0;
#line 865
  avi_if.body.payload[24] = (unsigned char)0;
#line 865
  avi_if.body.payload[25] = (unsigned char)0;
#line 865
  avi_if.body.payload[26] = (unsigned char)0;
#line 870
  tx_rate = (uint8_t )192U;
#line 871
  set_buf_index[0] = (uint8_t )1U;
#line 871
  set_buf_index[1] = (uint8_t )0U;
#line 872
  data = (uint64_t *)(& avi_if);
#line 875
  intel_dip_infoframe_csum(& avi_if);
#line 877
  __cil_tmp12 = (u8 )147;
#line 877
  __cil_tmp13 = (void const   *)(& set_buf_index);
#line 877
  tmp = intel_sdvo_set_value(intel_sdvo, __cil_tmp12, __cil_tmp13, 2);
  }
#line 877
  if (tmp) {
#line 877
    tmp___0 = 0;
  } else {
#line 877
    tmp___0 = 1;
  }
#line 877
  if (tmp___0) {
#line 880
    return ((bool )0);
  } else {

  }
#line 882
  i = 0U;
#line 882
  goto ldv_38213;
  ldv_38212: 
  {
#line 883
  __cil_tmp14 = (u8 )152;
#line 883
  __cil_tmp15 = (void const   *)data;
#line 883
  tmp___1 = intel_sdvo_set_value(intel_sdvo, __cil_tmp14, __cil_tmp15, 8);
  }
#line 883
  if (tmp___1) {
#line 883
    tmp___2 = 0;
  } else {
#line 883
    tmp___2 = 1;
  }
#line 883
  if (tmp___2) {
#line 886
    return ((bool )0);
  } else {

  }
#line 887
  data = data + 1;
#line 882
  i = i + 8U;
  ldv_38213: ;
#line 882
  if (i <= 31U) {
#line 883
    goto ldv_38212;
  } else {
#line 885
    goto ldv_38214;
  }
  ldv_38214: 
  {
#line 890
  __cil_tmp16 = (u8 )154;
#line 890
  __cil_tmp17 = (void const   *)(& tx_rate);
#line 890
  tmp___3 = intel_sdvo_set_value(intel_sdvo, __cil_tmp16, __cil_tmp17, 1);
  }
#line 890
  return (tmp___3);
}
}
#line 895 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo ) 
{ struct intel_sdvo_tv_format format ;
  uint32_t format_map ;
  size_t __len ;
  unsigned long _min1 ;
  unsigned long _min2 ;
  unsigned long tmp ;
  void *__ret ;
  bool tmp___0 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  void *__cil_tmp12 ;
  void *__cil_tmp13 ;
  void const   *__cil_tmp14 ;
  u8 __cil_tmp15 ;
  void const   *__cil_tmp16 ;

  {
  {
#line 900
  __cil_tmp10 = intel_sdvo->tv_format_index;
#line 900
  __cil_tmp11 = 1 << __cil_tmp10;
#line 900
  format_map = (uint32_t )__cil_tmp11;
#line 901
  __cil_tmp12 = (void *)(& format);
#line 901
  memset(__cil_tmp12, 0, 6UL);
#line 902
  _min1 = 6UL;
#line 902
  _min2 = 4UL;
  }
#line 902
  if (_min1 < _min2) {
#line 902
    tmp = _min1;
  } else {
#line 902
    tmp = _min2;
  }
  {
#line 902
  __len = tmp;
#line 902
  __cil_tmp13 = (void *)(& format);
#line 902
  __cil_tmp14 = (void const   *)(& format_map);
#line 902
  __ret = __builtin_memcpy(__cil_tmp13, __cil_tmp14, __len);
#line 905
  __cil_tmp15 = (u8 )41;
#line 905
  __cil_tmp16 = (void const   *)(& format);
#line 905
  tmp___0 = intel_sdvo_set_value(intel_sdvo, __cil_tmp15, __cil_tmp16, 6);
  }
#line 905
  return (tmp___0);
}
}
#line 911 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo ,
                                                    struct drm_display_mode *mode ) 
{ struct intel_sdvo_dtd output_dtd ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  uint16_t __cil_tmp8 ;
  int __cil_tmp9 ;
  u16 __cil_tmp10 ;
  struct drm_display_mode  const  *__cil_tmp11 ;

  {
  {
#line 916
  __cil_tmp8 = intel_sdvo->attached_output;
#line 916
  __cil_tmp9 = (int )__cil_tmp8;
#line 916
  __cil_tmp10 = (u16 )__cil_tmp9;
#line 916
  tmp = intel_sdvo_set_target_output(intel_sdvo, __cil_tmp10);
  }
#line 916
  if (tmp) {
#line 916
    tmp___0 = 0;
  } else {
#line 916
    tmp___0 = 1;
  }
#line 916
  if (tmp___0) {
#line 918
    return ((bool )0);
  } else {

  }
  {
#line 920
  __cil_tmp11 = (struct drm_display_mode  const  *)mode;
#line 920
  intel_sdvo_get_dtd_from_mode(& output_dtd, __cil_tmp11);
#line 921
  tmp___1 = intel_sdvo_set_output_timing(intel_sdvo, & output_dtd);
  }
#line 921
  if (tmp___1) {
#line 921
    tmp___2 = 0;
  } else {
#line 921
    tmp___2 = 1;
  }
#line 921
  if (tmp___2) {
#line 922
    return ((bool )0);
  } else {

  }
#line 924
  return ((bool )1);
}
}
#line 928 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo ,
                                                  struct drm_display_mode *mode ,
                                                  struct drm_display_mode *adjusted_mode ) 
{ bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  uint16_t __cil_tmp12 ;
  int __cil_tmp13 ;
  uint16_t __cil_tmp14 ;
  int __cil_tmp15 ;
  uint16_t __cil_tmp16 ;
  int __cil_tmp17 ;
  uint16_t __cil_tmp18 ;
  int __cil_tmp19 ;
  uint16_t __cil_tmp20 ;
  int __cil_tmp21 ;
  uint16_t __cil_tmp22 ;
  struct intel_sdvo_dtd *__cil_tmp23 ;
  struct intel_sdvo_dtd *__cil_tmp24 ;
  struct intel_sdvo_dtd  const  *__cil_tmp25 ;

  {
  {
#line 933
  tmp = intel_sdvo_set_target_input(intel_sdvo);
  }
#line 933
  if (tmp) {
#line 933
    tmp___0 = 0;
  } else {
#line 933
    tmp___0 = 1;
  }
#line 933
  if (tmp___0) {
#line 934
    return ((bool )0);
  } else {

  }
  {
#line 936
  __cil_tmp10 = mode->clock;
#line 936
  __cil_tmp11 = __cil_tmp10 / 10;
#line 936
  __cil_tmp12 = (uint16_t )__cil_tmp11;
#line 936
  __cil_tmp13 = (int )__cil_tmp12;
#line 936
  __cil_tmp14 = (uint16_t )__cil_tmp13;
#line 936
  __cil_tmp15 = mode->hdisplay;
#line 936
  __cil_tmp16 = (uint16_t )__cil_tmp15;
#line 936
  __cil_tmp17 = (int )__cil_tmp16;
#line 936
  __cil_tmp18 = (uint16_t )__cil_tmp17;
#line 936
  __cil_tmp19 = mode->vdisplay;
#line 936
  __cil_tmp20 = (uint16_t )__cil_tmp19;
#line 936
  __cil_tmp21 = (int )__cil_tmp20;
#line 936
  __cil_tmp22 = (uint16_t )__cil_tmp21;
#line 936
  tmp___1 = intel_sdvo_create_preferred_input_timing(intel_sdvo, __cil_tmp14, __cil_tmp18,
                                                     __cil_tmp22);
  }
#line 936
  if (tmp___1) {
#line 936
    tmp___2 = 0;
  } else {
#line 936
    tmp___2 = 1;
  }
#line 936
  if (tmp___2) {
#line 940
    return ((bool )0);
  } else {

  }
  {
#line 942
  __cil_tmp23 = & intel_sdvo->input_dtd;
#line 942
  tmp___3 = intel_sdvo_get_preferred_input_timing(intel_sdvo, __cil_tmp23);
  }
#line 942
  if (tmp___3) {
#line 942
    tmp___4 = 0;
  } else {
#line 942
    tmp___4 = 1;
  }
#line 942
  if (tmp___4) {
#line 944
    return ((bool )0);
  } else {

  }
  {
#line 946
  __cil_tmp24 = & intel_sdvo->input_dtd;
#line 946
  __cil_tmp25 = (struct intel_sdvo_dtd  const  *)__cil_tmp24;
#line 946
  intel_sdvo_get_mode_from_dtd(adjusted_mode, __cil_tmp25);
#line 948
  drm_mode_set_crtcinfo(adjusted_mode, 0);
  }
#line 949
  return ((bool )1);
}
}
#line 952 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                  struct drm_display_mode *adjusted_mode ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  int multiplier ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  bool __cil_tmp11 ;
  bool __cil_tmp12 ;
  struct drm_display_mode *__cil_tmp13 ;

  {
  {
#line 956
  tmp = to_intel_sdvo(encoder);
#line 956
  intel_sdvo = tmp;
  }
  {
#line 964
  __cil_tmp11 = intel_sdvo->is_tv;
#line 964
  if ((int )__cil_tmp11) {
    {
#line 965
    tmp___0 = intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode);
    }
#line 965
    if (tmp___0) {
#line 965
      tmp___1 = 0;
    } else {
#line 965
      tmp___1 = 1;
    }
#line 965
    if (tmp___1) {
#line 966
      return ((bool )0);
    } else {

    }
    {
#line 968
    intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode);
    }
  } else {
    {
#line 971
    __cil_tmp12 = intel_sdvo->is_lvds;
#line 971
    if ((int )__cil_tmp12) {
      {
#line 972
      __cil_tmp13 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 972
      tmp___2 = intel_sdvo_set_output_timings_from_mode(intel_sdvo, __cil_tmp13);
      }
#line 972
      if (tmp___2) {
#line 972
        tmp___3 = 0;
      } else {
#line 972
        tmp___3 = 1;
      }
#line 972
      if (tmp___3) {
#line 974
        return ((bool )0);
      } else {

      }
      {
#line 976
      intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode);
      }
    } else {

    }
    }
  }
  }
  {
#line 984
  multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
#line 985
  intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  }
#line 987
  return ((bool )1);
}
}
#line 990 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  u32 sdvox ;
  struct intel_sdvo_in_out_map in_out ;
  struct intel_sdvo_dtd input_dtd ;
  int pixel_multiplier ;
  int tmp___0 ;
  int rate ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  bool tmp___5 ;
  int tmp___6 ;
  bool tmp___7 ;
  int tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  void *__cil_tmp27 ;
  struct drm_display_mode  const  *__cil_tmp28 ;
  struct drm_display_mode *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  u8 __cil_tmp32 ;
  void const   *__cil_tmp33 ;
  uint16_t __cil_tmp34 ;
  int __cil_tmp35 ;
  u16 __cil_tmp36 ;
  bool __cil_tmp37 ;
  bool __cil_tmp38 ;
  uint16_t __cil_tmp39 ;
  int __cil_tmp40 ;
  u16 __cil_tmp41 ;
  struct drm_display_mode  const  *__cil_tmp42 ;
  bool __cil_tmp43 ;
  uint8_t __cil_tmp44 ;
  uint8_t __cil_tmp45 ;
  uint8_t __cil_tmp46 ;
  bool __cil_tmp47 ;
  u8 __cil_tmp48 ;
  int __cil_tmp49 ;
  u8 __cil_tmp50 ;
  void *__cil_tmp51 ;
  struct drm_i915_private *__cil_tmp52 ;
  struct intel_device_info  const  *__cil_tmp53 ;
  u8 __cil_tmp54 ;
  unsigned char __cil_tmp55 ;
  unsigned int __cil_tmp56 ;
  bool __cil_tmp57 ;
  uint32_t __cil_tmp58 ;
  void *__cil_tmp59 ;
  struct drm_i915_private *__cil_tmp60 ;
  struct intel_device_info  const  *__cil_tmp61 ;
  u8 __cil_tmp62 ;
  unsigned char __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  unsigned int __cil_tmp65 ;
  unsigned int __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  u32 __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  enum pipe __cil_tmp73 ;
  unsigned int __cil_tmp74 ;
  bool __cil_tmp75 ;
  void *__cil_tmp76 ;
  struct drm_i915_private *__cil_tmp77 ;
  struct intel_device_info  const  *__cil_tmp78 ;
  u8 __cil_tmp79 ;
  unsigned char __cil_tmp80 ;
  unsigned int __cil_tmp81 ;
  int __cil_tmp82 ;
  void *__cil_tmp83 ;
  struct drm_i915_private *__cil_tmp84 ;
  struct intel_device_info  const  *__cil_tmp85 ;
  unsigned char *__cil_tmp86 ;
  unsigned char *__cil_tmp87 ;
  unsigned char __cil_tmp88 ;
  unsigned int __cil_tmp89 ;
  void *__cil_tmp90 ;
  struct drm_i915_private *__cil_tmp91 ;
  struct intel_device_info  const  *__cil_tmp92 ;
  unsigned char *__cil_tmp93 ;
  unsigned char *__cil_tmp94 ;
  unsigned char __cil_tmp95 ;
  unsigned int __cil_tmp96 ;
  int __cil_tmp97 ;
  int __cil_tmp98 ;
  u32 __cil_tmp99 ;
  signed char __cil_tmp100 ;
  int __cil_tmp101 ;
  void *__cil_tmp102 ;
  struct drm_i915_private *__cil_tmp103 ;
  struct intel_device_info  const  *__cil_tmp104 ;
  u8 __cil_tmp105 ;
  unsigned char __cil_tmp106 ;
  unsigned int __cil_tmp107 ;

  {
  {
#line 994
  dev = encoder->dev;
#line 995
  __cil_tmp27 = dev->dev_private;
#line 995
  dev_priv = (struct drm_i915_private *)__cil_tmp27;
#line 996
  crtc = encoder->crtc;
#line 997
  __mptr = (struct drm_crtc  const  *)crtc;
#line 997
  intel_crtc = (struct intel_crtc *)__mptr;
#line 998
  tmp = to_intel_sdvo(encoder);
#line 998
  intel_sdvo = tmp;
#line 1002
  __cil_tmp28 = (struct drm_display_mode  const  *)adjusted_mode;
#line 1002
  tmp___0 = intel_mode_get_pixel_multiplier(__cil_tmp28);
#line 1002
  pixel_multiplier = tmp___0;
  }
  {
#line 1005
  __cil_tmp29 = (struct drm_display_mode *)0;
#line 1005
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 1005
  __cil_tmp31 = (unsigned long )mode;
#line 1005
  if (__cil_tmp31 == __cil_tmp30) {
#line 1006
    return;
  } else {

  }
  }
  {
#line 1014
  in_out.in0 = intel_sdvo->attached_output;
#line 1015
  in_out.in1 = (u16 )0U;
#line 1017
  __cil_tmp32 = (u8 )7;
#line 1017
  __cil_tmp33 = (void const   *)(& in_out);
#line 1017
  intel_sdvo_set_value(intel_sdvo, __cil_tmp32, __cil_tmp33, 4);
#line 1022
  __cil_tmp34 = intel_sdvo->attached_output;
#line 1022
  __cil_tmp35 = (int )__cil_tmp34;
#line 1022
  __cil_tmp36 = (u16 )__cil_tmp35;
#line 1022
  tmp___1 = intel_sdvo_set_target_output(intel_sdvo, __cil_tmp36);
  }
#line 1022
  if (tmp___1) {
#line 1022
    tmp___2 = 0;
  } else {
#line 1022
    tmp___2 = 1;
  }
#line 1022
  if (tmp___2) {
#line 1024
    return;
  } else {

  }
  {
#line 1029
  __cil_tmp37 = intel_sdvo->is_tv;
#line 1029
  if ((int )__cil_tmp37) {
#line 1030
    input_dtd = intel_sdvo->input_dtd;
  } else {
    {
#line 1029
    __cil_tmp38 = intel_sdvo->is_lvds;
#line 1029
    if ((int )__cil_tmp38) {
#line 1030
      input_dtd = intel_sdvo->input_dtd;
    } else {
      {
#line 1033
      __cil_tmp39 = intel_sdvo->attached_output;
#line 1033
      __cil_tmp40 = (int )__cil_tmp39;
#line 1033
      __cil_tmp41 = (u16 )__cil_tmp40;
#line 1033
      tmp___3 = intel_sdvo_set_target_output(intel_sdvo, __cil_tmp41);
      }
#line 1033
      if (tmp___3) {
#line 1033
        tmp___4 = 0;
      } else {
#line 1033
        tmp___4 = 1;
      }
#line 1033
      if (tmp___4) {
#line 1035
        return;
      } else {

      }
      {
#line 1037
      __cil_tmp42 = (struct drm_display_mode  const  *)adjusted_mode;
#line 1037
      intel_sdvo_get_dtd_from_mode(& input_dtd, __cil_tmp42);
#line 1038
      intel_sdvo_set_output_timing(intel_sdvo, & input_dtd);
      }
    }
    }
  }
  }
  {
#line 1042
  tmp___5 = intel_sdvo_set_target_input(intel_sdvo);
  }
#line 1042
  if (tmp___5) {
#line 1042
    tmp___6 = 0;
  } else {
#line 1042
    tmp___6 = 1;
  }
#line 1042
  if (tmp___6) {
#line 1043
    return;
  } else {

  }
  {
#line 1045
  __cil_tmp43 = intel_sdvo->has_hdmi_monitor;
#line 1045
  if ((int )__cil_tmp43) {
    {
#line 1046
    __cil_tmp44 = (uint8_t )1;
#line 1046
    intel_sdvo_set_encode(intel_sdvo, __cil_tmp44);
#line 1047
    __cil_tmp45 = (uint8_t )0;
#line 1047
    intel_sdvo_set_colorimetry(intel_sdvo, __cil_tmp45);
#line 1049
    intel_sdvo_set_avi_infoframe(intel_sdvo);
    }
  } else {
    {
#line 1051
    __cil_tmp46 = (uint8_t )0;
#line 1051
    intel_sdvo_set_encode(intel_sdvo, __cil_tmp46);
    }
  }
  }
  {
#line 1053
  __cil_tmp47 = intel_sdvo->is_tv;
#line 1053
  if ((int )__cil_tmp47) {
    {
#line 1053
    tmp___7 = intel_sdvo_set_tv_format(intel_sdvo);
    }
#line 1053
    if (tmp___7) {
#line 1053
      tmp___8 = 0;
    } else {
#line 1053
      tmp___8 = 1;
    }
#line 1053
    if (tmp___8) {
#line 1055
      return;
    } else {

    }
  } else {

  }
  }
  {
#line 1057
  intel_sdvo_set_input_timing(intel_sdvo, & input_dtd);
  }
#line 1061
  if (pixel_multiplier == 1) {
#line 1061
    goto case_1;
  } else
#line 1062
  if (pixel_multiplier == 2) {
#line 1062
    goto case_2;
  } else
#line 1063
  if (pixel_multiplier == 4) {
#line 1063
    goto case_4;
  } else {
#line 1060
    goto switch_default;
#line 1059
    if (0) {
      switch_default: ;
      case_1: 
#line 1061
      rate = 1;
#line 1061
      goto ldv_38265;
      case_2: 
#line 1062
      rate = 2;
#line 1062
      goto ldv_38265;
      case_4: 
#line 1063
      rate = 8;
#line 1063
      goto ldv_38265;
    } else {

    }
  }
  ldv_38265: 
  {
#line 1065
  __cil_tmp48 = (u8 )rate;
#line 1065
  __cil_tmp49 = (int )__cil_tmp48;
#line 1065
  __cil_tmp50 = (u8 )__cil_tmp49;
#line 1065
  tmp___9 = intel_sdvo_set_clock_rate_mult(intel_sdvo, __cil_tmp50);
  }
#line 1065
  if (tmp___9) {
#line 1065
    tmp___10 = 0;
  } else {
#line 1065
    tmp___10 = 1;
  }
#line 1065
  if (tmp___10) {
#line 1066
    return;
  } else {

  }
  {
#line 1069
  __cil_tmp51 = dev->dev_private;
#line 1069
  __cil_tmp52 = (struct drm_i915_private *)__cil_tmp51;
#line 1069
  __cil_tmp53 = __cil_tmp52->info;
#line 1069
  __cil_tmp54 = __cil_tmp53->gen;
#line 1069
  __cil_tmp55 = (unsigned char )__cil_tmp54;
#line 1069
  __cil_tmp56 = (unsigned int )__cil_tmp55;
#line 1069
  if (__cil_tmp56 > 3U) {
#line 1070
    sdvox = 0U;
    {
#line 1071
    __cil_tmp57 = intel_sdvo->is_hdmi;
#line 1071
    if ((int )__cil_tmp57) {
#line 1072
      __cil_tmp58 = intel_sdvo->color_range;
#line 1072
      sdvox = __cil_tmp58 | sdvox;
    } else {

    }
    }
    {
#line 1073
    __cil_tmp59 = dev->dev_private;
#line 1073
    __cil_tmp60 = (struct drm_i915_private *)__cil_tmp59;
#line 1073
    __cil_tmp61 = __cil_tmp60->info;
#line 1073
    __cil_tmp62 = __cil_tmp61->gen;
#line 1073
    __cil_tmp63 = (unsigned char )__cil_tmp62;
#line 1073
    __cil_tmp64 = (unsigned int )__cil_tmp63;
#line 1073
    if (__cil_tmp64 <= 4U) {
#line 1074
      sdvox = sdvox | 128U;
    } else {

    }
    }
    {
#line 1075
    __cil_tmp65 = adjusted_mode->flags;
#line 1075
    __cil_tmp66 = __cil_tmp65 & 4U;
#line 1075
    if (__cil_tmp66 != 0U) {
#line 1076
      sdvox = sdvox | 16U;
    } else {

    }
    }
    {
#line 1077
    __cil_tmp67 = adjusted_mode->flags;
#line 1077
    __cil_tmp68 = (int )__cil_tmp67;
#line 1077
    if (__cil_tmp68 & 1) {
#line 1078
      sdvox = sdvox | 8U;
    } else {

    }
    }
  } else {
    {
#line 1080
    __cil_tmp69 = intel_sdvo->sdvo_reg;
#line 1080
    __cil_tmp70 = (u32 )__cil_tmp69;
#line 1080
    sdvox = i915_read32___11(dev_priv, __cil_tmp70);
    }
    {
#line 1082
    __cil_tmp71 = intel_sdvo->sdvo_reg;
#line 1082
    if (__cil_tmp71 == 397632) {
#line 1082
      goto case_397632;
    } else {
      {
#line 1085
      __cil_tmp72 = intel_sdvo->sdvo_reg;
#line 1085
      if (__cil_tmp72 == 397664) {
#line 1085
        goto case_397664;
      } else
#line 1081
      if (0) {
        case_397632: 
#line 1083
        sdvox = sdvox & 67321856U;
#line 1084
        goto ldv_38269;
        case_397664: 
#line 1086
        sdvox = sdvox & 67239936U;
#line 1087
        goto ldv_38269;
      } else {

      }
      }
    }
    }
    ldv_38269: 
#line 1089
    sdvox = sdvox | 4718720U;
  }
  }
  {
#line 1091
  __cil_tmp73 = intel_crtc->pipe;
#line 1091
  __cil_tmp74 = (unsigned int )__cil_tmp73;
#line 1091
  if (__cil_tmp74 == 1U) {
#line 1092
    sdvox = sdvox | 1073741824U;
  } else {

  }
  }
  {
#line 1093
  __cil_tmp75 = intel_sdvo->has_hdmi_audio;
#line 1093
  if ((int )__cil_tmp75) {
#line 1094
    sdvox = sdvox | 64U;
  } else {

  }
  }
  {
#line 1096
  __cil_tmp76 = dev->dev_private;
#line 1096
  __cil_tmp77 = (struct drm_i915_private *)__cil_tmp76;
#line 1096
  __cil_tmp78 = __cil_tmp77->info;
#line 1096
  __cil_tmp79 = __cil_tmp78->gen;
#line 1096
  __cil_tmp80 = (unsigned char )__cil_tmp79;
#line 1096
  __cil_tmp81 = (unsigned int )__cil_tmp80;
#line 1096
  if (__cil_tmp81 > 3U) {

  } else {
    {
#line 1098
    __cil_tmp82 = dev->pci_device;
#line 1098
    if (__cil_tmp82 == 10098) {

    } else {
      {
#line 1098
      __cil_tmp83 = dev->dev_private;
#line 1098
      __cil_tmp84 = (struct drm_i915_private *)__cil_tmp83;
#line 1098
      __cil_tmp85 = __cil_tmp84->info;
#line 1098
      __cil_tmp86 = (unsigned char *)__cil_tmp85;
#line 1098
      __cil_tmp87 = __cil_tmp86 + 1UL;
#line 1098
      __cil_tmp88 = *__cil_tmp87;
#line 1098
      __cil_tmp89 = (unsigned int )__cil_tmp88;
#line 1098
      if (__cil_tmp89 != 0U) {

      } else {
        {
#line 1098
        __cil_tmp90 = dev->dev_private;
#line 1098
        __cil_tmp91 = (struct drm_i915_private *)__cil_tmp90;
#line 1098
        __cil_tmp92 = __cil_tmp91->info;
#line 1098
        __cil_tmp93 = (unsigned char *)__cil_tmp92;
#line 1098
        __cil_tmp94 = __cil_tmp93 + 1UL;
#line 1098
        __cil_tmp95 = *__cil_tmp94;
#line 1098
        __cil_tmp96 = (unsigned int )__cil_tmp95;
#line 1098
        if (__cil_tmp96 != 0U) {

        } else {
#line 1101
          __cil_tmp97 = pixel_multiplier + -1;
#line 1101
          __cil_tmp98 = __cil_tmp97 << 23;
#line 1101
          __cil_tmp99 = (u32 )__cil_tmp98;
#line 1101
          sdvox = __cil_tmp99 | sdvox;
        }
        }
      }
      }
    }
    }
  }
  }
  {
#line 1104
  __cil_tmp100 = (signed char )input_dtd.part2.sdvo_flags;
#line 1104
  __cil_tmp101 = (int )__cil_tmp100;
#line 1104
  if (__cil_tmp101 < 0) {
    {
#line 1104
    __cil_tmp102 = dev->dev_private;
#line 1104
    __cil_tmp103 = (struct drm_i915_private *)__cil_tmp102;
#line 1104
    __cil_tmp104 = __cil_tmp103->info;
#line 1104
    __cil_tmp105 = __cil_tmp104->gen;
#line 1104
    __cil_tmp106 = (unsigned char )__cil_tmp105;
#line 1104
    __cil_tmp107 = (unsigned int )__cil_tmp106;
#line 1104
    if (__cil_tmp107 <= 4U) {
#line 1106
      sdvox = sdvox | 536870912U;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1107
  intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  }
#line 1108
  return;
}
}
#line 1110 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_dpms(struct drm_encoder *encoder , int mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  u32 temp ;
  bool input1 ;
  bool input2 ;
  int i ;
  u8 status ;
  bool tmp___0 ;
  char *tmp___1 ;
  void *__cil_tmp16 ;
  struct drm_crtc *__cil_tmp17 ;
  u16 __cil_tmp18 ;
  int __cil_tmp19 ;
  u32 __cil_tmp20 ;
  int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  int __cil_tmp23 ;
  u32 __cil_tmp24 ;
  int __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  enum pipe __cil_tmp27 ;
  int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  uint16_t __cil_tmp32 ;
  int __cil_tmp33 ;
  u16 __cil_tmp34 ;

  {
  {
#line 1112
  dev = encoder->dev;
#line 1113
  __cil_tmp16 = dev->dev_private;
#line 1113
  dev_priv = (struct drm_i915_private *)__cil_tmp16;
#line 1114
  tmp = to_intel_sdvo(encoder);
#line 1114
  intel_sdvo = tmp;
#line 1115
  __cil_tmp17 = encoder->crtc;
#line 1115
  __mptr = (struct drm_crtc  const  *)__cil_tmp17;
#line 1115
  intel_crtc = (struct intel_crtc *)__mptr;
  }
#line 1118
  if (mode != 0) {
    {
#line 1119
    __cil_tmp18 = (u16 )0;
#line 1119
    intel_sdvo_set_active_outputs(intel_sdvo, __cil_tmp18);
    }
#line 1123
    if (mode == 3) {
      {
#line 1124
      __cil_tmp19 = intel_sdvo->sdvo_reg;
#line 1124
      __cil_tmp20 = (u32 )__cil_tmp19;
#line 1124
      temp = i915_read32___11(dev_priv, __cil_tmp20);
      }
      {
#line 1125
      __cil_tmp21 = (int )temp;
#line 1125
      if (__cil_tmp21 < 0) {
        {
#line 1126
        __cil_tmp22 = temp & 2147483647U;
#line 1126
        intel_sdvo_write_sdvox(intel_sdvo, __cil_tmp22);
        }
      } else {

      }
      }
    } else {

    }
  } else {
    {
#line 1134
    __cil_tmp23 = intel_sdvo->sdvo_reg;
#line 1134
    __cil_tmp24 = (u32 )__cil_tmp23;
#line 1134
    temp = i915_read32___11(dev_priv, __cil_tmp24);
    }
    {
#line 1135
    __cil_tmp25 = (int )temp;
#line 1135
    if (__cil_tmp25 >= 0) {
      {
#line 1136
      __cil_tmp26 = temp | 2147483648U;
#line 1136
      intel_sdvo_write_sdvox(intel_sdvo, __cil_tmp26);
      }
    } else {

    }
    }
#line 1137
    i = 0;
#line 1137
    goto ldv_38287;
    ldv_38286: 
    {
#line 1138
    __cil_tmp27 = intel_crtc->pipe;
#line 1138
    __cil_tmp28 = (int )__cil_tmp27;
#line 1138
    intel_wait_for_vblank(dev, __cil_tmp28);
#line 1137
    i = i + 1;
    }
    ldv_38287: ;
#line 1137
    if (i <= 1) {
#line 1138
      goto ldv_38286;
    } else {
#line 1140
      goto ldv_38288;
    }
    ldv_38288: 
    {
#line 1140
    tmp___0 = intel_sdvo_get_trained_inputs(intel_sdvo, & input1, & input2);
#line 1140
    status = (u8 )tmp___0;
    }
    {
#line 1145
    __cil_tmp29 = (unsigned int )status;
#line 1145
    if (__cil_tmp29 == 1U) {
#line 1145
      if (! input1) {
        {
#line 1146
        __cil_tmp30 = intel_sdvo->sdvo_reg;
#line 1146
        if (__cil_tmp30 == 397632) {
#line 1146
          tmp___1 = (char *)"SDVOB";
        } else {
          {
#line 1146
          __cil_tmp31 = intel_sdvo->sdvo_reg;
#line 1146
          if (__cil_tmp31 == 921920) {
#line 1146
            tmp___1 = (char *)"SDVOB";
          } else {
#line 1146
            tmp___1 = (char *)"SDVOC";
          }
          }
        }
        }
        {
#line 1146
        drm_ut_debug_printk(4U, "drm", "intel_sdvo_dpms", "First %s output reported failure to sync\n",
                            tmp___1);
        }
      } else {

      }
    } else {

    }
    }
    {
#line 1152
    __cil_tmp32 = intel_sdvo->attached_output;
#line 1152
    __cil_tmp33 = (int )__cil_tmp32;
#line 1152
    __cil_tmp34 = (u16 )__cil_tmp33;
#line 1152
    intel_sdvo_set_active_outputs(intel_sdvo, __cil_tmp34);
    }
  }
#line 1154
  return;
}
}
#line 1157 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static int intel_sdvo_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  unsigned int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  bool __cil_tmp11 ;
  struct drm_display_mode *__cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  struct drm_display_mode *__cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;

  {
  {
#line 1160
  tmp = intel_attached_sdvo(connector);
#line 1160
  intel_sdvo = tmp;
  }
  {
#line 1162
  __cil_tmp5 = mode->flags;
#line 1162
  __cil_tmp6 = __cil_tmp5 & 32U;
#line 1162
  if (__cil_tmp6 != 0U) {
#line 1163
    return (8);
  } else {

  }
  }
  {
#line 1165
  __cil_tmp7 = mode->clock;
#line 1165
  __cil_tmp8 = intel_sdvo->pixel_clock_min;
#line 1165
  if (__cil_tmp8 > __cil_tmp7) {
#line 1166
    return (16);
  } else {

  }
  }
  {
#line 1168
  __cil_tmp9 = mode->clock;
#line 1168
  __cil_tmp10 = intel_sdvo->pixel_clock_max;
#line 1168
  if (__cil_tmp10 < __cil_tmp9) {
#line 1169
    return (15);
  } else {

  }
  }
  {
#line 1171
  __cil_tmp11 = intel_sdvo->is_lvds;
#line 1171
  if ((int )__cil_tmp11) {
    {
#line 1172
    __cil_tmp12 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 1172
    __cil_tmp13 = __cil_tmp12->hdisplay;
#line 1172
    __cil_tmp14 = mode->hdisplay;
#line 1172
    if (__cil_tmp14 > __cil_tmp13) {
#line 1173
      return (29);
    } else {

    }
    }
    {
#line 1175
    __cil_tmp15 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 1175
    __cil_tmp16 = __cil_tmp15->vdisplay;
#line 1175
    __cil_tmp17 = mode->vdisplay;
#line 1175
    if (__cil_tmp17 > __cil_tmp16) {
#line 1176
      return (29);
    } else {

    }
    }
  } else {

  }
  }
#line 1179
  return (0);
}
}
#line 1182 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo , struct intel_sdvo_caps *caps ) 
{ bool tmp ;
  int tmp___0 ;
  u8 __cil_tmp5 ;
  void *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  int __cil_tmp8 ;
  u8 __cil_tmp9 ;
  int __cil_tmp10 ;
  u8 __cil_tmp11 ;
  int __cil_tmp12 ;
  u8 __cil_tmp13 ;
  int __cil_tmp14 ;
  u8 __cil_tmp15 ;
  int __cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  int __cil_tmp18 ;
  unsigned char __cil_tmp19 ;
  int __cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  int __cil_tmp22 ;
  unsigned char __cil_tmp23 ;
  int __cil_tmp24 ;
  unsigned char __cil_tmp25 ;
  int __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  int __cil_tmp28 ;
  u16 __cil_tmp29 ;
  int __cil_tmp30 ;

  {
  {
#line 1185
  __cil_tmp5 = (u8 )2;
#line 1185
  __cil_tmp6 = (void *)caps;
#line 1185
  tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp5, __cil_tmp6, 8);
  }
#line 1185
  if (tmp) {
#line 1185
    tmp___0 = 0;
  } else {
#line 1185
    tmp___0 = 1;
  }
#line 1185
  if (tmp___0) {
#line 1188
    return ((bool )0);
  } else {

  }
  {
#line 1190
  __cil_tmp7 = caps->vendor_id;
#line 1190
  __cil_tmp8 = (int )__cil_tmp7;
#line 1190
  __cil_tmp9 = caps->device_id;
#line 1190
  __cil_tmp10 = (int )__cil_tmp9;
#line 1190
  __cil_tmp11 = caps->device_rev_id;
#line 1190
  __cil_tmp12 = (int )__cil_tmp11;
#line 1190
  __cil_tmp13 = caps->sdvo_version_major;
#line 1190
  __cil_tmp14 = (int )__cil_tmp13;
#line 1190
  __cil_tmp15 = caps->sdvo_version_minor;
#line 1190
  __cil_tmp16 = (int )__cil_tmp15;
#line 1190
  __cil_tmp17 = caps->sdvo_inputs_mask;
#line 1190
  __cil_tmp18 = (int )__cil_tmp17;
#line 1190
  __cil_tmp19 = caps->smooth_scaling;
#line 1190
  __cil_tmp20 = (int )__cil_tmp19;
#line 1190
  __cil_tmp21 = caps->sharp_scaling;
#line 1190
  __cil_tmp22 = (int )__cil_tmp21;
#line 1190
  __cil_tmp23 = caps->up_scaling;
#line 1190
  __cil_tmp24 = (int )__cil_tmp23;
#line 1190
  __cil_tmp25 = caps->down_scaling;
#line 1190
  __cil_tmp26 = (int )__cil_tmp25;
#line 1190
  __cil_tmp27 = caps->stall_support;
#line 1190
  __cil_tmp28 = (int )__cil_tmp27;
#line 1190
  __cil_tmp29 = caps->output_flags;
#line 1190
  __cil_tmp30 = (int )__cil_tmp29;
#line 1190
  drm_ut_debug_printk(4U, "drm", "intel_sdvo_get_capabilities", "SDVO capabilities:\n  vendor_id: %d\n  device_id: %d\n  device_rev_id: %d\n  sdvo_version_major: %d\n  sdvo_version_minor: %d\n  sdvo_inputs_mask: %d\n  smooth_scaling: %d\n  sharp_scaling: %d\n  up_scaling: %d\n  down_scaling: %d\n  stall_support: %d\n  output_flags: %d\n",
                      __cil_tmp8, __cil_tmp10, __cil_tmp12, __cil_tmp14, __cil_tmp16,
                      __cil_tmp18, __cil_tmp20, __cil_tmp22, __cil_tmp24, __cil_tmp26,
                      __cil_tmp28, __cil_tmp30);
  }
#line 1216
  return ((bool )1);
}
}
#line 1289 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo ) 
{ int caps ;
  u16 __cil_tmp3 ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;

  {
#line 1292
  __cil_tmp3 = intel_sdvo->caps.output_flags;
#line 1292
  __cil_tmp4 = (int )__cil_tmp3;
#line 1292
  caps = __cil_tmp4 & 15;
  {
#line 1293
  __cil_tmp5 = - caps;
#line 1293
  __cil_tmp6 = __cil_tmp5 & caps;
#line 1293
  __cil_tmp7 = __cil_tmp6 != 0;
#line 1293
  return ((bool )__cil_tmp7);
  }
}
}
#line 1297 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct edid *intel_sdvo_get_edid(struct drm_connector *connector ) 
{ struct intel_sdvo *sdvo ;
  struct intel_sdvo *tmp ;
  struct edid *tmp___0 ;
  struct i2c_adapter *__cil_tmp5 ;

  {
  {
#line 1299
  tmp = intel_attached_sdvo(connector);
#line 1299
  sdvo = tmp;
#line 1300
  __cil_tmp5 = & sdvo->ddc;
#line 1300
  tmp___0 = drm_get_edid(connector, __cil_tmp5);
  }
#line 1300
  return (tmp___0);
}
}
#line 1305 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct edid *intel_sdvo_get_analog_edid(struct drm_connector *connector ) 
{ struct drm_i915_private *dev_priv ;
  struct edid *tmp ;
  struct drm_device *__cil_tmp4 ;
  void *__cil_tmp5 ;
  int __cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct intel_gmbus *__cil_tmp8 ;
  struct intel_gmbus *__cil_tmp9 ;
  struct i2c_adapter *__cil_tmp10 ;

  {
  {
#line 1307
  __cil_tmp4 = connector->dev;
#line 1307
  __cil_tmp5 = __cil_tmp4->dev_private;
#line 1307
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 1309
  __cil_tmp6 = dev_priv->crt_ddc_pin;
#line 1309
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 1309
  __cil_tmp8 = dev_priv->gmbus;
#line 1309
  __cil_tmp9 = __cil_tmp8 + __cil_tmp7;
#line 1309
  __cil_tmp10 = & __cil_tmp9->adapter;
#line 1309
  tmp = drm_get_edid(connector, __cil_tmp10);
  }
#line 1309
  return (tmp);
}
}
#line 1314 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
enum drm_connector_status intel_sdvo_hdmi_sink_detect(struct drm_connector *connector ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  enum drm_connector_status status ;
  struct edid *edid ;
  u8 ddc ;
  u8 saved_ddc ;
  bool tmp___0 ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp___1 ;
  struct edid *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  uint8_t __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  struct edid *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  struct edid *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct edid *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  struct edid *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  u8 __cil_tmp32 ;
  signed char __cil_tmp33 ;
  int __cil_tmp34 ;
  bool __cil_tmp35 ;
  void const   *__cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;

  {
  {
#line 1316
  tmp = intel_attached_sdvo(connector);
#line 1316
  intel_sdvo = tmp;
#line 1320
  edid = intel_sdvo_get_edid(connector);
  }
  {
#line 1322
  __cil_tmp11 = (struct edid *)0;
#line 1322
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 1322
  __cil_tmp13 = (unsigned long )edid;
#line 1322
  if (__cil_tmp13 == __cil_tmp12) {
    {
#line 1322
    tmp___0 = intel_sdvo_multifunc_encoder(intel_sdvo);
    }
#line 1322
    if ((int )tmp___0) {
#line 1323
      saved_ddc = intel_sdvo->ddc_bus;
#line 1329
      __cil_tmp14 = intel_sdvo->ddc_bus;
#line 1329
      __cil_tmp15 = (int )__cil_tmp14;
#line 1329
      __cil_tmp16 = __cil_tmp15 >> 1;
#line 1329
      ddc = (u8 )__cil_tmp16;
#line 1329
      goto ldv_38322;
      ldv_38321: 
      {
#line 1330
      intel_sdvo->ddc_bus = ddc;
#line 1331
      edid = intel_sdvo_get_edid(connector);
      }
      {
#line 1332
      __cil_tmp17 = (struct edid *)0;
#line 1332
      __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 1332
      __cil_tmp19 = (unsigned long )edid;
#line 1332
      if (__cil_tmp19 != __cil_tmp18) {
#line 1333
        goto ldv_38320;
      } else {

      }
      }
#line 1329
      __cil_tmp20 = (int )ddc;
#line 1329
      __cil_tmp21 = __cil_tmp20 >> 1;
#line 1329
      ddc = (u8 )__cil_tmp21;
      ldv_38322: ;
      {
#line 1329
      __cil_tmp22 = (unsigned int )ddc;
#line 1329
      if (__cil_tmp22 > 1U) {
#line 1330
        goto ldv_38321;
      } else {
#line 1332
        goto ldv_38320;
      }
      }
      ldv_38320: ;
      {
#line 1339
      __cil_tmp23 = (struct edid *)0;
#line 1339
      __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 1339
      __cil_tmp25 = (unsigned long )edid;
#line 1339
      if (__cil_tmp25 == __cil_tmp24) {
#line 1340
        intel_sdvo->ddc_bus = saved_ddc;
      } else {

      }
      }
    } else {

    }
  } else {

  }
  }
  {
#line 1347
  __cil_tmp26 = (struct edid *)0;
#line 1347
  __cil_tmp27 = (unsigned long )__cil_tmp26;
#line 1347
  __cil_tmp28 = (unsigned long )edid;
#line 1347
  if (__cil_tmp28 == __cil_tmp27) {
    {
#line 1348
    edid = intel_sdvo_get_analog_edid(connector);
    }
  } else {

  }
  }
#line 1350
  status = (enum drm_connector_status )3;
  {
#line 1351
  __cil_tmp29 = (struct edid *)0;
#line 1351
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 1351
  __cil_tmp31 = (unsigned long )edid;
#line 1351
  if (__cil_tmp31 != __cil_tmp30) {
    {
#line 1353
    __cil_tmp32 = edid->input;
#line 1353
    __cil_tmp33 = (signed char )__cil_tmp32;
#line 1353
    __cil_tmp34 = (int )__cil_tmp33;
#line 1353
    if (__cil_tmp34 < 0) {
#line 1354
      status = (enum drm_connector_status )1;
      {
#line 1355
      __cil_tmp35 = intel_sdvo->is_hdmi;
#line 1355
      if ((int )__cil_tmp35) {
        {
#line 1356
        intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
#line 1357
        intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
        }
      } else {

      }
      }
    } else {
#line 1360
      status = (enum drm_connector_status )2;
    }
    }
    {
#line 1361
    connector->display_info.raw_edid = (char *)0;
#line 1362
    __cil_tmp36 = (void const   *)edid;
#line 1362
    kfree(__cil_tmp36);
    }
  } else {

  }
  }
  {
#line 1365
  __cil_tmp37 = (unsigned int )status;
#line 1365
  if (__cil_tmp37 == 1U) {
    {
#line 1366
    tmp___1 = to_intel_sdvo_connector(connector);
#line 1366
    intel_sdvo_connector = tmp___1;
    }
    {
#line 1367
    __cil_tmp38 = intel_sdvo_connector->force_audio;
#line 1367
    if (__cil_tmp38 != 0) {
#line 1368
      __cil_tmp39 = intel_sdvo_connector->force_audio;
#line 1368
      __cil_tmp40 = __cil_tmp39 > 0;
#line 1368
      intel_sdvo->has_hdmi_audio = (bool )__cil_tmp40;
    } else {

    }
    }
  } else {

  }
  }
#line 1371
  return (status);
}
}
#line 1375 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector ,
                                                   bool force ) 
{ uint16_t response ;
  struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp___0 ;
  enum drm_connector_status ret ;
  bool tmp___1 ;
  int tmp___2 ;
  unsigned long __ms ;
  unsigned long tmp___3 ;
  bool tmp___4 ;
  int tmp___5 ;
  struct edid *edid ;
  u8 __cil_tmp16 ;
  void const   *__cil_tmp17 ;
  u16 __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  void *__cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  uint16_t __cil_tmp26 ;
  int __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  int __cil_tmp29 ;
  uint16_t __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  uint16_t __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  struct edid *__cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  struct edid *__cil_tmp40 ;
  unsigned long __cil_tmp41 ;
  unsigned long __cil_tmp42 ;
  u8 __cil_tmp43 ;
  signed char __cil_tmp44 ;
  int __cil_tmp45 ;
  void const   *__cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  int __cil_tmp48 ;
  int __cil_tmp49 ;
  int __cil_tmp50 ;
  int __cil_tmp51 ;
  struct drm_display_mode *__cil_tmp52 ;
  unsigned long __cil_tmp53 ;
  struct drm_display_mode *__cil_tmp54 ;
  unsigned long __cil_tmp55 ;
  int __cil_tmp56 ;

  {
  {
#line 1378
  tmp = intel_attached_sdvo(connector);
#line 1378
  intel_sdvo = tmp;
#line 1379
  tmp___0 = to_intel_sdvo_connector(connector);
#line 1379
  intel_sdvo_connector = tmp___0;
#line 1382
  __cil_tmp16 = (u8 )11;
#line 1382
  __cil_tmp17 = (void const   *)0;
#line 1382
  tmp___1 = intel_sdvo_write_cmd(intel_sdvo, __cil_tmp16, __cil_tmp17, 0);
  }
#line 1382
  if (tmp___1) {
#line 1382
    tmp___2 = 0;
  } else {
#line 1382
    tmp___2 = 1;
  }
#line 1382
  if (tmp___2) {
#line 1384
    return ((enum drm_connector_status )3);
  } else {

  }
  {
#line 1387
  __cil_tmp18 = intel_sdvo->caps.output_flags;
#line 1387
  __cil_tmp19 = (int )__cil_tmp18;
#line 1387
  __cil_tmp20 = __cil_tmp19 & 12;
#line 1387
  if (__cil_tmp20 != 0) {
#line 1389
    __ms = 30UL;
#line 1389
    goto ldv_38334;
    ldv_38333: 
    {
#line 1389
    __const_udelay(4295000UL);
    }
    ldv_38334: 
#line 1389
    tmp___3 = __ms;
#line 1389
    __ms = __ms - 1UL;
#line 1389
    if (tmp___3 != 0UL) {
#line 1390
      goto ldv_38333;
    } else {
#line 1392
      goto ldv_38335;
    }
    ldv_38335: ;
  } else {

  }
  }
  {
#line 1391
  __cil_tmp21 = (void *)(& response);
#line 1391
  tmp___4 = intel_sdvo_read_response(intel_sdvo, __cil_tmp21, 2);
  }
#line 1391
  if (tmp___4) {
#line 1391
    tmp___5 = 0;
  } else {
#line 1391
    tmp___5 = 1;
  }
#line 1391
  if (tmp___5) {
#line 1392
    return ((enum drm_connector_status )3);
  } else {

  }
  {
#line 1394
  __cil_tmp22 = (int )response;
#line 1394
  __cil_tmp23 = __cil_tmp22 & 255;
#line 1394
  __cil_tmp24 = (int )response;
#line 1394
  __cil_tmp25 = __cil_tmp24 >> 8;
#line 1394
  __cil_tmp26 = intel_sdvo_connector->output_flag;
#line 1394
  __cil_tmp27 = (int )__cil_tmp26;
#line 1394
  drm_ut_debug_printk(4U, "drm", "intel_sdvo_detect", "SDVO response %d %d [%x]\n",
                      __cil_tmp23, __cil_tmp25, __cil_tmp27);
  }
  {
#line 1398
  __cil_tmp28 = (unsigned int )response;
#line 1398
  if (__cil_tmp28 == 0U) {
#line 1399
    return ((enum drm_connector_status )2);
  } else {

  }
  }
#line 1401
  intel_sdvo->attached_output = response;
#line 1403
  intel_sdvo->has_hdmi_monitor = (bool )0;
#line 1404
  intel_sdvo->has_hdmi_audio = (bool )0;
  {
#line 1406
  __cil_tmp29 = (int )response;
#line 1406
  __cil_tmp30 = intel_sdvo_connector->output_flag;
#line 1406
  __cil_tmp31 = (int )__cil_tmp30;
#line 1406
  __cil_tmp32 = __cil_tmp31 & __cil_tmp29;
#line 1406
  __cil_tmp33 = (unsigned int )__cil_tmp32;
#line 1406
  if (__cil_tmp33 == 0U) {
#line 1407
    ret = (enum drm_connector_status )2;
  } else {
    {
#line 1408
    __cil_tmp34 = intel_sdvo_connector->output_flag;
#line 1408
    __cil_tmp35 = (int )__cil_tmp34;
#line 1408
    __cil_tmp36 = __cil_tmp35 & 257;
#line 1408
    if (__cil_tmp36 != 0) {
      {
#line 1409
      ret = intel_sdvo_hdmi_sink_detect(connector);
      }
    } else {
      {
#line 1414
      edid = intel_sdvo_get_edid(connector);
      }
      {
#line 1415
      __cil_tmp37 = (struct edid *)0;
#line 1415
      __cil_tmp38 = (unsigned long )__cil_tmp37;
#line 1415
      __cil_tmp39 = (unsigned long )edid;
#line 1415
      if (__cil_tmp39 == __cil_tmp38) {
        {
#line 1416
        edid = intel_sdvo_get_analog_edid(connector);
        }
      } else {

      }
      }
      {
#line 1417
      __cil_tmp40 = (struct edid *)0;
#line 1417
      __cil_tmp41 = (unsigned long )__cil_tmp40;
#line 1417
      __cil_tmp42 = (unsigned long )edid;
#line 1417
      if (__cil_tmp42 != __cil_tmp41) {
        {
#line 1418
        __cil_tmp43 = edid->input;
#line 1418
        __cil_tmp44 = (signed char )__cil_tmp43;
#line 1418
        __cil_tmp45 = (int )__cil_tmp44;
#line 1418
        if (__cil_tmp45 < 0) {
#line 1419
          ret = (enum drm_connector_status )2;
        } else {
#line 1421
          ret = (enum drm_connector_status )1;
        }
        }
        {
#line 1422
        connector->display_info.raw_edid = (char *)0;
#line 1423
        __cil_tmp46 = (void const   *)edid;
#line 1423
        kfree(__cil_tmp46);
        }
      } else {
#line 1425
        ret = (enum drm_connector_status )1;
      }
      }
    }
    }
  }
  }
  {
#line 1429
  __cil_tmp47 = (unsigned int )ret;
#line 1429
  if (__cil_tmp47 == 1U) {
#line 1430
    intel_sdvo->is_tv = (bool )0;
#line 1431
    intel_sdvo->is_lvds = (bool )0;
#line 1432
    intel_sdvo->base.needs_tv_clock = (bool )0;
    {
#line 1434
    __cil_tmp48 = (int )response;
#line 1434
    __cil_tmp49 = __cil_tmp48 & 12;
#line 1434
    if (__cil_tmp49 != 0) {
#line 1435
      intel_sdvo->is_tv = (bool )1;
#line 1436
      intel_sdvo->base.needs_tv_clock = (bool )1;
    } else {

    }
    }
    {
#line 1438
    __cil_tmp50 = (int )response;
#line 1438
    __cil_tmp51 = __cil_tmp50 & 16448;
#line 1438
    if (__cil_tmp51 != 0) {
#line 1439
      __cil_tmp52 = (struct drm_display_mode *)0;
#line 1439
      __cil_tmp53 = (unsigned long )__cil_tmp52;
#line 1439
      __cil_tmp54 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 1439
      __cil_tmp55 = (unsigned long )__cil_tmp54;
#line 1439
      __cil_tmp56 = __cil_tmp55 != __cil_tmp53;
#line 1439
      intel_sdvo->is_lvds = (bool )__cil_tmp56;
    } else {

    }
    }
  } else {

  }
  }
#line 1442
  return (ret);
}
}
#line 1445 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_get_ddc_modes(struct drm_connector *connector ) 
{ struct edid *edid ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp ;
  bool monitor_is_digital ;
  bool connector_is_digital ;
  struct edid *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct edid *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  u8 __cil_tmp13 ;
  signed char __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  uint16_t __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  void const   *__cil_tmp23 ;

  {
  {
#line 1450
  edid = intel_sdvo_get_edid(connector);
  }
  {
#line 1458
  __cil_tmp7 = (struct edid *)0;
#line 1458
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1458
  __cil_tmp9 = (unsigned long )edid;
#line 1458
  if (__cil_tmp9 == __cil_tmp8) {
    {
#line 1459
    edid = intel_sdvo_get_analog_edid(connector);
    }
  } else {

  }
  }
  {
#line 1461
  __cil_tmp10 = (struct edid *)0;
#line 1461
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 1461
  __cil_tmp12 = (unsigned long )edid;
#line 1461
  if (__cil_tmp12 != __cil_tmp11) {
    {
#line 1462
    tmp = to_intel_sdvo_connector(connector);
#line 1462
    intel_sdvo_connector = tmp;
#line 1463
    __cil_tmp13 = edid->input;
#line 1463
    __cil_tmp14 = (signed char )__cil_tmp13;
#line 1463
    __cil_tmp15 = (int )__cil_tmp14;
#line 1463
    __cil_tmp16 = __cil_tmp15 < 0;
#line 1463
    monitor_is_digital = (bool )__cil_tmp16;
#line 1464
    __cil_tmp17 = intel_sdvo_connector->output_flag;
#line 1464
    __cil_tmp18 = (int )__cil_tmp17;
#line 1464
    __cil_tmp19 = __cil_tmp18 & 257;
#line 1464
    __cil_tmp20 = __cil_tmp19 != 0;
#line 1464
    connector_is_digital = (bool )__cil_tmp20;
    }
    {
#line 1466
    __cil_tmp21 = (int )monitor_is_digital;
#line 1466
    __cil_tmp22 = (int )connector_is_digital;
#line 1466
    if (__cil_tmp22 == __cil_tmp21) {
      {
#line 1467
      drm_mode_connector_update_edid_property(connector, edid);
#line 1468
      drm_add_edid_modes(connector, edid);
      }
    } else {

    }
    }
    {
#line 1471
    connector->display_info.raw_edid = (char *)0;
#line 1472
    __cil_tmp23 = (void const   *)edid;
#line 1472
    kfree(__cil_tmp23);
    }
  } else {

  }
  }
#line 1474
  return;
}
}
#line 1481 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct drm_display_mode  const  sdvo_tv_modes[19U]  = 
#line 1481
  {      {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'3', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'2', (char )'0',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 5815, 320, 321, 384, 416, 0, 200, 201, 232,
      233, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'3', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'2', (char )'4',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 6814, 320, 321, 384, 416, 0, 240, 241, 272,
      273, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'4', (char )'0',
                                                                 (char )'0', (char )'x',
                                                                 (char )'3', (char )'0',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 9910, 400, 401, 464, 496, 0, 300, 301, 332,
      333, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'6', (char )'4',
                                                                 (char )'0', (char )'x',
                                                                 (char )'3', (char )'5',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 16913, 640, 641, 704, 736, 0, 350, 351, 382,
      383, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'6', (char )'4',
                                                                 (char )'0', (char )'x',
                                                                 (char )'4', (char )'0',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 19121, 640, 641, 704, 736, 0, 400, 401, 432,
      433, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'6', (char )'4',
                                                                 (char )'0', (char )'x',
                                                                 (char )'4', (char )'8',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 22654, 640, 641, 704, 736, 0, 480, 481, 512,
      513, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'0',
                                                                 (char )'4', (char )'x',
                                                                 (char )'4', (char )'8',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 24624, 704, 705, 768, 800, 0, 480, 481, 512,
      513, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'0',
                                                                 (char )'4', (char )'x',
                                                                 (char )'5', (char )'7',
                                                                 (char )'6', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 29232, 704, 705, 768, 800, 0, 576, 577, 608,
      609, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'3', (char )'5',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 18751, 720, 721, 784, 816, 0, 350, 351, 382,
      383, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'4', (char )'0',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 21199, 720, 721, 784, 816, 0, 400, 401, 432,
      433, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'4', (char )'8',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 25116, 720, 721, 784, 816, 0, 480, 481, 512,
      513, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'5', (char )'4',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 28054, 720, 721, 784, 816, 0, 540, 541, 572,
      573, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'5', (char )'7',
                                                                 (char )'6', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 29816, 720, 721, 784, 816, 0, 576, 577, 608,
      609, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'7', (char )'6',
                                                                 (char )'8', (char )'x',
                                                                 (char )'5', (char )'7',
                                                                 (char )'6', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 31570, 768, 769, 832, 864, 0, 576, 577, 608,
      609, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'8', (char )'0',
                                                                 (char )'0', (char )'x',
                                                                 (char )'6', (char )'0',
                                                                 (char )'0', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 34030, 800, 801, 864, 896, 0, 600, 601, 632,
      633, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'8', (char )'3',
                                                                 (char )'2', (char )'x',
                                                                 (char )'6', (char )'2',
                                                                 (char )'4', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 36581, 832, 833, 896, 928, 0, 624, 625, 656,
      657, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'9', (char )'2',
                                                                 (char )'0', (char )'x',
                                                                 (char )'7', (char )'6',
                                                                 (char )'6', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 48707, 920, 921, 984, 1016, 0, 766, 767, 798,
      799, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'1', (char )'0',
                                                                 (char )'2', (char )'4',
                                                                 (char )'x', (char )'7',
                                                                 (char )'6', (char )'8',
                                                                 (char )'\000'}, 0,
      (enum drm_mode_status )0, 64, 53827, 1024, 1025, 1088, 1120, 0, 768, 769, 800,
      801, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, (int *)0,
      0, 0, 0}, 
        {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'1', (char )'2',
                                                                 (char )'8', (char )'0',
                                                                 (char )'x', (char )'1',
                                                                 (char )'0', (char )'2',
                                                                 (char )'4', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 87265, 1280, 1281, 1344, 1376, 0, 1024, 1025,
      1056, 1057, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, (int *)0, 0, 0, 0}};
#line 1541 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_get_tv_modes(struct drm_connector *connector ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct intel_sdvo_sdtv_resolution_request tv_res ;
  uint32_t reply ;
  uint32_t format_map ;
  int i ;
  size_t __len ;
  unsigned long _min1 ;
  unsigned long _min2 ;
  unsigned long tmp___0 ;
  void *__ret ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  bool tmp___5 ;
  int tmp___6 ;
  struct drm_display_mode *nmode ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  void *__cil_tmp22 ;
  void const   *__cil_tmp23 ;
  uint16_t __cil_tmp24 ;
  int __cil_tmp25 ;
  u16 __cil_tmp26 ;
  u8 __cil_tmp27 ;
  void const   *__cil_tmp28 ;
  void *__cil_tmp29 ;
  int __cil_tmp30 ;
  uint32_t __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  struct drm_device *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  struct drm_display_mode  const  *__cil_tmp35 ;
  struct drm_display_mode  const  *__cil_tmp36 ;
  struct drm_display_mode *__cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  unsigned int __cil_tmp40 ;

  {
  {
#line 1543
  tmp = intel_attached_sdvo(connector);
#line 1543
  intel_sdvo = tmp;
#line 1545
  reply = 0U;
#line 1545
  format_map = 0U;
#line 1551
  __cil_tmp20 = intel_sdvo->tv_format_index;
#line 1551
  __cil_tmp21 = 1 << __cil_tmp20;
#line 1551
  format_map = (uint32_t )__cil_tmp21;
#line 1552
  _min1 = 4UL;
#line 1552
  _min2 = 3UL;
  }
#line 1552
  if (_min1 < _min2) {
#line 1552
    tmp___0 = _min1;
  } else {
#line 1552
    tmp___0 = _min2;
  }
  {
#line 1552
  __len = tmp___0;
#line 1552
  __cil_tmp22 = (void *)(& tv_res);
#line 1552
  __cil_tmp23 = (void const   *)(& format_map);
#line 1552
  __ret = __builtin_memcpy(__cil_tmp22, __cil_tmp23, __len);
#line 1555
  __cil_tmp24 = intel_sdvo->attached_output;
#line 1555
  __cil_tmp25 = (int )__cil_tmp24;
#line 1555
  __cil_tmp26 = (u16 )__cil_tmp25;
#line 1555
  tmp___1 = intel_sdvo_set_target_output(intel_sdvo, __cil_tmp26);
  }
#line 1555
  if (tmp___1) {
#line 1555
    tmp___2 = 0;
  } else {
#line 1555
    tmp___2 = 1;
  }
#line 1555
  if (tmp___2) {
#line 1556
    return;
  } else {

  }
  {
#line 1559
  __cil_tmp27 = (u8 )131;
#line 1559
  __cil_tmp28 = (void const   *)(& tv_res);
#line 1559
  tmp___3 = intel_sdvo_write_cmd(intel_sdvo, __cil_tmp27, __cil_tmp28, 3);
  }
#line 1559
  if (tmp___3) {
#line 1559
    tmp___4 = 0;
  } else {
#line 1559
    tmp___4 = 1;
  }
#line 1559
  if (tmp___4) {
#line 1562
    return;
  } else {

  }
  {
#line 1563
  __cil_tmp29 = (void *)(& reply);
#line 1563
  tmp___5 = intel_sdvo_read_response(intel_sdvo, __cil_tmp29, 3);
  }
#line 1563
  if (tmp___5) {
#line 1563
    tmp___6 = 0;
  } else {
#line 1563
    tmp___6 = 1;
  }
#line 1563
  if (tmp___6) {
#line 1564
    return;
  } else {

  }
#line 1566
  i = 0;
#line 1566
  goto ldv_38367;
  ldv_38366: ;
  {
#line 1567
  __cil_tmp30 = 1 << i;
#line 1567
  __cil_tmp31 = (uint32_t )__cil_tmp30;
#line 1567
  __cil_tmp32 = __cil_tmp31 & reply;
#line 1567
  if (__cil_tmp32 != 0U) {
    {
#line 1569
    __cil_tmp33 = connector->dev;
#line 1569
    __cil_tmp34 = (unsigned long )i;
#line 1569
    __cil_tmp35 = (struct drm_display_mode  const  *)(& sdvo_tv_modes);
#line 1569
    __cil_tmp36 = __cil_tmp35 + __cil_tmp34;
#line 1569
    nmode = drm_mode_duplicate(__cil_tmp33, __cil_tmp36);
    }
    {
#line 1571
    __cil_tmp37 = (struct drm_display_mode *)0;
#line 1571
    __cil_tmp38 = (unsigned long )__cil_tmp37;
#line 1571
    __cil_tmp39 = (unsigned long )nmode;
#line 1571
    if (__cil_tmp39 != __cil_tmp38) {
      {
#line 1572
      drm_mode_probed_add(connector, nmode);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 1566
  i = i + 1;
  ldv_38367: ;
  {
#line 1566
  __cil_tmp40 = (unsigned int )i;
#line 1566
  if (__cil_tmp40 <= 18U) {
#line 1567
    goto ldv_38366;
  } else {
#line 1569
    goto ldv_38368;
  }
  }
  ldv_38368: ;
#line 1571
  return;
}
}
#line 1576 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_get_lvds_modes(struct drm_connector *connector ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct drm_i915_private *dev_priv ;
  struct drm_display_mode *newmode ;
  int tmp___0 ;
  struct list_head  const  *__mptr ;
  struct list_head  const  *__mptr___0 ;
  struct drm_device *__cil_tmp9 ;
  void *__cil_tmp10 ;
  struct i2c_adapter *__cil_tmp11 ;
  struct list_head *__cil_tmp12 ;
  struct list_head  const  *__cil_tmp13 ;
  struct drm_display_mode *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct drm_display_mode *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_device *__cil_tmp18 ;
  struct drm_display_mode *__cil_tmp19 ;
  struct drm_display_mode  const  *__cil_tmp20 ;
  struct drm_display_mode *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct list_head *__cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  struct drm_device *__cil_tmp27 ;
  struct drm_display_mode  const  *__cil_tmp28 ;
  struct drm_display_mode *__cil_tmp29 ;
  struct list_head *__cil_tmp30 ;
  struct list_head *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  struct list_head *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;

  {
  {
#line 1578
  tmp = intel_attached_sdvo(connector);
#line 1578
  intel_sdvo = tmp;
#line 1579
  __cil_tmp9 = connector->dev;
#line 1579
  __cil_tmp10 = __cil_tmp9->dev_private;
#line 1579
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 1587
  __cil_tmp11 = intel_sdvo->i2c;
#line 1587
  intel_ddc_get_modes(connector, __cil_tmp11);
#line 1588
  __cil_tmp12 = & connector->probed_modes;
#line 1588
  __cil_tmp13 = (struct list_head  const  *)__cil_tmp12;
#line 1588
  tmp___0 = list_empty(__cil_tmp13);
  }
#line 1588
  if (tmp___0 == 0) {
#line 1589
    goto end;
  } else {

  }
  {
#line 1592
  __cil_tmp14 = (struct drm_display_mode *)0;
#line 1592
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 1592
  __cil_tmp16 = dev_priv->sdvo_lvds_vbt_mode;
#line 1592
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 1592
  if (__cil_tmp17 != __cil_tmp15) {
    {
#line 1593
    __cil_tmp18 = connector->dev;
#line 1593
    __cil_tmp19 = dev_priv->sdvo_lvds_vbt_mode;
#line 1593
    __cil_tmp20 = (struct drm_display_mode  const  *)__cil_tmp19;
#line 1593
    newmode = drm_mode_duplicate(__cil_tmp18, __cil_tmp20);
    }
    {
#line 1595
    __cil_tmp21 = (struct drm_display_mode *)0;
#line 1595
    __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 1595
    __cil_tmp23 = (unsigned long )newmode;
#line 1595
    if (__cil_tmp23 != __cil_tmp22) {
      {
#line 1597
      newmode->type = 72;
#line 1599
      drm_mode_probed_add(connector, newmode);
      }
    } else {

    }
    }
  } else {

  }
  }
  end: 
#line 1604
  __cil_tmp24 = connector->probed_modes.next;
#line 1604
  __mptr = (struct list_head  const  *)__cil_tmp24;
#line 1604
  newmode = (struct drm_display_mode *)__mptr;
#line 1604
  goto ldv_38382;
  ldv_38381: ;
  {
#line 1605
  __cil_tmp25 = newmode->type;
#line 1605
  __cil_tmp26 = __cil_tmp25 & 8;
#line 1605
  if (__cil_tmp26 != 0) {
    {
#line 1606
    __cil_tmp27 = connector->dev;
#line 1606
    __cil_tmp28 = (struct drm_display_mode  const  *)newmode;
#line 1606
    intel_sdvo->sdvo_lvds_fixed_mode = drm_mode_duplicate(__cil_tmp27, __cil_tmp28);
#line 1609
    __cil_tmp29 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 1609
    drm_mode_set_crtcinfo(__cil_tmp29, 0);
#line 1612
    intel_sdvo->is_lvds = (bool )1;
    }
#line 1613
    goto ldv_38380;
  } else {

  }
  }
#line 1604
  __cil_tmp30 = newmode->head.next;
#line 1604
  __mptr___0 = (struct list_head  const  *)__cil_tmp30;
#line 1604
  newmode = (struct drm_display_mode *)__mptr___0;
  ldv_38382: ;
  {
#line 1604
  __cil_tmp31 = & connector->probed_modes;
#line 1604
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 1604
  __cil_tmp33 = & newmode->head;
#line 1604
  __cil_tmp34 = (unsigned long )__cil_tmp33;
#line 1604
  if (__cil_tmp34 != __cil_tmp32) {
#line 1605
    goto ldv_38381;
  } else {
#line 1607
    goto ldv_38380;
  }
  }
  ldv_38380: ;
#line 1609
  return;
}
}
#line 1619 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static int intel_sdvo_get_modes(struct drm_connector *connector ) 
{ struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp ;
  int tmp___0 ;
  uint16_t __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  uint16_t __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  struct list_head *__cil_tmp11 ;
  struct list_head  const  *__cil_tmp12 ;

  {
  {
#line 1621
  tmp = to_intel_sdvo_connector(connector);
#line 1621
  intel_sdvo_connector = tmp;
  }
  {
#line 1623
  __cil_tmp5 = intel_sdvo_connector->output_flag;
#line 1623
  __cil_tmp6 = (int )__cil_tmp5;
#line 1623
  __cil_tmp7 = __cil_tmp6 & 12;
#line 1623
  if (__cil_tmp7 != 0) {
    {
#line 1624
    intel_sdvo_get_tv_modes(connector);
    }
  } else {
    {
#line 1625
    __cil_tmp8 = intel_sdvo_connector->output_flag;
#line 1625
    __cil_tmp9 = (int )__cil_tmp8;
#line 1625
    __cil_tmp10 = __cil_tmp9 & 16448;
#line 1625
    if (__cil_tmp10 != 0) {
      {
#line 1626
      intel_sdvo_get_lvds_modes(connector);
      }
    } else {
      {
#line 1628
      intel_sdvo_get_ddc_modes(connector);
      }
    }
    }
  }
  }
  {
#line 1630
  __cil_tmp11 = & connector->probed_modes;
#line 1630
  __cil_tmp12 = (struct list_head  const  *)__cil_tmp11;
#line 1630
  tmp___0 = list_empty(__cil_tmp12);
  }
#line 1630
  return (tmp___0 == 0);
}
}
#line 1634 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_destroy_enhance_property(struct drm_connector *connector ) 
{ struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp ;
  struct drm_device *dev ;
  struct drm_property *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  struct drm_property *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct drm_property *__cil_tmp9 ;
  struct drm_property *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct drm_property *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_property *__cil_tmp14 ;
  struct drm_property *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct drm_property *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  struct drm_property *__cil_tmp19 ;
  struct drm_property *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_property *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct drm_property *__cil_tmp24 ;
  struct drm_property *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  struct drm_property *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  struct drm_property *__cil_tmp29 ;
  struct drm_property *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  struct drm_property *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  struct drm_property *__cil_tmp34 ;
  struct drm_property *__cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  struct drm_property *__cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  struct drm_property *__cil_tmp39 ;
  struct drm_property *__cil_tmp40 ;
  unsigned long __cil_tmp41 ;
  struct drm_property *__cil_tmp42 ;
  unsigned long __cil_tmp43 ;
  struct drm_property *__cil_tmp44 ;
  struct drm_property *__cil_tmp45 ;
  unsigned long __cil_tmp46 ;
  struct drm_property *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  struct drm_property *__cil_tmp49 ;
  struct drm_property *__cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  struct drm_property *__cil_tmp52 ;
  unsigned long __cil_tmp53 ;
  struct drm_property *__cil_tmp54 ;
  struct drm_property *__cil_tmp55 ;
  unsigned long __cil_tmp56 ;
  struct drm_property *__cil_tmp57 ;
  unsigned long __cil_tmp58 ;
  struct drm_property *__cil_tmp59 ;
  struct drm_property *__cil_tmp60 ;
  unsigned long __cil_tmp61 ;
  struct drm_property *__cil_tmp62 ;
  unsigned long __cil_tmp63 ;
  struct drm_property *__cil_tmp64 ;
  struct drm_property *__cil_tmp65 ;
  unsigned long __cil_tmp66 ;
  struct drm_property *__cil_tmp67 ;
  unsigned long __cil_tmp68 ;
  struct drm_property *__cil_tmp69 ;
  struct drm_property *__cil_tmp70 ;
  unsigned long __cil_tmp71 ;
  struct drm_property *__cil_tmp72 ;
  unsigned long __cil_tmp73 ;
  struct drm_property *__cil_tmp74 ;
  struct drm_property *__cil_tmp75 ;
  unsigned long __cil_tmp76 ;
  struct drm_property *__cil_tmp77 ;
  unsigned long __cil_tmp78 ;
  struct drm_property *__cil_tmp79 ;
  struct drm_property *__cil_tmp80 ;
  unsigned long __cil_tmp81 ;
  struct drm_property *__cil_tmp82 ;
  unsigned long __cil_tmp83 ;
  struct drm_property *__cil_tmp84 ;
  struct drm_property *__cil_tmp85 ;
  unsigned long __cil_tmp86 ;
  struct drm_property *__cil_tmp87 ;
  unsigned long __cil_tmp88 ;
  struct drm_property *__cil_tmp89 ;

  {
  {
#line 1636
  tmp = to_intel_sdvo_connector(connector);
#line 1636
  intel_sdvo_connector = tmp;
#line 1637
  dev = connector->dev;
  }
  {
#line 1639
  __cil_tmp5 = (struct drm_property *)0;
#line 1639
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 1639
  __cil_tmp7 = intel_sdvo_connector->left;
#line 1639
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1639
  if (__cil_tmp8 != __cil_tmp6) {
    {
#line 1640
    __cil_tmp9 = intel_sdvo_connector->left;
#line 1640
    drm_property_destroy(dev, __cil_tmp9);
    }
  } else {

  }
  }
  {
#line 1641
  __cil_tmp10 = (struct drm_property *)0;
#line 1641
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 1641
  __cil_tmp12 = intel_sdvo_connector->right;
#line 1641
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 1641
  if (__cil_tmp13 != __cil_tmp11) {
    {
#line 1642
    __cil_tmp14 = intel_sdvo_connector->right;
#line 1642
    drm_property_destroy(dev, __cil_tmp14);
    }
  } else {

  }
  }
  {
#line 1643
  __cil_tmp15 = (struct drm_property *)0;
#line 1643
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 1643
  __cil_tmp17 = intel_sdvo_connector->top;
#line 1643
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 1643
  if (__cil_tmp18 != __cil_tmp16) {
    {
#line 1644
    __cil_tmp19 = intel_sdvo_connector->top;
#line 1644
    drm_property_destroy(dev, __cil_tmp19);
    }
  } else {

  }
  }
  {
#line 1645
  __cil_tmp20 = (struct drm_property *)0;
#line 1645
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 1645
  __cil_tmp22 = intel_sdvo_connector->bottom;
#line 1645
  __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 1645
  if (__cil_tmp23 != __cil_tmp21) {
    {
#line 1646
    __cil_tmp24 = intel_sdvo_connector->bottom;
#line 1646
    drm_property_destroy(dev, __cil_tmp24);
    }
  } else {

  }
  }
  {
#line 1647
  __cil_tmp25 = (struct drm_property *)0;
#line 1647
  __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 1647
  __cil_tmp27 = intel_sdvo_connector->hpos;
#line 1647
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 1647
  if (__cil_tmp28 != __cil_tmp26) {
    {
#line 1648
    __cil_tmp29 = intel_sdvo_connector->hpos;
#line 1648
    drm_property_destroy(dev, __cil_tmp29);
    }
  } else {

  }
  }
  {
#line 1649
  __cil_tmp30 = (struct drm_property *)0;
#line 1649
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 1649
  __cil_tmp32 = intel_sdvo_connector->vpos;
#line 1649
  __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 1649
  if (__cil_tmp33 != __cil_tmp31) {
    {
#line 1650
    __cil_tmp34 = intel_sdvo_connector->vpos;
#line 1650
    drm_property_destroy(dev, __cil_tmp34);
    }
  } else {

  }
  }
  {
#line 1651
  __cil_tmp35 = (struct drm_property *)0;
#line 1651
  __cil_tmp36 = (unsigned long )__cil_tmp35;
#line 1651
  __cil_tmp37 = intel_sdvo_connector->saturation;
#line 1651
  __cil_tmp38 = (unsigned long )__cil_tmp37;
#line 1651
  if (__cil_tmp38 != __cil_tmp36) {
    {
#line 1652
    __cil_tmp39 = intel_sdvo_connector->saturation;
#line 1652
    drm_property_destroy(dev, __cil_tmp39);
    }
  } else {

  }
  }
  {
#line 1653
  __cil_tmp40 = (struct drm_property *)0;
#line 1653
  __cil_tmp41 = (unsigned long )__cil_tmp40;
#line 1653
  __cil_tmp42 = intel_sdvo_connector->contrast;
#line 1653
  __cil_tmp43 = (unsigned long )__cil_tmp42;
#line 1653
  if (__cil_tmp43 != __cil_tmp41) {
    {
#line 1654
    __cil_tmp44 = intel_sdvo_connector->contrast;
#line 1654
    drm_property_destroy(dev, __cil_tmp44);
    }
  } else {

  }
  }
  {
#line 1655
  __cil_tmp45 = (struct drm_property *)0;
#line 1655
  __cil_tmp46 = (unsigned long )__cil_tmp45;
#line 1655
  __cil_tmp47 = intel_sdvo_connector->hue;
#line 1655
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 1655
  if (__cil_tmp48 != __cil_tmp46) {
    {
#line 1656
    __cil_tmp49 = intel_sdvo_connector->hue;
#line 1656
    drm_property_destroy(dev, __cil_tmp49);
    }
  } else {

  }
  }
  {
#line 1657
  __cil_tmp50 = (struct drm_property *)0;
#line 1657
  __cil_tmp51 = (unsigned long )__cil_tmp50;
#line 1657
  __cil_tmp52 = intel_sdvo_connector->sharpness;
#line 1657
  __cil_tmp53 = (unsigned long )__cil_tmp52;
#line 1657
  if (__cil_tmp53 != __cil_tmp51) {
    {
#line 1658
    __cil_tmp54 = intel_sdvo_connector->sharpness;
#line 1658
    drm_property_destroy(dev, __cil_tmp54);
    }
  } else {

  }
  }
  {
#line 1659
  __cil_tmp55 = (struct drm_property *)0;
#line 1659
  __cil_tmp56 = (unsigned long )__cil_tmp55;
#line 1659
  __cil_tmp57 = intel_sdvo_connector->flicker_filter;
#line 1659
  __cil_tmp58 = (unsigned long )__cil_tmp57;
#line 1659
  if (__cil_tmp58 != __cil_tmp56) {
    {
#line 1660
    __cil_tmp59 = intel_sdvo_connector->flicker_filter;
#line 1660
    drm_property_destroy(dev, __cil_tmp59);
    }
  } else {

  }
  }
  {
#line 1661
  __cil_tmp60 = (struct drm_property *)0;
#line 1661
  __cil_tmp61 = (unsigned long )__cil_tmp60;
#line 1661
  __cil_tmp62 = intel_sdvo_connector->flicker_filter_2d;
#line 1661
  __cil_tmp63 = (unsigned long )__cil_tmp62;
#line 1661
  if (__cil_tmp63 != __cil_tmp61) {
    {
#line 1662
    __cil_tmp64 = intel_sdvo_connector->flicker_filter_2d;
#line 1662
    drm_property_destroy(dev, __cil_tmp64);
    }
  } else {

  }
  }
  {
#line 1663
  __cil_tmp65 = (struct drm_property *)0;
#line 1663
  __cil_tmp66 = (unsigned long )__cil_tmp65;
#line 1663
  __cil_tmp67 = intel_sdvo_connector->flicker_filter_adaptive;
#line 1663
  __cil_tmp68 = (unsigned long )__cil_tmp67;
#line 1663
  if (__cil_tmp68 != __cil_tmp66) {
    {
#line 1664
    __cil_tmp69 = intel_sdvo_connector->flicker_filter_adaptive;
#line 1664
    drm_property_destroy(dev, __cil_tmp69);
    }
  } else {

  }
  }
  {
#line 1665
  __cil_tmp70 = (struct drm_property *)0;
#line 1665
  __cil_tmp71 = (unsigned long )__cil_tmp70;
#line 1665
  __cil_tmp72 = intel_sdvo_connector->tv_luma_filter;
#line 1665
  __cil_tmp73 = (unsigned long )__cil_tmp72;
#line 1665
  if (__cil_tmp73 != __cil_tmp71) {
    {
#line 1666
    __cil_tmp74 = intel_sdvo_connector->tv_luma_filter;
#line 1666
    drm_property_destroy(dev, __cil_tmp74);
    }
  } else {

  }
  }
  {
#line 1667
  __cil_tmp75 = (struct drm_property *)0;
#line 1667
  __cil_tmp76 = (unsigned long )__cil_tmp75;
#line 1667
  __cil_tmp77 = intel_sdvo_connector->tv_chroma_filter;
#line 1667
  __cil_tmp78 = (unsigned long )__cil_tmp77;
#line 1667
  if (__cil_tmp78 != __cil_tmp76) {
    {
#line 1668
    __cil_tmp79 = intel_sdvo_connector->tv_chroma_filter;
#line 1668
    drm_property_destroy(dev, __cil_tmp79);
    }
  } else {

  }
  }
  {
#line 1669
  __cil_tmp80 = (struct drm_property *)0;
#line 1669
  __cil_tmp81 = (unsigned long )__cil_tmp80;
#line 1669
  __cil_tmp82 = intel_sdvo_connector->dot_crawl;
#line 1669
  __cil_tmp83 = (unsigned long )__cil_tmp82;
#line 1669
  if (__cil_tmp83 != __cil_tmp81) {
    {
#line 1670
    __cil_tmp84 = intel_sdvo_connector->dot_crawl;
#line 1670
    drm_property_destroy(dev, __cil_tmp84);
    }
  } else {

  }
  }
  {
#line 1671
  __cil_tmp85 = (struct drm_property *)0;
#line 1671
  __cil_tmp86 = (unsigned long )__cil_tmp85;
#line 1671
  __cil_tmp87 = intel_sdvo_connector->brightness;
#line 1671
  __cil_tmp88 = (unsigned long )__cil_tmp87;
#line 1671
  if (__cil_tmp88 != __cil_tmp86) {
    {
#line 1672
    __cil_tmp89 = intel_sdvo_connector->brightness;
#line 1672
    drm_property_destroy(dev, __cil_tmp89);
    }
  } else {

  }
  }
#line 1673
  return;
}
}
#line 1675 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_destroy(struct drm_connector *connector ) 
{ struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp ;
  struct drm_property *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct drm_property *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct drm_device *__cil_tmp8 ;
  struct drm_property *__cil_tmp9 ;
  void const   *__cil_tmp10 ;

  {
  {
#line 1677
  tmp = to_intel_sdvo_connector(connector);
#line 1677
  intel_sdvo_connector = tmp;
  }
  {
#line 1679
  __cil_tmp4 = (struct drm_property *)0;
#line 1679
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 1679
  __cil_tmp6 = intel_sdvo_connector->tv_format;
#line 1679
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 1679
  if (__cil_tmp7 != __cil_tmp5) {
    {
#line 1680
    __cil_tmp8 = connector->dev;
#line 1680
    __cil_tmp9 = intel_sdvo_connector->tv_format;
#line 1680
    drm_property_destroy(__cil_tmp8, __cil_tmp9);
    }
  } else {

  }
  }
  {
#line 1683
  intel_sdvo_destroy_enhance_property(connector);
#line 1684
  drm_sysfs_connector_remove(connector);
#line 1685
  drm_connector_cleanup(connector);
#line 1686
  __cil_tmp10 = (void const   *)connector;
#line 1686
  kfree(__cil_tmp10);
  }
#line 1687
  return;
}
}
#line 1689 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct edid *edid ;
  bool has_audio ;
  bool __cil_tmp6 ;
  struct edid *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  u8 __cil_tmp10 ;
  signed char __cil_tmp11 ;
  int __cil_tmp12 ;

  {
  {
#line 1691
  tmp = intel_attached_sdvo(connector);
#line 1691
  intel_sdvo = tmp;
#line 1693
  has_audio = (bool )0;
  }
  {
#line 1695
  __cil_tmp6 = intel_sdvo->is_hdmi;
#line 1695
  if (! __cil_tmp6) {
#line 1696
    return ((bool )0);
  } else {

  }
  }
  {
#line 1698
  edid = intel_sdvo_get_edid(connector);
  }
  {
#line 1699
  __cil_tmp7 = (struct edid *)0;
#line 1699
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1699
  __cil_tmp9 = (unsigned long )edid;
#line 1699
  if (__cil_tmp9 != __cil_tmp8) {
    {
#line 1699
    __cil_tmp10 = edid->input;
#line 1699
    __cil_tmp11 = (signed char )__cil_tmp10;
#line 1699
    __cil_tmp12 = (int )__cil_tmp11;
#line 1699
    if (__cil_tmp12 < 0) {
      {
#line 1700
      has_audio = drm_detect_monitor_audio(edid);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 1702
  return (has_audio);
}
}
#line 1706 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static int intel_sdvo_set_property(struct drm_connector *connector , struct drm_property *property ,
                                   uint64_t val ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  struct intel_sdvo_connector *tmp___0 ;
  struct drm_i915_private *dev_priv ;
  uint16_t temp_value ;
  uint8_t cmd ;
  int ret ;
  int i ;
  bool has_audio ;
  bool tmp___1 ;
  int tmp___2 ;
  struct drm_crtc *crtc ;
  struct drm_device *__cil_tmp17 ;
  void *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  struct drm_property *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  bool __cil_tmp25 ;
  int __cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  struct drm_property *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  uint32_t __cil_tmp30 ;
  int __cil_tmp31 ;
  uint64_t __cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  struct drm_property *__cil_tmp34 ;
  unsigned long __cil_tmp35 ;
  u8 __cil_tmp36 ;
  int __cil_tmp37 ;
  int __cil_tmp38 ;
  u8 __cil_tmp39 ;
  uint16_t __cil_tmp40 ;
  int __cil_tmp41 ;
  int __cil_tmp42 ;
  unsigned long __cil_tmp43 ;
  struct drm_property *__cil_tmp44 ;
  unsigned long __cil_tmp45 ;
  struct drm_property *__cil_tmp46 ;
  u32 __cil_tmp47 ;
  u32 __cil_tmp48 ;
  u32 __cil_tmp49 ;
  uint16_t __cil_tmp50 ;
  int __cil_tmp51 ;
  u32 __cil_tmp52 ;
  uint16_t __cil_tmp53 ;
  int __cil_tmp54 ;
  int __cil_tmp55 ;
  unsigned long __cil_tmp56 ;
  struct drm_property *__cil_tmp57 ;
  unsigned long __cil_tmp58 ;
  struct drm_property *__cil_tmp59 ;
  u32 __cil_tmp60 ;
  u32 __cil_tmp61 ;
  u32 __cil_tmp62 ;
  uint16_t __cil_tmp63 ;
  int __cil_tmp64 ;
  u32 __cil_tmp65 ;
  uint16_t __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  unsigned long __cil_tmp69 ;
  struct drm_property *__cil_tmp70 ;
  unsigned long __cil_tmp71 ;
  struct drm_property *__cil_tmp72 ;
  u32 __cil_tmp73 ;
  u32 __cil_tmp74 ;
  u32 __cil_tmp75 ;
  uint16_t __cil_tmp76 ;
  int __cil_tmp77 ;
  u32 __cil_tmp78 ;
  uint16_t __cil_tmp79 ;
  int __cil_tmp80 ;
  int __cil_tmp81 ;
  unsigned long __cil_tmp82 ;
  struct drm_property *__cil_tmp83 ;
  unsigned long __cil_tmp84 ;
  struct drm_property *__cil_tmp85 ;
  u32 __cil_tmp86 ;
  u32 __cil_tmp87 ;
  u32 __cil_tmp88 ;
  uint16_t __cil_tmp89 ;
  int __cil_tmp90 ;
  u32 __cil_tmp91 ;
  uint16_t __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  unsigned long __cil_tmp95 ;
  struct drm_property *__cil_tmp96 ;
  unsigned long __cil_tmp97 ;
  u32 __cil_tmp98 ;
  u32 __cil_tmp99 ;
  u32 __cil_tmp100 ;
  u32 __cil_tmp101 ;
  unsigned long __cil_tmp102 ;
  struct drm_property *__cil_tmp103 ;
  unsigned long __cil_tmp104 ;
  u32 __cil_tmp105 ;
  u32 __cil_tmp106 ;
  u32 __cil_tmp107 ;
  u32 __cil_tmp108 ;
  unsigned long __cil_tmp109 ;
  struct drm_property *__cil_tmp110 ;
  unsigned long __cil_tmp111 ;
  u32 __cil_tmp112 ;
  u32 __cil_tmp113 ;
  u32 __cil_tmp114 ;
  u32 __cil_tmp115 ;
  unsigned long __cil_tmp116 ;
  struct drm_property *__cil_tmp117 ;
  unsigned long __cil_tmp118 ;
  u32 __cil_tmp119 ;
  u32 __cil_tmp120 ;
  u32 __cil_tmp121 ;
  u32 __cil_tmp122 ;
  unsigned long __cil_tmp123 ;
  struct drm_property *__cil_tmp124 ;
  unsigned long __cil_tmp125 ;
  u32 __cil_tmp126 ;
  u32 __cil_tmp127 ;
  u32 __cil_tmp128 ;
  u32 __cil_tmp129 ;
  unsigned long __cil_tmp130 ;
  struct drm_property *__cil_tmp131 ;
  unsigned long __cil_tmp132 ;
  u32 __cil_tmp133 ;
  u32 __cil_tmp134 ;
  u32 __cil_tmp135 ;
  u32 __cil_tmp136 ;
  unsigned long __cil_tmp137 ;
  struct drm_property *__cil_tmp138 ;
  unsigned long __cil_tmp139 ;
  u32 __cil_tmp140 ;
  u32 __cil_tmp141 ;
  u32 __cil_tmp142 ;
  u32 __cil_tmp143 ;
  unsigned long __cil_tmp144 ;
  struct drm_property *__cil_tmp145 ;
  unsigned long __cil_tmp146 ;
  u32 __cil_tmp147 ;
  u32 __cil_tmp148 ;
  u32 __cil_tmp149 ;
  u32 __cil_tmp150 ;
  unsigned long __cil_tmp151 ;
  struct drm_property *__cil_tmp152 ;
  unsigned long __cil_tmp153 ;
  u32 __cil_tmp154 ;
  u32 __cil_tmp155 ;
  u32 __cil_tmp156 ;
  u32 __cil_tmp157 ;
  unsigned long __cil_tmp158 ;
  struct drm_property *__cil_tmp159 ;
  unsigned long __cil_tmp160 ;
  u32 __cil_tmp161 ;
  u32 __cil_tmp162 ;
  u32 __cil_tmp163 ;
  u32 __cil_tmp164 ;
  unsigned long __cil_tmp165 ;
  struct drm_property *__cil_tmp166 ;
  unsigned long __cil_tmp167 ;
  u32 __cil_tmp168 ;
  u32 __cil_tmp169 ;
  u32 __cil_tmp170 ;
  u32 __cil_tmp171 ;
  unsigned long __cil_tmp172 ;
  struct drm_property *__cil_tmp173 ;
  unsigned long __cil_tmp174 ;
  u32 __cil_tmp175 ;
  u32 __cil_tmp176 ;
  u32 __cil_tmp177 ;
  u32 __cil_tmp178 ;
  unsigned long __cil_tmp179 ;
  struct drm_property *__cil_tmp180 ;
  unsigned long __cil_tmp181 ;
  u32 __cil_tmp182 ;
  u32 __cil_tmp183 ;
  u32 __cil_tmp184 ;
  u32 __cil_tmp185 ;
  int __cil_tmp186 ;
  u8 __cil_tmp187 ;
  void const   *__cil_tmp188 ;
  struct drm_crtc *__cil_tmp189 ;
  unsigned long __cil_tmp190 ;
  struct drm_crtc *__cil_tmp191 ;
  unsigned long __cil_tmp192 ;
  struct drm_display_mode *__cil_tmp193 ;
  int __cil_tmp194 ;
  int __cil_tmp195 ;
  struct drm_framebuffer *__cil_tmp196 ;

  {
  {
#line 1710
  tmp = intel_attached_sdvo(connector);
#line 1710
  intel_sdvo = tmp;
#line 1711
  tmp___0 = to_intel_sdvo_connector(connector);
#line 1711
  intel_sdvo_connector = tmp___0;
#line 1712
  __cil_tmp17 = connector->dev;
#line 1712
  __cil_tmp18 = __cil_tmp17->dev_private;
#line 1712
  dev_priv = (struct drm_i915_private *)__cil_tmp18;
#line 1717
  ret = drm_connector_property_set_value(connector, property, val);
  }
#line 1718
  if (ret != 0) {
#line 1719
    return (ret);
  } else {

  }
  {
#line 1721
  __cil_tmp19 = (unsigned long )property;
#line 1721
  __cil_tmp20 = dev_priv->force_audio_property;
#line 1721
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 1721
  if (__cil_tmp21 == __cil_tmp19) {
#line 1722
    i = (int )val;
    {
#line 1725
    __cil_tmp22 = intel_sdvo_connector->force_audio;
#line 1725
    if (__cil_tmp22 == i) {
#line 1726
      return (0);
    } else {

    }
    }
#line 1728
    intel_sdvo_connector->force_audio = i;
#line 1730
    if (i == 0) {
      {
#line 1731
      has_audio = intel_sdvo_detect_hdmi_audio(connector);
      }
    } else {
#line 1733
      __cil_tmp23 = i > 0;
#line 1733
      has_audio = (bool )__cil_tmp23;
    }
    {
#line 1735
    __cil_tmp24 = (int )has_audio;
#line 1735
    __cil_tmp25 = intel_sdvo->has_hdmi_audio;
#line 1735
    __cil_tmp26 = (int )__cil_tmp25;
#line 1735
    if (__cil_tmp26 == __cil_tmp24) {
#line 1736
      return (0);
    } else {

    }
    }
#line 1738
    intel_sdvo->has_hdmi_audio = has_audio;
#line 1739
    goto done;
  } else {

  }
  }
  {
#line 1742
  __cil_tmp27 = (unsigned long )property;
#line 1742
  __cil_tmp28 = dev_priv->broadcast_rgb_property;
#line 1742
  __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 1742
  if (__cil_tmp29 == __cil_tmp27) {
    {
#line 1743
    __cil_tmp30 = intel_sdvo->color_range;
#line 1743
    __cil_tmp31 = __cil_tmp30 != 0U;
#line 1743
    __cil_tmp32 = (uint64_t )__cil_tmp31;
#line 1743
    if (__cil_tmp32 == val) {
#line 1744
      return (0);
    } else {

    }
    }
#line 1746
    if (val != 0ULL) {
#line 1746
      intel_sdvo->color_range = 256U;
    } else {
#line 1746
      intel_sdvo->color_range = 0U;
    }
#line 1747
    goto done;
  } else {

  }
  }
  {
#line 1759
  __cil_tmp33 = (unsigned long )property;
#line 1759
  __cil_tmp34 = intel_sdvo_connector->tv_format;
#line 1759
  __cil_tmp35 = (unsigned long )__cil_tmp34;
#line 1759
  if (__cil_tmp35 == __cil_tmp33) {
#line 1760
    if (val > 18ULL) {
#line 1761
      return (-22);
    } else {

    }
    {
#line 1763
    __cil_tmp36 = intel_sdvo_connector->tv_format_supported[val];
#line 1763
    __cil_tmp37 = (int )__cil_tmp36;
#line 1763
    __cil_tmp38 = intel_sdvo->tv_format_index;
#line 1763
    if (__cil_tmp38 == __cil_tmp37) {
#line 1765
      return (0);
    } else {

    }
    }
#line 1767
    __cil_tmp39 = intel_sdvo_connector->tv_format_supported[val];
#line 1767
    intel_sdvo->tv_format_index = (int )__cil_tmp39;
#line 1768
    goto done;
  } else {
    {
#line 1769
    __cil_tmp40 = intel_sdvo_connector->output_flag;
#line 1769
    __cil_tmp41 = (int )__cil_tmp40;
#line 1769
    __cil_tmp42 = __cil_tmp41 & 16460;
#line 1769
    if (__cil_tmp42 != 0) {
#line 1770
      temp_value = (uint16_t )val;
      {
#line 1771
      __cil_tmp43 = (unsigned long )property;
#line 1771
      __cil_tmp44 = intel_sdvo_connector->left;
#line 1771
      __cil_tmp45 = (unsigned long )__cil_tmp44;
#line 1771
      if (__cil_tmp45 == __cil_tmp43) {
        {
#line 1772
        __cil_tmp46 = intel_sdvo_connector->right;
#line 1772
        drm_connector_property_set_value(connector, __cil_tmp46, val);
        }
        {
#line 1774
        __cil_tmp47 = (u32 )temp_value;
#line 1774
        __cil_tmp48 = intel_sdvo_connector->left_margin;
#line 1774
        if (__cil_tmp48 == __cil_tmp47) {
#line 1775
          return (0);
        } else {

        }
        }
#line 1777
        intel_sdvo_connector->left_margin = (u32 )temp_value;
#line 1778
        intel_sdvo_connector->right_margin = (u32 )temp_value;
#line 1779
        __cil_tmp49 = intel_sdvo_connector->left_margin;
#line 1779
        __cil_tmp50 = (uint16_t )__cil_tmp49;
#line 1779
        __cil_tmp51 = (int )__cil_tmp50;
#line 1779
        __cil_tmp52 = intel_sdvo_connector->max_hscan;
#line 1779
        __cil_tmp53 = (uint16_t )__cil_tmp52;
#line 1779
        __cil_tmp54 = (int )__cil_tmp53;
#line 1779
        __cil_tmp55 = __cil_tmp54 - __cil_tmp51;
#line 1779
        temp_value = (uint16_t )__cil_tmp55;
#line 1781
        cmd = (uint8_t )99U;
#line 1782
        goto set_value;
      } else {
        {
#line 1783
        __cil_tmp56 = (unsigned long )property;
#line 1783
        __cil_tmp57 = intel_sdvo_connector->right;
#line 1783
        __cil_tmp58 = (unsigned long )__cil_tmp57;
#line 1783
        if (__cil_tmp58 == __cil_tmp56) {
          {
#line 1784
          __cil_tmp59 = intel_sdvo_connector->left;
#line 1784
          drm_connector_property_set_value(connector, __cil_tmp59, val);
          }
          {
#line 1786
          __cil_tmp60 = (u32 )temp_value;
#line 1786
          __cil_tmp61 = intel_sdvo_connector->right_margin;
#line 1786
          if (__cil_tmp61 == __cil_tmp60) {
#line 1787
            return (0);
          } else {

          }
          }
#line 1789
          intel_sdvo_connector->left_margin = (u32 )temp_value;
#line 1790
          intel_sdvo_connector->right_margin = (u32 )temp_value;
#line 1791
          __cil_tmp62 = intel_sdvo_connector->left_margin;
#line 1791
          __cil_tmp63 = (uint16_t )__cil_tmp62;
#line 1791
          __cil_tmp64 = (int )__cil_tmp63;
#line 1791
          __cil_tmp65 = intel_sdvo_connector->max_hscan;
#line 1791
          __cil_tmp66 = (uint16_t )__cil_tmp65;
#line 1791
          __cil_tmp67 = (int )__cil_tmp66;
#line 1791
          __cil_tmp68 = __cil_tmp67 - __cil_tmp64;
#line 1791
          temp_value = (uint16_t )__cil_tmp68;
#line 1793
          cmd = (uint8_t )99U;
#line 1794
          goto set_value;
        } else {
          {
#line 1795
          __cil_tmp69 = (unsigned long )property;
#line 1795
          __cil_tmp70 = intel_sdvo_connector->top;
#line 1795
          __cil_tmp71 = (unsigned long )__cil_tmp70;
#line 1795
          if (__cil_tmp71 == __cil_tmp69) {
            {
#line 1796
            __cil_tmp72 = intel_sdvo_connector->bottom;
#line 1796
            drm_connector_property_set_value(connector, __cil_tmp72, val);
            }
            {
#line 1798
            __cil_tmp73 = (u32 )temp_value;
#line 1798
            __cil_tmp74 = intel_sdvo_connector->top_margin;
#line 1798
            if (__cil_tmp74 == __cil_tmp73) {
#line 1799
              return (0);
            } else {

            }
            }
#line 1801
            intel_sdvo_connector->top_margin = (u32 )temp_value;
#line 1802
            intel_sdvo_connector->bottom_margin = (u32 )temp_value;
#line 1803
            __cil_tmp75 = intel_sdvo_connector->top_margin;
#line 1803
            __cil_tmp76 = (uint16_t )__cil_tmp75;
#line 1803
            __cil_tmp77 = (int )__cil_tmp76;
#line 1803
            __cil_tmp78 = intel_sdvo_connector->max_vscan;
#line 1803
            __cil_tmp79 = (uint16_t )__cil_tmp78;
#line 1803
            __cil_tmp80 = (int )__cil_tmp79;
#line 1803
            __cil_tmp81 = __cil_tmp80 - __cil_tmp77;
#line 1803
            temp_value = (uint16_t )__cil_tmp81;
#line 1805
            cmd = (uint8_t )102U;
#line 1806
            goto set_value;
          } else {
            {
#line 1807
            __cil_tmp82 = (unsigned long )property;
#line 1807
            __cil_tmp83 = intel_sdvo_connector->bottom;
#line 1807
            __cil_tmp84 = (unsigned long )__cil_tmp83;
#line 1807
            if (__cil_tmp84 == __cil_tmp82) {
              {
#line 1808
              __cil_tmp85 = intel_sdvo_connector->top;
#line 1808
              drm_connector_property_set_value(connector, __cil_tmp85, val);
              }
              {
#line 1810
              __cil_tmp86 = (u32 )temp_value;
#line 1810
              __cil_tmp87 = intel_sdvo_connector->bottom_margin;
#line 1810
              if (__cil_tmp87 == __cil_tmp86) {
#line 1811
                return (0);
              } else {

              }
              }
#line 1813
              intel_sdvo_connector->top_margin = (u32 )temp_value;
#line 1814
              intel_sdvo_connector->bottom_margin = (u32 )temp_value;
#line 1815
              __cil_tmp88 = intel_sdvo_connector->top_margin;
#line 1815
              __cil_tmp89 = (uint16_t )__cil_tmp88;
#line 1815
              __cil_tmp90 = (int )__cil_tmp89;
#line 1815
              __cil_tmp91 = intel_sdvo_connector->max_vscan;
#line 1815
              __cil_tmp92 = (uint16_t )__cil_tmp91;
#line 1815
              __cil_tmp93 = (int )__cil_tmp92;
#line 1815
              __cil_tmp94 = __cil_tmp93 - __cil_tmp90;
#line 1815
              temp_value = (uint16_t )__cil_tmp94;
#line 1817
              cmd = (uint8_t )102U;
#line 1818
              goto set_value;
            } else {

            }
            }
          }
          }
        }
        }
      }
      }
      {
#line 1820
      __cil_tmp95 = (unsigned long )property;
#line 1820
      __cil_tmp96 = intel_sdvo_connector->hpos;
#line 1820
      __cil_tmp97 = (unsigned long )__cil_tmp96;
#line 1820
      if (__cil_tmp97 == __cil_tmp95) {
        {
#line 1820
        __cil_tmp98 = (u32 )temp_value;
#line 1820
        __cil_tmp99 = intel_sdvo_connector->cur_hpos;
#line 1820
        if (__cil_tmp99 == __cil_tmp98) {
#line 1820
          return (0);
        } else {

        }
        }
        {
#line 1820
        __cil_tmp100 = (u32 )temp_value;
#line 1820
        __cil_tmp101 = intel_sdvo_connector->max_hpos;
#line 1820
        if (__cil_tmp101 < __cil_tmp100) {
#line 1820
          return (-22);
        } else {

        }
        }
#line 1820
        cmd = (uint8_t )105U;
#line 1820
        intel_sdvo_connector->cur_hpos = (u32 )temp_value;
#line 1820
        goto set_value;
      } else {

      }
      }
      {
#line 1821
      __cil_tmp102 = (unsigned long )property;
#line 1821
      __cil_tmp103 = intel_sdvo_connector->vpos;
#line 1821
      __cil_tmp104 = (unsigned long )__cil_tmp103;
#line 1821
      if (__cil_tmp104 == __cil_tmp102) {
        {
#line 1821
        __cil_tmp105 = (u32 )temp_value;
#line 1821
        __cil_tmp106 = intel_sdvo_connector->cur_vpos;
#line 1821
        if (__cil_tmp106 == __cil_tmp105) {
#line 1821
          return (0);
        } else {

        }
        }
        {
#line 1821
        __cil_tmp107 = (u32 )temp_value;
#line 1821
        __cil_tmp108 = intel_sdvo_connector->max_vpos;
#line 1821
        if (__cil_tmp108 < __cil_tmp107) {
#line 1821
          return (-22);
        } else {

        }
        }
#line 1821
        cmd = (uint8_t )108U;
#line 1821
        intel_sdvo_connector->cur_vpos = (u32 )temp_value;
#line 1821
        goto set_value;
      } else {

      }
      }
      {
#line 1822
      __cil_tmp109 = (unsigned long )property;
#line 1822
      __cil_tmp110 = intel_sdvo_connector->saturation;
#line 1822
      __cil_tmp111 = (unsigned long )__cil_tmp110;
#line 1822
      if (__cil_tmp111 == __cil_tmp109) {
        {
#line 1822
        __cil_tmp112 = (u32 )temp_value;
#line 1822
        __cil_tmp113 = intel_sdvo_connector->cur_saturation;
#line 1822
        if (__cil_tmp113 == __cil_tmp112) {
#line 1822
          return (0);
        } else {

        }
        }
        {
#line 1822
        __cil_tmp114 = (u32 )temp_value;
#line 1822
        __cil_tmp115 = intel_sdvo_connector->max_saturation;
#line 1822
        if (__cil_tmp115 < __cil_tmp114) {
#line 1822
          return (-22);
        } else {

        }
        }
#line 1822
        cmd = (uint8_t )87U;
#line 1822
        intel_sdvo_connector->cur_saturation = (u32 )temp_value;
#line 1822
        goto set_value;
      } else {

      }
      }
      {
#line 1823
      __cil_tmp116 = (unsigned long )property;
#line 1823
      __cil_tmp117 = intel_sdvo_connector->contrast;
#line 1823
      __cil_tmp118 = (unsigned long )__cil_tmp117;
#line 1823
      if (__cil_tmp118 == __cil_tmp116) {
        {
#line 1823
        __cil_tmp119 = (u32 )temp_value;
#line 1823
        __cil_tmp120 = intel_sdvo_connector->cur_contrast;
#line 1823
        if (__cil_tmp120 == __cil_tmp119) {
#line 1823
          return (0);
        } else {

        }
        }
        {
#line 1823
        __cil_tmp121 = (u32 )temp_value;
#line 1823
        __cil_tmp122 = intel_sdvo_connector->max_contrast;
#line 1823
        if (__cil_tmp122 < __cil_tmp121) {
#line 1823
          return (-22);
        } else {

        }
        }
#line 1823
        cmd = (uint8_t )96U;
#line 1823
        intel_sdvo_connector->cur_contrast = (u32 )temp_value;
#line 1823
        goto set_value;
      } else {

      }
      }
      {
#line 1824
      __cil_tmp123 = (unsigned long )property;
#line 1824
      __cil_tmp124 = intel_sdvo_connector->hue;
#line 1824
      __cil_tmp125 = (unsigned long )__cil_tmp124;
#line 1824
      if (__cil_tmp125 == __cil_tmp123) {
        {
#line 1824
        __cil_tmp126 = (u32 )temp_value;
#line 1824
        __cil_tmp127 = intel_sdvo_connector->cur_hue;
#line 1824
        if (__cil_tmp127 == __cil_tmp126) {
#line 1824
          return (0);
        } else {

        }
        }
        {
#line 1824
        __cil_tmp128 = (u32 )temp_value;
#line 1824
        __cil_tmp129 = intel_sdvo_connector->max_hue;
#line 1824
        if (__cil_tmp129 < __cil_tmp128) {
#line 1824
          return (-22);
        } else {

        }
        }
#line 1824
        cmd = (uint8_t )90U;
#line 1824
        intel_sdvo_connector->cur_hue = (u32 )temp_value;
#line 1824
        goto set_value;
      } else {

      }
      }
      {
#line 1825
      __cil_tmp130 = (unsigned long )property;
#line 1825
      __cil_tmp131 = intel_sdvo_connector->brightness;
#line 1825
      __cil_tmp132 = (unsigned long )__cil_tmp131;
#line 1825
      if (__cil_tmp132 == __cil_tmp130) {
        {
#line 1825
        __cil_tmp133 = (u32 )temp_value;
#line 1825
        __cil_tmp134 = intel_sdvo_connector->cur_brightness;
#line 1825
        if (__cil_tmp134 == __cil_tmp133) {
#line 1825
          return (0);
        } else {

        }
        }
        {
#line 1825
        __cil_tmp135 = (u32 )temp_value;
#line 1825
        __cil_tmp136 = intel_sdvo_connector->max_brightness;
#line 1825
        if (__cil_tmp136 < __cil_tmp135) {
#line 1825
          return (-22);
        } else {

        }
        }
#line 1825
        cmd = (uint8_t )93U;
#line 1825
        intel_sdvo_connector->cur_brightness = (u32 )temp_value;
#line 1825
        goto set_value;
      } else {

      }
      }
      {
#line 1826
      __cil_tmp137 = (unsigned long )property;
#line 1826
      __cil_tmp138 = intel_sdvo_connector->sharpness;
#line 1826
      __cil_tmp139 = (unsigned long )__cil_tmp138;
#line 1826
      if (__cil_tmp139 == __cil_tmp137) {
        {
#line 1826
        __cil_tmp140 = (u32 )temp_value;
#line 1826
        __cil_tmp141 = intel_sdvo_connector->cur_sharpness;
#line 1826
        if (__cil_tmp141 == __cil_tmp140) {
#line 1826
          return (0);
        } else {

        }
        }
        {
#line 1826
        __cil_tmp142 = (u32 )temp_value;
#line 1826
        __cil_tmp143 = intel_sdvo_connector->max_sharpness;
#line 1826
        if (__cil_tmp143 < __cil_tmp142) {
#line 1826
          return (-22);
        } else {

        }
        }
#line 1826
        cmd = (uint8_t )111U;
#line 1826
        intel_sdvo_connector->cur_sharpness = (u32 )temp_value;
#line 1826
        goto set_value;
      } else {

      }
      }
      {
#line 1827
      __cil_tmp144 = (unsigned long )property;
#line 1827
      __cil_tmp145 = intel_sdvo_connector->flicker_filter;
#line 1827
      __cil_tmp146 = (unsigned long )__cil_tmp145;
#line 1827
      if (__cil_tmp146 == __cil_tmp144) {
        {
#line 1827
        __cil_tmp147 = (u32 )temp_value;
#line 1827
        __cil_tmp148 = intel_sdvo_connector->cur_flicker_filter;
#line 1827
        if (__cil_tmp148 == __cil_tmp147) {
#line 1827
          return (0);
        } else {

        }
        }
        {
#line 1827
        __cil_tmp149 = (u32 )temp_value;
#line 1827
        __cil_tmp150 = intel_sdvo_connector->max_flicker_filter;
#line 1827
        if (__cil_tmp150 < __cil_tmp149) {
#line 1827
          return (-22);
        } else {

        }
        }
#line 1827
        cmd = (uint8_t )79U;
#line 1827
        intel_sdvo_connector->cur_flicker_filter = (u32 )temp_value;
#line 1827
        goto set_value;
      } else {

      }
      }
      {
#line 1828
      __cil_tmp151 = (unsigned long )property;
#line 1828
      __cil_tmp152 = intel_sdvo_connector->flicker_filter_2d;
#line 1828
      __cil_tmp153 = (unsigned long )__cil_tmp152;
#line 1828
      if (__cil_tmp153 == __cil_tmp151) {
        {
#line 1828
        __cil_tmp154 = (u32 )temp_value;
#line 1828
        __cil_tmp155 = intel_sdvo_connector->cur_flicker_filter_2d;
#line 1828
        if (__cil_tmp155 == __cil_tmp154) {
#line 1828
          return (0);
        } else {

        }
        }
        {
#line 1828
        __cil_tmp156 = (u32 )temp_value;
#line 1828
        __cil_tmp157 = intel_sdvo_connector->max_flicker_filter_2d;
#line 1828
        if (__cil_tmp157 < __cil_tmp156) {
#line 1828
          return (-22);
        } else {

        }
        }
#line 1828
        cmd = (uint8_t )84U;
#line 1828
        intel_sdvo_connector->cur_flicker_filter_2d = (u32 )temp_value;
#line 1828
        goto set_value;
      } else {

      }
      }
      {
#line 1829
      __cil_tmp158 = (unsigned long )property;
#line 1829
      __cil_tmp159 = intel_sdvo_connector->flicker_filter_adaptive;
#line 1829
      __cil_tmp160 = (unsigned long )__cil_tmp159;
#line 1829
      if (__cil_tmp160 == __cil_tmp158) {
        {
#line 1829
        __cil_tmp161 = (u32 )temp_value;
#line 1829
        __cil_tmp162 = intel_sdvo_connector->cur_flicker_filter_adaptive;
#line 1829
        if (__cil_tmp162 == __cil_tmp161) {
#line 1829
          return (0);
        } else {

        }
        }
        {
#line 1829
        __cil_tmp163 = (u32 )temp_value;
#line 1829
        __cil_tmp164 = intel_sdvo_connector->max_flicker_filter_adaptive;
#line 1829
        if (__cil_tmp164 < __cil_tmp163) {
#line 1829
          return (-22);
        } else {

        }
        }
#line 1829
        cmd = (uint8_t )81U;
#line 1829
        intel_sdvo_connector->cur_flicker_filter_adaptive = (u32 )temp_value;
#line 1829
        goto set_value;
      } else {

      }
      }
      {
#line 1830
      __cil_tmp165 = (unsigned long )property;
#line 1830
      __cil_tmp166 = intel_sdvo_connector->tv_chroma_filter;
#line 1830
      __cil_tmp167 = (unsigned long )__cil_tmp166;
#line 1830
      if (__cil_tmp167 == __cil_tmp165) {
        {
#line 1830
        __cil_tmp168 = (u32 )temp_value;
#line 1830
        __cil_tmp169 = intel_sdvo_connector->cur_tv_chroma_filter;
#line 1830
        if (__cil_tmp169 == __cil_tmp168) {
#line 1830
          return (0);
        } else {

        }
        }
        {
#line 1830
        __cil_tmp170 = (u32 )temp_value;
#line 1830
        __cil_tmp171 = intel_sdvo_connector->max_tv_chroma_filter;
#line 1830
        if (__cil_tmp171 < __cil_tmp170) {
#line 1830
          return (-22);
        } else {

        }
        }
#line 1830
        cmd = (uint8_t )118U;
#line 1830
        intel_sdvo_connector->cur_tv_chroma_filter = (u32 )temp_value;
#line 1830
        goto set_value;
      } else {

      }
      }
      {
#line 1831
      __cil_tmp172 = (unsigned long )property;
#line 1831
      __cil_tmp173 = intel_sdvo_connector->tv_luma_filter;
#line 1831
      __cil_tmp174 = (unsigned long )__cil_tmp173;
#line 1831
      if (__cil_tmp174 == __cil_tmp172) {
        {
#line 1831
        __cil_tmp175 = (u32 )temp_value;
#line 1831
        __cil_tmp176 = intel_sdvo_connector->cur_tv_luma_filter;
#line 1831
        if (__cil_tmp176 == __cil_tmp175) {
#line 1831
          return (0);
        } else {

        }
        }
        {
#line 1831
        __cil_tmp177 = (u32 )temp_value;
#line 1831
        __cil_tmp178 = intel_sdvo_connector->max_tv_luma_filter;
#line 1831
        if (__cil_tmp178 < __cil_tmp177) {
#line 1831
          return (-22);
        } else {

        }
        }
#line 1831
        cmd = (uint8_t )121U;
#line 1831
        intel_sdvo_connector->cur_tv_luma_filter = (u32 )temp_value;
#line 1831
        goto set_value;
      } else {

      }
      }
      {
#line 1832
      __cil_tmp179 = (unsigned long )property;
#line 1832
      __cil_tmp180 = intel_sdvo_connector->dot_crawl;
#line 1832
      __cil_tmp181 = (unsigned long )__cil_tmp180;
#line 1832
      if (__cil_tmp181 == __cil_tmp179) {
        {
#line 1832
        __cil_tmp182 = (u32 )temp_value;
#line 1832
        __cil_tmp183 = intel_sdvo_connector->cur_dot_crawl;
#line 1832
        if (__cil_tmp183 == __cil_tmp182) {
#line 1832
          return (0);
        } else {

        }
        }
        {
#line 1832
        __cil_tmp184 = (u32 )temp_value;
#line 1832
        __cil_tmp185 = intel_sdvo_connector->max_dot_crawl;
#line 1832
        if (__cil_tmp185 < __cil_tmp184) {
#line 1832
          return (-22);
        } else {

        }
        }
#line 1832
        cmd = (uint8_t )113U;
#line 1832
        intel_sdvo_connector->cur_dot_crawl = (u32 )temp_value;
#line 1832
        goto set_value;
      } else {

      }
      }
    } else {

    }
    }
  }
  }
#line 1835
  return (-22);
  set_value: 
  {
#line 1838
  __cil_tmp186 = (int )cmd;
#line 1838
  __cil_tmp187 = (u8 )__cil_tmp186;
#line 1838
  __cil_tmp188 = (void const   *)(& temp_value);
#line 1838
  tmp___1 = intel_sdvo_set_value(intel_sdvo, __cil_tmp187, __cil_tmp188, 2);
  }
#line 1838
  if (tmp___1) {
#line 1838
    tmp___2 = 0;
  } else {
#line 1838
    tmp___2 = 1;
  }
#line 1838
  if (tmp___2) {
#line 1839
    return (-5);
  } else {

  }
  done: ;
  {
#line 1843
  __cil_tmp189 = (struct drm_crtc *)0;
#line 1843
  __cil_tmp190 = (unsigned long )__cil_tmp189;
#line 1843
  __cil_tmp191 = intel_sdvo->base.base.crtc;
#line 1843
  __cil_tmp192 = (unsigned long )__cil_tmp191;
#line 1843
  if (__cil_tmp192 != __cil_tmp190) {
    {
#line 1844
    crtc = intel_sdvo->base.base.crtc;
#line 1845
    __cil_tmp193 = & crtc->mode;
#line 1845
    __cil_tmp194 = crtc->x;
#line 1845
    __cil_tmp195 = crtc->y;
#line 1845
    __cil_tmp196 = crtc->fb;
#line 1845
    drm_crtc_helper_set_mode(crtc, __cil_tmp193, __cil_tmp194, __cil_tmp195, __cil_tmp196);
    }
  } else {

  }
  }
#line 1849
  return (0);
}
}
#line 1853 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct drm_encoder_helper_funcs  const  intel_sdvo_helper_funcs  = 
#line 1853
     {& intel_sdvo_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_sdvo_mode_fixup, & intel_encoder_prepare, & intel_encoder_commit, & intel_sdvo_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 1861 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct drm_connector_funcs  const  intel_sdvo_connector_funcs  = 
#line 1861
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    (void (*)(struct drm_connector * ))0, & intel_sdvo_detect, & drm_helper_probe_single_connector_modes,
    & intel_sdvo_set_property, & intel_sdvo_destroy, (void (*)(struct drm_connector * ))0};
#line 1869 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct drm_connector_helper_funcs  const  intel_sdvo_connector_helper_funcs  =    {& intel_sdvo_get_modes,
    & intel_sdvo_mode_valid, & intel_best_encoder};
#line 1875 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_enc_destroy(struct drm_encoder *encoder ) 
{ struct intel_sdvo *intel_sdvo ;
  struct intel_sdvo *tmp ;
  struct drm_display_mode *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct drm_display_mode *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct drm_device *__cil_tmp8 ;
  struct drm_display_mode *__cil_tmp9 ;
  struct i2c_adapter *__cil_tmp10 ;

  {
  {
#line 1877
  tmp = to_intel_sdvo(encoder);
#line 1877
  intel_sdvo = tmp;
  }
  {
#line 1879
  __cil_tmp4 = (struct drm_display_mode *)0;
#line 1879
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 1879
  __cil_tmp6 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 1879
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 1879
  if (__cil_tmp7 != __cil_tmp5) {
    {
#line 1880
    __cil_tmp8 = encoder->dev;
#line 1880
    __cil_tmp9 = intel_sdvo->sdvo_lvds_fixed_mode;
#line 1880
    drm_mode_destroy(__cil_tmp8, __cil_tmp9);
    }
  } else {

  }
  }
  {
#line 1883
  __cil_tmp10 = & intel_sdvo->ddc;
#line 1883
  i2c_del_adapter(__cil_tmp10);
#line 1884
  intel_encoder_destroy(encoder);
  }
#line 1885
  return;
}
}
#line 1887 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct drm_encoder_funcs  const  intel_sdvo_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_sdvo_enc_destroy};
#line 1892 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo ) 
{ uint16_t mask ;
  unsigned int num_bits ;
  uint16_t __cil_tmp4 ;
  int __cil_tmp5 ;
  uint16_t __cil_tmp6 ;
  int __cil_tmp7 ;
  uint16_t __cil_tmp8 ;
  int __cil_tmp9 ;
  uint16_t __cil_tmp10 ;
  int __cil_tmp11 ;
  uint16_t __cil_tmp12 ;
  int __cil_tmp13 ;
  uint16_t __cil_tmp14 ;
  int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  u16 __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;

  {
#line 1894
  mask = (uint16_t )0U;
  {
#line 1901
  __cil_tmp4 = sdvo->controlled_output;
#line 1901
  __cil_tmp5 = (int )__cil_tmp4;
#line 1901
  if (__cil_tmp5 == 16384) {
#line 1901
    goto case_16384;
  } else {
    {
#line 1903
    __cil_tmp6 = sdvo->controlled_output;
#line 1903
    __cil_tmp7 = (int )__cil_tmp6;
#line 1903
    if (__cil_tmp7 == 64) {
#line 1903
      goto case_64;
    } else {
      {
#line 1905
      __cil_tmp8 = sdvo->controlled_output;
#line 1905
      __cil_tmp9 = (int )__cil_tmp8;
#line 1905
      if (__cil_tmp9 == 256) {
#line 1905
        goto case_256;
      } else {
        {
#line 1907
        __cil_tmp10 = sdvo->controlled_output;
#line 1907
        __cil_tmp11 = (int )__cil_tmp10;
#line 1907
        if (__cil_tmp11 == 1) {
#line 1907
          goto case_1;
        } else {
          {
#line 1909
          __cil_tmp12 = sdvo->controlled_output;
#line 1909
          __cil_tmp13 = (int )__cil_tmp12;
#line 1909
          if (__cil_tmp13 == 512) {
#line 1909
            goto case_512;
          } else {
            {
#line 1911
            __cil_tmp14 = sdvo->controlled_output;
#line 1911
            __cil_tmp15 = (int )__cil_tmp14;
#line 1911
            if (__cil_tmp15 == 2) {
#line 1911
              goto case_2;
            } else
#line 1900
            if (0) {
              case_16384: 
#line 1902
              __cil_tmp16 = (unsigned int )mask;
#line 1902
              __cil_tmp17 = __cil_tmp16 | 16384U;
#line 1902
              mask = (uint16_t )__cil_tmp17;
              case_64: 
#line 1904
              __cil_tmp18 = (unsigned int )mask;
#line 1904
              __cil_tmp19 = __cil_tmp18 | 64U;
#line 1904
              mask = (uint16_t )__cil_tmp19;
              case_256: 
#line 1906
              __cil_tmp20 = (unsigned int )mask;
#line 1906
              __cil_tmp21 = __cil_tmp20 | 256U;
#line 1906
              mask = (uint16_t )__cil_tmp21;
              case_1: 
#line 1908
              __cil_tmp22 = (unsigned int )mask;
#line 1908
              __cil_tmp23 = __cil_tmp22 | 1U;
#line 1908
              mask = (uint16_t )__cil_tmp23;
              case_512: 
#line 1910
              __cil_tmp24 = (unsigned int )mask;
#line 1910
              __cil_tmp25 = __cil_tmp24 | 512U;
#line 1910
              mask = (uint16_t )__cil_tmp25;
              case_2: 
#line 1912
              __cil_tmp26 = (unsigned int )mask;
#line 1912
              __cil_tmp27 = __cil_tmp26 | 2U;
#line 1912
              mask = (uint16_t )__cil_tmp27;
#line 1913
              goto ldv_38437;
            } else {

            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_38437: 
  {
#line 1917
  __cil_tmp28 = (int )mask;
#line 1917
  __cil_tmp29 = sdvo->caps.output_flags;
#line 1917
  __cil_tmp30 = (int )__cil_tmp29;
#line 1917
  __cil_tmp31 = __cil_tmp30 & __cil_tmp28;
#line 1917
  mask = (uint16_t )__cil_tmp31;
#line 1918
  __cil_tmp32 = (unsigned int )mask;
#line 1918
  num_bits = __arch_hweight16(__cil_tmp32);
  }
#line 1920
  if (num_bits > 3U) {
#line 1921
    num_bits = 3U;
  } else {

  }
#line 1924
  __cil_tmp33 = (int )num_bits;
#line 1924
  __cil_tmp34 = 1 << __cil_tmp33;
#line 1924
  sdvo->ddc_bus = (uint8_t )__cil_tmp34;
#line 1925
  return;
}
}
#line 1935 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv , struct intel_sdvo *sdvo ,
                                      u32 reg ) 
{ struct sdvo_device_mapping *mapping ;
  struct sdvo_device_mapping (*__cil_tmp5)[2U] ;
  struct sdvo_device_mapping (*__cil_tmp6)[2U] ;
  struct sdvo_device_mapping (*__cil_tmp7)[2U] ;
  struct sdvo_device_mapping *__cil_tmp8 ;
  u8 __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  u8 __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;

  {
#line 1940
  if (reg == 397632U) {
#line 1941
    __cil_tmp5 = & dev_priv->sdvo_mappings;
#line 1941
    mapping = (struct sdvo_device_mapping *)__cil_tmp5;
  } else
#line 1940
  if (reg == 921920U) {
#line 1941
    __cil_tmp6 = & dev_priv->sdvo_mappings;
#line 1941
    mapping = (struct sdvo_device_mapping *)__cil_tmp6;
  } else {
#line 1943
    __cil_tmp7 = & dev_priv->sdvo_mappings;
#line 1943
    __cil_tmp8 = (struct sdvo_device_mapping *)__cil_tmp7;
#line 1943
    mapping = __cil_tmp8 + 1UL;
  }
  {
#line 1945
  __cil_tmp9 = mapping->initialized;
#line 1945
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 1945
  if (__cil_tmp10 != 0U) {
#line 1946
    __cil_tmp11 = mapping->ddc_pin;
#line 1946
    __cil_tmp12 = (int )__cil_tmp11;
#line 1946
    __cil_tmp13 = __cil_tmp12 >> 4;
#line 1946
    __cil_tmp14 = 1 << __cil_tmp13;
#line 1946
    sdvo->ddc_bus = (uint8_t )__cil_tmp14;
  } else {
    {
#line 1948
    intel_sdvo_guess_ddc_bus(sdvo);
    }
  }
  }
#line 1949
  return;
}
}
#line 1952 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv , struct intel_sdvo *sdvo ,
                                      u32 reg ) 
{ struct sdvo_device_mapping *mapping ;
  u8 pin ;
  u8 speed ;
  struct sdvo_device_mapping (*__cil_tmp7)[2U] ;
  struct sdvo_device_mapping (*__cil_tmp8)[2U] ;
  struct sdvo_device_mapping (*__cil_tmp9)[2U] ;
  struct sdvo_device_mapping *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct intel_gmbus *__cil_tmp15 ;
  struct intel_gmbus *__cil_tmp16 ;
  struct i2c_adapter *__cil_tmp17 ;
  int __cil_tmp18 ;
  struct i2c_adapter *__cil_tmp19 ;
  bool __cil_tmp20 ;
  struct intel_gmbus *__cil_tmp21 ;
  struct intel_gmbus *__cil_tmp22 ;

  {
#line 1958
  if (reg == 397632U) {
#line 1959
    __cil_tmp7 = & dev_priv->sdvo_mappings;
#line 1959
    mapping = (struct sdvo_device_mapping *)__cil_tmp7;
  } else
#line 1958
  if (reg == 921920U) {
#line 1959
    __cil_tmp8 = & dev_priv->sdvo_mappings;
#line 1959
    mapping = (struct sdvo_device_mapping *)__cil_tmp8;
  } else {
#line 1961
    __cil_tmp9 = & dev_priv->sdvo_mappings;
#line 1961
    __cil_tmp10 = (struct sdvo_device_mapping *)__cil_tmp9;
#line 1961
    mapping = __cil_tmp10 + 1UL;
  }
#line 1963
  pin = (u8 )5U;
#line 1964
  speed = (u8 )3U;
  {
#line 1965
  __cil_tmp11 = mapping->initialized;
#line 1965
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1965
  if (__cil_tmp12 != 0U) {
#line 1966
    pin = mapping->i2c_pin;
#line 1967
    speed = mapping->i2c_speed;
  } else {

  }
  }
  {
#line 1970
  __cil_tmp13 = (unsigned int )pin;
#line 1970
  if (__cil_tmp13 <= 7U) {
    {
#line 1971
    __cil_tmp14 = (unsigned long )pin;
#line 1971
    __cil_tmp15 = dev_priv->gmbus;
#line 1971
    __cil_tmp16 = __cil_tmp15 + __cil_tmp14;
#line 1971
    sdvo->i2c = & __cil_tmp16->adapter;
#line 1972
    __cil_tmp17 = sdvo->i2c;
#line 1972
    __cil_tmp18 = (int )speed;
#line 1972
    intel_gmbus_set_speed(__cil_tmp17, __cil_tmp18);
#line 1973
    __cil_tmp19 = sdvo->i2c;
#line 1973
    __cil_tmp20 = (bool )1;
#line 1973
    intel_gmbus_force_bit(__cil_tmp19, __cil_tmp20);
    }
  } else {
#line 1975
    __cil_tmp21 = dev_priv->gmbus;
#line 1975
    __cil_tmp22 = __cil_tmp21 + 5UL;
#line 1975
    sdvo->i2c = & __cil_tmp22->adapter;
  }
  }
#line 1976
  return;
}
}
#line 1979 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo , int device ) 
{ bool tmp ;

  {
  {
#line 1981
  tmp = intel_sdvo_check_supp_encode(intel_sdvo);
  }
#line 1981
  return (tmp);
}
}
#line 1985 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static u8 intel_sdvo_get_slave_addr(struct drm_device *dev , int sdvo_reg ) 
{ struct drm_i915_private *dev_priv ;
  struct sdvo_device_mapping *my_mapping ;
  struct sdvo_device_mapping *other_mapping ;
  void *__cil_tmp6 ;
  struct sdvo_device_mapping (*__cil_tmp7)[2U] ;
  struct sdvo_device_mapping (*__cil_tmp8)[2U] ;
  struct sdvo_device_mapping *__cil_tmp9 ;
  struct sdvo_device_mapping (*__cil_tmp10)[2U] ;
  struct sdvo_device_mapping (*__cil_tmp11)[2U] ;
  struct sdvo_device_mapping *__cil_tmp12 ;
  struct sdvo_device_mapping (*__cil_tmp13)[2U] ;
  struct sdvo_device_mapping *__cil_tmp14 ;
  struct sdvo_device_mapping (*__cil_tmp15)[2U] ;
  u8 __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  u8 __cil_tmp20 ;
  unsigned int __cil_tmp21 ;

  {
#line 1987
  __cil_tmp6 = dev->dev_private;
#line 1987
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 1990
  if (sdvo_reg == 397632) {
#line 1991
    __cil_tmp7 = & dev_priv->sdvo_mappings;
#line 1991
    my_mapping = (struct sdvo_device_mapping *)__cil_tmp7;
#line 1992
    __cil_tmp8 = & dev_priv->sdvo_mappings;
#line 1992
    __cil_tmp9 = (struct sdvo_device_mapping *)__cil_tmp8;
#line 1992
    other_mapping = __cil_tmp9 + 1UL;
  } else
#line 1990
  if (sdvo_reg == 921920) {
#line 1991
    __cil_tmp10 = & dev_priv->sdvo_mappings;
#line 1991
    my_mapping = (struct sdvo_device_mapping *)__cil_tmp10;
#line 1992
    __cil_tmp11 = & dev_priv->sdvo_mappings;
#line 1992
    __cil_tmp12 = (struct sdvo_device_mapping *)__cil_tmp11;
#line 1992
    other_mapping = __cil_tmp12 + 1UL;
  } else {
#line 1994
    __cil_tmp13 = & dev_priv->sdvo_mappings;
#line 1994
    __cil_tmp14 = (struct sdvo_device_mapping *)__cil_tmp13;
#line 1994
    my_mapping = __cil_tmp14 + 1UL;
#line 1995
    __cil_tmp15 = & dev_priv->sdvo_mappings;
#line 1995
    other_mapping = (struct sdvo_device_mapping *)__cil_tmp15;
  }
  {
#line 1999
  __cil_tmp16 = my_mapping->slave_addr;
#line 1999
  __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 1999
  if (__cil_tmp17 != 0U) {
#line 2000
    return (my_mapping->slave_addr);
  } else {

  }
  }
  {
#line 2005
  __cil_tmp18 = other_mapping->slave_addr;
#line 2005
  __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 2005
  if (__cil_tmp19 != 0U) {
    {
#line 2006
    __cil_tmp20 = other_mapping->slave_addr;
#line 2006
    __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 2006
    if (__cil_tmp21 == 112U) {
#line 2007
      return ((u8 )114U);
    } else {
#line 2009
      return ((u8 )112U);
    }
    }
  } else {

  }
  }
#line 2015
  if (sdvo_reg == 397632) {
#line 2016
    return ((u8 )112U);
  } else
#line 2015
  if (sdvo_reg == 921920) {
#line 2016
    return ((u8 )112U);
  } else {
#line 2018
    return ((u8 )114U);
  }
}
}
#line 2022 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_connector_init(struct intel_sdvo_connector *connector , struct intel_sdvo *encoder ) 
{ struct drm_device *__cil_tmp3 ;
  struct drm_connector *__cil_tmp4 ;
  int __cil_tmp5 ;
  struct drm_connector *__cil_tmp6 ;
  struct intel_connector *__cil_tmp7 ;
  struct intel_encoder *__cil_tmp8 ;
  struct drm_connector *__cil_tmp9 ;

  {
  {
#line 2025
  __cil_tmp3 = encoder->base.base.dev;
#line 2025
  __cil_tmp4 = & connector->base.base;
#line 2025
  __cil_tmp5 = connector->base.base.connector_type;
#line 2025
  drm_connector_init(__cil_tmp3, __cil_tmp4, & intel_sdvo_connector_funcs, __cil_tmp5);
#line 2030
  __cil_tmp6 = & connector->base.base;
#line 2030
  drm_connector_helper_add(__cil_tmp6, & intel_sdvo_connector_helper_funcs);
#line 2033
  connector->base.base.interlace_allowed = (bool )0;
#line 2034
  connector->base.base.doublescan_allowed = (bool )0;
#line 2035
  connector->base.base.display_info.subpixel_order = (enum subpixel_order )1;
#line 2037
  __cil_tmp7 = & connector->base;
#line 2037
  __cil_tmp8 = & encoder->base;
#line 2037
  intel_connector_attach_encoder(__cil_tmp7, __cil_tmp8);
#line 2038
  __cil_tmp9 = & connector->base.base;
#line 2038
  drm_sysfs_connector_add(__cil_tmp9);
  }
#line 2039
  return;
}
}
#line 2042 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static void intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_connector *__cil_tmp3 ;
  void *__cil_tmp4 ;
  struct drm_i915_private *__cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  void *__cil_tmp10 ;
  struct drm_i915_private *__cil_tmp11 ;
  struct intel_device_info  const  *__cil_tmp12 ;
  unsigned char *__cil_tmp13 ;
  unsigned char *__cil_tmp14 ;
  unsigned char __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  struct drm_connector *__cil_tmp17 ;

  {
  {
#line 2044
  dev = connector->base.base.dev;
#line 2046
  __cil_tmp3 = & connector->base.base;
#line 2046
  intel_attach_force_audio_property(__cil_tmp3);
  }
  {
#line 2047
  __cil_tmp4 = dev->dev_private;
#line 2047
  __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
#line 2047
  __cil_tmp6 = __cil_tmp5->info;
#line 2047
  __cil_tmp7 = __cil_tmp6->gen;
#line 2047
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 2047
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 2047
  if (__cil_tmp9 > 3U) {
    {
#line 2047
    __cil_tmp10 = dev->dev_private;
#line 2047
    __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
#line 2047
    __cil_tmp12 = __cil_tmp11->info;
#line 2047
    __cil_tmp13 = (unsigned char *)__cil_tmp12;
#line 2047
    __cil_tmp14 = __cil_tmp13 + 1UL;
#line 2047
    __cil_tmp15 = *__cil_tmp14;
#line 2047
    __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 2047
    if (__cil_tmp16 != 0U) {
      {
#line 2048
      __cil_tmp17 = & connector->base.base;
#line 2048
      intel_attach_broadcast_rgb_property(__cil_tmp17);
      }
    } else {

    }
    }
  } else {

  }
  }
#line 2049
  return;
}
}
#line 2052 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo , int device ) 
{ struct drm_encoder *encoder ;
  struct drm_connector *connector ;
  struct intel_connector *intel_connector ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  void *tmp ;
  bool tmp___0 ;
  struct intel_sdvo_connector *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  uint16_t __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  uint16_t __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  bool __cil_tmp18 ;

  {
  {
#line 2054
  encoder = & intel_sdvo->base.base;
#line 2059
  tmp = kzalloc(1880UL, 208U);
#line 2059
  intel_sdvo_connector = (struct intel_sdvo_connector *)tmp;
  }
  {
#line 2060
  __cil_tmp9 = (struct intel_sdvo_connector *)0;
#line 2060
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 2060
  __cil_tmp11 = (unsigned long )intel_sdvo_connector;
#line 2060
  if (__cil_tmp11 == __cil_tmp10) {
#line 2061
    return ((bool )0);
  } else {

  }
  }
#line 2063
  if (device == 0) {
#line 2064
    __cil_tmp12 = intel_sdvo->controlled_output;
#line 2064
    __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 2064
    __cil_tmp14 = __cil_tmp13 | 1U;
#line 2064
    intel_sdvo->controlled_output = (uint16_t )__cil_tmp14;
#line 2065
    intel_sdvo_connector->output_flag = (uint16_t )1U;
  } else
#line 2066
  if (device == 1) {
#line 2067
    __cil_tmp15 = intel_sdvo->controlled_output;
#line 2067
    __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 2067
    __cil_tmp17 = __cil_tmp16 | 256U;
#line 2067
    intel_sdvo->controlled_output = (uint16_t )__cil_tmp17;
#line 2068
    intel_sdvo_connector->output_flag = (uint16_t )256U;
  } else {

  }
  {
#line 2071
  intel_connector = & intel_sdvo_connector->base;
#line 2072
  connector = & intel_connector->base;
#line 2073
  connector->polled = (uint8_t )6U;
#line 2074
  encoder->encoder_type = 2;
#line 2075
  connector->connector_type = 3;
#line 2077
  tmp___0 = intel_sdvo_is_hdmi_connector(intel_sdvo, device);
  }
#line 2077
  if ((int )tmp___0) {
#line 2078
    connector->connector_type = 11;
#line 2079
    intel_sdvo->is_hdmi = (bool )1;
  } else {

  }
  {
#line 2081
  intel_sdvo->base.clone_mask = 576;
#line 2084
  intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  }
  {
#line 2085
  __cil_tmp18 = intel_sdvo->is_hdmi;
#line 2085
  if ((int )__cil_tmp18) {
    {
#line 2086
    intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
    }
  } else {

  }
  }
#line 2088
  return ((bool )1);
}
}
#line 2092 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo , int type ) 
{ struct drm_encoder *encoder ;
  struct drm_connector *connector ;
  struct intel_connector *intel_connector ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  void *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  struct intel_sdvo_connector *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  short __cil_tmp15 ;
  int __cil_tmp16 ;
  uint16_t __cil_tmp17 ;
  short __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;

  {
  {
#line 2094
  encoder = & intel_sdvo->base.base;
#line 2099
  tmp = kzalloc(1880UL, 208U);
#line 2099
  intel_sdvo_connector = (struct intel_sdvo_connector *)tmp;
  }
  {
#line 2100
  __cil_tmp12 = (struct intel_sdvo_connector *)0;
#line 2100
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 2100
  __cil_tmp14 = (unsigned long )intel_sdvo_connector;
#line 2100
  if (__cil_tmp14 == __cil_tmp13) {
#line 2101
    return ((bool )0);
  } else {

  }
  }
  {
#line 2103
  intel_connector = & intel_sdvo_connector->base;
#line 2104
  connector = & intel_connector->base;
#line 2105
  encoder->encoder_type = 4;
#line 2106
  connector->connector_type = 6;
#line 2108
  __cil_tmp15 = (short )type;
#line 2108
  __cil_tmp16 = (int )__cil_tmp15;
#line 2108
  __cil_tmp17 = intel_sdvo->controlled_output;
#line 2108
  __cil_tmp18 = (short )__cil_tmp17;
#line 2108
  __cil_tmp19 = (int )__cil_tmp18;
#line 2108
  __cil_tmp20 = __cil_tmp19 | __cil_tmp16;
#line 2108
  intel_sdvo->controlled_output = (uint16_t )__cil_tmp20;
#line 2109
  intel_sdvo_connector->output_flag = (uint16_t )type;
#line 2111
  intel_sdvo->is_tv = (bool )1;
#line 2112
  intel_sdvo->base.needs_tv_clock = (bool )1;
#line 2113
  intel_sdvo->base.clone_mask = 128;
#line 2115
  intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
#line 2117
  tmp___0 = intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type);
  }
#line 2117
  if (tmp___0) {
#line 2117
    tmp___1 = 0;
  } else {
#line 2117
    tmp___1 = 1;
  }
#line 2117
  if (tmp___1) {
#line 2118
    goto err;
  } else {

  }
  {
#line 2120
  tmp___2 = intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector);
  }
#line 2120
  if (tmp___2) {
#line 2120
    tmp___3 = 0;
  } else {
#line 2120
    tmp___3 = 1;
  }
#line 2120
  if (tmp___3) {
#line 2121
    goto err;
  } else {

  }
#line 2123
  return ((bool )1);
  err: 
  {
#line 2126
  intel_sdvo_destroy(connector);
  }
#line 2127
  return ((bool )0);
}
}
#line 2131 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo , int device ) 
{ struct drm_encoder *encoder ;
  struct drm_connector *connector ;
  struct intel_connector *intel_connector ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  void *tmp ;
  struct intel_sdvo_connector *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  uint16_t __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  uint16_t __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;

  {
  {
#line 2133
  encoder = & intel_sdvo->base.base;
#line 2138
  tmp = kzalloc(1880UL, 208U);
#line 2138
  intel_sdvo_connector = (struct intel_sdvo_connector *)tmp;
  }
  {
#line 2139
  __cil_tmp8 = (struct intel_sdvo_connector *)0;
#line 2139
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 2139
  __cil_tmp10 = (unsigned long )intel_sdvo_connector;
#line 2139
  if (__cil_tmp10 == __cil_tmp9) {
#line 2140
    return ((bool )0);
  } else {

  }
  }
#line 2142
  intel_connector = & intel_sdvo_connector->base;
#line 2143
  connector = & intel_connector->base;
#line 2144
  connector->polled = (uint8_t )2U;
#line 2145
  encoder->encoder_type = 1;
#line 2146
  connector->connector_type = 1;
#line 2148
  if (device == 0) {
#line 2149
    __cil_tmp11 = intel_sdvo->controlled_output;
#line 2149
    __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 2149
    __cil_tmp13 = __cil_tmp12 | 2U;
#line 2149
    intel_sdvo->controlled_output = (uint16_t )__cil_tmp13;
#line 2150
    intel_sdvo_connector->output_flag = (uint16_t )2U;
  } else
#line 2151
  if (device == 1) {
#line 2152
    __cil_tmp14 = intel_sdvo->controlled_output;
#line 2152
    __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 2152
    __cil_tmp16 = __cil_tmp15 | 512U;
#line 2152
    intel_sdvo->controlled_output = (uint16_t )__cil_tmp16;
#line 2153
    intel_sdvo_connector->output_flag = (uint16_t )512U;
  } else {

  }
  {
#line 2156
  intel_sdvo->base.clone_mask = 576;
#line 2159
  intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  }
#line 2161
  return ((bool )1);
}
}
#line 2165 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo , int device ) 
{ struct drm_encoder *encoder ;
  struct drm_connector *connector ;
  struct intel_connector *intel_connector ;
  struct intel_sdvo_connector *intel_sdvo_connector ;
  void *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  struct intel_sdvo_connector *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  uint16_t __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  uint16_t __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;

  {
  {
#line 2167
  encoder = & intel_sdvo->base.base;
#line 2172
  tmp = kzalloc(1880UL, 208U);
#line 2172
  intel_sdvo_connector = (struct intel_sdvo_connector *)tmp;
  }
  {
#line 2173
  __cil_tmp10 = (struct intel_sdvo_connector *)0;
#line 2173
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 2173
  __cil_tmp12 = (unsigned long )intel_sdvo_connector;
#line 2173
  if (__cil_tmp12 == __cil_tmp11) {
#line 2174
    return ((bool )0);
  } else {

  }
  }
#line 2176
  intel_connector = & intel_sdvo_connector->base;
#line 2177
  connector = & intel_connector->base;
#line 2178
  encoder->encoder_type = 3;
#line 2179
  connector->connector_type = 7;
#line 2181
  if (device == 0) {
#line 2182
    __cil_tmp13 = intel_sdvo->controlled_output;
#line 2182
    __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 2182
    __cil_tmp15 = __cil_tmp14 | 64U;
#line 2182
    intel_sdvo->controlled_output = (uint16_t )__cil_tmp15;
#line 2183
    intel_sdvo_connector->output_flag = (uint16_t )64U;
  } else
#line 2184
  if (device == 1) {
#line 2185
    __cil_tmp16 = intel_sdvo->controlled_output;
#line 2185
    __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 2185
    __cil_tmp18 = __cil_tmp17 | 16384U;
#line 2185
    intel_sdvo->controlled_output = (uint16_t )__cil_tmp18;
#line 2186
    intel_sdvo_connector->output_flag = (uint16_t )16384U;
  } else {

  }
  {
#line 2189
  intel_sdvo->base.clone_mask = 768;
#line 2192
  intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
#line 2193
  tmp___0 = intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector);
  }
#line 2193
  if (tmp___0) {
#line 2193
    tmp___1 = 0;
  } else {
#line 2193
    tmp___1 = 1;
  }
#line 2193
  if (tmp___1) {
#line 2194
    goto err;
  } else {

  }
#line 2196
  return ((bool )1);
  err: 
  {
#line 2199
  intel_sdvo_destroy(connector);
  }
#line 2200
  return ((bool )0);
}
}
#line 2204 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo , uint16_t flags ) 
{ bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  bool tmp___5 ;
  int tmp___6 ;
  bool tmp___7 ;
  int tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  bool tmp___11 ;
  int tmp___12 ;
  bool tmp___13 ;
  int tmp___14 ;
  unsigned char bytes[2U] ;
  size_t __len ;
  void *__ret ;
  char *tmp___15 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  void *__cil_tmp40 ;
  u16 *__cil_tmp41 ;
  void const   *__cil_tmp42 ;
  void *__cil_tmp43 ;
  u16 *__cil_tmp44 ;
  void const   *__cil_tmp45 ;
  int __cil_tmp46 ;
  int __cil_tmp47 ;
  int __cil_tmp48 ;
  int __cil_tmp49 ;

  {
#line 2206
  intel_sdvo->is_tv = (bool )0;
#line 2207
  intel_sdvo->base.needs_tv_clock = (bool )0;
#line 2208
  intel_sdvo->is_lvds = (bool )0;
  {
#line 2212
  __cil_tmp23 = (int )flags;
#line 2212
  if (__cil_tmp23 & 1) {
    {
#line 2213
    tmp = intel_sdvo_dvi_init(intel_sdvo, 0);
    }
#line 2213
    if (tmp) {
#line 2213
      tmp___0 = 0;
    } else {
#line 2213
      tmp___0 = 1;
    }
#line 2213
    if (tmp___0) {
#line 2214
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2216
  __cil_tmp24 = (int )flags;
#line 2216
  __cil_tmp25 = __cil_tmp24 & 257;
#line 2216
  if (__cil_tmp25 == 257) {
    {
#line 2217
    tmp___1 = intel_sdvo_dvi_init(intel_sdvo, 1);
    }
#line 2217
    if (tmp___1) {
#line 2217
      tmp___2 = 0;
    } else {
#line 2217
      tmp___2 = 1;
    }
#line 2217
    if (tmp___2) {
#line 2218
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2221
  __cil_tmp26 = (int )flags;
#line 2221
  __cil_tmp27 = __cil_tmp26 & 8;
#line 2221
  if (__cil_tmp27 != 0) {
    {
#line 2222
    tmp___3 = intel_sdvo_tv_init(intel_sdvo, 8);
    }
#line 2222
    if (tmp___3) {
#line 2222
      tmp___4 = 0;
    } else {
#line 2222
      tmp___4 = 1;
    }
#line 2222
    if (tmp___4) {
#line 2223
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2225
  __cil_tmp28 = (int )flags;
#line 2225
  __cil_tmp29 = __cil_tmp28 & 4;
#line 2225
  if (__cil_tmp29 != 0) {
    {
#line 2226
    tmp___5 = intel_sdvo_tv_init(intel_sdvo, 4);
    }
#line 2226
    if (tmp___5) {
#line 2226
      tmp___6 = 0;
    } else {
#line 2226
      tmp___6 = 1;
    }
#line 2226
    if (tmp___6) {
#line 2227
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2229
  __cil_tmp30 = (int )flags;
#line 2229
  __cil_tmp31 = __cil_tmp30 & 2;
#line 2229
  if (__cil_tmp31 != 0) {
    {
#line 2230
    tmp___7 = intel_sdvo_analog_init(intel_sdvo, 0);
    }
#line 2230
    if (tmp___7) {
#line 2230
      tmp___8 = 0;
    } else {
#line 2230
      tmp___8 = 1;
    }
#line 2230
    if (tmp___8) {
#line 2231
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2233
  __cil_tmp32 = (int )flags;
#line 2233
  __cil_tmp33 = __cil_tmp32 & 514;
#line 2233
  if (__cil_tmp33 == 514) {
    {
#line 2234
    tmp___9 = intel_sdvo_analog_init(intel_sdvo, 1);
    }
#line 2234
    if (tmp___9) {
#line 2234
      tmp___10 = 0;
    } else {
#line 2234
      tmp___10 = 1;
    }
#line 2234
    if (tmp___10) {
#line 2235
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2237
  __cil_tmp34 = (int )flags;
#line 2237
  __cil_tmp35 = __cil_tmp34 & 64;
#line 2237
  if (__cil_tmp35 != 0) {
    {
#line 2238
    tmp___11 = intel_sdvo_lvds_init(intel_sdvo, 0);
    }
#line 2238
    if (tmp___11) {
#line 2238
      tmp___12 = 0;
    } else {
#line 2238
      tmp___12 = 1;
    }
#line 2238
    if (tmp___12) {
#line 2239
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2241
  __cil_tmp36 = (int )flags;
#line 2241
  __cil_tmp37 = __cil_tmp36 & 16448;
#line 2241
  if (__cil_tmp37 == 16448) {
    {
#line 2242
    tmp___13 = intel_sdvo_lvds_init(intel_sdvo, 1);
    }
#line 2242
    if (tmp___13) {
#line 2242
      tmp___14 = 0;
    } else {
#line 2242
      tmp___14 = 1;
    }
#line 2242
    if (tmp___14) {
#line 2243
      return ((bool )0);
    } else {

    }
  } else {

  }
  }
  {
#line 2245
  __cil_tmp38 = (int )flags;
#line 2245
  __cil_tmp39 = __cil_tmp38 & 17231;
#line 2245
  if (__cil_tmp39 == 0) {
#line 2248
    intel_sdvo->controlled_output = (uint16_t )0U;
#line 2249
    __len = 2UL;
#line 2249
    if (__len > 63UL) {
      {
#line 2249
      __cil_tmp40 = (void *)(& bytes);
#line 2249
      __cil_tmp41 = & intel_sdvo->caps.output_flags;
#line 2249
      __cil_tmp42 = (void const   *)__cil_tmp41;
#line 2249
      __ret = __memcpy(__cil_tmp40, __cil_tmp42, __len);
      }
    } else {
      {
#line 2249
      __cil_tmp43 = (void *)(& bytes);
#line 2249
      __cil_tmp44 = & intel_sdvo->caps.output_flags;
#line 2249
      __cil_tmp45 = (void const   *)__cil_tmp44;
#line 2249
      __ret = __builtin_memcpy(__cil_tmp43, __cil_tmp45, __len);
      }
    }
    {
#line 2250
    __cil_tmp46 = intel_sdvo->sdvo_reg;
#line 2250
    if (__cil_tmp46 == 397632) {
#line 2250
      tmp___15 = (char *)"SDVOB";
    } else {
      {
#line 2250
      __cil_tmp47 = intel_sdvo->sdvo_reg;
#line 2250
      if (__cil_tmp47 == 921920) {
#line 2250
        tmp___15 = (char *)"SDVOB";
      } else {
#line 2250
        tmp___15 = (char *)"SDVOC";
      }
      }
    }
    }
    {
#line 2250
    __cil_tmp48 = (int )bytes[0];
#line 2250
    __cil_tmp49 = (int )bytes[1];
#line 2250
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_output_setup", "%s: Unknown SDVO output type (0x%02x%02x)\n",
                        tmp___15, __cil_tmp48, __cil_tmp49);
    }
#line 2253
    return ((bool )0);
  } else {

  }
  }
#line 2255
  intel_sdvo->base.crtc_mask = 3;
#line 2257
  return ((bool )1);
}
}
#line 2260 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo , struct intel_sdvo_connector *intel_sdvo_connector ,
                                          int type ) 
{ struct drm_device *dev ;
  struct intel_sdvo_tv_format format ;
  uint32_t format_map ;
  uint32_t i ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  size_t __len ;
  unsigned long _min1 ;
  unsigned long _min2 ;
  unsigned long tmp___3 ;
  void *__ret ;
  int tmp___4 ;
  u16 __cil_tmp18 ;
  int __cil_tmp19 ;
  u16 __cil_tmp20 ;
  u8 __cil_tmp21 ;
  void *__cil_tmp22 ;
  void *__cil_tmp23 ;
  void const   *__cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  uint32_t __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  struct drm_property *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  struct drm_property *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  struct drm_property *__cil_tmp35 ;
  int __cil_tmp36 ;
  uint64_t __cil_tmp37 ;
  int __cil_tmp38 ;
  uint32_t __cil_tmp39 ;
  u8 __cil_tmp40 ;
  struct drm_connector *__cil_tmp41 ;
  struct drm_property *__cil_tmp42 ;

  {
  {
#line 2264
  dev = intel_sdvo->base.base.dev;
#line 2268
  __cil_tmp18 = (u16 )type;
#line 2268
  __cil_tmp19 = (int )__cil_tmp18;
#line 2268
  __cil_tmp20 = (u16 )__cil_tmp19;
#line 2268
  tmp = intel_sdvo_set_target_output(intel_sdvo, __cil_tmp20);
  }
#line 2268
  if (tmp) {
#line 2268
    tmp___0 = 0;
  } else {
#line 2268
    tmp___0 = 1;
  }
#line 2268
  if (tmp___0) {
#line 2269
    return ((bool )0);
  } else {

  }
  {
#line 2272
  __cil_tmp21 = (u8 )39;
#line 2272
  __cil_tmp22 = (void *)(& format);
#line 2272
  tmp___1 = intel_sdvo_get_value(intel_sdvo, __cil_tmp21, __cil_tmp22, 6);
  }
#line 2272
  if (tmp___1) {
#line 2272
    tmp___2 = 0;
  } else {
#line 2272
    tmp___2 = 1;
  }
#line 2272
  if (tmp___2) {
#line 2275
    return ((bool )0);
  } else {

  }
#line 2277
  _min1 = 4UL;
#line 2277
  _min2 = 6UL;
#line 2277
  if (_min1 < _min2) {
#line 2277
    tmp___3 = _min1;
  } else {
#line 2277
    tmp___3 = _min2;
  }
  {
#line 2277
  __len = tmp___3;
#line 2277
  __cil_tmp23 = (void *)(& format_map);
#line 2277
  __cil_tmp24 = (void const   *)(& format);
#line 2277
  __ret = __builtin_memcpy(__cil_tmp23, __cil_tmp24, __len);
  }
#line 2279
  if (format_map == 0U) {
#line 2280
    return ((bool )0);
  } else {

  }
#line 2282
  intel_sdvo_connector->format_supported_num = 0;
#line 2283
  i = 0U;
#line 2283
  goto ldv_38533;
  ldv_38532: ;
  {
#line 2284
  __cil_tmp25 = (int )i;
#line 2284
  __cil_tmp26 = 1 << __cil_tmp25;
#line 2284
  __cil_tmp27 = (uint32_t )__cil_tmp26;
#line 2284
  __cil_tmp28 = __cil_tmp27 & format_map;
#line 2284
  if (__cil_tmp28 != 0U) {
#line 2285
    tmp___4 = intel_sdvo_connector->format_supported_num;
#line 2285
    __cil_tmp29 = intel_sdvo_connector->format_supported_num;
#line 2285
    intel_sdvo_connector->format_supported_num = __cil_tmp29 + 1;
#line 2285
    intel_sdvo_connector->tv_format_supported[tmp___4] = (u8 )i;
  } else {

  }
  }
#line 2283
  i = i + 1U;
  ldv_38533: ;
#line 2283
  if (i <= 18U) {
#line 2284
    goto ldv_38532;
  } else {
#line 2286
    goto ldv_38534;
  }
  ldv_38534: 
  {
#line 2288
  __cil_tmp30 = intel_sdvo_connector->format_supported_num;
#line 2288
  intel_sdvo_connector->tv_format = drm_property_create(dev, 8, "mode", __cil_tmp30);
  }
  {
#line 2291
  __cil_tmp31 = (struct drm_property *)0;
#line 2291
  __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 2291
  __cil_tmp33 = intel_sdvo_connector->tv_format;
#line 2291
  __cil_tmp34 = (unsigned long )__cil_tmp33;
#line 2291
  if (__cil_tmp34 == __cil_tmp32) {
#line 2292
    return ((bool )0);
  } else {

  }
  }
#line 2294
  i = 0U;
#line 2294
  goto ldv_38536;
  ldv_38535: 
  {
#line 2295
  __cil_tmp35 = intel_sdvo_connector->tv_format;
#line 2295
  __cil_tmp36 = (int )i;
#line 2295
  __cil_tmp37 = (uint64_t )i;
#line 2295
  drm_property_add_enum(__cil_tmp35, __cil_tmp36, __cil_tmp37, tv_format_names[(int )intel_sdvo_connector->tv_format_supported[i]]);
#line 2294
  i = i + 1U;
  }
  ldv_38536: ;
  {
#line 2294
  __cil_tmp38 = intel_sdvo_connector->format_supported_num;
#line 2294
  __cil_tmp39 = (uint32_t )__cil_tmp38;
#line 2294
  if (__cil_tmp39 > i) {
#line 2295
    goto ldv_38535;
  } else {
#line 2297
    goto ldv_38537;
  }
  }
  ldv_38537: 
  {
#line 2299
  __cil_tmp40 = intel_sdvo_connector->tv_format_supported[0];
#line 2299
  intel_sdvo->tv_format_index = (int )__cil_tmp40;
#line 2300
  __cil_tmp41 = & intel_sdvo_connector->base.base;
#line 2300
  __cil_tmp42 = intel_sdvo_connector->tv_format;
#line 2300
  drm_connector_attach_property(__cil_tmp41, __cil_tmp42, 0ULL);
  }
#line 2302
  return ((bool )1);
}
}
#line 2327 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo ,
                                                  struct intel_sdvo_connector *intel_sdvo_connector ,
                                                  struct intel_sdvo_enhancements_reply enhancements ) 
{ struct drm_device *dev ;
  struct drm_connector *connector ;
  uint16_t response ;
  uint16_t data_value[2U] ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  bool tmp___5 ;
  int tmp___6 ;
  bool tmp___7 ;
  int tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  bool tmp___11 ;
  int tmp___12 ;
  bool tmp___13 ;
  int tmp___14 ;
  bool tmp___15 ;
  int tmp___16 ;
  bool tmp___17 ;
  int tmp___18 ;
  bool tmp___19 ;
  int tmp___20 ;
  bool tmp___21 ;
  int tmp___22 ;
  bool tmp___23 ;
  int tmp___24 ;
  bool tmp___25 ;
  int tmp___26 ;
  bool tmp___27 ;
  int tmp___28 ;
  bool tmp___29 ;
  int tmp___30 ;
  bool tmp___31 ;
  int tmp___32 ;
  bool tmp___33 ;
  int tmp___34 ;
  bool tmp___35 ;
  int tmp___36 ;
  bool tmp___37 ;
  int tmp___38 ;
  bool tmp___39 ;
  int tmp___40 ;
  bool tmp___41 ;
  int tmp___42 ;
  bool tmp___43 ;
  int tmp___44 ;
  bool tmp___45 ;
  int tmp___46 ;
  bool tmp___47 ;
  int tmp___48 ;
  bool tmp___49 ;
  int tmp___50 ;
  bool tmp___51 ;
  int tmp___52 ;
  bool tmp___53 ;
  int tmp___54 ;
  bool tmp___55 ;
  int tmp___56 ;
  unsigned char *__cil_tmp66 ;
  unsigned char *__cil_tmp67 ;
  unsigned char __cil_tmp68 ;
  unsigned int __cil_tmp69 ;
  u8 __cil_tmp70 ;
  void *__cil_tmp71 ;
  u8 __cil_tmp72 ;
  void *__cil_tmp73 ;
  int __cil_tmp74 ;
  int __cil_tmp75 ;
  int __cil_tmp76 ;
  struct drm_property *__cil_tmp77 ;
  unsigned long __cil_tmp78 ;
  struct drm_property *__cil_tmp79 ;
  unsigned long __cil_tmp80 ;
  struct drm_property *__cil_tmp81 ;
  uint64_t *__cil_tmp82 ;
  struct drm_property *__cil_tmp83 ;
  uint64_t *__cil_tmp84 ;
  uint64_t *__cil_tmp85 ;
  struct drm_property *__cil_tmp86 ;
  u32 __cil_tmp87 ;
  uint64_t __cil_tmp88 ;
  struct drm_property *__cil_tmp89 ;
  unsigned long __cil_tmp90 ;
  struct drm_property *__cil_tmp91 ;
  unsigned long __cil_tmp92 ;
  struct drm_property *__cil_tmp93 ;
  uint64_t *__cil_tmp94 ;
  struct drm_property *__cil_tmp95 ;
  uint64_t *__cil_tmp96 ;
  uint64_t *__cil_tmp97 ;
  struct drm_property *__cil_tmp98 ;
  u32 __cil_tmp99 ;
  uint64_t __cil_tmp100 ;
  int __cil_tmp101 ;
  int __cil_tmp102 ;
  int __cil_tmp103 ;
  unsigned char *__cil_tmp104 ;
  unsigned char *__cil_tmp105 ;
  unsigned char __cil_tmp106 ;
  unsigned int __cil_tmp107 ;
  u8 __cil_tmp108 ;
  void *__cil_tmp109 ;
  u8 __cil_tmp110 ;
  void *__cil_tmp111 ;
  int __cil_tmp112 ;
  int __cil_tmp113 ;
  int __cil_tmp114 ;
  struct drm_property *__cil_tmp115 ;
  unsigned long __cil_tmp116 ;
  struct drm_property *__cil_tmp117 ;
  unsigned long __cil_tmp118 ;
  struct drm_property *__cil_tmp119 ;
  uint64_t *__cil_tmp120 ;
  struct drm_property *__cil_tmp121 ;
  uint64_t *__cil_tmp122 ;
  uint64_t *__cil_tmp123 ;
  struct drm_property *__cil_tmp124 ;
  u32 __cil_tmp125 ;
  uint64_t __cil_tmp126 ;
  struct drm_property *__cil_tmp127 ;
  unsigned long __cil_tmp128 ;
  struct drm_property *__cil_tmp129 ;
  unsigned long __cil_tmp130 ;
  struct drm_property *__cil_tmp131 ;
  uint64_t *__cil_tmp132 ;
  struct drm_property *__cil_tmp133 ;
  uint64_t *__cil_tmp134 ;
  uint64_t *__cil_tmp135 ;
  struct drm_property *__cil_tmp136 ;
  u32 __cil_tmp137 ;
  uint64_t __cil_tmp138 ;
  int __cil_tmp139 ;
  int __cil_tmp140 ;
  int __cil_tmp141 ;
  unsigned char *__cil_tmp142 ;
  unsigned char *__cil_tmp143 ;
  unsigned char __cil_tmp144 ;
  unsigned int __cil_tmp145 ;
  u8 __cil_tmp146 ;
  void *__cil_tmp147 ;
  u8 __cil_tmp148 ;
  void *__cil_tmp149 ;
  struct drm_property *__cil_tmp150 ;
  unsigned long __cil_tmp151 ;
  struct drm_property *__cil_tmp152 ;
  unsigned long __cil_tmp153 ;
  struct drm_property *__cil_tmp154 ;
  uint64_t *__cil_tmp155 ;
  struct drm_property *__cil_tmp156 ;
  uint64_t *__cil_tmp157 ;
  uint64_t *__cil_tmp158 ;
  struct drm_property *__cil_tmp159 ;
  u32 __cil_tmp160 ;
  uint64_t __cil_tmp161 ;
  int __cil_tmp162 ;
  int __cil_tmp163 ;
  int __cil_tmp164 ;
  unsigned char *__cil_tmp165 ;
  unsigned char *__cil_tmp166 ;
  unsigned char __cil_tmp167 ;
  unsigned int __cil_tmp168 ;
  u8 __cil_tmp169 ;
  void *__cil_tmp170 ;
  u8 __cil_tmp171 ;
  void *__cil_tmp172 ;
  struct drm_property *__cil_tmp173 ;
  unsigned long __cil_tmp174 ;
  struct drm_property *__cil_tmp175 ;
  unsigned long __cil_tmp176 ;
  struct drm_property *__cil_tmp177 ;
  uint64_t *__cil_tmp178 ;
  struct drm_property *__cil_tmp179 ;
  uint64_t *__cil_tmp180 ;
  uint64_t *__cil_tmp181 ;
  struct drm_property *__cil_tmp182 ;
  u32 __cil_tmp183 ;
  uint64_t __cil_tmp184 ;
  int __cil_tmp185 ;
  int __cil_tmp186 ;
  int __cil_tmp187 ;
  unsigned char *__cil_tmp188 ;
  unsigned char *__cil_tmp189 ;
  unsigned char __cil_tmp190 ;
  unsigned int __cil_tmp191 ;
  u8 __cil_tmp192 ;
  void *__cil_tmp193 ;
  u8 __cil_tmp194 ;
  void *__cil_tmp195 ;
  struct drm_property *__cil_tmp196 ;
  unsigned long __cil_tmp197 ;
  struct drm_property *__cil_tmp198 ;
  unsigned long __cil_tmp199 ;
  struct drm_property *__cil_tmp200 ;
  uint64_t *__cil_tmp201 ;
  struct drm_property *__cil_tmp202 ;
  uint64_t *__cil_tmp203 ;
  uint64_t *__cil_tmp204 ;
  struct drm_property *__cil_tmp205 ;
  u32 __cil_tmp206 ;
  uint64_t __cil_tmp207 ;
  int __cil_tmp208 ;
  int __cil_tmp209 ;
  int __cil_tmp210 ;
  unsigned char *__cil_tmp211 ;
  unsigned char *__cil_tmp212 ;
  unsigned char __cil_tmp213 ;
  unsigned int __cil_tmp214 ;
  u8 __cil_tmp215 ;
  void *__cil_tmp216 ;
  u8 __cil_tmp217 ;
  void *__cil_tmp218 ;
  struct drm_property *__cil_tmp219 ;
  unsigned long __cil_tmp220 ;
  struct drm_property *__cil_tmp221 ;
  unsigned long __cil_tmp222 ;
  struct drm_property *__cil_tmp223 ;
  uint64_t *__cil_tmp224 ;
  struct drm_property *__cil_tmp225 ;
  uint64_t *__cil_tmp226 ;
  uint64_t *__cil_tmp227 ;
  struct drm_property *__cil_tmp228 ;
  u32 __cil_tmp229 ;
  uint64_t __cil_tmp230 ;
  int __cil_tmp231 ;
  int __cil_tmp232 ;
  int __cil_tmp233 ;
  unsigned char *__cil_tmp234 ;
  unsigned char *__cil_tmp235 ;
  unsigned char __cil_tmp236 ;
  unsigned int __cil_tmp237 ;
  u8 __cil_tmp238 ;
  void *__cil_tmp239 ;
  u8 __cil_tmp240 ;
  void *__cil_tmp241 ;
  struct drm_property *__cil_tmp242 ;
  unsigned long __cil_tmp243 ;
  struct drm_property *__cil_tmp244 ;
  unsigned long __cil_tmp245 ;
  struct drm_property *__cil_tmp246 ;
  uint64_t *__cil_tmp247 ;
  struct drm_property *__cil_tmp248 ;
  uint64_t *__cil_tmp249 ;
  uint64_t *__cil_tmp250 ;
  struct drm_property *__cil_tmp251 ;
  u32 __cil_tmp252 ;
  uint64_t __cil_tmp253 ;
  int __cil_tmp254 ;
  int __cil_tmp255 ;
  int __cil_tmp256 ;
  unsigned char *__cil_tmp257 ;
  unsigned char *__cil_tmp258 ;
  unsigned char __cil_tmp259 ;
  unsigned int __cil_tmp260 ;
  u8 __cil_tmp261 ;
  void *__cil_tmp262 ;
  u8 __cil_tmp263 ;
  void *__cil_tmp264 ;
  struct drm_property *__cil_tmp265 ;
  unsigned long __cil_tmp266 ;
  struct drm_property *__cil_tmp267 ;
  unsigned long __cil_tmp268 ;
  struct drm_property *__cil_tmp269 ;
  uint64_t *__cil_tmp270 ;
  struct drm_property *__cil_tmp271 ;
  uint64_t *__cil_tmp272 ;
  uint64_t *__cil_tmp273 ;
  struct drm_property *__cil_tmp274 ;
  u32 __cil_tmp275 ;
  uint64_t __cil_tmp276 ;
  int __cil_tmp277 ;
  int __cil_tmp278 ;
  int __cil_tmp279 ;
  unsigned char *__cil_tmp280 ;
  unsigned char *__cil_tmp281 ;
  unsigned char __cil_tmp282 ;
  unsigned int __cil_tmp283 ;
  u8 __cil_tmp284 ;
  void *__cil_tmp285 ;
  u8 __cil_tmp286 ;
  void *__cil_tmp287 ;
  struct drm_property *__cil_tmp288 ;
  unsigned long __cil_tmp289 ;
  struct drm_property *__cil_tmp290 ;
  unsigned long __cil_tmp291 ;
  struct drm_property *__cil_tmp292 ;
  uint64_t *__cil_tmp293 ;
  struct drm_property *__cil_tmp294 ;
  uint64_t *__cil_tmp295 ;
  uint64_t *__cil_tmp296 ;
  struct drm_property *__cil_tmp297 ;
  u32 __cil_tmp298 ;
  uint64_t __cil_tmp299 ;
  int __cil_tmp300 ;
  int __cil_tmp301 ;
  int __cil_tmp302 ;
  unsigned char *__cil_tmp303 ;
  unsigned char *__cil_tmp304 ;
  unsigned char __cil_tmp305 ;
  unsigned int __cil_tmp306 ;
  u8 __cil_tmp307 ;
  void *__cil_tmp308 ;
  u8 __cil_tmp309 ;
  void *__cil_tmp310 ;
  struct drm_property *__cil_tmp311 ;
  unsigned long __cil_tmp312 ;
  struct drm_property *__cil_tmp313 ;
  unsigned long __cil_tmp314 ;
  struct drm_property *__cil_tmp315 ;
  uint64_t *__cil_tmp316 ;
  struct drm_property *__cil_tmp317 ;
  uint64_t *__cil_tmp318 ;
  uint64_t *__cil_tmp319 ;
  struct drm_property *__cil_tmp320 ;
  u32 __cil_tmp321 ;
  uint64_t __cil_tmp322 ;
  int __cil_tmp323 ;
  int __cil_tmp324 ;
  int __cil_tmp325 ;
  unsigned char *__cil_tmp326 ;
  unsigned char *__cil_tmp327 ;
  unsigned char __cil_tmp328 ;
  unsigned int __cil_tmp329 ;
  u8 __cil_tmp330 ;
  void *__cil_tmp331 ;
  u8 __cil_tmp332 ;
  void *__cil_tmp333 ;
  struct drm_property *__cil_tmp334 ;
  unsigned long __cil_tmp335 ;
  struct drm_property *__cil_tmp336 ;
  unsigned long __cil_tmp337 ;
  struct drm_property *__cil_tmp338 ;
  uint64_t *__cil_tmp339 ;
  struct drm_property *__cil_tmp340 ;
  uint64_t *__cil_tmp341 ;
  uint64_t *__cil_tmp342 ;
  struct drm_property *__cil_tmp343 ;
  u32 __cil_tmp344 ;
  uint64_t __cil_tmp345 ;
  int __cil_tmp346 ;
  int __cil_tmp347 ;
  int __cil_tmp348 ;
  unsigned char *__cil_tmp349 ;
  unsigned char *__cil_tmp350 ;
  unsigned char __cil_tmp351 ;
  unsigned int __cil_tmp352 ;
  u8 __cil_tmp353 ;
  void *__cil_tmp354 ;
  u8 __cil_tmp355 ;
  void *__cil_tmp356 ;
  struct drm_property *__cil_tmp357 ;
  unsigned long __cil_tmp358 ;
  struct drm_property *__cil_tmp359 ;
  unsigned long __cil_tmp360 ;
  struct drm_property *__cil_tmp361 ;
  uint64_t *__cil_tmp362 ;
  struct drm_property *__cil_tmp363 ;
  uint64_t *__cil_tmp364 ;
  uint64_t *__cil_tmp365 ;
  struct drm_property *__cil_tmp366 ;
  u32 __cil_tmp367 ;
  uint64_t __cil_tmp368 ;
  int __cil_tmp369 ;
  int __cil_tmp370 ;
  int __cil_tmp371 ;
  unsigned char *__cil_tmp372 ;
  unsigned char *__cil_tmp373 ;
  unsigned char __cil_tmp374 ;
  unsigned int __cil_tmp375 ;
  u8 __cil_tmp376 ;
  void *__cil_tmp377 ;
  u8 __cil_tmp378 ;
  void *__cil_tmp379 ;
  struct drm_property *__cil_tmp380 ;
  unsigned long __cil_tmp381 ;
  struct drm_property *__cil_tmp382 ;
  unsigned long __cil_tmp383 ;
  struct drm_property *__cil_tmp384 ;
  uint64_t *__cil_tmp385 ;
  struct drm_property *__cil_tmp386 ;
  uint64_t *__cil_tmp387 ;
  uint64_t *__cil_tmp388 ;
  struct drm_property *__cil_tmp389 ;
  u32 __cil_tmp390 ;
  uint64_t __cil_tmp391 ;
  int __cil_tmp392 ;
  int __cil_tmp393 ;
  int __cil_tmp394 ;
  unsigned char *__cil_tmp395 ;
  unsigned char *__cil_tmp396 ;
  unsigned char __cil_tmp397 ;
  unsigned int __cil_tmp398 ;
  u8 __cil_tmp399 ;
  void *__cil_tmp400 ;
  u8 __cil_tmp401 ;
  void *__cil_tmp402 ;
  struct drm_property *__cil_tmp403 ;
  unsigned long __cil_tmp404 ;
  struct drm_property *__cil_tmp405 ;
  unsigned long __cil_tmp406 ;
  struct drm_property *__cil_tmp407 ;
  uint64_t *__cil_tmp408 ;
  struct drm_property *__cil_tmp409 ;
  uint64_t *__cil_tmp410 ;
  uint64_t *__cil_tmp411 ;
  struct drm_property *__cil_tmp412 ;
  u32 __cil_tmp413 ;
  uint64_t __cil_tmp414 ;
  int __cil_tmp415 ;
  int __cil_tmp416 ;
  int __cil_tmp417 ;
  unsigned char *__cil_tmp418 ;
  unsigned char *__cil_tmp419 ;
  unsigned char __cil_tmp420 ;
  unsigned int __cil_tmp421 ;
  u8 __cil_tmp422 ;
  void *__cil_tmp423 ;
  u32 __cil_tmp424 ;
  struct drm_property *__cil_tmp425 ;
  unsigned long __cil_tmp426 ;
  struct drm_property *__cil_tmp427 ;
  unsigned long __cil_tmp428 ;
  struct drm_property *__cil_tmp429 ;
  uint64_t *__cil_tmp430 ;
  struct drm_property *__cil_tmp431 ;
  uint64_t *__cil_tmp432 ;
  uint64_t *__cil_tmp433 ;
  struct drm_property *__cil_tmp434 ;
  u32 __cil_tmp435 ;
  uint64_t __cil_tmp436 ;
  int __cil_tmp437 ;

  {
#line 2331
  dev = intel_sdvo->base.base.dev;
#line 2332
  connector = & intel_sdvo_connector->base.base;
  {
#line 2336
  __cil_tmp66 = (unsigned char *)(& enhancements);
#line 2336
  __cil_tmp67 = __cil_tmp66 + 0UL;
#line 2336
  __cil_tmp68 = *__cil_tmp67;
#line 2336
  __cil_tmp69 = (unsigned int )__cil_tmp68;
#line 2336
  if (__cil_tmp69 != 0U) {
    {
#line 2337
    __cil_tmp70 = (u8 )97;
#line 2337
    __cil_tmp71 = (void *)(& data_value);
#line 2337
    tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp70, __cil_tmp71, 4);
    }
#line 2337
    if (tmp) {
#line 2337
      tmp___0 = 0;
    } else {
#line 2337
      tmp___0 = 1;
    }
#line 2337
    if (tmp___0) {
#line 2340
      return ((bool )0);
    } else {

    }
    {
#line 2342
    __cil_tmp72 = (u8 )98;
#line 2342
    __cil_tmp73 = (void *)(& response);
#line 2342
    tmp___1 = intel_sdvo_get_value(intel_sdvo, __cil_tmp72, __cil_tmp73, 2);
    }
#line 2342
    if (tmp___1) {
#line 2342
      tmp___2 = 0;
    } else {
#line 2342
      tmp___2 = 1;
    }
#line 2342
    if (tmp___2) {
#line 2345
      return ((bool )0);
    } else {

    }
    {
#line 2347
    intel_sdvo_connector->max_hscan = (u32 )data_value[0];
#line 2348
    __cil_tmp74 = (int )response;
#line 2348
    __cil_tmp75 = (int )data_value[0];
#line 2348
    __cil_tmp76 = __cil_tmp75 - __cil_tmp74;
#line 2348
    intel_sdvo_connector->left_margin = (u32 )__cil_tmp76;
#line 2349
    intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
#line 2350
    intel_sdvo_connector->left = drm_property_create(dev, 2, "left_margin", 2);
    }
    {
#line 2353
    __cil_tmp77 = (struct drm_property *)0;
#line 2353
    __cil_tmp78 = (unsigned long )__cil_tmp77;
#line 2353
    __cil_tmp79 = intel_sdvo_connector->left;
#line 2353
    __cil_tmp80 = (unsigned long )__cil_tmp79;
#line 2353
    if (__cil_tmp80 == __cil_tmp78) {
#line 2354
      return ((bool )0);
    } else {

    }
    }
    {
#line 2356
    __cil_tmp81 = intel_sdvo_connector->left;
#line 2356
    __cil_tmp82 = __cil_tmp81->values;
#line 2356
    *__cil_tmp82 = 0ULL;
#line 2357
    __cil_tmp83 = intel_sdvo_connector->left;
#line 2357
    __cil_tmp84 = __cil_tmp83->values;
#line 2357
    __cil_tmp85 = __cil_tmp84 + 1UL;
#line 2357
    *__cil_tmp85 = (uint64_t )data_value[0];
#line 2358
    __cil_tmp86 = intel_sdvo_connector->left;
#line 2358
    __cil_tmp87 = intel_sdvo_connector->left_margin;
#line 2358
    __cil_tmp88 = (uint64_t )__cil_tmp87;
#line 2358
    drm_connector_attach_property(connector, __cil_tmp86, __cil_tmp88);
#line 2362
    intel_sdvo_connector->right = drm_property_create(dev, 2, "right_margin", 2);
    }
    {
#line 2365
    __cil_tmp89 = (struct drm_property *)0;
#line 2365
    __cil_tmp90 = (unsigned long )__cil_tmp89;
#line 2365
    __cil_tmp91 = intel_sdvo_connector->right;
#line 2365
    __cil_tmp92 = (unsigned long )__cil_tmp91;
#line 2365
    if (__cil_tmp92 == __cil_tmp90) {
#line 2366
      return ((bool )0);
    } else {

    }
    }
    {
#line 2368
    __cil_tmp93 = intel_sdvo_connector->right;
#line 2368
    __cil_tmp94 = __cil_tmp93->values;
#line 2368
    *__cil_tmp94 = 0ULL;
#line 2369
    __cil_tmp95 = intel_sdvo_connector->right;
#line 2369
    __cil_tmp96 = __cil_tmp95->values;
#line 2369
    __cil_tmp97 = __cil_tmp96 + 1UL;
#line 2369
    *__cil_tmp97 = (uint64_t )data_value[0];
#line 2370
    __cil_tmp98 = intel_sdvo_connector->right;
#line 2370
    __cil_tmp99 = intel_sdvo_connector->right_margin;
#line 2370
    __cil_tmp100 = (uint64_t )__cil_tmp99;
#line 2370
    drm_connector_attach_property(connector, __cil_tmp98, __cil_tmp100);
#line 2373
    __cil_tmp101 = (int )data_value[0];
#line 2373
    __cil_tmp102 = (int )data_value[1];
#line 2373
    __cil_tmp103 = (int )response;
#line 2373
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "h_overscan: max %d, default %d, current %d\n",
                        __cil_tmp101, __cil_tmp102, __cil_tmp103);
    }
  } else {

  }
  }
  {
#line 2378
  __cil_tmp104 = (unsigned char *)(& enhancements);
#line 2378
  __cil_tmp105 = __cil_tmp104 + 1UL;
#line 2378
  __cil_tmp106 = *__cil_tmp105;
#line 2378
  __cil_tmp107 = (unsigned int )__cil_tmp106;
#line 2378
  if (__cil_tmp107 != 0U) {
    {
#line 2379
    __cil_tmp108 = (u8 )100;
#line 2379
    __cil_tmp109 = (void *)(& data_value);
#line 2379
    tmp___3 = intel_sdvo_get_value(intel_sdvo, __cil_tmp108, __cil_tmp109, 4);
    }
#line 2379
    if (tmp___3) {
#line 2379
      tmp___4 = 0;
    } else {
#line 2379
      tmp___4 = 1;
    }
#line 2379
    if (tmp___4) {
#line 2382
      return ((bool )0);
    } else {

    }
    {
#line 2384
    __cil_tmp110 = (u8 )101;
#line 2384
    __cil_tmp111 = (void *)(& response);
#line 2384
    tmp___5 = intel_sdvo_get_value(intel_sdvo, __cil_tmp110, __cil_tmp111, 2);
    }
#line 2384
    if (tmp___5) {
#line 2384
      tmp___6 = 0;
    } else {
#line 2384
      tmp___6 = 1;
    }
#line 2384
    if (tmp___6) {
#line 2387
      return ((bool )0);
    } else {

    }
    {
#line 2389
    intel_sdvo_connector->max_vscan = (u32 )data_value[0];
#line 2390
    __cil_tmp112 = (int )response;
#line 2390
    __cil_tmp113 = (int )data_value[0];
#line 2390
    __cil_tmp114 = __cil_tmp113 - __cil_tmp112;
#line 2390
    intel_sdvo_connector->top_margin = (u32 )__cil_tmp114;
#line 2391
    intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
#line 2392
    intel_sdvo_connector->top = drm_property_create(dev, 2, "top_margin", 2);
    }
    {
#line 2395
    __cil_tmp115 = (struct drm_property *)0;
#line 2395
    __cil_tmp116 = (unsigned long )__cil_tmp115;
#line 2395
    __cil_tmp117 = intel_sdvo_connector->top;
#line 2395
    __cil_tmp118 = (unsigned long )__cil_tmp117;
#line 2395
    if (__cil_tmp118 == __cil_tmp116) {
#line 2396
      return ((bool )0);
    } else {

    }
    }
    {
#line 2398
    __cil_tmp119 = intel_sdvo_connector->top;
#line 2398
    __cil_tmp120 = __cil_tmp119->values;
#line 2398
    *__cil_tmp120 = 0ULL;
#line 2399
    __cil_tmp121 = intel_sdvo_connector->top;
#line 2399
    __cil_tmp122 = __cil_tmp121->values;
#line 2399
    __cil_tmp123 = __cil_tmp122 + 1UL;
#line 2399
    *__cil_tmp123 = (uint64_t )data_value[0];
#line 2400
    __cil_tmp124 = intel_sdvo_connector->top;
#line 2400
    __cil_tmp125 = intel_sdvo_connector->top_margin;
#line 2400
    __cil_tmp126 = (uint64_t )__cil_tmp125;
#line 2400
    drm_connector_attach_property(connector, __cil_tmp124, __cil_tmp126);
#line 2404
    intel_sdvo_connector->bottom = drm_property_create(dev, 2, "bottom_margin", 2);
    }
    {
#line 2407
    __cil_tmp127 = (struct drm_property *)0;
#line 2407
    __cil_tmp128 = (unsigned long )__cil_tmp127;
#line 2407
    __cil_tmp129 = intel_sdvo_connector->bottom;
#line 2407
    __cil_tmp130 = (unsigned long )__cil_tmp129;
#line 2407
    if (__cil_tmp130 == __cil_tmp128) {
#line 2408
      return ((bool )0);
    } else {

    }
    }
    {
#line 2410
    __cil_tmp131 = intel_sdvo_connector->bottom;
#line 2410
    __cil_tmp132 = __cil_tmp131->values;
#line 2410
    *__cil_tmp132 = 0ULL;
#line 2411
    __cil_tmp133 = intel_sdvo_connector->bottom;
#line 2411
    __cil_tmp134 = __cil_tmp133->values;
#line 2411
    __cil_tmp135 = __cil_tmp134 + 1UL;
#line 2411
    *__cil_tmp135 = (uint64_t )data_value[0];
#line 2412
    __cil_tmp136 = intel_sdvo_connector->bottom;
#line 2412
    __cil_tmp137 = intel_sdvo_connector->bottom_margin;
#line 2412
    __cil_tmp138 = (uint64_t )__cil_tmp137;
#line 2412
    drm_connector_attach_property(connector, __cil_tmp136, __cil_tmp138);
#line 2415
    __cil_tmp139 = (int )data_value[0];
#line 2415
    __cil_tmp140 = (int )data_value[1];
#line 2415
    __cil_tmp141 = (int )response;
#line 2415
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "v_overscan: max %d, default %d, current %d\n",
                        __cil_tmp139, __cil_tmp140, __cil_tmp141);
    }
  } else {

  }
  }
  {
#line 2420
  __cil_tmp142 = (unsigned char *)(& enhancements);
#line 2420
  __cil_tmp143 = __cil_tmp142 + 1UL;
#line 2420
  __cil_tmp144 = *__cil_tmp143;
#line 2420
  __cil_tmp145 = (unsigned int )__cil_tmp144;
#line 2420
  if (__cil_tmp145 != 0U) {
    {
#line 2420
    __cil_tmp146 = (u8 )103;
#line 2420
    __cil_tmp147 = (void *)(& data_value);
#line 2420
    tmp___7 = intel_sdvo_get_value(intel_sdvo, __cil_tmp146, __cil_tmp147, 4);
    }
#line 2420
    if (tmp___7) {
#line 2420
      tmp___8 = 0;
    } else {
#line 2420
      tmp___8 = 1;
    }
#line 2420
    if (tmp___8) {
#line 2420
      return ((bool )0);
    } else {
      {
#line 2420
      __cil_tmp148 = (u8 )104;
#line 2420
      __cil_tmp149 = (void *)(& response);
#line 2420
      tmp___9 = intel_sdvo_get_value(intel_sdvo, __cil_tmp148, __cil_tmp149, 2);
      }
#line 2420
      if (tmp___9) {
#line 2420
        tmp___10 = 0;
      } else {
#line 2420
        tmp___10 = 1;
      }
#line 2420
      if (tmp___10) {
#line 2420
        return ((bool )0);
      } else {

      }
    }
    {
#line 2420
    intel_sdvo_connector->max_hpos = (u32 )data_value[0];
#line 2420
    intel_sdvo_connector->cur_hpos = (u32 )response;
#line 2420
    intel_sdvo_connector->hpos = drm_property_create(dev, 2, "hpos", 2);
    }
    {
#line 2420
    __cil_tmp150 = (struct drm_property *)0;
#line 2420
    __cil_tmp151 = (unsigned long )__cil_tmp150;
#line 2420
    __cil_tmp152 = intel_sdvo_connector->hpos;
#line 2420
    __cil_tmp153 = (unsigned long )__cil_tmp152;
#line 2420
    if (__cil_tmp153 == __cil_tmp151) {
#line 2420
      return ((bool )0);
    } else {

    }
    }
    {
#line 2420
    __cil_tmp154 = intel_sdvo_connector->hpos;
#line 2420
    __cil_tmp155 = __cil_tmp154->values;
#line 2420
    *__cil_tmp155 = 0ULL;
#line 2420
    __cil_tmp156 = intel_sdvo_connector->hpos;
#line 2420
    __cil_tmp157 = __cil_tmp156->values;
#line 2420
    __cil_tmp158 = __cil_tmp157 + 1UL;
#line 2420
    *__cil_tmp158 = (uint64_t )data_value[0];
#line 2420
    __cil_tmp159 = intel_sdvo_connector->hpos;
#line 2420
    __cil_tmp160 = intel_sdvo_connector->cur_hpos;
#line 2420
    __cil_tmp161 = (uint64_t )__cil_tmp160;
#line 2420
    drm_connector_attach_property(connector, __cil_tmp159, __cil_tmp161);
#line 2420
    __cil_tmp162 = (int )data_value[0];
#line 2420
    __cil_tmp163 = (int )data_value[1];
#line 2420
    __cil_tmp164 = (int )response;
#line 2420
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "hpos: max %d, default %d, current %d\n",
                        __cil_tmp162, __cil_tmp163, __cil_tmp164);
    }
  } else {

  }
  }
  {
#line 2421
  __cil_tmp165 = (unsigned char *)(& enhancements);
#line 2421
  __cil_tmp166 = __cil_tmp165 + 1UL;
#line 2421
  __cil_tmp167 = *__cil_tmp166;
#line 2421
  __cil_tmp168 = (unsigned int )__cil_tmp167;
#line 2421
  if (__cil_tmp168 != 0U) {
    {
#line 2421
    __cil_tmp169 = (u8 )106;
#line 2421
    __cil_tmp170 = (void *)(& data_value);
#line 2421
    tmp___11 = intel_sdvo_get_value(intel_sdvo, __cil_tmp169, __cil_tmp170, 4);
    }
#line 2421
    if (tmp___11) {
#line 2421
      tmp___12 = 0;
    } else {
#line 2421
      tmp___12 = 1;
    }
#line 2421
    if (tmp___12) {
#line 2421
      return ((bool )0);
    } else {
      {
#line 2421
      __cil_tmp171 = (u8 )107;
#line 2421
      __cil_tmp172 = (void *)(& response);
#line 2421
      tmp___13 = intel_sdvo_get_value(intel_sdvo, __cil_tmp171, __cil_tmp172, 2);
      }
#line 2421
      if (tmp___13) {
#line 2421
        tmp___14 = 0;
      } else {
#line 2421
        tmp___14 = 1;
      }
#line 2421
      if (tmp___14) {
#line 2421
        return ((bool )0);
      } else {

      }
    }
    {
#line 2421
    intel_sdvo_connector->max_vpos = (u32 )data_value[0];
#line 2421
    intel_sdvo_connector->cur_vpos = (u32 )response;
#line 2421
    intel_sdvo_connector->vpos = drm_property_create(dev, 2, "vpos", 2);
    }
    {
#line 2421
    __cil_tmp173 = (struct drm_property *)0;
#line 2421
    __cil_tmp174 = (unsigned long )__cil_tmp173;
#line 2421
    __cil_tmp175 = intel_sdvo_connector->vpos;
#line 2421
    __cil_tmp176 = (unsigned long )__cil_tmp175;
#line 2421
    if (__cil_tmp176 == __cil_tmp174) {
#line 2421
      return ((bool )0);
    } else {

    }
    }
    {
#line 2421
    __cil_tmp177 = intel_sdvo_connector->vpos;
#line 2421
    __cil_tmp178 = __cil_tmp177->values;
#line 2421
    *__cil_tmp178 = 0ULL;
#line 2421
    __cil_tmp179 = intel_sdvo_connector->vpos;
#line 2421
    __cil_tmp180 = __cil_tmp179->values;
#line 2421
    __cil_tmp181 = __cil_tmp180 + 1UL;
#line 2421
    *__cil_tmp181 = (uint64_t )data_value[0];
#line 2421
    __cil_tmp182 = intel_sdvo_connector->vpos;
#line 2421
    __cil_tmp183 = intel_sdvo_connector->cur_vpos;
#line 2421
    __cil_tmp184 = (uint64_t )__cil_tmp183;
#line 2421
    drm_connector_attach_property(connector, __cil_tmp182, __cil_tmp184);
#line 2421
    __cil_tmp185 = (int )data_value[0];
#line 2421
    __cil_tmp186 = (int )data_value[1];
#line 2421
    __cil_tmp187 = (int )response;
#line 2421
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "vpos: max %d, default %d, current %d\n",
                        __cil_tmp185, __cil_tmp186, __cil_tmp187);
    }
  } else {

  }
  }
  {
#line 2422
  __cil_tmp188 = (unsigned char *)(& enhancements);
#line 2422
  __cil_tmp189 = __cil_tmp188 + 0UL;
#line 2422
  __cil_tmp190 = *__cil_tmp189;
#line 2422
  __cil_tmp191 = (unsigned int )__cil_tmp190;
#line 2422
  if (__cil_tmp191 != 0U) {
    {
#line 2422
    __cil_tmp192 = (u8 )85;
#line 2422
    __cil_tmp193 = (void *)(& data_value);
#line 2422
    tmp___15 = intel_sdvo_get_value(intel_sdvo, __cil_tmp192, __cil_tmp193, 4);
    }
#line 2422
    if (tmp___15) {
#line 2422
      tmp___16 = 0;
    } else {
#line 2422
      tmp___16 = 1;
    }
#line 2422
    if (tmp___16) {
#line 2422
      return ((bool )0);
    } else {
      {
#line 2422
      __cil_tmp194 = (u8 )86;
#line 2422
      __cil_tmp195 = (void *)(& response);
#line 2422
      tmp___17 = intel_sdvo_get_value(intel_sdvo, __cil_tmp194, __cil_tmp195, 2);
      }
#line 2422
      if (tmp___17) {
#line 2422
        tmp___18 = 0;
      } else {
#line 2422
        tmp___18 = 1;
      }
#line 2422
      if (tmp___18) {
#line 2422
        return ((bool )0);
      } else {

      }
    }
    {
#line 2422
    intel_sdvo_connector->max_saturation = (u32 )data_value[0];
#line 2422
    intel_sdvo_connector->cur_saturation = (u32 )response;
#line 2422
    intel_sdvo_connector->saturation = drm_property_create(dev, 2, "saturation", 2);
    }
    {
#line 2422
    __cil_tmp196 = (struct drm_property *)0;
#line 2422
    __cil_tmp197 = (unsigned long )__cil_tmp196;
#line 2422
    __cil_tmp198 = intel_sdvo_connector->saturation;
#line 2422
    __cil_tmp199 = (unsigned long )__cil_tmp198;
#line 2422
    if (__cil_tmp199 == __cil_tmp197) {
#line 2422
      return ((bool )0);
    } else {

    }
    }
    {
#line 2422
    __cil_tmp200 = intel_sdvo_connector->saturation;
#line 2422
    __cil_tmp201 = __cil_tmp200->values;
#line 2422
    *__cil_tmp201 = 0ULL;
#line 2422
    __cil_tmp202 = intel_sdvo_connector->saturation;
#line 2422
    __cil_tmp203 = __cil_tmp202->values;
#line 2422
    __cil_tmp204 = __cil_tmp203 + 1UL;
#line 2422
    *__cil_tmp204 = (uint64_t )data_value[0];
#line 2422
    __cil_tmp205 = intel_sdvo_connector->saturation;
#line 2422
    __cil_tmp206 = intel_sdvo_connector->cur_saturation;
#line 2422
    __cil_tmp207 = (uint64_t )__cil_tmp206;
#line 2422
    drm_connector_attach_property(connector, __cil_tmp205, __cil_tmp207);
#line 2422
    __cil_tmp208 = (int )data_value[0];
#line 2422
    __cil_tmp209 = (int )data_value[1];
#line 2422
    __cil_tmp210 = (int )response;
#line 2422
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "saturation: max %d, default %d, current %d\n",
                        __cil_tmp208, __cil_tmp209, __cil_tmp210);
    }
  } else {

  }
  }
  {
#line 2423
  __cil_tmp211 = (unsigned char *)(& enhancements);
#line 2423
  __cil_tmp212 = __cil_tmp211 + 0UL;
#line 2423
  __cil_tmp213 = *__cil_tmp212;
#line 2423
  __cil_tmp214 = (unsigned int )__cil_tmp213;
#line 2423
  if (__cil_tmp214 != 0U) {
    {
#line 2423
    __cil_tmp215 = (u8 )94;
#line 2423
    __cil_tmp216 = (void *)(& data_value);
#line 2423
    tmp___19 = intel_sdvo_get_value(intel_sdvo, __cil_tmp215, __cil_tmp216, 4);
    }
#line 2423
    if (tmp___19) {
#line 2423
      tmp___20 = 0;
    } else {
#line 2423
      tmp___20 = 1;
    }
#line 2423
    if (tmp___20) {
#line 2423
      return ((bool )0);
    } else {
      {
#line 2423
      __cil_tmp217 = (u8 )95;
#line 2423
      __cil_tmp218 = (void *)(& response);
#line 2423
      tmp___21 = intel_sdvo_get_value(intel_sdvo, __cil_tmp217, __cil_tmp218, 2);
      }
#line 2423
      if (tmp___21) {
#line 2423
        tmp___22 = 0;
      } else {
#line 2423
        tmp___22 = 1;
      }
#line 2423
      if (tmp___22) {
#line 2423
        return ((bool )0);
      } else {

      }
    }
    {
#line 2423
    intel_sdvo_connector->max_contrast = (u32 )data_value[0];
#line 2423
    intel_sdvo_connector->cur_contrast = (u32 )response;
#line 2423
    intel_sdvo_connector->contrast = drm_property_create(dev, 2, "contrast", 2);
    }
    {
#line 2423
    __cil_tmp219 = (struct drm_property *)0;
#line 2423
    __cil_tmp220 = (unsigned long )__cil_tmp219;
#line 2423
    __cil_tmp221 = intel_sdvo_connector->contrast;
#line 2423
    __cil_tmp222 = (unsigned long )__cil_tmp221;
#line 2423
    if (__cil_tmp222 == __cil_tmp220) {
#line 2423
      return ((bool )0);
    } else {

    }
    }
    {
#line 2423
    __cil_tmp223 = intel_sdvo_connector->contrast;
#line 2423
    __cil_tmp224 = __cil_tmp223->values;
#line 2423
    *__cil_tmp224 = 0ULL;
#line 2423
    __cil_tmp225 = intel_sdvo_connector->contrast;
#line 2423
    __cil_tmp226 = __cil_tmp225->values;
#line 2423
    __cil_tmp227 = __cil_tmp226 + 1UL;
#line 2423
    *__cil_tmp227 = (uint64_t )data_value[0];
#line 2423
    __cil_tmp228 = intel_sdvo_connector->contrast;
#line 2423
    __cil_tmp229 = intel_sdvo_connector->cur_contrast;
#line 2423
    __cil_tmp230 = (uint64_t )__cil_tmp229;
#line 2423
    drm_connector_attach_property(connector, __cil_tmp228, __cil_tmp230);
#line 2423
    __cil_tmp231 = (int )data_value[0];
#line 2423
    __cil_tmp232 = (int )data_value[1];
#line 2423
    __cil_tmp233 = (int )response;
#line 2423
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "contrast: max %d, default %d, current %d\n",
                        __cil_tmp231, __cil_tmp232, __cil_tmp233);
    }
  } else {

  }
  }
  {
#line 2424
  __cil_tmp234 = (unsigned char *)(& enhancements);
#line 2424
  __cil_tmp235 = __cil_tmp234 + 0UL;
#line 2424
  __cil_tmp236 = *__cil_tmp235;
#line 2424
  __cil_tmp237 = (unsigned int )__cil_tmp236;
#line 2424
  if (__cil_tmp237 != 0U) {
    {
#line 2424
    __cil_tmp238 = (u8 )88;
#line 2424
    __cil_tmp239 = (void *)(& data_value);
#line 2424
    tmp___23 = intel_sdvo_get_value(intel_sdvo, __cil_tmp238, __cil_tmp239, 4);
    }
#line 2424
    if (tmp___23) {
#line 2424
      tmp___24 = 0;
    } else {
#line 2424
      tmp___24 = 1;
    }
#line 2424
    if (tmp___24) {
#line 2424
      return ((bool )0);
    } else {
      {
#line 2424
      __cil_tmp240 = (u8 )89;
#line 2424
      __cil_tmp241 = (void *)(& response);
#line 2424
      tmp___25 = intel_sdvo_get_value(intel_sdvo, __cil_tmp240, __cil_tmp241, 2);
      }
#line 2424
      if (tmp___25) {
#line 2424
        tmp___26 = 0;
      } else {
#line 2424
        tmp___26 = 1;
      }
#line 2424
      if (tmp___26) {
#line 2424
        return ((bool )0);
      } else {

      }
    }
    {
#line 2424
    intel_sdvo_connector->max_hue = (u32 )data_value[0];
#line 2424
    intel_sdvo_connector->cur_hue = (u32 )response;
#line 2424
    intel_sdvo_connector->hue = drm_property_create(dev, 2, "hue", 2);
    }
    {
#line 2424
    __cil_tmp242 = (struct drm_property *)0;
#line 2424
    __cil_tmp243 = (unsigned long )__cil_tmp242;
#line 2424
    __cil_tmp244 = intel_sdvo_connector->hue;
#line 2424
    __cil_tmp245 = (unsigned long )__cil_tmp244;
#line 2424
    if (__cil_tmp245 == __cil_tmp243) {
#line 2424
      return ((bool )0);
    } else {

    }
    }
    {
#line 2424
    __cil_tmp246 = intel_sdvo_connector->hue;
#line 2424
    __cil_tmp247 = __cil_tmp246->values;
#line 2424
    *__cil_tmp247 = 0ULL;
#line 2424
    __cil_tmp248 = intel_sdvo_connector->hue;
#line 2424
    __cil_tmp249 = __cil_tmp248->values;
#line 2424
    __cil_tmp250 = __cil_tmp249 + 1UL;
#line 2424
    *__cil_tmp250 = (uint64_t )data_value[0];
#line 2424
    __cil_tmp251 = intel_sdvo_connector->hue;
#line 2424
    __cil_tmp252 = intel_sdvo_connector->cur_hue;
#line 2424
    __cil_tmp253 = (uint64_t )__cil_tmp252;
#line 2424
    drm_connector_attach_property(connector, __cil_tmp251, __cil_tmp253);
#line 2424
    __cil_tmp254 = (int )data_value[0];
#line 2424
    __cil_tmp255 = (int )data_value[1];
#line 2424
    __cil_tmp256 = (int )response;
#line 2424
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "hue: max %d, default %d, current %d\n",
                        __cil_tmp254, __cil_tmp255, __cil_tmp256);
    }
  } else {

  }
  }
  {
#line 2425
  __cil_tmp257 = (unsigned char *)(& enhancements);
#line 2425
  __cil_tmp258 = __cil_tmp257 + 1UL;
#line 2425
  __cil_tmp259 = *__cil_tmp258;
#line 2425
  __cil_tmp260 = (unsigned int )__cil_tmp259;
#line 2425
  if (__cil_tmp260 != 0U) {
    {
#line 2425
    __cil_tmp261 = (u8 )109;
#line 2425
    __cil_tmp262 = (void *)(& data_value);
#line 2425
    tmp___27 = intel_sdvo_get_value(intel_sdvo, __cil_tmp261, __cil_tmp262, 4);
    }
#line 2425
    if (tmp___27) {
#line 2425
      tmp___28 = 0;
    } else {
#line 2425
      tmp___28 = 1;
    }
#line 2425
    if (tmp___28) {
#line 2425
      return ((bool )0);
    } else {
      {
#line 2425
      __cil_tmp263 = (u8 )110;
#line 2425
      __cil_tmp264 = (void *)(& response);
#line 2425
      tmp___29 = intel_sdvo_get_value(intel_sdvo, __cil_tmp263, __cil_tmp264, 2);
      }
#line 2425
      if (tmp___29) {
#line 2425
        tmp___30 = 0;
      } else {
#line 2425
        tmp___30 = 1;
      }
#line 2425
      if (tmp___30) {
#line 2425
        return ((bool )0);
      } else {

      }
    }
    {
#line 2425
    intel_sdvo_connector->max_sharpness = (u32 )data_value[0];
#line 2425
    intel_sdvo_connector->cur_sharpness = (u32 )response;
#line 2425
    intel_sdvo_connector->sharpness = drm_property_create(dev, 2, "sharpness", 2);
    }
    {
#line 2425
    __cil_tmp265 = (struct drm_property *)0;
#line 2425
    __cil_tmp266 = (unsigned long )__cil_tmp265;
#line 2425
    __cil_tmp267 = intel_sdvo_connector->sharpness;
#line 2425
    __cil_tmp268 = (unsigned long )__cil_tmp267;
#line 2425
    if (__cil_tmp268 == __cil_tmp266) {
#line 2425
      return ((bool )0);
    } else {

    }
    }
    {
#line 2425
    __cil_tmp269 = intel_sdvo_connector->sharpness;
#line 2425
    __cil_tmp270 = __cil_tmp269->values;
#line 2425
    *__cil_tmp270 = 0ULL;
#line 2425
    __cil_tmp271 = intel_sdvo_connector->sharpness;
#line 2425
    __cil_tmp272 = __cil_tmp271->values;
#line 2425
    __cil_tmp273 = __cil_tmp272 + 1UL;
#line 2425
    *__cil_tmp273 = (uint64_t )data_value[0];
#line 2425
    __cil_tmp274 = intel_sdvo_connector->sharpness;
#line 2425
    __cil_tmp275 = intel_sdvo_connector->cur_sharpness;
#line 2425
    __cil_tmp276 = (uint64_t )__cil_tmp275;
#line 2425
    drm_connector_attach_property(connector, __cil_tmp274, __cil_tmp276);
#line 2425
    __cil_tmp277 = (int )data_value[0];
#line 2425
    __cil_tmp278 = (int )data_value[1];
#line 2425
    __cil_tmp279 = (int )response;
#line 2425
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "sharpness: max %d, default %d, current %d\n",
                        __cil_tmp277, __cil_tmp278, __cil_tmp279);
    }
  } else {

  }
  }
  {
#line 2426
  __cil_tmp280 = (unsigned char *)(& enhancements);
#line 2426
  __cil_tmp281 = __cil_tmp280 + 0UL;
#line 2426
  __cil_tmp282 = *__cil_tmp281;
#line 2426
  __cil_tmp283 = (unsigned int )__cil_tmp282;
#line 2426
  if (__cil_tmp283 != 0U) {
    {
#line 2426
    __cil_tmp284 = (u8 )91;
#line 2426
    __cil_tmp285 = (void *)(& data_value);
#line 2426
    tmp___31 = intel_sdvo_get_value(intel_sdvo, __cil_tmp284, __cil_tmp285, 4);
    }
#line 2426
    if (tmp___31) {
#line 2426
      tmp___32 = 0;
    } else {
#line 2426
      tmp___32 = 1;
    }
#line 2426
    if (tmp___32) {
#line 2426
      return ((bool )0);
    } else {
      {
#line 2426
      __cil_tmp286 = (u8 )92;
#line 2426
      __cil_tmp287 = (void *)(& response);
#line 2426
      tmp___33 = intel_sdvo_get_value(intel_sdvo, __cil_tmp286, __cil_tmp287, 2);
      }
#line 2426
      if (tmp___33) {
#line 2426
        tmp___34 = 0;
      } else {
#line 2426
        tmp___34 = 1;
      }
#line 2426
      if (tmp___34) {
#line 2426
        return ((bool )0);
      } else {

      }
    }
    {
#line 2426
    intel_sdvo_connector->max_brightness = (u32 )data_value[0];
#line 2426
    intel_sdvo_connector->cur_brightness = (u32 )response;
#line 2426
    intel_sdvo_connector->brightness = drm_property_create(dev, 2, "brightness", 2);
    }
    {
#line 2426
    __cil_tmp288 = (struct drm_property *)0;
#line 2426
    __cil_tmp289 = (unsigned long )__cil_tmp288;
#line 2426
    __cil_tmp290 = intel_sdvo_connector->brightness;
#line 2426
    __cil_tmp291 = (unsigned long )__cil_tmp290;
#line 2426
    if (__cil_tmp291 == __cil_tmp289) {
#line 2426
      return ((bool )0);
    } else {

    }
    }
    {
#line 2426
    __cil_tmp292 = intel_sdvo_connector->brightness;
#line 2426
    __cil_tmp293 = __cil_tmp292->values;
#line 2426
    *__cil_tmp293 = 0ULL;
#line 2426
    __cil_tmp294 = intel_sdvo_connector->brightness;
#line 2426
    __cil_tmp295 = __cil_tmp294->values;
#line 2426
    __cil_tmp296 = __cil_tmp295 + 1UL;
#line 2426
    *__cil_tmp296 = (uint64_t )data_value[0];
#line 2426
    __cil_tmp297 = intel_sdvo_connector->brightness;
#line 2426
    __cil_tmp298 = intel_sdvo_connector->cur_brightness;
#line 2426
    __cil_tmp299 = (uint64_t )__cil_tmp298;
#line 2426
    drm_connector_attach_property(connector, __cil_tmp297, __cil_tmp299);
#line 2426
    __cil_tmp300 = (int )data_value[0];
#line 2426
    __cil_tmp301 = (int )data_value[1];
#line 2426
    __cil_tmp302 = (int )response;
#line 2426
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "brightness: max %d, default %d, current %d\n",
                        __cil_tmp300, __cil_tmp301, __cil_tmp302);
    }
  } else {

  }
  }
  {
#line 2427
  __cil_tmp303 = (unsigned char *)(& enhancements);
#line 2427
  __cil_tmp304 = __cil_tmp303 + 0UL;
#line 2427
  __cil_tmp305 = *__cil_tmp304;
#line 2427
  __cil_tmp306 = (unsigned int )__cil_tmp305;
#line 2427
  if (__cil_tmp306 != 0U) {
    {
#line 2427
    __cil_tmp307 = (u8 )77;
#line 2427
    __cil_tmp308 = (void *)(& data_value);
#line 2427
    tmp___35 = intel_sdvo_get_value(intel_sdvo, __cil_tmp307, __cil_tmp308, 4);
    }
#line 2427
    if (tmp___35) {
#line 2427
      tmp___36 = 0;
    } else {
#line 2427
      tmp___36 = 1;
    }
#line 2427
    if (tmp___36) {
#line 2427
      return ((bool )0);
    } else {
      {
#line 2427
      __cil_tmp309 = (u8 )78;
#line 2427
      __cil_tmp310 = (void *)(& response);
#line 2427
      tmp___37 = intel_sdvo_get_value(intel_sdvo, __cil_tmp309, __cil_tmp310, 2);
      }
#line 2427
      if (tmp___37) {
#line 2427
        tmp___38 = 0;
      } else {
#line 2427
        tmp___38 = 1;
      }
#line 2427
      if (tmp___38) {
#line 2427
        return ((bool )0);
      } else {

      }
    }
    {
#line 2427
    intel_sdvo_connector->max_flicker_filter = (u32 )data_value[0];
#line 2427
    intel_sdvo_connector->cur_flicker_filter = (u32 )response;
#line 2427
    intel_sdvo_connector->flicker_filter = drm_property_create(dev, 2, "flicker_filter",
                                                               2);
    }
    {
#line 2427
    __cil_tmp311 = (struct drm_property *)0;
#line 2427
    __cil_tmp312 = (unsigned long )__cil_tmp311;
#line 2427
    __cil_tmp313 = intel_sdvo_connector->flicker_filter;
#line 2427
    __cil_tmp314 = (unsigned long )__cil_tmp313;
#line 2427
    if (__cil_tmp314 == __cil_tmp312) {
#line 2427
      return ((bool )0);
    } else {

    }
    }
    {
#line 2427
    __cil_tmp315 = intel_sdvo_connector->flicker_filter;
#line 2427
    __cil_tmp316 = __cil_tmp315->values;
#line 2427
    *__cil_tmp316 = 0ULL;
#line 2427
    __cil_tmp317 = intel_sdvo_connector->flicker_filter;
#line 2427
    __cil_tmp318 = __cil_tmp317->values;
#line 2427
    __cil_tmp319 = __cil_tmp318 + 1UL;
#line 2427
    *__cil_tmp319 = (uint64_t )data_value[0];
#line 2427
    __cil_tmp320 = intel_sdvo_connector->flicker_filter;
#line 2427
    __cil_tmp321 = intel_sdvo_connector->cur_flicker_filter;
#line 2427
    __cil_tmp322 = (uint64_t )__cil_tmp321;
#line 2427
    drm_connector_attach_property(connector, __cil_tmp320, __cil_tmp322);
#line 2427
    __cil_tmp323 = (int )data_value[0];
#line 2427
    __cil_tmp324 = (int )data_value[1];
#line 2427
    __cil_tmp325 = (int )response;
#line 2427
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "flicker_filter: max %d, default %d, current %d\n",
                        __cil_tmp323, __cil_tmp324, __cil_tmp325);
    }
  } else {

  }
  }
  {
#line 2428
  __cil_tmp326 = (unsigned char *)(& enhancements);
#line 2428
  __cil_tmp327 = __cil_tmp326 + 0UL;
#line 2428
  __cil_tmp328 = *__cil_tmp327;
#line 2428
  __cil_tmp329 = (unsigned int )__cil_tmp328;
#line 2428
  if (__cil_tmp329 != 0U) {
    {
#line 2428
    __cil_tmp330 = (u8 )123;
#line 2428
    __cil_tmp331 = (void *)(& data_value);
#line 2428
    tmp___39 = intel_sdvo_get_value(intel_sdvo, __cil_tmp330, __cil_tmp331, 4);
    }
#line 2428
    if (tmp___39) {
#line 2428
      tmp___40 = 0;
    } else {
#line 2428
      tmp___40 = 1;
    }
#line 2428
    if (tmp___40) {
#line 2428
      return ((bool )0);
    } else {
      {
#line 2428
      __cil_tmp332 = (u8 )80;
#line 2428
      __cil_tmp333 = (void *)(& response);
#line 2428
      tmp___41 = intel_sdvo_get_value(intel_sdvo, __cil_tmp332, __cil_tmp333, 2);
      }
#line 2428
      if (tmp___41) {
#line 2428
        tmp___42 = 0;
      } else {
#line 2428
        tmp___42 = 1;
      }
#line 2428
      if (tmp___42) {
#line 2428
        return ((bool )0);
      } else {

      }
    }
    {
#line 2428
    intel_sdvo_connector->max_flicker_filter_adaptive = (u32 )data_value[0];
#line 2428
    intel_sdvo_connector->cur_flicker_filter_adaptive = (u32 )response;
#line 2428
    intel_sdvo_connector->flicker_filter_adaptive = drm_property_create(dev, 2, "flicker_filter_adaptive",
                                                                        2);
    }
    {
#line 2428
    __cil_tmp334 = (struct drm_property *)0;
#line 2428
    __cil_tmp335 = (unsigned long )__cil_tmp334;
#line 2428
    __cil_tmp336 = intel_sdvo_connector->flicker_filter_adaptive;
#line 2428
    __cil_tmp337 = (unsigned long )__cil_tmp336;
#line 2428
    if (__cil_tmp337 == __cil_tmp335) {
#line 2428
      return ((bool )0);
    } else {

    }
    }
    {
#line 2428
    __cil_tmp338 = intel_sdvo_connector->flicker_filter_adaptive;
#line 2428
    __cil_tmp339 = __cil_tmp338->values;
#line 2428
    *__cil_tmp339 = 0ULL;
#line 2428
    __cil_tmp340 = intel_sdvo_connector->flicker_filter_adaptive;
#line 2428
    __cil_tmp341 = __cil_tmp340->values;
#line 2428
    __cil_tmp342 = __cil_tmp341 + 1UL;
#line 2428
    *__cil_tmp342 = (uint64_t )data_value[0];
#line 2428
    __cil_tmp343 = intel_sdvo_connector->flicker_filter_adaptive;
#line 2428
    __cil_tmp344 = intel_sdvo_connector->cur_flicker_filter_adaptive;
#line 2428
    __cil_tmp345 = (uint64_t )__cil_tmp344;
#line 2428
    drm_connector_attach_property(connector, __cil_tmp343, __cil_tmp345);
#line 2428
    __cil_tmp346 = (int )data_value[0];
#line 2428
    __cil_tmp347 = (int )data_value[1];
#line 2428
    __cil_tmp348 = (int )response;
#line 2428
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "flicker_filter_adaptive: max %d, default %d, current %d\n",
                        __cil_tmp346, __cil_tmp347, __cil_tmp348);
    }
  } else {

  }
  }
  {
#line 2429
  __cil_tmp349 = (unsigned char *)(& enhancements);
#line 2429
  __cil_tmp350 = __cil_tmp349 + 0UL;
#line 2429
  __cil_tmp351 = *__cil_tmp350;
#line 2429
  __cil_tmp352 = (unsigned int )__cil_tmp351;
#line 2429
  if (__cil_tmp352 != 0U) {
    {
#line 2429
    __cil_tmp353 = (u8 )82;
#line 2429
    __cil_tmp354 = (void *)(& data_value);
#line 2429
    tmp___43 = intel_sdvo_get_value(intel_sdvo, __cil_tmp353, __cil_tmp354, 4);
    }
#line 2429
    if (tmp___43) {
#line 2429
      tmp___44 = 0;
    } else {
#line 2429
      tmp___44 = 1;
    }
#line 2429
    if (tmp___44) {
#line 2429
      return ((bool )0);
    } else {
      {
#line 2429
      __cil_tmp355 = (u8 )83;
#line 2429
      __cil_tmp356 = (void *)(& response);
#line 2429
      tmp___45 = intel_sdvo_get_value(intel_sdvo, __cil_tmp355, __cil_tmp356, 2);
      }
#line 2429
      if (tmp___45) {
#line 2429
        tmp___46 = 0;
      } else {
#line 2429
        tmp___46 = 1;
      }
#line 2429
      if (tmp___46) {
#line 2429
        return ((bool )0);
      } else {

      }
    }
    {
#line 2429
    intel_sdvo_connector->max_flicker_filter_2d = (u32 )data_value[0];
#line 2429
    intel_sdvo_connector->cur_flicker_filter_2d = (u32 )response;
#line 2429
    intel_sdvo_connector->flicker_filter_2d = drm_property_create(dev, 2, "flicker_filter_2d",
                                                                  2);
    }
    {
#line 2429
    __cil_tmp357 = (struct drm_property *)0;
#line 2429
    __cil_tmp358 = (unsigned long )__cil_tmp357;
#line 2429
    __cil_tmp359 = intel_sdvo_connector->flicker_filter_2d;
#line 2429
    __cil_tmp360 = (unsigned long )__cil_tmp359;
#line 2429
    if (__cil_tmp360 == __cil_tmp358) {
#line 2429
      return ((bool )0);
    } else {

    }
    }
    {
#line 2429
    __cil_tmp361 = intel_sdvo_connector->flicker_filter_2d;
#line 2429
    __cil_tmp362 = __cil_tmp361->values;
#line 2429
    *__cil_tmp362 = 0ULL;
#line 2429
    __cil_tmp363 = intel_sdvo_connector->flicker_filter_2d;
#line 2429
    __cil_tmp364 = __cil_tmp363->values;
#line 2429
    __cil_tmp365 = __cil_tmp364 + 1UL;
#line 2429
    *__cil_tmp365 = (uint64_t )data_value[0];
#line 2429
    __cil_tmp366 = intel_sdvo_connector->flicker_filter_2d;
#line 2429
    __cil_tmp367 = intel_sdvo_connector->cur_flicker_filter_2d;
#line 2429
    __cil_tmp368 = (uint64_t )__cil_tmp367;
#line 2429
    drm_connector_attach_property(connector, __cil_tmp366, __cil_tmp368);
#line 2429
    __cil_tmp369 = (int )data_value[0];
#line 2429
    __cil_tmp370 = (int )data_value[1];
#line 2429
    __cil_tmp371 = (int )response;
#line 2429
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "flicker_filter_2d: max %d, default %d, current %d\n",
                        __cil_tmp369, __cil_tmp370, __cil_tmp371);
    }
  } else {

  }
  }
  {
#line 2430
  __cil_tmp372 = (unsigned char *)(& enhancements);
#line 2430
  __cil_tmp373 = __cil_tmp372 + 1UL;
#line 2430
  __cil_tmp374 = *__cil_tmp373;
#line 2430
  __cil_tmp375 = (unsigned int )__cil_tmp374;
#line 2430
  if (__cil_tmp375 != 0U) {
    {
#line 2430
    __cil_tmp376 = (u8 )116;
#line 2430
    __cil_tmp377 = (void *)(& data_value);
#line 2430
    tmp___47 = intel_sdvo_get_value(intel_sdvo, __cil_tmp376, __cil_tmp377, 4);
    }
#line 2430
    if (tmp___47) {
#line 2430
      tmp___48 = 0;
    } else {
#line 2430
      tmp___48 = 1;
    }
#line 2430
    if (tmp___48) {
#line 2430
      return ((bool )0);
    } else {
      {
#line 2430
      __cil_tmp378 = (u8 )117;
#line 2430
      __cil_tmp379 = (void *)(& response);
#line 2430
      tmp___49 = intel_sdvo_get_value(intel_sdvo, __cil_tmp378, __cil_tmp379, 2);
      }
#line 2430
      if (tmp___49) {
#line 2430
        tmp___50 = 0;
      } else {
#line 2430
        tmp___50 = 1;
      }
#line 2430
      if (tmp___50) {
#line 2430
        return ((bool )0);
      } else {

      }
    }
    {
#line 2430
    intel_sdvo_connector->max_tv_chroma_filter = (u32 )data_value[0];
#line 2430
    intel_sdvo_connector->cur_tv_chroma_filter = (u32 )response;
#line 2430
    intel_sdvo_connector->tv_chroma_filter = drm_property_create(dev, 2, "tv_chroma_filter",
                                                                 2);
    }
    {
#line 2430
    __cil_tmp380 = (struct drm_property *)0;
#line 2430
    __cil_tmp381 = (unsigned long )__cil_tmp380;
#line 2430
    __cil_tmp382 = intel_sdvo_connector->tv_chroma_filter;
#line 2430
    __cil_tmp383 = (unsigned long )__cil_tmp382;
#line 2430
    if (__cil_tmp383 == __cil_tmp381) {
#line 2430
      return ((bool )0);
    } else {

    }
    }
    {
#line 2430
    __cil_tmp384 = intel_sdvo_connector->tv_chroma_filter;
#line 2430
    __cil_tmp385 = __cil_tmp384->values;
#line 2430
    *__cil_tmp385 = 0ULL;
#line 2430
    __cil_tmp386 = intel_sdvo_connector->tv_chroma_filter;
#line 2430
    __cil_tmp387 = __cil_tmp386->values;
#line 2430
    __cil_tmp388 = __cil_tmp387 + 1UL;
#line 2430
    *__cil_tmp388 = (uint64_t )data_value[0];
#line 2430
    __cil_tmp389 = intel_sdvo_connector->tv_chroma_filter;
#line 2430
    __cil_tmp390 = intel_sdvo_connector->cur_tv_chroma_filter;
#line 2430
    __cil_tmp391 = (uint64_t )__cil_tmp390;
#line 2430
    drm_connector_attach_property(connector, __cil_tmp389, __cil_tmp391);
#line 2430
    __cil_tmp392 = (int )data_value[0];
#line 2430
    __cil_tmp393 = (int )data_value[1];
#line 2430
    __cil_tmp394 = (int )response;
#line 2430
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "tv_chroma_filter: max %d, default %d, current %d\n",
                        __cil_tmp392, __cil_tmp393, __cil_tmp394);
    }
  } else {

  }
  }
  {
#line 2431
  __cil_tmp395 = (unsigned char *)(& enhancements);
#line 2431
  __cil_tmp396 = __cil_tmp395 + 1UL;
#line 2431
  __cil_tmp397 = *__cil_tmp396;
#line 2431
  __cil_tmp398 = (unsigned int )__cil_tmp397;
#line 2431
  if (__cil_tmp398 != 0U) {
    {
#line 2431
    __cil_tmp399 = (u8 )119;
#line 2431
    __cil_tmp400 = (void *)(& data_value);
#line 2431
    tmp___51 = intel_sdvo_get_value(intel_sdvo, __cil_tmp399, __cil_tmp400, 4);
    }
#line 2431
    if (tmp___51) {
#line 2431
      tmp___52 = 0;
    } else {
#line 2431
      tmp___52 = 1;
    }
#line 2431
    if (tmp___52) {
#line 2431
      return ((bool )0);
    } else {
      {
#line 2431
      __cil_tmp401 = (u8 )120;
#line 2431
      __cil_tmp402 = (void *)(& response);
#line 2431
      tmp___53 = intel_sdvo_get_value(intel_sdvo, __cil_tmp401, __cil_tmp402, 2);
      }
#line 2431
      if (tmp___53) {
#line 2431
        tmp___54 = 0;
      } else {
#line 2431
        tmp___54 = 1;
      }
#line 2431
      if (tmp___54) {
#line 2431
        return ((bool )0);
      } else {

      }
    }
    {
#line 2431
    intel_sdvo_connector->max_tv_luma_filter = (u32 )data_value[0];
#line 2431
    intel_sdvo_connector->cur_tv_luma_filter = (u32 )response;
#line 2431
    intel_sdvo_connector->tv_luma_filter = drm_property_create(dev, 2, "tv_luma_filter",
                                                               2);
    }
    {
#line 2431
    __cil_tmp403 = (struct drm_property *)0;
#line 2431
    __cil_tmp404 = (unsigned long )__cil_tmp403;
#line 2431
    __cil_tmp405 = intel_sdvo_connector->tv_luma_filter;
#line 2431
    __cil_tmp406 = (unsigned long )__cil_tmp405;
#line 2431
    if (__cil_tmp406 == __cil_tmp404) {
#line 2431
      return ((bool )0);
    } else {

    }
    }
    {
#line 2431
    __cil_tmp407 = intel_sdvo_connector->tv_luma_filter;
#line 2431
    __cil_tmp408 = __cil_tmp407->values;
#line 2431
    *__cil_tmp408 = 0ULL;
#line 2431
    __cil_tmp409 = intel_sdvo_connector->tv_luma_filter;
#line 2431
    __cil_tmp410 = __cil_tmp409->values;
#line 2431
    __cil_tmp411 = __cil_tmp410 + 1UL;
#line 2431
    *__cil_tmp411 = (uint64_t )data_value[0];
#line 2431
    __cil_tmp412 = intel_sdvo_connector->tv_luma_filter;
#line 2431
    __cil_tmp413 = intel_sdvo_connector->cur_tv_luma_filter;
#line 2431
    __cil_tmp414 = (uint64_t )__cil_tmp413;
#line 2431
    drm_connector_attach_property(connector, __cil_tmp412, __cil_tmp414);
#line 2431
    __cil_tmp415 = (int )data_value[0];
#line 2431
    __cil_tmp416 = (int )data_value[1];
#line 2431
    __cil_tmp417 = (int )response;
#line 2431
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "tv_luma_filter: max %d, default %d, current %d\n",
                        __cil_tmp415, __cil_tmp416, __cil_tmp417);
    }
  } else {

  }
  }
  {
#line 2433
  __cil_tmp418 = (unsigned char *)(& enhancements);
#line 2433
  __cil_tmp419 = __cil_tmp418 + 1UL;
#line 2433
  __cil_tmp420 = *__cil_tmp419;
#line 2433
  __cil_tmp421 = (unsigned int )__cil_tmp420;
#line 2433
  if (__cil_tmp421 != 0U) {
    {
#line 2434
    __cil_tmp422 = (u8 )112;
#line 2434
    __cil_tmp423 = (void *)(& response);
#line 2434
    tmp___55 = intel_sdvo_get_value(intel_sdvo, __cil_tmp422, __cil_tmp423, 2);
    }
#line 2434
    if (tmp___55) {
#line 2434
      tmp___56 = 0;
    } else {
#line 2434
      tmp___56 = 1;
    }
#line 2434
    if (tmp___56) {
#line 2435
      return ((bool )0);
    } else {

    }
    {
#line 2437
    intel_sdvo_connector->max_dot_crawl = 1U;
#line 2438
    __cil_tmp424 = (u32 )response;
#line 2438
    intel_sdvo_connector->cur_dot_crawl = __cil_tmp424 & 1U;
#line 2439
    intel_sdvo_connector->dot_crawl = drm_property_create(dev, 2, "dot_crawl", 2);
    }
    {
#line 2441
    __cil_tmp425 = (struct drm_property *)0;
#line 2441
    __cil_tmp426 = (unsigned long )__cil_tmp425;
#line 2441
    __cil_tmp427 = intel_sdvo_connector->dot_crawl;
#line 2441
    __cil_tmp428 = (unsigned long )__cil_tmp427;
#line 2441
    if (__cil_tmp428 == __cil_tmp426) {
#line 2442
      return ((bool )0);
    } else {

    }
    }
    {
#line 2444
    __cil_tmp429 = intel_sdvo_connector->dot_crawl;
#line 2444
    __cil_tmp430 = __cil_tmp429->values;
#line 2444
    *__cil_tmp430 = 0ULL;
#line 2445
    __cil_tmp431 = intel_sdvo_connector->dot_crawl;
#line 2445
    __cil_tmp432 = __cil_tmp431->values;
#line 2445
    __cil_tmp433 = __cil_tmp432 + 1UL;
#line 2445
    *__cil_tmp433 = 1ULL;
#line 2446
    __cil_tmp434 = intel_sdvo_connector->dot_crawl;
#line 2446
    __cil_tmp435 = intel_sdvo_connector->cur_dot_crawl;
#line 2446
    __cil_tmp436 = (uint64_t )__cil_tmp435;
#line 2446
    drm_connector_attach_property(connector, __cil_tmp434, __cil_tmp436);
#line 2449
    __cil_tmp437 = (int )response;
#line 2449
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_tv", "dot crawl: current %d\n",
                        __cil_tmp437);
    }
  } else {

  }
  }
#line 2452
  return ((bool )1);
}
}
#line 2456 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo ,
                                                    struct intel_sdvo_connector *intel_sdvo_connector ,
                                                    struct intel_sdvo_enhancements_reply enhancements ) 
{ struct drm_device *dev ;
  struct drm_connector *connector ;
  uint16_t response ;
  uint16_t data_value[2U] ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  unsigned char *__cil_tmp12 ;
  unsigned char *__cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  u8 __cil_tmp16 ;
  void *__cil_tmp17 ;
  u8 __cil_tmp18 ;
  void *__cil_tmp19 ;
  struct drm_property *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_property *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct drm_property *__cil_tmp24 ;
  uint64_t *__cil_tmp25 ;
  struct drm_property *__cil_tmp26 ;
  uint64_t *__cil_tmp27 ;
  uint64_t *__cil_tmp28 ;
  struct drm_property *__cil_tmp29 ;
  u32 __cil_tmp30 ;
  uint64_t __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;

  {
#line 2460
  dev = intel_sdvo->base.base.dev;
#line 2461
  connector = & intel_sdvo_connector->base.base;
  {
#line 2464
  __cil_tmp12 = (unsigned char *)(& enhancements);
#line 2464
  __cil_tmp13 = __cil_tmp12 + 0UL;
#line 2464
  __cil_tmp14 = *__cil_tmp13;
#line 2464
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 2464
  if (__cil_tmp15 != 0U) {
    {
#line 2464
    __cil_tmp16 = (u8 )91;
#line 2464
    __cil_tmp17 = (void *)(& data_value);
#line 2464
    tmp = intel_sdvo_get_value(intel_sdvo, __cil_tmp16, __cil_tmp17, 4);
    }
#line 2464
    if (tmp) {
#line 2464
      tmp___0 = 0;
    } else {
#line 2464
      tmp___0 = 1;
    }
#line 2464
    if (tmp___0) {
#line 2464
      return ((bool )0);
    } else {
      {
#line 2464
      __cil_tmp18 = (u8 )92;
#line 2464
      __cil_tmp19 = (void *)(& response);
#line 2464
      tmp___1 = intel_sdvo_get_value(intel_sdvo, __cil_tmp18, __cil_tmp19, 2);
      }
#line 2464
      if (tmp___1) {
#line 2464
        tmp___2 = 0;
      } else {
#line 2464
        tmp___2 = 1;
      }
#line 2464
      if (tmp___2) {
#line 2464
        return ((bool )0);
      } else {

      }
    }
    {
#line 2464
    intel_sdvo_connector->max_brightness = (u32 )data_value[0];
#line 2464
    intel_sdvo_connector->cur_brightness = (u32 )response;
#line 2464
    intel_sdvo_connector->brightness = drm_property_create(dev, 2, "brightness", 2);
    }
    {
#line 2464
    __cil_tmp20 = (struct drm_property *)0;
#line 2464
    __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 2464
    __cil_tmp22 = intel_sdvo_connector->brightness;
#line 2464
    __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 2464
    if (__cil_tmp23 == __cil_tmp21) {
#line 2464
      return ((bool )0);
    } else {

    }
    }
    {
#line 2464
    __cil_tmp24 = intel_sdvo_connector->brightness;
#line 2464
    __cil_tmp25 = __cil_tmp24->values;
#line 2464
    *__cil_tmp25 = 0ULL;
#line 2464
    __cil_tmp26 = intel_sdvo_connector->brightness;
#line 2464
    __cil_tmp27 = __cil_tmp26->values;
#line 2464
    __cil_tmp28 = __cil_tmp27 + 1UL;
#line 2464
    *__cil_tmp28 = (uint64_t )data_value[0];
#line 2464
    __cil_tmp29 = intel_sdvo_connector->brightness;
#line 2464
    __cil_tmp30 = intel_sdvo_connector->cur_brightness;
#line 2464
    __cil_tmp31 = (uint64_t )__cil_tmp30;
#line 2464
    drm_connector_attach_property(connector, __cil_tmp29, __cil_tmp31);
#line 2464
    __cil_tmp32 = (int )data_value[0];
#line 2464
    __cil_tmp33 = (int )data_value[1];
#line 2464
    __cil_tmp34 = (int )response;
#line 2464
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property_lvds", "brightness: max %d, default %d, current %d\n",
                        __cil_tmp32, __cil_tmp33, __cil_tmp34);
    }
  } else {

  }
  }
#line 2466
  return ((bool )1);
}
}
#line 2470 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo , struct intel_sdvo_connector *intel_sdvo_connector ) 
{ union __anonunion_enhancements_197 enhancements ;
  bool tmp ;
  bool tmp___0 ;
  u8 __cil_tmp6 ;
  void *__cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  uint16_t __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  uint16_t __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 2480
  enhancements.response = (uint16_t )0U;
#line 2481
  __cil_tmp6 = (u8 )132;
#line 2481
  __cil_tmp7 = (void *)(& enhancements);
#line 2481
  intel_sdvo_get_value(intel_sdvo, __cil_tmp6, __cil_tmp7, 2);
  }
  {
#line 2484
  __cil_tmp8 = (unsigned int )enhancements.response;
#line 2484
  if (__cil_tmp8 == 0U) {
    {
#line 2485
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_create_enhance_property", "No enhancement is supported\n");
    }
#line 2486
    return ((bool )1);
  } else {

  }
  }
  {
#line 2489
  __cil_tmp9 = intel_sdvo_connector->output_flag;
#line 2489
  __cil_tmp10 = (int )__cil_tmp9;
#line 2489
  __cil_tmp11 = __cil_tmp10 & 12;
#line 2489
  if (__cil_tmp11 != 0) {
    {
#line 2490
    tmp = intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector,
                                                enhancements.reply);
    }
#line 2490
    return (tmp);
  } else {
    {
#line 2491
    __cil_tmp12 = intel_sdvo_connector->output_flag;
#line 2491
    __cil_tmp13 = (int )__cil_tmp12;
#line 2491
    __cil_tmp14 = __cil_tmp13 & 16448;
#line 2491
    if (__cil_tmp14 != 0) {
      {
#line 2492
      tmp___0 = intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector,
                                                        enhancements.reply);
      }
#line 2492
      return (tmp___0);
    } else {
#line 2494
      return ((bool )1);
    }
    }
  }
  }
}
}
#line 2497 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter , struct i2c_msg *msgs ,
                                     int num ) 
{ struct intel_sdvo *sdvo ;
  bool tmp ;
  int tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp8 ;
  uint8_t __cil_tmp9 ;
  int __cil_tmp10 ;
  u8 __cil_tmp11 ;
  struct i2c_adapter *__cil_tmp12 ;
  struct i2c_algorithm  const  *__cil_tmp13 ;
  int (*__cil_tmp14)(struct i2c_adapter * , struct i2c_msg * , int  ) ;
  struct i2c_adapter *__cil_tmp15 ;

  {
  {
#line 2501
  __cil_tmp8 = adapter->algo_data;
#line 2501
  sdvo = (struct intel_sdvo *)__cil_tmp8;
#line 2503
  __cil_tmp9 = sdvo->ddc_bus;
#line 2503
  __cil_tmp10 = (int )__cil_tmp9;
#line 2503
  __cil_tmp11 = (u8 )__cil_tmp10;
#line 2503
  tmp = intel_sdvo_set_control_bus_switch(sdvo, __cil_tmp11);
  }
#line 2503
  if (tmp) {
#line 2503
    tmp___0 = 0;
  } else {
#line 2503
    tmp___0 = 1;
  }
#line 2503
  if (tmp___0) {
#line 2504
    return (-5);
  } else {

  }
  {
#line 2506
  __cil_tmp12 = sdvo->i2c;
#line 2506
  __cil_tmp13 = __cil_tmp12->algo;
#line 2506
  __cil_tmp14 = __cil_tmp13->master_xfer;
#line 2506
  __cil_tmp15 = sdvo->i2c;
#line 2506
  tmp___1 = (*__cil_tmp14)(__cil_tmp15, msgs, num);
  }
#line 2506
  return (tmp___1);
}
}
#line 2509 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter ) 
{ struct intel_sdvo *sdvo ;
  u32 tmp ;
  void *__cil_tmp4 ;
  struct i2c_adapter *__cil_tmp5 ;
  struct i2c_algorithm  const  *__cil_tmp6 ;
  u32 (*__cil_tmp7)(struct i2c_adapter * ) ;
  struct i2c_adapter *__cil_tmp8 ;

  {
  {
#line 2511
  __cil_tmp4 = adapter->algo_data;
#line 2511
  sdvo = (struct intel_sdvo *)__cil_tmp4;
#line 2512
  __cil_tmp5 = sdvo->i2c;
#line 2512
  __cil_tmp6 = __cil_tmp5->algo;
#line 2512
  __cil_tmp7 = __cil_tmp6->functionality;
#line 2512
  __cil_tmp8 = sdvo->i2c;
#line 2512
  tmp = (*__cil_tmp7)(__cil_tmp8);
  }
#line 2512
  return (tmp);
}
}
#line 2515 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static struct i2c_algorithm  const  intel_sdvo_ddc_proxy  =    {& intel_sdvo_ddc_proxy_xfer, (int (*)(struct i2c_adapter * , u16  , unsigned short  ,
                                          char  , u8  , int  , union i2c_smbus_data * ))0,
    & intel_sdvo_ddc_proxy_func};
#line 2521 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
static bool intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo , struct drm_device *dev ) 
{ int tmp ;
  char (*__cil_tmp4)[48U] ;
  char *__cil_tmp5 ;
  struct pci_dev *__cil_tmp6 ;
  struct i2c_adapter *__cil_tmp7 ;
  int __cil_tmp8 ;

  {
  {
#line 2524
  sdvo->ddc.owner = & __this_module;
#line 2525
  sdvo->ddc.class = 8U;
#line 2526
  __cil_tmp4 = & sdvo->ddc.name;
#line 2526
  __cil_tmp5 = (char *)__cil_tmp4;
#line 2526
  snprintf(__cil_tmp5, 20UL, "SDVO DDC proxy");
#line 2527
  __cil_tmp6 = dev->pdev;
#line 2527
  sdvo->ddc.dev.parent = & __cil_tmp6->dev;
#line 2528
  sdvo->ddc.algo_data = (void *)sdvo;
#line 2529
  sdvo->ddc.algo = & intel_sdvo_ddc_proxy;
#line 2531
  __cil_tmp7 = & sdvo->ddc;
#line 2531
  tmp = i2c_add_adapter(__cil_tmp7);
  }
  {
#line 2531
  __cil_tmp8 = tmp == 0;
#line 2531
  return ((bool )__cil_tmp8);
  }
}
}
#line 2534 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_sdvo.c.p"
bool intel_sdvo_init(struct drm_device *dev , int sdvo_reg ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_encoder *intel_encoder ;
  struct intel_sdvo *intel_sdvo ;
  int i ;
  void *tmp ;
  u8 tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  u8 byte ;
  int tmp___3 ;
  bool tmp___4 ;
  int tmp___5 ;
  bool tmp___6 ;
  int tmp___7 ;
  int tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  bool tmp___11 ;
  int tmp___12 ;
  bool tmp___13 ;
  int tmp___14 ;
  int tmp___15 ;
  int tmp___16 ;
  int tmp___17 ;
  int tmp___18 ;
  char *tmp___19 ;
  void *__cil_tmp29 ;
  struct intel_sdvo *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  u32 __cil_tmp35 ;
  void const   *__cil_tmp36 ;
  struct drm_encoder *__cil_tmp37 ;
  u8 __cil_tmp38 ;
  int __cil_tmp39 ;
  u8 __cil_tmp40 ;
  u32 __cil_tmp41 ;
  u32 __cil_tmp42 ;
  u32 __cil_tmp43 ;
  struct drm_encoder *__cil_tmp44 ;
  struct intel_sdvo_caps *__cil_tmp45 ;
  u16 __cil_tmp46 ;
  int __cil_tmp47 ;
  uint16_t __cil_tmp48 ;
  u32 __cil_tmp49 ;
  int *__cil_tmp50 ;
  int *__cil_tmp51 ;
  u16 __cil_tmp52 ;
  int __cil_tmp53 ;
  int __cil_tmp54 ;
  u16 __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  unsigned char __cil_tmp58 ;
  int __cil_tmp59 ;
  int __cil_tmp60 ;
  unsigned char __cil_tmp61 ;
  int __cil_tmp62 ;
  int __cil_tmp63 ;
  int __cil_tmp64 ;
  u8 __cil_tmp65 ;
  int __cil_tmp66 ;
  u8 __cil_tmp67 ;
  int __cil_tmp68 ;
  u8 __cil_tmp69 ;
  int __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  struct drm_encoder *__cil_tmp75 ;
  struct i2c_adapter *__cil_tmp76 ;
  void const   *__cil_tmp77 ;

  {
  {
#line 2536
  __cil_tmp29 = dev->dev_private;
#line 2536
  dev_priv = (struct drm_i915_private *)__cil_tmp29;
#line 2541
  tmp = kzalloc(1832UL, 208U);
#line 2541
  intel_sdvo = (struct intel_sdvo *)tmp;
  }
  {
#line 2542
  __cil_tmp30 = (struct intel_sdvo *)0;
#line 2542
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 2542
  __cil_tmp32 = (unsigned long )intel_sdvo;
#line 2542
  if (__cil_tmp32 == __cil_tmp31) {
#line 2543
    return ((bool )0);
  } else {

  }
  }
  {
#line 2545
  intel_sdvo->sdvo_reg = sdvo_reg;
#line 2546
  tmp___0 = intel_sdvo_get_slave_addr(dev, sdvo_reg);
#line 2546
  __cil_tmp33 = (int )tmp___0;
#line 2546
  __cil_tmp34 = __cil_tmp33 >> 1;
#line 2546
  intel_sdvo->slave_addr = (u8 )__cil_tmp34;
#line 2547
  __cil_tmp35 = (u32 )sdvo_reg;
#line 2547
  intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, __cil_tmp35);
#line 2548
  tmp___1 = intel_sdvo_init_ddc_proxy(intel_sdvo, dev);
  }
#line 2548
  if (tmp___1) {
#line 2548
    tmp___2 = 0;
  } else {
#line 2548
    tmp___2 = 1;
  }
#line 2548
  if (tmp___2) {
    {
#line 2549
    __cil_tmp36 = (void const   *)intel_sdvo;
#line 2549
    kfree(__cil_tmp36);
    }
#line 2550
    return ((bool )0);
  } else {

  }
  {
#line 2554
  intel_encoder = & intel_sdvo->base;
#line 2555
  intel_encoder->type = 3;
#line 2556
  __cil_tmp37 = & intel_encoder->base;
#line 2556
  drm_encoder_init(dev, __cil_tmp37, & intel_sdvo_enc_funcs, 0);
#line 2559
  i = 0;
  }
#line 2559
  goto ldv_38594;
  ldv_38593: 
  {
#line 2562
  __cil_tmp38 = (u8 )i;
#line 2562
  __cil_tmp39 = (int )__cil_tmp38;
#line 2562
  __cil_tmp40 = (u8 )__cil_tmp39;
#line 2562
  tmp___4 = intel_sdvo_read_byte(intel_sdvo, __cil_tmp40, & byte);
  }
#line 2562
  if (tmp___4) {
#line 2562
    tmp___5 = 0;
  } else {
#line 2562
    tmp___5 = 1;
  }
#line 2562
  if (tmp___5) {
#line 2563
    if (sdvo_reg == 397632) {
#line 2563
      tmp___3 = 66;
    } else
#line 2563
    if (sdvo_reg == 921920) {
#line 2563
      tmp___3 = 66;
    } else {
#line 2563
      tmp___3 = 67;
    }
    {
#line 2563
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_init", "No SDVO device found on SDVO%c\n",
                        tmp___3);
    }
#line 2565
    goto err;
  } else {

  }
#line 2559
  i = i + 1;
  ldv_38594: ;
#line 2559
  if (i <= 63) {
#line 2560
    goto ldv_38593;
  } else {
#line 2562
    goto ldv_38595;
  }
  ldv_38595: ;
#line 2569
  if (sdvo_reg == 397632) {
#line 2570
    __cil_tmp41 = dev_priv->hotplug_supported_mask;
#line 2570
    dev_priv->hotplug_supported_mask = __cil_tmp41 | 64U;
  } else
#line 2569
  if (sdvo_reg == 921920) {
#line 2570
    __cil_tmp42 = dev_priv->hotplug_supported_mask;
#line 2570
    dev_priv->hotplug_supported_mask = __cil_tmp42 | 64U;
  } else {
#line 2572
    __cil_tmp43 = dev_priv->hotplug_supported_mask;
#line 2572
    dev_priv->hotplug_supported_mask = __cil_tmp43 | 128U;
  }
  {
#line 2574
  __cil_tmp44 = & intel_encoder->base;
#line 2574
  drm_encoder_helper_add(__cil_tmp44, & intel_sdvo_helper_funcs);
#line 2577
  __cil_tmp45 = & intel_sdvo->caps;
#line 2577
  tmp___6 = intel_sdvo_get_capabilities(intel_sdvo, __cil_tmp45);
  }
#line 2577
  if (tmp___6) {
#line 2577
    tmp___7 = 0;
  } else {
#line 2577
    tmp___7 = 1;
  }
#line 2577
  if (tmp___7) {
#line 2578
    goto err;
  } else {

  }
  {
#line 2580
  __cil_tmp46 = intel_sdvo->caps.output_flags;
#line 2580
  __cil_tmp47 = (int )__cil_tmp46;
#line 2580
  __cil_tmp48 = (uint16_t )__cil_tmp47;
#line 2580
  tmp___9 = intel_sdvo_output_setup(intel_sdvo, __cil_tmp48);
  }
#line 2580
  if (tmp___9) {
#line 2580
    tmp___10 = 0;
  } else {
#line 2580
    tmp___10 = 1;
  }
#line 2580
  if (tmp___10) {
#line 2582
    if (sdvo_reg == 397632) {
#line 2582
      tmp___8 = 66;
    } else
#line 2582
    if (sdvo_reg == 921920) {
#line 2582
      tmp___8 = 66;
    } else {
#line 2582
      tmp___8 = 67;
    }
    {
#line 2582
    drm_ut_debug_printk(4U, "drm", "intel_sdvo_init", "SDVO output failed to setup on SDVO%c\n",
                        tmp___8);
    }
#line 2584
    goto err;
  } else {

  }
  {
#line 2587
  __cil_tmp49 = (u32 )sdvo_reg;
#line 2587
  intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, __cil_tmp49);
#line 2590
  tmp___11 = intel_sdvo_set_target_input(intel_sdvo);
  }
#line 2590
  if (tmp___11) {
#line 2590
    tmp___12 = 0;
  } else {
#line 2590
    tmp___12 = 1;
  }
#line 2590
  if (tmp___12) {
#line 2591
    goto err;
  } else {

  }
  {
#line 2593
  __cil_tmp50 = & intel_sdvo->pixel_clock_min;
#line 2593
  __cil_tmp51 = & intel_sdvo->pixel_clock_max;
#line 2593
  tmp___13 = intel_sdvo_get_input_pixel_clock_range(intel_sdvo, __cil_tmp50, __cil_tmp51);
  }
#line 2593
  if (tmp___13) {
#line 2593
    tmp___14 = 0;
  } else {
#line 2593
    tmp___14 = 1;
  }
#line 2593
  if (tmp___14) {
#line 2596
    goto err;
  } else {

  }
  {
#line 2598
  __cil_tmp52 = intel_sdvo->caps.output_flags;
#line 2598
  __cil_tmp53 = (int )__cil_tmp52;
#line 2598
  __cil_tmp54 = __cil_tmp53 & 768;
#line 2598
  if (__cil_tmp54 != 0) {
#line 2598
    tmp___15 = 89;
  } else {
#line 2598
    tmp___15 = 78;
  }
  }
  {
#line 2598
  __cil_tmp55 = intel_sdvo->caps.output_flags;
#line 2598
  __cil_tmp56 = (int )__cil_tmp55;
#line 2598
  __cil_tmp57 = __cil_tmp56 & 3;
#line 2598
  if (__cil_tmp57 != 0) {
#line 2598
    tmp___16 = 89;
  } else {
#line 2598
    tmp___16 = 78;
  }
  }
  {
#line 2598
  __cil_tmp58 = intel_sdvo->caps.sdvo_inputs_mask;
#line 2598
  __cil_tmp59 = (int )__cil_tmp58;
#line 2598
  __cil_tmp60 = __cil_tmp59 & 2;
#line 2598
  if (__cil_tmp60 != 0) {
#line 2598
    tmp___17 = 89;
  } else {
#line 2598
    tmp___17 = 78;
  }
  }
  {
#line 2598
  __cil_tmp61 = intel_sdvo->caps.sdvo_inputs_mask;
#line 2598
  __cil_tmp62 = (int )__cil_tmp61;
#line 2598
  if (__cil_tmp62 & 1) {
#line 2598
    tmp___18 = 89;
  } else {
#line 2598
    tmp___18 = 78;
  }
  }
  {
#line 2598
  __cil_tmp63 = intel_sdvo->sdvo_reg;
#line 2598
  if (__cil_tmp63 == 397632) {
#line 2598
    tmp___19 = (char *)"SDVOB";
  } else {
    {
#line 2598
    __cil_tmp64 = intel_sdvo->sdvo_reg;
#line 2598
    if (__cil_tmp64 == 921920) {
#line 2598
      tmp___19 = (char *)"SDVOB";
    } else {
#line 2598
      tmp___19 = (char *)"SDVOC";
    }
    }
  }
  }
  {
#line 2598
  __cil_tmp65 = intel_sdvo->caps.vendor_id;
#line 2598
  __cil_tmp66 = (int )__cil_tmp65;
#line 2598
  __cil_tmp67 = intel_sdvo->caps.device_id;
#line 2598
  __cil_tmp68 = (int )__cil_tmp67;
#line 2598
  __cil_tmp69 = intel_sdvo->caps.device_rev_id;
#line 2598
  __cil_tmp70 = (int )__cil_tmp69;
#line 2598
  __cil_tmp71 = intel_sdvo->pixel_clock_min;
#line 2598
  __cil_tmp72 = __cil_tmp71 / 1000;
#line 2598
  __cil_tmp73 = intel_sdvo->pixel_clock_max;
#line 2598
  __cil_tmp74 = __cil_tmp73 / 1000;
#line 2598
  drm_ut_debug_printk(4U, "drm", "intel_sdvo_init", "%s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c\n",
                      tmp___19, __cil_tmp66, __cil_tmp68, __cil_tmp70, __cil_tmp72,
                      __cil_tmp74, tmp___18, tmp___17, tmp___16, tmp___15);
  }
#line 2614
  return ((bool )1);
  err: 
  {
#line 2617
  __cil_tmp75 = & intel_encoder->base;
#line 2617
  drm_encoder_cleanup(__cil_tmp75);
#line 2618
  __cil_tmp76 = & intel_sdvo->ddc;
#line 2618
  i2c_del_adapter(__cil_tmp76);
#line 2619
  __cil_tmp77 = (void const   *)intel_sdvo;
#line 2619
  kfree(__cil_tmp77);
  }
#line 2621
  return ((bool )0);
}
}
#line 44 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_modes.c.p"
bool intel_ddc_probe(struct intel_encoder *intel_encoder , int ddc_bus ) 
{ struct drm_i915_private *dev_priv ;
  u8 out_buf[2U] ;
  u8 buf[2U] ;
  struct i2c_msg msgs[2U] ;
  int tmp ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct intel_gmbus *__cil_tmp11 ;
  struct intel_gmbus *__cil_tmp12 ;
  struct i2c_adapter *__cil_tmp13 ;
  struct i2c_msg *__cil_tmp14 ;
  int __cil_tmp15 ;

  {
  {
#line 46
  __cil_tmp8 = intel_encoder->base.dev;
#line 46
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 46
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 47
  out_buf[0] = (u8 )0U;
#line 47
  out_buf[1] = (u8 )0U;
#line 49
  msgs[0].addr = (__u16 )80U;
#line 49
  msgs[0].flags = (__u16 )0U;
#line 49
  msgs[0].len = (__u16 )1U;
#line 49
  msgs[0].buf = (__u8 *)(& out_buf);
#line 49
  msgs[1].addr = (__u16 )80U;
#line 49
  msgs[1].flags = (__u16 )1U;
#line 49
  msgs[1].len = (__u16 )1U;
#line 49
  msgs[1].buf = (__u8 *)(& buf);
#line 64
  __cil_tmp10 = (unsigned long )ddc_bus;
#line 64
  __cil_tmp11 = dev_priv->gmbus;
#line 64
  __cil_tmp12 = __cil_tmp11 + __cil_tmp10;
#line 64
  __cil_tmp13 = & __cil_tmp12->adapter;
#line 64
  __cil_tmp14 = (struct i2c_msg *)(& msgs);
#line 64
  tmp = i2c_transfer(__cil_tmp13, __cil_tmp14, 2);
  }
  {
#line 64
  __cil_tmp15 = tmp == 2;
#line 64
  return ((bool )__cil_tmp15);
  }
}
}
#line 74 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_modes.c.p"
int intel_ddc_get_modes(struct drm_connector *connector , struct i2c_adapter *adapter ) 
{ struct edid *edid ;
  int ret ;
  struct edid *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  void const   *__cil_tmp8 ;

  {
  {
#line 78
  ret = 0;
#line 80
  edid = drm_get_edid(connector, adapter);
  }
  {
#line 81
  __cil_tmp5 = (struct edid *)0;
#line 81
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 81
  __cil_tmp7 = (unsigned long )edid;
#line 81
  if (__cil_tmp7 != __cil_tmp6) {
    {
#line 82
    drm_mode_connector_update_edid_property(connector, edid);
#line 83
    ret = drm_add_edid_modes(connector, edid);
#line 84
    connector->display_info.raw_edid = (char *)0;
#line 85
    __cil_tmp8 = (void const   *)edid;
#line 85
    kfree(__cil_tmp8);
    }
  } else {

  }
  }
#line 88
  return (ret);
}
}
#line 91 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_modes.c.p"
static char const   *force_audio_names[3U]  = {      "off",      "auto",      "on"};
#line 98 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_modes.c.p"
void intel_attach_force_audio_property(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct drm_property *prop ;
  int i ;
  void *__cil_tmp6 ;
  struct drm_property *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct drm_property *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  int __cil_tmp13 ;
  uint64_t __cil_tmp14 ;
  unsigned int __cil_tmp15 ;

  {
#line 100
  dev = connector->dev;
#line 101
  __cil_tmp6 = dev->dev_private;
#line 101
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 105
  prop = dev_priv->force_audio_property;
  {
#line 106
  __cil_tmp7 = (struct drm_property *)0;
#line 106
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 106
  __cil_tmp9 = (unsigned long )prop;
#line 106
  if (__cil_tmp9 == __cil_tmp8) {
    {
#line 107
    prop = drm_property_create(dev, 8, "audio", 3);
    }
    {
#line 110
    __cil_tmp10 = (struct drm_property *)0;
#line 110
    __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 110
    __cil_tmp12 = (unsigned long )prop;
#line 110
    if (__cil_tmp12 == __cil_tmp11) {
#line 111
      return;
    } else {

    }
    }
#line 113
    i = 0;
#line 113
    goto ldv_37293;
    ldv_37292: 
    {
#line 114
    __cil_tmp13 = i + -1;
#line 114
    __cil_tmp14 = (uint64_t )__cil_tmp13;
#line 114
    drm_property_add_enum(prop, i, __cil_tmp14, force_audio_names[i]);
#line 113
    i = i + 1;
    }
    ldv_37293: ;
    {
#line 113
    __cil_tmp15 = (unsigned int )i;
#line 113
    if (__cil_tmp15 <= 2U) {
#line 114
      goto ldv_37292;
    } else {
#line 116
      goto ldv_37294;
    }
    }
    ldv_37294: 
#line 116
    dev_priv->force_audio_property = prop;
  } else {

  }
  }
  {
#line 118
  drm_connector_attach_property(connector, prop, 0ULL);
  }
#line 119
  return;
}
}
#line 121 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_modes.c.p"
static char const   *broadcast_rgb_names[2U]  = {      "Full",      "Limited 16:235"};
#line 127 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_modes.c.p"
void intel_attach_broadcast_rgb_property(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct drm_property *prop ;
  int i ;
  void *__cil_tmp6 ;
  struct drm_property *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct drm_property *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  uint64_t __cil_tmp13 ;
  unsigned int __cil_tmp14 ;

  {
#line 129
  dev = connector->dev;
#line 130
  __cil_tmp6 = dev->dev_private;
#line 130
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 134
  prop = dev_priv->broadcast_rgb_property;
  {
#line 135
  __cil_tmp7 = (struct drm_property *)0;
#line 135
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 135
  __cil_tmp9 = (unsigned long )prop;
#line 135
  if (__cil_tmp9 == __cil_tmp8) {
    {
#line 136
    prop = drm_property_create(dev, 8, "Broadcast RGB", 2);
    }
    {
#line 139
    __cil_tmp10 = (struct drm_property *)0;
#line 139
    __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 139
    __cil_tmp12 = (unsigned long )prop;
#line 139
    if (__cil_tmp12 == __cil_tmp11) {
#line 140
      return;
    } else {

    }
    }
#line 142
    i = 0;
#line 142
    goto ldv_37308;
    ldv_37307: 
    {
#line 143
    __cil_tmp13 = (uint64_t )i;
#line 143
    drm_property_add_enum(prop, i, __cil_tmp13, broadcast_rgb_names[i]);
#line 142
    i = i + 1;
    }
    ldv_37308: ;
    {
#line 142
    __cil_tmp14 = (unsigned int )i;
#line 142
    if (__cil_tmp14 <= 1U) {
#line 143
      goto ldv_37307;
    } else {
#line 145
      goto ldv_37309;
    }
    }
    ldv_37309: 
#line 145
    dev_priv->broadcast_rgb_property = prop;
  } else {

  }
  }
  {
#line 148
  drm_connector_attach_property(connector, prop, 0ULL);
  }
#line 149
  return;
}
}
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___13(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36254: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36254;
      } else {
#line 390
        goto ldv_36255;
      }
      }
      ldv_36255: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___13(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___13(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___11(struct drm_i915_private *dev_priv , u32 reg ,
                                       u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___13(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 266 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/intel_drv.h"
u32 intel_panel_get_max_backlight(struct drm_device *dev ) ;
#line 267
u32 intel_panel_get_backlight(struct drm_device *dev ) ;
#line 268
void intel_panel_set_backlight(struct drm_device *dev , u32 level ) ;
#line 43 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode , struct drm_display_mode *adjusted_mode ) 
{ 

  {
  {
#line 46
  adjusted_mode->hdisplay = fixed_mode->hdisplay;
#line 47
  adjusted_mode->hsync_start = fixed_mode->hsync_start;
#line 48
  adjusted_mode->hsync_end = fixed_mode->hsync_end;
#line 49
  adjusted_mode->htotal = fixed_mode->htotal;
#line 51
  adjusted_mode->vdisplay = fixed_mode->vdisplay;
#line 52
  adjusted_mode->vsync_start = fixed_mode->vsync_start;
#line 53
  adjusted_mode->vsync_end = fixed_mode->vsync_end;
#line 54
  adjusted_mode->vtotal = fixed_mode->vtotal;
#line 56
  adjusted_mode->clock = fixed_mode->clock;
#line 58
  drm_mode_set_crtcinfo(adjusted_mode, 1);
  }
#line 59
  return;
}
}
#line 63 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
void intel_pch_panel_fitting(struct drm_device *dev , int fitting_mode , struct drm_display_mode *mode ,
                             struct drm_display_mode *adjusted_mode ) 
{ struct drm_i915_private *dev_priv ;
  int x ;
  int y ;
  int width ;
  int height ;
  u32 scaled_width ;
  u32 scaled_height ;
  void *__cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  u32 __cil_tmp30 ;
  u32 __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  u32 __cil_tmp36 ;
  u32 __cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  int __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;

  {
#line 68
  __cil_tmp12 = dev->dev_private;
#line 68
  dev_priv = (struct drm_i915_private *)__cil_tmp12;
#line 71
  height = 0;
#line 71
  width = height;
#line 71
  y = width;
#line 71
  x = y;
  {
#line 74
  __cil_tmp13 = mode->hdisplay;
#line 74
  __cil_tmp14 = adjusted_mode->hdisplay;
#line 74
  if (__cil_tmp14 == __cil_tmp13) {
    {
#line 74
    __cil_tmp15 = mode->vdisplay;
#line 74
    __cil_tmp16 = adjusted_mode->vdisplay;
#line 74
    if (__cil_tmp16 == __cil_tmp15) {
#line 76
      goto done;
    } else {

    }
    }
  } else {

  }
  }
#line 79
  if (fitting_mode == 2) {
#line 79
    goto case_2;
  } else
#line 86
  if (fitting_mode == 3) {
#line 86
    goto case_3;
  } else
#line 110
  if (fitting_mode == 1) {
#line 110
    goto case_1;
  } else {
#line 109
    goto switch_default;
#line 78
    if (0) {
      case_2: 
#line 80
      width = mode->hdisplay;
#line 81
      height = mode->vdisplay;
#line 82
      __cil_tmp17 = adjusted_mode->hdisplay;
#line 82
      __cil_tmp18 = __cil_tmp17 - width;
#line 82
      __cil_tmp19 = __cil_tmp18 + 1;
#line 82
      x = __cil_tmp19 / 2;
#line 83
      __cil_tmp20 = adjusted_mode->vdisplay;
#line 83
      __cil_tmp21 = __cil_tmp20 - height;
#line 83
      __cil_tmp22 = __cil_tmp21 + 1;
#line 83
      y = __cil_tmp22 / 2;
#line 84
      goto ldv_37283;
      case_3: 
#line 89
      __cil_tmp23 = mode->vdisplay;
#line 89
      __cil_tmp24 = adjusted_mode->hdisplay;
#line 89
      __cil_tmp25 = __cil_tmp24 * __cil_tmp23;
#line 89
      scaled_width = (u32 )__cil_tmp25;
#line 90
      __cil_tmp26 = adjusted_mode->vdisplay;
#line 90
      __cil_tmp27 = mode->hdisplay;
#line 90
      __cil_tmp28 = __cil_tmp27 * __cil_tmp26;
#line 90
      scaled_height = (u32 )__cil_tmp28;
#line 91
      if (scaled_width > scaled_height) {
#line 92
        __cil_tmp29 = mode->vdisplay;
#line 92
        __cil_tmp30 = (u32 )__cil_tmp29;
#line 92
        __cil_tmp31 = scaled_height / __cil_tmp30;
#line 92
        width = (int )__cil_tmp31;
#line 93
        __cil_tmp32 = adjusted_mode->hdisplay;
#line 93
        __cil_tmp33 = __cil_tmp32 - width;
#line 93
        __cil_tmp34 = __cil_tmp33 + 1;
#line 93
        x = __cil_tmp34 / 2;
#line 94
        y = 0;
#line 95
        height = adjusted_mode->vdisplay;
      } else
#line 96
      if (scaled_width < scaled_height) {
#line 97
        __cil_tmp35 = mode->hdisplay;
#line 97
        __cil_tmp36 = (u32 )__cil_tmp35;
#line 97
        __cil_tmp37 = scaled_width / __cil_tmp36;
#line 97
        height = (int )__cil_tmp37;
#line 98
        __cil_tmp38 = adjusted_mode->vdisplay;
#line 98
        __cil_tmp39 = __cil_tmp38 - height;
#line 98
        __cil_tmp40 = __cil_tmp39 + 1;
#line 98
        y = __cil_tmp40 / 2;
#line 99
        x = 0;
#line 100
        width = adjusted_mode->hdisplay;
      } else {
#line 102
        y = 0;
#line 102
        x = y;
#line 103
        width = adjusted_mode->hdisplay;
#line 104
        height = adjusted_mode->vdisplay;
      }
#line 107
      goto ldv_37283;
      switch_default: ;
      case_1: 
#line 111
      y = 0;
#line 111
      x = y;
#line 112
      width = adjusted_mode->hdisplay;
#line 113
      height = adjusted_mode->vdisplay;
#line 114
      goto ldv_37283;
    } else {

    }
  }
  ldv_37283: ;
  done: 
#line 118
  __cil_tmp41 = x << 16;
#line 118
  __cil_tmp42 = __cil_tmp41 | y;
#line 118
  dev_priv->pch_pf_pos = (u32 )__cil_tmp42;
#line 119
  __cil_tmp43 = width << 16;
#line 119
  __cil_tmp44 = __cil_tmp43 | height;
#line 119
  dev_priv->pch_pf_size = (u32 )__cil_tmp44;
#line 120
  return;
}
}
#line 122 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
static int is_backlight_combination_mode(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  u32 tmp___0 ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  struct drm_i915_private *__cil_tmp7 ;
  struct intel_device_info  const  *__cil_tmp8 ;
  u8 __cil_tmp9 ;
  unsigned char __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  int __cil_tmp12 ;
  void *__cil_tmp13 ;
  struct drm_i915_private *__cil_tmp14 ;
  struct intel_device_info  const  *__cil_tmp15 ;
  u8 __cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  int __cil_tmp19 ;

  {
#line 124
  __cil_tmp5 = dev->dev_private;
#line 124
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
  {
#line 126
  __cil_tmp6 = dev->dev_private;
#line 126
  __cil_tmp7 = (struct drm_i915_private *)__cil_tmp6;
#line 126
  __cil_tmp8 = __cil_tmp7->info;
#line 126
  __cil_tmp9 = __cil_tmp8->gen;
#line 126
  __cil_tmp10 = (unsigned char )__cil_tmp9;
#line 126
  __cil_tmp11 = (unsigned int )__cil_tmp10;
#line 126
  if (__cil_tmp11 > 3U) {
    {
#line 127
    tmp = i915_read32___13(dev_priv, 397904U);
    }
    {
#line 127
    __cil_tmp12 = (int )tmp;
#line 127
    return (__cil_tmp12 & 1073741824);
    }
  } else {

  }
  }
  {
#line 129
  __cil_tmp13 = dev->dev_private;
#line 129
  __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
#line 129
  __cil_tmp15 = __cil_tmp14->info;
#line 129
  __cil_tmp16 = __cil_tmp15->gen;
#line 129
  __cil_tmp17 = (unsigned char )__cil_tmp16;
#line 129
  __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 129
  if (__cil_tmp18 == 2U) {
    {
#line 130
    tmp___0 = i915_read32___13(dev_priv, 397908U);
    }
    {
#line 130
    __cil_tmp19 = (int )tmp___0;
#line 130
    return (__cil_tmp19 & 65536);
    }
  } else {

  }
  }
#line 132
  return (0);
}
}
#line 135 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv ) 
{ u32 val ;
  struct drm_device *__cil_tmp3 ;
  void *__cil_tmp4 ;
  struct drm_i915_private *__cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  struct drm_device *__cil_tmp10 ;
  void *__cil_tmp11 ;
  struct drm_i915_private *__cil_tmp12 ;
  struct intel_device_info  const  *__cil_tmp13 ;
  u8 __cil_tmp14 ;
  unsigned char __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  struct drm_device *__cil_tmp17 ;
  void *__cil_tmp18 ;
  struct drm_i915_private *__cil_tmp19 ;
  struct intel_device_info  const  *__cil_tmp20 ;
  unsigned char *__cil_tmp21 ;
  unsigned char *__cil_tmp22 ;
  unsigned char __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  u32 __cil_tmp25 ;
  u32 __cil_tmp26 ;
  u32 __cil_tmp27 ;
  u32 __cil_tmp28 ;
  u32 __cil_tmp29 ;

  {
  {
#line 141
  __cil_tmp3 = dev_priv->dev;
#line 141
  __cil_tmp4 = __cil_tmp3->dev_private;
#line 141
  __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
#line 141
  __cil_tmp6 = __cil_tmp5->info;
#line 141
  __cil_tmp7 = __cil_tmp6->gen;
#line 141
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 141
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 141
  if (__cil_tmp9 == 5U) {
#line 141
    goto _L;
  } else {
    {
#line 141
    __cil_tmp10 = dev_priv->dev;
#line 141
    __cil_tmp11 = __cil_tmp10->dev_private;
#line 141
    __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
#line 141
    __cil_tmp13 = __cil_tmp12->info;
#line 141
    __cil_tmp14 = __cil_tmp13->gen;
#line 141
    __cil_tmp15 = (unsigned char )__cil_tmp14;
#line 141
    __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 141
    if (__cil_tmp16 == 6U) {
#line 141
      goto _L;
    } else {
      {
#line 141
      __cil_tmp17 = dev_priv->dev;
#line 141
      __cil_tmp18 = __cil_tmp17->dev_private;
#line 141
      __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
#line 141
      __cil_tmp20 = __cil_tmp19->info;
#line 141
      __cil_tmp21 = (unsigned char *)__cil_tmp20;
#line 141
      __cil_tmp22 = __cil_tmp21 + 2UL;
#line 141
      __cil_tmp23 = *__cil_tmp22;
#line 141
      __cil_tmp24 = (unsigned int )__cil_tmp23;
#line 141
      if (__cil_tmp24 != 0U) {
        _L: 
        {
#line 142
        val = i915_read32___13(dev_priv, 819796U);
        }
        {
#line 143
        __cil_tmp25 = dev_priv->saveBLC_PWM_CTL2;
#line 143
        if (__cil_tmp25 == 0U) {
#line 144
          dev_priv->saveBLC_PWM_CTL2 = val;
        } else
#line 145
        if (val == 0U) {
          {
#line 146
          __cil_tmp26 = dev_priv->saveBLC_PWM_CTL;
#line 146
          i915_write32___11(dev_priv, 819796U, __cil_tmp26);
#line 148
          val = dev_priv->saveBLC_PWM_CTL;
          }
        } else {

        }
        }
      } else {
        {
#line 151
        val = i915_read32___13(dev_priv, 397908U);
        }
        {
#line 152
        __cil_tmp27 = dev_priv->saveBLC_PWM_CTL;
#line 152
        if (__cil_tmp27 == 0U) {
          {
#line 153
          dev_priv->saveBLC_PWM_CTL = val;
#line 154
          dev_priv->saveBLC_PWM_CTL2 = i915_read32___13(dev_priv, 397904U);
          }
        } else
#line 155
        if (val == 0U) {
          {
#line 156
          __cil_tmp28 = dev_priv->saveBLC_PWM_CTL;
#line 156
          i915_write32___11(dev_priv, 397908U, __cil_tmp28);
#line 158
          __cil_tmp29 = dev_priv->saveBLC_PWM_CTL2;
#line 158
          i915_write32___11(dev_priv, 397904U, __cil_tmp29);
#line 160
          val = dev_priv->saveBLC_PWM_CTL;
          }
        } else {

        }
        }
      }
      }
    }
    }
  }
  }
#line 164
  return (val);
}
}
#line 167 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
u32 intel_panel_get_max_backlight(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 max ;
  bool __print_once ;
  int tmp ;
  void *__cil_tmp6 ;
  void *__cil_tmp7 ;
  struct drm_i915_private *__cil_tmp8 ;
  struct intel_device_info  const  *__cil_tmp9 ;
  u8 __cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  void *__cil_tmp13 ;
  struct drm_i915_private *__cil_tmp14 ;
  struct intel_device_info  const  *__cil_tmp15 ;
  u8 __cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  void *__cil_tmp19 ;
  struct drm_i915_private *__cil_tmp20 ;
  struct intel_device_info  const  *__cil_tmp21 ;
  unsigned char *__cil_tmp22 ;
  unsigned char *__cil_tmp23 ;
  unsigned char __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  void *__cil_tmp26 ;
  struct drm_i915_private *__cil_tmp27 ;
  struct intel_device_info  const  *__cil_tmp28 ;
  unsigned char *__cil_tmp29 ;
  unsigned char *__cil_tmp30 ;
  unsigned char __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  void *__cil_tmp33 ;
  struct drm_i915_private *__cil_tmp34 ;
  struct intel_device_info  const  *__cil_tmp35 ;
  u8 __cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  unsigned int __cil_tmp38 ;

  {
  {
#line 169
  __cil_tmp6 = dev->dev_private;
#line 169
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 172
  max = i915_read_blc_pwm_ctl(dev_priv);
  }
#line 173
  if (max == 0U) {
#line 177
    if (! __print_once) {
      {
#line 177
      __print_once = (bool )1;
#line 177
      printk("<4>fixme: max PWM is zero.\n");
      }
    } else {

    }
#line 178
    return (1U);
  } else {

  }
  {
#line 181
  __cil_tmp7 = dev->dev_private;
#line 181
  __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
#line 181
  __cil_tmp9 = __cil_tmp8->info;
#line 181
  __cil_tmp10 = __cil_tmp9->gen;
#line 181
  __cil_tmp11 = (unsigned char )__cil_tmp10;
#line 181
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 181
  if (__cil_tmp12 == 5U) {
#line 182
    max = max >> 16;
  } else {
    {
#line 181
    __cil_tmp13 = dev->dev_private;
#line 181
    __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
#line 181
    __cil_tmp15 = __cil_tmp14->info;
#line 181
    __cil_tmp16 = __cil_tmp15->gen;
#line 181
    __cil_tmp17 = (unsigned char )__cil_tmp16;
#line 181
    __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 181
    if (__cil_tmp18 == 6U) {
#line 182
      max = max >> 16;
    } else {
      {
#line 181
      __cil_tmp19 = dev->dev_private;
#line 181
      __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
#line 181
      __cil_tmp21 = __cil_tmp20->info;
#line 181
      __cil_tmp22 = (unsigned char *)__cil_tmp21;
#line 181
      __cil_tmp23 = __cil_tmp22 + 2UL;
#line 181
      __cil_tmp24 = *__cil_tmp23;
#line 181
      __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 181
      if (__cil_tmp25 != 0U) {
#line 182
        max = max >> 16;
      } else {
        {
#line 184
        __cil_tmp26 = dev->dev_private;
#line 184
        __cil_tmp27 = (struct drm_i915_private *)__cil_tmp26;
#line 184
        __cil_tmp28 = __cil_tmp27->info;
#line 184
        __cil_tmp29 = (unsigned char *)__cil_tmp28;
#line 184
        __cil_tmp30 = __cil_tmp29 + 1UL;
#line 184
        __cil_tmp31 = *__cil_tmp30;
#line 184
        __cil_tmp32 = (unsigned int )__cil_tmp31;
#line 184
        if (__cil_tmp32 != 0U) {
#line 185
          max = max >> 17;
        } else {
#line 187
          max = max >> 16;
          {
#line 188
          __cil_tmp33 = dev->dev_private;
#line 188
          __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
#line 188
          __cil_tmp35 = __cil_tmp34->info;
#line 188
          __cil_tmp36 = __cil_tmp35->gen;
#line 188
          __cil_tmp37 = (unsigned char )__cil_tmp36;
#line 188
          __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 188
          if (__cil_tmp38 <= 3U) {
#line 189
            max = max & 4294967294U;
          } else {

          }
          }
        }
        }
        {
#line 192
        tmp = is_backlight_combination_mode(dev);
        }
#line 192
        if (tmp != 0) {
#line 193
          max = max * 255U;
        } else {

        }
      }
      }
    }
    }
  }
  }
  {
#line 196
  drm_ut_debug_printk(2U, "drm", "intel_panel_get_max_backlight", "max backlight PWM = %d\n",
                      max);
  }
#line 197
  return (max);
}
}
#line 200 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
u32 intel_panel_get_backlight(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 val ;
  u32 tmp ;
  u32 tmp___0 ;
  u8 lbpc ;
  int tmp___1 ;
  void *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  void *__cil_tmp15 ;
  struct drm_i915_private *__cil_tmp16 ;
  struct intel_device_info  const  *__cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned char __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  void *__cil_tmp21 ;
  struct drm_i915_private *__cil_tmp22 ;
  struct intel_device_info  const  *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char *__cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  void *__cil_tmp28 ;
  struct drm_i915_private *__cil_tmp29 ;
  struct intel_device_info  const  *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  struct pci_dev *__cil_tmp35 ;
  u32 __cil_tmp36 ;

  {
#line 202
  __cil_tmp8 = dev->dev_private;
#line 202
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
  {
#line 205
  __cil_tmp9 = dev->dev_private;
#line 205
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 205
  __cil_tmp11 = __cil_tmp10->info;
#line 205
  __cil_tmp12 = __cil_tmp11->gen;
#line 205
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 205
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 205
  if (__cil_tmp14 == 5U) {
    {
#line 206
    tmp = i915_read32___13(dev_priv, 295508U);
#line 206
    val = tmp & 65535U;
    }
  } else {
    {
#line 205
    __cil_tmp15 = dev->dev_private;
#line 205
    __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
#line 205
    __cil_tmp17 = __cil_tmp16->info;
#line 205
    __cil_tmp18 = __cil_tmp17->gen;
#line 205
    __cil_tmp19 = (unsigned char )__cil_tmp18;
#line 205
    __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 205
    if (__cil_tmp20 == 6U) {
      {
#line 206
      tmp = i915_read32___13(dev_priv, 295508U);
#line 206
      val = tmp & 65535U;
      }
    } else {
      {
#line 205
      __cil_tmp21 = dev->dev_private;
#line 205
      __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
#line 205
      __cil_tmp23 = __cil_tmp22->info;
#line 205
      __cil_tmp24 = (unsigned char *)__cil_tmp23;
#line 205
      __cil_tmp25 = __cil_tmp24 + 2UL;
#line 205
      __cil_tmp26 = *__cil_tmp25;
#line 205
      __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 205
      if (__cil_tmp27 != 0U) {
        {
#line 206
        tmp = i915_read32___13(dev_priv, 295508U);
#line 206
        val = tmp & 65535U;
        }
      } else {
        {
#line 208
        tmp___0 = i915_read32___13(dev_priv, 397908U);
#line 208
        val = tmp___0 & 65535U;
        }
        {
#line 209
        __cil_tmp28 = dev->dev_private;
#line 209
        __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
#line 209
        __cil_tmp30 = __cil_tmp29->info;
#line 209
        __cil_tmp31 = (unsigned char *)__cil_tmp30;
#line 209
        __cil_tmp32 = __cil_tmp31 + 1UL;
#line 209
        __cil_tmp33 = *__cil_tmp32;
#line 209
        __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 209
        if (__cil_tmp34 != 0U) {
#line 210
          val = val >> 1;
        } else {

        }
        }
        {
#line 212
        tmp___1 = is_backlight_combination_mode(dev);
        }
#line 212
        if (tmp___1 != 0) {
          {
#line 215
          val = val & 4294967294U;
#line 216
          __cil_tmp35 = dev->pdev;
#line 216
          pci_read_config_byte(__cil_tmp35, 244, & lbpc);
#line 217
          __cil_tmp36 = (u32 )lbpc;
#line 217
          val = __cil_tmp36 * val;
          }
        } else {

        }
      }
      }
    }
    }
  }
  }
  {
#line 221
  drm_ut_debug_printk(2U, "drm", "intel_panel_get_backlight", "get backlight PWM = %d\n",
                      val);
  }
#line 222
  return (val);
}
}
#line 232 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
void intel_panel_set_backlight(struct drm_device *dev , u32 level ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  u32 max ;
  u32 tmp___0 ;
  u8 lbpc ;
  int tmp___1 ;
  void *__cil_tmp9 ;
  void *__cil_tmp10 ;
  struct drm_i915_private *__cil_tmp11 ;
  struct intel_device_info  const  *__cil_tmp12 ;
  u8 __cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  u8 __cil_tmp19 ;
  unsigned char __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  void *__cil_tmp22 ;
  struct drm_i915_private *__cil_tmp23 ;
  struct intel_device_info  const  *__cil_tmp24 ;
  unsigned char *__cil_tmp25 ;
  unsigned char *__cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  u32 __cil_tmp29 ;
  u32 __cil_tmp30 ;
  u8 __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  u32 __cil_tmp34 ;
  struct pci_dev *__cil_tmp35 ;
  int __cil_tmp36 ;
  u8 __cil_tmp37 ;
  void *__cil_tmp38 ;
  struct drm_i915_private *__cil_tmp39 ;
  struct intel_device_info  const  *__cil_tmp40 ;
  unsigned char *__cil_tmp41 ;
  unsigned char *__cil_tmp42 ;
  unsigned char __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  unsigned int __cil_tmp45 ;

  {
  {
#line 234
  __cil_tmp9 = dev->dev_private;
#line 234
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 237
  drm_ut_debug_printk(2U, "drm", "intel_panel_set_backlight", "set backlight PWM = %d\n",
                      level);
  }
  {
#line 239
  __cil_tmp10 = dev->dev_private;
#line 239
  __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
#line 239
  __cil_tmp12 = __cil_tmp11->info;
#line 239
  __cil_tmp13 = __cil_tmp12->gen;
#line 239
  __cil_tmp14 = (unsigned char )__cil_tmp13;
#line 239
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 239
  if (__cil_tmp15 == 5U) {
#line 240
    return;
  } else {
    {
#line 239
    __cil_tmp16 = dev->dev_private;
#line 239
    __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 239
    __cil_tmp18 = __cil_tmp17->info;
#line 239
    __cil_tmp19 = __cil_tmp18->gen;
#line 239
    __cil_tmp20 = (unsigned char )__cil_tmp19;
#line 239
    __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 239
    if (__cil_tmp21 == 6U) {
#line 240
      return;
    } else {
      {
#line 239
      __cil_tmp22 = dev->dev_private;
#line 239
      __cil_tmp23 = (struct drm_i915_private *)__cil_tmp22;
#line 239
      __cil_tmp24 = __cil_tmp23->info;
#line 239
      __cil_tmp25 = (unsigned char *)__cil_tmp24;
#line 239
      __cil_tmp26 = __cil_tmp25 + 2UL;
#line 239
      __cil_tmp27 = *__cil_tmp26;
#line 239
      __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 239
      if (__cil_tmp28 != 0U) {
#line 240
        return;
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 242
  tmp___1 = is_backlight_combination_mode(dev);
  }
#line 242
  if (tmp___1 != 0) {
    {
#line 243
    tmp___0 = intel_panel_get_max_backlight(dev);
#line 243
    max = tmp___0;
#line 246
    __cil_tmp29 = level * 254U;
#line 246
    __cil_tmp30 = __cil_tmp29 / max;
#line 246
    __cil_tmp31 = (u8 )__cil_tmp30;
#line 246
    __cil_tmp32 = (unsigned int )__cil_tmp31;
#line 246
    __cil_tmp33 = __cil_tmp32 + 1U;
#line 246
    lbpc = (u8 )__cil_tmp33;
#line 247
    __cil_tmp34 = (u32 )lbpc;
#line 247
    level = level / __cil_tmp34;
#line 248
    __cil_tmp35 = dev->pdev;
#line 248
    __cil_tmp36 = (int )lbpc;
#line 248
    __cil_tmp37 = (u8 )__cil_tmp36;
#line 248
    pci_write_config_byte(__cil_tmp35, 244, __cil_tmp37);
    }
  } else {

  }
  {
#line 251
  tmp = i915_read32___13(dev_priv, 397908U);
  }
  {
#line 252
  __cil_tmp38 = dev->dev_private;
#line 252
  __cil_tmp39 = (struct drm_i915_private *)__cil_tmp38;
#line 252
  __cil_tmp40 = __cil_tmp39->info;
#line 252
  __cil_tmp41 = (unsigned char *)__cil_tmp40;
#line 252
  __cil_tmp42 = __cil_tmp41 + 1UL;
#line 252
  __cil_tmp43 = *__cil_tmp42;
#line 252
  __cil_tmp44 = (unsigned int )__cil_tmp43;
#line 252
  if (__cil_tmp44 != 0U) {
#line 253
    tmp = tmp & 4294901761U;
#line 254
    level = level << 1;
  } else {
#line 256
    tmp = tmp & 4294901760U;
  }
  }
  {
#line 257
  __cil_tmp45 = tmp | level;
#line 257
  i915_write32___11(dev_priv, 397908U, __cil_tmp45);
  }
#line 258
  return;
}
}
#line 260 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
void intel_panel_disable_backlight(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  void *__cil_tmp4 ;
  bool __cil_tmp5 ;

  {
#line 262
  __cil_tmp4 = dev->dev_private;
#line 262
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
  {
#line 264
  __cil_tmp5 = dev_priv->backlight_enabled;
#line 264
  if ((int )__cil_tmp5) {
    {
#line 265
    tmp = intel_panel_get_backlight(dev);
#line 265
    dev_priv->backlight_level = (int )tmp;
#line 266
    dev_priv->backlight_enabled = (bool )0;
    }
  } else {

  }
  }
  {
#line 269
  intel_panel_set_backlight(dev, 0U);
  }
#line 270
  return;
}
}
#line 272 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
void intel_panel_enable_backlight(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  void *__cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  u32 __cil_tmp7 ;

  {
#line 274
  __cil_tmp4 = dev->dev_private;
#line 274
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
  {
#line 276
  __cil_tmp5 = dev_priv->backlight_level;
#line 276
  if (__cil_tmp5 == 0) {
    {
#line 277
    tmp = intel_panel_get_max_backlight(dev);
#line 277
    dev_priv->backlight_level = (int )tmp;
    }
  } else {

  }
  }
  {
#line 279
  __cil_tmp6 = dev_priv->backlight_level;
#line 279
  __cil_tmp7 = (u32 )__cil_tmp6;
#line 279
  intel_panel_set_backlight(dev, __cil_tmp7);
#line 280
  dev_priv->backlight_enabled = (bool )1;
  }
#line 281
  return;
}
}
#line 283 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
void intel_panel_setup_backlight(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 tmp ;
  void *__cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;

  {
  {
#line 285
  __cil_tmp4 = dev->dev_private;
#line 285
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 287
  tmp = intel_panel_get_backlight(dev);
#line 287
  dev_priv->backlight_level = (int )tmp;
#line 288
  __cil_tmp5 = dev_priv->backlight_level;
#line 288
  __cil_tmp6 = __cil_tmp5 != 0;
#line 288
  dev_priv->backlight_enabled = (bool )__cil_tmp6;
  }
#line 289
  return;
}
}
#line 292 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_panel.c.p"
enum drm_connector_status intel_panel_detect(struct drm_device *dev ) 
{ int tmp ;

  {
#line 298
  if (i915_panel_ignore_lid != 0) {
#line 299
    if (i915_panel_ignore_lid > 0) {
#line 299
      tmp = 1;
    } else {
#line 299
      tmp = 2;
    }
#line 299
    return ((enum drm_connector_status )tmp);
  } else {

  }
#line 313
  return ((enum drm_connector_status )3);
}
}
#line 299 "include/linux/jiffies.h"
extern unsigned long usecs_to_jiffies(unsigned int  ) ;
#line 50 "include/linux/i2c-algo-bit.h"
extern int i2c_bit_add_bus(struct i2c_adapter * ) ;
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___14(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_36276: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_36276;
      } else {
#line 390
        goto ldv_36277;
      }
      }
      ldv_36277: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___14(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___14(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 1375 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static void i915_write32___12(struct drm_i915_private *dev_priv , u32 reg ,
                                       u32 val ) 
{ bool __cil_tmp4 ;
  u64 __cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;

  {
  {
#line 1375
  __cil_tmp4 = (bool )1;
#line 1375
  __cil_tmp5 = (u64 )val;
#line 1375
  trace_i915_reg_rw___14(__cil_tmp4, reg, __cil_tmp5, 4);
  }
  {
#line 1375
  __cil_tmp6 = dev_priv->info;
#line 1375
  __cil_tmp7 = __cil_tmp6->gen;
#line 1375
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 1375
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 1375
  if (__cil_tmp9 > 5U) {
#line 1375
    if (reg <= 262143U) {
#line 1375
      if (reg != 41356U) {
        {
#line 1375
        __gen6_gt_wait_for_fifo(dev_priv);
        }
      } else {

      }
    } else {

    }
  } else {

  }
  }
  {
#line 1375
  __cil_tmp10 = (unsigned long )reg;
#line 1375
  __cil_tmp11 = dev_priv->regs;
#line 1375
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 1375
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 1375
  writel(val, __cil_tmp13);
  }
#line 1376
  return;
}
}
#line 50 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
__inline static struct intel_gmbus *to_intel_gmbus(struct i2c_adapter *i2c ) 
{ struct i2c_adapter  const  *__mptr ;

  {
#line 52
  __mptr = (struct i2c_adapter  const  *)i2c;
#line 52
  return ((struct intel_gmbus *)__mptr);
}
}
#line 63 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
void intel_i2c_reset(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  void *__cil_tmp3 ;
  void *__cil_tmp4 ;
  struct drm_i915_private *__cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  u8 __cil_tmp7 ;
  unsigned char __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  void *__cil_tmp10 ;
  struct drm_i915_private *__cil_tmp11 ;
  struct intel_device_info  const  *__cil_tmp12 ;
  u8 __cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  unsigned char *__cil_tmp19 ;
  unsigned char *__cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;

  {
#line 65
  __cil_tmp3 = dev->dev_private;
#line 65
  dev_priv = (struct drm_i915_private *)__cil_tmp3;
  {
#line 66
  __cil_tmp4 = dev->dev_private;
#line 66
  __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
#line 66
  __cil_tmp6 = __cil_tmp5->info;
#line 66
  __cil_tmp7 = __cil_tmp6->gen;
#line 66
  __cil_tmp8 = (unsigned char )__cil_tmp7;
#line 66
  __cil_tmp9 = (unsigned int )__cil_tmp8;
#line 66
  if (__cil_tmp9 == 5U) {
    {
#line 67
    i915_write32___12(dev_priv, 807168U, 0U);
    }
  } else {
    {
#line 66
    __cil_tmp10 = dev->dev_private;
#line 66
    __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
#line 66
    __cil_tmp12 = __cil_tmp11->info;
#line 66
    __cil_tmp13 = __cil_tmp12->gen;
#line 66
    __cil_tmp14 = (unsigned char )__cil_tmp13;
#line 66
    __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 66
    if (__cil_tmp15 == 6U) {
      {
#line 67
      i915_write32___12(dev_priv, 807168U, 0U);
      }
    } else {
      {
#line 66
      __cil_tmp16 = dev->dev_private;
#line 66
      __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 66
      __cil_tmp18 = __cil_tmp17->info;
#line 66
      __cil_tmp19 = (unsigned char *)__cil_tmp18;
#line 66
      __cil_tmp20 = __cil_tmp19 + 2UL;
#line 66
      __cil_tmp21 = *__cil_tmp20;
#line 66
      __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 66
      if (__cil_tmp22 != 0U) {
        {
#line 67
        i915_write32___12(dev_priv, 807168U, 0U);
        }
      } else {
        {
#line 69
        i915_write32___12(dev_priv, 20736U, 0U);
        }
      }
      }
    }
    }
  }
  }
#line 70
  return;
}
}
#line 72 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv , bool enable ) 
{ u32 val ;
  struct drm_device *__cil_tmp4 ;
  void *__cil_tmp5 ;
  struct drm_i915_private *__cil_tmp6 ;
  struct intel_device_info  const  *__cil_tmp7 ;
  unsigned char *__cil_tmp8 ;
  unsigned char *__cil_tmp9 ;
  unsigned char __cil_tmp10 ;
  unsigned int __cil_tmp11 ;

  {
  {
#line 77
  __cil_tmp4 = dev_priv->dev;
#line 77
  __cil_tmp5 = __cil_tmp4->dev_private;
#line 77
  __cil_tmp6 = (struct drm_i915_private *)__cil_tmp5;
#line 77
  __cil_tmp7 = __cil_tmp6->info;
#line 77
  __cil_tmp8 = (unsigned char *)__cil_tmp7;
#line 77
  __cil_tmp9 = __cil_tmp8 + 1UL;
#line 77
  __cil_tmp10 = *__cil_tmp9;
#line 77
  __cil_tmp11 = (unsigned int )__cil_tmp10;
#line 77
  if (__cil_tmp11 == 0U) {
#line 78
    return;
  } else {

  }
  }
  {
#line 80
  val = i915_read32___14(dev_priv, 25088U);
  }
#line 81
  if ((int )enable) {
#line 82
    val = val | 16777216U;
  } else {
#line 84
    val = val & 4278190079U;
  }
  {
#line 85
  i915_write32___12(dev_priv, 25088U, val);
  }
#line 86
  return;
}
}
#line 88 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static u32 get_reserved(struct intel_gpio *gpio ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_device *dev ;
  u32 reserved ;
  unsigned int tmp ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  u32 __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  void *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  void const volatile   *__cil_tmp12 ;

  {
#line 90
  dev_priv = gpio->dev_priv;
#line 91
  dev = dev_priv->dev;
#line 92
  reserved = 0U;
  {
#line 95
  __cil_tmp6 = dev->pci_device;
#line 95
  if (__cil_tmp6 != 13687) {
    {
#line 95
    __cil_tmp7 = dev->pci_device;
#line 95
    if (__cil_tmp7 != 9570) {
      {
#line 96
      __cil_tmp8 = gpio->reg;
#line 96
      __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 96
      __cil_tmp10 = dev_priv->regs;
#line 96
      __cil_tmp11 = (void const volatile   *)__cil_tmp10;
#line 96
      __cil_tmp12 = __cil_tmp11 + __cil_tmp9;
#line 96
      tmp = readl(__cil_tmp12);
#line 96
      reserved = tmp & 8224U;
      }
    } else {

    }
    }
  } else {

  }
  }
#line 100
  return (reserved);
}
}
#line 103 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static int get_clock(void *data ) 
{ struct intel_gpio *gpio ;
  struct drm_i915_private *dev_priv ;
  u32 reserved ;
  u32 tmp ;
  unsigned int tmp___0 ;
  unsigned int __cil_tmp7 ;
  u32 __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  void *__cil_tmp10 ;
  void volatile   *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  u32 __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  void *__cil_tmp15 ;
  void volatile   *__cil_tmp16 ;
  void volatile   *__cil_tmp17 ;
  u32 __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  void *__cil_tmp20 ;
  void const volatile   *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  unsigned int __cil_tmp23 ;

  {
  {
#line 105
  gpio = (struct intel_gpio *)data;
#line 106
  dev_priv = gpio->dev_priv;
#line 107
  tmp = get_reserved(gpio);
#line 107
  reserved = tmp;
#line 108
  __cil_tmp7 = reserved | 1U;
#line 108
  __cil_tmp8 = gpio->reg;
#line 108
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 108
  __cil_tmp10 = dev_priv->regs;
#line 108
  __cil_tmp11 = (void volatile   *)__cil_tmp10;
#line 108
  __cil_tmp12 = __cil_tmp11 + __cil_tmp9;
#line 108
  writel(__cil_tmp7, __cil_tmp12);
#line 109
  __cil_tmp13 = gpio->reg;
#line 109
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 109
  __cil_tmp15 = dev_priv->regs;
#line 109
  __cil_tmp16 = (void volatile   *)__cil_tmp15;
#line 109
  __cil_tmp17 = __cil_tmp16 + __cil_tmp14;
#line 109
  writel(reserved, __cil_tmp17);
#line 110
  __cil_tmp18 = gpio->reg;
#line 110
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 110
  __cil_tmp20 = dev_priv->regs;
#line 110
  __cil_tmp21 = (void const volatile   *)__cil_tmp20;
#line 110
  __cil_tmp22 = __cil_tmp21 + __cil_tmp19;
#line 110
  tmp___0 = readl(__cil_tmp22);
  }
  {
#line 110
  __cil_tmp23 = tmp___0 & 16U;
#line 110
  return (__cil_tmp23 != 0U);
  }
}
}
#line 113 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static int get_data(void *data ) 
{ struct intel_gpio *gpio ;
  struct drm_i915_private *dev_priv ;
  u32 reserved ;
  u32 tmp ;
  unsigned int tmp___0 ;
  unsigned int __cil_tmp7 ;
  u32 __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  void *__cil_tmp10 ;
  void volatile   *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  u32 __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  void *__cil_tmp15 ;
  void volatile   *__cil_tmp16 ;
  void volatile   *__cil_tmp17 ;
  u32 __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  void *__cil_tmp20 ;
  void const volatile   *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  unsigned int __cil_tmp23 ;

  {
  {
#line 115
  gpio = (struct intel_gpio *)data;
#line 116
  dev_priv = gpio->dev_priv;
#line 117
  tmp = get_reserved(gpio);
#line 117
  reserved = tmp;
#line 118
  __cil_tmp7 = reserved | 256U;
#line 118
  __cil_tmp8 = gpio->reg;
#line 118
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 118
  __cil_tmp10 = dev_priv->regs;
#line 118
  __cil_tmp11 = (void volatile   *)__cil_tmp10;
#line 118
  __cil_tmp12 = __cil_tmp11 + __cil_tmp9;
#line 118
  writel(__cil_tmp7, __cil_tmp12);
#line 119
  __cil_tmp13 = gpio->reg;
#line 119
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 119
  __cil_tmp15 = dev_priv->regs;
#line 119
  __cil_tmp16 = (void volatile   *)__cil_tmp15;
#line 119
  __cil_tmp17 = __cil_tmp16 + __cil_tmp14;
#line 119
  writel(reserved, __cil_tmp17);
#line 120
  __cil_tmp18 = gpio->reg;
#line 120
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 120
  __cil_tmp20 = dev_priv->regs;
#line 120
  __cil_tmp21 = (void const volatile   *)__cil_tmp20;
#line 120
  __cil_tmp22 = __cil_tmp21 + __cil_tmp19;
#line 120
  tmp___0 = readl(__cil_tmp22);
  }
  {
#line 120
  __cil_tmp23 = tmp___0 & 4096U;
#line 120
  return (__cil_tmp23 != 0U);
  }
}
}
#line 123 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static void set_clock(void *data , int state_high ) 
{ struct intel_gpio *gpio ;
  struct drm_i915_private *dev_priv ;
  u32 reserved ;
  u32 tmp ;
  u32 clock_bits ;
  unsigned int __cil_tmp8 ;
  u32 __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;
  u32 __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  void *__cil_tmp16 ;
  void const volatile   *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;

  {
  {
#line 125
  gpio = (struct intel_gpio *)data;
#line 126
  dev_priv = gpio->dev_priv;
#line 127
  tmp = get_reserved(gpio);
#line 127
  reserved = tmp;
  }
#line 130
  if (state_high != 0) {
#line 131
    clock_bits = 1U;
  } else {
#line 133
    clock_bits = 7U;
  }
  {
#line 136
  __cil_tmp8 = reserved | clock_bits;
#line 136
  __cil_tmp9 = gpio->reg;
#line 136
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 136
  __cil_tmp11 = dev_priv->regs;
#line 136
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 136
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 136
  writel(__cil_tmp8, __cil_tmp13);
#line 137
  __cil_tmp14 = gpio->reg;
#line 137
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 137
  __cil_tmp16 = dev_priv->regs;
#line 137
  __cil_tmp17 = (void const volatile   *)__cil_tmp16;
#line 137
  __cil_tmp18 = __cil_tmp17 + __cil_tmp15;
#line 137
  readl(__cil_tmp18);
  }
#line 138
  return;
}
}
#line 140 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static void set_data(void *data , int state_high ) 
{ struct intel_gpio *gpio ;
  struct drm_i915_private *dev_priv ;
  u32 reserved ;
  u32 tmp ;
  u32 data_bits ;
  unsigned int __cil_tmp8 ;
  u32 __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  void *__cil_tmp11 ;
  void volatile   *__cil_tmp12 ;
  void volatile   *__cil_tmp13 ;
  u32 __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  void *__cil_tmp16 ;
  void const volatile   *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;

  {
  {
#line 142
  gpio = (struct intel_gpio *)data;
#line 143
  dev_priv = gpio->dev_priv;
#line 144
  tmp = get_reserved(gpio);
#line 144
  reserved = tmp;
  }
#line 147
  if (state_high != 0) {
#line 148
    data_bits = 256U;
  } else {
#line 150
    data_bits = 1792U;
  }
  {
#line 153
  __cil_tmp8 = reserved | data_bits;
#line 153
  __cil_tmp9 = gpio->reg;
#line 153
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 153
  __cil_tmp11 = dev_priv->regs;
#line 153
  __cil_tmp12 = (void volatile   *)__cil_tmp11;
#line 153
  __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 153
  writel(__cil_tmp8, __cil_tmp13);
#line 154
  __cil_tmp14 = gpio->reg;
#line 154
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 154
  __cil_tmp16 = dev_priv->regs;
#line 154
  __cil_tmp17 = (void const volatile   *)__cil_tmp16;
#line 154
  __cil_tmp18 = __cil_tmp17 + __cil_tmp15;
#line 154
  readl(__cil_tmp18);
  }
#line 155
  return;
}
}
#line 158 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static struct i2c_adapter *intel_gpio_create(struct drm_i915_private *dev_priv , u32 pin ) 
{ int map_pin_to_reg[8U] ;
  struct intel_gpio *gpio ;
  void *tmp ;
  unsigned long tmp___0 ;
  int tmp___1 ;
  struct intel_gpio *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct drm_device *__cil_tmp11 ;
  void *__cil_tmp12 ;
  struct drm_i915_private *__cil_tmp13 ;
  struct intel_device_info  const  *__cil_tmp14 ;
  u8 __cil_tmp15 ;
  unsigned char __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  u32 __cil_tmp18 ;
  struct drm_device *__cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  u8 __cil_tmp23 ;
  unsigned char __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  u32 __cil_tmp26 ;
  struct drm_device *__cil_tmp27 ;
  void *__cil_tmp28 ;
  struct drm_i915_private *__cil_tmp29 ;
  struct intel_device_info  const  *__cil_tmp30 ;
  unsigned char *__cil_tmp31 ;
  unsigned char *__cil_tmp32 ;
  unsigned char __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  u32 __cil_tmp35 ;
  char (*__cil_tmp36)[48U] ;
  char *__cil_tmp37 ;
  char const   *__cil_tmp38 ;
  char __cil_tmp39 ;
  int __cil_tmp40 ;
  struct i2c_algo_bit_data *__cil_tmp41 ;
  struct drm_device *__cil_tmp42 ;
  struct pci_dev *__cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  struct i2c_adapter *__cil_tmp46 ;
  void const   *__cil_tmp47 ;

  {
#line 160
  map_pin_to_reg[0] = 0;
#line 160
  map_pin_to_reg[1] = 20500;
#line 160
  map_pin_to_reg[2] = 20496;
#line 160
  map_pin_to_reg[3] = 20504;
#line 160
  map_pin_to_reg[4] = 20508;
#line 160
  map_pin_to_reg[5] = 20512;
#line 160
  map_pin_to_reg[6] = 0;
#line 160
  map_pin_to_reg[7] = 20516;
#line 172
  if (pin > 7U) {
#line 173
    return ((struct i2c_adapter *)0);
  } else
#line 172
  if (map_pin_to_reg[pin] == 0) {
#line 173
    return ((struct i2c_adapter *)0);
  } else {

  }
  {
#line 175
  tmp = kzalloc(1720UL, 208U);
#line 175
  gpio = (struct intel_gpio *)tmp;
  }
  {
#line 176
  __cil_tmp8 = (struct intel_gpio *)0;
#line 176
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 176
  __cil_tmp10 = (unsigned long )gpio;
#line 176
  if (__cil_tmp10 == __cil_tmp9) {
#line 177
    return ((struct i2c_adapter *)0);
  } else {

  }
  }
#line 179
  gpio->reg = (u32 )map_pin_to_reg[pin];
  {
#line 180
  __cil_tmp11 = dev_priv->dev;
#line 180
  __cil_tmp12 = __cil_tmp11->dev_private;
#line 180
  __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
#line 180
  __cil_tmp14 = __cil_tmp13->info;
#line 180
  __cil_tmp15 = __cil_tmp14->gen;
#line 180
  __cil_tmp16 = (unsigned char )__cil_tmp15;
#line 180
  __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 180
  if (__cil_tmp17 == 5U) {
#line 181
    __cil_tmp18 = gpio->reg;
#line 181
    gpio->reg = __cil_tmp18 + 786432U;
  } else {
    {
#line 180
    __cil_tmp19 = dev_priv->dev;
#line 180
    __cil_tmp20 = __cil_tmp19->dev_private;
#line 180
    __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 180
    __cil_tmp22 = __cil_tmp21->info;
#line 180
    __cil_tmp23 = __cil_tmp22->gen;
#line 180
    __cil_tmp24 = (unsigned char )__cil_tmp23;
#line 180
    __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 180
    if (__cil_tmp25 == 6U) {
#line 181
      __cil_tmp26 = gpio->reg;
#line 181
      gpio->reg = __cil_tmp26 + 786432U;
    } else {
      {
#line 180
      __cil_tmp27 = dev_priv->dev;
#line 180
      __cil_tmp28 = __cil_tmp27->dev_private;
#line 180
      __cil_tmp29 = (struct drm_i915_private *)__cil_tmp28;
#line 180
      __cil_tmp30 = __cil_tmp29->info;
#line 180
      __cil_tmp31 = (unsigned char *)__cil_tmp30;
#line 180
      __cil_tmp32 = __cil_tmp31 + 2UL;
#line 180
      __cil_tmp33 = *__cil_tmp32;
#line 180
      __cil_tmp34 = (unsigned int )__cil_tmp33;
#line 180
      if (__cil_tmp34 != 0U) {
#line 181
        __cil_tmp35 = gpio->reg;
#line 181
        gpio->reg = __cil_tmp35 + 786432U;
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 182
  gpio->dev_priv = dev_priv;
#line 184
  __cil_tmp36 = & gpio->adapter.name;
#line 184
  __cil_tmp37 = (char *)__cil_tmp36;
#line 184
  __cil_tmp38 = "?BACDE?F" + pin;
#line 184
  __cil_tmp39 = *__cil_tmp38;
#line 184
  __cil_tmp40 = (int )__cil_tmp39;
#line 184
  snprintf(__cil_tmp37, 48UL, "i915 GPIO%c", __cil_tmp40);
#line 186
  gpio->adapter.owner = & __this_module;
#line 187
  __cil_tmp41 = & gpio->algo;
#line 187
  gpio->adapter.algo_data = (void *)__cil_tmp41;
#line 188
  __cil_tmp42 = dev_priv->dev;
#line 188
  __cil_tmp43 = __cil_tmp42->pdev;
#line 188
  gpio->adapter.dev.parent = & __cil_tmp43->dev;
#line 189
  gpio->algo.setsda = & set_data;
#line 190
  gpio->algo.setscl = & set_clock;
#line 191
  gpio->algo.getsda = & get_data;
#line 192
  gpio->algo.getscl = & get_clock;
#line 193
  gpio->algo.udelay = 20;
#line 194
  __cil_tmp44 = (unsigned int const   )2200U;
#line 194
  __cil_tmp45 = (unsigned int )__cil_tmp44;
#line 194
  tmp___0 = usecs_to_jiffies(__cil_tmp45);
#line 194
  gpio->algo.timeout = (int )tmp___0;
#line 195
  gpio->algo.data = (void *)gpio;
#line 197
  __cil_tmp46 = & gpio->adapter;
#line 197
  tmp___1 = i2c_bit_add_bus(__cil_tmp46);
  }
#line 197
  if (tmp___1 != 0) {
#line 198
    goto out_free;
  } else {

  }
#line 200
  return (& gpio->adapter);
  out_free: 
  {
#line 203
  __cil_tmp47 = (void const   *)gpio;
#line 203
  kfree(__cil_tmp47);
  }
#line 204
  return ((struct i2c_adapter *)0);
}
}
#line 208 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static int intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv , struct i2c_adapter *adapter ,
                                struct i2c_msg *msgs , int num ) 
{ struct intel_gpio *gpio ;
  struct i2c_adapter  const  *__mptr ;
  int ret ;
  struct drm_device *__cil_tmp8 ;
  bool __cil_tmp9 ;
  void *__cil_tmp10 ;
  void *__cil_tmp11 ;
  struct i2c_algorithm  const  *__cil_tmp12 ;
  int (*__cil_tmp13)(struct i2c_adapter * , struct i2c_msg * , int  ) ;
  void *__cil_tmp14 ;
  void *__cil_tmp15 ;
  bool __cil_tmp16 ;

  {
  {
#line 213
  __mptr = (struct i2c_adapter  const  *)adapter;
#line 213
  gpio = (struct intel_gpio *)__mptr;
#line 218
  __cil_tmp8 = dev_priv->dev;
#line 218
  intel_i2c_reset(__cil_tmp8);
#line 220
  __cil_tmp9 = (bool )1;
#line 220
  intel_i2c_quirk_set(dev_priv, __cil_tmp9);
#line 221
  __cil_tmp10 = (void *)gpio;
#line 221
  set_data(__cil_tmp10, 1);
#line 222
  __cil_tmp11 = (void *)gpio;
#line 222
  set_clock(__cil_tmp11, 1);
#line 223
  __const_udelay(85900UL);
#line 225
  __cil_tmp12 = adapter->algo;
#line 225
  __cil_tmp13 = __cil_tmp12->master_xfer;
#line 225
  ret = (*__cil_tmp13)(adapter, msgs, num);
#line 227
  __cil_tmp14 = (void *)gpio;
#line 227
  set_data(__cil_tmp14, 1);
#line 228
  __cil_tmp15 = (void *)gpio;
#line 228
  set_clock(__cil_tmp15, 1);
#line 229
  __cil_tmp16 = (bool )0;
#line 229
  intel_i2c_quirk_set(dev_priv, __cil_tmp16);
  }
#line 231
  return (ret);
}
}
#line 235 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static int gmbus_xfer(struct i2c_adapter *adapter , struct i2c_msg *msgs , int num ) 
{ struct intel_gmbus *bus ;
  struct i2c_adapter  const  *__mptr ;
  struct drm_i915_private *dev_priv ;
  int i ;
  int reg_offset ;
  int tmp ;
  u16 len ;
  u8 *buf ;
  int tmp___0 ;
  u32 val ;
  u32 loop ;
  unsigned long timeout__ ;
  unsigned long tmp___1 ;
  int ret__ ;
  struct thread_info *tmp___2 ;
  int pfo_ret__ ;
  int tmp___3 ;
  u32 tmp___4 ;
  u32 tmp___5 ;
  u8 *tmp___6 ;
  u32 val___0 ;
  u32 loop___0 ;
  u8 *tmp___7 ;
  int tmp___8 ;
  unsigned long timeout_____0 ;
  unsigned long tmp___9 ;
  int ret_____0 ;
  struct thread_info *tmp___10 ;
  int pfo_ret_____0 ;
  int tmp___11 ;
  u32 tmp___12 ;
  u32 tmp___13 ;
  u8 *tmp___14 ;
  unsigned long timeout_____1 ;
  unsigned long tmp___15 ;
  int ret_____1 ;
  struct thread_info *tmp___16 ;
  int pfo_ret_____1 ;
  int tmp___17 ;
  u32 tmp___18 ;
  u32 tmp___19 ;
  int tmp___20 ;
  void *__cil_tmp46 ;
  struct i2c_adapter *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  struct i2c_adapter *__cil_tmp49 ;
  unsigned long __cil_tmp50 ;
  struct i2c_adapter *__cil_tmp51 ;
  struct drm_device *__cil_tmp52 ;
  void *__cil_tmp53 ;
  struct drm_i915_private *__cil_tmp54 ;
  struct intel_device_info  const  *__cil_tmp55 ;
  u8 __cil_tmp56 ;
  unsigned char __cil_tmp57 ;
  unsigned int __cil_tmp58 ;
  struct drm_device *__cil_tmp59 ;
  void *__cil_tmp60 ;
  struct drm_i915_private *__cil_tmp61 ;
  struct intel_device_info  const  *__cil_tmp62 ;
  u8 __cil_tmp63 ;
  unsigned char __cil_tmp64 ;
  unsigned int __cil_tmp65 ;
  struct drm_device *__cil_tmp66 ;
  void *__cil_tmp67 ;
  struct drm_i915_private *__cil_tmp68 ;
  struct intel_device_info  const  *__cil_tmp69 ;
  unsigned char *__cil_tmp70 ;
  unsigned char *__cil_tmp71 ;
  unsigned char __cil_tmp72 ;
  unsigned int __cil_tmp73 ;
  int __cil_tmp74 ;
  u32 __cil_tmp75 ;
  u32 __cil_tmp76 ;
  unsigned long __cil_tmp77 ;
  struct i2c_msg *__cil_tmp78 ;
  unsigned long __cil_tmp79 ;
  struct i2c_msg *__cil_tmp80 ;
  unsigned long __cil_tmp81 ;
  struct i2c_msg *__cil_tmp82 ;
  __u16 __cil_tmp83 ;
  int __cil_tmp84 ;
  int __cil_tmp85 ;
  int __cil_tmp86 ;
  u32 __cil_tmp87 ;
  unsigned long __cil_tmp88 ;
  struct i2c_msg *__cil_tmp89 ;
  __u16 __cil_tmp90 ;
  int __cil_tmp91 ;
  int __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  int __cil_tmp95 ;
  int __cil_tmp96 ;
  int __cil_tmp97 ;
  u32 __cil_tmp98 ;
  int __cil_tmp99 ;
  unsigned long __cil_tmp100 ;
  void *__cil_tmp101 ;
  void const volatile   *__cil_tmp102 ;
  void const volatile   *__cil_tmp103 ;
  unsigned int __cil_tmp104 ;
  unsigned int __cil_tmp105 ;
  unsigned long __cil_tmp106 ;
  long __cil_tmp107 ;
  long __cil_tmp108 ;
  long __cil_tmp109 ;
  int __cil_tmp110 ;
  int __cil_tmp111 ;
  atomic_t const   *__cil_tmp112 ;
  int __cil_tmp113 ;
  u32 __cil_tmp114 ;
  unsigned int __cil_tmp115 ;
  int __cil_tmp116 ;
  u32 __cil_tmp117 ;
  unsigned int __cil_tmp118 ;
  int __cil_tmp119 ;
  u32 __cil_tmp120 ;
  int __cil_tmp121 ;
  int __cil_tmp122 ;
  unsigned int __cil_tmp123 ;
  unsigned int __cil_tmp124 ;
  u32 __cil_tmp125 ;
  int __cil_tmp126 ;
  u8 __cil_tmp127 ;
  int __cil_tmp128 ;
  int __cil_tmp129 ;
  u32 __cil_tmp130 ;
  int __cil_tmp131 ;
  int __cil_tmp132 ;
  unsigned int __cil_tmp133 ;
  int __cil_tmp134 ;
  u32 __cil_tmp135 ;
  int __cil_tmp136 ;
  int __cil_tmp137 ;
  u32 __cil_tmp138 ;
  unsigned long __cil_tmp139 ;
  struct i2c_msg *__cil_tmp140 ;
  __u16 __cil_tmp141 ;
  int __cil_tmp142 ;
  int __cil_tmp143 ;
  unsigned long __cil_tmp144 ;
  struct i2c_msg *__cil_tmp145 ;
  __u16 __cil_tmp146 ;
  int __cil_tmp147 ;
  int __cil_tmp148 ;
  int __cil_tmp149 ;
  int __cil_tmp150 ;
  int __cil_tmp151 ;
  u32 __cil_tmp152 ;
  int __cil_tmp153 ;
  unsigned long __cil_tmp154 ;
  void *__cil_tmp155 ;
  void const volatile   *__cil_tmp156 ;
  void const volatile   *__cil_tmp157 ;
  unsigned int __cil_tmp158 ;
  unsigned int __cil_tmp159 ;
  unsigned long __cil_tmp160 ;
  long __cil_tmp161 ;
  long __cil_tmp162 ;
  long __cil_tmp163 ;
  int __cil_tmp164 ;
  int __cil_tmp165 ;
  atomic_t const   *__cil_tmp166 ;
  int __cil_tmp167 ;
  u32 __cil_tmp168 ;
  unsigned int __cil_tmp169 ;
  int __cil_tmp170 ;
  u32 __cil_tmp171 ;
  unsigned int __cil_tmp172 ;
  u32 __cil_tmp173 ;
  int __cil_tmp174 ;
  u8 __cil_tmp175 ;
  int __cil_tmp176 ;
  int __cil_tmp177 ;
  u32 __cil_tmp178 ;
  int __cil_tmp179 ;
  int __cil_tmp180 ;
  unsigned int __cil_tmp181 ;
  int __cil_tmp182 ;
  u32 __cil_tmp183 ;
  int __cil_tmp184 ;
  unsigned long __cil_tmp185 ;
  void *__cil_tmp186 ;
  void const volatile   *__cil_tmp187 ;
  void const volatile   *__cil_tmp188 ;
  unsigned int __cil_tmp189 ;
  int __cil_tmp190 ;
  unsigned int __cil_tmp191 ;
  unsigned int __cil_tmp192 ;
  unsigned long __cil_tmp193 ;
  long __cil_tmp194 ;
  long __cil_tmp195 ;
  long __cil_tmp196 ;
  int __cil_tmp197 ;
  int __cil_tmp198 ;
  atomic_t const   *__cil_tmp199 ;
  int __cil_tmp200 ;
  u32 __cil_tmp201 ;
  unsigned int __cil_tmp202 ;
  int __cil_tmp203 ;
  u32 __cil_tmp204 ;
  unsigned int __cil_tmp205 ;
  int __cil_tmp206 ;
  u32 __cil_tmp207 ;
  int __cil_tmp208 ;
  u32 __cil_tmp209 ;
  int __cil_tmp210 ;
  u32 __cil_tmp211 ;
  u32 __cil_tmp212 ;
  unsigned int __cil_tmp213 ;
  char (*__cil_tmp214)[48U] ;
  char *__cil_tmp215 ;
  int __cil_tmp216 ;
  u32 __cil_tmp217 ;
  u32 __cil_tmp218 ;
  unsigned int __cil_tmp219 ;
  struct i2c_adapter *__cil_tmp220 ;
  unsigned long __cil_tmp221 ;
  struct i2c_adapter *__cil_tmp222 ;
  unsigned long __cil_tmp223 ;
  struct i2c_adapter *__cil_tmp224 ;

  {
#line 239
  __mptr = (struct i2c_adapter  const  *)adapter;
#line 239
  bus = (struct intel_gmbus *)__mptr;
#line 242
  __cil_tmp46 = adapter->algo_data;
#line 242
  dev_priv = (struct drm_i915_private *)__cil_tmp46;
  {
#line 245
  __cil_tmp47 = (struct i2c_adapter *)0;
#line 245
  __cil_tmp48 = (unsigned long )__cil_tmp47;
#line 245
  __cil_tmp49 = bus->force_bit;
#line 245
  __cil_tmp50 = (unsigned long )__cil_tmp49;
#line 245
  if (__cil_tmp50 != __cil_tmp48) {
    {
#line 246
    __cil_tmp51 = bus->force_bit;
#line 246
    tmp = intel_i2c_quirk_xfer(dev_priv, __cil_tmp51, msgs, num);
    }
#line 246
    return (tmp);
  } else {

  }
  }
  {
#line 249
  __cil_tmp52 = dev_priv->dev;
#line 249
  __cil_tmp53 = __cil_tmp52->dev_private;
#line 249
  __cil_tmp54 = (struct drm_i915_private *)__cil_tmp53;
#line 249
  __cil_tmp55 = __cil_tmp54->info;
#line 249
  __cil_tmp56 = __cil_tmp55->gen;
#line 249
  __cil_tmp57 = (unsigned char )__cil_tmp56;
#line 249
  __cil_tmp58 = (unsigned int )__cil_tmp57;
#line 249
  if (__cil_tmp58 == 5U) {
#line 249
    reg_offset = 786432;
  } else {
    {
#line 249
    __cil_tmp59 = dev_priv->dev;
#line 249
    __cil_tmp60 = __cil_tmp59->dev_private;
#line 249
    __cil_tmp61 = (struct drm_i915_private *)__cil_tmp60;
#line 249
    __cil_tmp62 = __cil_tmp61->info;
#line 249
    __cil_tmp63 = __cil_tmp62->gen;
#line 249
    __cil_tmp64 = (unsigned char )__cil_tmp63;
#line 249
    __cil_tmp65 = (unsigned int )__cil_tmp64;
#line 249
    if (__cil_tmp65 == 6U) {
#line 249
      reg_offset = 786432;
    } else {
      {
#line 249
      __cil_tmp66 = dev_priv->dev;
#line 249
      __cil_tmp67 = __cil_tmp66->dev_private;
#line 249
      __cil_tmp68 = (struct drm_i915_private *)__cil_tmp67;
#line 249
      __cil_tmp69 = __cil_tmp68->info;
#line 249
      __cil_tmp70 = (unsigned char *)__cil_tmp69;
#line 249
      __cil_tmp71 = __cil_tmp70 + 2UL;
#line 249
      __cil_tmp72 = *__cil_tmp71;
#line 249
      __cil_tmp73 = (unsigned int )__cil_tmp72;
#line 249
      if (__cil_tmp73 != 0U) {
#line 249
        reg_offset = 786432;
      } else {
#line 249
        reg_offset = 0;
      }
      }
    }
    }
  }
  }
  {
#line 251
  __cil_tmp74 = reg_offset + 20736;
#line 251
  __cil_tmp75 = (u32 )__cil_tmp74;
#line 251
  __cil_tmp76 = bus->reg0;
#line 251
  i915_write32___12(dev_priv, __cil_tmp75, __cil_tmp76);
#line 253
  i = 0;
  }
#line 253
  goto ldv_37733;
  ldv_37732: 
#line 254
  __cil_tmp77 = (unsigned long )i;
#line 254
  __cil_tmp78 = msgs + __cil_tmp77;
#line 254
  len = __cil_tmp78->len;
#line 255
  __cil_tmp79 = (unsigned long )i;
#line 255
  __cil_tmp80 = msgs + __cil_tmp79;
#line 255
  buf = __cil_tmp80->buf;
  {
#line 257
  __cil_tmp81 = (unsigned long )i;
#line 257
  __cil_tmp82 = msgs + __cil_tmp81;
#line 257
  __cil_tmp83 = __cil_tmp82->flags;
#line 257
  __cil_tmp84 = (int )__cil_tmp83;
#line 257
  if (__cil_tmp84 & 1) {
    {
#line 258
    __cil_tmp85 = i + 1;
#line 258
    if (__cil_tmp85 == num) {
#line 258
      tmp___0 = 167772160;
    } else {
#line 258
      tmp___0 = 33554432;
    }
    }
    {
#line 258
    __cil_tmp86 = reg_offset + 20740;
#line 258
    __cil_tmp87 = (u32 )__cil_tmp86;
#line 258
    __cil_tmp88 = (unsigned long )i;
#line 258
    __cil_tmp89 = msgs + __cil_tmp88;
#line 258
    __cil_tmp90 = __cil_tmp89->addr;
#line 258
    __cil_tmp91 = (int )__cil_tmp90;
#line 258
    __cil_tmp92 = __cil_tmp91 << 1;
#line 258
    __cil_tmp93 = (int )len;
#line 258
    __cil_tmp94 = __cil_tmp93 << 16;
#line 258
    __cil_tmp95 = tmp___0 | __cil_tmp94;
#line 258
    __cil_tmp96 = __cil_tmp95 | __cil_tmp92;
#line 258
    __cil_tmp97 = __cil_tmp96 | 1073741825;
#line 258
    __cil_tmp98 = (u32 )__cil_tmp97;
#line 258
    i915_write32___12(dev_priv, __cil_tmp87, __cil_tmp98);
#line 263
    __cil_tmp99 = reg_offset + 20744;
#line 263
    __cil_tmp100 = (unsigned long )__cil_tmp99;
#line 263
    __cil_tmp101 = dev_priv->regs;
#line 263
    __cil_tmp102 = (void const volatile   *)__cil_tmp101;
#line 263
    __cil_tmp103 = __cil_tmp102 + __cil_tmp100;
#line 263
    readl(__cil_tmp103);
    }
    ldv_37681: 
    {
#line 265
    loop = 0U;
#line 267
    __cil_tmp104 = (unsigned int const   )50U;
#line 267
    __cil_tmp105 = (unsigned int )__cil_tmp104;
#line 267
    tmp___1 = msecs_to_jiffies(__cil_tmp105);
#line 267
    __cil_tmp106 = (unsigned long )jiffies;
#line 267
    timeout__ = tmp___1 + __cil_tmp106;
#line 267
    ret__ = 0;
    }
#line 267
    goto ldv_37675;
    ldv_37674: ;
    {
#line 267
    __cil_tmp107 = (long )jiffies;
#line 267
    __cil_tmp108 = (long )timeout__;
#line 267
    __cil_tmp109 = __cil_tmp108 - __cil_tmp107;
#line 267
    if (__cil_tmp109 < 0L) {
#line 267
      ret__ = -110;
#line 267
      goto ldv_37665;
    } else {

    }
    }
    {
#line 267
    tmp___2 = current_thread_info();
    }
    {
#line 267
    __cil_tmp110 = tmp___2->preempt_count;
#line 267
    __cil_tmp111 = __cil_tmp110 & -268435457;
#line 267
    if (__cil_tmp111 == 0) {
#line 267
      if (1) {
#line 267
        goto case_4;
      } else {
#line 267
        goto switch_default;
#line 267
        if (0) {
#line 267
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 267
          goto ldv_37668;
#line 267
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 267
          goto ldv_37668;
          case_4: 
#line 267
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 267
          goto ldv_37668;
#line 267
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 267
          goto ldv_37668;
          switch_default: 
          {
#line 267
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_37668: 
      {
#line 267
      __cil_tmp112 = (atomic_t const   *)(& kgdb_active);
#line 267
      tmp___3 = atomic_read(__cil_tmp112);
      }
#line 267
      if (pfo_ret__ != tmp___3) {
        {
#line 267
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_37675: 
    {
#line 267
    __cil_tmp113 = reg_offset + 20744;
#line 267
    __cil_tmp114 = (u32 )__cil_tmp113;
#line 267
    tmp___4 = i915_read32___14(dev_priv, __cil_tmp114);
    }
    {
#line 267
    __cil_tmp115 = tmp___4 & 3072U;
#line 267
    if (__cil_tmp115 == 0U) {
#line 268
      goto ldv_37674;
    } else {
#line 270
      goto ldv_37665;
    }
    }
    ldv_37665: ;
#line 267
    if (ret__ != 0) {
#line 268
      goto timeout;
    } else {

    }
    {
#line 269
    __cil_tmp116 = reg_offset + 20744;
#line 269
    __cil_tmp117 = (u32 )__cil_tmp116;
#line 269
    tmp___5 = i915_read32___14(dev_priv, __cil_tmp117);
    }
    {
#line 269
    __cil_tmp118 = tmp___5 & 1024U;
#line 269
    if (__cil_tmp118 != 0U) {
#line 270
      goto clear_err;
    } else {

    }
    }
    {
#line 272
    __cil_tmp119 = reg_offset + 20748;
#line 272
    __cil_tmp120 = (u32 )__cil_tmp119;
#line 272
    val = i915_read32___14(dev_priv, __cil_tmp120);
    }
    ldv_37679: 
#line 274
    tmp___6 = buf;
#line 274
    buf = buf + 1;
#line 274
    *tmp___6 = (u8 )val;
#line 275
    val = val >> 8;
#line 276
    __cil_tmp121 = (int )len;
#line 276
    __cil_tmp122 = __cil_tmp121 - 1;
#line 276
    len = (u16 )__cil_tmp122;
    {
#line 276
    __cil_tmp123 = (unsigned int )len;
#line 276
    if (__cil_tmp123 != 0U) {
#line 276
      loop = loop + 1U;
#line 276
      if (loop <= 3U) {
#line 277
        goto ldv_37679;
      } else {
#line 279
        goto ldv_37680;
      }
    } else {
#line 279
      goto ldv_37680;
    }
    }
    ldv_37680: ;
    {
#line 277
    __cil_tmp124 = (unsigned int )len;
#line 277
    if (__cil_tmp124 != 0U) {
#line 278
      goto ldv_37681;
    } else {
#line 280
      goto ldv_37682;
    }
    }
    ldv_37682: ;
  } else {
#line 281
    loop___0 = 0U;
#line 281
    val___0 = loop___0;
    ldv_37685: 
#line 283
    tmp___7 = buf;
#line 283
    buf = buf + 1;
#line 283
    __cil_tmp125 = loop___0 * 8U;
#line 283
    __cil_tmp126 = (int )__cil_tmp125;
#line 283
    __cil_tmp127 = *tmp___7;
#line 283
    __cil_tmp128 = (int )__cil_tmp127;
#line 283
    __cil_tmp129 = __cil_tmp128 << __cil_tmp126;
#line 283
    __cil_tmp130 = (u32 )__cil_tmp129;
#line 283
    val___0 = __cil_tmp130 | val___0;
#line 284
    __cil_tmp131 = (int )len;
#line 284
    __cil_tmp132 = __cil_tmp131 - 1;
#line 284
    len = (u16 )__cil_tmp132;
    {
#line 284
    __cil_tmp133 = (unsigned int )len;
#line 284
    if (__cil_tmp133 != 0U) {
#line 284
      loop___0 = loop___0 + 1U;
#line 284
      if (loop___0 <= 3U) {
#line 285
        goto ldv_37685;
      } else {
#line 287
        goto ldv_37686;
      }
    } else {
#line 287
      goto ldv_37686;
    }
    }
    ldv_37686: 
    {
#line 286
    __cil_tmp134 = reg_offset + 20748;
#line 286
    __cil_tmp135 = (u32 )__cil_tmp134;
#line 286
    i915_write32___12(dev_priv, __cil_tmp135, val___0);
    }
    {
#line 287
    __cil_tmp136 = i + 1;
#line 287
    if (__cil_tmp136 == num) {
#line 287
      tmp___8 = 134217728;
    } else {
#line 287
      tmp___8 = 33554432;
    }
    }
    {
#line 287
    __cil_tmp137 = reg_offset + 20740;
#line 287
    __cil_tmp138 = (u32 )__cil_tmp137;
#line 287
    __cil_tmp139 = (unsigned long )i;
#line 287
    __cil_tmp140 = msgs + __cil_tmp139;
#line 287
    __cil_tmp141 = __cil_tmp140->addr;
#line 287
    __cil_tmp142 = (int )__cil_tmp141;
#line 287
    __cil_tmp143 = __cil_tmp142 << 1;
#line 287
    __cil_tmp144 = (unsigned long )i;
#line 287
    __cil_tmp145 = msgs + __cil_tmp144;
#line 287
    __cil_tmp146 = __cil_tmp145->len;
#line 287
    __cil_tmp147 = (int )__cil_tmp146;
#line 287
    __cil_tmp148 = __cil_tmp147 << 16;
#line 287
    __cil_tmp149 = tmp___8 | __cil_tmp148;
#line 287
    __cil_tmp150 = __cil_tmp149 | __cil_tmp143;
#line 287
    __cil_tmp151 = __cil_tmp150 | 1073741824;
#line 287
    __cil_tmp152 = (u32 )__cil_tmp151;
#line 287
    i915_write32___12(dev_priv, __cil_tmp138, __cil_tmp152);
#line 292
    __cil_tmp153 = reg_offset + 20744;
#line 292
    __cil_tmp154 = (unsigned long )__cil_tmp153;
#line 292
    __cil_tmp155 = dev_priv->regs;
#line 292
    __cil_tmp156 = (void const volatile   *)__cil_tmp155;
#line 292
    __cil_tmp157 = __cil_tmp156 + __cil_tmp154;
#line 292
    readl(__cil_tmp157);
    }
#line 294
    goto ldv_37710;
    ldv_37709: 
    {
#line 295
    __cil_tmp158 = (unsigned int const   )50U;
#line 295
    __cil_tmp159 = (unsigned int )__cil_tmp158;
#line 295
    tmp___9 = msecs_to_jiffies(__cil_tmp159);
#line 295
    __cil_tmp160 = (unsigned long )jiffies;
#line 295
    timeout_____0 = tmp___9 + __cil_tmp160;
#line 295
    ret_____0 = 0;
    }
#line 295
    goto ldv_37705;
    ldv_37704: ;
    {
#line 295
    __cil_tmp161 = (long )jiffies;
#line 295
    __cil_tmp162 = (long )timeout_____0;
#line 295
    __cil_tmp163 = __cil_tmp162 - __cil_tmp161;
#line 295
    if (__cil_tmp163 < 0L) {
#line 295
      ret_____0 = -110;
#line 295
      goto ldv_37695;
    } else {

    }
    }
    {
#line 295
    tmp___10 = current_thread_info();
    }
    {
#line 295
    __cil_tmp164 = tmp___10->preempt_count;
#line 295
    __cil_tmp165 = __cil_tmp164 & -268435457;
#line 295
    if (__cil_tmp165 == 0) {
#line 295
      if (1) {
#line 295
        goto case_4___0;
      } else {
#line 295
        goto switch_default___0;
#line 295
        if (0) {
#line 295
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret_____0): "m" (cpu_number));
#line 295
          goto ldv_37698;
#line 295
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret_____0): "m" (cpu_number));
#line 295
          goto ldv_37698;
          case_4___0: 
#line 295
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret_____0): "m" (cpu_number));
#line 295
          goto ldv_37698;
#line 295
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret_____0): "m" (cpu_number));
#line 295
          goto ldv_37698;
          switch_default___0: 
          {
#line 295
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_37698: 
      {
#line 295
      __cil_tmp166 = (atomic_t const   *)(& kgdb_active);
#line 295
      tmp___11 = atomic_read(__cil_tmp166);
      }
#line 295
      if (pfo_ret_____0 != tmp___11) {
        {
#line 295
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_37705: 
    {
#line 295
    __cil_tmp167 = reg_offset + 20744;
#line 295
    __cil_tmp168 = (u32 )__cil_tmp167;
#line 295
    tmp___12 = i915_read32___14(dev_priv, __cil_tmp168);
    }
    {
#line 295
    __cil_tmp169 = tmp___12 & 3072U;
#line 295
    if (__cil_tmp169 == 0U) {
#line 296
      goto ldv_37704;
    } else {
#line 298
      goto ldv_37695;
    }
    }
    ldv_37695: ;
#line 295
    if (ret_____0 != 0) {
#line 296
      goto timeout;
    } else {

    }
    {
#line 297
    __cil_tmp170 = reg_offset + 20744;
#line 297
    __cil_tmp171 = (u32 )__cil_tmp170;
#line 297
    tmp___13 = i915_read32___14(dev_priv, __cil_tmp171);
    }
    {
#line 297
    __cil_tmp172 = tmp___13 & 1024U;
#line 297
    if (__cil_tmp172 != 0U) {
#line 298
      goto clear_err;
    } else {

    }
    }
#line 300
    loop___0 = 0U;
#line 300
    val___0 = loop___0;
    ldv_37707: 
#line 302
    tmp___14 = buf;
#line 302
    buf = buf + 1;
#line 302
    __cil_tmp173 = loop___0 * 8U;
#line 302
    __cil_tmp174 = (int )__cil_tmp173;
#line 302
    __cil_tmp175 = *tmp___14;
#line 302
    __cil_tmp176 = (int )__cil_tmp175;
#line 302
    __cil_tmp177 = __cil_tmp176 << __cil_tmp174;
#line 302
    __cil_tmp178 = (u32 )__cil_tmp177;
#line 302
    val___0 = __cil_tmp178 | val___0;
#line 303
    __cil_tmp179 = (int )len;
#line 303
    __cil_tmp180 = __cil_tmp179 - 1;
#line 303
    len = (u16 )__cil_tmp180;
    {
#line 303
    __cil_tmp181 = (unsigned int )len;
#line 303
    if (__cil_tmp181 != 0U) {
#line 303
      loop___0 = loop___0 + 1U;
#line 303
      if (loop___0 <= 3U) {
#line 304
        goto ldv_37707;
      } else {
#line 306
        goto ldv_37708;
      }
    } else {
#line 306
      goto ldv_37708;
    }
    }
    ldv_37708: 
    {
#line 305
    __cil_tmp182 = reg_offset + 20748;
#line 305
    __cil_tmp183 = (u32 )__cil_tmp182;
#line 305
    i915_write32___12(dev_priv, __cil_tmp183, val___0);
#line 306
    __cil_tmp184 = reg_offset + 20744;
#line 306
    __cil_tmp185 = (unsigned long )__cil_tmp184;
#line 306
    __cil_tmp186 = dev_priv->regs;
#line 306
    __cil_tmp187 = (void const volatile   *)__cil_tmp186;
#line 306
    __cil_tmp188 = __cil_tmp187 + __cil_tmp185;
#line 306
    readl(__cil_tmp188);
    }
    ldv_37710: ;
    {
#line 294
    __cil_tmp189 = (unsigned int )len;
#line 294
    if (__cil_tmp189 != 0U) {
#line 295
      goto ldv_37709;
    } else {
#line 297
      goto ldv_37711;
    }
    }
    ldv_37711: ;
  }
  }
  {
#line 310
  __cil_tmp190 = i + 1;
#line 310
  if (__cil_tmp190 < num) {
    {
#line 310
    __cil_tmp191 = (unsigned int const   )50U;
#line 310
    __cil_tmp192 = (unsigned int )__cil_tmp191;
#line 310
    tmp___15 = msecs_to_jiffies(__cil_tmp192);
#line 310
    __cil_tmp193 = (unsigned long )jiffies;
#line 310
    timeout_____1 = tmp___15 + __cil_tmp193;
#line 310
    ret_____1 = 0;
    }
#line 310
    goto ldv_37730;
    ldv_37729: ;
    {
#line 310
    __cil_tmp194 = (long )jiffies;
#line 310
    __cil_tmp195 = (long )timeout_____1;
#line 310
    __cil_tmp196 = __cil_tmp195 - __cil_tmp194;
#line 310
    if (__cil_tmp196 < 0L) {
#line 310
      ret_____1 = -110;
#line 310
      goto ldv_37720;
    } else {

    }
    }
    {
#line 310
    tmp___16 = current_thread_info();
    }
    {
#line 310
    __cil_tmp197 = tmp___16->preempt_count;
#line 310
    __cil_tmp198 = __cil_tmp197 & -268435457;
#line 310
    if (__cil_tmp198 == 0) {
#line 310
      if (1) {
#line 310
        goto case_4___1;
      } else {
#line 310
        goto switch_default___1;
#line 310
        if (0) {
#line 310
          __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret_____1): "m" (cpu_number));
#line 310
          goto ldv_37723;
#line 310
          __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret_____1): "m" (cpu_number));
#line 310
          goto ldv_37723;
          case_4___1: 
#line 310
          __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret_____1): "m" (cpu_number));
#line 310
          goto ldv_37723;
#line 310
          __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret_____1): "m" (cpu_number));
#line 310
          goto ldv_37723;
          switch_default___1: 
          {
#line 310
          __bad_percpu_size();
          }
        } else {

        }
      }
      ldv_37723: 
      {
#line 310
      __cil_tmp199 = (atomic_t const   *)(& kgdb_active);
#line 310
      tmp___17 = atomic_read(__cil_tmp199);
      }
#line 310
      if (pfo_ret_____1 != tmp___17) {
        {
#line 310
        msleep(1U);
        }
      } else {

      }
    } else {

    }
    }
    ldv_37730: 
    {
#line 310
    __cil_tmp200 = reg_offset + 20744;
#line 310
    __cil_tmp201 = (u32 )__cil_tmp200;
#line 310
    tmp___18 = i915_read32___14(dev_priv, __cil_tmp201);
    }
    {
#line 310
    __cil_tmp202 = tmp___18 & 17408U;
#line 310
    if (__cil_tmp202 == 0U) {
#line 311
      goto ldv_37729;
    } else {
#line 313
      goto ldv_37720;
    }
    }
    ldv_37720: ;
#line 310
    if (ret_____1 != 0) {
#line 311
      goto timeout;
    } else {

    }
  } else {

  }
  }
  {
#line 312
  __cil_tmp203 = reg_offset + 20744;
#line 312
  __cil_tmp204 = (u32 )__cil_tmp203;
#line 312
  tmp___19 = i915_read32___14(dev_priv, __cil_tmp204);
  }
  {
#line 312
  __cil_tmp205 = tmp___19 & 1024U;
#line 312
  if (__cil_tmp205 != 0U) {
#line 313
    goto clear_err;
  } else {

  }
  }
#line 253
  i = i + 1;
  ldv_37733: ;
#line 253
  if (i < num) {
#line 254
    goto ldv_37732;
  } else {
#line 256
    goto ldv_37734;
  }
  ldv_37734: ;
#line 316
  goto done;
  clear_err: 
  {
#line 323
  __cil_tmp206 = reg_offset + 20740;
#line 323
  __cil_tmp207 = (u32 )__cil_tmp206;
#line 323
  i915_write32___12(dev_priv, __cil_tmp207, 2147483648U);
#line 324
  __cil_tmp208 = reg_offset + 20740;
#line 324
  __cil_tmp209 = (u32 )__cil_tmp208;
#line 324
  i915_write32___12(dev_priv, __cil_tmp209, 0U);
  }
  done: 
  {
#line 330
  __cil_tmp210 = reg_offset + 20736;
#line 330
  __cil_tmp211 = (u32 )__cil_tmp210;
#line 330
  i915_write32___12(dev_priv, __cil_tmp211, 0U);
  }
#line 331
  return (i);
  timeout: 
  {
#line 334
  __cil_tmp212 = bus->reg0;
#line 334
  __cil_tmp213 = __cil_tmp212 & 255U;
#line 334
  __cil_tmp214 = & bus->adapter.name;
#line 334
  __cil_tmp215 = (char *)__cil_tmp214;
#line 334
  printk("<6>[drm] GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
         __cil_tmp213, __cil_tmp215);
#line 336
  __cil_tmp216 = reg_offset + 20736;
#line 336
  __cil_tmp217 = (u32 )__cil_tmp216;
#line 336
  i915_write32___12(dev_priv, __cil_tmp217, 0U);
#line 339
  __cil_tmp218 = bus->reg0;
#line 339
  __cil_tmp219 = __cil_tmp218 & 255U;
#line 339
  bus->force_bit = intel_gpio_create(dev_priv, __cil_tmp219);
  }
  {
#line 340
  __cil_tmp220 = (struct i2c_adapter *)0;
#line 340
  __cil_tmp221 = (unsigned long )__cil_tmp220;
#line 340
  __cil_tmp222 = bus->force_bit;
#line 340
  __cil_tmp223 = (unsigned long )__cil_tmp222;
#line 340
  if (__cil_tmp223 == __cil_tmp221) {
#line 341
    return (-12);
  } else {

  }
  }
  {
#line 343
  __cil_tmp224 = bus->force_bit;
#line 343
  tmp___20 = intel_i2c_quirk_xfer(dev_priv, __cil_tmp224, msgs, num);
  }
#line 343
  return (tmp___20);
}
}
#line 346 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static u32 gmbus_func(struct i2c_adapter *adapter ) 
{ struct intel_gmbus *bus ;
  struct i2c_adapter  const  *__mptr ;
  struct i2c_adapter *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct i2c_adapter *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct i2c_adapter *__cil_tmp8 ;
  struct i2c_algorithm  const  *__cil_tmp9 ;
  u32 (*__cil_tmp10)(struct i2c_adapter * ) ;
  struct i2c_adapter *__cil_tmp11 ;

  {
#line 348
  __mptr = (struct i2c_adapter  const  *)adapter;
#line 348
  bus = (struct intel_gmbus *)__mptr;
  {
#line 352
  __cil_tmp4 = (struct i2c_adapter *)0;
#line 352
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 352
  __cil_tmp6 = bus->force_bit;
#line 352
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 352
  if (__cil_tmp7 != __cil_tmp5) {
    {
#line 353
    __cil_tmp8 = bus->force_bit;
#line 353
    __cil_tmp9 = __cil_tmp8->algo;
#line 353
    __cil_tmp10 = __cil_tmp9->functionality;
#line 353
    __cil_tmp11 = bus->force_bit;
#line 353
    (*__cil_tmp10)(__cil_tmp11);
    }
  } else {

  }
  }
#line 355
  return (268402697U);
}
}
#line 361 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
static struct i2c_algorithm  const  gmbus_algorithm  =    {& gmbus_xfer, (int (*)(struct i2c_adapter * , u16  , unsigned short  , char  ,
                           u8  , int  , union i2c_smbus_data * ))0, & gmbus_func};
#line 370 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
int intel_setup_gmbus(struct drm_device *dev ) 
{ char const   *names[8U] ;
  struct drm_i915_private *dev_priv ;
  int ret ;
  int i ;
  void *tmp ;
  struct intel_gmbus *bus ;
  struct intel_gmbus *bus___0 ;
  void *__cil_tmp9 ;
  struct intel_gmbus *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct intel_gmbus *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct intel_gmbus *__cil_tmp15 ;
  char (*__cil_tmp16)[48U] ;
  char *__cil_tmp17 ;
  struct pci_dev *__cil_tmp18 ;
  struct i2c_adapter *__cil_tmp19 ;
  u32 __cil_tmp20 ;
  struct drm_device *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct intel_gmbus *__cil_tmp23 ;
  struct i2c_adapter *__cil_tmp24 ;
  struct intel_gmbus *__cil_tmp25 ;
  void const   *__cil_tmp26 ;

  {
  {
#line 372
  names[0] = "disabled";
#line 372
  names[1] = "ssc";
#line 372
  names[2] = "vga";
#line 372
  names[3] = "panel";
#line 372
  names[4] = "dpc";
#line 372
  names[5] = "dpb";
#line 372
  names[6] = "reserved";
#line 372
  names[7] = "dpd";
#line 382
  __cil_tmp9 = dev->dev_private;
#line 382
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 385
  tmp = kcalloc(1656UL, 8UL, 208U);
#line 385
  dev_priv->gmbus = (struct intel_gmbus *)tmp;
  }
  {
#line 387
  __cil_tmp10 = (struct intel_gmbus *)0;
#line 387
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 387
  __cil_tmp12 = dev_priv->gmbus;
#line 387
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 387
  if (__cil_tmp13 == __cil_tmp11) {
#line 388
    return (-12);
  } else {

  }
  }
#line 390
  i = 0;
#line 390
  goto ldv_37753;
  ldv_37752: 
  {
#line 391
  __cil_tmp14 = (unsigned long )i;
#line 391
  __cil_tmp15 = dev_priv->gmbus;
#line 391
  bus = __cil_tmp15 + __cil_tmp14;
#line 393
  bus->adapter.owner = & __this_module;
#line 394
  bus->adapter.class = 8U;
#line 395
  __cil_tmp16 = & bus->adapter.name;
#line 395
  __cil_tmp17 = (char *)__cil_tmp16;
#line 395
  snprintf(__cil_tmp17, 48UL, "i915 gmbus %s", names[i]);
#line 400
  __cil_tmp18 = dev->pdev;
#line 400
  bus->adapter.dev.parent = & __cil_tmp18->dev;
#line 401
  bus->adapter.algo_data = (void *)dev_priv;
#line 403
  bus->adapter.algo = & gmbus_algorithm;
#line 404
  __cil_tmp19 = & bus->adapter;
#line 404
  ret = i2c_add_adapter(__cil_tmp19);
  }
#line 405
  if (ret != 0) {
#line 406
    goto err;
  } else {

  }
  {
#line 409
  bus->reg0 = (u32 )i;
#line 412
  __cil_tmp20 = (u32 )i;
#line 412
  bus->force_bit = intel_gpio_create(dev_priv, __cil_tmp20);
#line 390
  i = i + 1;
  }
  ldv_37753: ;
#line 390
  if (i <= 7) {
#line 391
    goto ldv_37752;
  } else {
#line 393
    goto ldv_37754;
  }
  ldv_37754: 
  {
#line 415
  __cil_tmp21 = dev_priv->dev;
#line 415
  intel_i2c_reset(__cil_tmp21);
  }
#line 417
  return (0);
  err: ;
#line 420
  goto ldv_37757;
  ldv_37756: 
  {
#line 421
  __cil_tmp22 = (unsigned long )i;
#line 421
  __cil_tmp23 = dev_priv->gmbus;
#line 421
  bus___0 = __cil_tmp23 + __cil_tmp22;
#line 422
  __cil_tmp24 = & bus___0->adapter;
#line 422
  i2c_del_adapter(__cil_tmp24);
  }
  ldv_37757: 
#line 420
  i = i - 1;
#line 420
  if (i != 0) {
#line 421
    goto ldv_37756;
  } else {
#line 423
    goto ldv_37758;
  }
  ldv_37758: 
  {
#line 424
  __cil_tmp25 = dev_priv->gmbus;
#line 424
  __cil_tmp26 = (void const   *)__cil_tmp25;
#line 424
  kfree(__cil_tmp26);
#line 425
  dev_priv->gmbus = (struct intel_gmbus *)0;
  }
#line 426
  return (ret);
}
}
#line 429 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
void intel_gmbus_set_speed(struct i2c_adapter *adapter , int speed ) 
{ struct intel_gmbus *bus ;
  struct intel_gmbus *tmp ;
  int __cil_tmp5 ;
  u32 __cil_tmp6 ;
  u32 __cil_tmp7 ;
  unsigned int __cil_tmp8 ;

  {
  {
#line 431
  tmp = to_intel_gmbus(adapter);
#line 431
  bus = tmp;
#line 439
  __cil_tmp5 = speed << 8;
#line 439
  __cil_tmp6 = (u32 )__cil_tmp5;
#line 439
  __cil_tmp7 = bus->reg0;
#line 439
  __cil_tmp8 = __cil_tmp7 & 4294966527U;
#line 439
  bus->reg0 = __cil_tmp8 | __cil_tmp6;
  }
#line 440
  return;
}
}
#line 442 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
void intel_gmbus_force_bit(struct i2c_adapter *adapter , bool force_bit ) 
{ struct intel_gmbus *bus ;
  struct intel_gmbus *tmp ;
  struct drm_i915_private *dev_priv ;
  struct i2c_adapter *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct i2c_adapter *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  void *__cil_tmp10 ;
  u32 __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  struct i2c_adapter *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct i2c_adapter *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct i2c_adapter *__cil_tmp17 ;
  struct i2c_adapter *__cil_tmp18 ;
  void const   *__cil_tmp19 ;

  {
  {
#line 444
  tmp = to_intel_gmbus(adapter);
#line 444
  bus = tmp;
  }
#line 446
  if ((int )force_bit) {
    {
#line 447
    __cil_tmp6 = (struct i2c_adapter *)0;
#line 447
    __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 447
    __cil_tmp8 = bus->force_bit;
#line 447
    __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 447
    if (__cil_tmp9 == __cil_tmp7) {
      {
#line 448
      __cil_tmp10 = adapter->algo_data;
#line 448
      dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 449
      __cil_tmp11 = bus->reg0;
#line 449
      __cil_tmp12 = __cil_tmp11 & 255U;
#line 449
      bus->force_bit = intel_gpio_create(dev_priv, __cil_tmp12);
      }
    } else {
      {
#line 453
      __cil_tmp13 = (struct i2c_adapter *)0;
#line 453
      __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 453
      __cil_tmp15 = bus->force_bit;
#line 453
      __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 453
      if (__cil_tmp16 != __cil_tmp14) {
        {
#line 454
        __cil_tmp17 = bus->force_bit;
#line 454
        i2c_del_adapter(__cil_tmp17);
#line 455
        __cil_tmp18 = bus->force_bit;
#line 455
        __cil_tmp19 = (void const   *)__cil_tmp18;
#line 455
        kfree(__cil_tmp19);
#line 456
        bus->force_bit = (struct i2c_adapter *)0;
        }
      } else {

      }
      }
    }
    }
  } else {

  }
#line 458
  return;
}
}
#line 461 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_i2c.c.p"
void intel_teardown_gmbus(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  int i ;
  struct intel_gmbus *bus ;
  void *__cil_tmp5 ;
  struct intel_gmbus *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct intel_gmbus *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct intel_gmbus *__cil_tmp11 ;
  struct i2c_adapter *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct i2c_adapter *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct i2c_adapter *__cil_tmp16 ;
  struct i2c_adapter *__cil_tmp17 ;
  void const   *__cil_tmp18 ;
  struct i2c_adapter *__cil_tmp19 ;
  struct intel_gmbus *__cil_tmp20 ;
  void const   *__cil_tmp21 ;

  {
#line 463
  __cil_tmp5 = dev->dev_private;
#line 463
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
  {
#line 466
  __cil_tmp6 = (struct intel_gmbus *)0;
#line 466
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 466
  __cil_tmp8 = dev_priv->gmbus;
#line 466
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 466
  if (__cil_tmp9 == __cil_tmp7) {
#line 467
    return;
  } else {

  }
  }
#line 469
  i = 0;
#line 469
  goto ldv_37777;
  ldv_37776: 
#line 470
  __cil_tmp10 = (unsigned long )i;
#line 470
  __cil_tmp11 = dev_priv->gmbus;
#line 470
  bus = __cil_tmp11 + __cil_tmp10;
  {
#line 471
  __cil_tmp12 = (struct i2c_adapter *)0;
#line 471
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 471
  __cil_tmp14 = bus->force_bit;
#line 471
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 471
  if (__cil_tmp15 != __cil_tmp13) {
    {
#line 472
    __cil_tmp16 = bus->force_bit;
#line 472
    i2c_del_adapter(__cil_tmp16);
#line 473
    __cil_tmp17 = bus->force_bit;
#line 473
    __cil_tmp18 = (void const   *)__cil_tmp17;
#line 473
    kfree(__cil_tmp18);
    }
  } else {

  }
  }
  {
#line 475
  __cil_tmp19 = & bus->adapter;
#line 475
  i2c_del_adapter(__cil_tmp19);
#line 469
  i = i + 1;
  }
  ldv_37777: ;
#line 469
  if (i <= 7) {
#line 470
    goto ldv_37776;
  } else {
#line 472
    goto ldv_37778;
  }
  ldv_37778: 
  {
#line 478
  __cil_tmp20 = dev_priv->gmbus;
#line 478
  __cil_tmp21 = (void const   *)__cil_tmp20;
#line 478
  kfree(__cil_tmp21);
#line 479
  dev_priv->gmbus = (struct intel_gmbus *)0;
  }
#line 480
  return;
}
}
#line 62 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/string_64.h"
extern char *strcpy(char * , char const   * ) ;
#line 893 "include/linux/fb.h"
__inline static struct apertures_struct *alloc_apertures(unsigned int max_num ) 
{ struct apertures_struct *a ;
  void *tmp ;
  unsigned long __cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  struct apertures_struct *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;

  {
  {
#line 894
  __cil_tmp4 = (unsigned long )max_num;
#line 894
  __cil_tmp5 = __cil_tmp4 * 16UL;
#line 894
  __cil_tmp6 = __cil_tmp5 + 8UL;
#line 894
  tmp = kzalloc(__cil_tmp6, 208U);
#line 894
  a = (struct apertures_struct *)tmp;
  }
  {
#line 896
  __cil_tmp7 = (struct apertures_struct *)0;
#line 896
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 896
  __cil_tmp9 = (unsigned long )a;
#line 896
  if (__cil_tmp9 == __cil_tmp8) {
#line 897
    return ((struct apertures_struct *)0);
  } else {

  }
  }
#line 898
  a->count = max_num;
#line 899
  return (a);
}
}
#line 983
extern void cfb_fillrect(struct fb_info * , struct fb_fillrect  const  * ) ;
#line 984
extern void cfb_copyarea(struct fb_info * , struct fb_copyarea  const  * ) ;
#line 985
extern void cfb_imageblit(struct fb_info * , struct fb_image  const  * ) ;
#line 999
extern int unregister_framebuffer(struct fb_info * ) ;
#line 1068
extern struct fb_info *framebuffer_alloc(size_t  , struct device * ) ;
#line 1069
extern void framebuffer_release(struct fb_info * ) ;
#line 1129
extern int fb_alloc_cmap(struct fb_cmap * , int  , int  ) ;
#line 1131
extern void fb_dealloc_cmap(struct fb_cmap * ) ;
#line 39 "include/linux/vga_switcheroo.h"
extern void vga_switcheroo_client_fb_set(struct pci_dev * , struct fb_info * ) ;
#line 90 "include/drm/drm_fb_helper.h"
extern int drm_fb_helper_init(struct drm_device * , struct drm_fb_helper * , int  ,
                              int  ) ;
#line 93
extern void drm_fb_helper_fini(struct drm_fb_helper * ) ;
#line 94
extern int drm_fb_helper_blank(int  , struct fb_info * ) ;
#line 95
extern int drm_fb_helper_pan_display(struct fb_var_screeninfo * , struct fb_info * ) ;
#line 97
extern int drm_fb_helper_set_par(struct fb_info * ) ;
#line 98
extern int drm_fb_helper_check_var(struct fb_var_screeninfo * , struct fb_info * ) ;
#line 107
extern bool drm_fb_helper_restore_fbdev_mode(struct drm_fb_helper * ) ;
#line 109
extern void drm_fb_helper_fill_var(struct fb_info * , struct drm_fb_helper * , uint32_t  ,
                                   uint32_t  ) ;
#line 111
extern void drm_fb_helper_fill_fix(struct fb_info * , uint32_t  , uint32_t  ) ;
#line 114
extern int drm_fb_helper_setcmap(struct fb_cmap * , struct fb_info * ) ;
#line 116
extern int drm_fb_helper_hotplug_event(struct drm_fb_helper * ) ;
#line 117
extern bool drm_fb_helper_initial_config(struct drm_fb_helper * , int  ) ;
#line 118
extern int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper * ) ;
#line 119
extern int drm_fb_helper_debug_enter(struct fb_info * ) ;
#line 120
extern int drm_fb_helper_debug_leave(struct fb_info * ) ;
#line 55 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
static struct fb_ops intelfb_ops  = 
#line 55 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
     {& __this_module, (int (*)(struct fb_info * , int  ))0, (int (*)(struct fb_info * ,
                                                                    int  ))0, (ssize_t (*)(struct fb_info * ,
                                                                                           char * ,
                                                                                           size_t  ,
                                                                                           loff_t * ))0,
    (ssize_t (*)(struct fb_info * , char const   * , size_t  , loff_t * ))0, & drm_fb_helper_check_var,
    & drm_fb_helper_set_par, (int (*)(unsigned int  , unsigned int  , unsigned int  ,
                                      unsigned int  , unsigned int  , struct fb_info * ))0,
    & drm_fb_helper_setcmap, & drm_fb_helper_blank, & drm_fb_helper_pan_display, & cfb_fillrect,
    & cfb_copyarea, & cfb_imageblit, (int (*)(struct fb_info * , struct fb_cursor * ))0,
    (void (*)(struct fb_info * , int  ))0, (int (*)(struct fb_info * ))0, (int (*)(struct fb_info * ,
                                                                                   unsigned int  ,
                                                                                   unsigned long  ))0,
    (int (*)(struct fb_info * , unsigned int  , unsigned long  ))0, (int (*)(struct fb_info * ,
                                                                             struct vm_area_struct * ))0,
    (void (*)(struct fb_info * , struct fb_blit_caps * , struct fb_var_screeninfo * ))0,
    (void (*)(struct fb_info * ))0, & drm_fb_helper_debug_enter, & drm_fb_helper_debug_leave};
#line 69 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
static int intelfb_create(struct intel_fbdev *ifbdev , struct drm_fb_helper_surface_size *sizes ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct fb_info *info ;
  struct drm_framebuffer *fb ;
  struct drm_mode_fb_cmd mode_cmd ;
  struct drm_i915_gem_object *obj ;
  struct device *device ;
  int size ;
  int ret ;
  void *tmp ;
  void *__cil_tmp13 ;
  struct pci_dev *__cil_tmp14 ;
  u32 __cil_tmp15 ;
  __u32 __cil_tmp16 ;
  __u32 __cil_tmp17 ;
  __u32 __cil_tmp18 ;
  __u32 __cil_tmp19 ;
  __u32 __cil_tmp20 ;
  int __cil_tmp21 ;
  size_t __cil_tmp22 ;
  struct drm_i915_gem_object *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct mutex *__cil_tmp26 ;
  struct intel_ring_buffer *__cil_tmp27 ;
  struct fb_info *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  struct intel_framebuffer *__cil_tmp31 ;
  char (*__cil_tmp32)[16U] ;
  char *__cil_tmp33 ;
  struct fb_cmap *__cil_tmp34 ;
  struct apertures_struct *__cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  struct apertures_struct *__cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  struct apertures_struct *__cil_tmp39 ;
  struct apertures_struct *__cil_tmp40 ;
  struct intel_gtt  const  *__cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  uint32_t __cil_tmp44 ;
  resource_size_t __cil_tmp45 ;
  resource_size_t __cil_tmp46 ;
  resource_size_t __cil_tmp47 ;
  uint32_t __cil_tmp48 ;
  unsigned long __cil_tmp49 ;
  struct drm_agp_head *__cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  resource_size_t __cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  char *__cil_tmp55 ;
  unsigned long __cil_tmp56 ;
  char *__cil_tmp57 ;
  unsigned long __cil_tmp58 ;
  unsigned int __cil_tmp59 ;
  unsigned int __cil_tmp60 ;
  struct drm_fb_helper *__cil_tmp61 ;
  u32 __cil_tmp62 ;
  u32 __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  unsigned int __cil_tmp65 ;
  uint32_t __cil_tmp66 ;
  struct mutex *__cil_tmp67 ;
  struct pci_dev *__cil_tmp68 ;
  struct drm_gem_object *__cil_tmp69 ;
  struct mutex *__cil_tmp70 ;

  {
#line 72
  dev = ifbdev->helper.dev;
#line 73
  __cil_tmp13 = dev->dev_private;
#line 73
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 78
  __cil_tmp14 = dev->pdev;
#line 78
  device = & __cil_tmp14->dev;
  {
#line 82
  __cil_tmp15 = sizes->surface_bpp;
#line 82
  if (__cil_tmp15 == 24U) {
#line 83
    sizes->surface_bpp = 32U;
  } else {

  }
  }
  {
#line 85
  mode_cmd.width = sizes->surface_width;
#line 86
  mode_cmd.height = sizes->surface_height;
#line 88
  mode_cmd.bpp = sizes->surface_bpp;
#line 89
  __cil_tmp16 = mode_cmd.bpp + 7U;
#line 89
  __cil_tmp17 = __cil_tmp16 / 8U;
#line 89
  __cil_tmp18 = mode_cmd.width * __cil_tmp17;
#line 89
  __cil_tmp19 = __cil_tmp18 + 63U;
#line 89
  mode_cmd.pitch = __cil_tmp19 & 4294967232U;
#line 90
  mode_cmd.depth = sizes->surface_depth;
#line 92
  __cil_tmp20 = mode_cmd.pitch * mode_cmd.height;
#line 92
  size = (int )__cil_tmp20;
#line 93
  __cil_tmp21 = size + 4095;
#line 93
  size = __cil_tmp21 & -4096;
#line 94
  __cil_tmp22 = (size_t )size;
#line 94
  obj = i915_gem_alloc_object(dev, __cil_tmp22);
  }
  {
#line 95
  __cil_tmp23 = (struct drm_i915_gem_object *)0;
#line 95
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 95
  __cil_tmp25 = (unsigned long )obj;
#line 95
  if (__cil_tmp25 == __cil_tmp24) {
    {
#line 96
    drm_err("intelfb_create", "failed to allocate framebuffer\n");
#line 97
    ret = -12;
    }
#line 98
    goto out;
  } else {

  }
  }
  {
#line 101
  __cil_tmp26 = & dev->struct_mutex;
#line 101
  mutex_lock_nested(__cil_tmp26, 0U);
#line 104
  __cil_tmp27 = (struct intel_ring_buffer *)0;
#line 104
  ret = intel_pin_and_fence_fb_obj(dev, obj, __cil_tmp27);
  }
#line 105
  if (ret != 0) {
    {
#line 106
    drm_err("intelfb_create", "failed to pin fb: %d\n", ret);
    }
#line 107
    goto out_unref;
  } else {

  }
  {
#line 110
  info = framebuffer_alloc(0UL, device);
  }
  {
#line 111
  __cil_tmp28 = (struct fb_info *)0;
#line 111
  __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 111
  __cil_tmp30 = (unsigned long )info;
#line 111
  if (__cil_tmp30 == __cil_tmp29) {
#line 112
    ret = -12;
#line 113
    goto out_unpin;
  } else {

  }
  }
  {
#line 116
  info->par = (void *)ifbdev;
#line 118
  __cil_tmp31 = & ifbdev->ifb;
#line 118
  ret = intel_framebuffer_init(dev, __cil_tmp31, & mode_cmd, obj);
  }
#line 119
  if (ret != 0) {
#line 120
    goto out_unpin;
  } else {

  }
  {
#line 122
  fb = & ifbdev->ifb.base;
#line 124
  ifbdev->helper.fb = fb;
#line 125
  ifbdev->helper.fbdev = info;
#line 127
  __cil_tmp32 = & info->fix.id;
#line 127
  __cil_tmp33 = (char *)__cil_tmp32;
#line 127
  strcpy(__cil_tmp33, "inteldrmfb");
#line 129
  info->flags = 2097153;
#line 130
  info->fbops = & intelfb_ops;
#line 132
  __cil_tmp34 = & info->cmap;
#line 132
  ret = fb_alloc_cmap(__cil_tmp34, 256, 0);
  }
#line 133
  if (ret != 0) {
#line 134
    ret = -12;
#line 135
    goto out_unpin;
  } else {

  }
  {
#line 138
  info->apertures = alloc_apertures(1U);
  }
  {
#line 139
  __cil_tmp35 = (struct apertures_struct *)0;
#line 139
  __cil_tmp36 = (unsigned long )__cil_tmp35;
#line 139
  __cil_tmp37 = info->apertures;
#line 139
  __cil_tmp38 = (unsigned long )__cil_tmp37;
#line 139
  if (__cil_tmp38 == __cil_tmp36) {
#line 140
    ret = -12;
#line 141
    goto out_unpin;
  } else {

  }
  }
  {
#line 143
  __cil_tmp39 = info->apertures;
#line 143
  __cil_tmp39->ranges[0].base = dev->mode_config.fb_base;
#line 144
  __cil_tmp40 = info->apertures;
#line 144
  __cil_tmp41 = dev_priv->mm.gtt;
#line 144
  __cil_tmp42 = __cil_tmp41->gtt_mappable_entries;
#line 144
  __cil_tmp43 = __cil_tmp42 << 12;
#line 144
  __cil_tmp40->ranges[0].size = (resource_size_t )__cil_tmp43;
#line 147
  __cil_tmp44 = obj->gtt_offset;
#line 147
  __cil_tmp45 = (resource_size_t )__cil_tmp44;
#line 147
  __cil_tmp46 = dev->mode_config.fb_base;
#line 147
  __cil_tmp47 = __cil_tmp46 + __cil_tmp45;
#line 147
  info->fix.smem_start = (unsigned long )__cil_tmp47;
#line 148
  info->fix.smem_len = (__u32 )size;
#line 150
  __cil_tmp48 = obj->gtt_offset;
#line 150
  __cil_tmp49 = (unsigned long )__cil_tmp48;
#line 150
  __cil_tmp50 = dev->agp;
#line 150
  __cil_tmp51 = __cil_tmp50->base;
#line 150
  __cil_tmp52 = __cil_tmp51 + __cil_tmp49;
#line 150
  __cil_tmp53 = (resource_size_t )__cil_tmp52;
#line 150
  __cil_tmp54 = (unsigned long )size;
#line 150
  tmp = ioremap_wc(__cil_tmp53, __cil_tmp54);
#line 150
  info->screen_base = (char *)tmp;
  }
  {
#line 151
  __cil_tmp55 = (char *)0;
#line 151
  __cil_tmp56 = (unsigned long )__cil_tmp55;
#line 151
  __cil_tmp57 = info->screen_base;
#line 151
  __cil_tmp58 = (unsigned long )__cil_tmp57;
#line 151
  if (__cil_tmp58 == __cil_tmp56) {
#line 152
    ret = -28;
#line 153
    goto out_unpin;
  } else {

  }
  }
  {
#line 155
  info->screen_size = (unsigned long )size;
#line 159
  __cil_tmp59 = fb->pitch;
#line 159
  __cil_tmp60 = fb->depth;
#line 159
  drm_fb_helper_fill_fix(info, __cil_tmp59, __cil_tmp60);
#line 160
  __cil_tmp61 = & ifbdev->helper;
#line 160
  __cil_tmp62 = sizes->fb_width;
#line 160
  __cil_tmp63 = sizes->fb_height;
#line 160
  drm_fb_helper_fill_var(info, __cil_tmp61, __cil_tmp62, __cil_tmp63);
#line 162
  info->pixmap.size = 65536U;
#line 163
  info->pixmap.buf_align = 8U;
#line 164
  info->pixmap.access_align = 32U;
#line 165
  info->pixmap.flags = 2U;
#line 166
  info->pixmap.scan_align = 1U;
#line 168
  __cil_tmp64 = fb->width;
#line 168
  __cil_tmp65 = fb->height;
#line 168
  __cil_tmp66 = obj->gtt_offset;
#line 168
  drm_ut_debug_printk(4U, "drm", "intelfb_create", "allocated %dx%d fb: 0x%08x, bo %p\n",
                      __cil_tmp64, __cil_tmp65, __cil_tmp66, obj);
#line 173
  __cil_tmp67 = & dev->struct_mutex;
#line 173
  mutex_unlock(__cil_tmp67);
#line 174
  __cil_tmp68 = dev->pdev;
#line 174
  vga_switcheroo_client_fb_set(__cil_tmp68, info);
  }
#line 175
  return (0);
  out_unpin: 
  {
#line 178
  i915_gem_object_unpin(obj);
  }
  out_unref: 
  {
#line 180
  __cil_tmp69 = & obj->base;
#line 180
  drm_gem_object_unreference(__cil_tmp69);
#line 181
  __cil_tmp70 = & dev->struct_mutex;
#line 181
  mutex_unlock(__cil_tmp70);
  }
  out: ;
#line 183
  return (ret);
}
}
#line 186 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
static int intel_fb_find_or_create_single(struct drm_fb_helper *helper , struct drm_fb_helper_surface_size *sizes ) 
{ struct intel_fbdev *ifbdev ;
  int new_fb ;
  int ret ;
  struct drm_framebuffer *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct drm_framebuffer *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;

  {
#line 189
  ifbdev = (struct intel_fbdev *)helper;
#line 190
  new_fb = 0;
  {
#line 193
  __cil_tmp6 = (struct drm_framebuffer *)0;
#line 193
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 193
  __cil_tmp8 = helper->fb;
#line 193
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 193
  if (__cil_tmp9 == __cil_tmp7) {
    {
#line 194
    ret = intelfb_create(ifbdev, sizes);
    }
#line 195
    if (ret != 0) {
#line 196
      return (ret);
    } else {

    }
#line 197
    new_fb = 1;
  } else {

  }
  }
#line 199
  return (new_fb);
}
}
#line 202 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
static struct drm_fb_helper_funcs intel_fb_helper_funcs  =    {& intel_crtc_fb_gamma_set, & intel_crtc_fb_gamma_get, & intel_fb_find_or_create_single};
#line 208 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
static void intel_fbdev_destroy(struct drm_device *dev , struct intel_fbdev *ifbdev ) 
{ struct fb_info *info ;
  struct intel_framebuffer *ifb ;
  struct fb_info *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  struct fb_info *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  char *__cil_tmp9 ;
  void volatile   *__cil_tmp10 ;
  __u32 __cil_tmp11 ;
  struct fb_cmap *__cil_tmp12 ;
  struct drm_fb_helper *__cil_tmp13 ;
  struct drm_framebuffer *__cil_tmp14 ;
  struct drm_i915_gem_object *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct drm_i915_gem_object *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  struct drm_i915_gem_object *__cil_tmp19 ;
  struct drm_gem_object *__cil_tmp20 ;

  {
#line 212
  ifb = & ifbdev->ifb;
  {
#line 214
  __cil_tmp5 = (struct fb_info *)0;
#line 214
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 214
  __cil_tmp7 = ifbdev->helper.fbdev;
#line 214
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 214
  if (__cil_tmp8 != __cil_tmp6) {
    {
#line 215
    info = ifbdev->helper.fbdev;
#line 216
    unregister_framebuffer(info);
#line 217
    __cil_tmp9 = info->screen_base;
#line 217
    __cil_tmp10 = (void volatile   *)__cil_tmp9;
#line 217
    iounmap(__cil_tmp10);
    }
    {
#line 218
    __cil_tmp11 = info->cmap.len;
#line 218
    if (__cil_tmp11 != 0U) {
      {
#line 219
      __cil_tmp12 = & info->cmap;
#line 219
      fb_dealloc_cmap(__cil_tmp12);
      }
    } else {

    }
    }
    {
#line 220
    framebuffer_release(info);
    }
  } else {

  }
  }
  {
#line 223
  __cil_tmp13 = & ifbdev->helper;
#line 223
  drm_fb_helper_fini(__cil_tmp13);
#line 225
  __cil_tmp14 = & ifb->base;
#line 225
  drm_framebuffer_cleanup(__cil_tmp14);
  }
  {
#line 226
  __cil_tmp15 = (struct drm_i915_gem_object *)0;
#line 226
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 226
  __cil_tmp17 = ifb->obj;
#line 226
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 226
  if (__cil_tmp18 != __cil_tmp16) {
    {
#line 227
    __cil_tmp19 = ifb->obj;
#line 227
    __cil_tmp20 = & __cil_tmp19->base;
#line 227
    drm_gem_object_unreference_unlocked(__cil_tmp20);
#line 228
    ifb->obj = (struct drm_i915_gem_object *)0;
    }
  } else {

  }
  }
#line 230
  return;
}
}
#line 232 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
int intel_fbdev_init(struct drm_device *dev ) 
{ struct intel_fbdev *ifbdev ;
  drm_i915_private_t *dev_priv ;
  int ret ;
  void *tmp ;
  void *__cil_tmp6 ;
  struct intel_fbdev *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct drm_fb_helper *__cil_tmp10 ;
  int __cil_tmp11 ;
  void const   *__cil_tmp12 ;
  struct drm_fb_helper *__cil_tmp13 ;
  struct drm_fb_helper *__cil_tmp14 ;

  {
  {
#line 235
  __cil_tmp6 = dev->dev_private;
#line 235
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
#line 238
  tmp = kzalloc(304UL, 208U);
#line 238
  ifbdev = (struct intel_fbdev *)tmp;
  }
  {
#line 239
  __cil_tmp7 = (struct intel_fbdev *)0;
#line 239
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 239
  __cil_tmp9 = (unsigned long )ifbdev;
#line 239
  if (__cil_tmp9 == __cil_tmp8) {
#line 240
    return (-12);
  } else {

  }
  }
  {
#line 242
  dev_priv->fbdev = ifbdev;
#line 243
  ifbdev->helper.funcs = & intel_fb_helper_funcs;
#line 245
  __cil_tmp10 = & ifbdev->helper;
#line 245
  __cil_tmp11 = dev_priv->num_pipe;
#line 245
  ret = drm_fb_helper_init(dev, __cil_tmp10, __cil_tmp11, 4);
  }
#line 248
  if (ret != 0) {
    {
#line 249
    __cil_tmp12 = (void const   *)ifbdev;
#line 249
    kfree(__cil_tmp12);
    }
#line 250
    return (ret);
  } else {

  }
  {
#line 253
  __cil_tmp13 = & ifbdev->helper;
#line 253
  drm_fb_helper_single_add_all_connectors(__cil_tmp13);
#line 254
  __cil_tmp14 = & ifbdev->helper;
#line 254
  drm_fb_helper_initial_config(__cil_tmp14, 32);
  }
#line 255
  return (0);
}
}
#line 258 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
void intel_fbdev_fini(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  void *__cil_tmp3 ;
  struct intel_fbdev *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct intel_fbdev *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct intel_fbdev *__cil_tmp8 ;
  struct intel_fbdev *__cil_tmp9 ;
  void const   *__cil_tmp10 ;

  {
#line 260
  __cil_tmp3 = dev->dev_private;
#line 260
  dev_priv = (drm_i915_private_t *)__cil_tmp3;
  {
#line 261
  __cil_tmp4 = (struct intel_fbdev *)0;
#line 261
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 261
  __cil_tmp6 = dev_priv->fbdev;
#line 261
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 261
  if (__cil_tmp7 == __cil_tmp5) {
#line 262
    return;
  } else {

  }
  }
  {
#line 264
  __cil_tmp8 = dev_priv->fbdev;
#line 264
  intel_fbdev_destroy(dev, __cil_tmp8);
#line 265
  __cil_tmp9 = dev_priv->fbdev;
#line 265
  __cil_tmp10 = (void const   *)__cil_tmp9;
#line 265
  kfree(__cil_tmp10);
#line 266
  dev_priv->fbdev = (struct intel_fbdev *)0;
  }
#line 267
  return;
}
}
#line 270 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
void intel_fb_output_poll_changed(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  void *__cil_tmp3 ;
  struct intel_fbdev *__cil_tmp4 ;
  struct drm_fb_helper *__cil_tmp5 ;

  {
  {
#line 272
  __cil_tmp3 = dev->dev_private;
#line 272
  dev_priv = (drm_i915_private_t *)__cil_tmp3;
#line 273
  __cil_tmp4 = dev_priv->fbdev;
#line 273
  __cil_tmp5 = & __cil_tmp4->helper;
#line 273
  drm_fb_helper_hotplug_event(__cil_tmp5);
  }
#line 274
  return;
}
}
#line 276 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_fb.c.p"
void intel_fb_restore_mode(struct drm_device *dev ) 
{ int ret ;
  drm_i915_private_t *dev_priv ;
  bool tmp ;
  void *__cil_tmp5 ;
  struct intel_fbdev *__cil_tmp6 ;
  struct drm_fb_helper *__cil_tmp7 ;

  {
  {
#line 279
  __cil_tmp5 = dev->dev_private;
#line 279
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 281
  __cil_tmp6 = dev_priv->fbdev;
#line 281
  __cil_tmp7 = & __cil_tmp6->helper;
#line 281
  tmp = drm_fb_helper_restore_fbdev_mode(__cil_tmp7);
#line 281
  ret = (int )tmp;
  }
#line 282
  if (ret != 0) {
    {
#line 283
    drm_ut_debug_printk(1U, "drm", "intel_fb_restore_mode", "failed to restore crtc mode\n");
    }
  } else {

  }
#line 284
  return;
}
}
#line 64 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/string_64.h"
extern int strcmp(char const   * , char const   * ) ;
#line 684 "include/drm/drm_crtc.h"
extern struct drm_display_mode *drm_mode_create(struct drm_device * ) ;
#line 695
extern int drm_mode_vrefresh(struct drm_display_mode  const  * ) ;
#line 727
extern int drm_mode_create_tv_properties(struct drm_device * , int  , char ** ) ;
#line 106 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static u32 const   filter_table[206U]  = 
#line 106 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
  {      (u32 const   )2973773824U,      (u32 const   )773862656U,      (u32 const   )889204256U,      (u32 const   )805351744U, 
        (u32 const   )899723616U,      (u32 const   )767569536U,      (u32 const   )2973774976U,      (u32 const   )2975870976U, 
        (u32 const   )782251584U,      (u32 const   )872426880U,      (u32 const   )805351712U,      (u32 const   )920695136U, 
        (u32 const   )757083888U,      (u32 const   )2971677568U,      (u32 const   )2975870976U,      (u32 const   )791689088U, 
        (u32 const   )855649472U,      (u32 const   )805351680U,      (u32 const   )941666656U,      (u32 const   )746598224U, 
        (u32 const   )2969580192U,      (u32 const   )2975870976U,      (u32 const   )797980864U,      (u32 const   )840969248U, 
        (u32 const   )805351648U,      (u32 const   )964735328U,      (u32 const   )734015424U,      (u32 const   )2967482816U, 
        (u32 const   )2975870976U,      (u32 const   )804272672U,      (u32 const   )828386144U,      (u32 const   )2954932416U, 
        (u32 const   )987804000U,      (u32 const   )721426448U,      (u32 const   )2965385504U,      (u32 const   )2973806624U, 
        (u32 const   )405289888U,      (u32 const   )817900160U,      (u32 const   )2954932384U,      (u32 const   )1012969792U, 
        (u32 const   )706746424U,      (u32 const   )2963288192U,      (u32 const   )2971709472U,      (u32 const   )406338848U, 
        (u32 const   )809511360U,      (u32 const   )2957029504U,      (u32 const   )1038135552U,      (u32 const   )694163528U, 
        (u32 const   )2961190912U,      (u32 const   )2969612352U,      (u32 const   )407387840U,      (u32 const   )2956994816U, 
        (u32 const   )2957029472U,      (u32 const   )1065398464U,      (u32 const   )679483480U,      (u32 const   )2959126656U, 
        (u32 const   )2963320928U,      (u32 const   )408954912U,      (u32 const   )2963286048U,      (u32 const   )45152U, 
        (u32 const   )2973773824U,      (u32 const   )773862656U,      (u32 const   )889204256U,      (u32 const   )805351744U, 
        (u32 const   )899723616U,      (u32 const   )767569536U,      (u32 const   )2973774976U,      (u32 const   )2975870976U, 
        (u32 const   )782251584U,      (u32 const   )872426880U,      (u32 const   )805351712U,      (u32 const   )920695136U, 
        (u32 const   )757083888U,      (u32 const   )2971677568U,      (u32 const   )2975870976U,      (u32 const   )791689088U, 
        (u32 const   )855649472U,      (u32 const   )805351680U,      (u32 const   )941666656U,      (u32 const   )746598224U, 
        (u32 const   )2969580192U,      (u32 const   )2975870976U,      (u32 const   )797980864U,      (u32 const   )840969248U, 
        (u32 const   )805351648U,      (u32 const   )964735328U,      (u32 const   )734015424U,      (u32 const   )2967482816U, 
        (u32 const   )2975870976U,      (u32 const   )804272672U,      (u32 const   )828386144U,      (u32 const   )2954932416U, 
        (u32 const   )987804000U,      (u32 const   )721426448U,      (u32 const   )2965385504U,      (u32 const   )2973806624U, 
        (u32 const   )405289888U,      (u32 const   )817900160U,      (u32 const   )2954932384U,      (u32 const   )1012969792U, 
        (u32 const   )706746424U,      (u32 const   )2963288192U,      (u32 const   )2971709472U,      (u32 const   )406338848U, 
        (u32 const   )809511360U,      (u32 const   )2957029504U,      (u32 const   )1038135552U,      (u32 const   )694163528U, 
        (u32 const   )2961190912U,      (u32 const   )2969612352U,      (u32 const   )407387840U,      (u32 const   )2956994816U, 
        (u32 const   )2957029472U,      (u32 const   )1065398464U,      (u32 const   )679483480U,      (u32 const   )2959126656U, 
        (u32 const   )2963320928U,      (u32 const   )408954912U,      (u32 const   )2963286048U,      (u32 const   )45152U, 
        (u32 const   )910176256U,      (u32 const   )754986176U,      (u32 const   )805320256U,      (u32 const   )754988736U, 
        (u32 const   )901786816U,      (u32 const   )926953472U,      (u32 const   )746597696U,      (u32 const   )805320000U, 
        (u32 const   )763377600U,      (u32 const   )885009472U,      (u32 const   )943730688U,      (u32 const   )734014976U, 
        (u32 const   )805319744U,      (u32 const   )773863616U,      (u32 const   )872426368U,      (u32 const   )964702208U, 
        (u32 const   )725626432U,      (u32 const   )805319552U,      (u32 const   )778058240U,      (u32 const   )859843328U, 
        (u32 const   )981479488U,      (u32 const   )713043616U,      (u32 const   )809513728U,      (u32 const   )784350016U, 
        (u32 const   )847260224U,      (u32 const   )1006645312U,      (u32 const   )704655040U,      (u32 const   )813707840U, 
        (u32 const   )784350336U,      (u32 const   )838871488U,      (u32 const   )1027616896U,      (u32 const   )692072192U, 
        (u32 const   )813707712U,      (u32 const   )790642112U,      (u32 const   )830482688U,      (u32 const   )1048588480U, 
        (u32 const   )679489344U,      (u32 const   )817901888U,      (u32 const   )790642496U,      (u32 const   )826288192U, 
        (u32 const   )671101184U,      (u32 const   )671100672U,      (u32 const   )12544U,      (u32 const   )910176256U, 
        (u32 const   )754986176U,      (u32 const   )805320256U,      (u32 const   )754988736U,      (u32 const   )901786816U, 
        (u32 const   )926953472U,      (u32 const   )746597696U,      (u32 const   )805320000U,      (u32 const   )763377600U, 
        (u32 const   )885009472U,      (u32 const   )943730688U,      (u32 const   )734014976U,      (u32 const   )805319744U, 
        (u32 const   )773863616U,      (u32 const   )872426368U,      (u32 const   )964702208U,      (u32 const   )725626432U, 
        (u32 const   )805319552U,      (u32 const   )778058240U,      (u32 const   )859843328U,      (u32 const   )981479488U, 
        (u32 const   )713043616U,      (u32 const   )809513728U,      (u32 const   )784350016U,      (u32 const   )847260224U, 
        (u32 const   )1006645312U,      (u32 const   )704655040U,      (u32 const   )813707840U,      (u32 const   )784350336U, 
        (u32 const   )838871488U,      (u32 const   )1027616896U,      (u32 const   )692072192U,      (u32 const   )813707712U, 
        (u32 const   )790642112U,      (u32 const   )830482688U,      (u32 const   )1048588480U,      (u32 const   )679489344U, 
        (u32 const   )817901888U,      (u32 const   )790642496U,      (u32 const   )826288192U,      (u32 const   )671101184U, 
        (u32 const   )671100672U,      (u32 const   )12544U};
#line 228 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  ntsc_m_csc_composite  = 
#line 228
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )260U, (u16 )1843U, (u16 )1325U, (u16 )1479U,
    (u16 )512U, (u16 )832U, (u16 )780U, (u16 )1744U, (u16 )512U};
#line 234 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  ntsc_m_levels_composite  =    {225, 267, 113};
#line 238 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  ntsc_m_csc_svideo  = 
#line 238
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )307U, (u16 )1898U, (u16 )1380U, (u16 )781U,
    (u16 )512U, (u16 )890U, (u16 )829U, (u16 )1782U, (u16 )512U};
#line 244 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  ntsc_m_levels_svideo  =    {266, 316, 133};
#line 248 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  ntsc_j_csc_composite  = 
#line 248
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )281U, (u16 )1868U, (u16 )1350U, (u16 )1516U,
    (u16 )512U, (u16 )858U, (u16 )802U, (u16 )1761U, (u16 )512U};
#line 254 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  ntsc_j_levels_composite  =    {225, 225, 113};
#line 258 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  ntsc_j_csc_svideo  = 
#line 258
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )332U, (u16 )1928U, (u16 )1409U, (u16 )802U,
    (u16 )512U, (u16 )921U, (u16 )854U, (u16 )1802U, (u16 )512U};
#line 264 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  ntsc_j_levels_svideo  =    {266, 266, 133};
#line 268 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  pal_csc_composite  = 
#line 268
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )275U, (u16 )1861U, (u16 )1343U, (u16 )1505U,
    (u16 )512U, (u16 )851U, (u16 )796U, (u16 )1756U, (u16 )512U};
#line 274 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  pal_levels_composite  =    {237, 237, 118};
#line 278 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  pal_csc_svideo  = 
#line 278
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )325U, (u16 )1920U, (u16 )1401U, (u16 )796U,
    (u16 )512U, (u16 )912U, (u16 )847U, (u16 )1797U, (u16 )512U};
#line 284 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  pal_levels_svideo  =    {280, 280, 139};
#line 288 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  pal_m_csc_composite  = 
#line 288
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )260U, (u16 )1843U, (u16 )1325U, (u16 )1479U,
    (u16 )512U, (u16 )832U, (u16 )780U, (u16 )1744U, (u16 )512U};
#line 294 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  pal_m_levels_composite  =    {225, 267, 113};
#line 298 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  pal_m_csc_svideo  = 
#line 298
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )307U, (u16 )1898U, (u16 )1380U, (u16 )781U,
    (u16 )512U, (u16 )890U, (u16 )829U, (u16 )1782U, (u16 )512U};
#line 304 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  pal_m_levels_svideo  =    {266, 316, 133};
#line 308 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  pal_n_csc_composite  = 
#line 308
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )260U, (u16 )1843U, (u16 )1325U, (u16 )1479U,
    (u16 )512U, (u16 )832U, (u16 )780U, (u16 )1744U, (u16 )512U};
#line 314 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  pal_n_levels_composite  =    {225, 267, 118};
#line 318 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  pal_n_csc_svideo  = 
#line 318
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )307U, (u16 )1898U, (u16 )1380U, (u16 )781U,
    (u16 )512U, (u16 )890U, (u16 )829U, (u16 )1782U, (u16 )512U};
#line 324 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  pal_n_levels_svideo  =    {266, 316, 139};
#line 331 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  sdtv_csc_yprpb  = 
#line 331
     {(u16 )818U, (u16 )301U, (u16 )2003U, (u16 )325U, (u16 )1369U, (u16 )851U, (u16 )256U,
    (u16 )512U, (u16 )256U, (u16 )941U, (u16 )1869U, (u16 )512U};
#line 343 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct color_conversion  const  hdtv_csc_yprpb  = 
#line 343
     {(u16 )1459U, (u16 )366U, (u16 )1832U, (u16 )325U, (u16 )2005U, (u16 )907U, (u16 )256U,
    (u16 )512U, (u16 )256U, (u16 )977U, (u16 )1724U, (u16 )512U};
#line 355 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct video_levels  const  component_levels  =    {279, 279, 0};
#line 424 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct tv_mode  const  tv_modes[15U]  = 
#line 424
  {      {"NTSC-M", 108000, 29970, 786432U, 64, 836, 124, 857, (bool )0, (bool )0, (bool )0,
      6, 7, 6, (bool )1, 0, 1, 18, 20, 21, 240, (bool )1, 72, 34, 9, 240, 10, 240,
      9, 240, 10, 240, 27456, 0, 135, 20800, 0, 16777216U, (bool )0, & ntsc_m_levels_composite,
      & ntsc_m_levels_svideo, & ntsc_m_csc_composite, & ntsc_m_csc_svideo, (u32 const   *)(& filter_table),
      0}, 
        {"NTSC-443", 108000, 29970, 786432U, 64, 836, 124, 857, (bool )0, (bool )0, (bool )0,
      6, 7, 6, (bool )1, 0, 1, 18, 20, 21, 240, (bool )1, 72, 34, 9, 240, 10, 240,
      9, 240, 10, 240, 27456, 525, 168, 4093, 310, 50331648U, (bool )0, & ntsc_m_levels_composite,
      & ntsc_m_levels_svideo, & ntsc_m_csc_composite, & ntsc_m_csc_svideo, (u32 const   *)(& filter_table),
      0}, 
        {"NTSC-J", 108000, 29970, 786432U, 64, 836, 124, 857, (bool )0, (bool )0, (bool )0,
      6, 7, 6, (bool )1, 0, 1, 18, 20, 21, 240, (bool )1, 72, 34, 9, 240, 10, 240,
      9, 240, 10, 240, 27456, 0, 135, 20800, 0, 16777216U, (bool )0, & ntsc_j_levels_composite,
      & ntsc_j_levels_svideo, & ntsc_j_csc_composite, & ntsc_j_csc_svideo, (u32 const   *)(& filter_table),
      0}, 
        {"PAL-M", 108000, 29970, 786432U, 64, 836, 124, 857, (bool )0, (bool )0, (bool )0,
      6, 7, 6, (bool )1, 0, 1, 18, 20, 21, 240, (bool )1, 72, 34, 9, 240, 10, 240,
      9, 240, 10, 240, 27456, 0, 135, 16704, 0, 33554432U, (bool )1, & pal_m_levels_composite,
      & pal_m_levels_svideo, & pal_m_csc_composite, & pal_m_csc_svideo, (u32 const   *)(& filter_table),
      0}, 
        {"PAL-N", 108000, 25000, 786432U, 64, 844, 128, 863, (bool )0, (bool )0, (bool )0,
      6, 7, 6, (bool )1, 0, 1, 18, 24, 25, 286, (bool )1, 73, 34, 8, 285, 8, 286,
      9, 286, 9, 285, 27648, 625, 135, 23578, 134, 33554432U, (bool )1, & pal_n_levels_composite,
      & pal_n_levels_svideo, & pal_n_csc_composite, & pal_n_csc_svideo, (u32 const   *)(& filter_table),
      0}, 
        {"PAL", 108000, 25000, 786432U, 64, 844, 142, 863, (bool )0, (bool )0, (bool )0,
      5, 6, 5, (bool )1, 0, 1, 15, 24, 25, 286, (bool )1, 73, 32, 8, 285, 8, 286,
      9, 286, 9, 285, 27648, 625, 168, 4122, 67, 33554432U, (bool )1, & pal_levels_composite,
      & pal_levels_svideo, & pal_csc_composite, & pal_csc_svideo, (u32 const   *)(& filter_table),
      0}, 
        {"480p@59.94Hz", 107520, 59940, 0U, 64, 842, 122, 857, (bool )1, (bool )0, (bool )1,
      12, 12, 12, (bool )0, 0, 0, 0, 44, 44, 479, (bool )0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0, (struct video_levels  const  *)0,
      (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"480p@60Hz", 107520, 60000, 0U, 64, 842, 122, 856, (bool )1, (bool )0, (bool )1,
      12, 12, 12, (bool )0, 0, 0, 0, 44, 44, 479, (bool )0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0, (struct video_levels  const  *)0,
      (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"576p", 107520, 50000, 0U, 64, 859, 139, 863, (bool )1, (bool )0, (bool )1,
      10, 10, 10, (bool )0, 0, 0, 0, 48, 48, 575, (bool )0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0, (struct video_levels  const  *)0,
      (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"720p@60Hz", 148800, 60000, 262144U, 80, 1580, 300, 1649, (bool )1, (bool )1,
      (bool )1, 10, 10, 10, (bool )0, 0, 0, 0, 29, 29, 719, (bool )0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0,
      (struct video_levels  const  *)0, (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"720p@59.94Hz", 148800, 59940, 262144U, 80, 1580, 300, 1651, (bool )1, (bool )1,
      (bool )1, 10, 10, 10, (bool )0, 0, 0, 0, 29, 29, 719, (bool )0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0,
      (struct video_levels  const  *)0, (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"720p@50Hz", 148800, 50000, 262144U, 80, 1580, 300, 1979, (bool )1, (bool )1,
      (bool )1, 10, 10, 10, (bool )0, 0, 0, 0, 29, 29, 719, (bool )0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0,
      (struct video_levels  const  *)0, (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 800}, 
        {"1080i@50Hz", 148800, 25000, 262144U, 88, 2155, 235, 2639, (bool )0, (bool )1,
      (bool )1, 4, 5, 10, (bool )1, 4, 4, 10, 21, 22, 539, (bool )0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0,
      (struct video_levels  const  *)0, (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"1080i@60Hz", 148800, 30000, 262144U, 88, 2155, 235, 2199, (bool )0, (bool )1,
      (bool )1, 4, 5, 10, (bool )1, 4, 4, 10, 21, 22, 539, (bool )0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0,
      (struct video_levels  const  *)0, (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}, 
        {"1080i@59.94Hz", 148800, 29970, 262144U, 88, 2155, 235, 2201, (bool )0, (bool )1,
      (bool )1, 4, 5, 10, (bool )1, 4, 4, 10, 21, 22, 539, (bool )0, 0, 0, 0, 0, 0,
      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0U, (_Bool)0, (struct video_levels  const  *)0,
      (struct video_levels  const  *)0, (struct color_conversion  const  *)0, (struct color_conversion  const  *)0,
      (u32 const   *)(& filter_table), 0}};
#line 909 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder ) 
{ struct drm_encoder  const  *__mptr ;

  {
#line 911
  __mptr = (struct drm_encoder  const  *)encoder;
#line 911
  return ((struct intel_tv *)__mptr);
}
}
#line 914 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct intel_tv *intel_attached_tv(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 916
  tmp = intel_attached_encoder(connector);
#line 916
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 916
  return ((struct intel_tv *)__mptr);
}
}
#line 922 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static void intel_tv_dpms(struct drm_encoder *encoder , int mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 tmp ;
  u32 tmp___0 ;
  void *__cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;

  {
#line 924
  dev = encoder->dev;
#line 925
  __cil_tmp7 = dev->dev_private;
#line 925
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
#line 928
  if (mode == 0) {
#line 928
    goto case_0;
  } else
#line 931
  if (mode == 1) {
#line 931
    goto case_1;
  } else
#line 932
  if (mode == 2) {
#line 932
    goto case_2;
  } else
#line 933
  if (mode == 3) {
#line 933
    goto case_3;
  } else
#line 927
  if (0) {
    case_0: 
    {
#line 929
    tmp = i915_read32___11(dev_priv, 425984U);
#line 929
    __cil_tmp8 = tmp | 2147483648U;
#line 929
    i915_write32___9(dev_priv, 425984U, __cil_tmp8);
    }
#line 930
    goto ldv_37792;
    case_1: ;
    case_2: ;
    case_3: 
    {
#line 934
    tmp___0 = i915_read32___11(dev_priv, 425984U);
#line 934
    __cil_tmp9 = tmp___0 & 2147483647U;
#line 934
    i915_write32___9(dev_priv, 425984U, __cil_tmp9);
    }
#line 935
    goto ldv_37792;
  } else {

  }
  ldv_37792: ;
#line 938
  return;
}
}
#line 940 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct tv_mode  const  *intel_tv_mode_lookup(char const   *tv_format ) 
{ int i ;
  struct tv_mode  const  *tv_mode ;
  int tmp ;
  unsigned long __cil_tmp5 ;
  struct tv_mode  const  *__cil_tmp6 ;
  char const   *__cil_tmp7 ;
  char const   *__cil_tmp8 ;
  unsigned int __cil_tmp9 ;

  {
#line 944
  i = 0;
#line 944
  goto ldv_37802;
  ldv_37801: 
  {
#line 945
  __cil_tmp5 = (unsigned long )i;
#line 945
  __cil_tmp6 = (struct tv_mode  const  *)(& tv_modes);
#line 945
  tv_mode = __cil_tmp6 + __cil_tmp5;
#line 947
  __cil_tmp7 = tv_mode->name;
#line 947
  __cil_tmp8 = (char const   *)__cil_tmp7;
#line 947
  tmp = strcmp(tv_format, __cil_tmp8);
  }
#line 947
  if (tmp == 0) {
#line 948
    return (tv_mode);
  } else {

  }
#line 944
  i = i + 1;
  ldv_37802: ;
  {
#line 944
  __cil_tmp9 = (unsigned int )i;
#line 944
  if (__cil_tmp9 <= 14U) {
#line 945
    goto ldv_37801;
  } else {
#line 947
    goto ldv_37803;
  }
  }
  ldv_37803: ;
#line 950
  return ((struct tv_mode  const  *)0);
}
}
#line 954 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct tv_mode  const  *intel_tv_mode_find(struct intel_tv *intel_tv ) 
{ struct tv_mode  const  *tmp ;
  char const   *__cil_tmp3 ;

  {
  {
#line 956
  __cil_tmp3 = intel_tv->tv_format;
#line 956
  tmp = intel_tv_mode_lookup(__cil_tmp3);
  }
#line 956
  return (tmp);
}
}
#line 960 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static enum drm_mode_status intel_tv_mode_valid(struct drm_connector *connector ,
                                                struct drm_display_mode *mode ) 
{ struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct tv_mode  const  *tv_mode ;
  struct tv_mode  const  *tmp___0 ;
  long ret ;
  int __x___0 ;
  int tmp___2 ;
  int tmp___3 ;
  struct tv_mode  const  *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_display_mode  const  *__cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;

  {
  {
#line 963
  tmp = intel_attached_tv(connector);
#line 963
  intel_tv = tmp;
#line 964
  tmp___0 = intel_tv_mode_find(intel_tv);
#line 964
  tv_mode = tmp___0;
  }
  {
#line 967
  __cil_tmp11 = (struct tv_mode  const  *)0;
#line 967
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 967
  __cil_tmp13 = (unsigned long )tv_mode;
#line 967
  if (__cil_tmp13 != __cil_tmp12) {
    {
#line 967
    __cil_tmp14 = (struct drm_display_mode  const  *)mode;
#line 967
    tmp___2 = drm_mode_vrefresh(__cil_tmp14);
#line 967
    __cil_tmp15 = tmp___2 * -1000;
#line 967
    __cil_tmp16 = tv_mode->refresh;
#line 967
    __cil_tmp17 = (int )__cil_tmp16;
#line 967
    __x___0 = __cil_tmp17 + __cil_tmp15;
    }
#line 967
    if (__x___0 < 0) {
#line 967
      tmp___3 = - __x___0;
    } else {
#line 967
      tmp___3 = __x___0;
    }
#line 967
    ret = (long )tmp___3;
#line 967
    if (ret <= 999L) {
#line 969
      return ((enum drm_mode_status )0);
    } else {

    }
  } else {

  }
  }
#line 971
  return ((enum drm_mode_status )17);
}
}
#line 976 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static bool intel_tv_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_mode_config *drm_config ;
  struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct tv_mode  const  *tv_mode ;
  struct tv_mode  const  *tmp___0 ;
  struct drm_encoder *other_encoder ;
  struct list_head  const  *__mptr ;
  struct list_head  const  *__mptr___0 ;
  struct tv_mode  const  *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct list_head *__cil_tmp16 ;
  struct drm_encoder *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  struct drm_crtc *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_crtc *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  struct list_head *__cil_tmp24 ;
  struct drm_encoder *__cil_tmp25 ;
  struct list_head *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  struct list_head *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  int __cil_tmp30 ;

  {
  {
#line 979
  dev = encoder->dev;
#line 980
  drm_config = & dev->mode_config;
#line 981
  tmp = enc_to_intel_tv(encoder);
#line 981
  intel_tv = tmp;
#line 982
  tmp___0 = intel_tv_mode_find(intel_tv);
#line 982
  tv_mode = tmp___0;
  }
  {
#line 985
  __cil_tmp13 = (struct tv_mode  const  *)0;
#line 985
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 985
  __cil_tmp15 = (unsigned long )tv_mode;
#line 985
  if (__cil_tmp15 == __cil_tmp14) {
#line 986
    return ((bool )0);
  } else {

  }
  }
#line 989
  __cil_tmp16 = drm_config->encoder_list.next;
#line 989
  __mptr = (struct list_head  const  *)__cil_tmp16;
#line 989
  __cil_tmp17 = (struct drm_encoder *)__mptr;
#line 989
  other_encoder = __cil_tmp17 + 1152921504606846968UL;
#line 989
  goto ldv_37832;
  ldv_37831: ;
  {
#line 990
  __cil_tmp18 = (unsigned long )encoder;
#line 990
  __cil_tmp19 = (unsigned long )other_encoder;
#line 990
  if (__cil_tmp19 != __cil_tmp18) {
    {
#line 990
    __cil_tmp20 = encoder->crtc;
#line 990
    __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 990
    __cil_tmp22 = other_encoder->crtc;
#line 990
    __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 990
    if (__cil_tmp23 == __cil_tmp21) {
#line 992
      return ((bool )0);
    } else {

    }
    }
  } else {

  }
  }
#line 989
  __cil_tmp24 = other_encoder->head.next;
#line 989
  __mptr___0 = (struct list_head  const  *)__cil_tmp24;
#line 989
  __cil_tmp25 = (struct drm_encoder *)__mptr___0;
#line 989
  other_encoder = __cil_tmp25 + 1152921504606846968UL;
  ldv_37832: ;
  {
#line 989
  __cil_tmp26 = & drm_config->encoder_list;
#line 989
  __cil_tmp27 = (unsigned long )__cil_tmp26;
#line 989
  __cil_tmp28 = & other_encoder->head;
#line 989
  __cil_tmp29 = (unsigned long )__cil_tmp28;
#line 989
  if (__cil_tmp29 != __cil_tmp27) {
#line 990
    goto ldv_37831;
  } else {
#line 992
    goto ldv_37833;
  }
  }
  ldv_37833: 
#line 995
  __cil_tmp30 = tv_mode->clock;
#line 995
  adjusted_mode->clock = (int )__cil_tmp30;
#line 996
  return ((bool )1);
}
}
#line 1000 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static void intel_tv_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                              struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct drm_crtc *crtc ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct tv_mode  const  *tv_mode ;
  struct tv_mode  const  *tmp___0 ;
  u32 tv_ctl ;
  u32 hctl1 ;
  u32 hctl2 ;
  u32 hctl3 ;
  u32 vctl1 ;
  u32 vctl2 ;
  u32 vctl3 ;
  u32 vctl4 ;
  u32 vctl5 ;
  u32 vctl6 ;
  u32 vctl7 ;
  u32 scctl1 ;
  u32 scctl2 ;
  u32 scctl3 ;
  int i ;
  int j ;
  struct video_levels  const  *video_levels ;
  struct color_conversion  const  *color_conversion ;
  bool burst_ena ;
  int pipe ;
  int pipeconf_reg ;
  int dspcntr_reg ;
  int pipeconf ;
  u32 tmp___1 ;
  int dspcntr ;
  u32 tmp___2 ;
  int dspbase_reg ;
  int xpos ;
  int ypos ;
  unsigned int xsize ;
  unsigned int ysize ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  int tmp___5 ;
  int tmp___6 ;
  int tmp___7 ;
  int tmp___8 ;
  u32 tmp___9 ;
  void *__cil_tmp51 ;
  enum pipe __cil_tmp52 ;
  struct tv_mode  const  *__cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  unsigned long __cil_tmp55 ;
  int __cil_tmp56 ;
  int __cil_tmp57 ;
  int __cil_tmp58 ;
  int __cil_tmp59 ;
  struct video_levels  const  *__cil_tmp60 ;
  struct color_conversion  const  *__cil_tmp61 ;
  bool __cil_tmp62 ;
  bool __cil_tmp63 ;
  struct video_levels  const  *__cil_tmp64 ;
  struct color_conversion  const  *__cil_tmp65 ;
  bool __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  int __cil_tmp70 ;
  int __cil_tmp71 ;
  int __cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  int __cil_tmp75 ;
  int __cil_tmp76 ;
  int __cil_tmp77 ;
  int __cil_tmp78 ;
  int __cil_tmp79 ;
  int __cil_tmp80 ;
  int __cil_tmp81 ;
  int __cil_tmp82 ;
  int __cil_tmp83 ;
  int __cil_tmp84 ;
  int __cil_tmp85 ;
  int __cil_tmp86 ;
  int __cil_tmp87 ;
  int __cil_tmp88 ;
  int __cil_tmp89 ;
  int __cil_tmp90 ;
  int __cil_tmp91 ;
  int __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  int __cil_tmp95 ;
  int __cil_tmp96 ;
  int __cil_tmp97 ;
  int __cil_tmp98 ;
  int __cil_tmp99 ;
  int __cil_tmp100 ;
  int __cil_tmp101 ;
  int __cil_tmp102 ;
  int __cil_tmp103 ;
  int __cil_tmp104 ;
  int __cil_tmp105 ;
  int __cil_tmp106 ;
  int __cil_tmp107 ;
  int __cil_tmp108 ;
  int __cil_tmp109 ;
  int __cil_tmp110 ;
  int __cil_tmp111 ;
  int __cil_tmp112 ;
  int __cil_tmp113 ;
  int __cil_tmp114 ;
  bool __cil_tmp115 ;
  int __cil_tmp116 ;
  int __cil_tmp117 ;
  int __cil_tmp118 ;
  int __cil_tmp119 ;
  int __cil_tmp120 ;
  int __cil_tmp121 ;
  int __cil_tmp122 ;
  int __cil_tmp123 ;
  int __cil_tmp124 ;
  int __cil_tmp125 ;
  int __cil_tmp126 ;
  int __cil_tmp127 ;
  int __cil_tmp128 ;
  int __cil_tmp129 ;
  int __cil_tmp130 ;
  int __cil_tmp131 ;
  int __cil_tmp132 ;
  int __cil_tmp133 ;
  int __cil_tmp134 ;
  int __cil_tmp135 ;
  int __cil_tmp136 ;
  int __cil_tmp137 ;
  int __cil_tmp138 ;
  int __cil_tmp139 ;
  enum pipe __cil_tmp140 ;
  unsigned int __cil_tmp141 ;
  u32 __cil_tmp142 ;
  u32 __cil_tmp143 ;
  bool __cil_tmp144 ;
  bool __cil_tmp145 ;
  bool __cil_tmp146 ;
  int __cil_tmp147 ;
  int __cil_tmp148 ;
  int __cil_tmp149 ;
  int __cil_tmp150 ;
  int __cil_tmp151 ;
  int __cil_tmp152 ;
  u32 __cil_tmp153 ;
  u32 __cil_tmp154 ;
  struct video_levels  const  *__cil_tmp155 ;
  unsigned long __cil_tmp156 ;
  unsigned long __cil_tmp157 ;
  int __cil_tmp158 ;
  int __cil_tmp159 ;
  u32 __cil_tmp160 ;
  int __cil_tmp161 ;
  u32 __cil_tmp162 ;
  int __cil_tmp163 ;
  int __cil_tmp164 ;
  int __cil_tmp165 ;
  int __cil_tmp166 ;
  int __cil_tmp167 ;
  int __cil_tmp168 ;
  int __cil_tmp169 ;
  int __cil_tmp170 ;
  int __cil_tmp171 ;
  int __cil_tmp172 ;
  int __cil_tmp173 ;
  int __cil_tmp174 ;
  int __cil_tmp175 ;
  struct color_conversion  const  *__cil_tmp176 ;
  unsigned long __cil_tmp177 ;
  unsigned long __cil_tmp178 ;
  u16 __cil_tmp179 ;
  int __cil_tmp180 ;
  u16 __cil_tmp181 ;
  int __cil_tmp182 ;
  int __cil_tmp183 ;
  int __cil_tmp184 ;
  u32 __cil_tmp185 ;
  u16 __cil_tmp186 ;
  int __cil_tmp187 ;
  u16 __cil_tmp188 ;
  int __cil_tmp189 ;
  int __cil_tmp190 ;
  int __cil_tmp191 ;
  u32 __cil_tmp192 ;
  u16 __cil_tmp193 ;
  int __cil_tmp194 ;
  u16 __cil_tmp195 ;
  int __cil_tmp196 ;
  int __cil_tmp197 ;
  int __cil_tmp198 ;
  u32 __cil_tmp199 ;
  u16 __cil_tmp200 ;
  int __cil_tmp201 ;
  u16 __cil_tmp202 ;
  int __cil_tmp203 ;
  int __cil_tmp204 ;
  int __cil_tmp205 ;
  u32 __cil_tmp206 ;
  u16 __cil_tmp207 ;
  int __cil_tmp208 ;
  u16 __cil_tmp209 ;
  int __cil_tmp210 ;
  int __cil_tmp211 ;
  int __cil_tmp212 ;
  u32 __cil_tmp213 ;
  u16 __cil_tmp214 ;
  int __cil_tmp215 ;
  u16 __cil_tmp216 ;
  int __cil_tmp217 ;
  int __cil_tmp218 ;
  int __cil_tmp219 ;
  u32 __cil_tmp220 ;
  void *__cil_tmp221 ;
  struct drm_i915_private *__cil_tmp222 ;
  struct intel_device_info  const  *__cil_tmp223 ;
  u8 __cil_tmp224 ;
  unsigned char __cil_tmp225 ;
  unsigned int __cil_tmp226 ;
  struct video_levels  const  *__cil_tmp227 ;
  unsigned long __cil_tmp228 ;
  unsigned long __cil_tmp229 ;
  int __cil_tmp230 ;
  int __cil_tmp231 ;
  int __cil_tmp232 ;
  int __cil_tmp233 ;
  int __cil_tmp234 ;
  int __cil_tmp235 ;
  u32 __cil_tmp236 ;
  int __cil_tmp237 ;
  enum plane __cil_tmp238 ;
  unsigned int __cil_tmp239 ;
  unsigned int __cil_tmp240 ;
  unsigned int __cil_tmp241 ;
  u32 __cil_tmp242 ;
  u32 __cil_tmp243 ;
  enum plane __cil_tmp244 ;
  unsigned int __cil_tmp245 ;
  unsigned int __cil_tmp246 ;
  unsigned int __cil_tmp247 ;
  u32 __cil_tmp248 ;
  u32 __cil_tmp249 ;
  unsigned int __cil_tmp250 ;
  u32 __cil_tmp251 ;
  u32 __cil_tmp252 ;
  void *__cil_tmp253 ;
  struct drm_i915_private *__cil_tmp254 ;
  struct intel_device_info  const  *__cil_tmp255 ;
  u8 __cil_tmp256 ;
  unsigned char __cil_tmp257 ;
  unsigned int __cil_tmp258 ;
  enum pipe __cil_tmp259 ;
  int __cil_tmp260 ;
  u32 __cil_tmp261 ;
  u32 __cil_tmp262 ;
  unsigned int __cil_tmp263 ;
  enum pipe __cil_tmp264 ;
  int __cil_tmp265 ;
  int __cil_tmp266 ;
  int __cil_tmp267 ;
  int __cil_tmp268 ;
  int __cil_tmp269 ;
  int __cil_tmp270 ;
  bool __cil_tmp271 ;
  int __cil_tmp272 ;
  int __cil_tmp273 ;
  int __cil_tmp274 ;
  int __cil_tmp275 ;
  int __cil_tmp276 ;
  int __cil_tmp277 ;
  int __cil_tmp278 ;
  int __cil_tmp279 ;
  int __cil_tmp280 ;
  int __cil_tmp281 ;
  int __cil_tmp282 ;
  int __cil_tmp283 ;
  unsigned int __cil_tmp284 ;
  int __cil_tmp285 ;
  int __cil_tmp286 ;
  int __cil_tmp287 ;
  unsigned int __cil_tmp288 ;
  int __cil_tmp289 ;
  int __cil_tmp290 ;
  u32 __cil_tmp291 ;
  unsigned int __cil_tmp292 ;
  unsigned int __cil_tmp293 ;
  u32 __cil_tmp294 ;
  u32 __cil_tmp295 ;
  u32 __cil_tmp296 ;
  u32 __cil_tmp297 ;
  u32 __cil_tmp298 ;
  u32 __cil_tmp299 ;
  int __cil_tmp300 ;
  int __cil_tmp301 ;
  u32 __cil_tmp302 ;
  unsigned long __cil_tmp303 ;
  u32 const   *__cil_tmp304 ;
  u32 const   *__cil_tmp305 ;
  u32 __cil_tmp306 ;
  u32 __cil_tmp307 ;
  int __cil_tmp308 ;
  int __cil_tmp309 ;
  u32 __cil_tmp310 ;
  unsigned long __cil_tmp311 ;
  u32 const   *__cil_tmp312 ;
  u32 const   *__cil_tmp313 ;
  u32 __cil_tmp314 ;
  u32 __cil_tmp315 ;
  int __cil_tmp316 ;
  int __cil_tmp317 ;
  u32 __cil_tmp318 ;
  unsigned long __cil_tmp319 ;
  u32 const   *__cil_tmp320 ;
  u32 const   *__cil_tmp321 ;
  u32 __cil_tmp322 ;
  u32 __cil_tmp323 ;
  int __cil_tmp324 ;
  int __cil_tmp325 ;
  u32 __cil_tmp326 ;
  unsigned long __cil_tmp327 ;
  u32 const   *__cil_tmp328 ;
  u32 const   *__cil_tmp329 ;
  u32 __cil_tmp330 ;
  u32 __cil_tmp331 ;
  unsigned int __cil_tmp332 ;

  {
  {
#line 1003
  dev = encoder->dev;
#line 1004
  __cil_tmp51 = dev->dev_private;
#line 1004
  dev_priv = (struct drm_i915_private *)__cil_tmp51;
#line 1005
  crtc = encoder->crtc;
#line 1006
  __mptr = (struct drm_crtc  const  *)crtc;
#line 1006
  intel_crtc = (struct intel_crtc *)__mptr;
#line 1007
  tmp = enc_to_intel_tv(encoder);
#line 1007
  intel_tv = tmp;
#line 1008
  tmp___0 = intel_tv_mode_find(intel_tv);
#line 1008
  tv_mode = tmp___0;
#line 1017
  __cil_tmp52 = intel_crtc->pipe;
#line 1017
  pipe = (int )__cil_tmp52;
  }
  {
#line 1019
  __cil_tmp53 = (struct tv_mode  const  *)0;
#line 1019
  __cil_tmp54 = (unsigned long )__cil_tmp53;
#line 1019
  __cil_tmp55 = (unsigned long )tv_mode;
#line 1019
  if (__cil_tmp55 == __cil_tmp54) {
#line 1020
    return;
  } else {

  }
  }
  {
#line 1022
  tv_ctl = i915_read32___11(dev_priv, 425984U);
#line 1023
  tv_ctl = tv_ctl & 4047U;
  }
  {
#line 1027
  __cil_tmp56 = intel_tv->type;
#line 1027
  if (__cil_tmp56 == 0) {
#line 1027
    goto case_0;
  } else {
    {
#line 1028
    __cil_tmp57 = intel_tv->type;
#line 1028
    if (__cil_tmp57 == 5) {
#line 1028
      goto case_5;
    } else {
      {
#line 1034
      __cil_tmp58 = intel_tv->type;
#line 1034
      if (__cil_tmp58 == 8) {
#line 1034
        goto case_8;
      } else {
        {
#line 1043
        __cil_tmp59 = intel_tv->type;
#line 1043
        if (__cil_tmp59 == 6) {
#line 1043
          goto case_6;
        } else {
#line 1026
          goto switch_default;
#line 1025
          if (0) {
            switch_default: ;
            case_0: ;
            case_5: 
#line 1029
            tv_ctl = tv_ctl;
#line 1030
            __cil_tmp60 = tv_mode->composite_levels;
#line 1030
            video_levels = (struct video_levels  const  *)__cil_tmp60;
#line 1031
            __cil_tmp61 = tv_mode->composite_color;
#line 1031
            color_conversion = (struct color_conversion  const  *)__cil_tmp61;
#line 1032
            __cil_tmp62 = tv_mode->burst_ena;
#line 1032
            burst_ena = (bool )__cil_tmp62;
#line 1033
            goto ldv_37870;
            case_8: 
#line 1035
            tv_ctl = tv_ctl | 536870912U;
#line 1036
            video_levels = & component_levels;
            {
#line 1037
            __cil_tmp63 = tv_mode->burst_ena;
#line 1037
            if ((int )__cil_tmp63) {
#line 1038
              color_conversion = & sdtv_csc_yprpb;
            } else {
#line 1040
              color_conversion = & hdtv_csc_yprpb;
            }
            }
#line 1041
            burst_ena = (bool )0;
#line 1042
            goto ldv_37870;
            case_6: 
#line 1044
            tv_ctl = tv_ctl | 268435456U;
#line 1045
            __cil_tmp64 = tv_mode->svideo_levels;
#line 1045
            video_levels = (struct video_levels  const  *)__cil_tmp64;
#line 1046
            __cil_tmp65 = tv_mode->svideo_color;
#line 1046
            color_conversion = (struct color_conversion  const  *)__cil_tmp65;
#line 1047
            __cil_tmp66 = tv_mode->burst_ena;
#line 1047
            burst_ena = (bool )__cil_tmp66;
#line 1048
            goto ldv_37870;
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_37870: 
#line 1050
  __cil_tmp67 = tv_mode->htotal;
#line 1050
  __cil_tmp68 = (int )__cil_tmp67;
#line 1050
  __cil_tmp69 = tv_mode->hsync_end;
#line 1050
  __cil_tmp70 = __cil_tmp69 << 16;
#line 1050
  __cil_tmp71 = (int )__cil_tmp70;
#line 1050
  __cil_tmp72 = __cil_tmp71 | __cil_tmp68;
#line 1050
  hctl1 = (u32 )__cil_tmp72;
#line 1053
  __cil_tmp73 = tv_mode->hburst_len;
#line 1053
  __cil_tmp74 = (int )__cil_tmp73;
#line 1053
  __cil_tmp75 = tv_mode->hburst_start;
#line 1053
  __cil_tmp76 = __cil_tmp75 << 16;
#line 1053
  __cil_tmp77 = (int )__cil_tmp76;
#line 1053
  __cil_tmp78 = __cil_tmp77 | __cil_tmp74;
#line 1053
  hctl2 = (u32 )__cil_tmp78;
#line 1056
  if ((int )burst_ena) {
#line 1057
    hctl2 = hctl2 | 2147483648U;
  } else {

  }
#line 1059
  __cil_tmp79 = tv_mode->hblank_end;
#line 1059
  __cil_tmp80 = __cil_tmp79 << 16;
#line 1059
  __cil_tmp81 = (int )__cil_tmp80;
#line 1059
  __cil_tmp82 = tv_mode->hblank_start;
#line 1059
  __cil_tmp83 = (int )__cil_tmp82;
#line 1059
  __cil_tmp84 = __cil_tmp83 | __cil_tmp81;
#line 1059
  hctl3 = (u32 )__cil_tmp84;
#line 1062
  __cil_tmp85 = tv_mode->vi_end_f2;
#line 1062
  __cil_tmp86 = (int )__cil_tmp85;
#line 1062
  __cil_tmp87 = tv_mode->vi_end_f1;
#line 1062
  __cil_tmp88 = __cil_tmp87 << 8;
#line 1062
  __cil_tmp89 = (int )__cil_tmp88;
#line 1062
  __cil_tmp90 = tv_mode->nbr_end;
#line 1062
  __cil_tmp91 = __cil_tmp90 << 16;
#line 1062
  __cil_tmp92 = (int )__cil_tmp91;
#line 1062
  __cil_tmp93 = __cil_tmp92 | __cil_tmp89;
#line 1062
  __cil_tmp94 = __cil_tmp93 | __cil_tmp86;
#line 1062
  vctl1 = (u32 )__cil_tmp94;
#line 1066
  __cil_tmp95 = tv_mode->vsync_start_f2;
#line 1066
  __cil_tmp96 = (int )__cil_tmp95;
#line 1066
  __cil_tmp97 = tv_mode->vsync_start_f1;
#line 1066
  __cil_tmp98 = __cil_tmp97 << 8;
#line 1066
  __cil_tmp99 = (int )__cil_tmp98;
#line 1066
  __cil_tmp100 = tv_mode->vsync_len;
#line 1066
  __cil_tmp101 = __cil_tmp100 << 16;
#line 1066
  __cil_tmp102 = (int )__cil_tmp101;
#line 1066
  __cil_tmp103 = __cil_tmp102 | __cil_tmp99;
#line 1066
  __cil_tmp104 = __cil_tmp103 | __cil_tmp96;
#line 1066
  vctl2 = (u32 )__cil_tmp104;
#line 1070
  __cil_tmp105 = tv_mode->veq_start_f2;
#line 1070
  __cil_tmp106 = (int )__cil_tmp105;
#line 1070
  __cil_tmp107 = tv_mode->veq_start_f1;
#line 1070
  __cil_tmp108 = __cil_tmp107 << 8;
#line 1070
  __cil_tmp109 = (int )__cil_tmp108;
#line 1070
  __cil_tmp110 = tv_mode->veq_len;
#line 1070
  __cil_tmp111 = __cil_tmp110 << 16;
#line 1070
  __cil_tmp112 = (int )__cil_tmp111;
#line 1070
  __cil_tmp113 = __cil_tmp112 | __cil_tmp109;
#line 1070
  __cil_tmp114 = __cil_tmp113 | __cil_tmp106;
#line 1070
  vctl3 = (u32 )__cil_tmp114;
  {
#line 1074
  __cil_tmp115 = tv_mode->veq_ena;
#line 1074
  if ((int )__cil_tmp115) {
#line 1075
    vctl3 = vctl3 | 2147483648U;
  } else {

  }
  }
#line 1077
  __cil_tmp116 = tv_mode->vburst_end_f1;
#line 1077
  __cil_tmp117 = (int )__cil_tmp116;
#line 1077
  __cil_tmp118 = tv_mode->vburst_start_f1;
#line 1077
  __cil_tmp119 = __cil_tmp118 << 16;
#line 1077
  __cil_tmp120 = (int )__cil_tmp119;
#line 1077
  __cil_tmp121 = __cil_tmp120 | __cil_tmp117;
#line 1077
  vctl4 = (u32 )__cil_tmp121;
#line 1080
  __cil_tmp122 = tv_mode->vburst_end_f2;
#line 1080
  __cil_tmp123 = (int )__cil_tmp122;
#line 1080
  __cil_tmp124 = tv_mode->vburst_start_f2;
#line 1080
  __cil_tmp125 = __cil_tmp124 << 16;
#line 1080
  __cil_tmp126 = (int )__cil_tmp125;
#line 1080
  __cil_tmp127 = __cil_tmp126 | __cil_tmp123;
#line 1080
  vctl5 = (u32 )__cil_tmp127;
#line 1083
  __cil_tmp128 = tv_mode->vburst_end_f3;
#line 1083
  __cil_tmp129 = (int )__cil_tmp128;
#line 1083
  __cil_tmp130 = tv_mode->vburst_start_f3;
#line 1083
  __cil_tmp131 = __cil_tmp130 << 16;
#line 1083
  __cil_tmp132 = (int )__cil_tmp131;
#line 1083
  __cil_tmp133 = __cil_tmp132 | __cil_tmp129;
#line 1083
  vctl6 = (u32 )__cil_tmp133;
#line 1086
  __cil_tmp134 = tv_mode->vburst_end_f4;
#line 1086
  __cil_tmp135 = (int )__cil_tmp134;
#line 1086
  __cil_tmp136 = tv_mode->vburst_start_f4;
#line 1086
  __cil_tmp137 = __cil_tmp136 << 16;
#line 1086
  __cil_tmp138 = (int )__cil_tmp137;
#line 1086
  __cil_tmp139 = __cil_tmp138 | __cil_tmp135;
#line 1086
  vctl7 = (u32 )__cil_tmp139;
  {
#line 1089
  __cil_tmp140 = intel_crtc->pipe;
#line 1089
  __cil_tmp141 = (unsigned int )__cil_tmp140;
#line 1089
  if (__cil_tmp141 == 1U) {
#line 1090
    tv_ctl = tv_ctl | 1073741824U;
  } else {

  }
  }
#line 1091
  __cil_tmp142 = tv_mode->oversample;
#line 1091
  __cil_tmp143 = (u32 )__cil_tmp142;
#line 1091
  tv_ctl = __cil_tmp143 | tv_ctl;
  {
#line 1093
  __cil_tmp144 = tv_mode->progressive;
#line 1093
  if ((int )__cil_tmp144) {
#line 1094
    tv_ctl = tv_ctl | 131072U;
  } else {

  }
  }
  {
#line 1095
  __cil_tmp145 = tv_mode->trilevel_sync;
#line 1095
  if ((int )__cil_tmp145) {
#line 1096
    tv_ctl = tv_ctl | 2097152U;
  } else {

  }
  }
  {
#line 1097
  __cil_tmp146 = tv_mode->pal_burst;
#line 1097
  if ((int )__cil_tmp146) {
#line 1098
    tv_ctl = tv_ctl | 65536U;
  } else {

  }
  }
#line 1100
  scctl1 = 0U;
  {
#line 1101
  __cil_tmp147 = tv_mode->dda1_inc;
#line 1101
  __cil_tmp148 = (int )__cil_tmp147;
#line 1101
  if (__cil_tmp148 != 0) {
#line 1102
    scctl1 = scctl1 | 2147483648U;
  } else {

  }
  }
  {
#line 1103
  __cil_tmp149 = tv_mode->dda2_inc;
#line 1103
  __cil_tmp150 = (int )__cil_tmp149;
#line 1103
  if (__cil_tmp150 != 0) {
#line 1104
    scctl1 = scctl1 | 1073741824U;
  } else {

  }
  }
  {
#line 1105
  __cil_tmp151 = tv_mode->dda3_inc;
#line 1105
  __cil_tmp152 = (int )__cil_tmp151;
#line 1105
  if (__cil_tmp152 != 0) {
#line 1106
    scctl1 = scctl1 | 536870912U;
  } else {

  }
  }
#line 1107
  __cil_tmp153 = tv_mode->sc_reset;
#line 1107
  __cil_tmp154 = (u32 )__cil_tmp153;
#line 1107
  scctl1 = __cil_tmp154 | scctl1;
  {
#line 1108
  __cil_tmp155 = (struct video_levels  const  *)0;
#line 1108
  __cil_tmp156 = (unsigned long )__cil_tmp155;
#line 1108
  __cil_tmp157 = (unsigned long )video_levels;
#line 1108
  if (__cil_tmp157 != __cil_tmp156) {
#line 1109
    __cil_tmp158 = video_levels->burst;
#line 1109
    __cil_tmp159 = __cil_tmp158 << 16;
#line 1109
    __cil_tmp160 = (u32 )__cil_tmp159;
#line 1109
    scctl1 = __cil_tmp160 | scctl1;
  } else {

  }
  }
#line 1110
  __cil_tmp161 = tv_mode->dda1_inc;
#line 1110
  __cil_tmp162 = (u32 )__cil_tmp161;
#line 1110
  scctl1 = __cil_tmp162 | scctl1;
#line 1112
  __cil_tmp163 = tv_mode->dda2_inc;
#line 1112
  __cil_tmp164 = (int )__cil_tmp163;
#line 1112
  __cil_tmp165 = tv_mode->dda2_size;
#line 1112
  __cil_tmp166 = __cil_tmp165 << 16;
#line 1112
  __cil_tmp167 = (int )__cil_tmp166;
#line 1112
  __cil_tmp168 = __cil_tmp167 | __cil_tmp164;
#line 1112
  scctl2 = (u32 )__cil_tmp168;
#line 1115
  __cil_tmp169 = tv_mode->dda3_inc;
#line 1115
  __cil_tmp170 = (int )__cil_tmp169;
#line 1115
  __cil_tmp171 = tv_mode->dda3_size;
#line 1115
  __cil_tmp172 = __cil_tmp171 << 16;
#line 1115
  __cil_tmp173 = (int )__cil_tmp172;
#line 1115
  __cil_tmp174 = __cil_tmp173 | __cil_tmp170;
#line 1115
  scctl3 = (u32 )__cil_tmp174;
  {
#line 1119
  __cil_tmp175 = dev->pci_device;
#line 1119
  if (__cil_tmp175 <= 10097) {
#line 1120
    tv_ctl = tv_ctl | 3072U;
  } else {

  }
  }
  {
#line 1122
  i915_write32___9(dev_priv, 426032U, hctl1);
#line 1123
  i915_write32___9(dev_priv, 426036U, hctl2);
#line 1124
  i915_write32___9(dev_priv, 426040U, hctl3);
#line 1125
  i915_write32___9(dev_priv, 426044U, vctl1);
#line 1126
  i915_write32___9(dev_priv, 426048U, vctl2);
#line 1127
  i915_write32___9(dev_priv, 426052U, vctl3);
#line 1128
  i915_write32___9(dev_priv, 426056U, vctl4);
#line 1129
  i915_write32___9(dev_priv, 426060U, vctl5);
#line 1130
  i915_write32___9(dev_priv, 426064U, vctl6);
#line 1131
  i915_write32___9(dev_priv, 426068U, vctl7);
#line 1132
  i915_write32___9(dev_priv, 426080U, scctl1);
#line 1133
  i915_write32___9(dev_priv, 426084U, scctl2);
#line 1134
  i915_write32___9(dev_priv, 426088U, scctl3);
  }
  {
#line 1136
  __cil_tmp176 = (struct color_conversion  const  *)0;
#line 1136
  __cil_tmp177 = (unsigned long )__cil_tmp176;
#line 1136
  __cil_tmp178 = (unsigned long )color_conversion;
#line 1136
  if (__cil_tmp178 != __cil_tmp177) {
    {
#line 1137
    __cil_tmp179 = color_conversion->gy;
#line 1137
    __cil_tmp180 = (int )__cil_tmp179;
#line 1137
    __cil_tmp181 = color_conversion->ry;
#line 1137
    __cil_tmp182 = (int )__cil_tmp181;
#line 1137
    __cil_tmp183 = __cil_tmp182 << 16;
#line 1137
    __cil_tmp184 = __cil_tmp183 | __cil_tmp180;
#line 1137
    __cil_tmp185 = (u32 )__cil_tmp184;
#line 1137
    i915_write32___9(dev_priv, 426000U, __cil_tmp185);
#line 1139
    __cil_tmp186 = color_conversion->ay;
#line 1139
    __cil_tmp187 = (int )__cil_tmp186;
#line 1139
    __cil_tmp188 = color_conversion->by;
#line 1139
    __cil_tmp189 = (int )__cil_tmp188;
#line 1139
    __cil_tmp190 = __cil_tmp189 << 16;
#line 1139
    __cil_tmp191 = __cil_tmp190 | __cil_tmp187;
#line 1139
    __cil_tmp192 = (u32 )__cil_tmp191;
#line 1139
    i915_write32___9(dev_priv, 426004U, __cil_tmp192);
#line 1141
    __cil_tmp193 = color_conversion->gu;
#line 1141
    __cil_tmp194 = (int )__cil_tmp193;
#line 1141
    __cil_tmp195 = color_conversion->ru;
#line 1141
    __cil_tmp196 = (int )__cil_tmp195;
#line 1141
    __cil_tmp197 = __cil_tmp196 << 16;
#line 1141
    __cil_tmp198 = __cil_tmp197 | __cil_tmp194;
#line 1141
    __cil_tmp199 = (u32 )__cil_tmp198;
#line 1141
    i915_write32___9(dev_priv, 426008U, __cil_tmp199);
#line 1143
    __cil_tmp200 = color_conversion->au;
#line 1143
    __cil_tmp201 = (int )__cil_tmp200;
#line 1143
    __cil_tmp202 = color_conversion->bu;
#line 1143
    __cil_tmp203 = (int )__cil_tmp202;
#line 1143
    __cil_tmp204 = __cil_tmp203 << 16;
#line 1143
    __cil_tmp205 = __cil_tmp204 | __cil_tmp201;
#line 1143
    __cil_tmp206 = (u32 )__cil_tmp205;
#line 1143
    i915_write32___9(dev_priv, 426012U, __cil_tmp206);
#line 1145
    __cil_tmp207 = color_conversion->gv;
#line 1145
    __cil_tmp208 = (int )__cil_tmp207;
#line 1145
    __cil_tmp209 = color_conversion->rv;
#line 1145
    __cil_tmp210 = (int )__cil_tmp209;
#line 1145
    __cil_tmp211 = __cil_tmp210 << 16;
#line 1145
    __cil_tmp212 = __cil_tmp211 | __cil_tmp208;
#line 1145
    __cil_tmp213 = (u32 )__cil_tmp212;
#line 1145
    i915_write32___9(dev_priv, 426016U, __cil_tmp213);
#line 1147
    __cil_tmp214 = color_conversion->av;
#line 1147
    __cil_tmp215 = (int )__cil_tmp214;
#line 1147
    __cil_tmp216 = color_conversion->bv;
#line 1147
    __cil_tmp217 = (int )__cil_tmp216;
#line 1147
    __cil_tmp218 = __cil_tmp217 << 16;
#line 1147
    __cil_tmp219 = __cil_tmp218 | __cil_tmp215;
#line 1147
    __cil_tmp220 = (u32 )__cil_tmp219;
#line 1147
    i915_write32___9(dev_priv, 426020U, __cil_tmp220);
    }
  } else {

  }
  }
  {
#line 1151
  __cil_tmp221 = dev->dev_private;
#line 1151
  __cil_tmp222 = (struct drm_i915_private *)__cil_tmp221;
#line 1151
  __cil_tmp223 = __cil_tmp222->info;
#line 1151
  __cil_tmp224 = __cil_tmp223->gen;
#line 1151
  __cil_tmp225 = (unsigned char )__cil_tmp224;
#line 1151
  __cil_tmp226 = (unsigned int )__cil_tmp225;
#line 1151
  if (__cil_tmp226 > 3U) {
    {
#line 1152
    i915_write32___9(dev_priv, 426024U, 4210688U);
    }
  } else {
    {
#line 1154
    i915_write32___9(dev_priv, 426024U, 6316032U);
    }
  }
  }
  {
#line 1156
  __cil_tmp227 = (struct video_levels  const  *)0;
#line 1156
  __cil_tmp228 = (unsigned long )__cil_tmp227;
#line 1156
  __cil_tmp229 = (unsigned long )video_levels;
#line 1156
  if (__cil_tmp229 != __cil_tmp228) {
    {
#line 1157
    __cil_tmp230 = video_levels->blank;
#line 1157
    __cil_tmp231 = (int )__cil_tmp230;
#line 1157
    __cil_tmp232 = video_levels->black;
#line 1157
    __cil_tmp233 = __cil_tmp232 << 16;
#line 1157
    __cil_tmp234 = (int )__cil_tmp233;
#line 1157
    __cil_tmp235 = __cil_tmp234 | __cil_tmp231;
#line 1157
    __cil_tmp236 = (u32 )__cil_tmp235;
#line 1157
    i915_write32___9(dev_priv, 426028U, __cil_tmp236);
    }
  } else {

  }
  }
  {
#line 1161
  __cil_tmp237 = pipe * 4096;
#line 1161
  pipeconf_reg = __cil_tmp237 + 458760;
#line 1162
  __cil_tmp238 = intel_crtc->plane;
#line 1162
  __cil_tmp239 = (unsigned int )__cil_tmp238;
#line 1162
  __cil_tmp240 = __cil_tmp239 * 4096U;
#line 1162
  __cil_tmp241 = __cil_tmp240 + 459136U;
#line 1162
  dspcntr_reg = (int )__cil_tmp241;
#line 1163
  __cil_tmp242 = (u32 )pipeconf_reg;
#line 1163
  tmp___1 = i915_read32___11(dev_priv, __cil_tmp242);
#line 1163
  pipeconf = (int )tmp___1;
#line 1164
  __cil_tmp243 = (u32 )dspcntr_reg;
#line 1164
  tmp___2 = i915_read32___11(dev_priv, __cil_tmp243);
#line 1164
  dspcntr = (int )tmp___2;
#line 1165
  __cil_tmp244 = intel_crtc->plane;
#line 1165
  __cil_tmp245 = (unsigned int )__cil_tmp244;
#line 1165
  __cil_tmp246 = __cil_tmp245 * 4096U;
#line 1165
  __cil_tmp247 = __cil_tmp246 + 459140U;
#line 1165
  dspbase_reg = (int )__cil_tmp247;
#line 1166
  xpos = 0;
#line 1166
  ypos = 0;
#line 1169
  __cil_tmp248 = (u32 )dspcntr_reg;
#line 1169
  __cil_tmp249 = (u32 )dspcntr;
#line 1169
  __cil_tmp250 = __cil_tmp249 & 2147483647U;
#line 1169
  i915_write32___9(dev_priv, __cil_tmp248, __cil_tmp250);
#line 1171
  __cil_tmp251 = (u32 )dspbase_reg;
#line 1171
  tmp___3 = i915_read32___11(dev_priv, __cil_tmp251);
#line 1171
  __cil_tmp252 = (u32 )dspbase_reg;
#line 1171
  i915_write32___9(dev_priv, __cil_tmp252, tmp___3);
  }
  {
#line 1174
  __cil_tmp253 = dev->dev_private;
#line 1174
  __cil_tmp254 = (struct drm_i915_private *)__cil_tmp253;
#line 1174
  __cil_tmp255 = __cil_tmp254->info;
#line 1174
  __cil_tmp256 = __cil_tmp255->gen;
#line 1174
  __cil_tmp257 = (unsigned char )__cil_tmp256;
#line 1174
  __cil_tmp258 = (unsigned int )__cil_tmp257;
#line 1174
  if (__cil_tmp258 == 2U) {
    {
#line 1175
    __cil_tmp259 = intel_crtc->pipe;
#line 1175
    __cil_tmp260 = (int )__cil_tmp259;
#line 1175
    intel_wait_for_vblank(dev, __cil_tmp260);
    }
  } else {

  }
  }
  {
#line 1177
  __cil_tmp261 = (u32 )pipeconf_reg;
#line 1177
  __cil_tmp262 = (u32 )pipeconf;
#line 1177
  __cil_tmp263 = __cil_tmp262 & 2147483647U;
#line 1177
  i915_write32___9(dev_priv, __cil_tmp261, __cil_tmp263);
#line 1179
  __cil_tmp264 = intel_crtc->pipe;
#line 1179
  __cil_tmp265 = (int )__cil_tmp264;
#line 1179
  intel_wait_for_pipe_off(dev, __cil_tmp265);
#line 1182
  i915_write32___9(dev_priv, 426112U, 2147483648U);
#line 1183
  __cil_tmp266 = tv_mode->hblank_end;
#line 1183
  __cil_tmp267 = (int )__cil_tmp266;
#line 1183
  __cil_tmp268 = tv_mode->hblank_start;
#line 1183
  __cil_tmp269 = (int )__cil_tmp268;
#line 1183
  __cil_tmp270 = __cil_tmp269 - __cil_tmp267;
#line 1183
  xsize = (unsigned int )__cil_tmp270;
  }
  {
#line 1184
  __cil_tmp271 = tv_mode->progressive;
#line 1184
  if ((int )__cil_tmp271) {
#line 1185
    __cil_tmp272 = tv_mode->nbr_end;
#line 1185
    __cil_tmp273 = (int )__cil_tmp272;
#line 1185
    __cil_tmp274 = __cil_tmp273 + 1;
#line 1185
    ysize = (unsigned int )__cil_tmp274;
  } else {
#line 1187
    __cil_tmp275 = tv_mode->nbr_end;
#line 1187
    __cil_tmp276 = (int )__cil_tmp275;
#line 1187
    __cil_tmp277 = __cil_tmp276 * 2;
#line 1187
    __cil_tmp278 = __cil_tmp277 + 1;
#line 1187
    ysize = (unsigned int )__cil_tmp278;
  }
  }
  {
#line 1189
  __cil_tmp279 = intel_tv->margin[0];
#line 1189
  xpos = __cil_tmp279 + xpos;
#line 1190
  __cil_tmp280 = intel_tv->margin[1];
#line 1190
  ypos = __cil_tmp280 + ypos;
#line 1191
  __cil_tmp281 = intel_tv->margin[2];
#line 1191
  __cil_tmp282 = intel_tv->margin[0];
#line 1191
  __cil_tmp283 = __cil_tmp282 + __cil_tmp281;
#line 1191
  __cil_tmp284 = (unsigned int )__cil_tmp283;
#line 1191
  xsize = xsize - __cil_tmp284;
#line 1193
  __cil_tmp285 = intel_tv->margin[3];
#line 1193
  __cil_tmp286 = intel_tv->margin[1];
#line 1193
  __cil_tmp287 = __cil_tmp286 + __cil_tmp285;
#line 1193
  __cil_tmp288 = (unsigned int )__cil_tmp287;
#line 1193
  ysize = ysize - __cil_tmp288;
#line 1195
  __cil_tmp289 = xpos << 16;
#line 1195
  __cil_tmp290 = __cil_tmp289 | ypos;
#line 1195
  __cil_tmp291 = (u32 )__cil_tmp290;
#line 1195
  i915_write32___9(dev_priv, 426096U, __cil_tmp291);
#line 1196
  __cil_tmp292 = xsize << 16;
#line 1196
  __cil_tmp293 = __cil_tmp292 | ysize;
#line 1196
  i915_write32___9(dev_priv, 426100U, __cil_tmp293);
#line 1198
  __cil_tmp294 = (u32 )pipeconf_reg;
#line 1198
  __cil_tmp295 = (u32 )pipeconf;
#line 1198
  i915_write32___9(dev_priv, __cil_tmp294, __cil_tmp295);
#line 1199
  __cil_tmp296 = (u32 )dspcntr_reg;
#line 1199
  __cil_tmp297 = (u32 )dspcntr;
#line 1199
  i915_write32___9(dev_priv, __cil_tmp296, __cil_tmp297);
#line 1201
  __cil_tmp298 = (u32 )dspbase_reg;
#line 1201
  tmp___4 = i915_read32___11(dev_priv, __cil_tmp298);
#line 1201
  __cil_tmp299 = (u32 )dspbase_reg;
#line 1201
  i915_write32___9(dev_priv, __cil_tmp299, tmp___4);
#line 1204
  j = 0;
#line 1205
  i = 0;
  }
#line 1205
  goto ldv_37883;
  ldv_37882: 
  {
#line 1206
  tmp___5 = j;
#line 1206
  j = j + 1;
#line 1206
  __cil_tmp300 = i << 2;
#line 1206
  __cil_tmp301 = __cil_tmp300 + 426240;
#line 1206
  __cil_tmp302 = (u32 )__cil_tmp301;
#line 1206
  __cil_tmp303 = (unsigned long )tmp___5;
#line 1206
  __cil_tmp304 = tv_mode->filter_table;
#line 1206
  __cil_tmp305 = __cil_tmp304 + __cil_tmp303;
#line 1206
  __cil_tmp306 = *__cil_tmp305;
#line 1206
  __cil_tmp307 = (u32 )__cil_tmp306;
#line 1206
  i915_write32___9(dev_priv, __cil_tmp302, __cil_tmp307);
#line 1205
  i = i + 1;
  }
  ldv_37883: ;
#line 1205
  if (i <= 59) {
#line 1206
    goto ldv_37882;
  } else {
#line 1208
    goto ldv_37884;
  }
  ldv_37884: 
#line 1207
  i = 0;
#line 1207
  goto ldv_37886;
  ldv_37885: 
  {
#line 1208
  tmp___6 = j;
#line 1208
  j = j + 1;
#line 1208
  __cil_tmp308 = i << 2;
#line 1208
  __cil_tmp309 = __cil_tmp308 + 426496;
#line 1208
  __cil_tmp310 = (u32 )__cil_tmp309;
#line 1208
  __cil_tmp311 = (unsigned long )tmp___6;
#line 1208
  __cil_tmp312 = tv_mode->filter_table;
#line 1208
  __cil_tmp313 = __cil_tmp312 + __cil_tmp311;
#line 1208
  __cil_tmp314 = *__cil_tmp313;
#line 1208
  __cil_tmp315 = (u32 )__cil_tmp314;
#line 1208
  i915_write32___9(dev_priv, __cil_tmp310, __cil_tmp315);
#line 1207
  i = i + 1;
  }
  ldv_37886: ;
#line 1207
  if (i <= 59) {
#line 1208
    goto ldv_37885;
  } else {
#line 1210
    goto ldv_37887;
  }
  ldv_37887: 
#line 1209
  i = 0;
#line 1209
  goto ldv_37889;
  ldv_37888: 
  {
#line 1210
  tmp___7 = j;
#line 1210
  j = j + 1;
#line 1210
  __cil_tmp316 = i << 2;
#line 1210
  __cil_tmp317 = __cil_tmp316 + 426752;
#line 1210
  __cil_tmp318 = (u32 )__cil_tmp317;
#line 1210
  __cil_tmp319 = (unsigned long )tmp___7;
#line 1210
  __cil_tmp320 = tv_mode->filter_table;
#line 1210
  __cil_tmp321 = __cil_tmp320 + __cil_tmp319;
#line 1210
  __cil_tmp322 = *__cil_tmp321;
#line 1210
  __cil_tmp323 = (u32 )__cil_tmp322;
#line 1210
  i915_write32___9(dev_priv, __cil_tmp318, __cil_tmp323);
#line 1209
  i = i + 1;
  }
  ldv_37889: ;
#line 1209
  if (i <= 42) {
#line 1210
    goto ldv_37888;
  } else {
#line 1212
    goto ldv_37890;
  }
  ldv_37890: 
#line 1211
  i = 0;
#line 1211
  goto ldv_37892;
  ldv_37891: 
  {
#line 1212
  tmp___8 = j;
#line 1212
  j = j + 1;
#line 1212
  __cil_tmp324 = i << 2;
#line 1212
  __cil_tmp325 = __cil_tmp324 + 427008;
#line 1212
  __cil_tmp326 = (u32 )__cil_tmp325;
#line 1212
  __cil_tmp327 = (unsigned long )tmp___8;
#line 1212
  __cil_tmp328 = tv_mode->filter_table;
#line 1212
  __cil_tmp329 = __cil_tmp328 + __cil_tmp327;
#line 1212
  __cil_tmp330 = *__cil_tmp329;
#line 1212
  __cil_tmp331 = (u32 )__cil_tmp330;
#line 1212
  i915_write32___9(dev_priv, __cil_tmp326, __cil_tmp331);
#line 1211
  i = i + 1;
  }
  ldv_37892: ;
#line 1211
  if (i <= 42) {
#line 1212
    goto ldv_37891;
  } else {
#line 1214
    goto ldv_37893;
  }
  ldv_37893: 
  {
#line 1213
  tmp___9 = i915_read32___11(dev_priv, 425988U);
#line 1213
  __cil_tmp332 = tmp___9 & 16776960U;
#line 1213
  i915_write32___9(dev_priv, 425988U, __cil_tmp332);
#line 1214
  i915_write32___9(dev_priv, 425984U, tv_ctl);
  }
#line 1215
  return;
}
}
#line 1217 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct drm_display_mode  const  reported_modes[1U]  = {      {{(struct list_head *)0, (struct list_head *)0}, {0U, 0U}, {(char )'N', (char )'T',
                                                                 (char )'S', (char )'C',
                                                                 (char )' ', (char )'4',
                                                                 (char )'8', (char )'0',
                                                                 (char )'i', (char )'\000'},
      0, (enum drm_mode_status )0, 64, 107520, 1280, 1368, 1496, 1712, 0, 1024, 1027,
      1034, 1104, 0, 0U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
      0, (int *)0, 0, 0, 0}};
#line 1243 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static int intel_tv_detect_type(struct intel_tv *intel_tv , struct drm_connector *connector ) 
{ struct drm_encoder *encoder ;
  struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  unsigned long irqflags ;
  u32 tv_ctl ;
  u32 save_tv_ctl ;
  u32 tv_dac ;
  u32 save_tv_dac ;
  int type ;
  raw_spinlock_t *tmp ;
  struct drm_crtc  const  *__mptr ;
  unsigned long timeout__ ;
  unsigned long tmp___0 ;
  int ret__ ;
  struct thread_info *tmp___1 ;
  int pfo_ret__ ;
  int tmp___2 ;
  raw_spinlock_t *tmp___3 ;
  void *__cil_tmp21 ;
  uint8_t __cil_tmp22 ;
  int __cil_tmp23 ;
  spinlock_t *__cil_tmp24 ;
  spinlock_t *__cil_tmp25 ;
  void *__cil_tmp26 ;
  void const volatile   *__cil_tmp27 ;
  void const volatile   *__cil_tmp28 ;
  struct drm_crtc *__cil_tmp29 ;
  struct drm_device *__cil_tmp30 ;
  struct intel_crtc *__cil_tmp31 ;
  enum pipe __cil_tmp32 ;
  int __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  long __cil_tmp37 ;
  long __cil_tmp38 ;
  long __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  atomic_t const   *__cil_tmp42 ;
  int __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  unsigned int __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  uint8_t __cil_tmp48 ;
  int __cil_tmp49 ;
  spinlock_t *__cil_tmp50 ;
  spinlock_t *__cil_tmp51 ;

  {
#line 1246
  encoder = & intel_tv->base.base;
#line 1247
  dev = encoder->dev;
#line 1248
  __cil_tmp21 = dev->dev_private;
#line 1248
  dev_priv = (struct drm_i915_private *)__cil_tmp21;
  {
#line 1255
  __cil_tmp22 = connector->polled;
#line 1255
  __cil_tmp23 = (int )__cil_tmp22;
#line 1255
  if (__cil_tmp23 & 1) {
    {
#line 1256
    __cil_tmp24 = & dev_priv->irq_lock;
#line 1256
    tmp = spinlock_check(__cil_tmp24);
#line 1256
    irqflags = _raw_spin_lock_irqsave(tmp);
#line 1257
    i915_disable_pipestat(dev_priv, 0, 67371008U);
#line 1260
    __cil_tmp25 = & dev_priv->irq_lock;
#line 1260
    spin_unlock_irqrestore(__cil_tmp25, irqflags);
    }
  } else {

  }
  }
  {
#line 1263
  tv_dac = i915_read32___11(dev_priv, 425988U);
#line 1263
  save_tv_dac = tv_dac;
#line 1264
  tv_ctl = i915_read32___11(dev_priv, 425984U);
#line 1264
  save_tv_ctl = tv_ctl;
#line 1267
  tv_ctl = tv_ctl & 2147483640U;
#line 1268
  tv_ctl = tv_ctl | 7U;
#line 1270
  tv_dac = tv_dac & 2415919040U;
#line 1271
  tv_dac = tv_dac | 251658410U;
#line 1280
  i915_write32___9(dev_priv, 425984U, tv_ctl);
#line 1281
  i915_write32___9(dev_priv, 425988U, tv_dac);
#line 1282
  __cil_tmp26 = dev_priv->regs;
#line 1282
  __cil_tmp27 = (void const volatile   *)__cil_tmp26;
#line 1282
  __cil_tmp28 = __cil_tmp27 + 425988U;
#line 1282
  readl(__cil_tmp28);
#line 1285
  __cil_tmp29 = intel_tv->base.base.crtc;
#line 1285
  __mptr = (struct drm_crtc  const  *)__cil_tmp29;
#line 1285
  __cil_tmp30 = intel_tv->base.base.dev;
#line 1285
  __cil_tmp31 = (struct intel_crtc *)__mptr;
#line 1285
  __cil_tmp32 = __cil_tmp31->pipe;
#line 1285
  __cil_tmp33 = (int )__cil_tmp32;
#line 1285
  intel_wait_for_vblank(__cil_tmp30, __cil_tmp33);
#line 1287
  type = -1;
#line 1288
  __cil_tmp34 = (unsigned int const   )20U;
#line 1288
  __cil_tmp35 = (unsigned int )__cil_tmp34;
#line 1288
  tmp___0 = msecs_to_jiffies(__cil_tmp35);
#line 1288
  __cil_tmp36 = (unsigned long )jiffies;
#line 1288
  timeout__ = tmp___0 + __cil_tmp36;
#line 1288
  ret__ = 0;
  }
#line 1288
  goto ldv_37931;
  ldv_37930: ;
  {
#line 1288
  __cil_tmp37 = (long )jiffies;
#line 1288
  __cil_tmp38 = (long )timeout__;
#line 1288
  __cil_tmp39 = __cil_tmp38 - __cil_tmp37;
#line 1288
  if (__cil_tmp39 < 0L) {
#line 1288
    ret__ = -110;
#line 1288
    goto ldv_37921;
  } else {

  }
  }
  {
#line 1288
  tmp___1 = current_thread_info();
  }
  {
#line 1288
  __cil_tmp40 = tmp___1->preempt_count;
#line 1288
  __cil_tmp41 = __cil_tmp40 & -268435457;
#line 1288
  if (__cil_tmp41 == 0) {
#line 1288
    if (1) {
#line 1288
      goto case_4;
    } else {
#line 1288
      goto switch_default;
#line 1288
      if (0) {
#line 1288
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 1288
        goto ldv_37924;
#line 1288
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 1288
        goto ldv_37924;
        case_4: 
#line 1288
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 1288
        goto ldv_37924;
#line 1288
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 1288
        goto ldv_37924;
        switch_default: 
        {
#line 1288
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_37924: 
    {
#line 1288
    __cil_tmp42 = (atomic_t const   *)(& kgdb_active);
#line 1288
    tmp___2 = atomic_read(__cil_tmp42);
    }
#line 1288
    if (pfo_ret__ != tmp___2) {
      {
#line 1288
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_37931: 
  {
#line 1288
  tv_dac = i915_read32___11(dev_priv, 425988U);
  }
  {
#line 1288
  __cil_tmp43 = (int )tv_dac;
#line 1288
  if (__cil_tmp43 >= 0) {
#line 1289
    goto ldv_37930;
  } else {
#line 1291
    goto ldv_37921;
  }
  }
  ldv_37921: ;
#line 1288
  if (ret__ == 0) {
    {
#line 1289
    drm_ut_debug_printk(4U, "drm", "intel_tv_detect_type", "TV detected: %x, %x\n",
                        tv_ctl, tv_dac);
    }
    {
#line 1296
    __cil_tmp44 = tv_dac & 1879048192U;
#line 1296
    if (__cil_tmp44 == 805306368U) {
      {
#line 1297
      drm_ut_debug_printk(4U, "drm", "intel_tv_detect_type", "Detected Composite TV connection\n");
#line 1298
      type = 5;
      }
    } else {
      {
#line 1299
      __cil_tmp45 = tv_dac & 1610612736U;
#line 1299
      if (__cil_tmp45 == 1073741824U) {
        {
#line 1300
        drm_ut_debug_printk(4U, "drm", "intel_tv_detect_type", "Detected S-Video TV connection\n");
#line 1301
        type = 6;
        }
      } else {
        {
#line 1302
        __cil_tmp46 = tv_dac & 1879048192U;
#line 1302
        if (__cil_tmp46 == 0U) {
          {
#line 1303
          drm_ut_debug_printk(4U, "drm", "intel_tv_detect_type", "Detected Component TV connection\n");
#line 1304
          type = 8;
          }
        } else {
          {
#line 1306
          drm_ut_debug_printk(4U, "drm", "intel_tv_detect_type", "Unrecognised TV connection\n");
          }
        }
        }
      }
      }
    }
    }
  } else {

  }
  {
#line 1310
  __cil_tmp47 = save_tv_dac & 4160749567U;
#line 1310
  i915_write32___9(dev_priv, 425988U, __cil_tmp47);
#line 1311
  i915_write32___9(dev_priv, 425984U, save_tv_ctl);
  }
  {
#line 1314
  __cil_tmp48 = connector->polled;
#line 1314
  __cil_tmp49 = (int )__cil_tmp48;
#line 1314
  if (__cil_tmp49 & 1) {
    {
#line 1315
    __cil_tmp50 = & dev_priv->irq_lock;
#line 1315
    tmp___3 = spinlock_check(__cil_tmp50);
#line 1315
    irqflags = _raw_spin_lock_irqsave(tmp___3);
#line 1316
    i915_enable_pipestat(dev_priv, 0, 67371008U);
#line 1319
    __cil_tmp51 = & dev_priv->irq_lock;
#line 1319
    spin_unlock_irqrestore(__cil_tmp51, irqflags);
    }
  } else {

  }
  }
#line 1322
  return (type);
}
}
#line 1329 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static void intel_tv_find_better_format(struct drm_connector *connector ) 
{ struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct tv_mode  const  *tv_mode ;
  struct tv_mode  const  *tmp___0 ;
  int i ;
  bool __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct tv_mode  const  *__cil_tmp12 ;
  bool __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  char const   *__cil_tmp18 ;
  struct drm_device *__cil_tmp19 ;
  struct drm_property *__cil_tmp20 ;
  uint64_t __cil_tmp21 ;

  {
  {
#line 1331
  tmp = intel_attached_tv(connector);
#line 1331
  intel_tv = tmp;
#line 1332
  tmp___0 = intel_tv_mode_find(intel_tv);
#line 1332
  tv_mode = tmp___0;
  }
  {
#line 1335
  __cil_tmp7 = tv_mode->component_only;
#line 1335
  __cil_tmp8 = (int )__cil_tmp7;
#line 1335
  __cil_tmp9 = intel_tv->type;
#line 1335
  __cil_tmp10 = __cil_tmp9 == 8;
#line 1335
  if (__cil_tmp10 == __cil_tmp8) {
#line 1337
    return;
  } else {

  }
  }
#line 1340
  i = 0;
#line 1340
  goto ldv_37945;
  ldv_37944: 
#line 1341
  __cil_tmp11 = (unsigned long )i;
#line 1341
  __cil_tmp12 = (struct tv_mode  const  *)(& tv_modes);
#line 1341
  tv_mode = __cil_tmp12 + __cil_tmp11;
  {
#line 1343
  __cil_tmp13 = tv_mode->component_only;
#line 1343
  __cil_tmp14 = (int )__cil_tmp13;
#line 1343
  __cil_tmp15 = intel_tv->type;
#line 1343
  __cil_tmp16 = __cil_tmp15 == 8;
#line 1343
  if (__cil_tmp16 == __cil_tmp14) {
#line 1345
    goto ldv_37943;
  } else {

  }
  }
#line 1340
  i = i + 1;
  ldv_37945: ;
  {
#line 1340
  __cil_tmp17 = (unsigned int )i;
#line 1340
  if (__cil_tmp17 <= 14U) {
#line 1341
    goto ldv_37944;
  } else {
#line 1343
    goto ldv_37943;
  }
  }
  ldv_37943: 
  {
#line 1348
  __cil_tmp18 = tv_mode->name;
#line 1348
  intel_tv->tv_format = (char const   *)__cil_tmp18;
#line 1349
  __cil_tmp19 = connector->dev;
#line 1349
  __cil_tmp20 = __cil_tmp19->mode_config.tv_mode_property;
#line 1349
  __cil_tmp21 = (uint64_t )i;
#line 1349
  drm_connector_property_set_value(connector, __cil_tmp20, __cil_tmp21);
  }
#line 1351
  return;
}
}
#line 1360 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static enum drm_connector_status intel_tv_detect(struct drm_connector *connector ,
                                                 bool force ) 
{ struct drm_display_mode mode ;
  struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  int type ;
  struct intel_load_detect_pipe tmp___0 ;
  bool tmp___1 ;
  struct drm_crtc *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct drm_crtc *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct drm_crtc *__cil_tmp13 ;
  bool __cil_tmp14 ;
  struct intel_encoder *__cil_tmp15 ;
  struct intel_encoder *__cil_tmp16 ;

  {
  {
#line 1363
  tmp = intel_attached_tv(connector);
#line 1363
  intel_tv = tmp;
#line 1366
  mode = (struct drm_display_mode )reported_modes[0];
#line 1367
  drm_mode_set_crtcinfo(& mode, 1);
  }
  {
#line 1369
  __cil_tmp9 = (struct drm_crtc *)0;
#line 1369
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 1369
  __cil_tmp11 = intel_tv->base.base.crtc;
#line 1369
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 1369
  if (__cil_tmp12 != __cil_tmp10) {
    {
#line 1369
    __cil_tmp13 = intel_tv->base.base.crtc;
#line 1369
    __cil_tmp14 = __cil_tmp13->enabled;
#line 1369
    if ((int )__cil_tmp14) {
      {
#line 1370
      type = intel_tv_detect_type(intel_tv, connector);
      }
    } else {
#line 1369
      goto _L;
    }
    }
  } else
  _L: 
#line 1371
  if ((int )force) {
    {
#line 1374
    __cil_tmp15 = & intel_tv->base;
#line 1374
    tmp___1 = intel_get_load_detect_pipe(__cil_tmp15, connector, & mode, & tmp___0);
    }
#line 1374
    if ((int )tmp___1) {
      {
#line 1376
      type = intel_tv_detect_type(intel_tv, connector);
#line 1377
      __cil_tmp16 = & intel_tv->base;
#line 1377
      intel_release_load_detect_pipe(__cil_tmp16, connector, & tmp___0);
      }
    } else {
#line 1381
      return ((enum drm_connector_status )3);
    }
  } else {
#line 1383
    return (connector->status);
  }
  }
#line 1385
  if (type < 0) {
#line 1386
    return ((enum drm_connector_status )2);
  } else {

  }
  {
#line 1388
  intel_tv->type = type;
#line 1389
  intel_tv_find_better_format(connector);
  }
#line 1391
  return ((enum drm_connector_status )1);
}
}
#line 1397 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct input_res  const  input_res_table[7U]  = {      {"640x480", 640, 480}, 
        {"800x600", 800, 600}, 
        {"1024x768", 1024, 768}, 
        {"1280x1024", 1280, 1024}, 
        {"848x480", 848, 480}, 
        {"1280x720", 1280, 720}, 
        {"1920x1080", 1920, 1080}};
#line 1411 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static void intel_tv_chose_preferred_modes(struct drm_connector *connector , struct drm_display_mode *mode_ptr ) 
{ struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct tv_mode  const  *tv_mode ;
  struct tv_mode  const  *tmp___0 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  bool __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;

  {
  {
#line 1414
  tmp = intel_attached_tv(connector);
#line 1414
  intel_tv = tmp;
#line 1415
  tmp___0 = intel_tv_mode_find(intel_tv);
#line 1415
  tv_mode = tmp___0;
  }
  {
#line 1417
  __cil_tmp7 = tv_mode->nbr_end;
#line 1417
  __cil_tmp8 = (int )__cil_tmp7;
#line 1417
  if (__cil_tmp8 <= 479) {
    {
#line 1417
    __cil_tmp9 = mode_ptr->vdisplay;
#line 1417
    if (__cil_tmp9 == 480) {
#line 1418
      __cil_tmp10 = mode_ptr->type;
#line 1418
      mode_ptr->type = __cil_tmp10 | 8;
    } else {
#line 1417
      goto _L;
    }
    }
  } else {
    _L: 
    {
#line 1419
    __cil_tmp11 = tv_mode->nbr_end;
#line 1419
    __cil_tmp12 = (int )__cil_tmp11;
#line 1419
    if (__cil_tmp12 > 480) {
      {
#line 1420
      __cil_tmp13 = tv_mode->progressive;
#line 1420
      if ((int )__cil_tmp13) {
        {
#line 1420
        __cil_tmp14 = tv_mode->nbr_end;
#line 1420
        __cil_tmp15 = (int )__cil_tmp14;
#line 1420
        if (__cil_tmp15 <= 719) {
          {
#line 1421
          __cil_tmp16 = mode_ptr->vdisplay;
#line 1421
          if (__cil_tmp16 == 720) {
#line 1422
            __cil_tmp17 = mode_ptr->type;
#line 1422
            mode_ptr->type = __cil_tmp17 | 8;
          } else {
            {
#line 1423
            __cil_tmp18 = mode_ptr->vdisplay;
#line 1423
            if (__cil_tmp18 == 1080) {
#line 1424
              __cil_tmp19 = mode_ptr->type;
#line 1424
              mode_ptr->type = __cil_tmp19 | 8;
            } else {

            }
            }
          }
          }
        } else {

        }
        }
      } else {

      }
      }
    } else {

    }
    }
  }
  }
#line 1425
  return;
}
}
#line 1436 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static int intel_tv_get_modes(struct drm_connector *connector ) 
{ struct drm_display_mode *mode_ptr ;
  struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct tv_mode  const  *tv_mode ;
  struct tv_mode  const  *tmp___0 ;
  int j ;
  int count ;
  u64 tmp___1 ;
  struct input_res  const  *input ;
  unsigned int hactive_s ;
  unsigned int vactive_s ;
  unsigned long __cil_tmp13 ;
  struct input_res  const  *__cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  bool __cil_tmp25 ;
  _Bool __cil_tmp26 ;
  bool __cil_tmp27 ;
  _Bool __cil_tmp28 ;
  struct drm_device *__cil_tmp29 ;
  struct drm_display_mode *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  char (*__cil_tmp33)[32U] ;
  char *__cil_tmp34 ;
  char const   *__cil_tmp35 ;
  char const   *__cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  unsigned int __cil_tmp43 ;
  unsigned int __cil_tmp44 ;
  int __cil_tmp45 ;
  int __cil_tmp46 ;
  int __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  int __cil_tmp49 ;
  unsigned long long __cil_tmp50 ;
  int __cil_tmp51 ;
  unsigned long long __cil_tmp52 ;
  int __cil_tmp53 ;
  u64 __cil_tmp54 ;
  unsigned int __cil_tmp55 ;

  {
  {
#line 1439
  tmp = intel_attached_tv(connector);
#line 1439
  intel_tv = tmp;
#line 1440
  tmp___0 = intel_tv_mode_find(intel_tv);
#line 1440
  tv_mode = tmp___0;
#line 1441
  count = 0;
#line 1444
  j = 0;
  }
#line 1444
  goto ldv_37981;
  ldv_37980: 
#line 1446
  __cil_tmp13 = (unsigned long )j;
#line 1446
  __cil_tmp14 = (struct input_res  const  *)(& input_res_table);
#line 1446
  input = __cil_tmp14 + __cil_tmp13;
#line 1447
  __cil_tmp15 = input->w;
#line 1447
  hactive_s = (unsigned int )__cil_tmp15;
#line 1448
  __cil_tmp16 = input->h;
#line 1448
  vactive_s = (unsigned int )__cil_tmp16;
  {
#line 1450
  __cil_tmp17 = tv_mode->max_srcw;
#line 1450
  __cil_tmp18 = (int )__cil_tmp17;
#line 1450
  if (__cil_tmp18 != 0) {
    {
#line 1450
    __cil_tmp19 = tv_mode->max_srcw;
#line 1450
    __cil_tmp20 = (int )__cil_tmp19;
#line 1450
    __cil_tmp21 = input->w;
#line 1450
    __cil_tmp22 = (int )__cil_tmp21;
#line 1450
    if (__cil_tmp22 > __cil_tmp20) {
#line 1451
      goto ldv_37979;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1453
  __cil_tmp23 = input->w;
#line 1453
  __cil_tmp24 = (int )__cil_tmp23;
#line 1453
  if (__cil_tmp24 > 1024) {
    {
#line 1453
    __cil_tmp25 = tv_mode->progressive;
#line 1453
    __cil_tmp26 = (_Bool )__cil_tmp25;
#line 1453
    if (! __cil_tmp26) {
      {
#line 1453
      __cil_tmp27 = tv_mode->component_only;
#line 1453
      __cil_tmp28 = (_Bool )__cil_tmp27;
#line 1453
      if (! __cil_tmp28) {
#line 1455
        goto ldv_37979;
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1457
  __cil_tmp29 = connector->dev;
#line 1457
  mode_ptr = drm_mode_create(__cil_tmp29);
  }
  {
#line 1458
  __cil_tmp30 = (struct drm_display_mode *)0;
#line 1458
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 1458
  __cil_tmp32 = (unsigned long )mode_ptr;
#line 1458
  if (__cil_tmp32 == __cil_tmp31) {
#line 1459
    goto ldv_37979;
  } else {

  }
  }
  {
#line 1460
  __cil_tmp33 = & mode_ptr->name;
#line 1460
  __cil_tmp34 = (char *)__cil_tmp33;
#line 1460
  __cil_tmp35 = input->name;
#line 1460
  __cil_tmp36 = (char const   *)__cil_tmp35;
#line 1460
  strncpy(__cil_tmp34, __cil_tmp36, 32UL);
#line 1462
  mode_ptr->hdisplay = (int )hactive_s;
#line 1463
  __cil_tmp37 = hactive_s + 1U;
#line 1463
  mode_ptr->hsync_start = (int )__cil_tmp37;
#line 1464
  __cil_tmp38 = hactive_s + 64U;
#line 1464
  mode_ptr->hsync_end = (int )__cil_tmp38;
  }
  {
#line 1465
  __cil_tmp39 = mode_ptr->hsync_start;
#line 1465
  __cil_tmp40 = mode_ptr->hsync_end;
#line 1465
  if (__cil_tmp40 <= __cil_tmp39) {
#line 1466
    __cil_tmp41 = mode_ptr->hsync_start;
#line 1466
    mode_ptr->hsync_end = __cil_tmp41 + 1;
  } else {

  }
  }
#line 1467
  __cil_tmp42 = hactive_s + 96U;
#line 1467
  mode_ptr->htotal = (int )__cil_tmp42;
#line 1469
  mode_ptr->vdisplay = (int )vactive_s;
#line 1470
  __cil_tmp43 = vactive_s + 1U;
#line 1470
  mode_ptr->vsync_start = (int )__cil_tmp43;
#line 1471
  __cil_tmp44 = vactive_s + 32U;
#line 1471
  mode_ptr->vsync_end = (int )__cil_tmp44;
  {
#line 1472
  __cil_tmp45 = mode_ptr->vsync_start;
#line 1472
  __cil_tmp46 = mode_ptr->vsync_end;
#line 1472
  if (__cil_tmp46 <= __cil_tmp45) {
#line 1473
    __cil_tmp47 = mode_ptr->vsync_start;
#line 1473
    mode_ptr->vsync_end = __cil_tmp47 + 1;
  } else {

  }
  }
  {
#line 1474
  __cil_tmp48 = vactive_s + 33U;
#line 1474
  mode_ptr->vtotal = (int )__cil_tmp48;
#line 1476
  __cil_tmp49 = mode_ptr->vtotal;
#line 1476
  __cil_tmp50 = (unsigned long long )__cil_tmp49;
#line 1476
  __cil_tmp51 = tv_mode->refresh;
#line 1476
  __cil_tmp52 = (unsigned long long )__cil_tmp51;
#line 1476
  tmp___1 = __cil_tmp52 * __cil_tmp50;
#line 1477
  __cil_tmp53 = mode_ptr->htotal;
#line 1477
  __cil_tmp54 = (u64 )__cil_tmp53;
#line 1477
  tmp___1 = __cil_tmp54 * tmp___1;
#line 1478
  tmp___1 = div_u64(tmp___1, 1000000U);
#line 1479
  mode_ptr->clock = (int )tmp___1;
#line 1481
  mode_ptr->type = 64;
#line 1482
  intel_tv_chose_preferred_modes(connector, mode_ptr);
#line 1483
  drm_mode_probed_add(connector, mode_ptr);
#line 1484
  count = count + 1;
  }
  ldv_37979: 
#line 1445
  j = j + 1;
  ldv_37981: ;
  {
#line 1444
  __cil_tmp55 = (unsigned int )j;
#line 1444
  if (__cil_tmp55 <= 6U) {
#line 1445
    goto ldv_37980;
  } else {
#line 1447
    goto ldv_37982;
  }
  }
  ldv_37982: ;
#line 1487
  return (count);
}
}
#line 1491 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static void intel_tv_destroy(struct drm_connector *connector ) 
{ void const   *__cil_tmp2 ;

  {
  {
#line 1493
  drm_sysfs_connector_remove(connector);
#line 1494
  drm_connector_cleanup(connector);
#line 1495
  __cil_tmp2 = (void const   *)connector;
#line 1495
  kfree(__cil_tmp2);
  }
#line 1496
  return;
}
}
#line 1500 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static int intel_tv_set_property(struct drm_connector *connector , struct drm_property *property ,
                                 uint64_t val ) 
{ struct drm_device *dev ;
  struct intel_tv *intel_tv ;
  struct intel_tv *tmp ;
  struct drm_crtc *crtc ;
  int ret ;
  bool changed ;
  int tmp___0 ;
  unsigned long __cil_tmp11 ;
  struct drm_property *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  int __cil_tmp14 ;
  uint64_t __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct drm_property *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  int __cil_tmp19 ;
  uint64_t __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct drm_property *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  int __cil_tmp24 ;
  uint64_t __cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  struct drm_property *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  int __cil_tmp29 ;
  uint64_t __cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  struct drm_property *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  char const   *__cil_tmp34 ;
  char const   *__cil_tmp35 ;
  struct drm_crtc *__cil_tmp36 ;
  unsigned long __cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  struct drm_display_mode *__cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  struct drm_framebuffer *__cil_tmp42 ;

  {
  {
#line 1503
  dev = connector->dev;
#line 1504
  tmp = intel_attached_tv(connector);
#line 1504
  intel_tv = tmp;
#line 1505
  crtc = intel_tv->base.base.crtc;
#line 1506
  ret = 0;
#line 1507
  changed = (bool )0;
#line 1509
  ret = drm_connector_property_set_value(connector, property, val);
  }
#line 1510
  if (ret < 0) {
#line 1511
    goto out;
  } else {

  }
  {
#line 1513
  __cil_tmp11 = (unsigned long )property;
#line 1513
  __cil_tmp12 = dev->mode_config.tv_left_margin_property;
#line 1513
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 1513
  if (__cil_tmp13 == __cil_tmp11) {
    {
#line 1513
    __cil_tmp14 = intel_tv->margin[0];
#line 1513
    __cil_tmp15 = (uint64_t )__cil_tmp14;
#line 1513
    if (__cil_tmp15 != val) {
#line 1515
      intel_tv->margin[0] = (int )val;
#line 1516
      changed = (bool )1;
    } else {
#line 1513
      goto _L___2;
    }
    }
  } else {
    _L___2: 
    {
#line 1517
    __cil_tmp16 = (unsigned long )property;
#line 1517
    __cil_tmp17 = dev->mode_config.tv_right_margin_property;
#line 1517
    __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 1517
    if (__cil_tmp18 == __cil_tmp16) {
      {
#line 1517
      __cil_tmp19 = intel_tv->margin[2];
#line 1517
      __cil_tmp20 = (uint64_t )__cil_tmp19;
#line 1517
      if (__cil_tmp20 != val) {
#line 1519
        intel_tv->margin[2] = (int )val;
#line 1520
        changed = (bool )1;
      } else {
#line 1517
        goto _L___1;
      }
      }
    } else {
      _L___1: 
      {
#line 1521
      __cil_tmp21 = (unsigned long )property;
#line 1521
      __cil_tmp22 = dev->mode_config.tv_top_margin_property;
#line 1521
      __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 1521
      if (__cil_tmp23 == __cil_tmp21) {
        {
#line 1521
        __cil_tmp24 = intel_tv->margin[1];
#line 1521
        __cil_tmp25 = (uint64_t )__cil_tmp24;
#line 1521
        if (__cil_tmp25 != val) {
#line 1523
          intel_tv->margin[1] = (int )val;
#line 1524
          changed = (bool )1;
        } else {
#line 1521
          goto _L___0;
        }
        }
      } else {
        _L___0: 
        {
#line 1525
        __cil_tmp26 = (unsigned long )property;
#line 1525
        __cil_tmp27 = dev->mode_config.tv_bottom_margin_property;
#line 1525
        __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 1525
        if (__cil_tmp28 == __cil_tmp26) {
          {
#line 1525
          __cil_tmp29 = intel_tv->margin[3];
#line 1525
          __cil_tmp30 = (uint64_t )__cil_tmp29;
#line 1525
          if (__cil_tmp30 != val) {
#line 1527
            intel_tv->margin[3] = (int )val;
#line 1528
            changed = (bool )1;
          } else {
#line 1525
            goto _L;
          }
          }
        } else {
          _L: 
          {
#line 1529
          __cil_tmp31 = (unsigned long )property;
#line 1529
          __cil_tmp32 = dev->mode_config.tv_mode_property;
#line 1529
          __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 1529
          if (__cil_tmp33 == __cil_tmp31) {
#line 1530
            if (val > 14ULL) {
#line 1531
              ret = -22;
#line 1532
              goto out;
            } else {

            }
            {
#line 1534
            __cil_tmp34 = intel_tv->tv_format;
#line 1534
            __cil_tmp35 = (char const   *)tv_modes[val].name;
#line 1534
            tmp___0 = strcmp(__cil_tmp34, __cil_tmp35);
            }
#line 1534
            if (tmp___0 == 0) {
#line 1535
              goto out;
            } else {

            }
#line 1537
            intel_tv->tv_format = (char const   *)tv_modes[val].name;
#line 1538
            changed = (bool )1;
          } else {
#line 1540
            ret = -22;
#line 1541
            goto out;
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
#line 1544
  if ((int )changed) {
    {
#line 1544
    __cil_tmp36 = (struct drm_crtc *)0;
#line 1544
    __cil_tmp37 = (unsigned long )__cil_tmp36;
#line 1544
    __cil_tmp38 = (unsigned long )crtc;
#line 1544
    if (__cil_tmp38 != __cil_tmp37) {
      {
#line 1545
      __cil_tmp39 = & crtc->mode;
#line 1545
      __cil_tmp40 = crtc->x;
#line 1545
      __cil_tmp41 = crtc->y;
#line 1545
      __cil_tmp42 = crtc->fb;
#line 1545
      drm_crtc_helper_set_mode(crtc, __cil_tmp39, __cil_tmp40, __cil_tmp41, __cil_tmp42);
      }
    } else {

    }
    }
  } else {

  }
  out: ;
#line 1548
  return (ret);
}
}
#line 1551 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct drm_encoder_helper_funcs  const  intel_tv_helper_funcs  = 
#line 1551
     {& intel_tv_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_tv_mode_fixup, & intel_encoder_prepare, & intel_encoder_commit, & intel_tv_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 1559 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct drm_connector_funcs  const  intel_tv_connector_funcs  = 
#line 1559
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    (void (*)(struct drm_connector * ))0, & intel_tv_detect, & drm_helper_probe_single_connector_modes,
    & intel_tv_set_property, & intel_tv_destroy, (void (*)(struct drm_connector * ))0};
#line 1567 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct drm_connector_helper_funcs  const  intel_tv_connector_helper_funcs  =    {& intel_tv_get_modes,
    (int (*)(struct drm_connector * , struct drm_display_mode * ))(& intel_tv_mode_valid),
    & intel_best_encoder};
#line 1573 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static struct drm_encoder_funcs  const  intel_tv_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_encoder_destroy};
#line 1584 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
static int tv_is_present_in_vbt(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct child_device_config *p_child ;
  int i ;
  int ret ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct child_device_config *__cil_tmp9 ;
  u16 __cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  u16 __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  u16 __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  int __cil_tmp16 ;

  {
#line 1586
  __cil_tmp6 = dev->dev_private;
#line 1586
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
  {
#line 1590
  __cil_tmp7 = dev_priv->child_dev_num;
#line 1590
  if (__cil_tmp7 == 0) {
#line 1591
    return (1);
  } else {

  }
  }
#line 1593
  ret = 0;
#line 1594
  i = 0;
#line 1594
  goto ldv_38013;
  ldv_38012: 
#line 1595
  __cil_tmp8 = (unsigned long )i;
#line 1595
  __cil_tmp9 = dev_priv->child_dev;
#line 1595
  p_child = __cil_tmp9 + __cil_tmp8;
  {
#line 1599
  __cil_tmp10 = p_child->device_type;
#line 1599
  __cil_tmp11 = (unsigned int )__cil_tmp10;
#line 1599
  if (__cil_tmp11 != 4105U) {
    {
#line 1599
    __cil_tmp12 = p_child->device_type;
#line 1599
    __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 1599
    if (__cil_tmp13 != 9U) {
#line 1601
      goto ldv_38010;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1605
  __cil_tmp14 = p_child->addin_offset;
#line 1605
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 1605
  if (__cil_tmp15 != 0U) {
#line 1606
    ret = 1;
#line 1607
    goto ldv_38011;
  } else {

  }
  }
  ldv_38010: 
#line 1594
  i = i + 1;
  ldv_38013: ;
  {
#line 1594
  __cil_tmp16 = dev_priv->child_dev_num;
#line 1594
  if (__cil_tmp16 > i) {
#line 1595
    goto ldv_38012;
  } else {
#line 1597
    goto ldv_38011;
  }
  }
  ldv_38011: ;
#line 1610
  return (ret);
}
}
#line 1614 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_tv.c.p"
void intel_tv_init(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct drm_connector *connector ;
  struct intel_tv *intel_tv ;
  struct intel_encoder *intel_encoder ;
  struct intel_connector *intel_connector ;
  u32 tv_dac_on ;
  u32 tv_dac_off ;
  u32 save_tv_dac ;
  char *tv_format_names___0[15U] ;
  int i ;
  int initial_mode ;
  u32 tmp ;
  int tmp___0 ;
  void *tmp___1 ;
  void *tmp___2 ;
  void *__cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned char *__cil_tmp19 ;
  unsigned char *__cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  struct intel_tv *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  struct intel_connector *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  void const   *__cil_tmp33 ;
  struct drm_encoder *__cil_tmp34 ;
  struct drm_encoder *__cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  char **__cil_tmp37 ;
  struct drm_property *__cil_tmp38 ;
  uint64_t __cil_tmp39 ;
  struct drm_property *__cil_tmp40 ;
  int __cil_tmp41 ;
  uint64_t __cil_tmp42 ;
  struct drm_property *__cil_tmp43 ;
  int __cil_tmp44 ;
  uint64_t __cil_tmp45 ;
  struct drm_property *__cil_tmp46 ;
  int __cil_tmp47 ;
  uint64_t __cil_tmp48 ;
  struct drm_property *__cil_tmp49 ;
  int __cil_tmp50 ;
  uint64_t __cil_tmp51 ;

  {
  {
#line 1616
  __cil_tmp17 = dev->dev_private;
#line 1616
  dev_priv = (struct drm_i915_private *)__cil_tmp17;
#line 1623
  initial_mode = 0;
#line 1625
  tmp = i915_read32___11(dev_priv, 425984U);
  }
  {
#line 1625
  __cil_tmp18 = tmp & 48U;
#line 1625
  if (__cil_tmp18 == 32U) {
#line 1626
    return;
  } else {

  }
  }
  {
#line 1628
  tmp___0 = tv_is_present_in_vbt(dev);
  }
#line 1628
  if (tmp___0 == 0) {
    {
#line 1629
    drm_ut_debug_printk(4U, "drm", "intel_tv_init", "Integrated TV is not present.\n");
    }
#line 1630
    return;
  } else {

  }
  {
#line 1633
  __cil_tmp19 = (unsigned char *)dev_priv;
#line 1633
  __cil_tmp20 = __cil_tmp19 + 2072UL;
#line 1633
  __cil_tmp21 = *__cil_tmp20;
#line 1633
  __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 1633
  if (__cil_tmp22 == 0U) {
#line 1634
    return;
  } else {

  }
  }
  {
#line 1640
  save_tv_dac = i915_read32___11(dev_priv, 425988U);
#line 1642
  __cil_tmp23 = save_tv_dac | 134217728U;
#line 1642
  i915_write32___9(dev_priv, 425988U, __cil_tmp23);
#line 1643
  tv_dac_on = i915_read32___11(dev_priv, 425988U);
#line 1645
  __cil_tmp24 = save_tv_dac & 4160749567U;
#line 1645
  i915_write32___9(dev_priv, 425988U, __cil_tmp24);
#line 1646
  tv_dac_off = i915_read32___11(dev_priv, 425988U);
#line 1648
  i915_write32___9(dev_priv, 425988U, save_tv_dac);
  }
  {
#line 1655
  __cil_tmp25 = tv_dac_on & 134217728U;
#line 1655
  if (__cil_tmp25 == 0U) {
#line 1657
    return;
  } else {
    {
#line 1655
    __cil_tmp26 = tv_dac_off & 134217728U;
#line 1655
    if (__cil_tmp26 != 0U) {
#line 1657
      return;
    } else {

    }
    }
  }
  }
  {
#line 1659
  tmp___1 = kzalloc(1064UL, 208U);
#line 1659
  intel_tv = (struct intel_tv *)tmp___1;
  }
  {
#line 1660
  __cil_tmp27 = (struct intel_tv *)0;
#line 1660
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 1660
  __cil_tmp29 = (unsigned long )intel_tv;
#line 1660
  if (__cil_tmp29 == __cil_tmp28) {
#line 1661
    return;
  } else {

  }
  }
  {
#line 1664
  tmp___2 = kzalloc(1576UL, 208U);
#line 1664
  intel_connector = (struct intel_connector *)tmp___2;
  }
  {
#line 1665
  __cil_tmp30 = (struct intel_connector *)0;
#line 1665
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 1665
  __cil_tmp32 = (unsigned long )intel_connector;
#line 1665
  if (__cil_tmp32 == __cil_tmp31) {
    {
#line 1666
    __cil_tmp33 = (void const   *)intel_tv;
#line 1666
    kfree(__cil_tmp33);
    }
#line 1667
    return;
  } else {

  }
  }
  {
#line 1670
  intel_encoder = & intel_tv->base;
#line 1671
  connector = & intel_connector->base;
#line 1682
  connector->polled = (uint8_t )2U;
#line 1684
  drm_connector_init(dev, connector, & intel_tv_connector_funcs, 6);
#line 1687
  __cil_tmp34 = & intel_encoder->base;
#line 1687
  drm_encoder_init(dev, __cil_tmp34, & intel_tv_enc_funcs, 4);
#line 1690
  intel_connector_attach_encoder(intel_connector, intel_encoder);
#line 1691
  intel_encoder->type = 5;
#line 1692
  intel_encoder->crtc_mask = 3;
#line 1693
  intel_encoder->clone_mask = 1024;
#line 1694
  intel_encoder->base.possible_crtcs = 3U;
#line 1695
  intel_encoder->base.possible_clones = 32U;
#line 1696
  intel_tv->type = 0;
#line 1699
  intel_tv->margin[0] = 54;
#line 1700
  intel_tv->margin[1] = 36;
#line 1701
  intel_tv->margin[2] = 46;
#line 1702
  intel_tv->margin[3] = 37;
#line 1704
  intel_tv->tv_format = (char const   *)tv_modes[initial_mode].name;
#line 1706
  __cil_tmp35 = & intel_encoder->base;
#line 1706
  drm_encoder_helper_add(__cil_tmp35, & intel_tv_helper_funcs);
#line 1707
  drm_connector_helper_add(connector, & intel_tv_connector_helper_funcs);
#line 1708
  connector->interlace_allowed = (bool )0;
#line 1709
  connector->doublescan_allowed = (bool )0;
#line 1712
  i = 0;
  }
#line 1712
  goto ldv_38034;
  ldv_38033: 
#line 1713
  tv_format_names___0[i] = (char *)tv_modes[i].name;
#line 1712
  i = i + 1;
  ldv_38034: ;
  {
#line 1712
  __cil_tmp36 = (unsigned int )i;
#line 1712
  if (__cil_tmp36 <= 14U) {
#line 1713
    goto ldv_38033;
  } else {
#line 1715
    goto ldv_38035;
  }
  }
  ldv_38035: 
  {
#line 1714
  __cil_tmp37 = (char **)(& tv_format_names___0);
#line 1714
  drm_mode_create_tv_properties(dev, 15, __cil_tmp37);
#line 1718
  __cil_tmp38 = dev->mode_config.tv_mode_property;
#line 1718
  __cil_tmp39 = (uint64_t )initial_mode;
#line 1718
  drm_connector_attach_property(connector, __cil_tmp38, __cil_tmp39);
#line 1720
  __cil_tmp40 = dev->mode_config.tv_left_margin_property;
#line 1720
  __cil_tmp41 = intel_tv->margin[0];
#line 1720
  __cil_tmp42 = (uint64_t )__cil_tmp41;
#line 1720
  drm_connector_attach_property(connector, __cil_tmp40, __cil_tmp42);
#line 1723
  __cil_tmp43 = dev->mode_config.tv_top_margin_property;
#line 1723
  __cil_tmp44 = intel_tv->margin[1];
#line 1723
  __cil_tmp45 = (uint64_t )__cil_tmp44;
#line 1723
  drm_connector_attach_property(connector, __cil_tmp43, __cil_tmp45);
#line 1726
  __cil_tmp46 = dev->mode_config.tv_right_margin_property;
#line 1726
  __cil_tmp47 = intel_tv->margin[2];
#line 1726
  __cil_tmp48 = (uint64_t )__cil_tmp47;
#line 1726
  drm_connector_attach_property(connector, __cil_tmp46, __cil_tmp48);
#line 1729
  __cil_tmp49 = dev->mode_config.tv_bottom_margin_property;
#line 1729
  __cil_tmp50 = intel_tv->margin[3];
#line 1729
  __cil_tmp51 = (uint64_t )__cil_tmp50;
#line 1729
  drm_connector_attach_property(connector, __cil_tmp49, __cil_tmp51);
#line 1732
  drm_sysfs_connector_add(connector);
  }
#line 1733
  return;
}
}
#line 138 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/dvo.h"
struct intel_dvo_dev_ops sil164_ops ;
#line 139
struct intel_dvo_dev_ops ch7xxx_ops ;
#line 140
struct intel_dvo_dev_ops ivch_ops ;
#line 141
struct intel_dvo_dev_ops tfp410_ops ;
#line 142
struct intel_dvo_dev_ops ch7017_ops ;
#line 49 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct intel_dvo_device  const  intel_dvo_devices[5U]  = {      {"sil164", 2, 397664U, 0U, 56, (struct intel_dvo_dev_ops  const  *)(& sil164_ops),
      (void *)0, (struct i2c_adapter *)0}, 
        {"ch7xxx", 2, 397664U, 0U, 118, (struct intel_dvo_dev_ops  const  *)(& ch7xxx_ops),
      (void *)0, (struct i2c_adapter *)0}, 
        {"ivch", 1, 397600U, 0U, 2, (struct intel_dvo_dev_ops  const  *)(& ivch_ops),
      (void *)0, (struct i2c_adapter *)0}, 
        {"tfp410", 2, 397664U, 0U, 56, (struct intel_dvo_dev_ops  const  *)(& tfp410_ops),
      (void *)0, (struct i2c_adapter *)0}, 
        {"ch7017", 1, 397664U, 5U, 117, (struct intel_dvo_dev_ops  const  *)(& ch7017_ops),
      (void *)0, (struct i2c_adapter *)0}};
#line 97 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct intel_dvo *enc_to_intel_dvo(struct drm_encoder *encoder ) 
{ struct drm_encoder  const  *__mptr ;

  {
#line 99
  __mptr = (struct drm_encoder  const  *)encoder;
#line 99
  return ((struct intel_dvo *)__mptr);
}
}
#line 102 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector ) 
{ struct intel_encoder  const  *__mptr ;
  struct intel_encoder *tmp ;

  {
  {
#line 104
  tmp = intel_attached_encoder(connector);
#line 104
  __mptr = (struct intel_encoder  const  *)tmp;
  }
#line 104
  return ((struct intel_dvo *)__mptr);
}
}
#line 108 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static void intel_dvo_dpms(struct drm_encoder *encoder , int mode ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  u32 dvo_reg ;
  u32 temp ;
  u32 tmp___0 ;
  struct drm_device *__cil_tmp9 ;
  void *__cil_tmp10 ;
  unsigned int __cil_tmp11 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp12 ;
  void (*__cil_tmp13)(struct intel_dvo_device * , int  ) ;
  struct intel_dvo_device *__cil_tmp14 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp15 ;
  void (*__cil_tmp16)(struct intel_dvo_device * , int  ) ;
  struct intel_dvo_device *__cil_tmp17 ;
  unsigned int __cil_tmp18 ;

  {
  {
#line 110
  __cil_tmp9 = encoder->dev;
#line 110
  __cil_tmp10 = __cil_tmp9->dev_private;
#line 110
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 111
  tmp = enc_to_intel_dvo(encoder);
#line 111
  intel_dvo = tmp;
#line 112
  dvo_reg = intel_dvo->dev.dvo_reg;
#line 113
  tmp___0 = i915_read32___13(dev_priv, dvo_reg);
#line 113
  temp = tmp___0;
  }
#line 115
  if (mode == 0) {
    {
#line 116
    __cil_tmp11 = temp | 2147483648U;
#line 116
    i915_write32___11(dev_priv, dvo_reg, __cil_tmp11);
#line 117
    i915_read32___13(dev_priv, dvo_reg);
#line 118
    __cil_tmp12 = intel_dvo->dev.dev_ops;
#line 118
    __cil_tmp13 = __cil_tmp12->dpms;
#line 118
    __cil_tmp14 = & intel_dvo->dev;
#line 118
    (*__cil_tmp13)(__cil_tmp14, mode);
    }
  } else {
    {
#line 120
    __cil_tmp15 = intel_dvo->dev.dev_ops;
#line 120
    __cil_tmp16 = __cil_tmp15->dpms;
#line 120
    __cil_tmp17 = & intel_dvo->dev;
#line 120
    (*__cil_tmp16)(__cil_tmp17, mode);
#line 121
    __cil_tmp18 = temp & 2147483647U;
#line 121
    i915_write32___11(dev_priv, dvo_reg, __cil_tmp18);
#line 122
    i915_read32___13(dev_priv, dvo_reg);
    }
  }
#line 124
  return;
}
}
#line 126 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static int intel_dvo_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) 
{ struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  int tmp___0 ;
  unsigned int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  struct drm_display_mode *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct drm_display_mode *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct drm_display_mode *__cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  struct drm_display_mode *__cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp18 ;
  int (*__cil_tmp19)(struct intel_dvo_device * , struct drm_display_mode * ) ;
  struct intel_dvo_device *__cil_tmp20 ;

  {
  {
#line 129
  tmp = intel_attached_dvo(connector);
#line 129
  intel_dvo = tmp;
  }
  {
#line 131
  __cil_tmp6 = mode->flags;
#line 131
  __cil_tmp7 = __cil_tmp6 & 32U;
#line 131
  if (__cil_tmp7 != 0U) {
#line 132
    return (8);
  } else {

  }
  }
  {
#line 136
  __cil_tmp8 = (struct drm_display_mode *)0;
#line 136
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 136
  __cil_tmp10 = intel_dvo->panel_fixed_mode;
#line 136
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 136
  if (__cil_tmp11 != __cil_tmp9) {
    {
#line 137
    __cil_tmp12 = intel_dvo->panel_fixed_mode;
#line 137
    __cil_tmp13 = __cil_tmp12->hdisplay;
#line 137
    __cil_tmp14 = mode->hdisplay;
#line 137
    if (__cil_tmp14 > __cil_tmp13) {
#line 138
      return (29);
    } else {

    }
    }
    {
#line 139
    __cil_tmp15 = intel_dvo->panel_fixed_mode;
#line 139
    __cil_tmp16 = __cil_tmp15->vdisplay;
#line 139
    __cil_tmp17 = mode->vdisplay;
#line 139
    if (__cil_tmp17 > __cil_tmp16) {
#line 140
      return (29);
    } else {

    }
    }
  } else {

  }
  }
  {
#line 143
  __cil_tmp18 = intel_dvo->dev.dev_ops;
#line 143
  __cil_tmp19 = __cil_tmp18->mode_valid;
#line 143
  __cil_tmp20 = & intel_dvo->dev;
#line 143
  tmp___0 = (*__cil_tmp19)(__cil_tmp20, mode);
  }
#line 143
  return (tmp___0);
}
}
#line 146 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static bool intel_dvo_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                                 struct drm_display_mode *adjusted_mode ) 
{ struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  bool tmp___0 ;
  struct drm_display_mode *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct drm_display_mode *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct drm_display_mode *__cil_tmp11 ;
  struct drm_display_mode *__cil_tmp12 ;
  struct drm_display_mode *__cil_tmp13 ;
  struct drm_display_mode *__cil_tmp14 ;
  struct drm_display_mode *__cil_tmp15 ;
  struct drm_display_mode *__cil_tmp16 ;
  struct drm_display_mode *__cil_tmp17 ;
  struct drm_display_mode *__cil_tmp18 ;
  struct drm_display_mode *__cil_tmp19 ;
  bool (*__cil_tmp20)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ) ;
  unsigned long __cil_tmp21 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp22 ;
  bool (*__cil_tmp23)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ) ;
  unsigned long __cil_tmp24 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp25 ;
  bool (*__cil_tmp26)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ) ;
  struct intel_dvo_device *__cil_tmp27 ;

  {
  {
#line 150
  tmp = enc_to_intel_dvo(encoder);
#line 150
  intel_dvo = tmp;
  }
  {
#line 157
  __cil_tmp7 = (struct drm_display_mode *)0;
#line 157
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 157
  __cil_tmp9 = intel_dvo->panel_fixed_mode;
#line 157
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 157
  if (__cil_tmp10 != __cil_tmp8) {
    {
#line 159
    __cil_tmp11 = intel_dvo->panel_fixed_mode;
#line 159
    adjusted_mode->hdisplay = __cil_tmp11->hdisplay;
#line 160
    __cil_tmp12 = intel_dvo->panel_fixed_mode;
#line 160
    adjusted_mode->hsync_start = __cil_tmp12->hsync_start;
#line 161
    __cil_tmp13 = intel_dvo->panel_fixed_mode;
#line 161
    adjusted_mode->hsync_end = __cil_tmp13->hsync_end;
#line 162
    __cil_tmp14 = intel_dvo->panel_fixed_mode;
#line 162
    adjusted_mode->htotal = __cil_tmp14->htotal;
#line 163
    __cil_tmp15 = intel_dvo->panel_fixed_mode;
#line 163
    adjusted_mode->vdisplay = __cil_tmp15->vdisplay;
#line 164
    __cil_tmp16 = intel_dvo->panel_fixed_mode;
#line 164
    adjusted_mode->vsync_start = __cil_tmp16->vsync_start;
#line 165
    __cil_tmp17 = intel_dvo->panel_fixed_mode;
#line 165
    adjusted_mode->vsync_end = __cil_tmp17->vsync_end;
#line 166
    __cil_tmp18 = intel_dvo->panel_fixed_mode;
#line 166
    adjusted_mode->vtotal = __cil_tmp18->vtotal;
#line 167
    __cil_tmp19 = intel_dvo->panel_fixed_mode;
#line 167
    adjusted_mode->clock = __cil_tmp19->clock;
#line 168
    drm_mode_set_crtcinfo(adjusted_mode, 1);
    }
  } else {

  }
  }
  {
#line 172
  __cil_tmp20 = (bool (* const  )(struct intel_dvo_device * , struct drm_display_mode * ,
                                  struct drm_display_mode * ))0;
#line 172
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 172
  __cil_tmp22 = intel_dvo->dev.dev_ops;
#line 172
  __cil_tmp23 = __cil_tmp22->mode_fixup;
#line 172
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 172
  if (__cil_tmp24 != __cil_tmp21) {
    {
#line 173
    __cil_tmp25 = intel_dvo->dev.dev_ops;
#line 173
    __cil_tmp26 = __cil_tmp25->mode_fixup;
#line 173
    __cil_tmp27 = & intel_dvo->dev;
#line 173
    tmp___0 = (*__cil_tmp26)(__cil_tmp27, mode, adjusted_mode);
    }
#line 173
    return (tmp___0);
  } else {

  }
  }
#line 175
  return ((bool )1);
}
}
#line 178 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static void intel_dvo_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode ,
                               struct drm_display_mode *adjusted_mode ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_crtc *intel_crtc ;
  struct drm_crtc  const  *__mptr ;
  struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  int pipe ;
  u32 dvo_val ;
  u32 dvo_reg ;
  u32 dvo_srcdim_reg ;
  int dpll_reg ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  void *__cil_tmp17 ;
  struct drm_crtc *__cil_tmp18 ;
  enum pipe __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp24 ;
  void (*__cil_tmp25)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ) ;
  struct intel_dvo_device *__cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  u32 __cil_tmp31 ;
  u32 __cil_tmp32 ;
  unsigned int __cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  u32 __cil_tmp38 ;

  {
  {
#line 182
  dev = encoder->dev;
#line 183
  __cil_tmp17 = dev->dev_private;
#line 183
  dev_priv = (struct drm_i915_private *)__cil_tmp17;
#line 184
  __cil_tmp18 = encoder->crtc;
#line 184
  __mptr = (struct drm_crtc  const  *)__cil_tmp18;
#line 184
  intel_crtc = (struct intel_crtc *)__mptr;
#line 185
  tmp = enc_to_intel_dvo(encoder);
#line 185
  intel_dvo = tmp;
#line 186
  __cil_tmp19 = intel_crtc->pipe;
#line 186
  pipe = (int )__cil_tmp19;
#line 188
  dvo_reg = intel_dvo->dev.dvo_reg;
#line 189
  __cil_tmp20 = pipe + 6149;
#line 189
  dpll_reg = __cil_tmp20 * 4;
  }
  {
#line 192
  __cil_tmp21 = (int )dvo_reg;
#line 192
  if (__cil_tmp21 == 397600) {
#line 192
    goto case_397600;
  } else {
    {
#line 196
    __cil_tmp22 = (int )dvo_reg;
#line 196
    if (__cil_tmp22 == 397632) {
#line 196
      goto case_397632;
    } else {
      {
#line 199
      __cil_tmp23 = (int )dvo_reg;
#line 199
      if (__cil_tmp23 == 397664) {
#line 199
        goto case_397664;
      } else {
#line 193
        goto switch_default;
#line 191
        if (0) {
          case_397600: ;
          switch_default: 
#line 194
          dvo_srcdim_reg = 397604U;
#line 195
          goto ldv_37647;
          case_397632: 
#line 197
          dvo_srcdim_reg = 397636U;
#line 198
          goto ldv_37647;
          case_397664: 
#line 200
          dvo_srcdim_reg = 397668U;
#line 201
          goto ldv_37647;
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_37647: 
  {
#line 204
  __cil_tmp24 = intel_dvo->dev.dev_ops;
#line 204
  __cil_tmp25 = __cil_tmp24->mode_set;
#line 204
  __cil_tmp26 = & intel_dvo->dev;
#line 204
  (*__cil_tmp25)(__cil_tmp26, mode, adjusted_mode);
#line 207
  tmp___0 = i915_read32___13(dev_priv, dvo_reg);
#line 207
  dvo_val = tmp___0 & 117440576U;
#line 209
  dvo_val = dvo_val | 16516U;
  }
#line 212
  if (pipe == 1) {
#line 213
    dvo_val = dvo_val | 1073741824U;
  } else {

  }
#line 214
  dvo_val = dvo_val | 268435456U;
  {
#line 215
  __cil_tmp27 = adjusted_mode->flags;
#line 215
  __cil_tmp28 = (int )__cil_tmp27;
#line 215
  if (__cil_tmp28 & 1) {
#line 216
    dvo_val = dvo_val | 8U;
  } else {

  }
  }
  {
#line 217
  __cil_tmp29 = adjusted_mode->flags;
#line 217
  __cil_tmp30 = __cil_tmp29 & 4U;
#line 217
  if (__cil_tmp30 != 0U) {
#line 218
    dvo_val = dvo_val | 16U;
  } else {

  }
  }
  {
#line 220
  __cil_tmp31 = (u32 )dpll_reg;
#line 220
  tmp___1 = i915_read32___13(dev_priv, __cil_tmp31);
#line 220
  __cil_tmp32 = (u32 )dpll_reg;
#line 220
  __cil_tmp33 = tmp___1 | 1073741824U;
#line 220
  i915_write32___11(dev_priv, __cil_tmp32, __cil_tmp33);
#line 225
  __cil_tmp34 = adjusted_mode->vdisplay;
#line 225
  __cil_tmp35 = adjusted_mode->hdisplay;
#line 225
  __cil_tmp36 = __cil_tmp35 << 12;
#line 225
  __cil_tmp37 = __cil_tmp36 | __cil_tmp34;
#line 225
  __cil_tmp38 = (u32 )__cil_tmp37;
#line 225
  i915_write32___11(dev_priv, dvo_srcdim_reg, __cil_tmp38);
#line 229
  i915_write32___11(dev_priv, dvo_reg, dvo_val);
  }
#line 230
  return;
}
}
#line 238 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector ,
                                                  bool force ) 
{ struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  enum drm_connector_status tmp___0 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp6 ;
  enum drm_connector_status (*__cil_tmp7)(struct intel_dvo_device * ) ;
  struct intel_dvo_device *__cil_tmp8 ;

  {
  {
#line 240
  tmp = intel_attached_dvo(connector);
#line 240
  intel_dvo = tmp;
#line 241
  __cil_tmp6 = intel_dvo->dev.dev_ops;
#line 241
  __cil_tmp7 = __cil_tmp6->detect;
#line 241
  __cil_tmp8 = & intel_dvo->dev;
#line 241
  tmp___0 = (*__cil_tmp7)(__cil_tmp8);
  }
#line 241
  return (tmp___0);
}
}
#line 244 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static int intel_dvo_get_modes(struct drm_connector *connector ) 
{ struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  struct drm_i915_private *dev_priv ;
  int tmp___0 ;
  struct drm_display_mode *mode ;
  struct drm_device *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct intel_gmbus *__cil_tmp9 ;
  struct intel_gmbus *__cil_tmp10 ;
  struct i2c_adapter *__cil_tmp11 ;
  struct list_head *__cil_tmp12 ;
  struct list_head  const  *__cil_tmp13 ;
  struct drm_display_mode *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct drm_display_mode *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_device *__cil_tmp18 ;
  struct drm_display_mode *__cil_tmp19 ;
  struct drm_display_mode  const  *__cil_tmp20 ;
  struct drm_display_mode *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;

  {
  {
#line 246
  tmp = intel_attached_dvo(connector);
#line 246
  intel_dvo = tmp;
#line 247
  __cil_tmp7 = connector->dev;
#line 247
  __cil_tmp8 = __cil_tmp7->dev_private;
#line 247
  dev_priv = (struct drm_i915_private *)__cil_tmp8;
#line 254
  __cil_tmp9 = dev_priv->gmbus;
#line 254
  __cil_tmp10 = __cil_tmp9 + 4UL;
#line 254
  __cil_tmp11 = & __cil_tmp10->adapter;
#line 254
  intel_ddc_get_modes(connector, __cil_tmp11);
#line 256
  __cil_tmp12 = & connector->probed_modes;
#line 256
  __cil_tmp13 = (struct list_head  const  *)__cil_tmp12;
#line 256
  tmp___0 = list_empty(__cil_tmp13);
  }
#line 256
  if (tmp___0 == 0) {
#line 257
    return (1);
  } else {

  }
  {
#line 259
  __cil_tmp14 = (struct drm_display_mode *)0;
#line 259
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 259
  __cil_tmp16 = intel_dvo->panel_fixed_mode;
#line 259
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 259
  if (__cil_tmp17 != __cil_tmp15) {
    {
#line 261
    __cil_tmp18 = connector->dev;
#line 261
    __cil_tmp19 = intel_dvo->panel_fixed_mode;
#line 261
    __cil_tmp20 = (struct drm_display_mode  const  *)__cil_tmp19;
#line 261
    mode = drm_mode_duplicate(__cil_tmp18, __cil_tmp20);
    }
    {
#line 262
    __cil_tmp21 = (struct drm_display_mode *)0;
#line 262
    __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 262
    __cil_tmp23 = (unsigned long )mode;
#line 262
    if (__cil_tmp23 != __cil_tmp22) {
      {
#line 263
      drm_mode_probed_add(connector, mode);
      }
#line 264
      return (1);
    } else {

    }
    }
  } else {

  }
  }
#line 268
  return (0);
}
}
#line 271 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static void intel_dvo_destroy(struct drm_connector *connector ) 
{ void const   *__cil_tmp2 ;

  {
  {
#line 273
  drm_sysfs_connector_remove(connector);
#line 274
  drm_connector_cleanup(connector);
#line 275
  __cil_tmp2 = (void const   *)connector;
#line 275
  kfree(__cil_tmp2);
  }
#line 276
  return;
}
}
#line 278 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct drm_encoder_helper_funcs  const  intel_dvo_helper_funcs  = 
#line 278
     {& intel_dvo_dpms, (void (*)(struct drm_encoder * ))0, (void (*)(struct drm_encoder * ))0,
    & intel_dvo_mode_fixup, & intel_encoder_prepare, & intel_encoder_commit, & intel_dvo_mode_set,
    (struct drm_crtc *(*)(struct drm_encoder * ))0, (enum drm_connector_status (*)(struct drm_encoder * ,
                                                                                   struct drm_connector * ))0,
    (void (*)(struct drm_encoder * ))0};
#line 286 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct drm_connector_funcs  const  intel_dvo_connector_funcs  = 
#line 286
     {& drm_helper_connector_dpms, (void (*)(struct drm_connector * ))0, (void (*)(struct drm_connector * ))0,
    (void (*)(struct drm_connector * ))0, & intel_dvo_detect, & drm_helper_probe_single_connector_modes,
    (int (*)(struct drm_connector * , struct drm_property * , uint64_t  ))0, & intel_dvo_destroy,
    (void (*)(struct drm_connector * ))0};
#line 293 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct drm_connector_helper_funcs  const  intel_dvo_connector_helper_funcs  =    {& intel_dvo_get_modes,
    & intel_dvo_mode_valid, & intel_best_encoder};
#line 299 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static void intel_dvo_enc_destroy(struct drm_encoder *encoder ) 
{ struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  void (*__cil_tmp4)(struct intel_dvo_device * ) ;
  unsigned long __cil_tmp5 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp6 ;
  void (*__cil_tmp7)(struct intel_dvo_device * ) ;
  unsigned long __cil_tmp8 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp9 ;
  void (*__cil_tmp10)(struct intel_dvo_device * ) ;
  struct intel_dvo_device *__cil_tmp11 ;
  struct drm_display_mode *__cil_tmp12 ;
  void const   *__cil_tmp13 ;

  {
  {
#line 301
  tmp = enc_to_intel_dvo(encoder);
#line 301
  intel_dvo = tmp;
  }
  {
#line 303
  __cil_tmp4 = (void (* const  )(struct intel_dvo_device * ))0;
#line 303
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 303
  __cil_tmp6 = intel_dvo->dev.dev_ops;
#line 303
  __cil_tmp7 = __cil_tmp6->destroy;
#line 303
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 303
  if (__cil_tmp8 != __cil_tmp5) {
    {
#line 304
    __cil_tmp9 = intel_dvo->dev.dev_ops;
#line 304
    __cil_tmp10 = __cil_tmp9->destroy;
#line 304
    __cil_tmp11 = & intel_dvo->dev;
#line 304
    (*__cil_tmp10)(__cil_tmp11);
    }
  } else {

  }
  }
  {
#line 306
  __cil_tmp12 = intel_dvo->panel_fixed_mode;
#line 306
  __cil_tmp13 = (void const   *)__cil_tmp12;
#line 306
  kfree(__cil_tmp13);
#line 308
  intel_encoder_destroy(encoder);
  }
#line 309
  return;
}
}
#line 311 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct drm_encoder_funcs  const  intel_dvo_enc_funcs  =    {(void (*)(struct drm_encoder * ))0, & intel_dvo_enc_destroy};
#line 322 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
static struct drm_display_mode *intel_dvo_get_current_mode(struct drm_connector *connector ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct intel_dvo *intel_dvo ;
  struct intel_dvo *tmp ;
  uint32_t dvo_val ;
  u32 tmp___0 ;
  struct drm_display_mode *mode ;
  struct drm_crtc *crtc ;
  int pipe ;
  void *__cil_tmp11 ;
  u32 __cil_tmp12 ;
  int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  struct drm_crtc *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_display_mode *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  unsigned int __cil_tmp25 ;

  {
  {
#line 324
  dev = connector->dev;
#line 325
  __cil_tmp11 = dev->dev_private;
#line 325
  dev_priv = (struct drm_i915_private *)__cil_tmp11;
#line 326
  tmp = intel_attached_dvo(connector);
#line 326
  intel_dvo = tmp;
#line 327
  __cil_tmp12 = intel_dvo->dev.dvo_reg;
#line 327
  tmp___0 = i915_read32___13(dev_priv, __cil_tmp12);
#line 327
  dvo_val = tmp___0;
#line 328
  mode = (struct drm_display_mode *)0;
  }
  {
#line 333
  __cil_tmp13 = (int )dvo_val;
#line 333
  if (__cil_tmp13 < 0) {
    {
#line 335
    __cil_tmp14 = dvo_val & 1073741824U;
#line 335
    pipe = __cil_tmp14 != 0U;
#line 337
    crtc = intel_get_crtc_for_pipe(dev, pipe);
    }
    {
#line 338
    __cil_tmp15 = (struct drm_crtc *)0;
#line 338
    __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 338
    __cil_tmp17 = (unsigned long )crtc;
#line 338
    if (__cil_tmp17 != __cil_tmp16) {
      {
#line 339
      mode = intel_crtc_mode_get(dev, crtc);
      }
      {
#line 340
      __cil_tmp18 = (struct drm_display_mode *)0;
#line 340
      __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 340
      __cil_tmp20 = (unsigned long )mode;
#line 340
      if (__cil_tmp20 != __cil_tmp19) {
#line 341
        __cil_tmp21 = mode->type;
#line 341
        mode->type = __cil_tmp21 | 8;
        {
#line 342
        __cil_tmp22 = dvo_val & 8U;
#line 342
        if (__cil_tmp22 != 0U) {
#line 343
          __cil_tmp23 = mode->flags;
#line 343
          mode->flags = __cil_tmp23 | 1U;
        } else {

        }
        }
        {
#line 344
        __cil_tmp24 = dvo_val & 16U;
#line 344
        if (__cil_tmp24 != 0U) {
#line 345
          __cil_tmp25 = mode->flags;
#line 345
          mode->flags = __cil_tmp25 | 4U;
        } else {

        }
        }
      } else {

      }
      }
    } else {

    }
    }
  } else {

  }
  }
#line 350
  return (mode);
}
}
#line 353 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_dvo.c.p"
void intel_dvo_init(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_encoder *intel_encoder ;
  struct intel_dvo *intel_dvo ;
  struct intel_connector *intel_connector ;
  int i ;
  int encoder_type ;
  void *tmp ;
  void *tmp___0 ;
  struct drm_connector *connector ;
  struct intel_dvo_device  const  *dvo ;
  struct i2c_adapter *i2c ;
  int gpio ;
  bool tmp___1 ;
  int tmp___2 ;
  void *__cil_tmp16 ;
  struct intel_dvo *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  struct intel_connector *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  void const   *__cil_tmp23 ;
  struct drm_encoder *__cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct intel_dvo_device  const  *__cil_tmp26 ;
  u32 __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  u32 __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  struct intel_gmbus *__cil_tmp33 ;
  struct intel_gmbus *__cil_tmp34 ;
  struct intel_dvo_device __cil_tmp35 ;
  struct intel_dvo_dev_ops  const  *__cil_tmp36 ;
  bool (*__cil_tmp37)(struct intel_dvo_device * , struct i2c_adapter * ) ;
  struct intel_dvo_device *__cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  int __cil_tmp41 ;
  int __cil_tmp42 ;
  struct drm_encoder *__cil_tmp43 ;
  int __cil_tmp44 ;
  int __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  struct drm_encoder *__cil_tmp47 ;
  void const   *__cil_tmp48 ;
  void const   *__cil_tmp49 ;

  {
  {
#line 355
  __cil_tmp16 = dev->dev_private;
#line 355
  dev_priv = (struct drm_i915_private *)__cil_tmp16;
#line 360
  encoder_type = 0;
#line 362
  tmp = kzalloc(160UL, 208U);
#line 362
  intel_dvo = (struct intel_dvo *)tmp;
  }
  {
#line 363
  __cil_tmp17 = (struct intel_dvo *)0;
#line 363
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 363
  __cil_tmp19 = (unsigned long )intel_dvo;
#line 363
  if (__cil_tmp19 == __cil_tmp18) {
#line 364
    return;
  } else {

  }
  }
  {
#line 366
  tmp___0 = kzalloc(1576UL, 208U);
#line 366
  intel_connector = (struct intel_connector *)tmp___0;
  }
  {
#line 367
  __cil_tmp20 = (struct intel_connector *)0;
#line 367
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 367
  __cil_tmp22 = (unsigned long )intel_connector;
#line 367
  if (__cil_tmp22 == __cil_tmp21) {
    {
#line 368
    __cil_tmp23 = (void const   *)intel_dvo;
#line 368
    kfree(__cil_tmp23);
    }
#line 369
    return;
  } else {

  }
  }
  {
#line 372
  intel_encoder = & intel_dvo->base;
#line 373
  __cil_tmp24 = & intel_encoder->base;
#line 373
  drm_encoder_init(dev, __cil_tmp24, & intel_dvo_enc_funcs, encoder_type);
#line 377
  i = 0;
  }
#line 377
  goto ldv_37702;
  ldv_37701: 
#line 378
  connector = & intel_connector->base;
#line 379
  __cil_tmp25 = (unsigned long )i;
#line 379
  __cil_tmp26 = (struct intel_dvo_device  const  *)(& intel_dvo_devices);
#line 379
  dvo = __cil_tmp26 + __cil_tmp25;
  {
#line 387
  __cil_tmp27 = dvo->gpio;
#line 387
  __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 387
  if (__cil_tmp28 != 0U) {
#line 388
    __cil_tmp29 = dvo->gpio;
#line 388
    gpio = (int )__cil_tmp29;
  } else {
    {
#line 389
    __cil_tmp30 = dvo->type;
#line 389
    __cil_tmp31 = (int )__cil_tmp30;
#line 389
    if (__cil_tmp31 == 1) {
#line 390
      gpio = 1;
    } else {
#line 392
      gpio = 5;
    }
    }
  }
  }
  {
#line 398
  __cil_tmp32 = (unsigned long )gpio;
#line 398
  __cil_tmp33 = dev_priv->gmbus;
#line 398
  __cil_tmp34 = __cil_tmp33 + __cil_tmp32;
#line 398
  i2c = & __cil_tmp34->adapter;
#line 400
  __cil_tmp35 = *dvo;
#line 400
  intel_dvo->dev = (struct intel_dvo_device )__cil_tmp35;
#line 401
  __cil_tmp36 = dvo->dev_ops;
#line 401
  __cil_tmp37 = __cil_tmp36->init;
#line 401
  __cil_tmp38 = & intel_dvo->dev;
#line 401
  tmp___1 = (*__cil_tmp37)(__cil_tmp38, i2c);
  }
#line 401
  if (tmp___1) {
#line 401
    tmp___2 = 0;
  } else {
#line 401
    tmp___2 = 1;
  }
#line 401
  if (tmp___2) {
#line 402
    goto ldv_37697;
  } else {

  }
#line 404
  intel_encoder->type = 2;
#line 405
  intel_encoder->crtc_mask = 3;
  {
#line 407
  __cil_tmp39 = dvo->type;
#line 407
  __cil_tmp40 = (int )__cil_tmp39;
#line 407
  if (__cil_tmp40 == 2) {
#line 407
    goto case_2;
  } else {
    {
#line 416
    __cil_tmp41 = dvo->type;
#line 416
    __cil_tmp42 = (int )__cil_tmp41;
#line 416
    if (__cil_tmp42 == 1) {
#line 416
      goto case_1;
    } else
#line 406
    if (0) {
      case_2: 
      {
#line 408
      intel_encoder->clone_mask = 33280;
#line 411
      drm_connector_init(dev, connector, & intel_dvo_connector_funcs, 2);
#line 414
      encoder_type = 2;
      }
#line 415
      goto ldv_37699;
      case_1: 
      {
#line 417
      intel_encoder->clone_mask = 65536;
#line 419
      drm_connector_init(dev, connector, & intel_dvo_connector_funcs, 7);
#line 422
      encoder_type = 3;
      }
#line 423
      goto ldv_37699;
    } else {

    }
    }
  }
  }
  ldv_37699: 
  {
#line 426
  drm_connector_helper_add(connector, & intel_dvo_connector_helper_funcs);
#line 428
  connector->display_info.subpixel_order = (enum subpixel_order )1;
#line 429
  connector->interlace_allowed = (bool )0;
#line 430
  connector->doublescan_allowed = (bool )0;
#line 432
  __cil_tmp43 = & intel_encoder->base;
#line 432
  drm_encoder_helper_add(__cil_tmp43, & intel_dvo_helper_funcs);
#line 435
  intel_connector_attach_encoder(intel_connector, intel_encoder);
  }
  {
#line 436
  __cil_tmp44 = dvo->type;
#line 436
  __cil_tmp45 = (int )__cil_tmp44;
#line 436
  if (__cil_tmp45 == 1) {
    {
#line 444
    intel_dvo->panel_fixed_mode = intel_dvo_get_current_mode(connector);
#line 446
    intel_dvo->panel_wants_dither = (bool )1;
    }
  } else {

  }
  }
  {
#line 449
  drm_sysfs_connector_add(connector);
  }
#line 450
  return;
  ldv_37697: 
#line 377
  i = i + 1;
  ldv_37702: ;
  {
#line 377
  __cil_tmp46 = (unsigned int )i;
#line 377
  if (__cil_tmp46 <= 4U) {
#line 378
    goto ldv_37701;
  } else {
#line 380
    goto ldv_37703;
  }
  }
  ldv_37703: 
  {
#line 453
  __cil_tmp47 = & intel_encoder->base;
#line 453
  drm_encoder_cleanup(__cil_tmp47);
#line 454
  __cil_tmp48 = (void const   *)intel_dvo;
#line 454
  kfree(__cil_tmp48);
#line 455
  __cil_tmp49 = (void const   *)intel_connector;
#line 455
  kfree(__cil_tmp49);
  }
#line 456
  return;
}
}
#line 344 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_ring_wait_begin(struct intel_ring_buffer *ring ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp10 ;
  struct tracepoint_func **__cil_tmp11 ;
  struct tracepoint_func * volatile  *__cil_tmp12 ;
  struct tracepoint_func * volatile  __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  struct tracepoint_func *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  void (*__cil_tmp19)(void * , struct intel_ring_buffer * ) ;
  void *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;

  {
  {
#line 341
  __cil_tmp10 = & __tracepoint_i915_ring_wait_begin.key;
#line 341
  tmp___1 = static_branch(__cil_tmp10);
  }
#line 341
  if ((int )tmp___1) {
    {
#line 341
    rcu_read_lock_sched_notrace();
#line 341
    __cil_tmp11 = & __tracepoint_i915_ring_wait_begin.funcs;
#line 341
    __cil_tmp12 = (struct tracepoint_func * volatile  *)__cil_tmp11;
#line 341
    __cil_tmp13 = *__cil_tmp12;
#line 341
    _________p1 = (struct tracepoint_func *)__cil_tmp13;
#line 341
    tmp = debug_lockdep_rcu_enabled();
    }
#line 341
    if (tmp != 0) {
#line 341
      if (! __warned) {
        {
#line 341
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 341
        if (tmp___0 == 0) {
          {
#line 341
          __warned = (bool )1;
#line 341
          __cil_tmp14 = (int const   )344;
#line 341
          __cil_tmp15 = (int )__cil_tmp14;
#line 341
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp15);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 341
    it_func_ptr = _________p1;
    {
#line 341
    __cil_tmp16 = (struct tracepoint_func *)0;
#line 341
    __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 341
    __cil_tmp18 = (unsigned long )it_func_ptr;
#line 341
    if (__cil_tmp18 != __cil_tmp17) {
      ldv_36114: 
      {
#line 341
      it_func = it_func_ptr->func;
#line 341
      __data = it_func_ptr->data;
#line 341
      __cil_tmp19 = (void (*)(void * , struct intel_ring_buffer * ))it_func;
#line 341
      (*__cil_tmp19)(__data, ring);
#line 341
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 341
      __cil_tmp20 = (void *)0;
#line 341
      __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 341
      __cil_tmp22 = it_func_ptr->func;
#line 341
      __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 341
      if (__cil_tmp23 != __cil_tmp21) {
#line 342
        goto ldv_36114;
      } else {
#line 344
        goto ldv_36115;
      }
      }
      ldv_36115: ;
    } else {

    }
    }
    {
#line 341
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 343
  return;
}
}
#line 349 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_ring_wait_end(struct intel_ring_buffer *ring ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp10 ;
  struct tracepoint_func **__cil_tmp11 ;
  struct tracepoint_func * volatile  *__cil_tmp12 ;
  struct tracepoint_func * volatile  __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  struct tracepoint_func *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  void (*__cil_tmp19)(void * , struct intel_ring_buffer * ) ;
  void *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;

  {
  {
#line 346
  __cil_tmp10 = & __tracepoint_i915_ring_wait_end.key;
#line 346
  tmp___1 = static_branch(__cil_tmp10);
  }
#line 346
  if ((int )tmp___1) {
    {
#line 346
    rcu_read_lock_sched_notrace();
#line 346
    __cil_tmp11 = & __tracepoint_i915_ring_wait_end.funcs;
#line 346
    __cil_tmp12 = (struct tracepoint_func * volatile  *)__cil_tmp11;
#line 346
    __cil_tmp13 = *__cil_tmp12;
#line 346
    _________p1 = (struct tracepoint_func *)__cil_tmp13;
#line 346
    tmp = debug_lockdep_rcu_enabled();
    }
#line 346
    if (tmp != 0) {
#line 346
      if (! __warned) {
        {
#line 346
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 346
        if (tmp___0 == 0) {
          {
#line 346
          __warned = (bool )1;
#line 346
          __cil_tmp14 = (int const   )349;
#line 346
          __cil_tmp15 = (int )__cil_tmp14;
#line 346
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp15);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 346
    it_func_ptr = _________p1;
    {
#line 346
    __cil_tmp16 = (struct tracepoint_func *)0;
#line 346
    __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 346
    __cil_tmp18 = (unsigned long )it_func_ptr;
#line 346
    if (__cil_tmp18 != __cil_tmp17) {
      ldv_36145: 
      {
#line 346
      it_func = it_func_ptr->func;
#line 346
      __data = it_func_ptr->data;
#line 346
      __cil_tmp19 = (void (*)(void * , struct intel_ring_buffer * ))it_func;
#line 346
      (*__cil_tmp19)(__data, ring);
#line 346
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 346
      __cil_tmp20 = (void *)0;
#line 346
      __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 346
      __cil_tmp22 = it_func_ptr->func;
#line 346
      __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 346
      if (__cil_tmp23 != __cil_tmp21) {
#line 347
        goto ldv_36145;
      } else {
#line 349
        goto ldv_36146;
      }
      }
      ldv_36146: ;
    } else {

    }
    }
    {
#line 346
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 348
  return;
}
}
#line 45 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
__inline static int ring_space(struct intel_ring_buffer *ring ) 
{ int space ;
  u32 __cil_tmp3 ;
  u32 __cil_tmp4 ;
  unsigned int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  int __cil_tmp8 ;

  {
#line 47
  __cil_tmp3 = ring->tail;
#line 47
  __cil_tmp4 = ring->head;
#line 47
  __cil_tmp5 = __cil_tmp4 & 2097148U;
#line 47
  __cil_tmp6 = __cil_tmp5 - __cil_tmp3;
#line 47
  __cil_tmp7 = __cil_tmp6 - 8U;
#line 47
  space = (int )__cil_tmp7;
#line 48
  if (space < 0) {
#line 49
    __cil_tmp8 = ring->size;
#line 49
    space = __cil_tmp8 + space;
  } else {

  }
#line 50
  return (space);
}
}
#line 53 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static u32 i915_gem_get_seqno(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  u32 seqno ;
  void *__cil_tmp4 ;
  uint32_t __cil_tmp5 ;
  uint32_t __cil_tmp6 ;

  {
#line 55
  __cil_tmp4 = dev->dev_private;
#line 55
  dev_priv = (drm_i915_private_t *)__cil_tmp4;
#line 58
  seqno = dev_priv->next_seqno;
#line 61
  __cil_tmp5 = dev_priv->next_seqno;
#line 61
  dev_priv->next_seqno = __cil_tmp5 + 1U;
  {
#line 61
  __cil_tmp6 = dev_priv->next_seqno;
#line 61
  if (__cil_tmp6 == 0U) {
#line 62
    dev_priv->next_seqno = 1U;
  } else {

  }
  }
#line 64
  return (seqno);
}
}
#line 68 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int render_ring_flush(struct intel_ring_buffer *ring , u32 invalidate_domains ,
                             u32 flush_domains ) 
{ struct drm_device *dev ;
  u32 cmd ;
  int ret ;
  unsigned int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  void *__cil_tmp18 ;
  struct drm_i915_private *__cil_tmp19 ;
  struct intel_device_info  const  *__cil_tmp20 ;
  unsigned char *__cil_tmp21 ;
  unsigned char *__cil_tmp22 ;
  unsigned char __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  void *__cil_tmp25 ;
  struct drm_i915_private *__cil_tmp26 ;
  struct intel_device_info  const  *__cil_tmp27 ;
  u8 __cil_tmp28 ;
  unsigned char __cil_tmp29 ;
  unsigned int __cil_tmp30 ;

  {
#line 72
  dev = ring->dev;
#line 104
  cmd = 33554436U;
  {
#line 105
  __cil_tmp7 = invalidate_domains | flush_domains;
#line 105
  __cil_tmp8 = __cil_tmp7 & 2U;
#line 105
  if (__cil_tmp8 != 0U) {
#line 107
    cmd = cmd & 4294967291U;
  } else {

  }
  }
  {
#line 108
  __cil_tmp9 = dev->dev_private;
#line 108
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 108
  __cil_tmp11 = __cil_tmp10->info;
#line 108
  __cil_tmp12 = __cil_tmp11->gen;
#line 108
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 108
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 108
  if (__cil_tmp14 <= 3U) {
    {
#line 113
    __cil_tmp15 = invalidate_domains & 4U;
#line 113
    if (__cil_tmp15 != 0U) {
#line 114
      cmd = cmd | 1U;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 116
  __cil_tmp16 = invalidate_domains & 16U;
#line 116
  if (__cil_tmp16 != 0U) {
#line 117
    cmd = cmd | 2U;
  } else {

  }
  }
  {
#line 119
  __cil_tmp17 = invalidate_domains & 8U;
#line 119
  if (__cil_tmp17 != 0U) {
    {
#line 119
    __cil_tmp18 = dev->dev_private;
#line 119
    __cil_tmp19 = (struct drm_i915_private *)__cil_tmp18;
#line 119
    __cil_tmp20 = __cil_tmp19->info;
#line 119
    __cil_tmp21 = (unsigned char *)__cil_tmp20;
#line 119
    __cil_tmp22 = __cil_tmp21 + 1UL;
#line 119
    __cil_tmp23 = *__cil_tmp22;
#line 119
    __cil_tmp24 = (unsigned int )__cil_tmp23;
#line 119
    if (__cil_tmp24 != 0U) {
#line 121
      cmd = cmd | 32U;
    } else {
      {
#line 119
      __cil_tmp25 = dev->dev_private;
#line 119
      __cil_tmp26 = (struct drm_i915_private *)__cil_tmp25;
#line 119
      __cil_tmp27 = __cil_tmp26->info;
#line 119
      __cil_tmp28 = __cil_tmp27->gen;
#line 119
      __cil_tmp29 = (unsigned char )__cil_tmp28;
#line 119
      __cil_tmp30 = (unsigned int )__cil_tmp29;
#line 119
      if (__cil_tmp30 == 5U) {
#line 121
        cmd = cmd | 32U;
      } else {

      }
      }
    }
    }
  } else {

  }
  }
  {
#line 123
  ret = intel_ring_begin(ring, 2);
  }
#line 124
  if (ret != 0) {
#line 125
    return (ret);
  } else {

  }
  {
#line 127
  intel_ring_emit(ring, cmd);
#line 128
  intel_ring_emit(ring, 0U);
#line 129
  intel_ring_advance(ring);
  }
#line 131
  return (0);
}
}
#line 134 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void ring_write_tail(struct intel_ring_buffer *ring , u32 value ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_device *__cil_tmp4 ;
  void *__cil_tmp5 ;
  u32 __cil_tmp6 ;
  u32 __cil_tmp7 ;

  {
  {
#line 137
  __cil_tmp4 = ring->dev;
#line 137
  __cil_tmp5 = __cil_tmp4->dev_private;
#line 137
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 138
  __cil_tmp6 = ring->mmio_base;
#line 138
  __cil_tmp7 = __cil_tmp6 + 48U;
#line 138
  i915_write32___11(dev_priv, __cil_tmp7, value);
  }
#line 139
  return;
}
}
#line 141 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring ) 
{ drm_i915_private_t *dev_priv ;
  u32 acthd_reg ;
  u32 tmp ;
  u32 tmp___0 ;
  struct drm_device *__cil_tmp6 ;
  void *__cil_tmp7 ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  u32 __cil_tmp15 ;

  {
#line 143
  __cil_tmp6 = ring->dev;
#line 143
  __cil_tmp7 = __cil_tmp6->dev_private;
#line 143
  dev_priv = (drm_i915_private_t *)__cil_tmp7;
  {
#line 144
  __cil_tmp8 = ring->dev;
#line 144
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 144
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 144
  __cil_tmp11 = __cil_tmp10->info;
#line 144
  __cil_tmp12 = __cil_tmp11->gen;
#line 144
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 144
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 144
  if (__cil_tmp14 > 3U) {
#line 144
    __cil_tmp15 = ring->mmio_base;
#line 144
    tmp = __cil_tmp15 + 116U;
  } else {
#line 144
    tmp = 8392U;
  }
  }
  {
#line 144
  acthd_reg = tmp;
#line 147
  tmp___0 = i915_read32___13(dev_priv, acthd_reg);
  }
#line 147
  return (tmp___0);
}
}
#line 150 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int init_ring_common(struct intel_ring_buffer *ring ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_i915_gem_object *obj ;
  u32 head ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  u32 tmp___3 ;
  u32 tmp___4 ;
  u32 tmp___5 ;
  u32 tmp___6 ;
  u32 tmp___7 ;
  u32 tmp___8 ;
  u32 tmp___9 ;
  u32 tmp___10 ;
  u32 tmp___11 ;
  u32 tmp___12 ;
  u32 tmp___13 ;
  u32 tmp___14 ;
  u32 tmp___15 ;
  u32 tmp___16 ;
  int tmp___17 ;
  struct drm_device *__cil_tmp24 ;
  void *__cil_tmp25 ;
  u32 __cil_tmp26 ;
  u32 __cil_tmp27 ;
  u32 __cil_tmp28 ;
  u32 __cil_tmp29 ;
  void (*__cil_tmp30)(struct intel_ring_buffer * , u32  ) ;
  u32 __cil_tmp31 ;
  u32 __cil_tmp32 ;
  uint32_t __cil_tmp33 ;
  u32 __cil_tmp34 ;
  u32 __cil_tmp35 ;
  u32 __cil_tmp36 ;
  u32 __cil_tmp37 ;
  u32 __cil_tmp38 ;
  u32 __cil_tmp39 ;
  u32 __cil_tmp40 ;
  u32 __cil_tmp41 ;
  u32 __cil_tmp42 ;
  u32 __cil_tmp43 ;
  char const   *__cil_tmp44 ;
  u32 __cil_tmp45 ;
  u32 __cil_tmp46 ;
  u32 __cil_tmp47 ;
  u32 __cil_tmp48 ;
  unsigned int __cil_tmp49 ;
  u32 __cil_tmp50 ;
  u32 __cil_tmp51 ;
  u32 __cil_tmp52 ;
  u32 __cil_tmp53 ;
  u32 __cil_tmp54 ;
  u32 __cil_tmp55 ;
  u32 __cil_tmp56 ;
  u32 __cil_tmp57 ;
  char const   *__cil_tmp58 ;
  u32 __cil_tmp59 ;
  u32 __cil_tmp60 ;
  int __cil_tmp61 ;
  u32 __cil_tmp62 ;
  u32 __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  unsigned int __cil_tmp65 ;
  u32 __cil_tmp66 ;
  u32 __cil_tmp67 ;
  unsigned int __cil_tmp68 ;
  u32 __cil_tmp69 ;
  u32 __cil_tmp70 ;
  uint32_t __cil_tmp71 ;
  u32 __cil_tmp72 ;
  u32 __cil_tmp73 ;
  unsigned int __cil_tmp74 ;
  u32 __cil_tmp75 ;
  u32 __cil_tmp76 ;
  u32 __cil_tmp77 ;
  u32 __cil_tmp78 ;
  u32 __cil_tmp79 ;
  u32 __cil_tmp80 ;
  u32 __cil_tmp81 ;
  u32 __cil_tmp82 ;
  char const   *__cil_tmp83 ;
  struct drm_device *__cil_tmp84 ;
  struct drm_device *__cil_tmp85 ;
  u32 __cil_tmp86 ;
  u32 __cil_tmp87 ;
  u32 __cil_tmp88 ;
  u32 __cil_tmp89 ;

  {
  {
#line 152
  __cil_tmp24 = ring->dev;
#line 152
  __cil_tmp25 = __cil_tmp24->dev_private;
#line 152
  dev_priv = (drm_i915_private_t *)__cil_tmp25;
#line 153
  obj = ring->obj;
#line 157
  __cil_tmp26 = ring->mmio_base;
#line 157
  __cil_tmp27 = __cil_tmp26 + 60U;
#line 157
  i915_write32___11(dev_priv, __cil_tmp27, 0U);
#line 158
  __cil_tmp28 = ring->mmio_base;
#line 158
  __cil_tmp29 = __cil_tmp28 + 52U;
#line 158
  i915_write32___11(dev_priv, __cil_tmp29, 0U);
#line 159
  __cil_tmp30 = ring->write_tail;
#line 159
  (*__cil_tmp30)(ring, 0U);
#line 162
  __cil_tmp31 = ring->mmio_base;
#line 162
  __cil_tmp32 = __cil_tmp31 + 56U;
#line 162
  __cil_tmp33 = obj->gtt_offset;
#line 162
  i915_write32___11(dev_priv, __cil_tmp32, __cil_tmp33);
#line 163
  __cil_tmp34 = ring->mmio_base;
#line 163
  __cil_tmp35 = __cil_tmp34 + 52U;
#line 163
  tmp = i915_read32___13(dev_priv, __cil_tmp35);
#line 163
  head = tmp & 2097148U;
  }
#line 166
  if (head != 0U) {
    {
#line 167
    __cil_tmp36 = ring->mmio_base;
#line 167
    __cil_tmp37 = __cil_tmp36 + 56U;
#line 167
    tmp___0 = i915_read32___13(dev_priv, __cil_tmp37);
#line 167
    __cil_tmp38 = ring->mmio_base;
#line 167
    __cil_tmp39 = __cil_tmp38 + 48U;
#line 167
    tmp___1 = i915_read32___13(dev_priv, __cil_tmp39);
#line 167
    __cil_tmp40 = ring->mmio_base;
#line 167
    __cil_tmp41 = __cil_tmp40 + 52U;
#line 167
    tmp___2 = i915_read32___13(dev_priv, __cil_tmp41);
#line 167
    __cil_tmp42 = ring->mmio_base;
#line 167
    __cil_tmp43 = __cil_tmp42 + 60U;
#line 167
    tmp___3 = i915_read32___13(dev_priv, __cil_tmp43);
#line 167
    __cil_tmp44 = ring->name;
#line 167
    drm_ut_debug_printk(4U, "drm", "init_ring_common", "%s head not reset to zero ctl %08x head %08x tail %08x start %08x\n",
                        __cil_tmp44, tmp___3, tmp___2, tmp___1, tmp___0);
#line 175
    __cil_tmp45 = ring->mmio_base;
#line 175
    __cil_tmp46 = __cil_tmp45 + 52U;
#line 175
    i915_write32___11(dev_priv, __cil_tmp46, 0U);
#line 177
    __cil_tmp47 = ring->mmio_base;
#line 177
    __cil_tmp48 = __cil_tmp47 + 52U;
#line 177
    tmp___8 = i915_read32___13(dev_priv, __cil_tmp48);
    }
    {
#line 177
    __cil_tmp49 = tmp___8 & 2097148U;
#line 177
    if (__cil_tmp49 != 0U) {
      {
#line 178
      __cil_tmp50 = ring->mmio_base;
#line 178
      __cil_tmp51 = __cil_tmp50 + 56U;
#line 178
      tmp___4 = i915_read32___13(dev_priv, __cil_tmp51);
#line 178
      __cil_tmp52 = ring->mmio_base;
#line 178
      __cil_tmp53 = __cil_tmp52 + 48U;
#line 178
      tmp___5 = i915_read32___13(dev_priv, __cil_tmp53);
#line 178
      __cil_tmp54 = ring->mmio_base;
#line 178
      __cil_tmp55 = __cil_tmp54 + 52U;
#line 178
      tmp___6 = i915_read32___13(dev_priv, __cil_tmp55);
#line 178
      __cil_tmp56 = ring->mmio_base;
#line 178
      __cil_tmp57 = __cil_tmp56 + 60U;
#line 178
      tmp___7 = i915_read32___13(dev_priv, __cil_tmp57);
#line 178
      __cil_tmp58 = ring->name;
#line 178
      drm_err("init_ring_common", "failed to set %s head to zero ctl %08x head %08x tail %08x start %08x\n",
              __cil_tmp58, tmp___7, tmp___6, tmp___5, tmp___4);
      }
    } else {

    }
    }
  } else {

  }
  {
#line 188
  __cil_tmp59 = ring->mmio_base;
#line 188
  __cil_tmp60 = __cil_tmp59 + 60U;
#line 188
  __cil_tmp61 = ring->size;
#line 188
  __cil_tmp62 = (u32 )__cil_tmp61;
#line 188
  __cil_tmp63 = __cil_tmp62 - 4096U;
#line 188
  __cil_tmp64 = __cil_tmp63 & 2093056U;
#line 188
  __cil_tmp65 = __cil_tmp64 | 3U;
#line 188
  i915_write32___11(dev_priv, __cil_tmp60, __cil_tmp65);
#line 193
  __cil_tmp66 = ring->mmio_base;
#line 193
  __cil_tmp67 = __cil_tmp66 + 60U;
#line 193
  tmp___13 = i915_read32___13(dev_priv, __cil_tmp67);
  }
  {
#line 193
  __cil_tmp68 = tmp___13 & 1U;
#line 193
  if (__cil_tmp68 == 0U) {
#line 193
    goto _L;
  } else {
    {
#line 193
    __cil_tmp69 = ring->mmio_base;
#line 193
    __cil_tmp70 = __cil_tmp69 + 56U;
#line 193
    tmp___14 = i915_read32___13(dev_priv, __cil_tmp70);
    }
    {
#line 193
    __cil_tmp71 = obj->gtt_offset;
#line 193
    if (tmp___14 != __cil_tmp71) {
#line 193
      goto _L;
    } else {
      {
#line 193
      __cil_tmp72 = ring->mmio_base;
#line 193
      __cil_tmp73 = __cil_tmp72 + 52U;
#line 193
      tmp___15 = i915_read32___13(dev_priv, __cil_tmp73);
      }
      {
#line 193
      __cil_tmp74 = tmp___15 & 2097148U;
#line 193
      if (__cil_tmp74 != 0U) {
        _L: 
        {
#line 196
        __cil_tmp75 = ring->mmio_base;
#line 196
        __cil_tmp76 = __cil_tmp75 + 56U;
#line 196
        tmp___9 = i915_read32___13(dev_priv, __cil_tmp76);
#line 196
        __cil_tmp77 = ring->mmio_base;
#line 196
        __cil_tmp78 = __cil_tmp77 + 48U;
#line 196
        tmp___10 = i915_read32___13(dev_priv, __cil_tmp78);
#line 196
        __cil_tmp79 = ring->mmio_base;
#line 196
        __cil_tmp80 = __cil_tmp79 + 52U;
#line 196
        tmp___11 = i915_read32___13(dev_priv, __cil_tmp80);
#line 196
        __cil_tmp81 = ring->mmio_base;
#line 196
        __cil_tmp82 = __cil_tmp81 + 60U;
#line 196
        tmp___12 = i915_read32___13(dev_priv, __cil_tmp82);
#line 196
        __cil_tmp83 = ring->name;
#line 196
        drm_err("init_ring_common", "%s initialization failed ctl %08x head %08x tail %08x start %08x\n",
                __cil_tmp83, tmp___12, tmp___11, tmp___10, tmp___9);
        }
#line 203
        return (-5);
      } else {

      }
      }
    }
    }
  }
  }
  {
#line 206
  __cil_tmp84 = ring->dev;
#line 206
  tmp___17 = drm_core_check_feature(__cil_tmp84, 8192);
  }
#line 206
  if (tmp___17 == 0) {
    {
#line 207
    __cil_tmp85 = ring->dev;
#line 207
    i915_kernel_lost_context(__cil_tmp85);
    }
  } else {
    {
#line 209
    __cil_tmp86 = ring->mmio_base;
#line 209
    __cil_tmp87 = __cil_tmp86 + 52U;
#line 209
    ring->head = i915_read32___13(dev_priv, __cil_tmp87);
#line 210
    __cil_tmp88 = ring->mmio_base;
#line 210
    __cil_tmp89 = __cil_tmp88 + 48U;
#line 210
    tmp___16 = i915_read32___13(dev_priv, __cil_tmp89);
#line 210
    ring->tail = tmp___16 & 2097144U;
#line 211
    ring->space = ring_space(ring);
    }
  }
#line 214
  return (0);
}
}
#line 228 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int init_pipe_control(struct intel_ring_buffer *ring ) 
{ struct pipe_control *pc ;
  struct drm_i915_gem_object *obj ;
  int ret ;
  void *tmp ;
  void *tmp___0 ;
  void *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct pipe_control *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct drm_device *__cil_tmp14 ;
  struct drm_i915_gem_object *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  bool __cil_tmp18 ;
  struct page **__cil_tmp19 ;
  struct page *__cil_tmp20 ;
  u32 volatile   *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  u32 volatile   *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  struct drm_gem_object *__cil_tmp25 ;
  void const   *__cil_tmp26 ;

  {
  {
#line 234
  __cil_tmp7 = (void *)0;
#line 234
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 234
  __cil_tmp9 = ring->private;
#line 234
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 234
  if (__cil_tmp10 != __cil_tmp8) {
#line 235
    return (0);
  } else {

  }
  }
  {
#line 237
  tmp = kmalloc(24UL, 208U);
#line 237
  pc = (struct pipe_control *)tmp;
  }
  {
#line 238
  __cil_tmp11 = (struct pipe_control *)0;
#line 238
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 238
  __cil_tmp13 = (unsigned long )pc;
#line 238
  if (__cil_tmp13 == __cil_tmp12) {
#line 239
    return (-12);
  } else {

  }
  }
  {
#line 241
  __cil_tmp14 = ring->dev;
#line 241
  obj = i915_gem_alloc_object(__cil_tmp14, 4096UL);
  }
  {
#line 242
  __cil_tmp15 = (struct drm_i915_gem_object *)0;
#line 242
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 242
  __cil_tmp17 = (unsigned long )obj;
#line 242
  if (__cil_tmp17 == __cil_tmp16) {
    {
#line 243
    drm_err("init_pipe_control", "Failed to allocate seqno page\n");
#line 244
    ret = -12;
    }
#line 245
    goto err;
  } else {

  }
  }
  {
#line 247
  obj->cache_level = (unsigned char)1;
#line 249
  __cil_tmp18 = (bool )1;
#line 249
  ret = i915_gem_object_pin(obj, 4096U, __cil_tmp18);
  }
#line 250
  if (ret != 0) {
#line 251
    goto err_unref;
  } else {

  }
  {
#line 253
  pc->gtt_offset = obj->gtt_offset;
#line 254
  __cil_tmp19 = obj->pages;
#line 254
  __cil_tmp20 = *__cil_tmp19;
#line 254
  tmp___0 = kmap(__cil_tmp20);
#line 254
  pc->cpu_page = (u32 volatile   *)tmp___0;
  }
  {
#line 255
  __cil_tmp21 = (u32 volatile   *)0;
#line 255
  __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 255
  __cil_tmp23 = pc->cpu_page;
#line 255
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 255
  if (__cil_tmp24 == __cil_tmp22) {
#line 256
    goto err_unpin;
  } else {

  }
  }
#line 258
  pc->obj = obj;
#line 259
  ring->private = (void *)pc;
#line 260
  return (0);
  err_unpin: 
  {
#line 263
  i915_gem_object_unpin(obj);
  }
  err_unref: 
  {
#line 265
  __cil_tmp25 = & obj->base;
#line 265
  drm_gem_object_unreference(__cil_tmp25);
  }
  err: 
  {
#line 267
  __cil_tmp26 = (void const   *)pc;
#line 267
  kfree(__cil_tmp26);
  }
#line 268
  return (ret);
}
}
#line 272 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void cleanup_pipe_control(struct intel_ring_buffer *ring ) 
{ struct pipe_control *pc ;
  struct drm_i915_gem_object *obj ;
  void *__cil_tmp4 ;
  void *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  void *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct page **__cil_tmp9 ;
  struct page *__cil_tmp10 ;
  struct drm_gem_object *__cil_tmp11 ;
  void const   *__cil_tmp12 ;

  {
#line 274
  __cil_tmp4 = ring->private;
#line 274
  pc = (struct pipe_control *)__cil_tmp4;
  {
#line 277
  __cil_tmp5 = (void *)0;
#line 277
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 277
  __cil_tmp7 = ring->private;
#line 277
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 277
  if (__cil_tmp8 == __cil_tmp6) {
#line 278
    return;
  } else {

  }
  }
  {
#line 280
  obj = pc->obj;
#line 281
  __cil_tmp9 = obj->pages;
#line 281
  __cil_tmp10 = *__cil_tmp9;
#line 281
  kunmap(__cil_tmp10);
#line 282
  i915_gem_object_unpin(obj);
#line 283
  __cil_tmp11 = & obj->base;
#line 283
  drm_gem_object_unreference(__cil_tmp11);
#line 285
  __cil_tmp12 = (void const   *)pc;
#line 285
  kfree(__cil_tmp12);
#line 286
  ring->private = (void *)0;
  }
#line 287
  return;
}
}
#line 289 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int init_render_ring(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  int ret ;
  int tmp ;
  int mode ;
  void *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  u8 __cil_tmp23 ;
  unsigned char __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  u32 __cil_tmp26 ;
  void *__cil_tmp27 ;
  struct drm_i915_private *__cil_tmp28 ;
  struct intel_device_info  const  *__cil_tmp29 ;
  u8 __cil_tmp30 ;
  unsigned char __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  void *__cil_tmp33 ;
  struct drm_i915_private *__cil_tmp34 ;
  struct intel_device_info  const  *__cil_tmp35 ;
  u8 __cil_tmp36 ;
  unsigned char __cil_tmp37 ;
  unsigned int __cil_tmp38 ;

  {
  {
#line 291
  dev = ring->dev;
#line 292
  __cil_tmp7 = dev->dev_private;
#line 292
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
#line 293
  tmp = init_ring_common(ring);
#line 293
  ret = tmp;
  }
  {
#line 295
  __cil_tmp8 = dev->dev_private;
#line 295
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 295
  __cil_tmp10 = __cil_tmp9->info;
#line 295
  __cil_tmp11 = __cil_tmp10->gen;
#line 295
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 295
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 295
  if (__cil_tmp13 > 3U) {
#line 296
    mode = 4194368;
    {
#line 297
    __cil_tmp14 = dev->dev_private;
#line 297
    __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 297
    __cil_tmp16 = __cil_tmp15->info;
#line 297
    __cil_tmp17 = __cil_tmp16->gen;
#line 297
    __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 297
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 297
    if (__cil_tmp19 == 6U) {
#line 298
      mode = mode | 134219776;
    } else {
      {
#line 297
      __cil_tmp20 = dev->dev_private;
#line 297
      __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 297
      __cil_tmp22 = __cil_tmp21->info;
#line 297
      __cil_tmp23 = __cil_tmp22->gen;
#line 297
      __cil_tmp24 = (unsigned char )__cil_tmp23;
#line 297
      __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 297
      if (__cil_tmp25 == 7U) {
#line 298
        mode = mode | 134219776;
      } else {

      }
      }
    }
    }
    {
#line 299
    __cil_tmp26 = (u32 )mode;
#line 299
    i915_write32___11(dev_priv, 8348U, __cil_tmp26);
    }
  } else {

  }
  }
  {
#line 302
  __cil_tmp27 = dev->dev_private;
#line 302
  __cil_tmp28 = (struct drm_i915_private *)__cil_tmp27;
#line 302
  __cil_tmp29 = __cil_tmp28->info;
#line 302
  __cil_tmp30 = __cil_tmp29->gen;
#line 302
  __cil_tmp31 = (unsigned char )__cil_tmp30;
#line 302
  __cil_tmp32 = (unsigned int )__cil_tmp31;
#line 302
  if (__cil_tmp32 > 5U) {

  } else {
    {
#line 303
    __cil_tmp33 = dev->dev_private;
#line 303
    __cil_tmp34 = (struct drm_i915_private *)__cil_tmp33;
#line 303
    __cil_tmp35 = __cil_tmp34->info;
#line 303
    __cil_tmp36 = __cil_tmp35->gen;
#line 303
    __cil_tmp37 = (unsigned char )__cil_tmp36;
#line 303
    __cil_tmp38 = (unsigned int )__cil_tmp37;
#line 303
    if (__cil_tmp38 == 5U) {
      {
#line 304
      ret = init_pipe_control(ring);
      }
#line 305
      if (ret != 0) {
#line 306
        return (ret);
      } else {

      }
    } else {

    }
    }
  }
  }
#line 309
  return (ret);
}
}
#line 312 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void render_ring_cleanup(struct intel_ring_buffer *ring ) 
{ void *__cil_tmp2 ;
  unsigned long __cil_tmp3 ;
  void *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;

  {
  {
#line 314
  __cil_tmp2 = (void *)0;
#line 314
  __cil_tmp3 = (unsigned long )__cil_tmp2;
#line 314
  __cil_tmp4 = ring->private;
#line 314
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 314
  if (__cil_tmp5 == __cil_tmp3) {
#line 315
    return;
  } else {

  }
  }
  {
#line 317
  cleanup_pipe_control(ring);
  }
#line 318
  return;
}
}
#line 321 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void update_semaphore(struct intel_ring_buffer *ring , int i , u32 seqno ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  int id ;
  void *__cil_tmp7 ;
  struct intel_ring_buffer (*__cil_tmp8)[3U] ;
  long __cil_tmp9 ;
  long __cil_tmp10 ;
  long __cil_tmp11 ;
  long __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  u32 __cil_tmp15 ;
  u32 __cil_tmp16 ;
  u32 __cil_tmp17 ;
  u32 __cil_tmp18 ;

  {
  {
#line 323
  dev = ring->dev;
#line 324
  __cil_tmp7 = dev->dev_private;
#line 324
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
#line 332
  __cil_tmp8 = & dev_priv->ring;
#line 332
  __cil_tmp9 = (long )__cil_tmp8;
#line 332
  __cil_tmp10 = (long )ring;
#line 332
  __cil_tmp11 = __cil_tmp10 - __cil_tmp9;
#line 332
  __cil_tmp12 = __cil_tmp11 / 456L;
#line 332
  id = (int )__cil_tmp12;
#line 333
  __cil_tmp13 = 2 - i;
#line 333
  id = __cil_tmp13 + id;
#line 334
  id = id % 3;
#line 336
  intel_ring_emit(ring, 186908673U);
#line 340
  intel_ring_emit(ring, seqno);
#line 341
  __cil_tmp14 = i * 4;
#line 341
  __cil_tmp15 = (u32 )__cil_tmp14;
#line 341
  __cil_tmp16 = dev_priv->ring[id].mmio_base;
#line 341
  __cil_tmp17 = __cil_tmp16 + __cil_tmp15;
#line 341
  __cil_tmp18 = __cil_tmp17 + 64U;
#line 341
  intel_ring_emit(ring, __cil_tmp18);
  }
#line 343
  return;
}
}
#line 346 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int gen6_add_request(struct intel_ring_buffer *ring , u32 *result ) 
{ u32 seqno ;
  int ret ;
  struct drm_device *__cil_tmp5 ;

  {
  {
#line 352
  ret = intel_ring_begin(ring, 10);
  }
#line 353
  if (ret != 0) {
#line 354
    return (ret);
  } else {

  }
  {
#line 356
  __cil_tmp5 = ring->dev;
#line 356
  seqno = i915_gem_get_seqno(__cil_tmp5);
#line 357
  update_semaphore(ring, 0, seqno);
#line 358
  update_semaphore(ring, 1, seqno);
#line 360
  intel_ring_emit(ring, 276824065U);
#line 361
  intel_ring_emit(ring, 128U);
#line 362
  intel_ring_emit(ring, seqno);
#line 363
  intel_ring_emit(ring, 16777216U);
#line 364
  intel_ring_advance(ring);
#line 366
  *result = seqno;
  }
#line 367
  return (0);
}
}
#line 371 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_ring_sync(struct intel_ring_buffer *ring , struct intel_ring_buffer *to ,
                    u32 seqno ) 
{ int ret ;
  u32 tmp ;
  u32 __cil_tmp6 ;
  unsigned int __cil_tmp7 ;

  {
  {
#line 377
  ret = intel_ring_begin(ring, 4);
  }
#line 378
  if (ret != 0) {
#line 379
    return (ret);
  } else {

  }
  {
#line 381
  tmp = intel_ring_sync_index(ring, to);
#line 381
  __cil_tmp6 = tmp << 17;
#line 381
  __cil_tmp7 = __cil_tmp6 | 185860097U;
#line 381
  intel_ring_emit(ring, __cil_tmp7);
#line 386
  intel_ring_emit(ring, seqno);
#line 387
  intel_ring_emit(ring, 0U);
#line 388
  intel_ring_emit(ring, 0U);
#line 389
  intel_ring_advance(ring);
  }
#line 391
  return (0);
}
}
#line 404 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int pc_render_add_request(struct intel_ring_buffer *ring , u32 *result ) 
{ struct drm_device *dev ;
  u32 seqno ;
  u32 tmp ;
  struct pipe_control *pc ;
  u32 scratch_addr ;
  int ret ;
  void *__cil_tmp9 ;
  u32 __cil_tmp10 ;
  u32 __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  unsigned int __cil_tmp20 ;

  {
  {
#line 407
  dev = ring->dev;
#line 408
  tmp = i915_gem_get_seqno(dev);
#line 408
  seqno = tmp;
#line 409
  __cil_tmp9 = ring->private;
#line 409
  pc = (struct pipe_control *)__cil_tmp9;
#line 410
  __cil_tmp10 = pc->gtt_offset;
#line 410
  scratch_addr = __cil_tmp10 + 128U;
#line 421
  ret = intel_ring_begin(ring, 32);
  }
#line 422
  if (ret != 0) {
#line 423
    return (ret);
  } else {

  }
  {
#line 425
  intel_ring_emit(ring, 2046841858U);
#line 427
  __cil_tmp11 = pc->gtt_offset;
#line 427
  __cil_tmp12 = __cil_tmp11 | 4U;
#line 427
  intel_ring_emit(ring, __cil_tmp12);
#line 428
  intel_ring_emit(ring, seqno);
#line 429
  intel_ring_emit(ring, 0U);
#line 430
  intel_ring_emit(ring, 2046844930U);
#line 430
  __cil_tmp13 = scratch_addr | 4U;
#line 430
  intel_ring_emit(ring, __cil_tmp13);
#line 430
  intel_ring_emit(ring, 0U);
#line 430
  intel_ring_emit(ring, 0U);
#line 431
  scratch_addr = scratch_addr + 128U;
#line 432
  intel_ring_emit(ring, 2046844930U);
#line 432
  __cil_tmp14 = scratch_addr | 4U;
#line 432
  intel_ring_emit(ring, __cil_tmp14);
#line 432
  intel_ring_emit(ring, 0U);
#line 432
  intel_ring_emit(ring, 0U);
#line 433
  scratch_addr = scratch_addr + 128U;
#line 434
  intel_ring_emit(ring, 2046844930U);
#line 434
  __cil_tmp15 = scratch_addr | 4U;
#line 434
  intel_ring_emit(ring, __cil_tmp15);
#line 434
  intel_ring_emit(ring, 0U);
#line 434
  intel_ring_emit(ring, 0U);
#line 435
  scratch_addr = scratch_addr + 128U;
#line 436
  intel_ring_emit(ring, 2046844930U);
#line 436
  __cil_tmp16 = scratch_addr | 4U;
#line 436
  intel_ring_emit(ring, __cil_tmp16);
#line 436
  intel_ring_emit(ring, 0U);
#line 436
  intel_ring_emit(ring, 0U);
#line 437
  scratch_addr = scratch_addr + 128U;
#line 438
  intel_ring_emit(ring, 2046844930U);
#line 438
  __cil_tmp17 = scratch_addr | 4U;
#line 438
  intel_ring_emit(ring, __cil_tmp17);
#line 438
  intel_ring_emit(ring, 0U);
#line 438
  intel_ring_emit(ring, 0U);
#line 439
  scratch_addr = scratch_addr + 128U;
#line 440
  intel_ring_emit(ring, 2046844930U);
#line 440
  __cil_tmp18 = scratch_addr | 4U;
#line 440
  intel_ring_emit(ring, __cil_tmp18);
#line 440
  intel_ring_emit(ring, 0U);
#line 440
  intel_ring_emit(ring, 0U);
#line 441
  intel_ring_emit(ring, 2046842114U);
#line 444
  __cil_tmp19 = pc->gtt_offset;
#line 444
  __cil_tmp20 = __cil_tmp19 | 4U;
#line 444
  intel_ring_emit(ring, __cil_tmp20);
#line 445
  intel_ring_emit(ring, seqno);
#line 446
  intel_ring_emit(ring, 0U);
#line 447
  intel_ring_advance(ring);
#line 449
  *result = seqno;
  }
#line 450
  return (0);
}
}
#line 454 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int render_ring_add_request(struct intel_ring_buffer *ring , u32 *result ) 
{ struct drm_device *dev ;
  u32 seqno ;
  u32 tmp ;
  int ret ;

  {
  {
#line 457
  dev = ring->dev;
#line 458
  tmp = i915_gem_get_seqno(dev);
#line 458
  seqno = tmp;
#line 461
  ret = intel_ring_begin(ring, 4);
  }
#line 462
  if (ret != 0) {
#line 463
    return (ret);
  } else {

  }
  {
#line 465
  intel_ring_emit(ring, 276824065U);
#line 466
  intel_ring_emit(ring, 128U);
#line 467
  intel_ring_emit(ring, seqno);
#line 468
  intel_ring_emit(ring, 16777216U);
#line 469
  intel_ring_advance(ring);
#line 471
  *result = seqno;
  }
#line 472
  return (0);
}
}
#line 476 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static u32 ring_get_seqno(struct intel_ring_buffer *ring ) 
{ u32 tmp ;

  {
  {
#line 478
  tmp = intel_read_status_page(ring, 32);
  }
#line 478
  return (tmp);
}
}
#line 482 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static u32 pc_render_get_seqno(struct intel_ring_buffer *ring ) 
{ struct pipe_control *pc ;
  void *__cil_tmp3 ;
  u32 volatile   *__cil_tmp4 ;
  u32 volatile   __cil_tmp5 ;

  {
#line 484
  __cil_tmp3 = ring->private;
#line 484
  pc = (struct pipe_control *)__cil_tmp3;
  {
#line 485
  __cil_tmp4 = pc->cpu_page;
#line 485
  __cil_tmp5 = *__cil_tmp4;
#line 485
  return ((u32 )__cil_tmp5);
  }
}
}
#line 489 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void ironlake_enable_irq(drm_i915_private_t *dev_priv , u32 mask ) 
{ u32 __cil_tmp3 ;
  u32 __cil_tmp4 ;
  u32 __cil_tmp5 ;
  void *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;
  void const volatile   *__cil_tmp8 ;

  {
  {
#line 491
  __cil_tmp3 = ~ mask;
#line 491
  __cil_tmp4 = dev_priv->gt_irq_mask;
#line 491
  dev_priv->gt_irq_mask = __cil_tmp4 & __cil_tmp3;
#line 492
  __cil_tmp5 = dev_priv->gt_irq_mask;
#line 492
  i915_write32___11(dev_priv, 278548U, __cil_tmp5);
#line 493
  __cil_tmp6 = dev_priv->regs;
#line 493
  __cil_tmp7 = (void const volatile   *)__cil_tmp6;
#line 493
  __cil_tmp8 = __cil_tmp7 + 278548U;
#line 493
  readl(__cil_tmp8);
  }
#line 494
  return;
}
}
#line 497 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void ironlake_disable_irq(drm_i915_private_t *dev_priv , u32 mask ) 
{ u32 __cil_tmp3 ;
  u32 __cil_tmp4 ;
  void *__cil_tmp5 ;
  void const volatile   *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;

  {
  {
#line 499
  __cil_tmp3 = dev_priv->gt_irq_mask;
#line 499
  dev_priv->gt_irq_mask = __cil_tmp3 | mask;
#line 500
  __cil_tmp4 = dev_priv->gt_irq_mask;
#line 500
  i915_write32___11(dev_priv, 278548U, __cil_tmp4);
#line 501
  __cil_tmp5 = dev_priv->regs;
#line 501
  __cil_tmp6 = (void const volatile   *)__cil_tmp5;
#line 501
  __cil_tmp7 = __cil_tmp6 + 278548U;
#line 501
  readl(__cil_tmp7);
  }
#line 502
  return;
}
}
#line 505 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void i915_enable_irq(drm_i915_private_t *dev_priv , u32 mask ) 
{ u32 __cil_tmp3 ;
  u32 __cil_tmp4 ;
  u32 __cil_tmp5 ;
  void *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;
  void const volatile   *__cil_tmp8 ;

  {
  {
#line 507
  __cil_tmp3 = ~ mask;
#line 507
  __cil_tmp4 = dev_priv->irq_mask;
#line 507
  dev_priv->irq_mask = __cil_tmp4 & __cil_tmp3;
#line 508
  __cil_tmp5 = dev_priv->irq_mask;
#line 508
  i915_write32___11(dev_priv, 8360U, __cil_tmp5);
#line 509
  __cil_tmp6 = dev_priv->regs;
#line 509
  __cil_tmp7 = (void const volatile   *)__cil_tmp6;
#line 509
  __cil_tmp8 = __cil_tmp7 + 8360U;
#line 509
  readl(__cil_tmp8);
  }
#line 510
  return;
}
}
#line 513 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void i915_disable_irq(drm_i915_private_t *dev_priv , u32 mask ) 
{ u32 __cil_tmp3 ;
  u32 __cil_tmp4 ;
  void *__cil_tmp5 ;
  void const volatile   *__cil_tmp6 ;
  void const volatile   *__cil_tmp7 ;

  {
  {
#line 515
  __cil_tmp3 = dev_priv->irq_mask;
#line 515
  dev_priv->irq_mask = __cil_tmp3 | mask;
#line 516
  __cil_tmp4 = dev_priv->irq_mask;
#line 516
  i915_write32___11(dev_priv, 8360U, __cil_tmp4);
#line 517
  __cil_tmp5 = dev_priv->regs;
#line 517
  __cil_tmp6 = (void const volatile   *)__cil_tmp5;
#line 517
  __cil_tmp7 = __cil_tmp6 + 8360U;
#line 517
  readl(__cil_tmp7);
  }
#line 518
  return;
}
}
#line 521 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static bool render_ring_get_irq(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  u32 tmp ;
  void *__cil_tmp5 ;
  int __cil_tmp6 ;
  spinlock_t *__cil_tmp7 ;
  u32 __cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  void *__cil_tmp15 ;
  struct drm_i915_private *__cil_tmp16 ;
  struct intel_device_info  const  *__cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned char __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  void *__cil_tmp21 ;
  struct drm_i915_private *__cil_tmp22 ;
  struct intel_device_info  const  *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char *__cil_tmp25 ;
  unsigned char __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  spinlock_t *__cil_tmp28 ;

  {
#line 523
  dev = ring->dev;
#line 524
  __cil_tmp5 = dev->dev_private;
#line 524
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
  {
#line 526
  __cil_tmp6 = dev->irq_enabled;
#line 526
  if (__cil_tmp6 == 0) {
#line 527
    return ((bool )0);
  } else {

  }
  }
  {
#line 529
  __cil_tmp7 = & ring->irq_lock;
#line 529
  spin_lock(__cil_tmp7);
#line 530
  tmp = ring->irq_refcount;
#line 530
  __cil_tmp8 = ring->irq_refcount;
#line 530
  ring->irq_refcount = __cil_tmp8 + 1U;
  }
#line 530
  if (tmp == 0U) {
    {
#line 531
    __cil_tmp9 = dev->dev_private;
#line 531
    __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 531
    __cil_tmp11 = __cil_tmp10->info;
#line 531
    __cil_tmp12 = __cil_tmp11->gen;
#line 531
    __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 531
    __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 531
    if (__cil_tmp14 == 5U) {
      {
#line 532
      ironlake_enable_irq(dev_priv, 17U);
      }
    } else {
      {
#line 531
      __cil_tmp15 = dev->dev_private;
#line 531
      __cil_tmp16 = (struct drm_i915_private *)__cil_tmp15;
#line 531
      __cil_tmp17 = __cil_tmp16->info;
#line 531
      __cil_tmp18 = __cil_tmp17->gen;
#line 531
      __cil_tmp19 = (unsigned char )__cil_tmp18;
#line 531
      __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 531
      if (__cil_tmp20 == 6U) {
        {
#line 532
        ironlake_enable_irq(dev_priv, 17U);
        }
      } else {
        {
#line 531
        __cil_tmp21 = dev->dev_private;
#line 531
        __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
#line 531
        __cil_tmp23 = __cil_tmp22->info;
#line 531
        __cil_tmp24 = (unsigned char *)__cil_tmp23;
#line 531
        __cil_tmp25 = __cil_tmp24 + 2UL;
#line 531
        __cil_tmp26 = *__cil_tmp25;
#line 531
        __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 531
        if (__cil_tmp27 != 0U) {
          {
#line 532
          ironlake_enable_irq(dev_priv, 17U);
          }
        } else {
          {
#line 535
          i915_enable_irq(dev_priv, 2U);
          }
        }
        }
      }
      }
    }
    }
  } else {

  }
  {
#line 537
  __cil_tmp28 = & ring->irq_lock;
#line 537
  spin_unlock(__cil_tmp28);
  }
#line 539
  return ((bool )1);
}
}
#line 543 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void render_ring_put_irq(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  void *__cil_tmp4 ;
  spinlock_t *__cil_tmp5 ;
  u32 __cil_tmp6 ;
  u32 __cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  void *__cil_tmp20 ;
  struct drm_i915_private *__cil_tmp21 ;
  struct intel_device_info  const  *__cil_tmp22 ;
  unsigned char *__cil_tmp23 ;
  unsigned char *__cil_tmp24 ;
  unsigned char __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  spinlock_t *__cil_tmp27 ;

  {
  {
#line 545
  dev = ring->dev;
#line 546
  __cil_tmp4 = dev->dev_private;
#line 546
  dev_priv = (drm_i915_private_t *)__cil_tmp4;
#line 548
  __cil_tmp5 = & ring->irq_lock;
#line 548
  spin_lock(__cil_tmp5);
#line 549
  __cil_tmp6 = ring->irq_refcount;
#line 549
  ring->irq_refcount = __cil_tmp6 - 1U;
  }
  {
#line 549
  __cil_tmp7 = ring->irq_refcount;
#line 549
  if (__cil_tmp7 == 0U) {
    {
#line 550
    __cil_tmp8 = dev->dev_private;
#line 550
    __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 550
    __cil_tmp10 = __cil_tmp9->info;
#line 550
    __cil_tmp11 = __cil_tmp10->gen;
#line 550
    __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 550
    __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 550
    if (__cil_tmp13 == 5U) {
      {
#line 551
      ironlake_disable_irq(dev_priv, 17U);
      }
    } else {
      {
#line 550
      __cil_tmp14 = dev->dev_private;
#line 550
      __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 550
      __cil_tmp16 = __cil_tmp15->info;
#line 550
      __cil_tmp17 = __cil_tmp16->gen;
#line 550
      __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 550
      __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 550
      if (__cil_tmp19 == 6U) {
        {
#line 551
        ironlake_disable_irq(dev_priv, 17U);
        }
      } else {
        {
#line 550
        __cil_tmp20 = dev->dev_private;
#line 550
        __cil_tmp21 = (struct drm_i915_private *)__cil_tmp20;
#line 550
        __cil_tmp22 = __cil_tmp21->info;
#line 550
        __cil_tmp23 = (unsigned char *)__cil_tmp22;
#line 550
        __cil_tmp24 = __cil_tmp23 + 2UL;
#line 550
        __cil_tmp25 = *__cil_tmp24;
#line 550
        __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 550
        if (__cil_tmp26 != 0U) {
          {
#line 551
          ironlake_disable_irq(dev_priv, 17U);
          }
        } else {
          {
#line 555
          i915_disable_irq(dev_priv, 2U);
          }
        }
        }
      }
      }
    }
    }
  } else {

  }
  }
  {
#line 557
  __cil_tmp27 = & ring->irq_lock;
#line 557
  spin_unlock(__cil_tmp27);
  }
#line 558
  return;
}
}
#line 560 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
void intel_ring_setup_status_page(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  u32 mmio ;
  struct drm_device *__cil_tmp5 ;
  void *__cil_tmp6 ;
  void *__cil_tmp7 ;
  struct drm_i915_private *__cil_tmp8 ;
  struct intel_device_info  const  *__cil_tmp9 ;
  u8 __cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  enum intel_ring_id __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  int __cil_tmp15 ;
  enum intel_ring_id __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  int __cil_tmp18 ;
  enum intel_ring_id __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  int __cil_tmp21 ;
  struct drm_device *__cil_tmp22 ;
  void *__cil_tmp23 ;
  struct drm_i915_private *__cil_tmp24 ;
  struct intel_device_info  const  *__cil_tmp25 ;
  u8 __cil_tmp26 ;
  unsigned char __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  u32 __cil_tmp29 ;
  u32 __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  void *__cil_tmp33 ;
  void const volatile   *__cil_tmp34 ;
  void const volatile   *__cil_tmp35 ;

  {
#line 562
  dev = ring->dev;
#line 563
  __cil_tmp5 = ring->dev;
#line 563
  __cil_tmp6 = __cil_tmp5->dev_private;
#line 563
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
#line 564
  mmio = 0U;
  {
#line 569
  __cil_tmp7 = dev->dev_private;
#line 569
  __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
#line 569
  __cil_tmp9 = __cil_tmp8->info;
#line 569
  __cil_tmp10 = __cil_tmp9->gen;
#line 569
  __cil_tmp11 = (unsigned char )__cil_tmp10;
#line 569
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 569
  if (__cil_tmp12 == 7U) {
    {
#line 571
    __cil_tmp13 = ring->id;
#line 571
    __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 571
    __cil_tmp15 = (int )__cil_tmp14;
#line 571
    if (__cil_tmp15 == 1) {
#line 571
      goto case_1;
    } else {
      {
#line 574
      __cil_tmp16 = ring->id;
#line 574
      __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 574
      __cil_tmp18 = (int )__cil_tmp17;
#line 574
      if (__cil_tmp18 == 4) {
#line 574
        goto case_4;
      } else {
        {
#line 577
        __cil_tmp19 = ring->id;
#line 577
        __cil_tmp20 = (unsigned int )__cil_tmp19;
#line 577
        __cil_tmp21 = (int )__cil_tmp20;
#line 577
        if (__cil_tmp21 == 2) {
#line 577
          goto case_2;
        } else
#line 570
        if (0) {
          case_1: 
#line 572
          mmio = 16512U;
#line 573
          goto ldv_37687;
          case_4: 
#line 575
          mmio = 17024U;
#line 576
          goto ldv_37687;
          case_2: 
#line 578
          mmio = 16768U;
#line 579
          goto ldv_37687;
        } else {

        }
        }
      }
      }
    }
    }
    ldv_37687: ;
  } else {
    {
#line 581
    __cil_tmp22 = ring->dev;
#line 581
    __cil_tmp23 = __cil_tmp22->dev_private;
#line 581
    __cil_tmp24 = (struct drm_i915_private *)__cil_tmp23;
#line 581
    __cil_tmp25 = __cil_tmp24->info;
#line 581
    __cil_tmp26 = __cil_tmp25->gen;
#line 581
    __cil_tmp27 = (unsigned char )__cil_tmp26;
#line 581
    __cil_tmp28 = (unsigned int )__cil_tmp27;
#line 581
    if (__cil_tmp28 == 6U) {
#line 582
      __cil_tmp29 = ring->mmio_base;
#line 582
      mmio = __cil_tmp29 + 8320U;
    } else {
#line 584
      __cil_tmp30 = ring->mmio_base;
#line 584
      mmio = __cil_tmp30 + 128U;
    }
    }
  }
  }
  {
#line 587
  __cil_tmp31 = ring->status_page.gfx_addr;
#line 587
  i915_write32___11(dev_priv, mmio, __cil_tmp31);
#line 588
  __cil_tmp32 = (unsigned long )mmio;
#line 588
  __cil_tmp33 = dev_priv->regs;
#line 588
  __cil_tmp34 = (void const volatile   *)__cil_tmp33;
#line 588
  __cil_tmp35 = __cil_tmp34 + __cil_tmp32;
#line 588
  readl(__cil_tmp35);
  }
#line 589
  return;
}
}
#line 592 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int bsd_ring_flush(struct intel_ring_buffer *ring , u32 invalidate_domains ,
                          u32 flush_domains ) 
{ int ret ;

  {
  {
#line 598
  ret = intel_ring_begin(ring, 2);
  }
#line 599
  if (ret != 0) {
#line 600
    return (ret);
  } else {

  }
  {
#line 602
  intel_ring_emit(ring, 33554432U);
#line 603
  intel_ring_emit(ring, 0U);
#line 604
  intel_ring_advance(ring);
  }
#line 605
  return (0);
}
}
#line 609 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int ring_add_request(struct intel_ring_buffer *ring , u32 *result ) 
{ u32 seqno ;
  int ret ;
  struct drm_device *__cil_tmp5 ;

  {
  {
#line 615
  ret = intel_ring_begin(ring, 4);
  }
#line 616
  if (ret != 0) {
#line 617
    return (ret);
  } else {

  }
  {
#line 619
  __cil_tmp5 = ring->dev;
#line 619
  seqno = i915_gem_get_seqno(__cil_tmp5);
#line 621
  intel_ring_emit(ring, 276824065U);
#line 622
  intel_ring_emit(ring, 128U);
#line 623
  intel_ring_emit(ring, seqno);
#line 624
  intel_ring_emit(ring, 16777216U);
#line 625
  intel_ring_advance(ring);
#line 627
  *result = seqno;
  }
#line 628
  return (0);
}
}
#line 632 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static bool gen6_ring_get_irq(struct intel_ring_buffer *ring , u32 gflag , u32 rflag ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  u32 tmp ;
  void *__cil_tmp7 ;
  int __cil_tmp8 ;
  spinlock_t *__cil_tmp9 ;
  u32 __cil_tmp10 ;
  u32 __cil_tmp11 ;
  u32 __cil_tmp12 ;
  u32 __cil_tmp13 ;
  u32 __cil_tmp14 ;
  u32 __cil_tmp15 ;
  spinlock_t *__cil_tmp16 ;

  {
#line 634
  dev = ring->dev;
#line 635
  __cil_tmp7 = dev->dev_private;
#line 635
  dev_priv = (drm_i915_private_t *)__cil_tmp7;
  {
#line 637
  __cil_tmp8 = dev->irq_enabled;
#line 637
  if (__cil_tmp8 == 0) {
#line 638
    return ((bool )0);
  } else {

  }
  }
  {
#line 640
  __cil_tmp9 = & ring->irq_lock;
#line 640
  spin_lock(__cil_tmp9);
#line 641
  tmp = ring->irq_refcount;
#line 641
  __cil_tmp10 = ring->irq_refcount;
#line 641
  ring->irq_refcount = __cil_tmp10 + 1U;
  }
#line 641
  if (tmp == 0U) {
    {
#line 642
    __cil_tmp11 = ~ rflag;
#line 642
    __cil_tmp12 = ring->irq_mask;
#line 642
    ring->irq_mask = __cil_tmp12 & __cil_tmp11;
#line 643
    __cil_tmp13 = ring->mmio_base;
#line 643
    __cil_tmp14 = __cil_tmp13 + 168U;
#line 643
    __cil_tmp15 = ring->irq_mask;
#line 643
    i915_write32___11(dev_priv, __cil_tmp14, __cil_tmp15);
#line 644
    ironlake_enable_irq(dev_priv, gflag);
    }
  } else {

  }
  {
#line 646
  __cil_tmp16 = & ring->irq_lock;
#line 646
  spin_unlock(__cil_tmp16);
  }
#line 648
  return ((bool )1);
}
}
#line 652 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void gen6_ring_put_irq(struct intel_ring_buffer *ring , u32 gflag , u32 rflag ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  void *__cil_tmp6 ;
  spinlock_t *__cil_tmp7 ;
  u32 __cil_tmp8 ;
  u32 __cil_tmp9 ;
  u32 __cil_tmp10 ;
  u32 __cil_tmp11 ;
  u32 __cil_tmp12 ;
  u32 __cil_tmp13 ;
  spinlock_t *__cil_tmp14 ;

  {
  {
#line 654
  dev = ring->dev;
#line 655
  __cil_tmp6 = dev->dev_private;
#line 655
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
#line 657
  __cil_tmp7 = & ring->irq_lock;
#line 657
  spin_lock(__cil_tmp7);
#line 658
  __cil_tmp8 = ring->irq_refcount;
#line 658
  ring->irq_refcount = __cil_tmp8 - 1U;
  }
  {
#line 658
  __cil_tmp9 = ring->irq_refcount;
#line 658
  if (__cil_tmp9 == 0U) {
    {
#line 659
    __cil_tmp10 = ring->irq_mask;
#line 659
    ring->irq_mask = __cil_tmp10 | rflag;
#line 660
    __cil_tmp11 = ring->mmio_base;
#line 660
    __cil_tmp12 = __cil_tmp11 + 168U;
#line 660
    __cil_tmp13 = ring->irq_mask;
#line 660
    i915_write32___11(dev_priv, __cil_tmp12, __cil_tmp13);
#line 661
    ironlake_disable_irq(dev_priv, gflag);
    }
  } else {

  }
  }
  {
#line 663
  __cil_tmp14 = & ring->irq_lock;
#line 663
  spin_unlock(__cil_tmp14);
  }
#line 664
  return;
}
}
#line 667 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static bool bsd_ring_get_irq(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  u32 tmp ;
  void *__cil_tmp5 ;
  int __cil_tmp6 ;
  spinlock_t *__cil_tmp7 ;
  u32 __cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  unsigned char *__cil_tmp12 ;
  unsigned char *__cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  spinlock_t *__cil_tmp16 ;

  {
#line 669
  dev = ring->dev;
#line 670
  __cil_tmp5 = dev->dev_private;
#line 670
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
  {
#line 672
  __cil_tmp6 = dev->irq_enabled;
#line 672
  if (__cil_tmp6 == 0) {
#line 673
    return ((bool )0);
  } else {

  }
  }
  {
#line 675
  __cil_tmp7 = & ring->irq_lock;
#line 675
  spin_lock(__cil_tmp7);
#line 676
  tmp = ring->irq_refcount;
#line 676
  __cil_tmp8 = ring->irq_refcount;
#line 676
  ring->irq_refcount = __cil_tmp8 + 1U;
  }
#line 676
  if (tmp == 0U) {
    {
#line 677
    __cil_tmp9 = dev->dev_private;
#line 677
    __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 677
    __cil_tmp11 = __cil_tmp10->info;
#line 677
    __cil_tmp12 = (unsigned char *)__cil_tmp11;
#line 677
    __cil_tmp13 = __cil_tmp12 + 1UL;
#line 677
    __cil_tmp14 = *__cil_tmp13;
#line 677
    __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 677
    if (__cil_tmp15 != 0U) {
      {
#line 678
      i915_enable_irq(dev_priv, 33554432U);
      }
    } else {
      {
#line 680
      ironlake_enable_irq(dev_priv, 32U);
      }
    }
    }
  } else {

  }
  {
#line 682
  __cil_tmp16 = & ring->irq_lock;
#line 682
  spin_unlock(__cil_tmp16);
  }
#line 684
  return ((bool )1);
}
}
#line 687 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void bsd_ring_put_irq(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  void *__cil_tmp4 ;
  spinlock_t *__cil_tmp5 ;
  u32 __cil_tmp6 ;
  u32 __cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  unsigned char *__cil_tmp11 ;
  unsigned char *__cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  spinlock_t *__cil_tmp15 ;

  {
  {
#line 689
  dev = ring->dev;
#line 690
  __cil_tmp4 = dev->dev_private;
#line 690
  dev_priv = (drm_i915_private_t *)__cil_tmp4;
#line 692
  __cil_tmp5 = & ring->irq_lock;
#line 692
  spin_lock(__cil_tmp5);
#line 693
  __cil_tmp6 = ring->irq_refcount;
#line 693
  ring->irq_refcount = __cil_tmp6 - 1U;
  }
  {
#line 693
  __cil_tmp7 = ring->irq_refcount;
#line 693
  if (__cil_tmp7 == 0U) {
    {
#line 694
    __cil_tmp8 = dev->dev_private;
#line 694
    __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 694
    __cil_tmp10 = __cil_tmp9->info;
#line 694
    __cil_tmp11 = (unsigned char *)__cil_tmp10;
#line 694
    __cil_tmp12 = __cil_tmp11 + 1UL;
#line 694
    __cil_tmp13 = *__cil_tmp12;
#line 694
    __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 694
    if (__cil_tmp14 != 0U) {
      {
#line 695
      i915_disable_irq(dev_priv, 33554432U);
      }
    } else {
      {
#line 697
      ironlake_disable_irq(dev_priv, 32U);
      }
    }
    }
  } else {

  }
  }
  {
#line 699
  __cil_tmp15 = & ring->irq_lock;
#line 699
  spin_unlock(__cil_tmp15);
  }
#line 700
  return;
}
}
#line 703 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int ring_dispatch_execbuffer(struct intel_ring_buffer *ring , u32 offset ,
                                    u32 length ) 
{ int ret ;

  {
  {
#line 707
  ret = intel_ring_begin(ring, 2);
  }
#line 708
  if (ret != 0) {
#line 709
    return (ret);
  } else {

  }
  {
#line 711
  intel_ring_emit(ring, 411042176U);
#line 714
  intel_ring_emit(ring, offset);
#line 715
  intel_ring_advance(ring);
  }
#line 717
  return (0);
}
}
#line 721 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring , u32 offset ,
                                           u32 len ) 
{ struct drm_device *dev ;
  int ret ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  u32 __cil_tmp9 ;
  u32 __cil_tmp10 ;
  void *__cil_tmp11 ;
  struct drm_i915_private *__cil_tmp12 ;
  struct intel_device_info  const  *__cil_tmp13 ;
  u8 __cil_tmp14 ;
  unsigned char __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;

  {
#line 724
  dev = ring->dev;
  {
#line 727
  __cil_tmp6 = dev->pci_device;
#line 727
  if (__cil_tmp6 == 13687) {
#line 727
    goto _L;
  } else {
    {
#line 727
    __cil_tmp7 = dev->pci_device;
#line 727
    if (__cil_tmp7 == 9570) {
      _L: 
      {
#line 728
      ret = intel_ring_begin(ring, 4);
      }
#line 729
      if (ret != 0) {
#line 730
        return (ret);
      } else {

      }
      {
#line 732
      intel_ring_emit(ring, 402653185U);
#line 733
      __cil_tmp8 = offset | 1U;
#line 733
      intel_ring_emit(ring, __cil_tmp8);
#line 734
      __cil_tmp9 = offset + len;
#line 734
      __cil_tmp10 = __cil_tmp9 - 8U;
#line 734
      intel_ring_emit(ring, __cil_tmp10);
#line 735
      intel_ring_emit(ring, 0U);
      }
    } else {
      {
#line 737
      ret = intel_ring_begin(ring, 2);
      }
#line 738
      if (ret != 0) {
#line 739
        return (ret);
      } else {

      }
      {
#line 741
      __cil_tmp11 = dev->dev_private;
#line 741
      __cil_tmp12 = (struct drm_i915_private *)__cil_tmp11;
#line 741
      __cil_tmp13 = __cil_tmp12->info;
#line 741
      __cil_tmp14 = __cil_tmp13->gen;
#line 741
      __cil_tmp15 = (unsigned char )__cil_tmp14;
#line 741
      __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 741
      if (__cil_tmp16 > 3U) {
        {
#line 742
        intel_ring_emit(ring, 411042176U);
#line 745
        intel_ring_emit(ring, offset);
        }
      } else {
        {
#line 747
        intel_ring_emit(ring, 411041920U);
#line 749
        __cil_tmp17 = offset | 1U;
#line 749
        intel_ring_emit(ring, __cil_tmp17);
        }
      }
      }
    }
    }
  }
  }
  {
#line 752
  intel_ring_advance(ring);
  }
#line 754
  return (0);
}
}
#line 757 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void cleanup_status_page(struct intel_ring_buffer *ring ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_i915_gem_object *obj ;
  struct drm_device *__cil_tmp4 ;
  void *__cil_tmp5 ;
  struct drm_i915_gem_object *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct page **__cil_tmp9 ;
  struct page *__cil_tmp10 ;
  struct drm_gem_object *__cil_tmp11 ;
  drm_local_map_t *__cil_tmp12 ;
  void *__cil_tmp13 ;

  {
#line 759
  __cil_tmp4 = ring->dev;
#line 759
  __cil_tmp5 = __cil_tmp4->dev_private;
#line 759
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 762
  obj = ring->status_page.obj;
  {
#line 763
  __cil_tmp6 = (struct drm_i915_gem_object *)0;
#line 763
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 763
  __cil_tmp8 = (unsigned long )obj;
#line 763
  if (__cil_tmp8 == __cil_tmp7) {
#line 764
    return;
  } else {

  }
  }
  {
#line 766
  __cil_tmp9 = obj->pages;
#line 766
  __cil_tmp10 = *__cil_tmp9;
#line 766
  kunmap(__cil_tmp10);
#line 767
  i915_gem_object_unpin(obj);
#line 768
  __cil_tmp11 = & obj->base;
#line 768
  drm_gem_object_unreference(__cil_tmp11);
#line 769
  ring->status_page.obj = (struct drm_i915_gem_object *)0;
#line 771
  __cil_tmp12 = & dev_priv->hws_map;
#line 771
  __cil_tmp13 = (void *)__cil_tmp12;
#line 771
  memset(__cil_tmp13, 0, 40UL);
  }
#line 772
  return;
}
}
#line 774 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int init_status_page(struct intel_ring_buffer *ring ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  struct drm_i915_gem_object *obj ;
  int ret ;
  void *tmp ;
  void *__cil_tmp7 ;
  struct drm_i915_gem_object *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  bool __cil_tmp11 ;
  struct page **__cil_tmp12 ;
  struct page *__cil_tmp13 ;
  u32 *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  u32 *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  drm_local_map_t *__cil_tmp18 ;
  void *__cil_tmp19 ;
  u32 *__cil_tmp20 ;
  void *__cil_tmp21 ;
  char const   *__cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  struct drm_gem_object *__cil_tmp24 ;

  {
  {
#line 776
  dev = ring->dev;
#line 777
  __cil_tmp7 = dev->dev_private;
#line 777
  dev_priv = (drm_i915_private_t *)__cil_tmp7;
#line 781
  obj = i915_gem_alloc_object(dev, 4096UL);
  }
  {
#line 782
  __cil_tmp8 = (struct drm_i915_gem_object *)0;
#line 782
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 782
  __cil_tmp10 = (unsigned long )obj;
#line 782
  if (__cil_tmp10 == __cil_tmp9) {
    {
#line 783
    drm_err("init_status_page", "Failed to allocate status page\n");
#line 784
    ret = -12;
    }
#line 785
    goto err;
  } else {

  }
  }
  {
#line 787
  obj->cache_level = (unsigned char)1;
#line 789
  __cil_tmp11 = (bool )1;
#line 789
  ret = i915_gem_object_pin(obj, 4096U, __cil_tmp11);
  }
#line 790
  if (ret != 0) {
#line 791
    goto err_unref;
  } else {

  }
  {
#line 794
  ring->status_page.gfx_addr = obj->gtt_offset;
#line 795
  __cil_tmp12 = obj->pages;
#line 795
  __cil_tmp13 = *__cil_tmp12;
#line 795
  tmp = kmap(__cil_tmp13);
#line 795
  ring->status_page.page_addr = (u32 *)tmp;
  }
  {
#line 796
  __cil_tmp14 = (u32 *)0;
#line 796
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 796
  __cil_tmp16 = ring->status_page.page_addr;
#line 796
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 796
  if (__cil_tmp17 == __cil_tmp15) {
    {
#line 797
    __cil_tmp18 = & dev_priv->hws_map;
#line 797
    __cil_tmp19 = (void *)__cil_tmp18;
#line 797
    memset(__cil_tmp19, 0, 40UL);
    }
#line 798
    goto err_unpin;
  } else {

  }
  }
  {
#line 800
  ring->status_page.obj = obj;
#line 801
  __cil_tmp20 = ring->status_page.page_addr;
#line 801
  __cil_tmp21 = (void *)__cil_tmp20;
#line 801
  memset(__cil_tmp21, 0, 4096UL);
#line 803
  intel_ring_setup_status_page(ring);
#line 804
  __cil_tmp22 = ring->name;
#line 804
  __cil_tmp23 = ring->status_page.gfx_addr;
#line 804
  drm_ut_debug_printk(2U, "drm", "init_status_page", "%s hws offset: 0x%08x\n", __cil_tmp22,
                      __cil_tmp23);
  }
#line 807
  return (0);
  err_unpin: 
  {
#line 810
  i915_gem_object_unpin(obj);
  }
  err_unref: 
  {
#line 812
  __cil_tmp24 = & obj->base;
#line 812
  drm_gem_object_unreference(__cil_tmp24);
  }
  err: ;
#line 814
  return (ret);
}
}
#line 817 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_init_ring_buffer(struct drm_device *dev , struct intel_ring_buffer *ring ) 
{ struct drm_i915_gem_object *obj ;
  int ret ;
  struct lock_class_key __key ;
  struct lock_class_key __key___0 ;
  struct list_head *__cil_tmp7 ;
  struct list_head *__cil_tmp8 ;
  struct list_head *__cil_tmp9 ;
  wait_queue_head_t *__cil_tmp10 ;
  spinlock_t *__cil_tmp11 ;
  struct raw_spinlock *__cil_tmp12 ;
  void *__cil_tmp13 ;
  struct drm_i915_private *__cil_tmp14 ;
  struct intel_device_info  const  *__cil_tmp15 ;
  unsigned char *__cil_tmp16 ;
  unsigned char *__cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  int __cil_tmp20 ;
  size_t __cil_tmp21 ;
  struct drm_i915_gem_object *__cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  bool __cil_tmp25 ;
  int __cil_tmp26 ;
  uint32_t __cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  struct drm_agp_head *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  drm_local_map_t *__cil_tmp32 ;
  void *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  void *__cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  int (*__cil_tmp37)(struct intel_ring_buffer * ) ;
  struct drm_device *__cil_tmp38 ;
  int __cil_tmp39 ;
  int __cil_tmp40 ;
  drm_local_map_t *__cil_tmp41 ;
  struct drm_gem_object *__cil_tmp42 ;

  {
  {
#line 823
  ring->dev = dev;
#line 824
  __cil_tmp7 = & ring->active_list;
#line 824
  INIT_LIST_HEAD(__cil_tmp7);
#line 825
  __cil_tmp8 = & ring->request_list;
#line 825
  INIT_LIST_HEAD(__cil_tmp8);
#line 826
  __cil_tmp9 = & ring->gpu_write_list;
#line 826
  INIT_LIST_HEAD(__cil_tmp9);
#line 828
  __cil_tmp10 = & ring->irq_queue;
#line 828
  __init_waitqueue_head(__cil_tmp10, & __key);
#line 829
  __cil_tmp11 = & ring->irq_lock;
#line 829
  spinlock_check(__cil_tmp11);
#line 829
  __cil_tmp12 = & ring->irq_lock.ldv_6060.rlock;
#line 829
  __raw_spin_lock_init(__cil_tmp12, "&(&ring->irq_lock)->rlock", & __key___0);
#line 830
  ring->irq_mask = 4294967295U;
  }
  {
#line 832
  __cil_tmp13 = dev->dev_private;
#line 832
  __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
#line 832
  __cil_tmp15 = __cil_tmp14->info;
#line 832
  __cil_tmp16 = (unsigned char *)__cil_tmp15;
#line 832
  __cil_tmp17 = __cil_tmp16 + 1UL;
#line 832
  __cil_tmp18 = *__cil_tmp17;
#line 832
  __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 832
  if (__cil_tmp19 != 0U) {
    {
#line 833
    ret = init_status_page(ring);
    }
#line 834
    if (ret != 0) {
#line 835
      return (ret);
    } else {

    }
  } else {

  }
  }
  {
#line 838
  __cil_tmp20 = ring->size;
#line 838
  __cil_tmp21 = (size_t )__cil_tmp20;
#line 838
  obj = i915_gem_alloc_object(dev, __cil_tmp21);
  }
  {
#line 839
  __cil_tmp22 = (struct drm_i915_gem_object *)0;
#line 839
  __cil_tmp23 = (unsigned long )__cil_tmp22;
#line 839
  __cil_tmp24 = (unsigned long )obj;
#line 839
  if (__cil_tmp24 == __cil_tmp23) {
    {
#line 840
    drm_err("intel_init_ring_buffer", "Failed to allocate ringbuffer\n");
#line 841
    ret = -12;
    }
#line 842
    goto err_hws;
  } else {

  }
  }
  {
#line 845
  ring->obj = obj;
#line 847
  __cil_tmp25 = (bool )1;
#line 847
  ret = i915_gem_object_pin(obj, 4096U, __cil_tmp25);
  }
#line 848
  if (ret != 0) {
#line 849
    goto err_unref;
  } else {

  }
  {
#line 851
  __cil_tmp26 = ring->size;
#line 851
  ring->map.size = (unsigned long )__cil_tmp26;
#line 852
  __cil_tmp27 = obj->gtt_offset;
#line 852
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 852
  __cil_tmp29 = dev->agp;
#line 852
  __cil_tmp30 = __cil_tmp29->base;
#line 852
  __cil_tmp31 = __cil_tmp30 + __cil_tmp28;
#line 852
  ring->map.offset = (resource_size_t )__cil_tmp31;
#line 853
  ring->map.type = (enum drm_map_type )0;
#line 854
  ring->map.flags = (enum drm_map_flags )0;
#line 855
  ring->map.mtrr = 0;
#line 857
  __cil_tmp32 = & ring->map;
#line 857
  drm_core_ioremap_wc(__cil_tmp32, dev);
  }
  {
#line 858
  __cil_tmp33 = (void *)0;
#line 858
  __cil_tmp34 = (unsigned long )__cil_tmp33;
#line 858
  __cil_tmp35 = ring->map.handle;
#line 858
  __cil_tmp36 = (unsigned long )__cil_tmp35;
#line 858
  if (__cil_tmp36 == __cil_tmp34) {
    {
#line 859
    drm_err("intel_init_ring_buffer", "Failed to map ringbuffer.\n");
#line 860
    ret = -22;
    }
#line 861
    goto err_unpin;
  } else {

  }
  }
  {
#line 864
  ring->virtual_start = ring->map.handle;
#line 865
  __cil_tmp37 = ring->init;
#line 865
  ret = (*__cil_tmp37)(ring);
  }
#line 866
  if (ret != 0) {
#line 867
    goto err_unmap;
  } else {

  }
#line 873
  ring->effective_size = ring->size;
  {
#line 874
  __cil_tmp38 = ring->dev;
#line 874
  __cil_tmp39 = __cil_tmp38->pci_device;
#line 874
  if (__cil_tmp39 == 13687) {
#line 875
    __cil_tmp40 = ring->effective_size;
#line 875
    ring->effective_size = __cil_tmp40 + -128;
  } else {

  }
  }
#line 877
  return (0);
  err_unmap: 
  {
#line 880
  __cil_tmp41 = & ring->map;
#line 880
  drm_core_ioremapfree(__cil_tmp41, dev);
  }
  err_unpin: 
  {
#line 882
  i915_gem_object_unpin(obj);
  }
  err_unref: 
  {
#line 884
  __cil_tmp42 = & obj->base;
#line 884
  drm_gem_object_unreference(__cil_tmp42);
#line 885
  ring->obj = (struct drm_i915_gem_object *)0;
  }
  err_hws: 
  {
#line 887
  cleanup_status_page(ring);
  }
#line 888
  return (ret);
}
}
#line 891 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring ) 
{ struct drm_i915_private *dev_priv ;
  int ret ;
  struct drm_i915_gem_object *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct drm_i915_gem_object *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  char const   *__cil_tmp10 ;
  u32 __cil_tmp11 ;
  u32 __cil_tmp12 ;
  drm_local_map_t *__cil_tmp13 ;
  struct drm_device *__cil_tmp14 ;
  struct drm_i915_gem_object *__cil_tmp15 ;
  struct drm_i915_gem_object *__cil_tmp16 ;
  struct drm_gem_object *__cil_tmp17 ;
  void (*__cil_tmp18)(struct intel_ring_buffer * ) ;
  unsigned long __cil_tmp19 ;
  void (*__cil_tmp20)(struct intel_ring_buffer * ) ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(struct intel_ring_buffer * ) ;

  {
  {
#line 896
  __cil_tmp4 = (struct drm_i915_gem_object *)0;
#line 896
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 896
  __cil_tmp6 = ring->obj;
#line 896
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 896
  if (__cil_tmp7 == __cil_tmp5) {
#line 897
    return;
  } else {

  }
  }
  {
#line 900
  __cil_tmp8 = ring->dev;
#line 900
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 900
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 901
  ret = intel_wait_ring_idle(ring);
  }
#line 902
  if (ret != 0) {
    {
#line 903
    __cil_tmp10 = ring->name;
#line 903
    drm_err("intel_cleanup_ring_buffer", "failed to quiesce %s whilst cleaning up: %d\n",
            __cil_tmp10, ret);
    }
  } else {

  }
  {
#line 906
  __cil_tmp11 = ring->mmio_base;
#line 906
  __cil_tmp12 = __cil_tmp11 + 60U;
#line 906
  i915_write32___11(dev_priv, __cil_tmp12, 0U);
#line 908
  __cil_tmp13 = & ring->map;
#line 908
  __cil_tmp14 = ring->dev;
#line 908
  drm_core_ioremapfree(__cil_tmp13, __cil_tmp14);
#line 910
  __cil_tmp15 = ring->obj;
#line 910
  i915_gem_object_unpin(__cil_tmp15);
#line 911
  __cil_tmp16 = ring->obj;
#line 911
  __cil_tmp17 = & __cil_tmp16->base;
#line 911
  drm_gem_object_unreference(__cil_tmp17);
#line 912
  ring->obj = (struct drm_i915_gem_object *)0;
  }
  {
#line 914
  __cil_tmp18 = (void (*)(struct intel_ring_buffer * ))0;
#line 914
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 914
  __cil_tmp20 = ring->cleanup;
#line 914
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 914
  if (__cil_tmp21 != __cil_tmp19) {
    {
#line 915
    __cil_tmp22 = ring->cleanup;
#line 915
    (*__cil_tmp22)(ring);
    }
  } else {

  }
  }
  {
#line 917
  cleanup_status_page(ring);
  }
#line 918
  return;
}
}
#line 920 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring ) 
{ unsigned int *virt ;
  int rem ;
  int ret ;
  int tmp ;
  unsigned int *tmp___0 ;
  unsigned int *tmp___1 ;
  int tmp___2 ;
  u32 __cil_tmp9 ;
  int __cil_tmp10 ;
  u32 __cil_tmp11 ;
  u32 __cil_tmp12 ;
  int __cil_tmp13 ;
  u32 __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  void *__cil_tmp16 ;
  unsigned int *__cil_tmp17 ;

  {
#line 923
  __cil_tmp9 = ring->tail;
#line 923
  __cil_tmp10 = ring->size;
#line 923
  __cil_tmp11 = (u32 )__cil_tmp10;
#line 923
  __cil_tmp12 = __cil_tmp11 - __cil_tmp9;
#line 923
  rem = (int )__cil_tmp12;
  {
#line 925
  __cil_tmp13 = ring->space;
#line 925
  if (__cil_tmp13 < rem) {
    {
#line 926
    tmp = intel_wait_ring_buffer(ring, rem);
#line 926
    ret = tmp;
    }
#line 927
    if (ret != 0) {
#line 928
      return (ret);
    } else {

    }
  } else {

  }
  }
#line 931
  __cil_tmp14 = ring->tail;
#line 931
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 931
  __cil_tmp16 = ring->virtual_start;
#line 931
  __cil_tmp17 = (unsigned int *)__cil_tmp16;
#line 931
  virt = __cil_tmp17 + __cil_tmp15;
#line 932
  rem = rem / 8;
#line 933
  goto ldv_37781;
  ldv_37780: 
#line 934
  tmp___0 = virt;
#line 934
  virt = virt + 1;
#line 934
  *tmp___0 = 0U;
#line 935
  tmp___1 = virt;
#line 935
  virt = virt + 1;
#line 935
  *tmp___1 = 0U;
  ldv_37781: 
#line 933
  tmp___2 = rem;
#line 933
  rem = rem - 1;
#line 933
  if (tmp___2 != 0) {
#line 934
    goto ldv_37780;
  } else {
#line 936
    goto ldv_37782;
  }
  ldv_37782: 
  {
#line 938
  ring->tail = 0U;
#line 939
  ring->space = ring_space(ring);
  }
#line 941
  return (0);
}
}
#line 944 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_wait_ring_buffer(struct intel_ring_buffer *ring , int n ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  unsigned long end ;
  u32 head ;
  struct drm_i915_master_private *master_priv ;
  int tmp ;
  void *__cil_tmp9 ;
  u32 __cil_tmp10 ;
  int __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  u32 __cil_tmp13 ;
  u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  struct drm_master *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct drm_minor *__cil_tmp18 ;
  struct drm_master *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  struct drm_minor *__cil_tmp21 ;
  struct drm_master *__cil_tmp22 ;
  void *__cil_tmp23 ;
  struct _drm_i915_sarea *__cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  struct _drm_i915_sarea *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  struct _drm_i915_sarea *__cil_tmp28 ;
  struct _drm_i915_sarea *__cil_tmp29 ;
  int __cil_tmp30 ;
  atomic_t *__cil_tmp31 ;
  atomic_t const   *__cil_tmp32 ;
  long __cil_tmp33 ;
  long __cil_tmp34 ;
  long __cil_tmp35 ;

  {
  {
#line 946
  dev = ring->dev;
#line 947
  __cil_tmp9 = dev->dev_private;
#line 947
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 954
  head = intel_read_status_page(ring, 4);
  }
  {
#line 955
  __cil_tmp10 = ring->head;
#line 955
  if (__cil_tmp10 < head) {
    {
#line 956
    ring->head = head;
#line 957
    ring->space = ring_space(ring);
    }
    {
#line 958
    __cil_tmp11 = ring->space;
#line 958
    if (__cil_tmp11 >= n) {
#line 959
      return (0);
    } else {

    }
    }
  } else {

  }
  }
  {
#line 962
  trace_i915_ring_wait_begin(ring);
#line 963
  __cil_tmp12 = (unsigned long )jiffies;
#line 963
  end = __cil_tmp12 + 750UL;
  }
  ldv_37798: 
  {
#line 965
  __cil_tmp13 = ring->mmio_base;
#line 965
  __cil_tmp14 = __cil_tmp13 + 52U;
#line 965
  ring->head = i915_read32___13(dev_priv, __cil_tmp14);
#line 966
  ring->space = ring_space(ring);
  }
  {
#line 967
  __cil_tmp15 = ring->space;
#line 967
  if (__cil_tmp15 >= n) {
    {
#line 968
    trace_i915_ring_wait_end(ring);
    }
#line 969
    return (0);
  } else {

  }
  }
  {
#line 972
  __cil_tmp16 = (struct drm_master *)0;
#line 972
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 972
  __cil_tmp18 = dev->primary;
#line 972
  __cil_tmp19 = __cil_tmp18->master;
#line 972
  __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 972
  if (__cil_tmp20 != __cil_tmp17) {
#line 973
    __cil_tmp21 = dev->primary;
#line 973
    __cil_tmp22 = __cil_tmp21->master;
#line 973
    __cil_tmp23 = __cil_tmp22->driver_priv;
#line 973
    master_priv = (struct drm_i915_master_private *)__cil_tmp23;
    {
#line 974
    __cil_tmp24 = (struct _drm_i915_sarea *)0;
#line 974
    __cil_tmp25 = (unsigned long )__cil_tmp24;
#line 974
    __cil_tmp26 = master_priv->sarea_priv;
#line 974
    __cil_tmp27 = (unsigned long )__cil_tmp26;
#line 974
    if (__cil_tmp27 != __cil_tmp25) {
#line 975
      __cil_tmp28 = master_priv->sarea_priv;
#line 975
      __cil_tmp29 = master_priv->sarea_priv;
#line 975
      __cil_tmp30 = __cil_tmp29->perf_boxes;
#line 975
      __cil_tmp28->perf_boxes = __cil_tmp30 | 4;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 978
  msleep(1U);
#line 979
  __cil_tmp31 = & dev_priv->mm.wedged;
#line 979
  __cil_tmp32 = (atomic_t const   *)__cil_tmp31;
#line 979
  tmp = atomic_read(__cil_tmp32);
  }
#line 979
  if (tmp != 0) {
#line 980
    return (-11);
  } else {

  }
  {
#line 981
  __cil_tmp33 = (long )jiffies;
#line 981
  __cil_tmp34 = (long )end;
#line 981
  __cil_tmp35 = __cil_tmp34 - __cil_tmp33;
#line 981
  if (__cil_tmp35 >= 0L) {
#line 982
    goto ldv_37798;
  } else {
#line 984
    goto ldv_37799;
  }
  }
  ldv_37799: 
  {
#line 982
  trace_i915_ring_wait_end(ring);
  }
#line 983
  return (-16);
}
}
#line 986 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_ring_begin(struct intel_ring_buffer *ring , int num_dwords ) 
{ struct drm_i915_private *dev_priv ;
  int n ;
  int ret ;
  int tmp ;
  long tmp___0 ;
  long tmp___1 ;
  long tmp___2 ;
  long tmp___3 ;
  long tmp___4 ;
  struct drm_device *__cil_tmp12 ;
  void *__cil_tmp13 ;
  atomic_t *__cil_tmp14 ;
  atomic_t const   *__cil_tmp15 ;
  int __cil_tmp16 ;
  long __cil_tmp17 ;
  int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  u32 __cil_tmp20 ;
  u32 __cil_tmp21 ;
  u32 __cil_tmp22 ;
  int __cil_tmp23 ;
  long __cil_tmp24 ;
  int __cil_tmp25 ;
  long __cil_tmp26 ;
  int __cil_tmp27 ;
  int __cil_tmp28 ;
  long __cil_tmp29 ;
  int __cil_tmp30 ;
  long __cil_tmp31 ;
  int __cil_tmp32 ;

  {
  {
#line 989
  __cil_tmp12 = ring->dev;
#line 989
  __cil_tmp13 = __cil_tmp12->dev_private;
#line 989
  dev_priv = (struct drm_i915_private *)__cil_tmp13;
#line 990
  n = num_dwords * 4;
#line 993
  __cil_tmp14 = & dev_priv->mm.wedged;
#line 993
  __cil_tmp15 = (atomic_t const   *)__cil_tmp14;
#line 993
  tmp = atomic_read(__cil_tmp15);
#line 993
  __cil_tmp16 = tmp != 0;
#line 993
  __cil_tmp17 = (long )__cil_tmp16;
#line 993
  tmp___0 = __builtin_expect(__cil_tmp17, 0L);
  }
#line 993
  if (tmp___0 != 0L) {
#line 994
    return (-5);
  } else {

  }
  {
#line 996
  __cil_tmp18 = ring->effective_size;
#line 996
  __cil_tmp19 = (u32 )__cil_tmp18;
#line 996
  __cil_tmp20 = (u32 )n;
#line 996
  __cil_tmp21 = ring->tail;
#line 996
  __cil_tmp22 = __cil_tmp21 + __cil_tmp20;
#line 996
  __cil_tmp23 = __cil_tmp22 > __cil_tmp19;
#line 996
  __cil_tmp24 = (long )__cil_tmp23;
#line 996
  tmp___2 = __builtin_expect(__cil_tmp24, 0L);
  }
#line 996
  if (tmp___2 != 0L) {
    {
#line 997
    ret = intel_wrap_ring_buffer(ring);
#line 998
    __cil_tmp25 = ret != 0;
#line 998
    __cil_tmp26 = (long )__cil_tmp25;
#line 998
    tmp___1 = __builtin_expect(__cil_tmp26, 0L);
    }
#line 998
    if (tmp___1 != 0L) {
#line 999
      return (ret);
    } else {

    }
  } else {

  }
  {
#line 1002
  __cil_tmp27 = ring->space;
#line 1002
  __cil_tmp28 = __cil_tmp27 < n;
#line 1002
  __cil_tmp29 = (long )__cil_tmp28;
#line 1002
  tmp___4 = __builtin_expect(__cil_tmp29, 0L);
  }
#line 1002
  if (tmp___4 != 0L) {
    {
#line 1003
    ret = intel_wait_ring_buffer(ring, n);
#line 1004
    __cil_tmp30 = ret != 0;
#line 1004
    __cil_tmp31 = (long )__cil_tmp30;
#line 1004
    tmp___3 = __builtin_expect(__cil_tmp31, 0L);
    }
#line 1004
    if (tmp___3 != 0L) {
#line 1005
      return (ret);
    } else {

    }
  } else {

  }
#line 1008
  __cil_tmp32 = ring->space;
#line 1008
  ring->space = __cil_tmp32 - n;
#line 1009
  return (0);
}
}
#line 1012 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
void intel_ring_advance(struct intel_ring_buffer *ring ) 
{ int __cil_tmp2 ;
  int __cil_tmp3 ;
  u32 __cil_tmp4 ;
  u32 __cil_tmp5 ;
  void (*__cil_tmp6)(struct intel_ring_buffer * , u32  ) ;
  u32 __cil_tmp7 ;

  {
  {
#line 1014
  __cil_tmp2 = ring->size;
#line 1014
  __cil_tmp3 = __cil_tmp2 + -1;
#line 1014
  __cil_tmp4 = (u32 )__cil_tmp3;
#line 1014
  __cil_tmp5 = ring->tail;
#line 1014
  ring->tail = __cil_tmp5 & __cil_tmp4;
#line 1015
  __cil_tmp6 = ring->write_tail;
#line 1015
  __cil_tmp7 = ring->tail;
#line 1015
  (*__cil_tmp6)(ring, __cil_tmp7);
  }
#line 1016
  return;
}
}
#line 1018 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static struct intel_ring_buffer  const  render_ring  = 
#line 1018
     {"render ring", (enum intel_ring_id )1, 8192U, (void *)0, (struct drm_device *)0,
    (struct drm_i915_gem_object *)0, 0U, 0U, 0, 131072, 0, {(u32 *)0, 0U, (struct drm_i915_gem_object *)0},
    {{{{0U}, 0U, 0U, (void *)0, {(struct lock_class_key *)0, {(struct lock_class *)0,
                                                              (struct lock_class *)0},
                                 (char const   *)0, 0, 0UL}}}}, 0U, 0U, 0U, 0U, 0U,
    {0U, 0U}, & render_ring_get_irq, & render_ring_put_irq, & init_render_ring, & ring_write_tail,
    & render_ring_flush, & render_ring_add_request, & ring_get_seqno, & render_ring_dispatch_execbuffer,
    & render_ring_cleanup, {(struct list_head *)0, (struct list_head *)0}, {(struct list_head *)0,
                                                                            (struct list_head *)0},
    {(struct list_head *)0, (struct list_head *)0}, 0U, {{{{{0U}, 0U, 0U, (void *)0,
                                                            {(struct lock_class_key *)0,
                                                             {(struct lock_class *)0,
                                                              (struct lock_class *)0},
                                                             (char const   *)0, 0,
                                                             0UL}}}}, {(struct list_head *)0,
                                                                       (struct list_head *)0}},
    {0ULL, 0UL, (enum drm_map_type )0, (enum drm_map_flags )0, (void *)0, 0}, (void *)0};
#line 1036 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static struct intel_ring_buffer  const  bsd_ring  = 
#line 1036
     {"bsd ring", (enum intel_ring_id )2, 16384U, (void *)0, (struct drm_device *)0,
    (struct drm_i915_gem_object *)0, 0U, 0U, 0, 131072, 0, {(u32 *)0, 0U, (struct drm_i915_gem_object *)0},
    {{{{0U}, 0U, 0U, (void *)0, {(struct lock_class_key *)0, {(struct lock_class *)0,
                                                              (struct lock_class *)0},
                                 (char const   *)0, 0, 0UL}}}}, 0U, 0U, 0U, 0U, 0U,
    {0U, 0U}, & bsd_ring_get_irq, & bsd_ring_put_irq, & init_ring_common, & ring_write_tail,
    & bsd_ring_flush, & ring_add_request, & ring_get_seqno, & ring_dispatch_execbuffer,
    (void (*)(struct intel_ring_buffer * ))0, {(struct list_head *)0, (struct list_head *)0},
    {(struct list_head *)0, (struct list_head *)0}, {(struct list_head *)0, (struct list_head *)0},
    0U, {{{{{0U}, 0U, 0U, (void *)0, {(struct lock_class_key *)0, {(struct lock_class *)0,
                                                                   (struct lock_class *)0},
                                      (char const   *)0, 0, 0UL}}}}, {(struct list_head *)0,
                                                                      (struct list_head *)0}},
    {0ULL, 0UL, (enum drm_map_type )0, (enum drm_map_flags )0, (void *)0, 0}, (void *)0};
#line 1052 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring , u32 value ) 
{ drm_i915_private_t *dev_priv ;
  unsigned long timeout__ ;
  unsigned long tmp ;
  int ret__ ;
  struct thread_info *tmp___0 ;
  int pfo_ret__ ;
  int tmp___1 ;
  u32 tmp___2 ;
  struct drm_device *__cil_tmp11 ;
  void *__cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  long __cil_tmp16 ;
  long __cil_tmp17 ;
  long __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  atomic_t const   *__cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  u32 __cil_tmp23 ;
  u32 __cil_tmp24 ;

  {
  {
#line 1055
  __cil_tmp11 = ring->dev;
#line 1055
  __cil_tmp12 = __cil_tmp11->dev_private;
#line 1055
  dev_priv = (drm_i915_private_t *)__cil_tmp12;
#line 1058
  i915_write32___11(dev_priv, 73808U, 65537U);
#line 1061
  i915_write32___11(dev_priv, 74136U, 0U);
#line 1063
  __cil_tmp13 = (unsigned int const   )50U;
#line 1063
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 1063
  tmp = msecs_to_jiffies(__cil_tmp14);
#line 1063
  __cil_tmp15 = (unsigned long )jiffies;
#line 1063
  timeout__ = tmp + __cil_tmp15;
#line 1063
  ret__ = 0;
  }
#line 1063
  goto ldv_37835;
  ldv_37834: ;
  {
#line 1063
  __cil_tmp16 = (long )jiffies;
#line 1063
  __cil_tmp17 = (long )timeout__;
#line 1063
  __cil_tmp18 = __cil_tmp17 - __cil_tmp16;
#line 1063
  if (__cil_tmp18 < 0L) {
#line 1063
    ret__ = -110;
#line 1063
    goto ldv_37825;
  } else {

  }
  }
  {
#line 1063
  tmp___0 = current_thread_info();
  }
  {
#line 1063
  __cil_tmp19 = tmp___0->preempt_count;
#line 1063
  __cil_tmp20 = __cil_tmp19 & -268435457;
#line 1063
  if (__cil_tmp20 == 0) {
#line 1063
    if (1) {
#line 1063
      goto case_4;
    } else {
#line 1063
      goto switch_default;
#line 1063
      if (0) {
#line 1063
        __asm__  ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "m" (cpu_number));
#line 1063
        goto ldv_37828;
#line 1063
        __asm__  ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 1063
        goto ldv_37828;
        case_4: 
#line 1063
        __asm__  ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 1063
        goto ldv_37828;
#line 1063
        __asm__  ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "m" (cpu_number));
#line 1063
        goto ldv_37828;
        switch_default: 
        {
#line 1063
        __bad_percpu_size();
        }
      } else {

      }
    }
    ldv_37828: 
    {
#line 1063
    __cil_tmp21 = (atomic_t const   *)(& kgdb_active);
#line 1063
    tmp___1 = atomic_read(__cil_tmp21);
    }
#line 1063
    if (pfo_ret__ != tmp___1) {
      {
#line 1063
      msleep(1U);
      }
    } else {

    }
  } else {

  }
  }
  ldv_37835: 
  {
#line 1063
  tmp___2 = i915_read32___13(dev_priv, 73808U);
  }
  {
#line 1063
  __cil_tmp22 = tmp___2 & 8U;
#line 1063
  if (__cil_tmp22 != 0U) {
#line 1064
    goto ldv_37834;
  } else {
#line 1066
    goto ldv_37825;
  }
  }
  ldv_37825: ;
#line 1063
  if (ret__ != 0) {
    {
#line 1066
    drm_err("gen6_bsd_ring_write_tail", "timed out waiting for IDLE Indicator\n");
    }
  } else {

  }
  {
#line 1068
  __cil_tmp23 = ring->mmio_base;
#line 1068
  __cil_tmp24 = __cil_tmp23 + 48U;
#line 1068
  i915_write32___11(dev_priv, __cil_tmp24, value);
#line 1069
  i915_write32___11(dev_priv, 73808U, 65536U);
  }
#line 1070
  return;
}
}
#line 1074 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int gen6_ring_flush(struct intel_ring_buffer *ring , u32 invalidate , u32 flush ) 
{ uint32_t cmd ;
  int ret ;
  unsigned int __cil_tmp6 ;

  {
  {
#line 1080
  ret = intel_ring_begin(ring, 4);
  }
#line 1081
  if (ret != 0) {
#line 1082
    return (ret);
  } else {

  }
#line 1084
  cmd = 318767105U;
  {
#line 1085
  __cil_tmp6 = invalidate & 4294967230U;
#line 1085
  if (__cil_tmp6 != 0U) {
#line 1086
    cmd = cmd | 262272U;
  } else {

  }
  }
  {
#line 1087
  intel_ring_emit(ring, cmd);
#line 1088
  intel_ring_emit(ring, 0U);
#line 1089
  intel_ring_emit(ring, 0U);
#line 1090
  intel_ring_emit(ring, 0U);
#line 1091
  intel_ring_advance(ring);
  }
#line 1092
  return (0);
}
}
#line 1096 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring , u32 offset ,
                                         u32 len ) 
{ int ret ;

  {
  {
#line 1101
  ret = intel_ring_begin(ring, 2);
  }
#line 1102
  if (ret != 0) {
#line 1103
    return (ret);
  } else {

  }
  {
#line 1105
  intel_ring_emit(ring, 411042048U);
#line 1107
  intel_ring_emit(ring, offset);
#line 1108
  intel_ring_advance(ring);
  }
#line 1110
  return (0);
}
}
#line 1114 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static bool gen6_render_ring_get_irq(struct intel_ring_buffer *ring ) 
{ bool tmp ;

  {
  {
#line 1116
  tmp = gen6_ring_get_irq(ring, 1U, 1U);
  }
#line 1116
  return (tmp);
}
}
#line 1122 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void gen6_render_ring_put_irq(struct intel_ring_buffer *ring ) 
{ 

  {
#line 1124
  return;
}
}
#line 1130 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static bool gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring ) 
{ bool tmp ;

  {
  {
#line 1132
  tmp = gen6_ring_get_irq(ring, 4096U, 4096U);
  }
#line 1132
  return (tmp);
}
}
#line 1138 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring ) 
{ 

  {
#line 1140
  return;
}
}
#line 1146 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static struct intel_ring_buffer  const  gen6_bsd_ring  = 
#line 1146
     {"gen6 bsd ring", (enum intel_ring_id )2, 73728U, (void *)0, (struct drm_device *)0,
    (struct drm_i915_gem_object *)0, 0U, 0U, 0, 131072, 0, {(u32 *)0, 0U, (struct drm_i915_gem_object *)0},
    {{{{0U}, 0U, 0U, (void *)0, {(struct lock_class_key *)0, {(struct lock_class *)0,
                                                              (struct lock_class *)0},
                                 (char const   *)0, 0, 0UL}}}}, 0U, 0U, 0U, 0U, 0U,
    {0U, 0U}, & gen6_bsd_ring_get_irq, & gen6_bsd_ring_put_irq, & init_ring_common,
    & gen6_bsd_ring_write_tail, & gen6_ring_flush, & gen6_add_request, & ring_get_seqno,
    & gen6_ring_dispatch_execbuffer, (void (*)(struct intel_ring_buffer * ))0, {(struct list_head *)0,
                                                                                (struct list_head *)0},
    {(struct list_head *)0, (struct list_head *)0}, {(struct list_head *)0, (struct list_head *)0},
    0U, {{{{{0U}, 0U, 0U, (void *)0, {(struct lock_class_key *)0, {(struct lock_class *)0,
                                                                   (struct lock_class *)0},
                                      (char const   *)0, 0, 0UL}}}}, {(struct list_head *)0,
                                                                      (struct list_head *)0}},
    {0ULL, 0UL, (enum drm_map_type )0, (enum drm_map_flags )0, (void *)0, 0}, (void *)0};
#line 1164 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static bool blt_ring_get_irq(struct intel_ring_buffer *ring ) 
{ bool tmp ;

  {
  {
#line 1166
  tmp = gen6_ring_get_irq(ring, 4194304U, 4194304U);
  }
#line 1166
  return (tmp);
}
}
#line 1172 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void blt_ring_put_irq(struct intel_ring_buffer *ring ) 
{ 

  {
  {
#line 1174
  gen6_ring_put_irq(ring, 4194304U, 4194304U);
  }
#line 1175
  return;
}
}
#line 1189 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
__inline static struct drm_i915_gem_object *to_blt_workaround(struct intel_ring_buffer *ring ) 
{ void *__cil_tmp2 ;

  {
  {
#line 1191
  __cil_tmp2 = ring->private;
#line 1191
  return ((struct drm_i915_gem_object *)__cil_tmp2);
  }
}
}
#line 1194 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int blt_ring_init(struct intel_ring_buffer *ring ) 
{ struct drm_i915_gem_object *obj ;
  u32 *ptr ;
  int ret ;
  void *tmp ;
  u32 *tmp___0 ;
  u32 *tmp___1 ;
  int tmp___2 ;
  struct drm_device *__cil_tmp9 ;
  void *__cil_tmp10 ;
  struct drm_i915_private *__cil_tmp11 ;
  struct intel_device_info  const  *__cil_tmp12 ;
  u8 __cil_tmp13 ;
  unsigned char __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  struct drm_device *__cil_tmp16 ;
  struct pci_dev *__cil_tmp17 ;
  u8 __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  struct drm_device *__cil_tmp20 ;
  struct drm_i915_gem_object *__cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  bool __cil_tmp24 ;
  struct drm_gem_object *__cil_tmp25 ;
  struct page **__cil_tmp26 ;
  struct page *__cil_tmp27 ;
  struct page **__cil_tmp28 ;
  struct page *__cil_tmp29 ;
  bool __cil_tmp30 ;
  struct drm_gem_object *__cil_tmp31 ;

  {
  {
#line 1196
  __cil_tmp9 = ring->dev;
#line 1196
  __cil_tmp10 = __cil_tmp9->dev_private;
#line 1196
  __cil_tmp11 = (struct drm_i915_private *)__cil_tmp10;
#line 1196
  __cil_tmp12 = __cil_tmp11->info;
#line 1196
  __cil_tmp13 = __cil_tmp12->gen;
#line 1196
  __cil_tmp14 = (unsigned char )__cil_tmp13;
#line 1196
  __cil_tmp15 = (unsigned int )__cil_tmp14;
#line 1196
  if (__cil_tmp15 == 6U) {
    {
#line 1196
    __cil_tmp16 = ring->dev;
#line 1196
    __cil_tmp17 = __cil_tmp16->pdev;
#line 1196
    __cil_tmp18 = __cil_tmp17->revision;
#line 1196
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 1196
    if (__cil_tmp19 <= 7U) {
      {
#line 1201
      __cil_tmp20 = ring->dev;
#line 1201
      obj = i915_gem_alloc_object(__cil_tmp20, 4096UL);
      }
      {
#line 1202
      __cil_tmp21 = (struct drm_i915_gem_object *)0;
#line 1202
      __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 1202
      __cil_tmp23 = (unsigned long )obj;
#line 1202
      if (__cil_tmp23 == __cil_tmp22) {
#line 1203
        return (-12);
      } else {

      }
      }
      {
#line 1205
      __cil_tmp24 = (bool )1;
#line 1205
      ret = i915_gem_object_pin(obj, 4096U, __cil_tmp24);
      }
#line 1206
      if (ret != 0) {
        {
#line 1207
        __cil_tmp25 = & obj->base;
#line 1207
        drm_gem_object_unreference(__cil_tmp25);
        }
#line 1208
        return (ret);
      } else {

      }
      {
#line 1211
      __cil_tmp26 = obj->pages;
#line 1211
      __cil_tmp27 = *__cil_tmp26;
#line 1211
      tmp = kmap(__cil_tmp27);
#line 1211
      ptr = (u32 *)tmp;
#line 1212
      tmp___0 = ptr;
#line 1212
      ptr = ptr + 1;
#line 1212
      *tmp___0 = 83886080U;
#line 1213
      tmp___1 = ptr;
#line 1213
      ptr = ptr + 1;
#line 1213
      *tmp___1 = 0U;
#line 1214
      __cil_tmp28 = obj->pages;
#line 1214
      __cil_tmp29 = *__cil_tmp28;
#line 1214
      kunmap(__cil_tmp29);
#line 1216
      __cil_tmp30 = (bool )0;
#line 1216
      ret = i915_gem_object_set_to_gtt_domain(obj, __cil_tmp30);
      }
#line 1217
      if (ret != 0) {
        {
#line 1218
        i915_gem_object_unpin(obj);
#line 1219
        __cil_tmp31 = & obj->base;
#line 1219
        drm_gem_object_unreference(__cil_tmp31);
        }
#line 1220
        return (ret);
      } else {

      }
#line 1223
      ring->private = (void *)obj;
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1226
  tmp___2 = init_ring_common(ring);
  }
#line 1226
  return (tmp___2);
}
}
#line 1229 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int blt_ring_begin(struct intel_ring_buffer *ring , int num_dwords ) 
{ int ret ;
  int tmp ;
  struct drm_i915_gem_object *tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  int __cil_tmp11 ;
  uint32_t __cil_tmp12 ;

  {
  {
#line 1232
  __cil_tmp7 = (void *)0;
#line 1232
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1232
  __cil_tmp9 = ring->private;
#line 1232
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 1232
  if (__cil_tmp10 != __cil_tmp8) {
    {
#line 1233
    __cil_tmp11 = num_dwords + 2;
#line 1233
    tmp = intel_ring_begin(ring, __cil_tmp11);
#line 1233
    ret = tmp;
    }
#line 1234
    if (ret != 0) {
#line 1235
      return (ret);
    } else {

    }
    {
#line 1237
    intel_ring_emit(ring, 411041792U);
#line 1238
    tmp___0 = to_blt_workaround(ring);
#line 1238
    __cil_tmp12 = tmp___0->gtt_offset;
#line 1238
    intel_ring_emit(ring, __cil_tmp12);
    }
#line 1240
    return (0);
  } else {
    {
#line 1242
    tmp___1 = intel_ring_begin(ring, 4);
    }
#line 1242
    return (tmp___1);
  }
  }
}
}
#line 1245 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static int blt_ring_flush(struct intel_ring_buffer *ring , u32 invalidate , u32 flush ) 
{ uint32_t cmd ;
  int ret ;
  unsigned int __cil_tmp6 ;

  {
  {
#line 1251
  ret = blt_ring_begin(ring, 4);
  }
#line 1252
  if (ret != 0) {
#line 1253
    return (ret);
  } else {

  }
#line 1255
  cmd = 318767105U;
  {
#line 1256
  __cil_tmp6 = invalidate & 2U;
#line 1256
  if (__cil_tmp6 != 0U) {
#line 1257
    cmd = cmd | 262144U;
  } else {

  }
  }
  {
#line 1258
  intel_ring_emit(ring, cmd);
#line 1259
  intel_ring_emit(ring, 0U);
#line 1260
  intel_ring_emit(ring, 0U);
#line 1261
  intel_ring_emit(ring, 0U);
#line 1262
  intel_ring_advance(ring);
  }
#line 1263
  return (0);
}
}
#line 1266 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static void blt_ring_cleanup(struct intel_ring_buffer *ring ) 
{ void *__cil_tmp2 ;
  unsigned long __cil_tmp3 ;
  void *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  void *__cil_tmp6 ;
  struct drm_i915_gem_object *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_gem_object *__cil_tmp9 ;

  {
  {
#line 1268
  __cil_tmp2 = (void *)0;
#line 1268
  __cil_tmp3 = (unsigned long )__cil_tmp2;
#line 1268
  __cil_tmp4 = ring->private;
#line 1268
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 1268
  if (__cil_tmp5 == __cil_tmp3) {
#line 1269
    return;
  } else {

  }
  }
  {
#line 1271
  __cil_tmp6 = ring->private;
#line 1271
  __cil_tmp7 = (struct drm_i915_gem_object *)__cil_tmp6;
#line 1271
  i915_gem_object_unpin(__cil_tmp7);
#line 1272
  __cil_tmp8 = ring->private;
#line 1272
  __cil_tmp9 = (struct drm_gem_object *)__cil_tmp8;
#line 1272
  drm_gem_object_unreference(__cil_tmp9);
#line 1273
  ring->private = (void *)0;
  }
#line 1274
  return;
}
}
#line 1276 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
static struct intel_ring_buffer  const  gen6_blt_ring  = 
#line 1276
     {"blt ring", (enum intel_ring_id )4, 139264U, (void *)0, (struct drm_device *)0,
    (struct drm_i915_gem_object *)0, 0U, 0U, 0, 131072, 0, {(u32 *)0, 0U, (struct drm_i915_gem_object *)0},
    {{{{0U}, 0U, 0U, (void *)0, {(struct lock_class_key *)0, {(struct lock_class *)0,
                                                              (struct lock_class *)0},
                                 (char const   *)0, 0, 0UL}}}}, 0U, 0U, 0U, 0U, 0U,
    {0U, 0U}, & blt_ring_get_irq, & blt_ring_put_irq, & blt_ring_init, & ring_write_tail,
    & blt_ring_flush, & gen6_add_request, & ring_get_seqno, & gen6_ring_dispatch_execbuffer,
    & blt_ring_cleanup, {(struct list_head *)0, (struct list_head *)0}, {(struct list_head *)0,
                                                                         (struct list_head *)0},
    {(struct list_head *)0, (struct list_head *)0}, 0U, {{{{{0U}, 0U, 0U, (void *)0,
                                                            {(struct lock_class_key *)0,
                                                             {(struct lock_class *)0,
                                                              (struct lock_class *)0},
                                                             (char const   *)0, 0,
                                                             0UL}}}}, {(struct list_head *)0,
                                                                       (struct list_head *)0}},
    {0ULL, 0UL, (enum drm_map_type )0, (enum drm_map_flags )0, (void *)0, 0}, (void *)0};
#line 1292 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_init_render_ring_buffer(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_ring_buffer *ring ;
  int tmp ;
  void *__cil_tmp5 ;
  struct intel_ring_buffer (*__cil_tmp6)[3U] ;
  void *__cil_tmp7 ;
  struct drm_i915_private *__cil_tmp8 ;
  struct intel_device_info  const  *__cil_tmp9 ;
  u8 __cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  void *__cil_tmp13 ;
  struct drm_i915_private *__cil_tmp14 ;
  struct intel_device_info  const  *__cil_tmp15 ;
  u8 __cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  void *__cil_tmp19 ;
  struct drm_i915_private *__cil_tmp20 ;
  struct intel_device_info  const  *__cil_tmp21 ;
  unsigned char *__cil_tmp22 ;
  unsigned char *__cil_tmp23 ;
  unsigned char __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  drm_dma_handle_t *__cil_tmp26 ;
  void *__cil_tmp27 ;
  u32 *__cil_tmp28 ;
  void *__cil_tmp29 ;

  {
#line 1294
  __cil_tmp5 = dev->dev_private;
#line 1294
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 1295
  __cil_tmp6 = & dev_priv->ring;
#line 1295
  ring = (struct intel_ring_buffer *)__cil_tmp6;
#line 1297
  *ring = (struct intel_ring_buffer )render_ring;
  {
#line 1298
  __cil_tmp7 = dev->dev_private;
#line 1298
  __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
#line 1298
  __cil_tmp9 = __cil_tmp8->info;
#line 1298
  __cil_tmp10 = __cil_tmp9->gen;
#line 1298
  __cil_tmp11 = (unsigned char )__cil_tmp10;
#line 1298
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1298
  if (__cil_tmp12 > 5U) {
#line 1299
    ring->add_request = & gen6_add_request;
#line 1300
    ring->irq_get = & gen6_render_ring_get_irq;
#line 1301
    ring->irq_put = & gen6_render_ring_put_irq;
  } else {
    {
#line 1302
    __cil_tmp13 = dev->dev_private;
#line 1302
    __cil_tmp14 = (struct drm_i915_private *)__cil_tmp13;
#line 1302
    __cil_tmp15 = __cil_tmp14->info;
#line 1302
    __cil_tmp16 = __cil_tmp15->gen;
#line 1302
    __cil_tmp17 = (unsigned char )__cil_tmp16;
#line 1302
    __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 1302
    if (__cil_tmp18 == 5U) {
#line 1303
      ring->add_request = & pc_render_add_request;
#line 1304
      ring->get_seqno = & pc_render_get_seqno;
    } else {

    }
    }
  }
  }
  {
#line 1307
  __cil_tmp19 = dev->dev_private;
#line 1307
  __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
#line 1307
  __cil_tmp21 = __cil_tmp20->info;
#line 1307
  __cil_tmp22 = (unsigned char *)__cil_tmp21;
#line 1307
  __cil_tmp23 = __cil_tmp22 + 1UL;
#line 1307
  __cil_tmp24 = *__cil_tmp23;
#line 1307
  __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 1307
  if (__cil_tmp25 == 0U) {
    {
#line 1308
    __cil_tmp26 = dev_priv->status_page_dmah;
#line 1308
    __cil_tmp27 = __cil_tmp26->vaddr;
#line 1308
    ring->status_page.page_addr = (u32 *)__cil_tmp27;
#line 1309
    __cil_tmp28 = ring->status_page.page_addr;
#line 1309
    __cil_tmp29 = (void *)__cil_tmp28;
#line 1309
    memset(__cil_tmp29, 0, 4096UL);
    }
  } else {

  }
  }
  {
#line 1312
  tmp = intel_init_ring_buffer(dev, ring);
  }
#line 1312
  return (tmp);
}
}
#line 1315 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_render_ring_init_dri(struct drm_device *dev , u64 start , u32 size ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_ring_buffer *ring ;
  void *__cil_tmp6 ;
  struct intel_ring_buffer (*__cil_tmp7)[3U] ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  struct list_head *__cil_tmp20 ;
  struct list_head *__cil_tmp21 ;
  struct list_head *__cil_tmp22 ;
  struct drm_device *__cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  drm_local_map_t *__cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;
  void *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;

  {
#line 1317
  __cil_tmp6 = dev->dev_private;
#line 1317
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
#line 1318
  __cil_tmp7 = & dev_priv->ring;
#line 1318
  ring = (struct intel_ring_buffer *)__cil_tmp7;
#line 1320
  *ring = (struct intel_ring_buffer )render_ring;
  {
#line 1321
  __cil_tmp8 = dev->dev_private;
#line 1321
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 1321
  __cil_tmp10 = __cil_tmp9->info;
#line 1321
  __cil_tmp11 = __cil_tmp10->gen;
#line 1321
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 1321
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 1321
  if (__cil_tmp13 > 5U) {
#line 1322
    ring->add_request = & gen6_add_request;
#line 1323
    ring->irq_get = & gen6_render_ring_get_irq;
#line 1324
    ring->irq_put = & gen6_render_ring_put_irq;
  } else {
    {
#line 1325
    __cil_tmp14 = dev->dev_private;
#line 1325
    __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 1325
    __cil_tmp16 = __cil_tmp15->info;
#line 1325
    __cil_tmp17 = __cil_tmp16->gen;
#line 1325
    __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 1325
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 1325
    if (__cil_tmp19 == 5U) {
#line 1326
      ring->add_request = & pc_render_add_request;
#line 1327
      ring->get_seqno = & pc_render_get_seqno;
    } else {

    }
    }
  }
  }
  {
#line 1330
  ring->dev = dev;
#line 1331
  __cil_tmp20 = & ring->active_list;
#line 1331
  INIT_LIST_HEAD(__cil_tmp20);
#line 1332
  __cil_tmp21 = & ring->request_list;
#line 1332
  INIT_LIST_HEAD(__cil_tmp21);
#line 1333
  __cil_tmp22 = & ring->gpu_write_list;
#line 1333
  INIT_LIST_HEAD(__cil_tmp22);
#line 1335
  ring->size = (int )size;
#line 1336
  ring->effective_size = ring->size;
  }
  {
#line 1337
  __cil_tmp23 = ring->dev;
#line 1337
  __cil_tmp24 = __cil_tmp23->pci_device;
#line 1337
  if (__cil_tmp24 == 13687) {
#line 1338
    __cil_tmp25 = ring->effective_size;
#line 1338
    ring->effective_size = __cil_tmp25 + -128;
  } else {

  }
  }
  {
#line 1340
  ring->map.offset = start;
#line 1341
  ring->map.size = (unsigned long )size;
#line 1342
  ring->map.type = (enum drm_map_type )0;
#line 1343
  ring->map.flags = (enum drm_map_flags )0;
#line 1344
  ring->map.mtrr = 0;
#line 1346
  __cil_tmp26 = & ring->map;
#line 1346
  drm_core_ioremap_wc(__cil_tmp26, dev);
  }
  {
#line 1347
  __cil_tmp27 = (void *)0;
#line 1347
  __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 1347
  __cil_tmp29 = ring->map.handle;
#line 1347
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 1347
  if (__cil_tmp30 == __cil_tmp28) {
    {
#line 1348
    drm_err("intel_render_ring_init_dri", "can not ioremap virtual address for ring buffer\n");
    }
#line 1350
    return (-12);
  } else {

  }
  }
#line 1353
  ring->virtual_start = ring->map.handle;
#line 1354
  return (0);
}
}
#line 1357 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_init_bsd_ring_buffer(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_ring_buffer *ring ;
  int tmp ;
  void *__cil_tmp5 ;
  struct intel_ring_buffer (*__cil_tmp6)[3U] ;
  struct intel_ring_buffer *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned char __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  void *__cil_tmp14 ;
  struct drm_i915_private *__cil_tmp15 ;
  struct intel_device_info  const  *__cil_tmp16 ;
  u8 __cil_tmp17 ;
  unsigned char __cil_tmp18 ;
  unsigned int __cil_tmp19 ;

  {
#line 1359
  __cil_tmp5 = dev->dev_private;
#line 1359
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 1360
  __cil_tmp6 = & dev_priv->ring;
#line 1360
  __cil_tmp7 = (struct intel_ring_buffer *)__cil_tmp6;
#line 1360
  ring = __cil_tmp7 + 1UL;
  {
#line 1362
  __cil_tmp8 = dev->dev_private;
#line 1362
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 1362
  __cil_tmp10 = __cil_tmp9->info;
#line 1362
  __cil_tmp11 = __cil_tmp10->gen;
#line 1362
  __cil_tmp12 = (unsigned char )__cil_tmp11;
#line 1362
  __cil_tmp13 = (unsigned int )__cil_tmp12;
#line 1362
  if (__cil_tmp13 == 6U) {
#line 1363
    *ring = (struct intel_ring_buffer )gen6_bsd_ring;
  } else {
    {
#line 1362
    __cil_tmp14 = dev->dev_private;
#line 1362
    __cil_tmp15 = (struct drm_i915_private *)__cil_tmp14;
#line 1362
    __cil_tmp16 = __cil_tmp15->info;
#line 1362
    __cil_tmp17 = __cil_tmp16->gen;
#line 1362
    __cil_tmp18 = (unsigned char )__cil_tmp17;
#line 1362
    __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 1362
    if (__cil_tmp19 == 7U) {
#line 1363
      *ring = (struct intel_ring_buffer )gen6_bsd_ring;
    } else {
#line 1365
      *ring = (struct intel_ring_buffer )bsd_ring;
    }
    }
  }
  }
  {
#line 1367
  tmp = intel_init_ring_buffer(dev, ring);
  }
#line 1367
  return (tmp);
}
}
#line 1370 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_ringbuffer.c.p"
int intel_init_blt_ring_buffer(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_ring_buffer *ring ;
  int tmp ;
  void *__cil_tmp5 ;
  struct intel_ring_buffer (*__cil_tmp6)[3U] ;
  struct intel_ring_buffer *__cil_tmp7 ;

  {
  {
#line 1372
  __cil_tmp5 = dev->dev_private;
#line 1372
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 1373
  __cil_tmp6 = & dev_priv->ring;
#line 1373
  __cil_tmp7 = (struct intel_ring_buffer *)__cil_tmp6;
#line 1373
  ring = __cil_tmp7 + 2UL;
#line 1375
  *ring = (struct intel_ring_buffer )gen6_blt_ring;
#line 1377
  tmp = intel_init_ring_buffer(dev, ring);
  }
#line 1377
  return (tmp);
}
}
#line 200 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static struct overlay_registers *intel_overlay_map_regs(struct intel_overlay *overlay ) 
{ drm_i915_private_t *dev_priv ;
  struct overlay_registers *regs ;
  void *tmp ;
  struct drm_device *__cil_tmp5 ;
  void *__cil_tmp6 ;
  struct drm_device *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  unsigned char *__cil_tmp11 ;
  unsigned char *__cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  struct drm_i915_gem_object *__cil_tmp15 ;
  struct drm_i915_gem_phys_object *__cil_tmp16 ;
  drm_dma_handle_t *__cil_tmp17 ;
  void *__cil_tmp18 ;
  struct io_mapping *__cil_tmp19 ;
  struct drm_i915_gem_object *__cil_tmp20 ;
  uint32_t __cil_tmp21 ;
  unsigned long __cil_tmp22 ;

  {
#line 202
  __cil_tmp5 = overlay->dev;
#line 202
  __cil_tmp6 = __cil_tmp5->dev_private;
#line 202
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
  {
#line 205
  __cil_tmp7 = overlay->dev;
#line 205
  __cil_tmp8 = __cil_tmp7->dev_private;
#line 205
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 205
  __cil_tmp10 = __cil_tmp9->info;
#line 205
  __cil_tmp11 = (unsigned char *)__cil_tmp10;
#line 205
  __cil_tmp12 = __cil_tmp11 + 3UL;
#line 205
  __cil_tmp13 = *__cil_tmp12;
#line 205
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 205
  if (__cil_tmp14 != 0U) {
#line 206
    __cil_tmp15 = overlay->reg_bo;
#line 206
    __cil_tmp16 = __cil_tmp15->phys_obj;
#line 206
    __cil_tmp17 = __cil_tmp16->handle;
#line 206
    __cil_tmp18 = __cil_tmp17->vaddr;
#line 206
    regs = (struct overlay_registers *)__cil_tmp18;
  } else {
    {
#line 208
    __cil_tmp19 = dev_priv->mm.gtt_mapping;
#line 208
    __cil_tmp20 = overlay->reg_bo;
#line 208
    __cil_tmp21 = __cil_tmp20->gtt_offset;
#line 208
    __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 208
    tmp = io_mapping_map_atomic_wc(__cil_tmp19, __cil_tmp22);
#line 208
    regs = (struct overlay_registers *)tmp;
    }
  }
  }
#line 211
  return (regs);
}
}
#line 214 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void intel_overlay_unmap_regs(struct intel_overlay *overlay , struct overlay_registers *regs ) 
{ struct drm_device *__cil_tmp3 ;
  void *__cil_tmp4 ;
  struct drm_i915_private *__cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  unsigned char *__cil_tmp7 ;
  unsigned char *__cil_tmp8 ;
  unsigned char __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  void *__cil_tmp11 ;

  {
  {
#line 217
  __cil_tmp3 = overlay->dev;
#line 217
  __cil_tmp4 = __cil_tmp3->dev_private;
#line 217
  __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
#line 217
  __cil_tmp6 = __cil_tmp5->info;
#line 217
  __cil_tmp7 = (unsigned char *)__cil_tmp6;
#line 217
  __cil_tmp8 = __cil_tmp7 + 3UL;
#line 217
  __cil_tmp9 = *__cil_tmp8;
#line 217
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 217
  if (__cil_tmp10 == 0U) {
    {
#line 218
    __cil_tmp11 = (void *)regs;
#line 218
    io_mapping_unmap_atomic(__cil_tmp11);
    }
  } else {

  }
  }
#line 219
  return;
}
}
#line 221 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_do_wait_request(struct intel_overlay *overlay , struct drm_i915_gem_request *request ,
                                         void (*tail)(struct intel_overlay * ) ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  int ret ;
  long tmp ;
  void *__cil_tmp8 ;
  uint32_t __cil_tmp9 ;
  int __cil_tmp10 ;
  long __cil_tmp11 ;
  struct intel_ring_buffer (*__cil_tmp12)[3U] ;
  struct intel_ring_buffer *__cil_tmp13 ;
  struct drm_file *__cil_tmp14 ;
  void const   *__cil_tmp15 ;
  struct intel_ring_buffer (*__cil_tmp16)[3U] ;
  struct intel_ring_buffer *__cil_tmp17 ;
  uint32_t __cil_tmp18 ;

  {
  {
#line 225
  dev = overlay->dev;
#line 226
  __cil_tmp8 = dev->dev_private;
#line 226
  dev_priv = (drm_i915_private_t *)__cil_tmp8;
#line 229
  __cil_tmp9 = overlay->last_flip_req;
#line 229
  __cil_tmp10 = __cil_tmp9 != 0U;
#line 229
  __cil_tmp11 = (long )__cil_tmp10;
#line 229
  tmp = __builtin_expect(__cil_tmp11, 0L);
  }
#line 229
  if (tmp != 0L) {
#line 229
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (229), "i" (12UL));
    ldv_37636: ;
#line 229
    goto ldv_37636;
  } else {

  }
  {
#line 230
  __cil_tmp12 = & dev_priv->ring;
#line 230
  __cil_tmp13 = (struct intel_ring_buffer *)__cil_tmp12;
#line 230
  __cil_tmp14 = (struct drm_file *)0;
#line 230
  ret = i915_add_request(__cil_tmp13, __cil_tmp14, request);
  }
#line 231
  if (ret != 0) {
    {
#line 232
    __cil_tmp15 = (void const   *)request;
#line 232
    kfree(__cil_tmp15);
    }
#line 233
    return (ret);
  } else {

  }
  {
#line 235
  overlay->last_flip_req = request->seqno;
#line 236
  overlay->flip_tail = tail;
#line 237
  __cil_tmp16 = & dev_priv->ring;
#line 237
  __cil_tmp17 = (struct intel_ring_buffer *)__cil_tmp16;
#line 237
  __cil_tmp18 = overlay->last_flip_req;
#line 237
  ret = i915_wait_request(__cil_tmp17, __cil_tmp18);
  }
#line 238
  if (ret != 0) {
#line 239
    return (ret);
  } else {

  }
#line 241
  overlay->last_flip_req = 0U;
#line 242
  return (0);
}
}
#line 247 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int i830_activate_pipe_a(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_crtc *crtc ;
  struct drm_crtc_helper_funcs *crtc_funcs ;
  struct drm_display_mode vesa_640x480 ;
  struct drm_display_mode *mode ;
  struct drm_crtc  const  *__mptr ;
  u32 tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp11 ;
  struct drm_crtc *__cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  void *__cil_tmp15 ;
  void (*__cil_tmp16)(struct drm_crtc * , int  ) ;
  unsigned long __cil_tmp17 ;
  void (*__cil_tmp18)(struct drm_crtc * , int  ) ;
  unsigned long __cil_tmp19 ;
  struct drm_display_mode  const  *__cil_tmp20 ;
  struct drm_crtc *__cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  struct drm_framebuffer *__cil_tmp24 ;
  void (*__cil_tmp25)(struct drm_crtc * , int  ) ;
  struct drm_crtc *__cil_tmp26 ;

  {
#line 249
  __cil_tmp11 = dev->dev_private;
#line 249
  dev_priv = (drm_i915_private_t *)__cil_tmp11;
#line 252
  vesa_640x480.head.next = (struct list_head *)0;
#line 252
  vesa_640x480.head.prev = (struct list_head *)0;
#line 252
  vesa_640x480.base.id = 0U;
#line 252
  vesa_640x480.base.type = 0U;
#line 252
  vesa_640x480.name[0] = (char )'6';
#line 252
  vesa_640x480.name[1] = (char )'4';
#line 252
  vesa_640x480.name[2] = (char )'0';
#line 252
  vesa_640x480.name[3] = (char )'x';
#line 252
  vesa_640x480.name[4] = (char )'4';
#line 252
  vesa_640x480.name[5] = (char )'8';
#line 252
  vesa_640x480.name[6] = (char )'0';
#line 252
  vesa_640x480.name[7] = (char )'\000';
#line 252
  vesa_640x480.connector_count = 0;
#line 252
  vesa_640x480.status = (enum drm_mode_status )0;
#line 252
  vesa_640x480.type = 64;
#line 252
  vesa_640x480.clock = 25175;
#line 252
  vesa_640x480.hdisplay = 640;
#line 252
  vesa_640x480.hsync_start = 656;
#line 252
  vesa_640x480.hsync_end = 752;
#line 252
  vesa_640x480.htotal = 800;
#line 252
  vesa_640x480.hskew = 0;
#line 252
  vesa_640x480.vdisplay = 480;
#line 252
  vesa_640x480.vsync_start = 489;
#line 252
  vesa_640x480.vsync_end = 492;
#line 252
  vesa_640x480.vtotal = 525;
#line 252
  vesa_640x480.vscan = 0;
#line 252
  vesa_640x480.flags = 10U;
#line 252
  vesa_640x480.width_mm = 0;
#line 252
  vesa_640x480.height_mm = 0;
#line 252
  vesa_640x480.clock_index = 0;
#line 252
  vesa_640x480.synth_clock = 0;
#line 252
  vesa_640x480.crtc_hdisplay = 0;
#line 252
  vesa_640x480.crtc_hblank_start = 0;
#line 252
  vesa_640x480.crtc_hblank_end = 0;
#line 252
  vesa_640x480.crtc_hsync_start = 0;
#line 252
  vesa_640x480.crtc_hsync_end = 0;
#line 252
  vesa_640x480.crtc_htotal = 0;
#line 252
  vesa_640x480.crtc_hskew = 0;
#line 252
  vesa_640x480.crtc_vdisplay = 0;
#line 252
  vesa_640x480.crtc_vblank_start = 0;
#line 252
  vesa_640x480.crtc_vblank_end = 0;
#line 252
  vesa_640x480.crtc_vsync_start = 0;
#line 252
  vesa_640x480.crtc_vsync_end = 0;
#line 252
  vesa_640x480.crtc_vtotal = 0;
#line 252
  vesa_640x480.crtc_hadjusted = 0;
#line 252
  vesa_640x480.crtc_vadjusted = 0;
#line 252
  vesa_640x480.private_size = 0;
#line 252
  vesa_640x480.private = (int *)0;
#line 252
  vesa_640x480.private_flags = 0;
#line 252
  vesa_640x480.vrefresh = 0;
#line 252
  vesa_640x480.hsync = 0;
#line 258
  __cil_tmp12 = dev_priv->pipe_to_crtc_mapping[0];
#line 258
  __mptr = (struct drm_crtc  const  *)__cil_tmp12;
#line 258
  crtc = (struct intel_crtc *)__mptr;
  {
#line 259
  __cil_tmp13 = crtc->dpms_mode;
#line 259
  if (__cil_tmp13 == 0) {
#line 260
    return (0);
  } else {

  }
  }
  {
#line 263
  tmp = i915_read32(dev_priv, 458760U);
  }
  {
#line 263
  __cil_tmp14 = (int )tmp;
#line 263
  if (__cil_tmp14 < 0) {
#line 264
    return (0);
  } else {

  }
  }
#line 266
  __cil_tmp15 = crtc->base.helper_private;
#line 266
  crtc_funcs = (struct drm_crtc_helper_funcs *)__cil_tmp15;
  {
#line 267
  __cil_tmp16 = (void (*)(struct drm_crtc * , int  ))0;
#line 267
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 267
  __cil_tmp18 = crtc_funcs->dpms;
#line 267
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 267
  if (__cil_tmp19 == __cil_tmp17) {
#line 268
    return (0);
  } else {

  }
  }
  {
#line 270
  drm_ut_debug_printk(2U, "drm", "i830_activate_pipe_a", "Enabling pipe A in order to enable overlay\n");
#line 272
  __cil_tmp20 = (struct drm_display_mode  const  *)(& vesa_640x480);
#line 272
  mode = drm_mode_duplicate(dev, __cil_tmp20);
#line 273
  drm_mode_set_crtcinfo(mode, 1);
#line 274
  __cil_tmp21 = & crtc->base;
#line 274
  __cil_tmp22 = crtc->base.x;
#line 274
  __cil_tmp23 = crtc->base.y;
#line 274
  __cil_tmp24 = crtc->base.fb;
#line 274
  tmp___0 = drm_crtc_helper_set_mode(__cil_tmp21, mode, __cil_tmp22, __cil_tmp23,
                                     __cil_tmp24);
  }
#line 274
  if (tmp___0) {
#line 274
    tmp___1 = 0;
  } else {
#line 274
    tmp___1 = 1;
  }
#line 274
  if (tmp___1) {
#line 277
    return (0);
  } else {

  }
  {
#line 279
  __cil_tmp25 = crtc_funcs->dpms;
#line 279
  __cil_tmp26 = & crtc->base;
#line 279
  (*__cil_tmp25)(__cil_tmp26, 0);
  }
#line 280
  return (1);
}
}
#line 284 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void i830_deactivate_pipe_a(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct drm_crtc *crtc ;
  struct drm_crtc_helper_funcs *crtc_funcs ;
  void *__cil_tmp5 ;
  void *__cil_tmp6 ;
  void (*__cil_tmp7)(struct drm_crtc * , int  ) ;

  {
  {
#line 286
  __cil_tmp5 = dev->dev_private;
#line 286
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
#line 287
  crtc = dev_priv->pipe_to_crtc_mapping[0];
#line 288
  __cil_tmp6 = crtc->helper_private;
#line 288
  crtc_funcs = (struct drm_crtc_helper_funcs *)__cil_tmp6;
#line 290
  __cil_tmp7 = crtc_funcs->dpms;
#line 290
  (*__cil_tmp7)(crtc, 3);
  }
#line 291
  return;
}
}
#line 294 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_on(struct intel_overlay *overlay ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  struct drm_i915_gem_request *request ;
  int pipe_a_quirk ;
  int ret ;
  long tmp ;
  void *tmp___0 ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  long __cil_tmp12 ;
  int __cil_tmp13 ;
  struct drm_i915_gem_request *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct intel_ring_buffer (*__cil_tmp17)[3U] ;
  struct intel_ring_buffer *__cil_tmp18 ;
  void const   *__cil_tmp19 ;
  struct intel_ring_buffer (*__cil_tmp20)[3U] ;
  struct intel_ring_buffer *__cil_tmp21 ;
  struct intel_ring_buffer (*__cil_tmp22)[3U] ;
  struct intel_ring_buffer *__cil_tmp23 ;
  u32 __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  struct intel_ring_buffer (*__cil_tmp26)[3U] ;
  struct intel_ring_buffer *__cil_tmp27 ;
  struct intel_ring_buffer (*__cil_tmp28)[3U] ;
  struct intel_ring_buffer *__cil_tmp29 ;
  struct intel_ring_buffer (*__cil_tmp30)[3U] ;
  struct intel_ring_buffer *__cil_tmp31 ;
  void (*__cil_tmp32)(struct intel_overlay * ) ;

  {
  {
#line 296
  dev = overlay->dev;
#line 297
  __cil_tmp9 = dev->dev_private;
#line 297
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 299
  pipe_a_quirk = 0;
#line 302
  __cil_tmp10 = overlay->active;
#line 302
  __cil_tmp11 = __cil_tmp10 != 0;
#line 302
  __cil_tmp12 = (long )__cil_tmp11;
#line 302
  tmp = __builtin_expect(__cil_tmp12, 0L);
  }
#line 302
  if (tmp != 0L) {
#line 302
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (302), "i" (12UL));
    ldv_37662: ;
#line 302
    goto ldv_37662;
  } else {

  }
#line 303
  overlay->active = 1;
  {
#line 305
  __cil_tmp13 = dev->pci_device;
#line 305
  if (__cil_tmp13 == 13687) {
    {
#line 306
    pipe_a_quirk = i830_activate_pipe_a(dev);
    }
#line 307
    if (pipe_a_quirk < 0) {
#line 308
      return (pipe_a_quirk);
    } else {

    }
  } else {

  }
  }
  {
#line 311
  tmp___0 = kzalloc(64UL, 208U);
#line 311
  request = (struct drm_i915_gem_request *)tmp___0;
  }
  {
#line 312
  __cil_tmp14 = (struct drm_i915_gem_request *)0;
#line 312
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 312
  __cil_tmp16 = (unsigned long )request;
#line 312
  if (__cil_tmp16 == __cil_tmp15) {
#line 313
    ret = -12;
#line 314
    goto out;
  } else {

  }
  }
  {
#line 317
  __cil_tmp17 = & dev_priv->ring;
#line 317
  __cil_tmp18 = (struct intel_ring_buffer *)__cil_tmp17;
#line 317
  ret = intel_ring_begin(__cil_tmp18, 4);
  }
#line 318
  if (ret != 0) {
    {
#line 319
    __cil_tmp19 = (void const   *)request;
#line 319
    kfree(__cil_tmp19);
    }
#line 320
    goto out;
  } else {

  }
  {
#line 323
  __cil_tmp20 = & dev_priv->ring;
#line 323
  __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
#line 323
  intel_ring_emit(__cil_tmp21, 144703488U);
#line 324
  __cil_tmp22 = & dev_priv->ring;
#line 324
  __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
#line 324
  __cil_tmp24 = overlay->flip_addr;
#line 324
  __cil_tmp25 = __cil_tmp24 | 1U;
#line 324
  intel_ring_emit(__cil_tmp23, __cil_tmp25);
#line 325
  __cil_tmp26 = & dev_priv->ring;
#line 325
  __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
#line 325
  intel_ring_emit(__cil_tmp27, 25231360U);
#line 326
  __cil_tmp28 = & dev_priv->ring;
#line 326
  __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
#line 326
  intel_ring_emit(__cil_tmp29, 0U);
#line 327
  __cil_tmp30 = & dev_priv->ring;
#line 327
  __cil_tmp31 = (struct intel_ring_buffer *)__cil_tmp30;
#line 327
  intel_ring_advance(__cil_tmp31);
#line 329
  __cil_tmp32 = (void (*)(struct intel_overlay * ))0;
#line 329
  ret = intel_overlay_do_wait_request(overlay, request, __cil_tmp32);
  }
  out: ;
#line 331
  if (pipe_a_quirk != 0) {
    {
#line 332
    i830_deactivate_pipe_a(dev);
    }
  } else {

  }
#line 334
  return (ret);
}
}
#line 338 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_continue(struct intel_overlay *overlay , bool load_polyphase_filter ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  struct drm_i915_gem_request *request ;
  u32 flip_addr ;
  u32 tmp ;
  int ret ;
  long tmp___0 ;
  void *tmp___1 ;
  void *__cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  long __cil_tmp14 ;
  struct drm_i915_gem_request *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  struct intel_ring_buffer (*__cil_tmp19)[3U] ;
  struct intel_ring_buffer *__cil_tmp20 ;
  void const   *__cil_tmp21 ;
  struct intel_ring_buffer (*__cil_tmp22)[3U] ;
  struct intel_ring_buffer *__cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;
  struct intel_ring_buffer (*__cil_tmp26)[3U] ;
  struct intel_ring_buffer *__cil_tmp27 ;
  struct intel_ring_buffer (*__cil_tmp28)[3U] ;
  struct intel_ring_buffer *__cil_tmp29 ;
  struct drm_file *__cil_tmp30 ;
  void const   *__cil_tmp31 ;

  {
  {
#line 341
  dev = overlay->dev;
#line 342
  __cil_tmp11 = dev->dev_private;
#line 342
  dev_priv = (drm_i915_private_t *)__cil_tmp11;
#line 344
  flip_addr = overlay->flip_addr;
#line 348
  __cil_tmp12 = overlay->active;
#line 348
  __cil_tmp13 = __cil_tmp12 == 0;
#line 348
  __cil_tmp14 = (long )__cil_tmp13;
#line 348
  tmp___0 = __builtin_expect(__cil_tmp14, 0L);
  }
#line 348
  if (tmp___0 != 0L) {
#line 348
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (348), "i" (12UL));
    ldv_37674: ;
#line 348
    goto ldv_37674;
  } else {

  }
  {
#line 350
  tmp___1 = kzalloc(64UL, 208U);
#line 350
  request = (struct drm_i915_gem_request *)tmp___1;
  }
  {
#line 351
  __cil_tmp15 = (struct drm_i915_gem_request *)0;
#line 351
  __cil_tmp16 = (unsigned long )__cil_tmp15;
#line 351
  __cil_tmp17 = (unsigned long )request;
#line 351
  if (__cil_tmp17 == __cil_tmp16) {
#line 352
    return (-12);
  } else {

  }
  }
#line 354
  if ((int )load_polyphase_filter) {
#line 355
    flip_addr = flip_addr | 1U;
  } else {

  }
  {
#line 358
  tmp = i915_read32(dev_priv, 196616U);
  }
  {
#line 359
  __cil_tmp18 = tmp & 131072U;
#line 359
  if (__cil_tmp18 != 0U) {
    {
#line 360
    drm_ut_debug_printk(1U, "drm", "intel_overlay_continue", "overlay underrun, DOVSTA: %x\n",
                        tmp);
    }
  } else {

  }
  }
  {
#line 362
  __cil_tmp19 = & dev_priv->ring;
#line 362
  __cil_tmp20 = (struct intel_ring_buffer *)__cil_tmp19;
#line 362
  ret = intel_ring_begin(__cil_tmp20, 2);
  }
#line 363
  if (ret != 0) {
    {
#line 364
    __cil_tmp21 = (void const   *)request;
#line 364
    kfree(__cil_tmp21);
    }
#line 365
    return (ret);
  } else {

  }
  {
#line 367
  __cil_tmp22 = & dev_priv->ring;
#line 367
  __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
#line 367
  intel_ring_emit(__cil_tmp23, 142606336U);
#line 368
  __cil_tmp24 = & dev_priv->ring;
#line 368
  __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 368
  intel_ring_emit(__cil_tmp25, flip_addr);
#line 369
  __cil_tmp26 = & dev_priv->ring;
#line 369
  __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
#line 369
  intel_ring_advance(__cil_tmp27);
#line 371
  __cil_tmp28 = & dev_priv->ring;
#line 371
  __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
#line 371
  __cil_tmp30 = (struct drm_file *)0;
#line 371
  ret = i915_add_request(__cil_tmp29, __cil_tmp30, request);
  }
#line 372
  if (ret != 0) {
    {
#line 373
    __cil_tmp31 = (void const   *)request;
#line 373
    kfree(__cil_tmp31);
    }
#line 374
    return (ret);
  } else {

  }
#line 377
  overlay->last_flip_req = request->seqno;
#line 378
  return (0);
}
}
#line 381 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay ) 
{ struct drm_i915_gem_object *obj ;
  struct drm_gem_object *__cil_tmp3 ;

  {
  {
#line 383
  obj = overlay->old_vid_bo;
#line 385
  i915_gem_object_unpin(obj);
#line 386
  __cil_tmp3 = & obj->base;
#line 386
  drm_gem_object_unreference(__cil_tmp3);
#line 388
  overlay->old_vid_bo = (struct drm_i915_gem_object *)0;
  }
#line 389
  return;
}
}
#line 391 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void intel_overlay_off_tail(struct intel_overlay *overlay ) 
{ struct drm_i915_gem_object *obj ;
  long tmp ;
  struct drm_i915_gem_object *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  struct drm_i915_gem_object *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  int __cil_tmp8 ;
  long __cil_tmp9 ;
  struct drm_gem_object *__cil_tmp10 ;
  struct intel_crtc *__cil_tmp11 ;

  {
  {
#line 393
  obj = overlay->vid_bo;
#line 396
  __cil_tmp4 = (struct drm_i915_gem_object *)0;
#line 396
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 396
  __cil_tmp6 = overlay->vid_bo;
#line 396
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 396
  __cil_tmp8 = __cil_tmp7 == __cil_tmp5;
#line 396
  __cil_tmp9 = (long )__cil_tmp8;
#line 396
  tmp = __builtin_expect(__cil_tmp9, 0L);
  }
#line 396
  if (tmp != 0L) {
#line 396
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (396), "i" (12UL));
    ldv_37684: ;
#line 396
    goto ldv_37684;
  } else {

  }
  {
#line 398
  i915_gem_object_unpin(obj);
#line 399
  __cil_tmp10 = & obj->base;
#line 399
  drm_gem_object_unreference(__cil_tmp10);
#line 400
  overlay->vid_bo = (struct drm_i915_gem_object *)0;
#line 402
  __cil_tmp11 = overlay->crtc;
#line 402
  __cil_tmp11->overlay = (struct intel_overlay *)0;
#line 403
  overlay->crtc = (struct intel_crtc *)0;
#line 404
  overlay->active = 0;
  }
#line 405
  return;
}
}
#line 408 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_off(struct intel_overlay *overlay ) 
{ struct drm_device *dev ;
  struct drm_i915_private *dev_priv ;
  u32 flip_addr ;
  struct drm_i915_gem_request *request ;
  int ret ;
  long tmp ;
  void *tmp___0 ;
  int tmp___1 ;
  void *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  long __cil_tmp13 ;
  struct drm_i915_gem_request *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct intel_ring_buffer (*__cil_tmp17)[3U] ;
  struct intel_ring_buffer *__cil_tmp18 ;
  void const   *__cil_tmp19 ;
  struct intel_ring_buffer (*__cil_tmp20)[3U] ;
  struct intel_ring_buffer *__cil_tmp21 ;
  struct intel_ring_buffer (*__cil_tmp22)[3U] ;
  struct intel_ring_buffer *__cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;
  struct intel_ring_buffer (*__cil_tmp26)[3U] ;
  struct intel_ring_buffer *__cil_tmp27 ;
  struct intel_ring_buffer (*__cil_tmp28)[3U] ;
  struct intel_ring_buffer *__cil_tmp29 ;
  struct intel_ring_buffer (*__cil_tmp30)[3U] ;
  struct intel_ring_buffer *__cil_tmp31 ;
  struct intel_ring_buffer (*__cil_tmp32)[3U] ;
  struct intel_ring_buffer *__cil_tmp33 ;

  {
  {
#line 410
  dev = overlay->dev;
#line 411
  __cil_tmp10 = dev->dev_private;
#line 411
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 412
  flip_addr = overlay->flip_addr;
#line 416
  __cil_tmp11 = overlay->active;
#line 416
  __cil_tmp12 = __cil_tmp11 == 0;
#line 416
  __cil_tmp13 = (long )__cil_tmp12;
#line 416
  tmp = __builtin_expect(__cil_tmp13, 0L);
  }
#line 416
  if (tmp != 0L) {
#line 416
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (416), "i" (12UL));
    ldv_37693: ;
#line 416
    goto ldv_37693;
  } else {

  }
  {
#line 418
  tmp___0 = kzalloc(64UL, 208U);
#line 418
  request = (struct drm_i915_gem_request *)tmp___0;
  }
  {
#line 419
  __cil_tmp14 = (struct drm_i915_gem_request *)0;
#line 419
  __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 419
  __cil_tmp16 = (unsigned long )request;
#line 419
  if (__cil_tmp16 == __cil_tmp15) {
#line 420
    return (-12);
  } else {

  }
  }
  {
#line 426
  flip_addr = flip_addr | 1U;
#line 428
  __cil_tmp17 = & dev_priv->ring;
#line 428
  __cil_tmp18 = (struct intel_ring_buffer *)__cil_tmp17;
#line 428
  ret = intel_ring_begin(__cil_tmp18, 6);
  }
#line 429
  if (ret != 0) {
    {
#line 430
    __cil_tmp19 = (void const   *)request;
#line 430
    kfree(__cil_tmp19);
    }
#line 431
    return (ret);
  } else {

  }
  {
#line 434
  __cil_tmp20 = & dev_priv->ring;
#line 434
  __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
#line 434
  intel_ring_emit(__cil_tmp21, 142606336U);
#line 435
  __cil_tmp22 = & dev_priv->ring;
#line 435
  __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
#line 435
  intel_ring_emit(__cil_tmp23, flip_addr);
#line 436
  __cil_tmp24 = & dev_priv->ring;
#line 436
  __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 436
  intel_ring_emit(__cil_tmp25, 25231360U);
#line 438
  __cil_tmp26 = & dev_priv->ring;
#line 438
  __cil_tmp27 = (struct intel_ring_buffer *)__cil_tmp26;
#line 438
  intel_ring_emit(__cil_tmp27, 146800640U);
#line 439
  __cil_tmp28 = & dev_priv->ring;
#line 439
  __cil_tmp29 = (struct intel_ring_buffer *)__cil_tmp28;
#line 439
  intel_ring_emit(__cil_tmp29, flip_addr);
#line 440
  __cil_tmp30 = & dev_priv->ring;
#line 440
  __cil_tmp31 = (struct intel_ring_buffer *)__cil_tmp30;
#line 440
  intel_ring_emit(__cil_tmp31, 25231360U);
#line 441
  __cil_tmp32 = & dev_priv->ring;
#line 441
  __cil_tmp33 = (struct intel_ring_buffer *)__cil_tmp32;
#line 441
  intel_ring_advance(__cil_tmp33);
#line 443
  tmp___1 = intel_overlay_do_wait_request(overlay, request, & intel_overlay_off_tail);
  }
#line 443
  return (tmp___1);
}
}
#line 449 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  int ret ;
  void *__cil_tmp5 ;
  uint32_t __cil_tmp6 ;
  struct intel_ring_buffer (*__cil_tmp7)[3U] ;
  struct intel_ring_buffer *__cil_tmp8 ;
  uint32_t __cil_tmp9 ;
  void (*__cil_tmp10)(struct intel_overlay * ) ;
  unsigned long __cil_tmp11 ;
  void (*__cil_tmp12)(struct intel_overlay * ) ;
  unsigned long __cil_tmp13 ;
  void (*__cil_tmp14)(struct intel_overlay * ) ;

  {
#line 451
  dev = overlay->dev;
#line 452
  __cil_tmp5 = dev->dev_private;
#line 452
  dev_priv = (drm_i915_private_t *)__cil_tmp5;
  {
#line 455
  __cil_tmp6 = overlay->last_flip_req;
#line 455
  if (__cil_tmp6 == 0U) {
#line 456
    return (0);
  } else {

  }
  }
  {
#line 458
  __cil_tmp7 = & dev_priv->ring;
#line 458
  __cil_tmp8 = (struct intel_ring_buffer *)__cil_tmp7;
#line 458
  __cil_tmp9 = overlay->last_flip_req;
#line 458
  ret = i915_wait_request(__cil_tmp8, __cil_tmp9);
  }
#line 459
  if (ret != 0) {
#line 460
    return (ret);
  } else {

  }
  {
#line 462
  __cil_tmp10 = (void (*)(struct intel_overlay * ))0;
#line 462
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 462
  __cil_tmp12 = overlay->flip_tail;
#line 462
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 462
  if (__cil_tmp13 != __cil_tmp11) {
    {
#line 463
    __cil_tmp14 = overlay->flip_tail;
#line 463
    (*__cil_tmp14)(overlay);
    }
  } else {

  }
  }
#line 465
  overlay->last_flip_req = 0U;
#line 466
  return (0);
}
}
#line 473 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_release_old_vid(struct intel_overlay *overlay ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  int ret ;
  struct drm_i915_gem_request *request ;
  void *tmp ;
  u32 tmp___0 ;
  void *__cil_tmp8 ;
  struct drm_i915_gem_object *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct drm_i915_gem_object *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  struct drm_i915_gem_request *__cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  struct intel_ring_buffer (*__cil_tmp17)[3U] ;
  struct intel_ring_buffer *__cil_tmp18 ;
  void const   *__cil_tmp19 ;
  struct intel_ring_buffer (*__cil_tmp20)[3U] ;
  struct intel_ring_buffer *__cil_tmp21 ;
  struct intel_ring_buffer (*__cil_tmp22)[3U] ;
  struct intel_ring_buffer *__cil_tmp23 ;
  struct intel_ring_buffer (*__cil_tmp24)[3U] ;
  struct intel_ring_buffer *__cil_tmp25 ;

  {
#line 475
  dev = overlay->dev;
#line 476
  __cil_tmp8 = dev->dev_private;
#line 476
  dev_priv = (drm_i915_private_t *)__cil_tmp8;
  {
#line 482
  __cil_tmp9 = (struct drm_i915_gem_object *)0;
#line 482
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 482
  __cil_tmp11 = overlay->old_vid_bo;
#line 482
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 482
  if (__cil_tmp12 == __cil_tmp10) {
#line 483
    return (0);
  } else {

  }
  }
  {
#line 485
  tmp___0 = i915_read32(dev_priv, 8364U);
  }
  {
#line 485
  __cil_tmp13 = tmp___0 & 512U;
#line 485
  if (__cil_tmp13 != 0U) {
    {
#line 489
    tmp = kzalloc(64UL, 208U);
#line 489
    request = (struct drm_i915_gem_request *)tmp;
    }
    {
#line 490
    __cil_tmp14 = (struct drm_i915_gem_request *)0;
#line 490
    __cil_tmp15 = (unsigned long )__cil_tmp14;
#line 490
    __cil_tmp16 = (unsigned long )request;
#line 490
    if (__cil_tmp16 == __cil_tmp15) {
#line 491
      return (-12);
    } else {

    }
    }
    {
#line 493
    __cil_tmp17 = & dev_priv->ring;
#line 493
    __cil_tmp18 = (struct intel_ring_buffer *)__cil_tmp17;
#line 493
    ret = intel_ring_begin(__cil_tmp18, 2);
    }
#line 494
    if (ret != 0) {
      {
#line 495
      __cil_tmp19 = (void const   *)request;
#line 495
      kfree(__cil_tmp19);
      }
#line 496
      return (ret);
    } else {

    }
    {
#line 499
    __cil_tmp20 = & dev_priv->ring;
#line 499
    __cil_tmp21 = (struct intel_ring_buffer *)__cil_tmp20;
#line 499
    intel_ring_emit(__cil_tmp21, 25231360U);
#line 500
    __cil_tmp22 = & dev_priv->ring;
#line 500
    __cil_tmp23 = (struct intel_ring_buffer *)__cil_tmp22;
#line 500
    intel_ring_emit(__cil_tmp23, 0U);
#line 501
    __cil_tmp24 = & dev_priv->ring;
#line 501
    __cil_tmp25 = (struct intel_ring_buffer *)__cil_tmp24;
#line 501
    intel_ring_advance(__cil_tmp25);
#line 503
    ret = intel_overlay_do_wait_request(overlay, request, & intel_overlay_release_old_vid_tail);
    }
#line 505
    if (ret != 0) {
#line 506
      return (ret);
    } else {

    }
  } else {

  }
  }
  {
#line 509
  intel_overlay_release_old_vid_tail(overlay);
  }
#line 510
  return (0);
}
}
#line 530 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int packed_depth_bytes(u32 format ) 
{ unsigned int __cil_tmp2 ;
  int __cil_tmp3 ;
  unsigned int __cil_tmp4 ;
  int __cil_tmp5 ;

  {
  {
#line 533
  __cil_tmp2 = format & 65280U;
#line 533
  __cil_tmp3 = (int )__cil_tmp2;
#line 533
  if (__cil_tmp3 == 256) {
#line 533
    goto case_256;
  } else {
    {
#line 535
    __cil_tmp4 = format & 65280U;
#line 535
    __cil_tmp5 = (int )__cil_tmp4;
#line 535
    if (__cil_tmp5 == 512) {
#line 535
      goto case_512;
    } else {
#line 537
      goto switch_default;
#line 532
      if (0) {
        case_256: ;
#line 534
        return (4);
        case_512: ;
        switch_default: ;
#line 538
        return (-22);
      } else {

      }
    }
    }
  }
  }
}
}
#line 542 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int packed_width_bytes(u32 format , short width ) 
{ unsigned int __cil_tmp3 ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;

  {
  {
#line 545
  __cil_tmp3 = format & 65280U;
#line 545
  __cil_tmp4 = (int )__cil_tmp3;
#line 545
  if (__cil_tmp4 == 256) {
#line 545
    goto case_256;
  } else {
#line 547
    goto switch_default;
#line 544
    if (0) {
      case_256: ;
      {
#line 546
      __cil_tmp5 = (int )width;
#line 546
      return (__cil_tmp5 << 1);
      }
      switch_default: ;
#line 548
      return (-22);
    } else {

    }
  }
  }
}
}
#line 552 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int uv_hsubsampling(u32 format ) 
{ unsigned int __cil_tmp2 ;
  int __cil_tmp3 ;
  unsigned int __cil_tmp4 ;
  int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  int __cil_tmp9 ;

  {
  {
#line 555
  __cil_tmp2 = format & 65280U;
#line 555
  __cil_tmp3 = (int )__cil_tmp2;
#line 555
  if (__cil_tmp3 == 256) {
#line 555
    goto case_256;
  } else {
    {
#line 556
    __cil_tmp4 = format & 65280U;
#line 556
    __cil_tmp5 = (int )__cil_tmp4;
#line 556
    if (__cil_tmp5 == 768) {
#line 556
      goto case_768;
    } else {
      {
#line 558
      __cil_tmp6 = format & 65280U;
#line 558
      __cil_tmp7 = (int )__cil_tmp6;
#line 558
      if (__cil_tmp7 == 512) {
#line 558
        goto case_512;
      } else {
        {
#line 559
        __cil_tmp8 = format & 65280U;
#line 559
        __cil_tmp9 = (int )__cil_tmp8;
#line 559
        if (__cil_tmp9 == 1024) {
#line 559
          goto case_1024;
        } else {
#line 561
          goto switch_default;
#line 554
          if (0) {
            case_256: ;
            case_768: ;
#line 557
            return (2);
            case_512: ;
            case_1024: ;
#line 560
            return (4);
            switch_default: ;
#line 562
            return (-22);
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
}
}
#line 566 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int uv_vsubsampling(u32 format ) 
{ unsigned int __cil_tmp2 ;
  int __cil_tmp3 ;
  unsigned int __cil_tmp4 ;
  int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  int __cil_tmp9 ;

  {
  {
#line 569
  __cil_tmp2 = format & 65280U;
#line 569
  __cil_tmp3 = (int )__cil_tmp2;
#line 569
  if (__cil_tmp3 == 768) {
#line 569
    goto case_768;
  } else {
    {
#line 570
    __cil_tmp4 = format & 65280U;
#line 570
    __cil_tmp5 = (int )__cil_tmp4;
#line 570
    if (__cil_tmp5 == 1024) {
#line 570
      goto case_1024;
    } else {
      {
#line 572
      __cil_tmp6 = format & 65280U;
#line 572
      __cil_tmp7 = (int )__cil_tmp6;
#line 572
      if (__cil_tmp7 == 256) {
#line 572
        goto case_256;
      } else {
        {
#line 573
        __cil_tmp8 = format & 65280U;
#line 573
        __cil_tmp9 = (int )__cil_tmp8;
#line 573
        if (__cil_tmp9 == 512) {
#line 573
          goto case_512;
        } else {
#line 575
          goto switch_default;
#line 568
          if (0) {
            case_768: ;
            case_1024: ;
#line 571
            return (2);
            case_256: ;
            case_512: ;
#line 574
            return (1);
            switch_default: ;
#line 576
            return (-22);
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
}
}
#line 580 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static u32 calc_swidthsw(struct drm_device *dev , u32 offset , u32 width ) 
{ u32 mask ;
  u32 shift ;
  u32 ret ;
  void *__cil_tmp7 ;
  struct drm_i915_private *__cil_tmp8 ;
  struct intel_device_info  const  *__cil_tmp9 ;
  u8 __cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  int __cil_tmp13 ;
  u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  u32 __cil_tmp16 ;
  u32 __cil_tmp17 ;
  u32 __cil_tmp18 ;
  void *__cil_tmp19 ;
  struct drm_i915_private *__cil_tmp20 ;
  struct intel_device_info  const  *__cil_tmp21 ;
  u8 __cil_tmp22 ;
  unsigned char __cil_tmp23 ;
  unsigned int __cil_tmp24 ;

  {
  {
#line 583
  __cil_tmp7 = dev->dev_private;
#line 583
  __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
#line 583
  __cil_tmp9 = __cil_tmp8->info;
#line 583
  __cil_tmp10 = __cil_tmp9->gen;
#line 583
  __cil_tmp11 = (unsigned char )__cil_tmp10;
#line 583
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 583
  if (__cil_tmp12 == 2U) {
#line 584
    mask = 31U;
#line 585
    shift = 5U;
  } else {
#line 587
    mask = 63U;
#line 588
    shift = 6U;
  }
  }
#line 590
  __cil_tmp13 = (int )shift;
#line 590
  __cil_tmp14 = offset >> __cil_tmp13;
#line 590
  __cil_tmp15 = (int )shift;
#line 590
  __cil_tmp16 = offset + width;
#line 590
  __cil_tmp17 = __cil_tmp16 + mask;
#line 590
  __cil_tmp18 = __cil_tmp17 >> __cil_tmp15;
#line 590
  ret = __cil_tmp18 - __cil_tmp14;
  {
#line 591
  __cil_tmp19 = dev->dev_private;
#line 591
  __cil_tmp20 = (struct drm_i915_private *)__cil_tmp19;
#line 591
  __cil_tmp21 = __cil_tmp20->info;
#line 591
  __cil_tmp22 = __cil_tmp21->gen;
#line 591
  __cil_tmp23 = (unsigned char )__cil_tmp22;
#line 591
  __cil_tmp24 = (unsigned int )__cil_tmp23;
#line 591
  if (__cil_tmp24 != 2U) {
#line 592
    ret = ret << 1;
  } else {

  }
  }
#line 593
  ret = ret - 1U;
#line 594
  return (ret << 2);
}
}
#line 597 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static u16 const   y_static_hcoeffs[85U]  = 
#line 597
  {      (u16 const   )12288U,      (u16 const   )46240U,      (u16 const   )6448U,      (u16 const   )6432U, 
        (u16 const   )46240U,      (u16 const   )12288U,      (u16 const   )46336U,      (u16 const   )6608U, 
        (u16 const   )6272U,      (u16 const   )46144U,      (u16 const   )12288U,      (u16 const   )46400U, 
        (u16 const   )6792U,      (u16 const   )12160U,      (u16 const   )46048U,      (u16 const   )12288U, 
        (u16 const   )46464U,      (u16 const   )6960U,      (u16 const   )11808U,      (u16 const   )45952U, 
        (u16 const   )12288U,      (u16 const   )46528U,      (u16 const   )7128U,      (u16 const   )11456U, 
        (u16 const   )45856U,      (u16 const   )12320U,      (u16 const   )46560U,      (u16 const   )7264U, 
        (u16 const   )11136U,      (u16 const   )45760U,      (u16 const   )12320U,      (u16 const   )46560U, 
        (u16 const   )7416U,      (u16 const   )10784U,      (u16 const   )45664U,      (u16 const   )12320U, 
        (u16 const   )46560U,      (u16 const   )7552U,      (u16 const   )10464U,      (u16 const   )45568U, 
        (u16 const   )12320U,      (u16 const   )46528U,      (u16 const   )7688U,      (u16 const   )16192U, 
        (u16 const   )45504U,      (u16 const   )12320U,      (u16 const   )46464U,      (u16 const   )7800U, 
        (u16 const   )15584U,      (u16 const   )45408U,      (u16 const   )12352U,      (u16 const   )46368U, 
        (u16 const   )7896U,      (u16 const   )15008U,      (u16 const   )45344U,      (u16 const   )12352U, 
        (u16 const   )46240U,      (u16 const   )7984U,      (u16 const   )14464U,      (u16 const   )45280U, 
        (u16 const   )12352U,      (u16 const   )46080U,      (u16 const   )8056U,      (u16 const   )13952U, 
        (u16 const   )45216U,      (u16 const   )12320U,      (u16 const   )45888U,      (u16 const   )8120U, 
        (u16 const   )13472U,      (u16 const   )45152U,      (u16 const   )12320U,      (u16 const   )45632U, 
        (u16 const   )8160U,      (u16 const   )13024U,      (u16 const   )45120U,      (u16 const   )12320U, 
        (u16 const   )45376U,      (u16 const   )8184U,      (u16 const   )12640U,      (u16 const   )45088U, 
        (u16 const   )45056U,      (u16 const   )12288U,      (u16 const   )2048U,      (u16 const   )12288U, 
        (u16 const   )45056U};
#line 617 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static u16 const   uv_static_hcoeffs[51U]  = 
#line 617
  {      (u16 const   )12288U,      (u16 const   )6144U,      (u16 const   )6144U,      (u16 const   )45056U, 
        (u16 const   )6352U,      (u16 const   )11872U,      (u16 const   )45056U,      (u16 const   )6544U, 
        (u16 const   )11488U,      (u16 const   )45088U,      (u16 const   )6760U,      (u16 const   )11072U, 
        (u16 const   )45120U,      (u16 const   )6944U,      (u16 const   )10720U,      (u16 const   )45152U, 
        (u16 const   )7128U,      (u16 const   )10368U,      (u16 const   )45184U,      (u16 const   )7304U, 
        (u16 const   )15968U,      (u16 const   )45216U,      (u16 const   )7464U,      (u16 const   )15360U, 
        (u16 const   )45248U,      (u16 const   )7608U,      (u16 const   )14816U,      (u16 const   )45280U, 
        (u16 const   )7744U,      (u16 const   )14304U,      (u16 const   )45312U,      (u16 const   )7864U, 
        (u16 const   )13856U,      (u16 const   )45312U,      (u16 const   )7960U,      (u16 const   )13472U, 
        (u16 const   )45312U,      (u16 const   )8040U,      (u16 const   )13152U,      (u16 const   )45280U, 
        (u16 const   )8104U,      (u16 const   )12864U,      (u16 const   )45248U,      (u16 const   )8160U, 
        (u16 const   )12608U,      (u16 const   )45152U,      (u16 const   )8176U,      (u16 const   )12448U, 
        (u16 const   )12288U,      (u16 const   )2048U,      (u16 const   )12288U};
#line 629 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void update_polyphase_filter(struct overlay_registers *regs ) 
{ size_t __len ;
  void *__ret ;
  size_t __len___0 ;
  void *__ret___0 ;
  u16 (*__cil_tmp6)[85U] ;
  void *__cil_tmp7 ;
  void const   *__cil_tmp8 ;
  u16 (*__cil_tmp9)[85U] ;
  void *__cil_tmp10 ;
  void const   *__cil_tmp11 ;
  u16 (*__cil_tmp12)[51U] ;
  void *__cil_tmp13 ;
  void const   *__cil_tmp14 ;
  u16 (*__cil_tmp15)[51U] ;
  void *__cil_tmp16 ;
  void const   *__cil_tmp17 ;

  {
#line 631
  __len = 170UL;
#line 631
  if (__len > 63UL) {
    {
#line 631
    __cil_tmp6 = & regs->Y_HCOEFS;
#line 631
    __cil_tmp7 = (void *)__cil_tmp6;
#line 631
    __cil_tmp8 = (void const   *)(& y_static_hcoeffs);
#line 631
    __ret = __memcpy(__cil_tmp7, __cil_tmp8, __len);
    }
  } else {
    {
#line 631
    __cil_tmp9 = & regs->Y_HCOEFS;
#line 631
    __cil_tmp10 = (void *)__cil_tmp9;
#line 631
    __cil_tmp11 = (void const   *)(& y_static_hcoeffs);
#line 631
    __ret = __builtin_memcpy(__cil_tmp10, __cil_tmp11, __len);
    }
  }
#line 632
  __len___0 = 102UL;
#line 632
  if (__len___0 > 63UL) {
    {
#line 632
    __cil_tmp12 = & regs->UV_HCOEFS;
#line 632
    __cil_tmp13 = (void *)__cil_tmp12;
#line 632
    __cil_tmp14 = (void const   *)(& uv_static_hcoeffs);
#line 632
    __ret___0 = __memcpy(__cil_tmp13, __cil_tmp14, __len___0);
    }
  } else {
    {
#line 632
    __cil_tmp15 = & regs->UV_HCOEFS;
#line 632
    __cil_tmp16 = (void *)__cil_tmp15;
#line 632
    __cil_tmp17 = (void const   *)(& uv_static_hcoeffs);
#line 632
    __ret___0 = __builtin_memcpy(__cil_tmp16, __cil_tmp17, __len___0);
    }
  }
#line 634
  return;
}
}
#line 635 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static bool update_scaling_factors(struct intel_overlay *overlay , struct overlay_registers *regs ,
                                   struct put_image_params *params ) 
{ u32 xscale ;
  u32 yscale ;
  u32 xscale_UV ;
  u32 yscale_UV ;
  bool scale_changed ;
  int uv_hscale ;
  int tmp ;
  int uv_vscale ;
  int tmp___0 ;
  int __cil_tmp13 ;
  u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  u32 __cil_tmp16 ;
  short __cil_tmp17 ;
  int __cil_tmp18 ;
  short __cil_tmp19 ;
  int __cil_tmp20 ;
  short __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  short __cil_tmp26 ;
  int __cil_tmp27 ;
  short __cil_tmp28 ;
  int __cil_tmp29 ;
  short __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  int __cil_tmp34 ;
  u32 __cil_tmp35 ;
  u32 __cil_tmp36 ;
  u32 __cil_tmp37 ;
  u32 __cil_tmp38 ;
  u32 __cil_tmp39 ;
  u32 __cil_tmp40 ;
  unsigned int __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  u32 __cil_tmp43 ;
  u32 __cil_tmp44 ;
  u32 __cil_tmp45 ;
  unsigned int __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  u32 __cil_tmp49 ;
  u32 __cil_tmp50 ;
  u32 __cil_tmp51 ;
  unsigned int __cil_tmp52 ;
  u32 __cil_tmp53 ;
  u32 __cil_tmp54 ;
  u32 __cil_tmp55 ;

  {
  {
#line 643
  scale_changed = (bool )0;
#line 644
  __cil_tmp13 = params->format;
#line 644
  __cil_tmp14 = (u32 )__cil_tmp13;
#line 644
  tmp = uv_hsubsampling(__cil_tmp14);
#line 644
  uv_hscale = tmp;
#line 645
  __cil_tmp15 = params->format;
#line 645
  __cil_tmp16 = (u32 )__cil_tmp15;
#line 645
  tmp___0 = uv_vsubsampling(__cil_tmp16);
#line 645
  uv_vscale = tmp___0;
  }
  {
#line 647
  __cil_tmp17 = params->dst_w;
#line 647
  __cil_tmp18 = (int )__cil_tmp17;
#line 647
  if (__cil_tmp18 > 1) {
#line 648
    __cil_tmp19 = params->dst_w;
#line 648
    __cil_tmp20 = (int )__cil_tmp19;
#line 648
    __cil_tmp21 = params->src_scan_w;
#line 648
    __cil_tmp22 = (int )__cil_tmp21;
#line 648
    __cil_tmp23 = __cil_tmp22 + -1;
#line 648
    __cil_tmp24 = __cil_tmp23 << 12;
#line 648
    __cil_tmp25 = __cil_tmp24 / __cil_tmp20;
#line 648
    xscale = (u32 )__cil_tmp25;
  } else {
#line 651
    xscale = 4096U;
  }
  }
  {
#line 653
  __cil_tmp26 = params->dst_h;
#line 653
  __cil_tmp27 = (int )__cil_tmp26;
#line 653
  if (__cil_tmp27 > 1) {
#line 654
    __cil_tmp28 = params->dst_h;
#line 654
    __cil_tmp29 = (int )__cil_tmp28;
#line 654
    __cil_tmp30 = params->src_scan_h;
#line 654
    __cil_tmp31 = (int )__cil_tmp30;
#line 654
    __cil_tmp32 = __cil_tmp31 + -1;
#line 654
    __cil_tmp33 = __cil_tmp32 << 12;
#line 654
    __cil_tmp34 = __cil_tmp33 / __cil_tmp29;
#line 654
    yscale = (u32 )__cil_tmp34;
  } else {
#line 657
    yscale = 4096U;
  }
  }
#line 660
  __cil_tmp35 = (u32 )uv_hscale;
#line 660
  xscale_UV = xscale / __cil_tmp35;
#line 661
  __cil_tmp36 = (u32 )uv_vscale;
#line 661
  yscale_UV = yscale / __cil_tmp36;
#line 663
  __cil_tmp37 = (u32 )uv_hscale;
#line 663
  xscale = xscale_UV * __cil_tmp37;
#line 664
  __cil_tmp38 = (u32 )uv_vscale;
#line 664
  yscale = yscale_UV * __cil_tmp38;
  {
#line 670
  __cil_tmp39 = overlay->old_xscale;
#line 670
  if (__cil_tmp39 != xscale) {
#line 671
    scale_changed = (bool )1;
  } else {
    {
#line 670
    __cil_tmp40 = overlay->old_yscale;
#line 670
    if (__cil_tmp40 != yscale) {
#line 671
      scale_changed = (bool )1;
    } else {

    }
    }
  }
  }
#line 672
  overlay->old_xscale = xscale;
#line 673
  overlay->old_yscale = yscale;
#line 675
  __cil_tmp41 = xscale & 4095U;
#line 675
  __cil_tmp42 = __cil_tmp41 << 3;
#line 675
  __cil_tmp43 = xscale >> 12;
#line 675
  __cil_tmp44 = __cil_tmp43 << 16;
#line 675
  __cil_tmp45 = yscale << 20;
#line 675
  __cil_tmp46 = __cil_tmp45 | __cil_tmp44;
#line 675
  regs->YRGBSCALE = __cil_tmp46 | __cil_tmp42;
#line 679
  __cil_tmp47 = xscale_UV & 4095U;
#line 679
  __cil_tmp48 = __cil_tmp47 << 3;
#line 679
  __cil_tmp49 = xscale_UV >> 12;
#line 679
  __cil_tmp50 = __cil_tmp49 << 16;
#line 679
  __cil_tmp51 = yscale_UV << 20;
#line 679
  __cil_tmp52 = __cil_tmp51 | __cil_tmp50;
#line 679
  regs->UVSCALE = __cil_tmp52 | __cil_tmp48;
#line 683
  __cil_tmp53 = yscale_UV >> 12;
#line 683
  __cil_tmp54 = yscale >> 12;
#line 683
  __cil_tmp55 = __cil_tmp54 << 16;
#line 683
  regs->UVSCALEV = __cil_tmp55 | __cil_tmp53;
#line 686
  if ((int )scale_changed) {
    {
#line 687
    update_polyphase_filter(regs);
    }
  } else {

  }
#line 689
  return (scale_changed);
}
}
#line 692 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void update_colorkey(struct intel_overlay *overlay , struct overlay_registers *regs ) 
{ u32 key ;
  struct intel_crtc *__cil_tmp4 ;
  struct drm_framebuffer *__cil_tmp5 ;
  int __cil_tmp6 ;
  struct intel_crtc *__cil_tmp7 ;
  struct drm_framebuffer *__cil_tmp8 ;
  int __cil_tmp9 ;
  struct intel_crtc *__cil_tmp10 ;
  struct drm_framebuffer *__cil_tmp11 ;
  int __cil_tmp12 ;
  struct intel_crtc *__cil_tmp13 ;
  struct drm_framebuffer *__cil_tmp14 ;
  int __cil_tmp15 ;
  struct intel_crtc *__cil_tmp16 ;
  struct drm_framebuffer *__cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  u32 __cil_tmp19 ;
  unsigned int __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  u32 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  unsigned int __cil_tmp31 ;
  unsigned int __cil_tmp32 ;

  {
#line 695
  key = overlay->color_key;
  {
#line 698
  __cil_tmp4 = overlay->crtc;
#line 698
  __cil_tmp5 = __cil_tmp4->base.fb;
#line 698
  __cil_tmp6 = __cil_tmp5->bits_per_pixel;
#line 698
  if (__cil_tmp6 == 8) {
#line 698
    goto case_8;
  } else {
    {
#line 703
    __cil_tmp7 = overlay->crtc;
#line 703
    __cil_tmp8 = __cil_tmp7->base.fb;
#line 703
    __cil_tmp9 = __cil_tmp8->bits_per_pixel;
#line 703
    if (__cil_tmp9 == 16) {
#line 703
      goto case_16;
    } else {
      {
#line 713
      __cil_tmp10 = overlay->crtc;
#line 713
      __cil_tmp11 = __cil_tmp10->base.fb;
#line 713
      __cil_tmp12 = __cil_tmp11->bits_per_pixel;
#line 713
      if (__cil_tmp12 == 24) {
#line 713
        goto case_24;
      } else {
        {
#line 714
        __cil_tmp13 = overlay->crtc;
#line 714
        __cil_tmp14 = __cil_tmp13->base.fb;
#line 714
        __cil_tmp15 = __cil_tmp14->bits_per_pixel;
#line 714
        if (__cil_tmp15 == 32) {
#line 714
          goto case_32;
        } else
#line 697
        if (0) {
          case_8: 
#line 699
          regs->DCLRKV = 0U;
#line 700
          regs->DCLRKM = 2164260863U;
#line 701
          goto ldv_37787;
          case_16: ;
          {
#line 704
          __cil_tmp16 = overlay->crtc;
#line 704
          __cil_tmp17 = __cil_tmp16->base.fb;
#line 704
          __cil_tmp18 = __cil_tmp17->depth;
#line 704
          if (__cil_tmp18 == 15U) {
#line 705
            __cil_tmp19 = key << 3;
#line 705
            __cil_tmp20 = __cil_tmp19 & 255U;
#line 705
            __cil_tmp21 = key & 992U;
#line 705
            __cil_tmp22 = __cil_tmp21 << 6;
#line 705
            __cil_tmp23 = key & 31744U;
#line 705
            __cil_tmp24 = __cil_tmp23 << 9;
#line 705
            __cil_tmp25 = __cil_tmp24 | __cil_tmp22;
#line 705
            regs->DCLRKV = __cil_tmp25 | __cil_tmp20;
#line 706
            regs->DCLRKM = 2147944199U;
          } else {
#line 708
            __cil_tmp26 = key << 3;
#line 708
            __cil_tmp27 = __cil_tmp26 & 255U;
#line 708
            __cil_tmp28 = key & 2016U;
#line 708
            __cil_tmp29 = __cil_tmp28 << 5;
#line 708
            __cil_tmp30 = key & 63488U;
#line 708
            __cil_tmp31 = __cil_tmp30 << 8;
#line 708
            __cil_tmp32 = __cil_tmp31 | __cil_tmp29;
#line 708
            regs->DCLRKV = __cil_tmp32 | __cil_tmp27;
#line 709
            regs->DCLRKM = 2147943175U;
          }
          }
#line 711
          goto ldv_37787;
          case_24: ;
          case_32: 
#line 715
          regs->DCLRKV = key;
#line 716
          regs->DCLRKM = 2147483648U;
#line 717
          goto ldv_37787;
        } else {

        }
        }
      }
      }
    }
    }
  }
  }
  ldv_37787: ;
#line 720
  return;
}
}
#line 721 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static u32 overlay_cmd_reg(struct put_image_params *params ) 
{ u32 cmd ;
  int __cil_tmp3 ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;

  {
#line 723
  cmd = 1U;
  {
#line 725
  __cil_tmp3 = params->format;
#line 725
  if (__cil_tmp3 & 1) {
    {
#line 727
    __cil_tmp4 = params->format;
#line 727
    __cil_tmp5 = __cil_tmp4 & 65280;
#line 727
    if (__cil_tmp5 == 256) {
#line 727
      goto case_256;
    } else {
      {
#line 730
      __cil_tmp6 = params->format;
#line 730
      __cil_tmp7 = __cil_tmp6 & 65280;
#line 730
      if (__cil_tmp7 == 768) {
#line 730
        goto case_768;
      } else {
        {
#line 733
        __cil_tmp8 = params->format;
#line 733
        __cil_tmp9 = __cil_tmp8 & 65280;
#line 733
        if (__cil_tmp9 == 512) {
#line 733
          goto case_512;
        } else {
          {
#line 734
          __cil_tmp10 = params->format;
#line 734
          __cil_tmp11 = __cil_tmp10 & 65280;
#line 734
          if (__cil_tmp11 == 1024) {
#line 734
            goto case_1024;
          } else
#line 726
          if (0) {
            case_256: 
#line 728
            cmd = cmd | 13312U;
#line 729
            goto ldv_37796;
            case_768: 
#line 731
            cmd = cmd | 12288U;
#line 732
            goto ldv_37796;
            case_512: ;
            case_1024: 
#line 735
            cmd = cmd | 14336U;
#line 736
            goto ldv_37796;
          } else {

          }
          }
        }
        }
      }
      }
    }
    }
    ldv_37796: ;
  } else {
    {
#line 740
    __cil_tmp12 = params->format;
#line 740
    __cil_tmp13 = __cil_tmp12 & 65280;
#line 740
    if (__cil_tmp13 == 256) {
#line 740
      goto case_256___0;
    } else {
      {
#line 743
      __cil_tmp14 = params->format;
#line 743
      __cil_tmp15 = __cil_tmp14 & 65280;
#line 743
      if (__cil_tmp15 == 512) {
#line 743
        goto case_512___0;
      } else
#line 739
      if (0) {
        case_256___0: 
#line 741
        cmd = cmd | 8192U;
#line 742
        goto ldv_37801;
        case_512___0: 
#line 744
        cmd = cmd | 9216U;
#line 745
        goto ldv_37801;
      } else {

      }
      }
    }
    }
    ldv_37801: ;
    {
#line 749
    __cil_tmp16 = params->format;
#line 749
    __cil_tmp17 = __cil_tmp16 & 16711680;
#line 749
    if (__cil_tmp17 == 0) {
#line 749
      goto case_0;
    } else {
      {
#line 751
      __cil_tmp18 = params->format;
#line 751
      __cil_tmp19 = __cil_tmp18 & 16711680;
#line 751
      if (__cil_tmp19 == 65536) {
#line 751
        goto case_65536;
      } else {
        {
#line 754
        __cil_tmp20 = params->format;
#line 754
        __cil_tmp21 = __cil_tmp20 & 16711680;
#line 754
        if (__cil_tmp21 == 131072) {
#line 754
          goto case_131072;
        } else {
          {
#line 757
          __cil_tmp22 = params->format;
#line 757
          __cil_tmp23 = __cil_tmp22 & 16711680;
#line 757
          if (__cil_tmp23 == 196608) {
#line 757
            goto case_196608;
          } else
#line 748
          if (0) {
            case_0: ;
#line 750
            goto ldv_37804;
            case_65536: 
#line 752
            cmd = cmd | 16384U;
#line 753
            goto ldv_37804;
            case_131072: 
#line 755
            cmd = cmd | 32768U;
#line 756
            goto ldv_37804;
            case_196608: 
#line 758
            cmd = cmd | 49152U;
#line 759
            goto ldv_37804;
          } else {

          }
          }
        }
        }
      }
      }
    }
    }
    ldv_37804: ;
  }
  }
#line 763
  return (cmd);
}
}
#line 766 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_overlay_do_put_image(struct intel_overlay *overlay , struct drm_i915_gem_object *new_bo ,
                                      struct put_image_params *params ) 
{ int ret ;
  int tmp_width ;
  struct overlay_registers *regs ;
  bool scale_changed ;
  struct drm_device *dev ;
  int tmp ;
  long tmp___0 ;
  int tmp___1 ;
  long tmp___2 ;
  long tmp___3 ;
  unsigned int tmp___4 ;
  int uv_hscale ;
  int tmp___5 ;
  int uv_vscale ;
  int tmp___6 ;
  u32 tmp_U ;
  u32 tmp_V ;
  u32 __max1 ;
  u32 __max2 ;
  u32 tmp___7 ;
  struct mutex *__cil_tmp24 ;
  int __cil_tmp25 ;
  long __cil_tmp26 ;
  struct mutex *__cil_tmp27 ;
  int __cil_tmp28 ;
  long __cil_tmp29 ;
  struct intel_overlay *__cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  int __cil_tmp33 ;
  long __cil_tmp34 ;
  bool __cil_tmp35 ;
  bool __cil_tmp36 ;
  int __cil_tmp37 ;
  struct overlay_registers *__cil_tmp38 ;
  unsigned long __cil_tmp39 ;
  unsigned long __cil_tmp40 ;
  struct drm_device *__cil_tmp41 ;
  void *__cil_tmp42 ;
  struct drm_i915_private *__cil_tmp43 ;
  struct intel_device_info  const  *__cil_tmp44 ;
  u8 __cil_tmp45 ;
  unsigned char __cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  u32 __cil_tmp48 ;
  struct intel_crtc *__cil_tmp49 ;
  enum pipe __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  u32 __cil_tmp52 ;
  struct overlay_registers *__cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  unsigned long __cil_tmp55 ;
  short __cil_tmp56 ;
  int __cil_tmp57 ;
  short __cil_tmp58 ;
  int __cil_tmp59 ;
  int __cil_tmp60 ;
  int __cil_tmp61 ;
  short __cil_tmp62 ;
  int __cil_tmp63 ;
  short __cil_tmp64 ;
  int __cil_tmp65 ;
  int __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  int __cil_tmp70 ;
  u32 __cil_tmp71 ;
  short __cil_tmp72 ;
  int __cil_tmp73 ;
  short __cil_tmp74 ;
  short __cil_tmp75 ;
  short __cil_tmp76 ;
  struct drm_device *__cil_tmp77 ;
  int __cil_tmp78 ;
  u32 __cil_tmp79 ;
  u32 __cil_tmp80 ;
  short __cil_tmp81 ;
  int __cil_tmp82 ;
  uint32_t __cil_tmp83 ;
  uint32_t __cil_tmp84 ;
  short __cil_tmp85 ;
  int __cil_tmp86 ;
  int __cil_tmp87 ;
  u32 __cil_tmp88 ;
  int __cil_tmp89 ;
  u32 __cil_tmp90 ;
  short __cil_tmp91 ;
  int __cil_tmp92 ;
  int __cil_tmp93 ;
  int __cil_tmp94 ;
  u32 __cil_tmp95 ;
  u32 __cil_tmp96 ;
  struct drm_device *__cil_tmp97 ;
  int __cil_tmp98 ;
  u32 __cil_tmp99 ;
  short __cil_tmp100 ;
  int __cil_tmp101 ;
  int __cil_tmp102 ;
  u32 __cil_tmp103 ;
  struct drm_device *__cil_tmp104 ;
  int __cil_tmp105 ;
  u32 __cil_tmp106 ;
  short __cil_tmp107 ;
  int __cil_tmp108 ;
  int __cil_tmp109 ;
  u32 __cil_tmp110 ;
  u32 __cil_tmp111 ;
  u32 __cil_tmp112 ;
  short __cil_tmp113 ;
  int __cil_tmp114 ;
  int __cil_tmp115 ;
  int __cil_tmp116 ;
  u32 __cil_tmp117 ;
  u32 __cil_tmp118 ;
  int __cil_tmp119 ;
  uint32_t __cil_tmp120 ;
  uint32_t __cil_tmp121 ;
  int __cil_tmp122 ;
  uint32_t __cil_tmp123 ;
  uint32_t __cil_tmp124 ;
  short __cil_tmp125 ;
  int __cil_tmp126 ;
  int __cil_tmp127 ;
  u32 __cil_tmp128 ;
  u32 __cil_tmp129 ;
  int __cil_tmp130 ;
  bool __cil_tmp131 ;

  {
  {
#line 772
  scale_changed = (bool )0;
#line 773
  dev = overlay->dev;
#line 775
  __cil_tmp24 = & dev->struct_mutex;
#line 775
  tmp = mutex_is_locked(__cil_tmp24);
#line 775
  __cil_tmp25 = tmp == 0;
#line 775
  __cil_tmp26 = (long )__cil_tmp25;
#line 775
  tmp___0 = __builtin_expect(__cil_tmp26, 0L);
  }
#line 775
  if (tmp___0 != 0L) {
#line 775
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (775), "i" (12UL));
    ldv_37818: ;
#line 775
    goto ldv_37818;
  } else {

  }
  {
#line 776
  __cil_tmp27 = & dev->mode_config.mutex;
#line 776
  tmp___1 = mutex_is_locked(__cil_tmp27);
#line 776
  __cil_tmp28 = tmp___1 == 0;
#line 776
  __cil_tmp29 = (long )__cil_tmp28;
#line 776
  tmp___2 = __builtin_expect(__cil_tmp29, 0L);
  }
#line 776
  if (tmp___2 != 0L) {
#line 776
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (776), "i" (12UL));
    ldv_37819: ;
#line 776
    goto ldv_37819;
  } else {

  }
  {
#line 777
  __cil_tmp30 = (struct intel_overlay *)0;
#line 777
  __cil_tmp31 = (unsigned long )__cil_tmp30;
#line 777
  __cil_tmp32 = (unsigned long )overlay;
#line 777
  __cil_tmp33 = __cil_tmp32 == __cil_tmp31;
#line 777
  __cil_tmp34 = (long )__cil_tmp33;
#line 777
  tmp___3 = __builtin_expect(__cil_tmp34, 0L);
  }
#line 777
  if (tmp___3 != 0L) {
#line 777
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (777), "i" (12UL));
    ldv_37820: ;
#line 777
    goto ldv_37820;
  } else {

  }
  {
#line 779
  ret = intel_overlay_release_old_vid(overlay);
  }
#line 780
  if (ret != 0) {
#line 781
    return (ret);
  } else {

  }
  {
#line 783
  __cil_tmp35 = (bool )1;
#line 783
  ret = i915_gem_object_pin(new_bo, 4096U, __cil_tmp35);
  }
#line 784
  if (ret != 0) {
#line 785
    return (ret);
  } else {

  }
  {
#line 787
  __cil_tmp36 = (bool )0;
#line 787
  ret = i915_gem_object_set_to_gtt_domain(new_bo, __cil_tmp36);
  }
#line 788
  if (ret != 0) {
#line 789
    goto out_unpin;
  } else {

  }
  {
#line 791
  ret = i915_gem_object_put_fence(new_bo);
  }
#line 792
  if (ret != 0) {
#line 793
    goto out_unpin;
  } else {

  }
  {
#line 795
  __cil_tmp37 = overlay->active;
#line 795
  if (__cil_tmp37 == 0) {
    {
#line 796
    regs = intel_overlay_map_regs(overlay);
    }
    {
#line 797
    __cil_tmp38 = (struct overlay_registers *)0;
#line 797
    __cil_tmp39 = (unsigned long )__cil_tmp38;
#line 797
    __cil_tmp40 = (unsigned long )regs;
#line 797
    if (__cil_tmp40 == __cil_tmp39) {
#line 798
      ret = -12;
#line 799
      goto out_unpin;
    } else {

    }
    }
#line 801
    regs->OCONFIG = 8U;
    {
#line 802
    __cil_tmp41 = overlay->dev;
#line 802
    __cil_tmp42 = __cil_tmp41->dev_private;
#line 802
    __cil_tmp43 = (struct drm_i915_private *)__cil_tmp42;
#line 802
    __cil_tmp44 = __cil_tmp43->info;
#line 802
    __cil_tmp45 = __cil_tmp44->gen;
#line 802
    __cil_tmp46 = (unsigned char )__cil_tmp45;
#line 802
    __cil_tmp47 = (unsigned int )__cil_tmp46;
#line 802
    if (__cil_tmp47 == 4U) {
#line 803
      __cil_tmp48 = regs->OCONFIG;
#line 803
      regs->OCONFIG = __cil_tmp48 | 32U;
    } else {

    }
    }
    {
#line 804
    __cil_tmp49 = overlay->crtc;
#line 804
    __cil_tmp50 = __cil_tmp49->pipe;
#line 804
    __cil_tmp51 = (unsigned int )__cil_tmp50;
#line 804
    if (__cil_tmp51 == 0U) {
#line 804
      tmp___4 = 0U;
    } else {
#line 804
      tmp___4 = 262144U;
    }
    }
    {
#line 804
    __cil_tmp52 = regs->OCONFIG;
#line 804
    regs->OCONFIG = __cil_tmp52 | tmp___4;
#line 806
    intel_overlay_unmap_regs(overlay, regs);
#line 808
    ret = intel_overlay_on(overlay);
    }
#line 809
    if (ret != 0) {
#line 810
      goto out_unpin;
    } else {

    }
  } else {

  }
  }
  {
#line 813
  regs = intel_overlay_map_regs(overlay);
  }
  {
#line 814
  __cil_tmp53 = (struct overlay_registers *)0;
#line 814
  __cil_tmp54 = (unsigned long )__cil_tmp53;
#line 814
  __cil_tmp55 = (unsigned long )regs;
#line 814
  if (__cil_tmp55 == __cil_tmp54) {
#line 815
    ret = -12;
#line 816
    goto out_unpin;
  } else {

  }
  }
#line 819
  __cil_tmp56 = params->dst_x;
#line 819
  __cil_tmp57 = (int )__cil_tmp56;
#line 819
  __cil_tmp58 = params->dst_y;
#line 819
  __cil_tmp59 = (int )__cil_tmp58;
#line 819
  __cil_tmp60 = __cil_tmp59 << 16;
#line 819
  __cil_tmp61 = __cil_tmp60 | __cil_tmp57;
#line 819
  regs->DWINPOS = (u32 )__cil_tmp61;
#line 820
  __cil_tmp62 = params->dst_w;
#line 820
  __cil_tmp63 = (int )__cil_tmp62;
#line 820
  __cil_tmp64 = params->dst_h;
#line 820
  __cil_tmp65 = (int )__cil_tmp64;
#line 820
  __cil_tmp66 = __cil_tmp65 << 16;
#line 820
  __cil_tmp67 = __cil_tmp66 | __cil_tmp63;
#line 820
  regs->DWINSZ = (u32 )__cil_tmp67;
  {
#line 822
  __cil_tmp68 = params->format;
#line 822
  __cil_tmp69 = __cil_tmp68 & 2;
#line 822
  if (__cil_tmp69 != 0) {
    {
#line 823
    __cil_tmp70 = params->format;
#line 823
    __cil_tmp71 = (u32 )__cil_tmp70;
#line 823
    __cil_tmp72 = params->src_w;
#line 823
    __cil_tmp73 = (int )__cil_tmp72;
#line 823
    __cil_tmp74 = (short )__cil_tmp73;
#line 823
    tmp_width = packed_width_bytes(__cil_tmp71, __cil_tmp74);
    }
  } else {
#line 825
    __cil_tmp75 = params->src_w;
#line 825
    tmp_width = (int )__cil_tmp75;
  }
  }
  {
#line 827
  __cil_tmp76 = params->src_w;
#line 827
  regs->SWIDTH = (u32 )__cil_tmp76;
#line 828
  __cil_tmp77 = overlay->dev;
#line 828
  __cil_tmp78 = params->offset_Y;
#line 828
  __cil_tmp79 = (u32 )__cil_tmp78;
#line 828
  __cil_tmp80 = (u32 )tmp_width;
#line 828
  regs->SWIDTHSW = calc_swidthsw(__cil_tmp77, __cil_tmp79, __cil_tmp80);
#line 830
  __cil_tmp81 = params->src_h;
#line 830
  regs->SHEIGHT = (u32 )__cil_tmp81;
#line 831
  __cil_tmp82 = params->offset_Y;
#line 831
  __cil_tmp83 = (uint32_t )__cil_tmp82;
#line 831
  __cil_tmp84 = new_bo->gtt_offset;
#line 831
  regs->OBUF_0Y = __cil_tmp84 + __cil_tmp83;
#line 832
  __cil_tmp85 = params->stride_Y;
#line 832
  regs->OSTRIDE = (u32 )__cil_tmp85;
  }
  {
#line 834
  __cil_tmp86 = params->format;
#line 834
  if (__cil_tmp86 & 1) {
    {
#line 835
    __cil_tmp87 = params->format;
#line 835
    __cil_tmp88 = (u32 )__cil_tmp87;
#line 835
    tmp___5 = uv_hsubsampling(__cil_tmp88);
#line 835
    uv_hscale = tmp___5;
#line 836
    __cil_tmp89 = params->format;
#line 836
    __cil_tmp90 = (u32 )__cil_tmp89;
#line 836
    tmp___6 = uv_vsubsampling(__cil_tmp90);
#line 836
    uv_vscale = tmp___6;
#line 838
    __cil_tmp91 = params->src_w;
#line 838
    __cil_tmp92 = (int )__cil_tmp91;
#line 838
    __cil_tmp93 = __cil_tmp92 / uv_hscale;
#line 838
    __cil_tmp94 = __cil_tmp93 << 16;
#line 838
    __cil_tmp95 = (u32 )__cil_tmp94;
#line 838
    __cil_tmp96 = regs->SWIDTH;
#line 838
    regs->SWIDTH = __cil_tmp96 | __cil_tmp95;
#line 839
    __cil_tmp97 = overlay->dev;
#line 839
    __cil_tmp98 = params->offset_U;
#line 839
    __cil_tmp99 = (u32 )__cil_tmp98;
#line 839
    __cil_tmp100 = params->src_w;
#line 839
    __cil_tmp101 = (int )__cil_tmp100;
#line 839
    __cil_tmp102 = __cil_tmp101 / uv_hscale;
#line 839
    __cil_tmp103 = (u32 )__cil_tmp102;
#line 839
    tmp_U = calc_swidthsw(__cil_tmp97, __cil_tmp99, __cil_tmp103);
#line 841
    __cil_tmp104 = overlay->dev;
#line 841
    __cil_tmp105 = params->offset_V;
#line 841
    __cil_tmp106 = (u32 )__cil_tmp105;
#line 841
    __cil_tmp107 = params->src_w;
#line 841
    __cil_tmp108 = (int )__cil_tmp107;
#line 841
    __cil_tmp109 = __cil_tmp108 / uv_hscale;
#line 841
    __cil_tmp110 = (u32 )__cil_tmp109;
#line 841
    tmp_V = calc_swidthsw(__cil_tmp104, __cil_tmp106, __cil_tmp110);
#line 843
    __max1 = tmp_U;
#line 843
    __max2 = tmp_V;
    }
#line 843
    if (__max1 > __max2) {
#line 843
      tmp___7 = __max1;
    } else {
#line 843
      tmp___7 = __max2;
    }
#line 843
    __cil_tmp111 = tmp___7 << 16;
#line 843
    __cil_tmp112 = regs->SWIDTHSW;
#line 843
    regs->SWIDTHSW = __cil_tmp112 | __cil_tmp111;
#line 844
    __cil_tmp113 = params->src_h;
#line 844
    __cil_tmp114 = (int )__cil_tmp113;
#line 844
    __cil_tmp115 = __cil_tmp114 / uv_vscale;
#line 844
    __cil_tmp116 = __cil_tmp115 << 16;
#line 844
    __cil_tmp117 = (u32 )__cil_tmp116;
#line 844
    __cil_tmp118 = regs->SHEIGHT;
#line 844
    regs->SHEIGHT = __cil_tmp118 | __cil_tmp117;
#line 845
    __cil_tmp119 = params->offset_U;
#line 845
    __cil_tmp120 = (uint32_t )__cil_tmp119;
#line 845
    __cil_tmp121 = new_bo->gtt_offset;
#line 845
    regs->OBUF_0U = __cil_tmp121 + __cil_tmp120;
#line 846
    __cil_tmp122 = params->offset_V;
#line 846
    __cil_tmp123 = (uint32_t )__cil_tmp122;
#line 846
    __cil_tmp124 = new_bo->gtt_offset;
#line 846
    regs->OBUF_0V = __cil_tmp124 + __cil_tmp123;
#line 847
    __cil_tmp125 = params->stride_UV;
#line 847
    __cil_tmp126 = (int )__cil_tmp125;
#line 847
    __cil_tmp127 = __cil_tmp126 << 16;
#line 847
    __cil_tmp128 = (u32 )__cil_tmp127;
#line 847
    __cil_tmp129 = regs->OSTRIDE;
#line 847
    regs->OSTRIDE = __cil_tmp129 | __cil_tmp128;
  } else {

  }
  }
  {
#line 850
  scale_changed = update_scaling_factors(overlay, regs, params);
#line 852
  update_colorkey(overlay, regs);
#line 854
  regs->OCMD = overlay_cmd_reg(params);
#line 856
  intel_overlay_unmap_regs(overlay, regs);
#line 858
  __cil_tmp130 = (int )scale_changed;
#line 858
  __cil_tmp131 = (bool )__cil_tmp130;
#line 858
  ret = intel_overlay_continue(overlay, __cil_tmp131);
  }
#line 859
  if (ret != 0) {
#line 860
    goto out_unpin;
  } else {

  }
#line 862
  overlay->old_vid_bo = overlay->vid_bo;
#line 863
  overlay->vid_bo = new_bo;
#line 865
  return (0);
  out_unpin: 
  {
#line 868
  i915_gem_object_unpin(new_bo);
  }
#line 869
  return (ret);
}
}
#line 872 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
int intel_overlay_switch_off(struct intel_overlay *overlay ) 
{ struct overlay_registers *regs ;
  struct drm_device *dev ;
  int ret ;
  int tmp ;
  long tmp___0 ;
  int tmp___1 ;
  long tmp___2 ;
  struct mutex *__cil_tmp9 ;
  int __cil_tmp10 ;
  long __cil_tmp11 ;
  struct mutex *__cil_tmp12 ;
  int __cil_tmp13 ;
  long __cil_tmp14 ;
  int __cil_tmp15 ;

  {
  {
#line 875
  dev = overlay->dev;
#line 878
  __cil_tmp9 = & dev->struct_mutex;
#line 878
  tmp = mutex_is_locked(__cil_tmp9);
#line 878
  __cil_tmp10 = tmp == 0;
#line 878
  __cil_tmp11 = (long )__cil_tmp10;
#line 878
  tmp___0 = __builtin_expect(__cil_tmp11, 0L);
  }
#line 878
  if (tmp___0 != 0L) {
#line 878
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (878), "i" (12UL));
    ldv_37835: ;
#line 878
    goto ldv_37835;
  } else {

  }
  {
#line 879
  __cil_tmp12 = & dev->mode_config.mutex;
#line 879
  tmp___1 = mutex_is_locked(__cil_tmp12);
#line 879
  __cil_tmp13 = tmp___1 == 0;
#line 879
  __cil_tmp14 = (long )__cil_tmp13;
#line 879
  tmp___2 = __builtin_expect(__cil_tmp14, 0L);
  }
#line 879
  if (tmp___2 != 0L) {
#line 879
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (879), "i" (12UL));
    ldv_37836: ;
#line 879
    goto ldv_37836;
  } else {

  }
  {
#line 881
  ret = intel_overlay_recover_from_interrupt(overlay);
  }
#line 882
  if (ret != 0) {
#line 883
    return (ret);
  } else {

  }
  {
#line 885
  __cil_tmp15 = overlay->active;
#line 885
  if (__cil_tmp15 == 0) {
#line 886
    return (0);
  } else {

  }
  }
  {
#line 888
  ret = intel_overlay_release_old_vid(overlay);
  }
#line 889
  if (ret != 0) {
#line 890
    return (ret);
  } else {

  }
  {
#line 892
  regs = intel_overlay_map_regs(overlay);
#line 893
  regs->OCMD = 0U;
#line 894
  intel_overlay_unmap_regs(overlay, regs);
#line 896
  ret = intel_overlay_off(overlay);
  }
#line 897
  if (ret != 0) {
#line 898
    return (ret);
  } else {

  }
  {
#line 900
  intel_overlay_off_tail(overlay);
  }
#line 901
  return (0);
}
}
#line 904 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int check_overlay_possible_on_crtc(struct intel_overlay *overlay , struct intel_crtc *crtc ) 
{ drm_i915_private_t *dev_priv ;
  u32 tmp ;
  struct drm_device *__cil_tmp5 ;
  void *__cil_tmp6 ;
  bool __cil_tmp7 ;
  struct drm_device *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  enum pipe __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  unsigned int __cil_tmp19 ;

  {
#line 907
  __cil_tmp5 = overlay->dev;
#line 907
  __cil_tmp6 = __cil_tmp5->dev_private;
#line 907
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
  {
#line 909
  __cil_tmp7 = crtc->active;
#line 909
  if (! __cil_tmp7) {
#line 910
    return (-22);
  } else {

  }
  }
  {
#line 913
  __cil_tmp8 = overlay->dev;
#line 913
  __cil_tmp9 = __cil_tmp8->dev_private;
#line 913
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 913
  __cil_tmp11 = __cil_tmp10->info;
#line 913
  __cil_tmp12 = __cil_tmp11->gen;
#line 913
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 913
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 913
  if (__cil_tmp14 <= 3U) {
    {
#line 913
    __cil_tmp15 = crtc->pipe;
#line 913
    __cil_tmp16 = (unsigned int )__cil_tmp15;
#line 913
    __cil_tmp17 = __cil_tmp16 * 4096U;
#line 913
    __cil_tmp18 = __cil_tmp17 + 458760U;
#line 913
    tmp = i915_read32(dev_priv, __cil_tmp18);
    }
    {
#line 913
    __cil_tmp19 = tmp & 3221225472U;
#line 913
    if (__cil_tmp19 != 2147483648U) {
#line 915
      return (-22);
    } else {

    }
    }
  } else {

  }
  }
#line 917
  return (0);
}
}
#line 920 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void update_pfit_vscale_ratio(struct intel_overlay *overlay ) 
{ struct drm_device *dev ;
  drm_i915_private_t *dev_priv ;
  u32 pfit_control ;
  u32 tmp ;
  u32 ratio ;
  u32 tmp___0 ;
  void *__cil_tmp8 ;
  void *__cil_tmp9 ;
  struct drm_i915_private *__cil_tmp10 ;
  struct intel_device_info  const  *__cil_tmp11 ;
  u8 __cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;

  {
  {
#line 922
  dev = overlay->dev;
#line 923
  __cil_tmp8 = dev->dev_private;
#line 923
  dev_priv = (drm_i915_private_t *)__cil_tmp8;
#line 924
  tmp = i915_read32(dev_priv, 397872U);
#line 924
  pfit_control = tmp;
  }
  {
#line 930
  __cil_tmp9 = dev->dev_private;
#line 930
  __cil_tmp10 = (struct drm_i915_private *)__cil_tmp9;
#line 930
  __cil_tmp11 = __cil_tmp10->info;
#line 930
  __cil_tmp12 = __cil_tmp11->gen;
#line 930
  __cil_tmp13 = (unsigned char )__cil_tmp12;
#line 930
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 930
  if (__cil_tmp14 > 3U) {
    {
#line 932
    tmp___0 = i915_read32(dev_priv, 397876U);
#line 932
    ratio = tmp___0 >> 16;
    }
  } else {
    {
#line 934
    __cil_tmp15 = pfit_control & 512U;
#line 934
    if (__cil_tmp15 != 0U) {
      {
#line 935
      ratio = i915_read32(dev_priv, 397880U);
      }
    } else {
      {
#line 937
      ratio = i915_read32(dev_priv, 397876U);
      }
    }
    }
#line 938
    ratio = ratio >> 20;
  }
  }
#line 941
  overlay->pfit_vscale_ratio = ratio;
#line 942
  return;
}
}
#line 944 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int check_overlay_dst(struct intel_overlay *overlay , struct drm_intel_overlay_put_image *rec ) 
{ struct drm_display_mode *mode ;
  struct intel_crtc *__cil_tmp4 ;
  int __cil_tmp5 ;
  __u16 __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  __u16 __cil_tmp9 ;
  int __cil_tmp10 ;
  __u16 __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  __u16 __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  __u16 __cil_tmp18 ;
  int __cil_tmp19 ;
  __u16 __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;

  {
#line 947
  __cil_tmp4 = overlay->crtc;
#line 947
  mode = & __cil_tmp4->base.mode;
  {
#line 949
  __cil_tmp5 = mode->crtc_hdisplay;
#line 949
  __cil_tmp6 = rec->dst_x;
#line 949
  __cil_tmp7 = (int )__cil_tmp6;
#line 949
  if (__cil_tmp7 < __cil_tmp5) {
    {
#line 949
    __cil_tmp8 = mode->crtc_hdisplay;
#line 949
    __cil_tmp9 = rec->dst_width;
#line 949
    __cil_tmp10 = (int )__cil_tmp9;
#line 949
    __cil_tmp11 = rec->dst_x;
#line 949
    __cil_tmp12 = (int )__cil_tmp11;
#line 949
    __cil_tmp13 = __cil_tmp12 + __cil_tmp10;
#line 949
    if (__cil_tmp13 <= __cil_tmp8) {
      {
#line 949
      __cil_tmp14 = mode->crtc_vdisplay;
#line 949
      __cil_tmp15 = rec->dst_y;
#line 949
      __cil_tmp16 = (int )__cil_tmp15;
#line 949
      if (__cil_tmp16 < __cil_tmp14) {
        {
#line 949
        __cil_tmp17 = mode->crtc_vdisplay;
#line 949
        __cil_tmp18 = rec->dst_height;
#line 949
        __cil_tmp19 = (int )__cil_tmp18;
#line 949
        __cil_tmp20 = rec->dst_y;
#line 949
        __cil_tmp21 = (int )__cil_tmp20;
#line 949
        __cil_tmp22 = __cil_tmp21 + __cil_tmp19;
#line 949
        if (__cil_tmp22 <= __cil_tmp17) {
#line 953
          return (0);
        } else {
#line 955
          return (-22);
        }
        }
      } else {
#line 955
        return (-22);
      }
      }
    } else {
#line 955
      return (-22);
    }
    }
  } else {
#line 955
    return (-22);
  }
  }
}
}
#line 958 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int check_overlay_scaling(struct put_image_params *rec ) 
{ u32 tmp ;
  short __cil_tmp3 ;
  int __cil_tmp4 ;
  short __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  short __cil_tmp10 ;
  int __cil_tmp11 ;
  short __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;

  {
#line 963
  __cil_tmp3 = rec->dst_h;
#line 963
  __cil_tmp4 = (int )__cil_tmp3;
#line 963
  __cil_tmp5 = rec->src_scan_h;
#line 963
  __cil_tmp6 = (int )__cil_tmp5;
#line 963
  __cil_tmp7 = __cil_tmp6 << 16;
#line 963
  __cil_tmp8 = __cil_tmp7 / __cil_tmp4;
#line 963
  __cil_tmp9 = __cil_tmp8 >> 16;
#line 963
  tmp = (u32 )__cil_tmp9;
#line 964
  if (tmp > 7U) {
#line 965
    return (-22);
  } else {

  }
#line 966
  __cil_tmp10 = rec->dst_w;
#line 966
  __cil_tmp11 = (int )__cil_tmp10;
#line 966
  __cil_tmp12 = rec->src_scan_w;
#line 966
  __cil_tmp13 = (int )__cil_tmp12;
#line 966
  __cil_tmp14 = __cil_tmp13 << 16;
#line 966
  __cil_tmp15 = __cil_tmp14 / __cil_tmp11;
#line 966
  __cil_tmp16 = __cil_tmp15 >> 16;
#line 966
  tmp = (u32 )__cil_tmp16;
#line 967
  if (tmp > 7U) {
#line 968
    return (-22);
  } else {

  }
#line 970
  return (0);
}
}
#line 973 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int check_overlay_src(struct drm_device *dev , struct drm_intel_overlay_put_image *rec ,
                             struct drm_i915_gem_object *new_bo ) 
{ int uv_hscale ;
  int tmp ;
  int uv_vscale ;
  int tmp___0 ;
  u32 stride_mask ;
  int depth ;
  u32 tmp___1 ;
  int tmp___2 ;
  __u32 __cil_tmp12 ;
  __u32 __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  __u16 __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  __u16 __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  __u16 __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  __u16 __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  __u16 __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  __u16 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  __u32 __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  int __cil_tmp30 ;
  __u32 __cil_tmp31 ;
  unsigned int __cil_tmp32 ;
  int __cil_tmp33 ;
  __u32 __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  int __cil_tmp36 ;
  __u32 __cil_tmp37 ;
  __u32 __cil_tmp38 ;
  __u32 __cil_tmp39 ;
  unsigned int __cil_tmp40 ;
  __u16 __cil_tmp41 ;
  int __cil_tmp42 ;
  int __cil_tmp43 ;
  int __cil_tmp44 ;
  int __cil_tmp45 ;
  __u16 __cil_tmp46 ;
  u32 __cil_tmp47 ;
  unsigned int __cil_tmp48 ;
  __u16 __cil_tmp49 ;
  u32 __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  void *__cil_tmp52 ;
  struct drm_i915_private *__cil_tmp53 ;
  struct intel_device_info  const  *__cil_tmp54 ;
  u8 __cil_tmp55 ;
  unsigned char __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  __u16 __cil_tmp58 ;
  unsigned int __cil_tmp59 ;
  __u32 __cil_tmp60 ;
  unsigned int __cil_tmp61 ;
  __u16 __cil_tmp62 ;
  u32 __cil_tmp63 ;
  __u16 __cil_tmp64 ;
  unsigned int __cil_tmp65 ;
  __u32 __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  int __cil_tmp68 ;
  __u32 __cil_tmp69 ;
  unsigned int __cil_tmp70 ;
  int __cil_tmp71 ;
  __u32 __cil_tmp72 ;
  unsigned int __cil_tmp73 ;
  int __cil_tmp74 ;
  __u32 __cil_tmp75 ;
  __u16 __cil_tmp76 ;
  short __cil_tmp77 ;
  int __cil_tmp78 ;
  short __cil_tmp79 ;
  __u16 __cil_tmp80 ;
  int __cil_tmp81 ;
  __u16 __cil_tmp82 ;
  int __cil_tmp83 ;
  __u16 __cil_tmp84 ;
  int __cil_tmp85 ;
  int __cil_tmp86 ;
  size_t __cil_tmp87 ;
  __u32 __cil_tmp88 ;
  __u32 __cil_tmp89 ;
  size_t __cil_tmp90 ;
  __u16 __cil_tmp91 ;
  int __cil_tmp92 ;
  __u16 __cil_tmp93 ;
  int __cil_tmp94 ;
  __u16 __cil_tmp95 ;
  int __cil_tmp96 ;
  __u16 __cil_tmp97 ;
  int __cil_tmp98 ;
  int __cil_tmp99 ;
  __u16 __cil_tmp100 ;
  int __cil_tmp101 ;
  __u16 __cil_tmp102 ;
  int __cil_tmp103 ;
  int __cil_tmp104 ;
  size_t __cil_tmp105 ;
  __u32 __cil_tmp106 ;
  __u32 __cil_tmp107 ;
  size_t __cil_tmp108 ;
  __u16 __cil_tmp109 ;
  int __cil_tmp110 ;
  int __cil_tmp111 ;
  __u16 __cil_tmp112 ;
  int __cil_tmp113 ;
  int __cil_tmp114 ;
  size_t __cil_tmp115 ;
  __u32 __cil_tmp116 ;
  __u32 __cil_tmp117 ;
  size_t __cil_tmp118 ;
  size_t __cil_tmp119 ;
  __u32 __cil_tmp120 ;
  __u32 __cil_tmp121 ;
  size_t __cil_tmp122 ;

  {
  {
#line 977
  __cil_tmp12 = rec->flags;
#line 977
  tmp = uv_hsubsampling(__cil_tmp12);
#line 977
  uv_hscale = tmp;
#line 978
  __cil_tmp13 = rec->flags;
#line 978
  tmp___0 = uv_vsubsampling(__cil_tmp13);
#line 978
  uv_vscale = tmp___0;
  }
  {
#line 984
  __cil_tmp14 = dev->pci_device;
#line 984
  if (__cil_tmp14 == 9570) {
#line 984
    goto _L;
  } else {
    {
#line 984
    __cil_tmp15 = dev->pci_device;
#line 984
    if (__cil_tmp15 == 13687) {
      _L: 
      {
#line 985
      __cil_tmp16 = rec->src_height;
#line 985
      __cil_tmp17 = (unsigned int )__cil_tmp16;
#line 985
      if (__cil_tmp17 > 1088U) {
#line 987
        return (-22);
      } else {
        {
#line 985
        __cil_tmp18 = rec->src_width;
#line 985
        __cil_tmp19 = (unsigned int )__cil_tmp18;
#line 985
        if (__cil_tmp19 > 1024U) {
#line 987
          return (-22);
        } else {
          {
#line 989
          __cil_tmp20 = rec->src_height;
#line 989
          __cil_tmp21 = (unsigned int )__cil_tmp20;
#line 989
          if (__cil_tmp21 > 2046U) {
#line 991
            return (-22);
          } else {
            {
#line 989
            __cil_tmp22 = rec->src_width;
#line 989
            __cil_tmp23 = (unsigned int )__cil_tmp22;
#line 989
            if (__cil_tmp23 > 2048U) {
#line 991
              return (-22);
            } else {

            }
            }
          }
          }
        }
        }
      }
      }
    } else {

    }
    }
  }
  }
  {
#line 995
  __cil_tmp24 = rec->src_height;
#line 995
  __cil_tmp25 = (unsigned int )__cil_tmp24;
#line 995
  if (__cil_tmp25 <= 11U) {
#line 997
    return (-22);
  } else {
    {
#line 995
    __cil_tmp26 = rec->src_width;
#line 995
    __cil_tmp27 = (unsigned int )__cil_tmp26;
#line 995
    if (__cil_tmp27 <= 19U) {
#line 997
      return (-22);
    } else {

    }
    }
  }
  }
  {
#line 1001
  __cil_tmp28 = rec->flags;
#line 1001
  __cil_tmp29 = __cil_tmp28 & 255U;
#line 1001
  __cil_tmp30 = (int )__cil_tmp29;
#line 1001
  if (__cil_tmp30 == 3) {
#line 1001
    goto case_3;
  } else {
    {
#line 1005
    __cil_tmp31 = rec->flags;
#line 1005
    __cil_tmp32 = __cil_tmp31 & 255U;
#line 1005
    __cil_tmp33 = (int )__cil_tmp32;
#line 1005
    if (__cil_tmp33 == 2) {
#line 1005
      goto case_2;
    } else {
      {
#line 1022
      __cil_tmp34 = rec->flags;
#line 1022
      __cil_tmp35 = __cil_tmp34 & 255U;
#line 1022
      __cil_tmp36 = (int )__cil_tmp35;
#line 1022
      if (__cil_tmp36 == 1) {
#line 1022
        goto case_1;
      } else {
#line 1028
        goto switch_default;
#line 1000
        if (0) {
          case_3: ;
#line 1003
          return (-22);
          case_2: ;
#line 1006
          if (uv_vscale != 1) {
#line 1007
            return (-22);
          } else {

          }
          {
#line 1009
          __cil_tmp37 = rec->flags;
#line 1009
          depth = packed_depth_bytes(__cil_tmp37);
          }
#line 1010
          if (depth < 0) {
#line 1011
            return (depth);
          } else {

          }
#line 1014
          rec->stride_UV = (__u16 )0U;
#line 1015
          rec->offset_U = 0U;
#line 1016
          rec->offset_V = 0U;
          {
#line 1018
          __cil_tmp38 = (__u32 )depth;
#line 1018
          __cil_tmp39 = rec->offset_Y;
#line 1018
          __cil_tmp40 = __cil_tmp39 % __cil_tmp38;
#line 1018
          if (__cil_tmp40 != 0U) {
#line 1019
            return (-22);
          } else {

          }
          }
#line 1020
          goto ldv_37870;
          case_1: ;
#line 1023
          if (uv_vscale < 0) {
#line 1024
            return (-22);
          } else
#line 1023
          if (uv_hscale < 0) {
#line 1024
            return (-22);
          } else {

          }
#line 1026
          goto ldv_37870;
          switch_default: ;
#line 1029
          return (-22);
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_37870: ;
  {
#line 1032
  __cil_tmp41 = rec->src_width;
#line 1032
  __cil_tmp42 = (int )__cil_tmp41;
#line 1032
  __cil_tmp43 = __cil_tmp42 % uv_hscale;
#line 1032
  if (__cil_tmp43 != 0) {
#line 1033
    return (-22);
  } else {

  }
  }
  {
#line 1036
  __cil_tmp44 = dev->pci_device;
#line 1036
  if (__cil_tmp44 == 13687) {
#line 1037
    stride_mask = 255U;
  } else {
    {
#line 1036
    __cil_tmp45 = dev->pci_device;
#line 1036
    if (__cil_tmp45 == 9570) {
#line 1037
      stride_mask = 255U;
    } else {
#line 1039
      stride_mask = 63U;
    }
    }
  }
  }
  {
#line 1041
  __cil_tmp46 = rec->stride_Y;
#line 1041
  __cil_tmp47 = (u32 )__cil_tmp46;
#line 1041
  __cil_tmp48 = __cil_tmp47 & stride_mask;
#line 1041
  if (__cil_tmp48 != 0U) {
#line 1042
    return (-22);
  } else {
    {
#line 1041
    __cil_tmp49 = rec->stride_UV;
#line 1041
    __cil_tmp50 = (u32 )__cil_tmp49;
#line 1041
    __cil_tmp51 = __cil_tmp50 & stride_mask;
#line 1041
    if (__cil_tmp51 != 0U) {
#line 1042
      return (-22);
    } else {

    }
    }
  }
  }
  {
#line 1043
  __cil_tmp52 = dev->dev_private;
#line 1043
  __cil_tmp53 = (struct drm_i915_private *)__cil_tmp52;
#line 1043
  __cil_tmp54 = __cil_tmp53->info;
#line 1043
  __cil_tmp55 = __cil_tmp54->gen;
#line 1043
  __cil_tmp56 = (unsigned char )__cil_tmp55;
#line 1043
  __cil_tmp57 = (unsigned int )__cil_tmp56;
#line 1043
  if (__cil_tmp57 == 4U) {
    {
#line 1043
    __cil_tmp58 = rec->stride_Y;
#line 1043
    __cil_tmp59 = (unsigned int )__cil_tmp58;
#line 1043
    if (__cil_tmp59 <= 511U) {
#line 1044
      return (-22);
    } else {

    }
    }
  } else {

  }
  }
  {
#line 1046
  __cil_tmp60 = rec->flags;
#line 1046
  __cil_tmp61 = __cil_tmp60 & 255U;
#line 1046
  if (__cil_tmp61 == 1U) {
#line 1046
    tmp___1 = 4096U;
  } else {
#line 1046
    tmp___1 = 8192U;
  }
  }
  {
#line 1048
  __cil_tmp62 = rec->stride_Y;
#line 1048
  __cil_tmp63 = (u32 )__cil_tmp62;
#line 1048
  if (__cil_tmp63 > tmp___1) {
#line 1049
    return (-22);
  } else {
    {
#line 1048
    __cil_tmp64 = rec->stride_UV;
#line 1048
    __cil_tmp65 = (unsigned int )__cil_tmp64;
#line 1048
    if (__cil_tmp65 > 2048U) {
#line 1049
      return (-22);
    } else {

    }
    }
  }
  }
  {
#line 1053
  __cil_tmp66 = rec->flags;
#line 1053
  __cil_tmp67 = __cil_tmp66 & 255U;
#line 1053
  __cil_tmp68 = (int )__cil_tmp67;
#line 1053
  if (__cil_tmp68 == 3) {
#line 1053
    goto case_3___0;
  } else {
    {
#line 1054
    __cil_tmp69 = rec->flags;
#line 1054
    __cil_tmp70 = __cil_tmp69 & 255U;
#line 1054
    __cil_tmp71 = (int )__cil_tmp70;
#line 1054
    if (__cil_tmp71 == 2) {
#line 1054
      goto case_2___0;
    } else {
      {
#line 1064
      __cil_tmp72 = rec->flags;
#line 1064
      __cil_tmp73 = __cil_tmp72 & 255U;
#line 1064
      __cil_tmp74 = (int )__cil_tmp73;
#line 1064
      if (__cil_tmp74 == 1) {
#line 1064
        goto case_1___0;
      } else
#line 1052
      if (0) {
        case_3___0: ;
        case_2___0: 
        {
#line 1056
        __cil_tmp75 = rec->flags;
#line 1056
        __cil_tmp76 = rec->src_width;
#line 1056
        __cil_tmp77 = (short )__cil_tmp76;
#line 1056
        __cil_tmp78 = (int )__cil_tmp77;
#line 1056
        __cil_tmp79 = (short )__cil_tmp78;
#line 1056
        tmp___2 = packed_width_bytes(__cil_tmp75, __cil_tmp79);
        }
        {
#line 1056
        __cil_tmp80 = rec->stride_Y;
#line 1056
        __cil_tmp81 = (int )__cil_tmp80;
#line 1056
        if (tmp___2 > __cil_tmp81) {
#line 1057
          return (-22);
        } else {

        }
        }
#line 1059
        __cil_tmp82 = rec->src_height;
#line 1059
        __cil_tmp83 = (int )__cil_tmp82;
#line 1059
        __cil_tmp84 = rec->stride_Y;
#line 1059
        __cil_tmp85 = (int )__cil_tmp84;
#line 1059
        __cil_tmp86 = __cil_tmp85 * __cil_tmp83;
#line 1059
        tmp___1 = (u32 )__cil_tmp86;
        {
#line 1060
        __cil_tmp87 = new_bo->base.size;
#line 1060
        __cil_tmp88 = rec->offset_Y;
#line 1060
        __cil_tmp89 = __cil_tmp88 + tmp___1;
#line 1060
        __cil_tmp90 = (size_t )__cil_tmp89;
#line 1060
        if (__cil_tmp90 > __cil_tmp87) {
#line 1061
          return (-22);
        } else {

        }
        }
#line 1062
        goto ldv_37875;
        case_1___0: ;
        {
#line 1065
        __cil_tmp91 = rec->stride_Y;
#line 1065
        __cil_tmp92 = (int )__cil_tmp91;
#line 1065
        __cil_tmp93 = rec->src_width;
#line 1065
        __cil_tmp94 = (int )__cil_tmp93;
#line 1065
        if (__cil_tmp94 > __cil_tmp92) {
#line 1066
          return (-22);
        } else {

        }
        }
        {
#line 1067
        __cil_tmp95 = rec->stride_UV;
#line 1067
        __cil_tmp96 = (int )__cil_tmp95;
#line 1067
        __cil_tmp97 = rec->src_width;
#line 1067
        __cil_tmp98 = (int )__cil_tmp97;
#line 1067
        __cil_tmp99 = __cil_tmp98 / uv_hscale;
#line 1067
        if (__cil_tmp99 > __cil_tmp96) {
#line 1068
          return (-22);
        } else {

        }
        }
#line 1070
        __cil_tmp100 = rec->src_height;
#line 1070
        __cil_tmp101 = (int )__cil_tmp100;
#line 1070
        __cil_tmp102 = rec->stride_Y;
#line 1070
        __cil_tmp103 = (int )__cil_tmp102;
#line 1070
        __cil_tmp104 = __cil_tmp103 * __cil_tmp101;
#line 1070
        tmp___1 = (u32 )__cil_tmp104;
        {
#line 1071
        __cil_tmp105 = new_bo->base.size;
#line 1071
        __cil_tmp106 = rec->offset_Y;
#line 1071
        __cil_tmp107 = __cil_tmp106 + tmp___1;
#line 1071
        __cil_tmp108 = (size_t )__cil_tmp107;
#line 1071
        if (__cil_tmp108 > __cil_tmp105) {
#line 1072
          return (-22);
        } else {

        }
        }
#line 1074
        __cil_tmp109 = rec->src_height;
#line 1074
        __cil_tmp110 = (int )__cil_tmp109;
#line 1074
        __cil_tmp111 = __cil_tmp110 / uv_vscale;
#line 1074
        __cil_tmp112 = rec->stride_UV;
#line 1074
        __cil_tmp113 = (int )__cil_tmp112;
#line 1074
        __cil_tmp114 = __cil_tmp113 * __cil_tmp111;
#line 1074
        tmp___1 = (u32 )__cil_tmp114;
        {
#line 1075
        __cil_tmp115 = new_bo->base.size;
#line 1075
        __cil_tmp116 = rec->offset_U;
#line 1075
        __cil_tmp117 = __cil_tmp116 + tmp___1;
#line 1075
        __cil_tmp118 = (size_t )__cil_tmp117;
#line 1075
        if (__cil_tmp118 > __cil_tmp115) {
#line 1077
          return (-22);
        } else {
          {
#line 1075
          __cil_tmp119 = new_bo->base.size;
#line 1075
          __cil_tmp120 = rec->offset_V;
#line 1075
          __cil_tmp121 = __cil_tmp120 + tmp___1;
#line 1075
          __cil_tmp122 = (size_t )__cil_tmp121;
#line 1075
          if (__cil_tmp122 > __cil_tmp119) {
#line 1077
            return (-22);
          } else {

          }
          }
        }
        }
#line 1078
        goto ldv_37875;
      } else {

      }
      }
    }
    }
  }
  }
  ldv_37875: ;
#line 1081
  return (0);
}
}
#line 1088 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int intel_panel_fitter_pipe(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  u32 pfit_control ;
  void *__cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  void *__cil_tmp7 ;
  struct drm_i915_private *__cil_tmp8 ;
  struct intel_device_info  const  *__cil_tmp9 ;
  u8 __cil_tmp10 ;
  unsigned char __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  u32 __cil_tmp13 ;
  int __cil_tmp14 ;

  {
#line 1090
  __cil_tmp4 = dev->dev_private;
#line 1090
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
  {
#line 1094
  __cil_tmp5 = dev->pci_device;
#line 1094
  if (__cil_tmp5 == 13687) {
#line 1095
    return (-1);
  } else {

  }
  }
  {
#line 1097
  pfit_control = i915_read32(dev_priv, 397872U);
  }
  {
#line 1100
  __cil_tmp6 = (int )pfit_control;
#line 1100
  if (__cil_tmp6 >= 0) {
#line 1101
    return (-1);
  } else {

  }
  }
  {
#line 1104
  __cil_tmp7 = dev->dev_private;
#line 1104
  __cil_tmp8 = (struct drm_i915_private *)__cil_tmp7;
#line 1104
  __cil_tmp9 = __cil_tmp8->info;
#line 1104
  __cil_tmp10 = __cil_tmp9->gen;
#line 1104
  __cil_tmp11 = (unsigned char )__cil_tmp10;
#line 1104
  __cil_tmp12 = (unsigned int )__cil_tmp11;
#line 1104
  if (__cil_tmp12 == 4U) {
    {
#line 1105
    __cil_tmp13 = pfit_control >> 29;
#line 1105
    __cil_tmp14 = (int )__cil_tmp13;
#line 1105
    return (__cil_tmp14 & 3);
    }
  } else {

  }
  }
#line 1108
  return (1);
}
}
#line 1111 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
int intel_overlay_put_image(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
{ struct drm_intel_overlay_put_image *put_image_rec ;
  drm_i915_private_t *dev_priv ;
  struct intel_overlay *overlay ;
  struct drm_mode_object *drmmode_obj ;
  struct intel_crtc *crtc ;
  struct drm_i915_gem_object *new_bo ;
  struct put_image_params *params ;
  int ret ;
  void *tmp ;
  struct drm_crtc  const  *__mptr ;
  struct drm_mode_object  const  *__mptr___0 ;
  struct drm_gem_object  const  *__mptr___1 ;
  struct drm_gem_object *tmp___0 ;
  struct drm_display_mode *mode ;
  int tmp___1 ;
  void *__cil_tmp19 ;
  drm_i915_private_t *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  unsigned long __cil_tmp22 ;
  struct intel_overlay *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  __u32 __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  struct mutex *__cil_tmp28 ;
  struct mutex *__cil_tmp29 ;
  struct mutex *__cil_tmp30 ;
  struct mutex *__cil_tmp31 ;
  struct put_image_params *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  __u32 __cil_tmp35 ;
  struct drm_mode_object *__cil_tmp36 ;
  unsigned long __cil_tmp37 ;
  unsigned long __cil_tmp38 ;
  struct drm_crtc *__cil_tmp39 ;
  struct drm_crtc *__cil_tmp40 ;
  __u32 __cil_tmp41 ;
  struct drm_gem_object *__cil_tmp42 ;
  unsigned long __cil_tmp43 ;
  struct drm_gem_object *__cil_tmp44 ;
  unsigned long __cil_tmp45 ;
  struct mutex *__cil_tmp46 ;
  struct mutex *__cil_tmp47 ;
  unsigned char *__cil_tmp48 ;
  unsigned char *__cil_tmp49 ;
  unsigned char __cil_tmp50 ;
  unsigned int __cil_tmp51 ;
  unsigned long __cil_tmp52 ;
  struct intel_crtc *__cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  int __cil_tmp55 ;
  enum pipe __cil_tmp56 ;
  unsigned int __cil_tmp57 ;
  unsigned int __cil_tmp58 ;
  int __cil_tmp59 ;
  u32 __cil_tmp60 ;
  __u16 __cil_tmp61 ;
  unsigned int __cil_tmp62 ;
  unsigned int __cil_tmp63 ;
  unsigned int __cil_tmp64 ;
  u32 __cil_tmp65 ;
  __u16 __cil_tmp66 ;
  unsigned int __cil_tmp67 ;
  unsigned int __cil_tmp68 ;
  unsigned int __cil_tmp69 ;
  unsigned short __cil_tmp70 ;
  unsigned int __cil_tmp71 ;
  unsigned int __cil_tmp72 ;
  __u16 __cil_tmp73 ;
  __u16 __cil_tmp74 ;
  __u16 __cil_tmp75 ;
  __u16 __cil_tmp76 ;
  __u16 __cil_tmp77 ;
  __u16 __cil_tmp78 ;
  __u16 __cil_tmp79 ;
  __u16 __cil_tmp80 ;
  short __cil_tmp81 ;
  int __cil_tmp82 ;
  short __cil_tmp83 ;
  int __cil_tmp84 ;
  short __cil_tmp85 ;
  int __cil_tmp86 ;
  short __cil_tmp87 ;
  int __cil_tmp88 ;
  __u32 __cil_tmp89 ;
  int __cil_tmp90 ;
  __u16 __cil_tmp91 ;
  __u16 __cil_tmp92 ;
  __u32 __cil_tmp93 ;
  __u32 __cil_tmp94 ;
  __u32 __cil_tmp95 ;
  struct mutex *__cil_tmp96 ;
  struct mutex *__cil_tmp97 ;
  void const   *__cil_tmp98 ;
  struct mutex *__cil_tmp99 ;
  struct mutex *__cil_tmp100 ;
  struct drm_gem_object *__cil_tmp101 ;
  void const   *__cil_tmp102 ;

  {
#line 1114
  put_image_rec = (struct drm_intel_overlay_put_image *)data;
#line 1115
  __cil_tmp19 = dev->dev_private;
#line 1115
  dev_priv = (drm_i915_private_t *)__cil_tmp19;
  {
#line 1123
  __cil_tmp20 = (drm_i915_private_t *)0;
#line 1123
  __cil_tmp21 = (unsigned long )__cil_tmp20;
#line 1123
  __cil_tmp22 = (unsigned long )dev_priv;
#line 1123
  if (__cil_tmp22 == __cil_tmp21) {
    {
#line 1124
    drm_err("intel_overlay_put_image", "called with no initialization\n");
    }
#line 1125
    return (-22);
  } else {

  }
  }
#line 1128
  overlay = dev_priv->overlay;
  {
#line 1129
  __cil_tmp23 = (struct intel_overlay *)0;
#line 1129
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 1129
  __cil_tmp25 = (unsigned long )overlay;
#line 1129
  if (__cil_tmp25 == __cil_tmp24) {
    {
#line 1130
    drm_ut_debug_printk(1U, "drm", "intel_overlay_put_image", "userspace bug: no overlay\n");
    }
#line 1131
    return (-19);
  } else {

  }
  }
  {
#line 1134
  __cil_tmp26 = put_image_rec->flags;
#line 1134
  __cil_tmp27 = __cil_tmp26 & 16777216U;
#line 1134
  if (__cil_tmp27 == 0U) {
    {
#line 1135
    __cil_tmp28 = & dev->mode_config.mutex;
#line 1135
    mutex_lock_nested(__cil_tmp28, 0U);
#line 1136
    __cil_tmp29 = & dev->struct_mutex;
#line 1136
    mutex_lock_nested(__cil_tmp29, 0U);
#line 1138
    ret = intel_overlay_switch_off(overlay);
#line 1140
    __cil_tmp30 = & dev->struct_mutex;
#line 1140
    mutex_unlock(__cil_tmp30);
#line 1141
    __cil_tmp31 = & dev->mode_config.mutex;
#line 1141
    mutex_unlock(__cil_tmp31);
    }
#line 1143
    return (ret);
  } else {

  }
  }
  {
#line 1146
  tmp = kmalloc(36UL, 208U);
#line 1146
  params = (struct put_image_params *)tmp;
  }
  {
#line 1147
  __cil_tmp32 = (struct put_image_params *)0;
#line 1147
  __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 1147
  __cil_tmp34 = (unsigned long )params;
#line 1147
  if (__cil_tmp34 == __cil_tmp33) {
#line 1148
    return (-12);
  } else {

  }
  }
  {
#line 1150
  __cil_tmp35 = put_image_rec->crtc_id;
#line 1150
  drmmode_obj = drm_mode_object_find(dev, __cil_tmp35, 3435973836U);
  }
  {
#line 1152
  __cil_tmp36 = (struct drm_mode_object *)0;
#line 1152
  __cil_tmp37 = (unsigned long )__cil_tmp36;
#line 1152
  __cil_tmp38 = (unsigned long )drmmode_obj;
#line 1152
  if (__cil_tmp38 == __cil_tmp37) {
#line 1153
    ret = -2;
#line 1154
    goto out_free;
  } else {

  }
  }
  {
#line 1156
  __mptr___0 = (struct drm_mode_object  const  *)drmmode_obj;
#line 1156
  __cil_tmp39 = (struct drm_crtc *)__mptr___0;
#line 1156
  __cil_tmp40 = __cil_tmp39 + 1152921504606846952UL;
#line 1156
  __mptr = (struct drm_crtc  const  *)__cil_tmp40;
#line 1156
  crtc = (struct intel_crtc *)__mptr;
#line 1158
  __cil_tmp41 = put_image_rec->bo_handle;
#line 1158
  tmp___0 = drm_gem_object_lookup(dev, file_priv, __cil_tmp41);
#line 1158
  __mptr___1 = (struct drm_gem_object  const  *)tmp___0;
#line 1158
  new_bo = (struct drm_i915_gem_object *)__mptr___1;
  }
  {
#line 1160
  __cil_tmp42 = (struct drm_gem_object *)0;
#line 1160
  __cil_tmp43 = (unsigned long )__cil_tmp42;
#line 1160
  __cil_tmp44 = & new_bo->base;
#line 1160
  __cil_tmp45 = (unsigned long )__cil_tmp44;
#line 1160
  if (__cil_tmp45 == __cil_tmp43) {
#line 1161
    ret = -2;
#line 1162
    goto out_free;
  } else {

  }
  }
  {
#line 1165
  __cil_tmp46 = & dev->mode_config.mutex;
#line 1165
  mutex_lock_nested(__cil_tmp46, 0U);
#line 1166
  __cil_tmp47 = & dev->struct_mutex;
#line 1166
  mutex_lock_nested(__cil_tmp47, 0U);
  }
  {
#line 1168
  __cil_tmp48 = (unsigned char *)new_bo;
#line 1168
  __cil_tmp49 = __cil_tmp48 + 225UL;
#line 1168
  __cil_tmp50 = *__cil_tmp49;
#line 1168
  __cil_tmp51 = (unsigned int )__cil_tmp50;
#line 1168
  if (__cil_tmp51 != 0U) {
    {
#line 1169
    drm_err("intel_overlay_put_image", "buffer used for overlay image can not be tiled\n");
#line 1170
    ret = -22;
    }
#line 1171
    goto out_unlock;
  } else {

  }
  }
  {
#line 1174
  ret = intel_overlay_recover_from_interrupt(overlay);
  }
#line 1175
  if (ret != 0) {
#line 1176
    goto out_unlock;
  } else {

  }
  {
#line 1178
  __cil_tmp52 = (unsigned long )crtc;
#line 1178
  __cil_tmp53 = overlay->crtc;
#line 1178
  __cil_tmp54 = (unsigned long )__cil_tmp53;
#line 1178
  if (__cil_tmp54 != __cil_tmp52) {
    {
#line 1179
    mode = & crtc->base.mode;
#line 1180
    ret = intel_overlay_switch_off(overlay);
    }
#line 1181
    if (ret != 0) {
#line 1182
      goto out_unlock;
    } else {

    }
    {
#line 1184
    ret = check_overlay_possible_on_crtc(overlay, crtc);
    }
#line 1185
    if (ret != 0) {
#line 1186
      goto out_unlock;
    } else {

    }
#line 1188
    overlay->crtc = crtc;
#line 1189
    crtc->overlay = overlay;
    {
#line 1192
    __cil_tmp55 = mode->hdisplay;
#line 1192
    if (__cil_tmp55 > 1024) {
      {
#line 1192
      tmp___1 = intel_panel_fitter_pipe(dev);
      }
      {
#line 1192
      __cil_tmp56 = crtc->pipe;
#line 1192
      __cil_tmp57 = (unsigned int )__cil_tmp56;
#line 1192
      __cil_tmp58 = (unsigned int )tmp___1;
#line 1192
      if (__cil_tmp58 == __cil_tmp57) {
        {
#line 1194
        overlay->pfit_active = 1;
#line 1195
        update_pfit_vscale_ratio(overlay);
        }
      } else {
#line 1197
        overlay->pfit_active = 0;
      }
      }
    } else {
#line 1197
      overlay->pfit_active = 0;
    }
    }
  } else {

  }
  }
  {
#line 1200
  ret = check_overlay_dst(overlay, put_image_rec);
  }
#line 1201
  if (ret != 0) {
#line 1202
    goto out_unlock;
  } else {

  }
  {
#line 1204
  __cil_tmp59 = overlay->pfit_active;
#line 1204
  if (__cil_tmp59 != 0) {
#line 1205
    __cil_tmp60 = overlay->pfit_vscale_ratio;
#line 1205
    __cil_tmp61 = put_image_rec->dst_y;
#line 1205
    __cil_tmp62 = (unsigned int )__cil_tmp61;
#line 1205
    __cil_tmp63 = __cil_tmp62 << 12;
#line 1205
    __cil_tmp64 = __cil_tmp63 / __cil_tmp60;
#line 1205
    params->dst_y = (short )__cil_tmp64;
#line 1208
    __cil_tmp65 = overlay->pfit_vscale_ratio;
#line 1208
    __cil_tmp66 = put_image_rec->dst_height;
#line 1208
    __cil_tmp67 = (unsigned int )__cil_tmp66;
#line 1208
    __cil_tmp68 = __cil_tmp67 << 12;
#line 1208
    __cil_tmp69 = __cil_tmp68 / __cil_tmp65;
#line 1208
    __cil_tmp70 = (unsigned short )__cil_tmp69;
#line 1208
    __cil_tmp71 = (unsigned int )__cil_tmp70;
#line 1208
    __cil_tmp72 = __cil_tmp71 + 1U;
#line 1208
    params->dst_h = (short )__cil_tmp72;
  } else {
#line 1211
    __cil_tmp73 = put_image_rec->dst_y;
#line 1211
    params->dst_y = (short )__cil_tmp73;
#line 1212
    __cil_tmp74 = put_image_rec->dst_height;
#line 1212
    params->dst_h = (short )__cil_tmp74;
  }
  }
#line 1214
  __cil_tmp75 = put_image_rec->dst_x;
#line 1214
  params->dst_x = (short )__cil_tmp75;
#line 1215
  __cil_tmp76 = put_image_rec->dst_width;
#line 1215
  params->dst_w = (short )__cil_tmp76;
#line 1217
  __cil_tmp77 = put_image_rec->src_width;
#line 1217
  params->src_w = (short )__cil_tmp77;
#line 1218
  __cil_tmp78 = put_image_rec->src_height;
#line 1218
  params->src_h = (short )__cil_tmp78;
#line 1219
  __cil_tmp79 = put_image_rec->src_scan_width;
#line 1219
  params->src_scan_w = (short )__cil_tmp79;
#line 1220
  __cil_tmp80 = put_image_rec->src_scan_height;
#line 1220
  params->src_scan_h = (short )__cil_tmp80;
  {
#line 1221
  __cil_tmp81 = params->src_h;
#line 1221
  __cil_tmp82 = (int )__cil_tmp81;
#line 1221
  __cil_tmp83 = params->src_scan_h;
#line 1221
  __cil_tmp84 = (int )__cil_tmp83;
#line 1221
  if (__cil_tmp84 > __cil_tmp82) {
#line 1223
    ret = -22;
#line 1224
    goto out_unlock;
  } else {
    {
#line 1221
    __cil_tmp85 = params->src_w;
#line 1221
    __cil_tmp86 = (int )__cil_tmp85;
#line 1221
    __cil_tmp87 = params->src_scan_w;
#line 1221
    __cil_tmp88 = (int )__cil_tmp87;
#line 1221
    if (__cil_tmp88 > __cil_tmp86) {
#line 1223
      ret = -22;
#line 1224
      goto out_unlock;
    } else {

    }
    }
  }
  }
  {
#line 1227
  ret = check_overlay_src(dev, put_image_rec, new_bo);
  }
#line 1228
  if (ret != 0) {
#line 1229
    goto out_unlock;
  } else {

  }
  {
#line 1230
  __cil_tmp89 = put_image_rec->flags;
#line 1230
  __cil_tmp90 = (int )__cil_tmp89;
#line 1230
  params->format = __cil_tmp90 & 16777215;
#line 1231
  __cil_tmp91 = put_image_rec->stride_Y;
#line 1231
  params->stride_Y = (short )__cil_tmp91;
#line 1232
  __cil_tmp92 = put_image_rec->stride_UV;
#line 1232
  params->stride_UV = (short )__cil_tmp92;
#line 1233
  __cil_tmp93 = put_image_rec->offset_Y;
#line 1233
  params->offset_Y = (int )__cil_tmp93;
#line 1234
  __cil_tmp94 = put_image_rec->offset_U;
#line 1234
  params->offset_U = (int )__cil_tmp94;
#line 1235
  __cil_tmp95 = put_image_rec->offset_V;
#line 1235
  params->offset_V = (int )__cil_tmp95;
#line 1238
  ret = check_overlay_scaling(params);
  }
#line 1239
  if (ret != 0) {
#line 1240
    goto out_unlock;
  } else {

  }
  {
#line 1242
  ret = intel_overlay_do_put_image(overlay, new_bo, params);
  }
#line 1243
  if (ret != 0) {
#line 1244
    goto out_unlock;
  } else {

  }
  {
#line 1246
  __cil_tmp96 = & dev->struct_mutex;
#line 1246
  mutex_unlock(__cil_tmp96);
#line 1247
  __cil_tmp97 = & dev->mode_config.mutex;
#line 1247
  mutex_unlock(__cil_tmp97);
#line 1249
  __cil_tmp98 = (void const   *)params;
#line 1249
  kfree(__cil_tmp98);
  }
#line 1251
  return (0);
  out_unlock: 
  {
#line 1254
  __cil_tmp99 = & dev->struct_mutex;
#line 1254
  mutex_unlock(__cil_tmp99);
#line 1255
  __cil_tmp100 = & dev->mode_config.mutex;
#line 1255
  mutex_unlock(__cil_tmp100);
#line 1256
  __cil_tmp101 = & new_bo->base;
#line 1256
  drm_gem_object_unreference_unlocked(__cil_tmp101);
  }
  out_free: 
  {
#line 1258
  __cil_tmp102 = (void const   *)params;
#line 1258
  kfree(__cil_tmp102);
  }
#line 1260
  return (ret);
}
}
#line 1263 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void update_reg_attrs(struct intel_overlay *overlay , struct overlay_registers *regs ) 
{ u32 __cil_tmp3 ;
  unsigned int __cil_tmp4 ;
  u32 __cil_tmp5 ;
  u32 __cil_tmp6 ;

  {
#line 1266
  __cil_tmp3 = overlay->brightness;
#line 1266
  __cil_tmp4 = __cil_tmp3 & 255U;
#line 1266
  __cil_tmp5 = overlay->contrast;
#line 1266
  __cil_tmp6 = __cil_tmp5 << 18;
#line 1266
  regs->OCLRC0 = __cil_tmp6 | __cil_tmp4;
#line 1267
  regs->OCLRC1 = overlay->saturation;
#line 1268
  return;
}
}
#line 1270 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static bool check_gamma_bounds(u32 gamma1 , u32 gamma2 ) 
{ int i ;
  unsigned int __cil_tmp4 ;
  unsigned int __cil_tmp5 ;
  int __cil_tmp6 ;
  u32 __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  int __cil_tmp9 ;
  u32 __cil_tmp10 ;
  unsigned int __cil_tmp11 ;

  {
  {
#line 1274
  __cil_tmp4 = gamma1 & 4278190080U;
#line 1274
  if (__cil_tmp4 != 0U) {
#line 1275
    return ((bool )0);
  } else {
    {
#line 1274
    __cil_tmp5 = gamma2 & 4278190080U;
#line 1274
    if (__cil_tmp5 != 0U) {
#line 1275
      return ((bool )0);
    } else {

    }
    }
  }
  }
#line 1277
  i = 0;
#line 1277
  goto ldv_37915;
  ldv_37914: ;
  {
#line 1278
  __cil_tmp6 = i * 8;
#line 1278
  __cil_tmp7 = gamma2 >> __cil_tmp6;
#line 1278
  __cil_tmp8 = __cil_tmp7 & 255U;
#line 1278
  __cil_tmp9 = i * 8;
#line 1278
  __cil_tmp10 = gamma1 >> __cil_tmp9;
#line 1278
  __cil_tmp11 = __cil_tmp10 & 255U;
#line 1278
  if (__cil_tmp11 >= __cil_tmp8) {
#line 1279
    return ((bool )0);
  } else {

  }
  }
#line 1277
  i = i + 1;
  ldv_37915: ;
#line 1277
  if (i <= 2) {
#line 1278
    goto ldv_37914;
  } else {
#line 1280
    goto ldv_37916;
  }
  ldv_37916: ;
#line 1282
  return ((bool )1);
}
}
#line 1285 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static bool check_gamma5_errata(u32 gamma5 ) 
{ int i ;
  int __cil_tmp3 ;
  u32 __cil_tmp4 ;
  unsigned int __cil_tmp5 ;

  {
#line 1289
  i = 0;
#line 1289
  goto ldv_37922;
  ldv_37921: ;
  {
#line 1290
  __cil_tmp3 = i * 8;
#line 1290
  __cil_tmp4 = gamma5 >> __cil_tmp3;
#line 1290
  __cil_tmp5 = __cil_tmp4 & 255U;
#line 1290
  if (__cil_tmp5 == 128U) {
#line 1291
    return ((bool )0);
  } else {

  }
  }
#line 1289
  i = i + 1;
  ldv_37922: ;
#line 1289
  if (i <= 2) {
#line 1290
    goto ldv_37921;
  } else {
#line 1292
    goto ldv_37923;
  }
  ldv_37923: ;
#line 1294
  return ((bool )1);
}
}
#line 1297 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static int check_gamma(struct drm_intel_overlay_attrs *attrs ) 
{ bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  bool tmp___3 ;
  int tmp___4 ;
  bool tmp___5 ;
  int tmp___6 ;
  bool tmp___7 ;
  int tmp___8 ;
  bool tmp___9 ;
  int tmp___10 ;
  bool tmp___11 ;
  int tmp___12 ;
  bool tmp___13 ;
  int tmp___14 ;
  __u32 __cil_tmp18 ;
  __u32 __cil_tmp19 ;
  __u32 __cil_tmp20 ;
  __u32 __cil_tmp21 ;
  __u32 __cil_tmp22 ;
  __u32 __cil_tmp23 ;
  __u32 __cil_tmp24 ;
  __u32 __cil_tmp25 ;
  __u32 __cil_tmp26 ;
  __u32 __cil_tmp27 ;
  __u32 __cil_tmp28 ;
  __u32 __cil_tmp29 ;
  __u32 __cil_tmp30 ;

  {
  {
#line 1299
  __cil_tmp18 = attrs->gamma0;
#line 1299
  tmp = check_gamma_bounds(0U, __cil_tmp18);
  }
#line 1299
  if (tmp) {
#line 1299
    tmp___0 = 0;
  } else {
#line 1299
    tmp___0 = 1;
  }
#line 1299
  if (tmp___0) {
#line 1306
    return (-22);
  } else {
    {
#line 1299
    __cil_tmp19 = attrs->gamma0;
#line 1299
    __cil_tmp20 = attrs->gamma1;
#line 1299
    tmp___1 = check_gamma_bounds(__cil_tmp19, __cil_tmp20);
    }
#line 1299
    if (tmp___1) {
#line 1299
      tmp___2 = 0;
    } else {
#line 1299
      tmp___2 = 1;
    }
#line 1299
    if (tmp___2) {
#line 1306
      return (-22);
    } else {
      {
#line 1299
      __cil_tmp21 = attrs->gamma1;
#line 1299
      __cil_tmp22 = attrs->gamma2;
#line 1299
      tmp___3 = check_gamma_bounds(__cil_tmp21, __cil_tmp22);
      }
#line 1299
      if (tmp___3) {
#line 1299
        tmp___4 = 0;
      } else {
#line 1299
        tmp___4 = 1;
      }
#line 1299
      if (tmp___4) {
#line 1306
        return (-22);
      } else {
        {
#line 1299
        __cil_tmp23 = attrs->gamma2;
#line 1299
        __cil_tmp24 = attrs->gamma3;
#line 1299
        tmp___5 = check_gamma_bounds(__cil_tmp23, __cil_tmp24);
        }
#line 1299
        if (tmp___5) {
#line 1299
          tmp___6 = 0;
        } else {
#line 1299
          tmp___6 = 1;
        }
#line 1299
        if (tmp___6) {
#line 1306
          return (-22);
        } else {
          {
#line 1299
          __cil_tmp25 = attrs->gamma3;
#line 1299
          __cil_tmp26 = attrs->gamma4;
#line 1299
          tmp___7 = check_gamma_bounds(__cil_tmp25, __cil_tmp26);
          }
#line 1299
          if (tmp___7) {
#line 1299
            tmp___8 = 0;
          } else {
#line 1299
            tmp___8 = 1;
          }
#line 1299
          if (tmp___8) {
#line 1306
            return (-22);
          } else {
            {
#line 1299
            __cil_tmp27 = attrs->gamma4;
#line 1299
            __cil_tmp28 = attrs->gamma5;
#line 1299
            tmp___9 = check_gamma_bounds(__cil_tmp27, __cil_tmp28);
            }
#line 1299
            if (tmp___9) {
#line 1299
              tmp___10 = 0;
            } else {
#line 1299
              tmp___10 = 1;
            }
#line 1299
            if (tmp___10) {
#line 1306
              return (-22);
            } else {
              {
#line 1299
              __cil_tmp29 = attrs->gamma5;
#line 1299
              tmp___11 = check_gamma_bounds(__cil_tmp29, 16777215U);
              }
#line 1299
              if (tmp___11) {
#line 1299
                tmp___12 = 0;
              } else {
#line 1299
                tmp___12 = 1;
              }
#line 1299
              if (tmp___12) {
#line 1306
                return (-22);
              } else {

              }
            }
          }
        }
      }
    }
  }
  {
#line 1308
  __cil_tmp30 = attrs->gamma5;
#line 1308
  tmp___13 = check_gamma5_errata(__cil_tmp30);
  }
#line 1308
  if (tmp___13) {
#line 1308
    tmp___14 = 0;
  } else {
#line 1308
    tmp___14 = 1;
  }
#line 1308
  if (tmp___14) {
#line 1309
    return (-22);
  } else {

  }
#line 1311
  return (0);
}
}
#line 1314 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
int intel_overlay_attrs(struct drm_device *dev , void *data , struct drm_file *file_priv ) 
{ struct drm_intel_overlay_attrs *attrs ;
  drm_i915_private_t *dev_priv ;
  struct intel_overlay *overlay ;
  struct overlay_registers *regs ;
  int ret ;
  void *__cil_tmp9 ;
  drm_i915_private_t *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct intel_overlay *__cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  unsigned long __cil_tmp15 ;
  struct mutex *__cil_tmp16 ;
  struct mutex *__cil_tmp17 ;
  __u32 __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  u32 __cil_tmp20 ;
  void *__cil_tmp21 ;
  struct drm_i915_private *__cil_tmp22 ;
  struct intel_device_info  const  *__cil_tmp23 ;
  u8 __cil_tmp24 ;
  unsigned char __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  __s32 __cil_tmp27 ;
  __s32 __cil_tmp28 ;
  __u32 __cil_tmp29 ;
  __u32 __cil_tmp30 ;
  __s32 __cil_tmp31 ;
  struct overlay_registers *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  __u32 __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  void *__cil_tmp37 ;
  struct drm_i915_private *__cil_tmp38 ;
  struct intel_device_info  const  *__cil_tmp39 ;
  u8 __cil_tmp40 ;
  unsigned char __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  int __cil_tmp43 ;
  __u32 __cil_tmp44 ;
  __u32 __cil_tmp45 ;
  __u32 __cil_tmp46 ;
  __u32 __cil_tmp47 ;
  __u32 __cil_tmp48 ;
  __u32 __cil_tmp49 ;
  struct mutex *__cil_tmp50 ;
  struct mutex *__cil_tmp51 ;

  {
#line 1317
  attrs = (struct drm_intel_overlay_attrs *)data;
#line 1318
  __cil_tmp9 = dev->dev_private;
#line 1318
  dev_priv = (drm_i915_private_t *)__cil_tmp9;
  {
#line 1323
  __cil_tmp10 = (drm_i915_private_t *)0;
#line 1323
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 1323
  __cil_tmp12 = (unsigned long )dev_priv;
#line 1323
  if (__cil_tmp12 == __cil_tmp11) {
    {
#line 1324
    drm_err("intel_overlay_attrs", "called with no initialization\n");
    }
#line 1325
    return (-22);
  } else {

  }
  }
#line 1328
  overlay = dev_priv->overlay;
  {
#line 1329
  __cil_tmp13 = (struct intel_overlay *)0;
#line 1329
  __cil_tmp14 = (unsigned long )__cil_tmp13;
#line 1329
  __cil_tmp15 = (unsigned long )overlay;
#line 1329
  if (__cil_tmp15 == __cil_tmp14) {
    {
#line 1330
    drm_ut_debug_printk(1U, "drm", "intel_overlay_attrs", "userspace bug: no overlay\n");
    }
#line 1331
    return (-19);
  } else {

  }
  }
  {
#line 1334
  __cil_tmp16 = & dev->mode_config.mutex;
#line 1334
  mutex_lock_nested(__cil_tmp16, 0U);
#line 1335
  __cil_tmp17 = & dev->struct_mutex;
#line 1335
  mutex_lock_nested(__cil_tmp17, 0U);
#line 1337
  ret = -22;
  }
  {
#line 1338
  __cil_tmp18 = attrs->flags;
#line 1338
  __cil_tmp19 = __cil_tmp18 & 1U;
#line 1338
  if (__cil_tmp19 == 0U) {
#line 1339
    attrs->color_key = overlay->color_key;
#line 1340
    __cil_tmp20 = overlay->brightness;
#line 1340
    attrs->brightness = (__s32 )__cil_tmp20;
#line 1341
    attrs->contrast = overlay->contrast;
#line 1342
    attrs->saturation = overlay->saturation;
    {
#line 1344
    __cil_tmp21 = dev->dev_private;
#line 1344
    __cil_tmp22 = (struct drm_i915_private *)__cil_tmp21;
#line 1344
    __cil_tmp23 = __cil_tmp22->info;
#line 1344
    __cil_tmp24 = __cil_tmp23->gen;
#line 1344
    __cil_tmp25 = (unsigned char )__cil_tmp24;
#line 1344
    __cil_tmp26 = (unsigned int )__cil_tmp25;
#line 1344
    if (__cil_tmp26 != 2U) {
      {
#line 1345
      attrs->gamma0 = i915_read32(dev_priv, 196644U);
#line 1346
      attrs->gamma1 = i915_read32(dev_priv, 196640U);
#line 1347
      attrs->gamma2 = i915_read32(dev_priv, 196636U);
#line 1348
      attrs->gamma3 = i915_read32(dev_priv, 196632U);
#line 1349
      attrs->gamma4 = i915_read32(dev_priv, 196628U);
#line 1350
      attrs->gamma5 = i915_read32(dev_priv, 196624U);
      }
    } else {

    }
    }
  } else {
    {
#line 1353
    __cil_tmp27 = attrs->brightness;
#line 1353
    if (__cil_tmp27 < -128) {
#line 1354
      goto out_unlock;
    } else {
      {
#line 1353
      __cil_tmp28 = attrs->brightness;
#line 1353
      if (__cil_tmp28 > 127) {
#line 1354
        goto out_unlock;
      } else {

      }
      }
    }
    }
    {
#line 1355
    __cil_tmp29 = attrs->contrast;
#line 1355
    if (__cil_tmp29 > 255U) {
#line 1356
      goto out_unlock;
    } else {

    }
    }
    {
#line 1357
    __cil_tmp30 = attrs->saturation;
#line 1357
    if (__cil_tmp30 > 1023U) {
#line 1358
      goto out_unlock;
    } else {

    }
    }
    {
#line 1360
    overlay->color_key = attrs->color_key;
#line 1361
    __cil_tmp31 = attrs->brightness;
#line 1361
    overlay->brightness = (u32 )__cil_tmp31;
#line 1362
    overlay->contrast = attrs->contrast;
#line 1363
    overlay->saturation = attrs->saturation;
#line 1365
    regs = intel_overlay_map_regs(overlay);
    }
    {
#line 1366
    __cil_tmp32 = (struct overlay_registers *)0;
#line 1366
    __cil_tmp33 = (unsigned long )__cil_tmp32;
#line 1366
    __cil_tmp34 = (unsigned long )regs;
#line 1366
    if (__cil_tmp34 == __cil_tmp33) {
#line 1367
      ret = -12;
#line 1368
      goto out_unlock;
    } else {

    }
    }
    {
#line 1371
    update_reg_attrs(overlay, regs);
#line 1373
    intel_overlay_unmap_regs(overlay, regs);
    }
    {
#line 1375
    __cil_tmp35 = attrs->flags;
#line 1375
    __cil_tmp36 = __cil_tmp35 & 2U;
#line 1375
    if (__cil_tmp36 != 0U) {
      {
#line 1376
      __cil_tmp37 = dev->dev_private;
#line 1376
      __cil_tmp38 = (struct drm_i915_private *)__cil_tmp37;
#line 1376
      __cil_tmp39 = __cil_tmp38->info;
#line 1376
      __cil_tmp40 = __cil_tmp39->gen;
#line 1376
      __cil_tmp41 = (unsigned char )__cil_tmp40;
#line 1376
      __cil_tmp42 = (unsigned int )__cil_tmp41;
#line 1376
      if (__cil_tmp42 == 2U) {
#line 1377
        goto out_unlock;
      } else {

      }
      }
      {
#line 1379
      __cil_tmp43 = overlay->active;
#line 1379
      if (__cil_tmp43 != 0) {
#line 1380
        ret = -16;
#line 1381
        goto out_unlock;
      } else {

      }
      }
      {
#line 1384
      ret = check_gamma(attrs);
      }
#line 1385
      if (ret != 0) {
#line 1386
        goto out_unlock;
      } else {

      }
      {
#line 1388
      __cil_tmp44 = attrs->gamma0;
#line 1388
      i915_write32(dev_priv, 196644U, __cil_tmp44);
#line 1389
      __cil_tmp45 = attrs->gamma1;
#line 1389
      i915_write32(dev_priv, 196640U, __cil_tmp45);
#line 1390
      __cil_tmp46 = attrs->gamma2;
#line 1390
      i915_write32(dev_priv, 196636U, __cil_tmp46);
#line 1391
      __cil_tmp47 = attrs->gamma3;
#line 1391
      i915_write32(dev_priv, 196632U, __cil_tmp47);
#line 1392
      __cil_tmp48 = attrs->gamma4;
#line 1392
      i915_write32(dev_priv, 196628U, __cil_tmp48);
#line 1393
      __cil_tmp49 = attrs->gamma5;
#line 1393
      i915_write32(dev_priv, 196624U, __cil_tmp49);
      }
    } else {

    }
    }
  }
  }
#line 1397
  ret = 0;
  out_unlock: 
  {
#line 1399
  __cil_tmp50 = & dev->struct_mutex;
#line 1399
  mutex_unlock(__cil_tmp50);
#line 1400
  __cil_tmp51 = & dev->mode_config.mutex;
#line 1400
  mutex_unlock(__cil_tmp51);
  }
#line 1402
  return (ret);
}
}
#line 1405 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
void intel_setup_overlay(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_overlay *overlay ;
  struct drm_i915_gem_object *reg_bo ;
  struct overlay_registers *regs ;
  int ret ;
  void *tmp ;
  int __ret_warn_on ;
  long tmp___0 ;
  long tmp___1 ;
  void *__cil_tmp11 ;
  void *__cil_tmp12 ;
  struct drm_i915_private *__cil_tmp13 ;
  struct intel_device_info  const  *__cil_tmp14 ;
  unsigned char *__cil_tmp15 ;
  unsigned char *__cil_tmp16 ;
  unsigned char __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  struct intel_overlay *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  struct mutex *__cil_tmp22 ;
  struct intel_overlay *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  struct intel_overlay *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  int __cil_tmp27 ;
  long __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  long __cil_tmp32 ;
  struct drm_i915_gem_object *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  unsigned long __cil_tmp35 ;
  void *__cil_tmp36 ;
  struct drm_i915_private *__cil_tmp37 ;
  struct intel_device_info  const  *__cil_tmp38 ;
  unsigned char *__cil_tmp39 ;
  unsigned char *__cil_tmp40 ;
  unsigned char __cil_tmp41 ;
  unsigned int __cil_tmp42 ;
  struct drm_i915_gem_phys_object *__cil_tmp43 ;
  drm_dma_handle_t *__cil_tmp44 ;
  dma_addr_t __cil_tmp45 ;
  bool __cil_tmp46 ;
  bool __cil_tmp47 ;
  struct overlay_registers *__cil_tmp48 ;
  unsigned long __cil_tmp49 ;
  unsigned long __cil_tmp50 ;
  void *__cil_tmp51 ;
  struct mutex *__cil_tmp52 ;
  void *__cil_tmp53 ;
  struct drm_i915_private *__cil_tmp54 ;
  struct intel_device_info  const  *__cil_tmp55 ;
  unsigned char *__cil_tmp56 ;
  unsigned char *__cil_tmp57 ;
  unsigned char __cil_tmp58 ;
  unsigned int __cil_tmp59 ;
  struct drm_gem_object *__cil_tmp60 ;
  struct mutex *__cil_tmp61 ;
  void const   *__cil_tmp62 ;

  {
#line 1407
  __cil_tmp11 = dev->dev_private;
#line 1407
  dev_priv = (drm_i915_private_t *)__cil_tmp11;
  {
#line 1413
  __cil_tmp12 = dev->dev_private;
#line 1413
  __cil_tmp13 = (struct drm_i915_private *)__cil_tmp12;
#line 1413
  __cil_tmp14 = __cil_tmp13->info;
#line 1413
  __cil_tmp15 = (unsigned char *)__cil_tmp14;
#line 1413
  __cil_tmp16 = __cil_tmp15 + 2UL;
#line 1413
  __cil_tmp17 = *__cil_tmp16;
#line 1413
  __cil_tmp18 = (unsigned int )__cil_tmp17;
#line 1413
  if (__cil_tmp18 == 0U) {
#line 1414
    return;
  } else {

  }
  }
  {
#line 1416
  tmp = kzalloc(96UL, 208U);
#line 1416
  overlay = (struct intel_overlay *)tmp;
  }
  {
#line 1417
  __cil_tmp19 = (struct intel_overlay *)0;
#line 1417
  __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 1417
  __cil_tmp21 = (unsigned long )overlay;
#line 1417
  if (__cil_tmp21 == __cil_tmp20) {
#line 1418
    return;
  } else {

  }
  }
  {
#line 1420
  __cil_tmp22 = & dev->struct_mutex;
#line 1420
  mutex_lock_nested(__cil_tmp22, 0U);
#line 1421
  __cil_tmp23 = (struct intel_overlay *)0;
#line 1421
  __cil_tmp24 = (unsigned long )__cil_tmp23;
#line 1421
  __cil_tmp25 = dev_priv->overlay;
#line 1421
  __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 1421
  __ret_warn_on = __cil_tmp26 != __cil_tmp24;
#line 1421
  __cil_tmp27 = __ret_warn_on != 0;
#line 1421
  __cil_tmp28 = (long )__cil_tmp27;
#line 1421
  tmp___0 = __builtin_expect(__cil_tmp28, 0L);
  }
#line 1421
  if (tmp___0 != 0L) {
    {
#line 1421
    __cil_tmp29 = (int const   )1421;
#line 1421
    __cil_tmp30 = (int )__cil_tmp29;
#line 1421
    warn_slowpath_null("/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p",
                       __cil_tmp30);
    }
  } else {

  }
  {
#line 1421
  __cil_tmp31 = __ret_warn_on != 0;
#line 1421
  __cil_tmp32 = (long )__cil_tmp31;
#line 1421
  tmp___1 = __builtin_expect(__cil_tmp32, 0L);
  }
#line 1421
  if (tmp___1 != 0L) {
#line 1422
    goto out_free;
  } else {

  }
  {
#line 1424
  overlay->dev = dev;
#line 1426
  reg_bo = i915_gem_alloc_object(dev, 4096UL);
  }
  {
#line 1427
  __cil_tmp33 = (struct drm_i915_gem_object *)0;
#line 1427
  __cil_tmp34 = (unsigned long )__cil_tmp33;
#line 1427
  __cil_tmp35 = (unsigned long )reg_bo;
#line 1427
  if (__cil_tmp35 == __cil_tmp34) {
#line 1428
    goto out_free;
  } else {

  }
  }
#line 1429
  overlay->reg_bo = reg_bo;
  {
#line 1431
  __cil_tmp36 = dev->dev_private;
#line 1431
  __cil_tmp37 = (struct drm_i915_private *)__cil_tmp36;
#line 1431
  __cil_tmp38 = __cil_tmp37->info;
#line 1431
  __cil_tmp39 = (unsigned char *)__cil_tmp38;
#line 1431
  __cil_tmp40 = __cil_tmp39 + 3UL;
#line 1431
  __cil_tmp41 = *__cil_tmp40;
#line 1431
  __cil_tmp42 = (unsigned int )__cil_tmp41;
#line 1431
  if (__cil_tmp42 != 0U) {
    {
#line 1432
    ret = i915_gem_attach_phys_object(dev, reg_bo, 3, 4096);
    }
#line 1435
    if (ret != 0) {
      {
#line 1436
      drm_err("intel_setup_overlay", "failed to attach phys overlay regs\n");
      }
#line 1437
      goto out_free_bo;
    } else {

    }
#line 1439
    __cil_tmp43 = reg_bo->phys_obj;
#line 1439
    __cil_tmp44 = __cil_tmp43->handle;
#line 1439
    __cil_tmp45 = __cil_tmp44->busaddr;
#line 1439
    overlay->flip_addr = (u32 )__cil_tmp45;
  } else {
    {
#line 1441
    __cil_tmp46 = (bool )1;
#line 1441
    ret = i915_gem_object_pin(reg_bo, 4096U, __cil_tmp46);
    }
#line 1442
    if (ret != 0) {
      {
#line 1443
      drm_err("intel_setup_overlay", "failed to pin overlay register bo\n");
      }
#line 1444
      goto out_free_bo;
    } else {

    }
    {
#line 1446
    overlay->flip_addr = reg_bo->gtt_offset;
#line 1448
    __cil_tmp47 = (bool )1;
#line 1448
    ret = i915_gem_object_set_to_gtt_domain(reg_bo, __cil_tmp47);
    }
#line 1449
    if (ret != 0) {
      {
#line 1450
      drm_err("intel_setup_overlay", "failed to move overlay register bo into the GTT\n");
      }
#line 1451
      goto out_unpin_bo;
    } else {

    }
  }
  }
  {
#line 1456
  overlay->color_key = 66046U;
#line 1457
  overlay->brightness = 4294967277U;
#line 1458
  overlay->contrast = 75U;
#line 1459
  overlay->saturation = 146U;
#line 1461
  regs = intel_overlay_map_regs(overlay);
  }
  {
#line 1462
  __cil_tmp48 = (struct overlay_registers *)0;
#line 1462
  __cil_tmp49 = (unsigned long )__cil_tmp48;
#line 1462
  __cil_tmp50 = (unsigned long )regs;
#line 1462
  if (__cil_tmp50 == __cil_tmp49) {
#line 1463
    goto out_unpin_bo;
  } else {

  }
  }
  {
#line 1465
  __cil_tmp51 = (void *)regs;
#line 1465
  memset(__cil_tmp51, 0, 1792UL);
#line 1466
  update_polyphase_filter(regs);
#line 1467
  update_reg_attrs(overlay, regs);
#line 1469
  intel_overlay_unmap_regs(overlay, regs);
#line 1471
  dev_priv->overlay = overlay;
#line 1472
  __cil_tmp52 = & dev->struct_mutex;
#line 1472
  mutex_unlock(__cil_tmp52);
#line 1473
  printk("<6>[drm] initialized overlay support\n");
  }
#line 1474
  return;
  out_unpin_bo: ;
  {
#line 1477
  __cil_tmp53 = dev->dev_private;
#line 1477
  __cil_tmp54 = (struct drm_i915_private *)__cil_tmp53;
#line 1477
  __cil_tmp55 = __cil_tmp54->info;
#line 1477
  __cil_tmp56 = (unsigned char *)__cil_tmp55;
#line 1477
  __cil_tmp57 = __cil_tmp56 + 3UL;
#line 1477
  __cil_tmp58 = *__cil_tmp57;
#line 1477
  __cil_tmp59 = (unsigned int )__cil_tmp58;
#line 1477
  if (__cil_tmp59 == 0U) {
    {
#line 1478
    i915_gem_object_unpin(reg_bo);
    }
  } else {

  }
  }
  out_free_bo: 
  {
#line 1480
  __cil_tmp60 = & reg_bo->base;
#line 1480
  drm_gem_object_unreference(__cil_tmp60);
  }
  out_free: 
  {
#line 1482
  __cil_tmp61 = & dev->struct_mutex;
#line 1482
  mutex_unlock(__cil_tmp61);
#line 1483
  __cil_tmp62 = (void const   *)overlay;
#line 1483
  kfree(__cil_tmp62);
  }
#line 1484
  return;
}
}
#line 1487 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
void intel_cleanup_overlay(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  long tmp ;
  void *__cil_tmp4 ;
  struct intel_overlay *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  struct intel_overlay *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct intel_overlay *__cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  long __cil_tmp12 ;
  struct intel_overlay *__cil_tmp13 ;
  struct drm_i915_gem_object *__cil_tmp14 ;
  struct drm_gem_object *__cil_tmp15 ;
  struct intel_overlay *__cil_tmp16 ;
  void const   *__cil_tmp17 ;

  {
#line 1489
  __cil_tmp4 = dev->dev_private;
#line 1489
  dev_priv = (drm_i915_private_t *)__cil_tmp4;
  {
#line 1491
  __cil_tmp5 = (struct intel_overlay *)0;
#line 1491
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 1491
  __cil_tmp7 = dev_priv->overlay;
#line 1491
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 1491
  if (__cil_tmp8 == __cil_tmp6) {
#line 1492
    return;
  } else {

  }
  }
  {
#line 1497
  __cil_tmp9 = dev_priv->overlay;
#line 1497
  __cil_tmp10 = __cil_tmp9->active;
#line 1497
  __cil_tmp11 = __cil_tmp10 != 0;
#line 1497
  __cil_tmp12 = (long )__cil_tmp11;
#line 1497
  tmp = __builtin_expect(__cil_tmp12, 0L);
  }
#line 1497
  if (tmp != 0L) {
#line 1497
    __asm__  volatile   ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"),
                         "i" (1497), "i" (12UL));
    ldv_37957: ;
#line 1497
    goto ldv_37957;
  } else {

  }
  {
#line 1499
  __cil_tmp13 = dev_priv->overlay;
#line 1499
  __cil_tmp14 = __cil_tmp13->reg_bo;
#line 1499
  __cil_tmp15 = & __cil_tmp14->base;
#line 1499
  drm_gem_object_unreference_unlocked(__cil_tmp15);
#line 1500
  __cil_tmp16 = dev_priv->overlay;
#line 1500
  __cil_tmp17 = (void const   *)__cil_tmp16;
#line 1500
  kfree(__cil_tmp17);
  }
#line 1501
  return;
}
}
#line 1514 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay ) 
{ drm_i915_private_t *dev_priv ;
  struct overlay_registers *regs ;
  void *tmp ;
  struct drm_device *__cil_tmp5 ;
  void *__cil_tmp6 ;
  struct drm_device *__cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  unsigned char *__cil_tmp11 ;
  unsigned char *__cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  struct drm_i915_gem_object *__cil_tmp15 ;
  struct drm_i915_gem_phys_object *__cil_tmp16 ;
  drm_dma_handle_t *__cil_tmp17 ;
  void *__cil_tmp18 ;
  struct io_mapping *__cil_tmp19 ;
  struct drm_i915_gem_object *__cil_tmp20 ;
  uint32_t __cil_tmp21 ;
  unsigned long __cil_tmp22 ;

  {
#line 1516
  __cil_tmp5 = overlay->dev;
#line 1516
  __cil_tmp6 = __cil_tmp5->dev_private;
#line 1516
  dev_priv = (drm_i915_private_t *)__cil_tmp6;
  {
#line 1519
  __cil_tmp7 = overlay->dev;
#line 1519
  __cil_tmp8 = __cil_tmp7->dev_private;
#line 1519
  __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 1519
  __cil_tmp10 = __cil_tmp9->info;
#line 1519
  __cil_tmp11 = (unsigned char *)__cil_tmp10;
#line 1519
  __cil_tmp12 = __cil_tmp11 + 3UL;
#line 1519
  __cil_tmp13 = *__cil_tmp12;
#line 1519
  __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 1519
  if (__cil_tmp14 != 0U) {
#line 1520
    __cil_tmp15 = overlay->reg_bo;
#line 1520
    __cil_tmp16 = __cil_tmp15->phys_obj;
#line 1520
    __cil_tmp17 = __cil_tmp16->handle;
#line 1520
    __cil_tmp18 = __cil_tmp17->vaddr;
#line 1520
    regs = (struct overlay_registers *)__cil_tmp18;
  } else {
    {
#line 1522
    __cil_tmp19 = dev_priv->mm.gtt_mapping;
#line 1522
    __cil_tmp20 = overlay->reg_bo;
#line 1522
    __cil_tmp21 = __cil_tmp20->gtt_offset;
#line 1522
    __cil_tmp22 = (unsigned long )__cil_tmp21;
#line 1522
    tmp = io_mapping_map_atomic_wc(__cil_tmp19, __cil_tmp22);
#line 1522
    regs = (struct overlay_registers *)tmp;
    }
  }
  }
#line 1525
  return (regs);
}
}
#line 1528 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay , struct overlay_registers *regs ) 
{ struct drm_device *__cil_tmp3 ;
  void *__cil_tmp4 ;
  struct drm_i915_private *__cil_tmp5 ;
  struct intel_device_info  const  *__cil_tmp6 ;
  unsigned char *__cil_tmp7 ;
  unsigned char *__cil_tmp8 ;
  unsigned char __cil_tmp9 ;
  unsigned int __cil_tmp10 ;
  void *__cil_tmp11 ;

  {
  {
#line 1531
  __cil_tmp3 = overlay->dev;
#line 1531
  __cil_tmp4 = __cil_tmp3->dev_private;
#line 1531
  __cil_tmp5 = (struct drm_i915_private *)__cil_tmp4;
#line 1531
  __cil_tmp6 = __cil_tmp5->info;
#line 1531
  __cil_tmp7 = (unsigned char *)__cil_tmp6;
#line 1531
  __cil_tmp8 = __cil_tmp7 + 3UL;
#line 1531
  __cil_tmp9 = *__cil_tmp8;
#line 1531
  __cil_tmp10 = (unsigned int )__cil_tmp9;
#line 1531
  if (__cil_tmp10 == 0U) {
    {
#line 1532
    __cil_tmp11 = (void *)regs;
#line 1532
    io_mapping_unmap_atomic(__cil_tmp11);
    }
  } else {

  }
  }
#line 1533
  return;
}
}
#line 1537 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev ) 
{ drm_i915_private_t *dev_priv ;
  struct intel_overlay *overlay ;
  struct intel_overlay_error_state *error ;
  struct overlay_registers *regs ;
  void *tmp ;
  void *__cil_tmp7 ;
  struct intel_overlay *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  int __cil_tmp11 ;
  struct intel_overlay_error_state *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  struct drm_device *__cil_tmp15 ;
  void *__cil_tmp16 ;
  struct drm_i915_private *__cil_tmp17 ;
  struct intel_device_info  const  *__cil_tmp18 ;
  unsigned char *__cil_tmp19 ;
  unsigned char *__cil_tmp20 ;
  unsigned char __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  struct drm_i915_gem_object *__cil_tmp23 ;
  struct drm_i915_gem_phys_object *__cil_tmp24 ;
  drm_dma_handle_t *__cil_tmp25 ;
  void *__cil_tmp26 ;
  struct drm_i915_gem_object *__cil_tmp27 ;
  uint32_t __cil_tmp28 ;
  struct overlay_registers *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  unsigned long __cil_tmp31 ;
  struct overlay_registers *__cil_tmp32 ;
  void *__cil_tmp33 ;
  void const volatile   *__cil_tmp34 ;
  void const   *__cil_tmp35 ;

  {
#line 1539
  __cil_tmp7 = dev->dev_private;
#line 1539
  dev_priv = (drm_i915_private_t *)__cil_tmp7;
#line 1540
  overlay = dev_priv->overlay;
  {
#line 1544
  __cil_tmp8 = (struct intel_overlay *)0;
#line 1544
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 1544
  __cil_tmp10 = (unsigned long )overlay;
#line 1544
  if (__cil_tmp10 == __cil_tmp9) {
#line 1545
    return ((struct intel_overlay_error_state *)0);
  } else {
    {
#line 1544
    __cil_tmp11 = overlay->active;
#line 1544
    if (__cil_tmp11 == 0) {
#line 1545
      return ((struct intel_overlay_error_state *)0);
    } else {

    }
    }
  }
  }
  {
#line 1547
  tmp = kmalloc(1808UL, 32U);
#line 1547
  error = (struct intel_overlay_error_state *)tmp;
  }
  {
#line 1548
  __cil_tmp12 = (struct intel_overlay_error_state *)0;
#line 1548
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 1548
  __cil_tmp14 = (unsigned long )error;
#line 1548
  if (__cil_tmp14 == __cil_tmp13) {
#line 1549
    return ((struct intel_overlay_error_state *)0);
  } else {

  }
  }
  {
#line 1551
  error->dovsta = i915_read32(dev_priv, 196616U);
#line 1552
  error->isr = i915_read32(dev_priv, 8364U);
  }
  {
#line 1553
  __cil_tmp15 = overlay->dev;
#line 1553
  __cil_tmp16 = __cil_tmp15->dev_private;
#line 1553
  __cil_tmp17 = (struct drm_i915_private *)__cil_tmp16;
#line 1553
  __cil_tmp18 = __cil_tmp17->info;
#line 1553
  __cil_tmp19 = (unsigned char *)__cil_tmp18;
#line 1553
  __cil_tmp20 = __cil_tmp19 + 3UL;
#line 1553
  __cil_tmp21 = *__cil_tmp20;
#line 1553
  __cil_tmp22 = (unsigned int )__cil_tmp21;
#line 1553
  if (__cil_tmp22 != 0U) {
#line 1554
    __cil_tmp23 = overlay->reg_bo;
#line 1554
    __cil_tmp24 = __cil_tmp23->phys_obj;
#line 1554
    __cil_tmp25 = __cil_tmp24->handle;
#line 1554
    __cil_tmp26 = __cil_tmp25->vaddr;
#line 1554
    error->base = (unsigned long )__cil_tmp26;
  } else {
#line 1556
    __cil_tmp27 = overlay->reg_bo;
#line 1556
    __cil_tmp28 = __cil_tmp27->gtt_offset;
#line 1556
    error->base = (unsigned long )__cil_tmp28;
  }
  }
  {
#line 1558
  regs = intel_overlay_map_regs_atomic(overlay);
  }
  {
#line 1559
  __cil_tmp29 = (struct overlay_registers *)0;
#line 1559
  __cil_tmp30 = (unsigned long )__cil_tmp29;
#line 1559
  __cil_tmp31 = (unsigned long )regs;
#line 1559
  if (__cil_tmp31 == __cil_tmp30) {
#line 1560
    goto err;
  } else {

  }
  }
  {
#line 1562
  __cil_tmp32 = & error->regs;
#line 1562
  __cil_tmp33 = (void *)__cil_tmp32;
#line 1562
  __cil_tmp34 = (void const volatile   *)regs;
#line 1562
  memcpy_fromio(__cil_tmp33, __cil_tmp34, 1792UL);
#line 1563
  intel_overlay_unmap_regs_atomic(overlay, regs);
  }
#line 1565
  return (error);
  err: 
  {
#line 1568
  __cil_tmp35 = (void const   *)error;
#line 1568
  kfree(__cil_tmp35);
  }
#line 1569
  return ((struct intel_overlay_error_state *)0);
}
}
#line 1573 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_overlay.c.p"
void intel_overlay_print_error_state(struct seq_file *m , struct intel_overlay_error_state *error ) 
{ u32 __cil_tmp3 ;
  u32 __cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  u32 __cil_tmp6 ;
  u32 __cil_tmp7 ;
  u32 __cil_tmp8 ;
  u32 __cil_tmp9 ;
  u32 __cil_tmp10 ;
  u32 __cil_tmp11 ;
  u32 __cil_tmp12 ;
  u32 __cil_tmp13 ;
  u32 __cil_tmp14 ;
  u32 __cil_tmp15 ;
  u32 __cil_tmp16 ;
  u32 __cil_tmp17 ;
  u32 __cil_tmp18 ;
  u32 __cil_tmp19 ;
  u32 __cil_tmp20 ;
  u32 __cil_tmp21 ;
  u32 __cil_tmp22 ;
  u32 __cil_tmp23 ;
  u32 __cil_tmp24 ;
  u32 __cil_tmp25 ;
  u32 __cil_tmp26 ;
  u32 __cil_tmp27 ;
  u32 __cil_tmp28 ;
  u32 __cil_tmp29 ;
  u32 __cil_tmp30 ;
  u32 __cil_tmp31 ;
  u32 __cil_tmp32 ;
  u32 __cil_tmp33 ;
  u32 __cil_tmp34 ;
  u32 __cil_tmp35 ;
  u32 __cil_tmp36 ;
  u32 __cil_tmp37 ;
  u32 __cil_tmp38 ;
  u32 __cil_tmp39 ;
  u32 __cil_tmp40 ;
  u32 __cil_tmp41 ;
  u32 __cil_tmp42 ;
  u32 __cil_tmp43 ;
  u32 __cil_tmp44 ;
  u32 __cil_tmp45 ;
  u32 __cil_tmp46 ;

  {
  {
#line 1575
  __cil_tmp3 = error->dovsta;
#line 1575
  __cil_tmp4 = error->isr;
#line 1575
  seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", __cil_tmp3, __cil_tmp4);
#line 1577
  __cil_tmp5 = error->base;
#line 1577
  seq_printf(m, "  Register file at 0x%08lx:\n", __cil_tmp5);
#line 1581
  __cil_tmp6 = error->regs.OBUF_0Y;
#line 1581
  seq_printf(m, "    OBUF_0Y:\t0x%08x\n", __cil_tmp6);
#line 1582
  __cil_tmp7 = error->regs.OBUF_1Y;
#line 1582
  seq_printf(m, "    OBUF_1Y:\t0x%08x\n", __cil_tmp7);
#line 1583
  __cil_tmp8 = error->regs.OBUF_0U;
#line 1583
  seq_printf(m, "    OBUF_0U:\t0x%08x\n", __cil_tmp8);
#line 1584
  __cil_tmp9 = error->regs.OBUF_0V;
#line 1584
  seq_printf(m, "    OBUF_0V:\t0x%08x\n", __cil_tmp9);
#line 1585
  __cil_tmp10 = error->regs.OBUF_1U;
#line 1585
  seq_printf(m, "    OBUF_1U:\t0x%08x\n", __cil_tmp10);
#line 1586
  __cil_tmp11 = error->regs.OBUF_1V;
#line 1586
  seq_printf(m, "    OBUF_1V:\t0x%08x\n", __cil_tmp11);
#line 1587
  __cil_tmp12 = error->regs.OSTRIDE;
#line 1587
  seq_printf(m, "    OSTRIDE:\t0x%08x\n", __cil_tmp12);
#line 1588
  __cil_tmp13 = error->regs.YRGB_VPH;
#line 1588
  seq_printf(m, "    YRGB_VPH:\t0x%08x\n", __cil_tmp13);
#line 1589
  __cil_tmp14 = error->regs.UV_VPH;
#line 1589
  seq_printf(m, "    UV_VPH:\t0x%08x\n", __cil_tmp14);
#line 1590
  __cil_tmp15 = error->regs.HORZ_PH;
#line 1590
  seq_printf(m, "    HORZ_PH:\t0x%08x\n", __cil_tmp15);
#line 1591
  __cil_tmp16 = error->regs.INIT_PHS;
#line 1591
  seq_printf(m, "    INIT_PHS:\t0x%08x\n", __cil_tmp16);
#line 1592
  __cil_tmp17 = error->regs.DWINPOS;
#line 1592
  seq_printf(m, "    DWINPOS:\t0x%08x\n", __cil_tmp17);
#line 1593
  __cil_tmp18 = error->regs.DWINSZ;
#line 1593
  seq_printf(m, "    DWINSZ:\t0x%08x\n", __cil_tmp18);
#line 1594
  __cil_tmp19 = error->regs.SWIDTH;
#line 1594
  seq_printf(m, "    SWIDTH:\t0x%08x\n", __cil_tmp19);
#line 1595
  __cil_tmp20 = error->regs.SWIDTHSW;
#line 1595
  seq_printf(m, "    SWIDTHSW:\t0x%08x\n", __cil_tmp20);
#line 1596
  __cil_tmp21 = error->regs.SHEIGHT;
#line 1596
  seq_printf(m, "    SHEIGHT:\t0x%08x\n", __cil_tmp21);
#line 1597
  __cil_tmp22 = error->regs.YRGBSCALE;
#line 1597
  seq_printf(m, "    YRGBSCALE:\t0x%08x\n", __cil_tmp22);
#line 1598
  __cil_tmp23 = error->regs.UVSCALE;
#line 1598
  seq_printf(m, "    UVSCALE:\t0x%08x\n", __cil_tmp23);
#line 1599
  __cil_tmp24 = error->regs.OCLRC0;
#line 1599
  seq_printf(m, "    OCLRC0:\t0x%08x\n", __cil_tmp24);
#line 1600
  __cil_tmp25 = error->regs.OCLRC1;
#line 1600
  seq_printf(m, "    OCLRC1:\t0x%08x\n", __cil_tmp25);
#line 1601
  __cil_tmp26 = error->regs.DCLRKV;
#line 1601
  seq_printf(m, "    DCLRKV:\t0x%08x\n", __cil_tmp26);
#line 1602
  __cil_tmp27 = error->regs.DCLRKM;
#line 1602
  seq_printf(m, "    DCLRKM:\t0x%08x\n", __cil_tmp27);
#line 1603
  __cil_tmp28 = error->regs.SCLRKVH;
#line 1603
  seq_printf(m, "    SCLRKVH:\t0x%08x\n", __cil_tmp28);
#line 1604
  __cil_tmp29 = error->regs.SCLRKVL;
#line 1604
  seq_printf(m, "    SCLRKVL:\t0x%08x\n", __cil_tmp29);
#line 1605
  __cil_tmp30 = error->regs.SCLRKEN;
#line 1605
  seq_printf(m, "    SCLRKEN:\t0x%08x\n", __cil_tmp30);
#line 1606
  __cil_tmp31 = error->regs.OCONFIG;
#line 1606
  seq_printf(m, "    OCONFIG:\t0x%08x\n", __cil_tmp31);
#line 1607
  __cil_tmp32 = error->regs.OCMD;
#line 1607
  seq_printf(m, "    OCMD:\t0x%08x\n", __cil_tmp32);
#line 1608
  __cil_tmp33 = error->regs.OSTART_0Y;
#line 1608
  seq_printf(m, "    OSTART_0Y:\t0x%08x\n", __cil_tmp33);
#line 1609
  __cil_tmp34 = error->regs.OSTART_1Y;
#line 1609
  seq_printf(m, "    OSTART_1Y:\t0x%08x\n", __cil_tmp34);
#line 1610
  __cil_tmp35 = error->regs.OSTART_0U;
#line 1610
  seq_printf(m, "    OSTART_0U:\t0x%08x\n", __cil_tmp35);
#line 1611
  __cil_tmp36 = error->regs.OSTART_0V;
#line 1611
  seq_printf(m, "    OSTART_0V:\t0x%08x\n", __cil_tmp36);
#line 1612
  __cil_tmp37 = error->regs.OSTART_1U;
#line 1612
  seq_printf(m, "    OSTART_1U:\t0x%08x\n", __cil_tmp37);
#line 1613
  __cil_tmp38 = error->regs.OSTART_1V;
#line 1613
  seq_printf(m, "    OSTART_1V:\t0x%08x\n", __cil_tmp38);
#line 1614
  __cil_tmp39 = error->regs.OTILEOFF_0Y;
#line 1614
  seq_printf(m, "    OTILEOFF_0Y:\t0x%08x\n", __cil_tmp39);
#line 1615
  __cil_tmp40 = error->regs.OTILEOFF_1Y;
#line 1615
  seq_printf(m, "    OTILEOFF_1Y:\t0x%08x\n", __cil_tmp40);
#line 1616
  __cil_tmp41 = error->regs.OTILEOFF_0U;
#line 1616
  seq_printf(m, "    OTILEOFF_0U:\t0x%08x\n", __cil_tmp41);
#line 1617
  __cil_tmp42 = error->regs.OTILEOFF_0V;
#line 1617
  seq_printf(m, "    OTILEOFF_0V:\t0x%08x\n", __cil_tmp42);
#line 1618
  __cil_tmp43 = error->regs.OTILEOFF_1U;
#line 1618
  seq_printf(m, "    OTILEOFF_1U:\t0x%08x\n", __cil_tmp43);
#line 1619
  __cil_tmp44 = error->regs.OTILEOFF_1V;
#line 1619
  seq_printf(m, "    OTILEOFF_1V:\t0x%08x\n", __cil_tmp44);
#line 1620
  __cil_tmp45 = error->regs.FASTHSCALE;
#line 1620
  seq_printf(m, "    FASTHSCALE:\t0x%08x\n", __cil_tmp45);
#line 1621
  __cil_tmp46 = error->regs.UVSCALEV;
#line 1621
  seq_printf(m, "    UVSCALEV:\t0x%08x\n", __cil_tmp46);
  }
#line 1622
  return;
}
}
#line 177 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/arch/x86/include/asm/io.h"
extern void *ioremap_cache(resource_size_t  , unsigned long  ) ;
#line 788 "include/linux/device.h"
extern int dev_printk(char const   * , struct device  const  * , char const   *  , ...) ;
#line 45 "include/acpi/acpi_bus.h"
extern acpi_status acpi_evaluate_integer(acpi_handle  , acpi_string  , struct acpi_object_list * ,
                                         unsigned long long * ) ;
#line 308
extern int register_acpi_notifier(struct notifier_block * ) ;
#line 309
extern int unregister_acpi_notifier(struct notifier_block * ) ;
#line 317
extern int acpi_bus_get_device(acpi_handle  , struct acpi_device ** ) ;
#line 191 "include/linux/acpi.h"
extern long acpi_is_video_device(struct acpi_device * ) ;
#line 7 "include/linux/acpi_io.h"
__inline static void *acpi_os_ioremap(acpi_physical_address phys , acpi_size size ) 
{ void *tmp ;
  unsigned long __cil_tmp4 ;

  {
  {
#line 10
  __cil_tmp4 = (unsigned long )size;
#line 10
  tmp = ioremap_cache(phys, __cil_tmp4);
  }
#line 10
  return (tmp);
}
}
#line 411 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h"
__inline static void trace_i915_reg_rw___19(bool write , u32 reg , u64 val , int len ) 
{ struct tracepoint_func *it_func_ptr ;
  void *it_func ;
  void *__data ;
  struct tracepoint_func *_________p1 ;
  bool __warned ;
  int tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  struct jump_label_key *__cil_tmp13 ;
  struct tracepoint_func **__cil_tmp14 ;
  struct tracepoint_func * volatile  *__cil_tmp15 ;
  struct tracepoint_func * volatile  __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  struct tracepoint_func *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  void (*__cil_tmp22)(void * , bool  , u32  , u64  , int  ) ;
  int __cil_tmp23 ;
  bool __cil_tmp24 ;
  void *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  void *__cil_tmp27 ;
  unsigned long __cil_tmp28 ;

  {
  {
#line 387
  __cil_tmp13 = & __tracepoint_i915_reg_rw.key;
#line 387
  tmp___1 = static_branch(__cil_tmp13);
  }
#line 387
  if ((int )tmp___1) {
    {
#line 387
    rcu_read_lock_sched_notrace();
#line 387
    __cil_tmp14 = & __tracepoint_i915_reg_rw.funcs;
#line 387
    __cil_tmp15 = (struct tracepoint_func * volatile  *)__cil_tmp14;
#line 387
    __cil_tmp16 = *__cil_tmp15;
#line 387
    _________p1 = (struct tracepoint_func *)__cil_tmp16;
#line 387
    tmp = debug_lockdep_rcu_enabled();
    }
#line 387
    if (tmp != 0) {
#line 387
      if (! __warned) {
        {
#line 387
        tmp___0 = rcu_read_lock_sched_held();
        }
#line 387
        if (tmp___0 == 0) {
          {
#line 387
          __warned = (bool )1;
#line 387
          __cil_tmp17 = (int const   )411;
#line 387
          __cil_tmp18 = (int )__cil_tmp17;
#line 387
          lockdep_rcu_dereference("/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_trace.h",
                                  __cil_tmp18);
          }
        } else {

        }
      } else {

      }
    } else {

    }
#line 387
    it_func_ptr = _________p1;
    {
#line 387
    __cil_tmp19 = (struct tracepoint_func *)0;
#line 387
    __cil_tmp20 = (unsigned long )__cil_tmp19;
#line 387
    __cil_tmp21 = (unsigned long )it_func_ptr;
#line 387
    if (__cil_tmp21 != __cil_tmp20) {
      ldv_38929: 
      {
#line 387
      it_func = it_func_ptr->func;
#line 387
      __data = it_func_ptr->data;
#line 387
      __cil_tmp22 = (void (*)(void * , bool  , u32  , u64  , int  ))it_func;
#line 387
      __cil_tmp23 = (int )write;
#line 387
      __cil_tmp24 = (bool )__cil_tmp23;
#line 387
      (*__cil_tmp22)(__data, __cil_tmp24, reg, val, len);
#line 387
      it_func_ptr = it_func_ptr + 1;
      }
      {
#line 387
      __cil_tmp25 = (void *)0;
#line 387
      __cil_tmp26 = (unsigned long )__cil_tmp25;
#line 387
      __cil_tmp27 = it_func_ptr->func;
#line 387
      __cil_tmp28 = (unsigned long )__cil_tmp27;
#line 387
      if (__cil_tmp28 != __cil_tmp26) {
#line 388
        goto ldv_38929;
      } else {
#line 390
        goto ldv_38930;
      }
      }
      ldv_38930: ;
    } else {

    }
    }
    {
#line 387
    rcu_read_lock_sched_notrace();
    }
  } else {

  }
#line 389
  return;
}
}
#line 1361 "/anthill/stuff/tacas-comp/inst/current/envs/linux-3.0.1/linux-3.0.1/drivers/gpu/drm/i915/i915_drv.h"
__inline static u32 i915_read32___19(struct drm_i915_private *dev_priv , u32 reg ) 
{ u32 val ;
  struct intel_device_info  const  *__cil_tmp4 ;
  u8 __cil_tmp5 ;
  unsigned char __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  void *__cil_tmp9 ;
  void const volatile   *__cil_tmp10 ;
  void const volatile   *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  void *__cil_tmp13 ;
  void const volatile   *__cil_tmp14 ;
  void const volatile   *__cil_tmp15 ;
  unsigned long __cil_tmp16 ;
  void *__cil_tmp17 ;
  void const volatile   *__cil_tmp18 ;
  void const volatile   *__cil_tmp19 ;
  unsigned long __cil_tmp20 ;
  void *__cil_tmp21 ;
  void const volatile   *__cil_tmp22 ;
  void const volatile   *__cil_tmp23 ;
  bool __cil_tmp24 ;
  u64 __cil_tmp25 ;

  {
#line 1361
  val = 0U;
  {
#line 1361
  __cil_tmp4 = dev_priv->info;
#line 1361
  __cil_tmp5 = __cil_tmp4->gen;
#line 1361
  __cil_tmp6 = (unsigned char )__cil_tmp5;
#line 1361
  __cil_tmp7 = (unsigned int )__cil_tmp6;
#line 1361
  if (__cil_tmp7 > 5U) {
#line 1361
    if (reg <= 262143U) {
#line 1361
      if (reg != 41356U) {
        {
#line 1361
        gen6_gt_force_wake_get(dev_priv);
#line 1361
        __cil_tmp8 = (unsigned long )reg;
#line 1361
        __cil_tmp9 = dev_priv->regs;
#line 1361
        __cil_tmp10 = (void const volatile   *)__cil_tmp9;
#line 1361
        __cil_tmp11 = __cil_tmp10 + __cil_tmp8;
#line 1361
        val = readl(__cil_tmp11);
#line 1361
        gen6_gt_force_wake_put(dev_priv);
        }
      } else {
        {
#line 1361
        __cil_tmp12 = (unsigned long )reg;
#line 1361
        __cil_tmp13 = dev_priv->regs;
#line 1361
        __cil_tmp14 = (void const volatile   *)__cil_tmp13;
#line 1361
        __cil_tmp15 = __cil_tmp14 + __cil_tmp12;
#line 1361
        val = readl(__cil_tmp15);
        }
      }
    } else {
      {
#line 1361
      __cil_tmp16 = (unsigned long )reg;
#line 1361
      __cil_tmp17 = dev_priv->regs;
#line 1361
      __cil_tmp18 = (void const volatile   *)__cil_tmp17;
#line 1361
      __cil_tmp19 = __cil_tmp18 + __cil_tmp16;
#line 1361
      val = readl(__cil_tmp19);
      }
    }
  } else {
    {
#line 1361
    __cil_tmp20 = (unsigned long )reg;
#line 1361
    __cil_tmp21 = dev_priv->regs;
#line 1361
    __cil_tmp22 = (void const volatile   *)__cil_tmp21;
#line 1361
    __cil_tmp23 = __cil_tmp22 + __cil_tmp20;
#line 1361
    val = readl(__cil_tmp23);
    }
  }
  }
  {
#line 1361
  __cil_tmp24 = (bool )0;
#line 1361
  __cil_tmp25 = (u64 )val;
#line 1361
  trace_i915_reg_rw___19(__cil_tmp24, reg, __cil_tmp25, 4);
  }
#line 1361
  return (val);
}
}
#line 157 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static u32 asle_set_backlight(struct drm_device *dev , u32 bclp ) 
{ struct drm_i915_private *dev_priv ;
  struct opregion_asle *asle ;
  u32 max ;
  void *__cil_tmp6 ;
  int __cil_tmp7 ;
  u32 __cil_tmp8 ;
  u32 __cil_tmp9 ;
  u32 __cil_tmp10 ;
  u32 __cil_tmp11 ;

  {
#line 159
  __cil_tmp6 = dev->dev_private;
#line 159
  dev_priv = (struct drm_i915_private *)__cil_tmp6;
#line 160
  asle = dev_priv->opregion.asle;
  {
#line 163
  __cil_tmp7 = (int )bclp;
#line 163
  if (__cil_tmp7 >= 0) {
#line 164
    return (4096U);
  } else {

  }
  }
#line 166
  bclp = bclp & 2147483647U;
#line 167
  if (bclp > 255U) {
#line 168
    return (4096U);
  } else {

  }
  {
#line 170
  max = intel_panel_get_max_backlight(dev);
#line 171
  __cil_tmp8 = bclp * max;
#line 171
  __cil_tmp9 = __cil_tmp8 / 255U;
#line 171
  intel_panel_set_backlight(dev, __cil_tmp9);
#line 172
  __cil_tmp10 = bclp * 100U;
#line 172
  __cil_tmp11 = __cil_tmp10 / 255U;
#line 172
  asle->cblv = __cil_tmp11 | 2147483648U;
  }
#line 174
  return (0U);
}
}
#line 177 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static u32 asle_set_als_illum(struct drm_device *dev , u32 alsi ) 
{ 

  {
#line 181
  return (0U);
}
}
#line 184 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static u32 asle_set_pwm_freq(struct drm_device *dev , u32 pfmb ) 
{ struct drm_i915_private *dev_priv ;
  u32 blc_pwm_ctl ;
  u32 tmp ;
  u32 pwm ;
  void *__cil_tmp7 ;
  int __cil_tmp8 ;

  {
#line 186
  __cil_tmp7 = dev->dev_private;
#line 186
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
  {
#line 187
  __cil_tmp8 = (int )pfmb;
#line 187
  if (__cil_tmp8 < 0) {
    {
#line 188
    tmp = i915_read32___19(dev_priv, 397908U);
#line 188
    blc_pwm_ctl = tmp;
#line 189
    pwm = pfmb & 2147483136U;
#line 190
    blc_pwm_ctl = blc_pwm_ctl & 65535U;
#line 191
    pwm = pwm >> 9;
    }
  } else {

  }
  }
#line 194
  return (0U);
}
}
#line 197 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static u32 asle_set_pfit(struct drm_device *dev , u32 pfit ) 
{ int __cil_tmp3 ;

  {
  {
#line 201
  __cil_tmp3 = (int )pfit;
#line 201
  if (__cil_tmp3 >= 0) {
#line 202
    return (16384U);
  } else {

  }
  }
#line 203
  return (0U);
}
}
#line 206 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
void intel_opregion_asle_intr(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct opregion_asle *asle ;
  u32 asle_stat ;
  u32 asle_req ;
  u32 tmp ;
  u32 tmp___0 ;
  u32 tmp___1 ;
  u32 tmp___2 ;
  void *__cil_tmp10 ;
  struct opregion_asle *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  u32 __cil_tmp14 ;
  int __cil_tmp15 ;
  u32 __cil_tmp16 ;
  unsigned int __cil_tmp17 ;
  u32 __cil_tmp18 ;
  unsigned int __cil_tmp19 ;
  u32 __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  u32 __cil_tmp22 ;

  {
#line 208
  __cil_tmp10 = dev->dev_private;
#line 208
  dev_priv = (struct drm_i915_private *)__cil_tmp10;
#line 209
  asle = dev_priv->opregion.asle;
#line 210
  asle_stat = 0U;
  {
#line 213
  __cil_tmp11 = (struct opregion_asle *)0;
#line 213
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 213
  __cil_tmp13 = (unsigned long )asle;
#line 213
  if (__cil_tmp13 == __cil_tmp12) {
#line 214
    return;
  } else {

  }
  }
#line 216
  __cil_tmp14 = asle->aslc;
#line 216
  asle_req = __cil_tmp14 & 15U;
#line 218
  if (asle_req == 0U) {
    {
#line 219
    drm_ut_debug_printk(2U, "drm", "intel_opregion_asle_intr", "non asle set request??\n");
    }
#line 220
    return;
  } else {

  }
  {
#line 223
  __cil_tmp15 = (int )asle_req;
#line 223
  if (__cil_tmp15 & 1) {
    {
#line 224
    __cil_tmp16 = asle->alsi;
#line 224
    tmp = asle_set_als_illum(dev, __cil_tmp16);
#line 224
    asle_stat = tmp | asle_stat;
    }
  } else {

  }
  }
  {
#line 226
  __cil_tmp17 = asle_req & 2U;
#line 226
  if (__cil_tmp17 != 0U) {
    {
#line 227
    __cil_tmp18 = asle->bclp;
#line 227
    tmp___0 = asle_set_backlight(dev, __cil_tmp18);
#line 227
    asle_stat = tmp___0 | asle_stat;
    }
  } else {

  }
  }
  {
#line 229
  __cil_tmp19 = asle_req & 4U;
#line 229
  if (__cil_tmp19 != 0U) {
    {
#line 230
    __cil_tmp20 = asle->pfit;
#line 230
    tmp___1 = asle_set_pfit(dev, __cil_tmp20);
#line 230
    asle_stat = tmp___1 | asle_stat;
    }
  } else {

  }
  }
  {
#line 232
  __cil_tmp21 = asle_req & 8U;
#line 232
  if (__cil_tmp21 != 0U) {
    {
#line 233
    __cil_tmp22 = asle->pfmb;
#line 233
    tmp___2 = asle_set_pwm_freq(dev, __cil_tmp22);
#line 233
    asle_stat = tmp___2 | asle_stat;
    }
  } else {

  }
  }
#line 235
  asle->aslc = asle_stat;
#line 236
  return;
}
}
#line 239 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
void intel_opregion_gse_intr(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct opregion_asle *asle ;
  u32 asle_stat ;
  u32 asle_req ;
  u32 tmp ;
  void *__cil_tmp7 ;
  struct opregion_asle *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  u32 __cil_tmp11 ;
  int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  u32 __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;

  {
#line 241
  __cil_tmp7 = dev->dev_private;
#line 241
  dev_priv = (struct drm_i915_private *)__cil_tmp7;
#line 242
  asle = dev_priv->opregion.asle;
#line 243
  asle_stat = 0U;
  {
#line 246
  __cil_tmp8 = (struct opregion_asle *)0;
#line 246
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 246
  __cil_tmp10 = (unsigned long )asle;
#line 246
  if (__cil_tmp10 == __cil_tmp9) {
#line 247
    return;
  } else {

  }
  }
#line 249
  __cil_tmp11 = asle->aslc;
#line 249
  asle_req = __cil_tmp11 & 15U;
#line 251
  if (asle_req == 0U) {
    {
#line 252
    drm_ut_debug_printk(2U, "drm", "intel_opregion_gse_intr", "non asle set request??\n");
    }
#line 253
    return;
  } else {

  }
  {
#line 256
  __cil_tmp12 = (int )asle_req;
#line 256
  if (__cil_tmp12 & 1) {
    {
#line 257
    drm_ut_debug_printk(2U, "drm", "intel_opregion_gse_intr", "Illum is not supported\n");
#line 258
    asle_stat = asle_stat | 1024U;
    }
  } else {

  }
  }
  {
#line 261
  __cil_tmp13 = asle_req & 2U;
#line 261
  if (__cil_tmp13 != 0U) {
    {
#line 262
    __cil_tmp14 = asle->bclp;
#line 262
    tmp = asle_set_backlight(dev, __cil_tmp14);
#line 262
    asle_stat = tmp | asle_stat;
    }
  } else {

  }
  }
  {
#line 264
  __cil_tmp15 = asle_req & 4U;
#line 264
  if (__cil_tmp15 != 0U) {
    {
#line 265
    drm_ut_debug_printk(2U, "drm", "intel_opregion_gse_intr", "Pfit is not supported\n");
#line 266
    asle_stat = asle_stat | 16384U;
    }
  } else {

  }
  }
  {
#line 269
  __cil_tmp16 = asle_req & 8U;
#line 269
  if (__cil_tmp16 != 0U) {
    {
#line 270
    drm_ut_debug_printk(2U, "drm", "intel_opregion_gse_intr", "PWM freq is not supported\n");
#line 271
    asle_stat = asle_stat | 65536U;
    }
  } else {

  }
  }
#line 274
  asle->aslc = asle_stat;
#line 275
  return;
}
}
#line 281 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
void intel_opregion_enable_asle(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct opregion_asle *asle ;
  void *__cil_tmp4 ;
  struct opregion_asle *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  void *__cil_tmp8 ;
  struct drm_i915_private *__cil_tmp9 ;
  struct intel_device_info  const  *__cil_tmp10 ;
  unsigned char *__cil_tmp11 ;
  unsigned char *__cil_tmp12 ;
  unsigned char __cil_tmp13 ;
  unsigned int __cil_tmp14 ;

  {
#line 283
  __cil_tmp4 = dev->dev_private;
#line 283
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 284
  asle = dev_priv->opregion.asle;
  {
#line 286
  __cil_tmp5 = (struct opregion_asle *)0;
#line 286
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 286
  __cil_tmp7 = (unsigned long )asle;
#line 286
  if (__cil_tmp7 != __cil_tmp6) {
    {
#line 287
    __cil_tmp8 = dev->dev_private;
#line 287
    __cil_tmp9 = (struct drm_i915_private *)__cil_tmp8;
#line 287
    __cil_tmp10 = __cil_tmp9->info;
#line 287
    __cil_tmp11 = (unsigned char *)__cil_tmp10;
#line 287
    __cil_tmp12 = __cil_tmp11 + 1UL;
#line 287
    __cil_tmp13 = *__cil_tmp12;
#line 287
    __cil_tmp14 = (unsigned int )__cil_tmp13;
#line 287
    if (__cil_tmp14 != 0U) {
      {
#line 288
      intel_enable_asle(dev);
      }
    } else {

    }
    }
#line 290
    asle->tche = 15U;
#line 292
    asle->ardy = 1U;
  } else {

  }
  }
#line 294
  return;
}
}
#line 300 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static struct intel_opregion *system_opregion  ;
#line 302 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static int intel_opregion_video_event(struct notifier_block *nb , unsigned long val ,
                                      void *data ) 
{ struct opregion_acpi *acpi ;
  struct intel_opregion *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  unsigned long __cil_tmp7 ;

  {
  {
#line 314
  __cil_tmp5 = (struct intel_opregion *)0;
#line 314
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 314
  __cil_tmp7 = (unsigned long )system_opregion;
#line 314
  if (__cil_tmp7 == __cil_tmp6) {
#line 315
    return (0);
  } else {

  }
  }
#line 317
  acpi = system_opregion->acpi;
#line 318
  acpi->csts = 0U;
#line 320
  return (1);
}
}
#line 323 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static struct notifier_block intel_opregion_notifier  =    {& intel_opregion_video_event, (struct notifier_block *)0, 0};
#line 333 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
static void intel_didl_outputs(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_opregion *opregion ;
  struct drm_connector *connector ;
  acpi_handle handle ;
  struct acpi_device *acpi_dev ;
  struct acpi_device *acpi_cdev ;
  struct acpi_device *acpi_video_bus ;
  unsigned long long device_id ;
  acpi_status status ;
  int i ;
  int tmp ;
  struct list_head  const  *__mptr ;
  long tmp___0 ;
  struct list_head  const  *__mptr___0 ;
  long tmp___1 ;
  struct list_head  const  *__mptr___1 ;
  struct list_head  const  *__mptr___2 ;
  struct list_head  const  *__mptr___3 ;
  int output_type ;
  struct list_head  const  *__mptr___4 ;
  void *__cil_tmp22 ;
  struct pci_dev *__cil_tmp23 ;
  acpi_handle __cil_tmp24 ;
  unsigned long __cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  struct list_head *__cil_tmp27 ;
  struct acpi_device *__cil_tmp28 ;
  struct list_head *__cil_tmp29 ;
  struct acpi_device *__cil_tmp30 ;
  struct list_head *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  struct list_head *__cil_tmp33 ;
  unsigned long __cil_tmp34 ;
  struct acpi_device *__cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  unsigned long __cil_tmp37 ;
  struct list_head *__cil_tmp38 ;
  struct acpi_device *__cil_tmp39 ;
  struct pci_dev *__cil_tmp40 ;
  struct device *__cil_tmp41 ;
  struct device  const  *__cil_tmp42 ;
  acpi_handle __cil_tmp43 ;
  char *__cil_tmp44 ;
  struct acpi_object_list *__cil_tmp45 ;
  struct opregion_acpi *__cil_tmp46 ;
  unsigned int __cil_tmp47 ;
  struct list_head *__cil_tmp48 ;
  struct acpi_device *__cil_tmp49 ;
  struct list_head *__cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  struct list_head *__cil_tmp52 ;
  unsigned long __cil_tmp53 ;
  struct opregion_acpi *__cil_tmp54 ;
  struct list_head *__cil_tmp55 ;
  struct drm_connector *__cil_tmp56 ;
  struct pci_dev *__cil_tmp57 ;
  struct device *__cil_tmp58 ;
  struct device  const  *__cil_tmp59 ;
  int __cil_tmp60 ;
  int __cil_tmp61 ;
  int __cil_tmp62 ;
  int __cil_tmp63 ;
  int __cil_tmp64 ;
  int __cil_tmp65 ;
  int __cil_tmp66 ;
  int __cil_tmp67 ;
  int __cil_tmp68 ;
  int __cil_tmp69 ;
  int __cil_tmp70 ;
  int __cil_tmp71 ;
  struct opregion_acpi *__cil_tmp72 ;
  int __cil_tmp73 ;
  int __cil_tmp74 ;
  u32 __cil_tmp75 ;
  struct opregion_acpi *__cil_tmp76 ;
  u32 __cil_tmp77 ;
  struct list_head *__cil_tmp78 ;
  struct drm_connector *__cil_tmp79 ;
  struct list_head *__cil_tmp80 ;
  unsigned long __cil_tmp81 ;
  struct list_head *__cil_tmp82 ;
  unsigned long __cil_tmp83 ;

  {
#line 335
  __cil_tmp22 = dev->dev_private;
#line 335
  dev_priv = (struct drm_i915_private *)__cil_tmp22;
#line 336
  opregion = & dev_priv->opregion;
#line 339
  acpi_video_bus = (struct acpi_device *)0;
#line 342
  i = 0;
#line 344
  __cil_tmp23 = dev->pdev;
#line 344
  handle = __cil_tmp23->dev.archdata.acpi_handle;
  {
#line 345
  __cil_tmp24 = (acpi_handle )0;
#line 345
  __cil_tmp25 = (unsigned long )__cil_tmp24;
#line 345
  __cil_tmp26 = (unsigned long )handle;
#line 345
  if (__cil_tmp26 == __cil_tmp25) {
#line 346
    return;
  } else {
    {
#line 345
    tmp = acpi_bus_get_device(handle, & acpi_dev);
    }
#line 345
    if (tmp != 0) {
#line 346
      return;
    } else {

    }
  }
  }
  {
#line 348
  tmp___1 = acpi_is_video_device(acpi_dev);
  }
#line 348
  if (tmp___1 != 0L) {
#line 349
    acpi_video_bus = acpi_dev;
  } else {
#line 351
    __cil_tmp27 = acpi_dev->children.next;
#line 351
    __mptr = (struct list_head  const  *)__cil_tmp27;
#line 351
    __cil_tmp28 = (struct acpi_device *)__mptr;
#line 351
    acpi_cdev = __cil_tmp28 + 1152921504606846936UL;
#line 351
    goto ldv_40054;
    ldv_40053: 
    {
#line 352
    tmp___0 = acpi_is_video_device(acpi_cdev);
    }
#line 352
    if (tmp___0 != 0L) {
#line 353
      acpi_video_bus = acpi_cdev;
#line 354
      goto ldv_40052;
    } else {

    }
#line 351
    __cil_tmp29 = acpi_cdev->node.next;
#line 351
    __mptr___0 = (struct list_head  const  *)__cil_tmp29;
#line 351
    __cil_tmp30 = (struct acpi_device *)__mptr___0;
#line 351
    acpi_cdev = __cil_tmp30 + 1152921504606846936UL;
    ldv_40054: ;
    {
#line 351
    __cil_tmp31 = & acpi_dev->children;
#line 351
    __cil_tmp32 = (unsigned long )__cil_tmp31;
#line 351
    __cil_tmp33 = & acpi_cdev->node;
#line 351
    __cil_tmp34 = (unsigned long )__cil_tmp33;
#line 351
    if (__cil_tmp34 != __cil_tmp32) {
#line 352
      goto ldv_40053;
    } else {
#line 354
      goto ldv_40052;
    }
    }
    ldv_40052: ;
  }
  {
#line 359
  __cil_tmp35 = (struct acpi_device *)0;
#line 359
  __cil_tmp36 = (unsigned long )__cil_tmp35;
#line 359
  __cil_tmp37 = (unsigned long )acpi_video_bus;
#line 359
  if (__cil_tmp37 == __cil_tmp36) {
    {
#line 360
    printk("<4>No ACPI video bus found\n");
    }
#line 361
    return;
  } else {

  }
  }
#line 364
  __cil_tmp38 = acpi_video_bus->children.next;
#line 364
  __mptr___1 = (struct list_head  const  *)__cil_tmp38;
#line 364
  __cil_tmp39 = (struct acpi_device *)__mptr___1;
#line 364
  acpi_cdev = __cil_tmp39 + 1152921504606846936UL;
#line 364
  goto ldv_40061;
  ldv_40060: ;
#line 365
  if (i > 7) {
    {
#line 366
    __cil_tmp40 = dev->pdev;
#line 366
    __cil_tmp41 = & __cil_tmp40->dev;
#line 366
    __cil_tmp42 = (struct device  const  *)__cil_tmp41;
#line 366
    dev_printk("<3>", __cil_tmp42, "More than 8 outputs detected\n");
    }
#line 368
    return;
  } else {

  }
  {
#line 370
  __cil_tmp43 = acpi_cdev->handle;
#line 370
  __cil_tmp44 = (char *)"_ADR";
#line 370
  __cil_tmp45 = (struct acpi_object_list *)0;
#line 370
  status = acpi_evaluate_integer(__cil_tmp43, __cil_tmp44, __cil_tmp45, & device_id);
  }
#line 373
  if (status == 0U) {
#line 374
    if (device_id == 0ULL) {
#line 375
      goto blind_set;
    } else {

    }
#line 376
    __cil_tmp46 = opregion->acpi;
#line 376
    __cil_tmp47 = (unsigned int )device_id;
#line 376
    __cil_tmp46->didl[i] = __cil_tmp47 & 3855U;
#line 377
    i = i + 1;
  } else {

  }
#line 364
  __cil_tmp48 = acpi_cdev->node.next;
#line 364
  __mptr___2 = (struct list_head  const  *)__cil_tmp48;
#line 364
  __cil_tmp49 = (struct acpi_device *)__mptr___2;
#line 364
  acpi_cdev = __cil_tmp49 + 1152921504606846936UL;
  ldv_40061: ;
  {
#line 364
  __cil_tmp50 = & acpi_video_bus->children;
#line 364
  __cil_tmp51 = (unsigned long )__cil_tmp50;
#line 364
  __cil_tmp52 = & acpi_cdev->node;
#line 364
  __cil_tmp53 = (unsigned long )__cil_tmp52;
#line 364
  if (__cil_tmp53 != __cil_tmp51) {
#line 365
    goto ldv_40060;
  } else {
#line 367
    goto ldv_40062;
  }
  }
  ldv_40062: ;
  end: ;
#line 383
  if (i <= 7) {
#line 384
    __cil_tmp54 = opregion->acpi;
#line 384
    __cil_tmp54->didl[i] = 0U;
  } else {

  }
#line 385
  return;
  blind_set: 
#line 388
  i = 0;
#line 389
  __cil_tmp55 = dev->mode_config.connector_list.next;
#line 389
  __mptr___3 = (struct list_head  const  *)__cil_tmp55;
#line 389
  __cil_tmp56 = (struct drm_connector *)__mptr___3;
#line 389
  connector = __cil_tmp56 + 1152921504606845848UL;
#line 389
  goto ldv_40083;
  ldv_40082: 
#line 390
  output_type = 0;
#line 391
  if (i > 7) {
    {
#line 392
    __cil_tmp57 = dev->pdev;
#line 392
    __cil_tmp58 = & __cil_tmp57->dev;
#line 392
    __cil_tmp59 = (struct device  const  *)__cil_tmp58;
#line 392
    dev_printk("<3>", __cil_tmp59, "More than 8 outputs detected\n");
    }
#line 394
    return;
  } else {

  }
  {
#line 397
  __cil_tmp60 = connector->connector_type;
#line 397
  if (__cil_tmp60 == 1) {
#line 397
    goto case_1;
  } else {
    {
#line 398
    __cil_tmp61 = connector->connector_type;
#line 398
    if (__cil_tmp61 == 4) {
#line 398
      goto case_4;
    } else {
      {
#line 401
      __cil_tmp62 = connector->connector_type;
#line 401
      if (__cil_tmp62 == 5) {
#line 401
        goto case_5;
      } else {
        {
#line 402
        __cil_tmp63 = connector->connector_type;
#line 402
        if (__cil_tmp63 == 6) {
#line 402
          goto case_6;
        } else {
          {
#line 403
          __cil_tmp64 = connector->connector_type;
#line 403
          if (__cil_tmp64 == 8) {
#line 403
            goto case_8;
          } else {
            {
#line 404
            __cil_tmp65 = connector->connector_type;
#line 404
            if (__cil_tmp65 == 9) {
#line 404
              goto case_9;
            } else {
              {
#line 407
              __cil_tmp66 = connector->connector_type;
#line 407
              if (__cil_tmp66 == 2) {
#line 407
                goto case_2;
              } else {
                {
#line 408
                __cil_tmp67 = connector->connector_type;
#line 408
                if (__cil_tmp67 == 3) {
#line 408
                  goto case_3;
                } else {
                  {
#line 409
                  __cil_tmp68 = connector->connector_type;
#line 409
                  if (__cil_tmp68 == 10) {
#line 409
                    goto case_10;
                  } else {
                    {
#line 410
                    __cil_tmp69 = connector->connector_type;
#line 410
                    if (__cil_tmp69 == 11) {
#line 410
                      goto case_11;
                    } else {
                      {
#line 411
                      __cil_tmp70 = connector->connector_type;
#line 411
                      if (__cil_tmp70 == 12) {
#line 411
                        goto case_12;
                      } else {
                        {
#line 414
                        __cil_tmp71 = connector->connector_type;
#line 414
                        if (__cil_tmp71 == 7) {
#line 414
                          goto case_7;
                        } else
#line 396
                        if (0) {
                          case_1: ;
                          case_4: 
#line 399
                          output_type = 256;
#line 400
                          goto ldv_40071;
                          case_5: ;
                          case_6: ;
                          case_8: ;
                          case_9: 
#line 405
                          output_type = 512;
#line 406
                          goto ldv_40071;
                          case_2: ;
                          case_3: ;
                          case_10: ;
                          case_11: ;
                          case_12: 
#line 412
                          output_type = 768;
#line 413
                          goto ldv_40071;
                          case_7: 
#line 415
                          output_type = 1024;
#line 416
                          goto ldv_40071;
                        } else {

                        }
                        }
                      }
                      }
                    }
                    }
                  }
                  }
                }
                }
              }
              }
            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
  ldv_40071: 
#line 418
  __cil_tmp72 = opregion->acpi;
#line 418
  __cil_tmp73 = output_type | (-0x7FFFFFFF-1);
#line 418
  __cil_tmp74 = __cil_tmp73 | i;
#line 418
  __cil_tmp75 = (u32 )__cil_tmp74;
#line 418
  __cil_tmp76 = opregion->acpi;
#line 418
  __cil_tmp77 = __cil_tmp76->didl[i];
#line 418
  __cil_tmp72->didl[i] = __cil_tmp77 | __cil_tmp75;
#line 419
  i = i + 1;
#line 389
  __cil_tmp78 = connector->head.next;
#line 389
  __mptr___4 = (struct list_head  const  *)__cil_tmp78;
#line 389
  __cil_tmp79 = (struct drm_connector *)__mptr___4;
#line 389
  connector = __cil_tmp79 + 1152921504606845848UL;
  ldv_40083: ;
  {
#line 389
  __cil_tmp80 = & dev->mode_config.connector_list;
#line 389
  __cil_tmp81 = (unsigned long )__cil_tmp80;
#line 389
  __cil_tmp82 = & connector->head;
#line 389
  __cil_tmp83 = (unsigned long )__cil_tmp82;
#line 389
  if (__cil_tmp83 != __cil_tmp81) {
#line 390
    goto ldv_40082;
  } else {
#line 392
    goto ldv_40084;
  }
  }
  ldv_40084: ;
#line 421
  goto end;
}
}
#line 424 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
void intel_opregion_init(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_opregion *opregion ;
  int tmp ;
  void *__cil_tmp5 ;
  struct opregion_header *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  struct opregion_header *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  struct opregion_acpi *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  struct opregion_acpi *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  struct opregion_acpi *__cil_tmp14 ;
  struct opregion_acpi *__cil_tmp15 ;
  struct opregion_asle *__cil_tmp16 ;
  unsigned long __cil_tmp17 ;
  struct opregion_asle *__cil_tmp18 ;
  unsigned long __cil_tmp19 ;

  {
#line 426
  __cil_tmp5 = dev->dev_private;
#line 426
  dev_priv = (struct drm_i915_private *)__cil_tmp5;
#line 427
  opregion = & dev_priv->opregion;
  {
#line 429
  __cil_tmp6 = (struct opregion_header *)0;
#line 429
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 429
  __cil_tmp8 = opregion->header;
#line 429
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 429
  if (__cil_tmp9 == __cil_tmp7) {
#line 430
    return;
  } else {

  }
  }
  {
#line 432
  __cil_tmp10 = (struct opregion_acpi *)0;
#line 432
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 432
  __cil_tmp12 = opregion->acpi;
#line 432
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 432
  if (__cil_tmp13 != __cil_tmp11) {
    {
#line 433
    tmp = drm_core_check_feature(dev, 8192);
    }
#line 433
    if (tmp != 0) {
      {
#line 434
      intel_didl_outputs(dev);
      }
    } else {

    }
    {
#line 439
    __cil_tmp14 = opregion->acpi;
#line 439
    __cil_tmp14->csts = 0U;
#line 440
    __cil_tmp15 = opregion->acpi;
#line 440
    __cil_tmp15->drdy = 1U;
#line 442
    system_opregion = opregion;
#line 443
    register_acpi_notifier(& intel_opregion_notifier);
    }
  } else {

  }
  }
  {
#line 446
  __cil_tmp16 = (struct opregion_asle *)0;
#line 446
  __cil_tmp17 = (unsigned long )__cil_tmp16;
#line 446
  __cil_tmp18 = opregion->asle;
#line 446
  __cil_tmp19 = (unsigned long )__cil_tmp18;
#line 446
  if (__cil_tmp19 != __cil_tmp17) {
    {
#line 447
    intel_opregion_enable_asle(dev);
    }
  } else {

  }
  }
#line 448
  return;
}
}
#line 450 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
void intel_opregion_fini(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_opregion *opregion ;
  void *__cil_tmp4 ;
  struct opregion_header *__cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  struct opregion_header *__cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  struct opregion_acpi *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  struct opregion_acpi *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  struct opregion_acpi *__cil_tmp13 ;
  struct opregion_header *__cil_tmp14 ;
  void volatile   *__cil_tmp15 ;

  {
#line 452
  __cil_tmp4 = dev->dev_private;
#line 452
  dev_priv = (struct drm_i915_private *)__cil_tmp4;
#line 453
  opregion = & dev_priv->opregion;
  {
#line 455
  __cil_tmp5 = (struct opregion_header *)0;
#line 455
  __cil_tmp6 = (unsigned long )__cil_tmp5;
#line 455
  __cil_tmp7 = opregion->header;
#line 455
  __cil_tmp8 = (unsigned long )__cil_tmp7;
#line 455
  if (__cil_tmp8 == __cil_tmp6) {
#line 456
    return;
  } else {

  }
  }
  {
#line 458
  __cil_tmp9 = (struct opregion_acpi *)0;
#line 458
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 458
  __cil_tmp11 = opregion->acpi;
#line 458
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 458
  if (__cil_tmp12 != __cil_tmp10) {
    {
#line 459
    __cil_tmp13 = opregion->acpi;
#line 459
    __cil_tmp13->drdy = 0U;
#line 461
    system_opregion = (struct intel_opregion *)0;
#line 462
    unregister_acpi_notifier(& intel_opregion_notifier);
    }
  } else {

  }
  }
  {
#line 466
  __cil_tmp14 = opregion->header;
#line 466
  __cil_tmp15 = (void volatile   *)__cil_tmp14;
#line 466
  iounmap(__cil_tmp15);
#line 467
  opregion->header = (struct opregion_header *)0;
#line 468
  opregion->acpi = (struct opregion_acpi *)0;
#line 469
  opregion->swsci = (struct opregion_swsci *)0;
#line 470
  opregion->asle = (struct opregion_asle *)0;
#line 471
  opregion->vbt = (void *)0;
  }
#line 472
  return;
}
}
#line 475 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_opregion.c.p"
int intel_opregion_setup(struct drm_device *dev ) 
{ struct drm_i915_private *dev_priv ;
  struct intel_opregion *opregion ;
  void *base ;
  u32 asls ;
  u32 mboxes ;
  int err ;
  int tmp ;
  void *__cil_tmp9 ;
  struct pci_dev *__cil_tmp10 ;
  acpi_physical_address __cil_tmp11 ;
  void *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  void const   *__cil_tmp15 ;
  void const   *__cil_tmp16 ;
  u32 *__cil_tmp17 ;
  struct opregion_header *__cil_tmp18 ;
  int __cil_tmp19 ;
  struct opregion_acpi *__cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  struct opregion_swsci *__cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  struct opregion_asle *__cil_tmp24 ;
  void volatile   *__cil_tmp25 ;

  {
  {
#line 477
  __cil_tmp9 = dev->dev_private;
#line 477
  dev_priv = (struct drm_i915_private *)__cil_tmp9;
#line 478
  opregion = & dev_priv->opregion;
#line 481
  err = 0;
#line 483
  __cil_tmp10 = dev->pdev;
#line 483
  pci_read_config_dword(__cil_tmp10, 252, & asls);
#line 484
  drm_ut_debug_printk(2U, "drm", "intel_opregion_setup", "graphic opregion physical addr: 0x%x\n",
                      asls);
  }
#line 485
  if (asls == 0U) {
    {
#line 486
    drm_ut_debug_printk(2U, "drm", "intel_opregion_setup", "ACPI OpRegion not supported!\n");
    }
#line 487
    return (-524);
  } else {

  }
  {
#line 490
  __cil_tmp11 = (acpi_physical_address )asls;
#line 490
  base = acpi_os_ioremap(__cil_tmp11, 8192ULL);
  }
  {
#line 491
  __cil_tmp12 = (void *)0;
#line 491
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 491
  __cil_tmp14 = (unsigned long )base;
#line 491
  if (__cil_tmp14 == __cil_tmp13) {
#line 492
    return (-12);
  } else {

  }
  }
  {
#line 494
  __cil_tmp15 = (void const   *)base;
#line 494
  __cil_tmp16 = (void const   *)"IntelGraphicsMem";
#line 494
  tmp = memcmp(__cil_tmp15, __cil_tmp16, 16UL);
  }
#line 494
  if (tmp != 0) {
    {
#line 495
    drm_ut_debug_printk(2U, "drm", "intel_opregion_setup", "opregion signature mismatch\n");
#line 496
    err = -22;
    }
#line 497
    goto err_out;
  } else {

  }
#line 499
  opregion->header = (struct opregion_header *)base;
#line 500
  opregion->vbt = base + 1024UL;
#line 502
  __cil_tmp17 = (u32 *)base;
#line 502
  opregion->lid_state = __cil_tmp17 + 428U;
#line 504
  __cil_tmp18 = opregion->header;
#line 504
  mboxes = __cil_tmp18->mboxes;
  {
#line 505
  __cil_tmp19 = (int )mboxes;
#line 505
  if (__cil_tmp19 & 1) {
    {
#line 506
    drm_ut_debug_printk(2U, "drm", "intel_opregion_setup", "Public ACPI methods supported\n");
#line 507
    __cil_tmp20 = (struct opregion_acpi *)base;
#line 507
    opregion->acpi = __cil_tmp20 + 256U;
    }
  } else {

  }
  }
  {
#line 510
  __cil_tmp21 = mboxes & 2U;
#line 510
  if (__cil_tmp21 != 0U) {
    {
#line 511
    drm_ut_debug_printk(2U, "drm", "intel_opregion_setup", "SWSCI supported\n");
#line 512
    __cil_tmp22 = (struct opregion_swsci *)base;
#line 512
    opregion->swsci = __cil_tmp22 + 512U;
    }
  } else {

  }
  }
  {
#line 514
  __cil_tmp23 = mboxes & 4U;
#line 514
  if (__cil_tmp23 != 0U) {
    {
#line 515
    drm_ut_debug_printk(2U, "drm", "intel_opregion_setup", "ASLE supported\n");
#line 516
    __cil_tmp24 = (struct opregion_asle *)base;
#line 516
    opregion->asle = __cil_tmp24 + 768U;
    }
  } else {

  }
  }
#line 519
  return (0);
  err_out: 
  {
#line 522
  __cil_tmp25 = (void volatile   *)base;
#line 522
  iounmap(__cil_tmp25);
  }
#line 523
  return (err);
}
}
#line 96 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static struct ch7xxx_id_struct ch7xxx_ids[4U]  = {      {(uint8_t )131U, (char *)"CH7011"}, 
        {(uint8_t )132U, (char *)"CH7009A"}, 
        {(uint8_t )133U, (char *)"CH7009B"}, 
        {(uint8_t )149U, (char *)"CH7301"}};
#line 107 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static char *ch7xxx_get_id(uint8_t vid ) 
{ int i ;
  int __cil_tmp3 ;
  int __cil_tmp4 ;
  unsigned int __cil_tmp5 ;

  {
#line 111
  i = 0;
#line 111
  goto ldv_37325;
  ldv_37324: ;
  {
#line 112
  __cil_tmp3 = (int )vid;
#line 112
  __cil_tmp4 = (int )ch7xxx_ids[i].vid;
#line 112
  if (__cil_tmp4 == __cil_tmp3) {
#line 113
    return (ch7xxx_ids[i].name);
  } else {

  }
  }
#line 111
  i = i + 1;
  ldv_37325: ;
  {
#line 111
  __cil_tmp5 = (unsigned int )i;
#line 111
  if (__cil_tmp5 <= 3U) {
#line 112
    goto ldv_37324;
  } else {
#line 114
    goto ldv_37326;
  }
  }
  ldv_37326: ;
#line 116
  return ((char *)0);
}
}
#line 120 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static bool ch7xxx_readb(struct intel_dvo_device *dvo , int addr , uint8_t *ch ) 
{ struct ch7xxx_priv *ch7xxx ;
  struct i2c_adapter *adapter ;
  u8 out_buf[2U] ;
  u8 in_buf[2U] ;
  struct i2c_msg msgs[2U] ;
  int tmp ;
  void *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  struct i2c_msg *__cil_tmp13 ;
  bool __cil_tmp14 ;
  char (*__cil_tmp15)[48U] ;
  char *__cil_tmp16 ;
  int __cil_tmp17 ;

  {
  {
#line 122
  __cil_tmp10 = dvo->dev_priv;
#line 122
  ch7xxx = (struct ch7xxx_priv *)__cil_tmp10;
#line 123
  adapter = dvo->i2c_bus;
#line 127
  __cil_tmp11 = dvo->slave_addr;
#line 127
  msgs[0].addr = (unsigned short )__cil_tmp11;
#line 127
  msgs[0].flags = (__u16 )0U;
#line 127
  msgs[0].len = (__u16 )1U;
#line 127
  msgs[0].buf = (__u8 *)(& out_buf);
#line 127
  __cil_tmp12 = dvo->slave_addr;
#line 127
  msgs[1].addr = (unsigned short )__cil_tmp12;
#line 127
  msgs[1].flags = (__u16 )1U;
#line 127
  msgs[1].len = (__u16 )1U;
#line 127
  msgs[1].buf = (__u8 *)(& in_buf);
#line 142
  out_buf[0] = (u8 )addr;
#line 143
  out_buf[1] = (u8 )0U;
#line 145
  __cil_tmp13 = (struct i2c_msg *)(& msgs);
#line 145
  tmp = i2c_transfer(adapter, __cil_tmp13, 2);
  }
#line 145
  if (tmp == 2) {
#line 146
    *ch = in_buf[0];
#line 147
    return ((bool )1);
  } else {

  }
  {
#line 150
  __cil_tmp14 = ch7xxx->quiet;
#line 150
  if (! __cil_tmp14) {
    {
#line 151
    __cil_tmp15 = & adapter->name;
#line 151
    __cil_tmp16 = (char *)__cil_tmp15;
#line 151
    __cil_tmp17 = dvo->slave_addr;
#line 151
    drm_ut_debug_printk(4U, "drm", "ch7xxx_readb", "Unable to read register 0x%02x from %s:%02x.\n",
                        addr, __cil_tmp16, __cil_tmp17);
    }
  } else {

  }
  }
#line 154
  return ((bool )0);
}
}
#line 158 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static bool ch7xxx_writeb(struct intel_dvo_device *dvo , int addr , uint8_t ch ) 
{ struct ch7xxx_priv *ch7xxx ;
  struct i2c_adapter *adapter ;
  uint8_t out_buf[2U] ;
  struct i2c_msg msg ;
  int tmp ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  bool __cil_tmp11 ;
  char (*__cil_tmp12)[48U] ;
  char *__cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 160
  __cil_tmp9 = dvo->dev_priv;
#line 160
  ch7xxx = (struct ch7xxx_priv *)__cil_tmp9;
#line 161
  adapter = dvo->i2c_bus;
#line 163
  __cil_tmp10 = dvo->slave_addr;
#line 163
  msg.addr = (unsigned short )__cil_tmp10;
#line 163
  msg.flags = (__u16 )0U;
#line 163
  msg.len = (__u16 )2U;
#line 163
  msg.buf = (__u8 *)(& out_buf);
#line 170
  out_buf[0] = (uint8_t )addr;
#line 171
  out_buf[1] = ch;
#line 173
  tmp = i2c_transfer(adapter, & msg, 1);
  }
#line 173
  if (tmp == 1) {
#line 174
    return ((bool )1);
  } else {

  }
  {
#line 176
  __cil_tmp11 = ch7xxx->quiet;
#line 176
  if (! __cil_tmp11) {
    {
#line 177
    __cil_tmp12 = & adapter->name;
#line 177
    __cil_tmp13 = (char *)__cil_tmp12;
#line 177
    __cil_tmp14 = dvo->slave_addr;
#line 177
    drm_ut_debug_printk(4U, "drm", "ch7xxx_writeb", "Unable to write register 0x%02x to %s:%d.\n",
                        addr, __cil_tmp13, __cil_tmp14);
    }
  } else {

  }
  }
#line 181
  return ((bool )0);
}
}
#line 184 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static bool ch7xxx_init(struct intel_dvo_device *dvo , struct i2c_adapter *adapter ) 
{ struct ch7xxx_priv *ch7xxx ;
  uint8_t vendor ;
  uint8_t device ;
  char *name ;
  void *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  struct ch7xxx_priv *__cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  unsigned long __cil_tmp14 ;
  int __cil_tmp15 ;
  uint8_t __cil_tmp16 ;
  char *__cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  int __cil_tmp20 ;
  char (*__cil_tmp21)[48U] ;
  char *__cil_tmp22 ;
  int __cil_tmp23 ;
  unsigned int __cil_tmp24 ;
  int __cil_tmp25 ;
  char (*__cil_tmp26)[48U] ;
  char *__cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  void const   *__cil_tmp31 ;

  {
  {
#line 192
  tmp = kzalloc(1UL, 208U);
#line 192
  ch7xxx = (struct ch7xxx_priv *)tmp;
  }
  {
#line 193
  __cil_tmp12 = (struct ch7xxx_priv *)0;
#line 193
  __cil_tmp13 = (unsigned long )__cil_tmp12;
#line 193
  __cil_tmp14 = (unsigned long )ch7xxx;
#line 193
  if (__cil_tmp14 == __cil_tmp13) {
#line 194
    return ((bool )0);
  } else {

  }
  }
  {
#line 196
  dvo->i2c_bus = adapter;
#line 197
  dvo->dev_priv = (void *)ch7xxx;
#line 198
  ch7xxx->quiet = (bool )1;
#line 200
  tmp___0 = ch7xxx_readb(dvo, 74, & vendor);
  }
#line 200
  if (tmp___0) {
#line 200
    tmp___1 = 0;
  } else {
#line 200
    tmp___1 = 1;
  }
#line 200
  if (tmp___1) {
#line 201
    goto out;
  } else {

  }
  {
#line 203
  __cil_tmp15 = (int )vendor;
#line 203
  __cil_tmp16 = (uint8_t )__cil_tmp15;
#line 203
  name = ch7xxx_get_id(__cil_tmp16);
  }
  {
#line 204
  __cil_tmp17 = (char *)0;
#line 204
  __cil_tmp18 = (unsigned long )__cil_tmp17;
#line 204
  __cil_tmp19 = (unsigned long )name;
#line 204
  if (__cil_tmp19 == __cil_tmp18) {
    {
#line 205
    __cil_tmp20 = (int )vendor;
#line 205
    __cil_tmp21 = & adapter->name;
#line 205
    __cil_tmp22 = (char *)__cil_tmp21;
#line 205
    __cil_tmp23 = dvo->slave_addr;
#line 205
    drm_ut_debug_printk(4U, "drm", "ch7xxx_init", "ch7xxx not detected; got 0x%02x from %s slave %d.\n",
                        __cil_tmp20, __cil_tmp22, __cil_tmp23);
    }
#line 208
    goto out;
  } else {

  }
  }
  {
#line 212
  tmp___2 = ch7xxx_readb(dvo, 75, & device);
  }
#line 212
  if (tmp___2) {
#line 212
    tmp___3 = 0;
  } else {
#line 212
    tmp___3 = 1;
  }
#line 212
  if (tmp___3) {
#line 213
    goto out;
  } else {

  }
  {
#line 215
  __cil_tmp24 = (unsigned int )device;
#line 215
  if (__cil_tmp24 != 23U) {
    {
#line 216
    __cil_tmp25 = (int )vendor;
#line 216
    __cil_tmp26 = & adapter->name;
#line 216
    __cil_tmp27 = (char *)__cil_tmp26;
#line 216
    __cil_tmp28 = dvo->slave_addr;
#line 216
    drm_ut_debug_printk(4U, "drm", "ch7xxx_init", "ch7xxx not detected; got 0x%02x from %s slave %d.\n",
                        __cil_tmp25, __cil_tmp27, __cil_tmp28);
    }
#line 219
    goto out;
  } else {

  }
  }
  {
#line 222
  ch7xxx->quiet = (bool )0;
#line 223
  __cil_tmp29 = (int )vendor;
#line 223
  __cil_tmp30 = (int )device;
#line 223
  drm_ut_debug_printk(4U, "drm", "ch7xxx_init", "Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
                      name, __cil_tmp29, __cil_tmp30);
  }
#line 225
  return ((bool )1);
  out: 
  {
#line 227
  __cil_tmp31 = (void const   *)ch7xxx;
#line 227
  kfree(__cil_tmp31);
  }
#line 228
  return ((bool )0);
}
}
#line 231 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo ) 
{ uint8_t cdet ;
  uint8_t orig_pm ;
  uint8_t pm ;
  unsigned int __cil_tmp5 ;
  unsigned int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  int __cil_tmp9 ;
  uint8_t __cil_tmp10 ;
  int __cil_tmp11 ;
  uint8_t __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 235
  ch7xxx_readb(dvo, 73, & orig_pm);
#line 237
  pm = orig_pm;
#line 238
  __cil_tmp5 = (unsigned int )pm;
#line 238
  __cil_tmp6 = __cil_tmp5 & 254U;
#line 238
  pm = (uint8_t )__cil_tmp6;
#line 239
  __cil_tmp7 = (unsigned int )pm;
#line 239
  __cil_tmp8 = __cil_tmp7 | 192U;
#line 239
  pm = (uint8_t )__cil_tmp8;
#line 241
  __cil_tmp9 = (int )pm;
#line 241
  __cil_tmp10 = (uint8_t )__cil_tmp9;
#line 241
  ch7xxx_writeb(dvo, 73, __cil_tmp10);
#line 243
  ch7xxx_readb(dvo, 32, & cdet);
#line 245
  __cil_tmp11 = (int )orig_pm;
#line 245
  __cil_tmp12 = (uint8_t )__cil_tmp11;
#line 245
  ch7xxx_writeb(dvo, 73, __cil_tmp12);
  }
  {
#line 247
  __cil_tmp13 = (int )cdet;
#line 247
  __cil_tmp14 = __cil_tmp13 & 32;
#line 247
  if (__cil_tmp14 != 0) {
#line 248
    return ((enum drm_connector_status )1);
  } else {

  }
  }
#line 249
  return ((enum drm_connector_status )2);
}
}
#line 252 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo , struct drm_display_mode *mode ) 
{ int __cil_tmp3 ;

  {
  {
#line 255
  __cil_tmp3 = mode->clock;
#line 255
  if (__cil_tmp3 > 165000) {
#line 256
    return ((enum drm_mode_status )15);
  } else {

  }
  }
#line 258
  return ((enum drm_mode_status )0);
}
}
#line 261 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static void ch7xxx_mode_set(struct intel_dvo_device *dvo , struct drm_display_mode *mode ,
                            struct drm_display_mode *adjusted_mode ) 
{ uint8_t tvco ;
  uint8_t tpcp ;
  uint8_t tpd ;
  uint8_t tlpf ;
  uint8_t idf ;
  int __cil_tmp9 ;
  uint8_t __cil_tmp10 ;
  int __cil_tmp11 ;
  uint8_t __cil_tmp12 ;
  int __cil_tmp13 ;
  uint8_t __cil_tmp14 ;
  int __cil_tmp15 ;
  uint8_t __cil_tmp16 ;
  uint8_t __cil_tmp17 ;
  int __cil_tmp18 ;
  uint8_t __cil_tmp19 ;
  uint8_t __cil_tmp20 ;
  unsigned int __cil_tmp21 ;
  unsigned int __cil_tmp22 ;
  unsigned int __cil_tmp23 ;
  int __cil_tmp24 ;
  unsigned int __cil_tmp25 ;
  unsigned int __cil_tmp26 ;
  unsigned int __cil_tmp27 ;
  unsigned int __cil_tmp28 ;
  unsigned int __cil_tmp29 ;
  unsigned int __cil_tmp30 ;
  int __cil_tmp31 ;
  uint8_t __cil_tmp32 ;

  {
  {
#line 267
  __cil_tmp9 = mode->clock;
#line 267
  if (__cil_tmp9 <= 65000) {
#line 268
    tvco = (uint8_t )35U;
#line 269
    tpcp = (uint8_t )8U;
#line 270
    tpd = (uint8_t )22U;
#line 271
    tlpf = (uint8_t )96U;
  } else {
#line 273
    tvco = (uint8_t )45U;
#line 274
    tpcp = (uint8_t )6U;
#line 275
    tpd = (uint8_t )38U;
#line 276
    tlpf = (uint8_t )160U;
  }
  }
  {
#line 279
  __cil_tmp10 = (uint8_t )0;
#line 279
  ch7xxx_writeb(dvo, 49, __cil_tmp10);
#line 280
  __cil_tmp11 = (int )tvco;
#line 280
  __cil_tmp12 = (uint8_t )__cil_tmp11;
#line 280
  ch7xxx_writeb(dvo, 50, __cil_tmp12);
#line 281
  __cil_tmp13 = (int )tpcp;
#line 281
  __cil_tmp14 = (uint8_t )__cil_tmp13;
#line 281
  ch7xxx_writeb(dvo, 51, __cil_tmp14);
#line 282
  __cil_tmp15 = (int )tpd;
#line 282
  __cil_tmp16 = (uint8_t )__cil_tmp15;
#line 282
  ch7xxx_writeb(dvo, 52, __cil_tmp16);
#line 283
  __cil_tmp17 = (uint8_t )48;
#line 283
  ch7xxx_writeb(dvo, 53, __cil_tmp17);
#line 284
  __cil_tmp18 = (int )tlpf;
#line 284
  __cil_tmp19 = (uint8_t )__cil_tmp18;
#line 284
  ch7xxx_writeb(dvo, 54, __cil_tmp19);
#line 285
  __cil_tmp20 = (uint8_t )0;
#line 285
  ch7xxx_writeb(dvo, 55, __cil_tmp20);
#line 287
  ch7xxx_readb(dvo, 31, & idf);
#line 289
  __cil_tmp21 = (unsigned int )idf;
#line 289
  __cil_tmp22 = __cil_tmp21 & 231U;
#line 289
  idf = (uint8_t )__cil_tmp22;
  }
  {
#line 290
  __cil_tmp23 = mode->flags;
#line 290
  __cil_tmp24 = (int )__cil_tmp23;
#line 290
  if (__cil_tmp24 & 1) {
#line 291
    __cil_tmp25 = (unsigned int )idf;
#line 291
    __cil_tmp26 = __cil_tmp25 | 8U;
#line 291
    idf = (uint8_t )__cil_tmp26;
  } else {

  }
  }
  {
#line 293
  __cil_tmp27 = mode->flags;
#line 293
  __cil_tmp28 = __cil_tmp27 & 4U;
#line 293
  if (__cil_tmp28 != 0U) {
#line 294
    __cil_tmp29 = (unsigned int )idf;
#line 294
    __cil_tmp30 = __cil_tmp29 | 8U;
#line 294
    idf = (uint8_t )__cil_tmp30;
  } else {

  }
  }
  {
#line 296
  __cil_tmp31 = (int )idf;
#line 296
  __cil_tmp32 = (uint8_t )__cil_tmp31;
#line 296
  ch7xxx_writeb(dvo, 31, __cil_tmp32);
  }
#line 297
  return;
}
}
#line 300 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static void ch7xxx_dpms(struct intel_dvo_device *dvo , int mode ) 
{ uint8_t __cil_tmp3 ;
  uint8_t __cil_tmp4 ;

  {
#line 302
  if (mode == 0) {
    {
#line 303
    __cil_tmp3 = (uint8_t )192;
#line 303
    ch7xxx_writeb(dvo, 73, __cil_tmp3);
    }
  } else {
    {
#line 305
    __cil_tmp4 = (uint8_t )1;
#line 305
    ch7xxx_writeb(dvo, 73, __cil_tmp4);
    }
  }
#line 306
  return;
}
}
#line 308 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static void ch7xxx_dump_regs(struct intel_dvo_device *dvo ) 
{ int i ;
  uint8_t val ;
  unsigned int __cil_tmp4 ;
  unsigned int __cil_tmp5 ;
  char const   *__cil_tmp6 ;
  char const   *__cil_tmp7 ;
  char const   *__cil_tmp8 ;
  char const   *__cil_tmp9 ;
  int __cil_tmp10 ;

  {
#line 312
  i = 0;
#line 312
  goto ldv_37388;
  ldv_37387: ;
  {
#line 314
  __cil_tmp4 = (unsigned int )i;
#line 314
  __cil_tmp5 = __cil_tmp4 & 7U;
#line 314
  if (__cil_tmp5 == 0U) {
    {
#line 315
    __cil_tmp6 = (char const   *)0;
#line 315
    __cil_tmp7 = (char const   *)0;
#line 315
    drm_ut_debug_printk(4U, __cil_tmp6, __cil_tmp7, "\n %02X: ", i);
    }
  } else {

  }
  }
  {
#line 316
  ch7xxx_readb(dvo, i, & val);
#line 317
  __cil_tmp8 = (char const   *)0;
#line 317
  __cil_tmp9 = (char const   *)0;
#line 317
  __cil_tmp10 = (int )val;
#line 317
  drm_ut_debug_printk(4U, __cil_tmp8, __cil_tmp9, "%02X ", __cil_tmp10);
#line 312
  i = i + 1;
  }
  ldv_37388: ;
#line 312
  if (i <= 75) {
#line 313
    goto ldv_37387;
  } else {
#line 315
    goto ldv_37389;
  }
  ldv_37389: ;
#line 317
  return;
}
}
#line 321 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
static void ch7xxx_destroy(struct intel_dvo_device *dvo ) 
{ struct ch7xxx_priv *ch7xxx ;
  void *__cil_tmp3 ;
  struct ch7xxx_priv *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  void const   *__cil_tmp7 ;

  {
#line 323
  __cil_tmp3 = dvo->dev_priv;
#line 323
  ch7xxx = (struct ch7xxx_priv *)__cil_tmp3;
  {
#line 325
  __cil_tmp4 = (struct ch7xxx_priv *)0;
#line 325
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 325
  __cil_tmp6 = (unsigned long )ch7xxx;
#line 325
  if (__cil_tmp6 != __cil_tmp5) {
    {
#line 326
    __cil_tmp7 = (void const   *)ch7xxx;
#line 326
    kfree(__cil_tmp7);
#line 327
    dvo->dev_priv = (void *)0;
    }
  } else {

  }
  }
#line 329
  return;
}
}
#line 331 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7xxx.c.p"
struct intel_dvo_dev_ops ch7xxx_ops  = 
#line 331
     {& ch7xxx_init, (void (*)(struct intel_dvo_device * ))0, & ch7xxx_dpms, (int (*)(struct intel_dvo_device * ,
                                                                                    struct drm_display_mode * ))(& ch7xxx_mode_valid),
    (bool (*)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ))0,
    (void (*)(struct intel_dvo_device * ))0, (void (*)(struct intel_dvo_device * ))0,
    & ch7xxx_mode_set, & ch7xxx_detect, (struct drm_display_mode *(*)(struct intel_dvo_device * ))0,
    & ch7xxx_destroy, & ch7xxx_dump_regs};
#line 173 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static void ch7017_dump_regs(struct intel_dvo_device *dvo ) ;
#line 174
static void ch7017_dpms(struct intel_dvo_device *dvo , int mode ) ;
#line 176 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static bool ch7017_read(struct intel_dvo_device *dvo , u8 addr , u8 *val ) 
{ struct i2c_msg msgs[2U] ;
  int tmp ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  struct i2c_adapter *__cil_tmp8 ;
  struct i2c_msg *__cil_tmp9 ;
  int __cil_tmp10 ;

  {
  {
#line 178
  __cil_tmp6 = dvo->slave_addr;
#line 178
  msgs[0].addr = (unsigned short )__cil_tmp6;
#line 178
  msgs[0].flags = (__u16 )0U;
#line 178
  msgs[0].len = (__u16 )1U;
#line 178
  msgs[0].buf = & addr;
#line 178
  __cil_tmp7 = dvo->slave_addr;
#line 178
  msgs[1].addr = (unsigned short )__cil_tmp7;
#line 178
  msgs[1].flags = (__u16 )1U;
#line 178
  msgs[1].len = (__u16 )1U;
#line 178
  msgs[1].buf = val;
#line 192
  __cil_tmp8 = dvo->i2c_bus;
#line 192
  __cil_tmp9 = (struct i2c_msg *)(& msgs);
#line 192
  tmp = i2c_transfer(__cil_tmp8, __cil_tmp9, 2);
  }
  {
#line 192
  __cil_tmp10 = tmp == 2;
#line 192
  return ((bool )__cil_tmp10);
  }
}
}
#line 195 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static bool ch7017_write(struct intel_dvo_device *dvo , u8 addr , u8 val ) 
{ uint8_t buf[2U] ;
  struct i2c_msg msg ;
  int tmp ;
  int __cil_tmp7 ;
  struct i2c_adapter *__cil_tmp8 ;
  int __cil_tmp9 ;

  {
  {
#line 197
  buf[0] = addr;
#line 197
  buf[1] = val;
#line 198
  __cil_tmp7 = dvo->slave_addr;
#line 198
  msg.addr = (unsigned short )__cil_tmp7;
#line 198
  msg.flags = (__u16 )0U;
#line 198
  msg.len = (__u16 )2U;
#line 198
  msg.buf = (__u8 *)(& buf);
#line 204
  __cil_tmp8 = dvo->i2c_bus;
#line 204
  tmp = i2c_transfer(__cil_tmp8, & msg, 1);
  }
  {
#line 204
  __cil_tmp9 = tmp == 1;
#line 204
  return ((bool )__cil_tmp9);
  }
}
}
#line 208 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static bool ch7017_init(struct intel_dvo_device *dvo , struct i2c_adapter *adapter ) 
{ struct ch7017_priv *priv ;
  char const   *str ;
  u8 val ;
  void *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  struct ch7017_priv *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  u8 __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  char (*__cil_tmp17)[48U] ;
  char *__cil_tmp18 ;
  int __cil_tmp19 ;
  char (*__cil_tmp20)[48U] ;
  char *__cil_tmp21 ;
  int __cil_tmp22 ;
  void const   *__cil_tmp23 ;

  {
  {
#line 215
  tmp = kzalloc(1UL, 208U);
#line 215
  priv = (struct ch7017_priv *)tmp;
  }
  {
#line 216
  __cil_tmp9 = (struct ch7017_priv *)0;
#line 216
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 216
  __cil_tmp11 = (unsigned long )priv;
#line 216
  if (__cil_tmp11 == __cil_tmp10) {
#line 217
    return ((bool )0);
  } else {

  }
  }
  {
#line 219
  dvo->i2c_bus = adapter;
#line 220
  dvo->dev_priv = (void *)priv;
#line 222
  __cil_tmp12 = (u8 )75;
#line 222
  tmp___0 = ch7017_read(dvo, __cil_tmp12, & val);
  }
#line 222
  if (tmp___0) {
#line 222
    tmp___1 = 0;
  } else {
#line 222
    tmp___1 = 1;
  }
#line 222
  if (tmp___1) {
#line 223
    goto fail;
  } else {

  }
  {
#line 226
  __cil_tmp13 = (int )val;
#line 226
  if (__cil_tmp13 == 27) {
#line 226
    goto case_27;
  } else {
    {
#line 229
    __cil_tmp14 = (int )val;
#line 229
    if (__cil_tmp14 == 26) {
#line 229
      goto case_26;
    } else {
      {
#line 232
      __cil_tmp15 = (int )val;
#line 232
      if (__cil_tmp15 == 25) {
#line 232
        goto case_25;
      } else {
#line 235
        goto switch_default;
#line 225
        if (0) {
          case_27: 
#line 227
          str = "ch7017";
#line 228
          goto ldv_37341;
          case_26: 
#line 230
          str = "ch7018";
#line 231
          goto ldv_37341;
          case_25: 
#line 233
          str = "ch7019";
#line 234
          goto ldv_37341;
          switch_default: 
          {
#line 236
          __cil_tmp16 = (int )val;
#line 236
          __cil_tmp17 = & adapter->name;
#line 236
          __cil_tmp18 = (char *)__cil_tmp17;
#line 236
          __cil_tmp19 = dvo->slave_addr;
#line 236
          drm_ut_debug_printk(4U, "drm", "ch7017_init", "ch701x not detected, got %d: from %s slave %d.\n",
                              __cil_tmp16, __cil_tmp18, __cil_tmp19);
          }
#line 239
          goto fail;
        } else {

        }
      }
      }
    }
    }
  }
  }
  ldv_37341: 
  {
#line 242
  __cil_tmp20 = & adapter->name;
#line 242
  __cil_tmp21 = (char *)__cil_tmp20;
#line 242
  __cil_tmp22 = dvo->slave_addr;
#line 242
  drm_ut_debug_printk(4U, "drm", "ch7017_init", "%s detected on %s, addr %d\n", str,
                      __cil_tmp21, __cil_tmp22);
  }
#line 244
  return ((bool )1);
  fail: 
  {
#line 247
  __cil_tmp23 = (void const   *)priv;
#line 247
  kfree(__cil_tmp23);
  }
#line 248
  return ((bool )0);
}
}
#line 251 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo ) 
{ 

  {
#line 253
  return ((enum drm_connector_status )1);
}
}
#line 256 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo , struct drm_display_mode *mode ) 
{ int __cil_tmp3 ;

  {
  {
#line 259
  __cil_tmp3 = mode->clock;
#line 259
  if (__cil_tmp3 > 160000) {
#line 260
    return ((enum drm_mode_status )15);
  } else {

  }
  }
#line 262
  return ((enum drm_mode_status )0);
}
}
#line 265 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static void ch7017_mode_set(struct intel_dvo_device *dvo , struct drm_display_mode *mode ,
                            struct drm_display_mode *adjusted_mode ) 
{ uint8_t lvds_pll_feedback_div ;
  uint8_t lvds_pll_vco_control ;
  uint8_t outputs_enable ;
  uint8_t lvds_control_2 ;
  uint8_t lvds_power_down ;
  uint8_t horizontal_active_pixel_input ;
  uint8_t horizontal_active_pixel_output ;
  uint8_t vertical_active_line_output ;
  uint8_t active_input_line_output ;
  int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  signed char __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  signed char __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  int __cil_tmp33 ;
  signed char __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  u8 __cil_tmp37 ;
  int __cil_tmp38 ;
  u8 __cil_tmp39 ;
  u8 __cil_tmp40 ;
  int __cil_tmp41 ;
  u8 __cil_tmp42 ;
  u8 __cil_tmp43 ;
  int __cil_tmp44 ;
  u8 __cil_tmp45 ;
  u8 __cil_tmp46 ;
  int __cil_tmp47 ;
  u8 __cil_tmp48 ;
  u8 __cil_tmp49 ;
  int __cil_tmp50 ;
  u8 __cil_tmp51 ;
  u8 __cil_tmp52 ;
  int __cil_tmp53 ;
  u8 __cil_tmp54 ;
  u8 __cil_tmp55 ;
  int __cil_tmp56 ;
  u8 __cil_tmp57 ;
  u8 __cil_tmp58 ;
  int __cil_tmp59 ;
  u8 __cil_tmp60 ;
  u8 __cil_tmp61 ;
  int __cil_tmp62 ;
  u8 __cil_tmp63 ;

  {
  {
#line 275
  drm_ut_debug_printk(4U, "drm", "ch7017_mode_set", "Registers before mode setting\n");
#line 276
  ch7017_dump_regs(dvo);
  }
  {
#line 279
  __cil_tmp13 = mode->clock;
#line 279
  if (__cil_tmp13 <= 99999) {
#line 280
    outputs_enable = (uint8_t )8U;
#line 281
    lvds_pll_feedback_div = (uint8_t )173U;
#line 284
    lvds_pll_vco_control = (uint8_t )163U;
#line 287
    lvds_control_2 = (uint8_t )32U;
  } else {
#line 290
    outputs_enable = (uint8_t )11U;
#line 291
    lvds_pll_feedback_div = (uint8_t )163U;
#line 294
    lvds_pll_feedback_div = (uint8_t )35U;
#line 295
    lvds_control_2 = (uint8_t )96U;
#line 298
    __cil_tmp14 = (unsigned int )outputs_enable;
#line 298
    __cil_tmp15 = __cil_tmp14 | 16U;
#line 298
    outputs_enable = (uint8_t )__cil_tmp15;
#line 299
    lvds_pll_vco_control = (uint8_t )173U;
  }
  }
  {
#line 309
  __cil_tmp16 = mode->hdisplay;
#line 309
  horizontal_active_pixel_input = (uint8_t )__cil_tmp16;
#line 311
  __cil_tmp17 = mode->vdisplay;
#line 311
  vertical_active_line_output = (uint8_t )__cil_tmp17;
#line 312
  __cil_tmp18 = mode->hdisplay;
#line 312
  horizontal_active_pixel_output = (uint8_t )__cil_tmp18;
#line 314
  __cil_tmp19 = mode->vdisplay;
#line 314
  __cil_tmp20 = __cil_tmp19 & 1792;
#line 314
  __cil_tmp21 = __cil_tmp20 >> 8;
#line 314
  __cil_tmp22 = __cil_tmp21 << 3;
#line 314
  __cil_tmp23 = (signed char )__cil_tmp22;
#line 314
  __cil_tmp24 = (int )__cil_tmp23;
#line 314
  __cil_tmp25 = mode->hdisplay;
#line 314
  __cil_tmp26 = __cil_tmp25 & 1792;
#line 314
  __cil_tmp27 = __cil_tmp26 >> 8;
#line 314
  __cil_tmp28 = (signed char )__cil_tmp27;
#line 314
  __cil_tmp29 = (int )__cil_tmp28;
#line 314
  __cil_tmp30 = __cil_tmp29 | __cil_tmp24;
#line 314
  active_input_line_output = (uint8_t )__cil_tmp30;
#line 317
  __cil_tmp31 = mode->hdisplay;
#line 317
  __cil_tmp32 = __cil_tmp31 & 1792;
#line 317
  __cil_tmp33 = __cil_tmp32 >> 8;
#line 317
  __cil_tmp34 = (signed char )__cil_tmp33;
#line 317
  __cil_tmp35 = (int )__cil_tmp34;
#line 317
  __cil_tmp36 = __cil_tmp35 | 8;
#line 317
  lvds_power_down = (uint8_t )__cil_tmp36;
#line 320
  ch7017_dpms(dvo, 3);
#line 321
  __cil_tmp37 = (u8 )95;
#line 321
  __cil_tmp38 = (int )horizontal_active_pixel_input;
#line 321
  __cil_tmp39 = (u8 )__cil_tmp38;
#line 321
  ch7017_write(dvo, __cil_tmp37, __cil_tmp39);
#line 323
  __cil_tmp40 = (u8 )98;
#line 323
  __cil_tmp41 = (int )horizontal_active_pixel_output;
#line 323
  __cil_tmp42 = (u8 )__cil_tmp41;
#line 323
  ch7017_write(dvo, __cil_tmp40, __cil_tmp42);
#line 325
  __cil_tmp43 = (u8 )97;
#line 325
  __cil_tmp44 = (int )vertical_active_line_output;
#line 325
  __cil_tmp45 = (u8 )__cil_tmp44;
#line 325
  ch7017_write(dvo, __cil_tmp43, __cil_tmp45);
#line 327
  __cil_tmp46 = (u8 )96;
#line 327
  __cil_tmp47 = (int )active_input_line_output;
#line 327
  __cil_tmp48 = (u8 )__cil_tmp47;
#line 327
  ch7017_write(dvo, __cil_tmp46, __cil_tmp48);
#line 329
  __cil_tmp49 = (u8 )114;
#line 329
  __cil_tmp50 = (int )lvds_pll_vco_control;
#line 329
  __cil_tmp51 = (u8 )__cil_tmp50;
#line 329
  ch7017_write(dvo, __cil_tmp49, __cil_tmp51);
#line 330
  __cil_tmp52 = (u8 )113;
#line 330
  __cil_tmp53 = (int )lvds_pll_feedback_div;
#line 330
  __cil_tmp54 = (u8 )__cil_tmp53;
#line 330
  ch7017_write(dvo, __cil_tmp52, __cil_tmp54);
#line 331
  __cil_tmp55 = (u8 )120;
#line 331
  __cil_tmp56 = (int )lvds_control_2;
#line 331
  __cil_tmp57 = (u8 )__cil_tmp56;
#line 331
  ch7017_write(dvo, __cil_tmp55, __cil_tmp57);
#line 332
  __cil_tmp58 = (u8 )115;
#line 332
  __cil_tmp59 = (int )outputs_enable;
#line 332
  __cil_tmp60 = (u8 )__cil_tmp59;
#line 332
  ch7017_write(dvo, __cil_tmp58, __cil_tmp60);
#line 335
  __cil_tmp61 = (u8 )99;
#line 335
  __cil_tmp62 = (int )lvds_power_down;
#line 335
  __cil_tmp63 = (u8 )__cil_tmp62;
#line 335
  ch7017_write(dvo, __cil_tmp61, __cil_tmp63);
#line 337
  drm_ut_debug_printk(4U, "drm", "ch7017_mode_set", "Registers after mode setting\n");
#line 338
  ch7017_dump_regs(dvo);
  }
#line 339
  return;
}
}
#line 342 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static void ch7017_dpms(struct intel_dvo_device *dvo , int mode ) 
{ uint8_t val ;
  u8 __cil_tmp4 ;
  u8 __cil_tmp5 ;
  u8 __cil_tmp6 ;
  u8 __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  u8 __cil_tmp10 ;
  u8 __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  int __cil_tmp14 ;
  u8 __cil_tmp15 ;

  {
  {
#line 346
  __cil_tmp4 = (u8 )99;
#line 346
  ch7017_read(dvo, __cil_tmp4, & val);
#line 349
  __cil_tmp5 = (u8 )73;
#line 349
  __cil_tmp6 = (u8 )62;
#line 349
  ch7017_write(dvo, __cil_tmp5, __cil_tmp6);
  }
#line 356
  if (mode == 0) {
    {
#line 358
    __cil_tmp7 = (u8 )99;
#line 358
    __cil_tmp8 = (int )val;
#line 358
    __cil_tmp9 = __cil_tmp8 & 191;
#line 358
    __cil_tmp10 = (u8 )__cil_tmp9;
#line 358
    ch7017_write(dvo, __cil_tmp7, __cil_tmp10);
    }
  } else {
    {
#line 362
    __cil_tmp11 = (u8 )99;
#line 362
    __cil_tmp12 = (unsigned int )val;
#line 362
    __cil_tmp13 = __cil_tmp12 | 64U;
#line 362
    __cil_tmp14 = (int )__cil_tmp13;
#line 362
    __cil_tmp15 = (u8 )__cil_tmp14;
#line 362
    ch7017_write(dvo, __cil_tmp11, __cil_tmp15);
    }
  }
  {
#line 367
  msleep(20U);
  }
#line 368
  return;
}
}
#line 370 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static void ch7017_dump_regs(struct intel_dvo_device *dvo ) 
{ uint8_t val ;
  u8 __cil_tmp3 ;
  int __cil_tmp4 ;
  u8 __cil_tmp5 ;
  int __cil_tmp6 ;
  u8 __cil_tmp7 ;
  int __cil_tmp8 ;
  u8 __cil_tmp9 ;
  int __cil_tmp10 ;
  u8 __cil_tmp11 ;
  int __cil_tmp12 ;
  u8 __cil_tmp13 ;
  int __cil_tmp14 ;
  u8 __cil_tmp15 ;
  int __cil_tmp16 ;
  u8 __cil_tmp17 ;
  int __cil_tmp18 ;
  u8 __cil_tmp19 ;
  int __cil_tmp20 ;

  {
  {
#line 380
  __cil_tmp3 = (u8 )95;
#line 380
  ch7017_read(dvo, __cil_tmp3, & val);
#line 380
  __cil_tmp4 = (int )val;
#line 380
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT: %02x\n",
                      __cil_tmp4);
#line 381
  __cil_tmp5 = (u8 )98;
#line 381
  ch7017_read(dvo, __cil_tmp5, & val);
#line 381
  __cil_tmp6 = (int )val;
#line 381
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT: %02x\n",
                      __cil_tmp6);
#line 382
  __cil_tmp7 = (u8 )97;
#line 382
  ch7017_read(dvo, __cil_tmp7, & val);
#line 382
  __cil_tmp8 = (int )val;
#line 382
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_VERTICAL_ACTIVE_LINE_OUTPUT: %02x\n",
                      __cil_tmp8);
#line 383
  __cil_tmp9 = (u8 )96;
#line 383
  ch7017_read(dvo, __cil_tmp9, & val);
#line 383
  __cil_tmp10 = (int )val;
#line 383
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_ACTIVE_INPUT_LINE_OUTPUT: %02x\n",
                      __cil_tmp10);
#line 384
  __cil_tmp11 = (u8 )114;
#line 384
  ch7017_read(dvo, __cil_tmp11, & val);
#line 384
  __cil_tmp12 = (int )val;
#line 384
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_LVDS_PLL_VCO_CONTROL: %02x\n",
                      __cil_tmp12);
#line 385
  __cil_tmp13 = (u8 )113;
#line 385
  ch7017_read(dvo, __cil_tmp13, & val);
#line 385
  __cil_tmp14 = (int )val;
#line 385
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_LVDS_PLL_FEEDBACK_DIV: %02x\n",
                      __cil_tmp14);
#line 386
  __cil_tmp15 = (u8 )120;
#line 386
  ch7017_read(dvo, __cil_tmp15, & val);
#line 386
  __cil_tmp16 = (int )val;
#line 386
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_LVDS_CONTROL_2: %02x\n",
                      __cil_tmp16);
#line 387
  __cil_tmp17 = (u8 )115;
#line 387
  ch7017_read(dvo, __cil_tmp17, & val);
#line 387
  __cil_tmp18 = (int )val;
#line 387
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_OUTPUTS_ENABLE: %02x\n",
                      __cil_tmp18);
#line 388
  __cil_tmp19 = (u8 )99;
#line 388
  ch7017_read(dvo, __cil_tmp19, & val);
#line 388
  __cil_tmp20 = (int )val;
#line 388
  drm_ut_debug_printk(4U, "drm", "ch7017_dump_regs", "CH7017_LVDS_POWER_DOWN: %02x\n",
                      __cil_tmp20);
  }
#line 389
  return;
}
}
#line 391 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
static void ch7017_destroy(struct intel_dvo_device *dvo ) 
{ struct ch7017_priv *priv ;
  void *__cil_tmp3 ;
  struct ch7017_priv *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  void const   *__cil_tmp7 ;

  {
#line 393
  __cil_tmp3 = dvo->dev_priv;
#line 393
  priv = (struct ch7017_priv *)__cil_tmp3;
  {
#line 395
  __cil_tmp4 = (struct ch7017_priv *)0;
#line 395
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 395
  __cil_tmp6 = (unsigned long )priv;
#line 395
  if (__cil_tmp6 != __cil_tmp5) {
    {
#line 396
    __cil_tmp7 = (void const   *)priv;
#line 396
    kfree(__cil_tmp7);
#line 397
    dvo->dev_priv = (void *)0;
    }
  } else {

  }
  }
#line 399
  return;
}
}
#line 401 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ch7017.c.p"
struct intel_dvo_dev_ops ch7017_ops  = 
#line 401
     {& ch7017_init, (void (*)(struct intel_dvo_device * ))0, & ch7017_dpms, (int (*)(struct intel_dvo_device * ,
                                                                                    struct drm_display_mode * ))(& ch7017_mode_valid),
    (bool (*)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ))0,
    (void (*)(struct intel_dvo_device * ))0, (void (*)(struct intel_dvo_device * ))0,
    & ch7017_mode_set, & ch7017_detect, (struct drm_display_mode *(*)(struct intel_dvo_device * ))0,
    & ch7017_destroy, & ch7017_dump_regs};
#line 167 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static void ivch_dump_regs(struct intel_dvo_device *dvo ) ;
#line 174 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static bool ivch_read(struct intel_dvo_device *dvo , int addr , uint16_t *data ) 
{ struct ivch_priv *priv ;
  struct i2c_adapter *adapter ;
  u8 out_buf[1U] ;
  u8 in_buf[2U] ;
  struct i2c_msg msgs[3U] ;
  int tmp ;
  void *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  struct i2c_msg *__cil_tmp13 ;
  short __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  short __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  bool __cil_tmp21 ;
  char (*__cil_tmp22)[48U] ;
  char *__cil_tmp23 ;
  int __cil_tmp24 ;

  {
  {
#line 176
  __cil_tmp10 = dvo->dev_priv;
#line 176
  priv = (struct ivch_priv *)__cil_tmp10;
#line 177
  adapter = dvo->i2c_bus;
#line 181
  __cil_tmp11 = dvo->slave_addr;
#line 181
  msgs[0].addr = (unsigned short )__cil_tmp11;
#line 181
  msgs[0].flags = (__u16 )1U;
#line 181
  msgs[0].len = (__u16 )0U;
#line 181
  msgs[0].buf = (__u8 *)0;
#line 181
  msgs[1].addr = (__u16 )0U;
#line 181
  msgs[1].flags = (__u16 )16384U;
#line 181
  msgs[1].len = (__u16 )1U;
#line 181
  msgs[1].buf = (__u8 *)(& out_buf);
#line 181
  __cil_tmp12 = dvo->slave_addr;
#line 181
  msgs[2].addr = (unsigned short )__cil_tmp12;
#line 181
  msgs[2].flags = (__u16 )16385U;
#line 181
  msgs[2].len = (__u16 )2U;
#line 181
  msgs[2].buf = (__u8 *)(& in_buf);
#line 201
  out_buf[0] = (u8 )addr;
#line 203
  __cil_tmp13 = (struct i2c_msg *)(& msgs);
#line 203
  tmp = i2c_transfer(adapter, __cil_tmp13, 3);
  }
#line 203
  if (tmp == 3) {
#line 204
    __cil_tmp14 = (short )in_buf[0];
#line 204
    __cil_tmp15 = (int )__cil_tmp14;
#line 204
    __cil_tmp16 = (int )in_buf[1];
#line 204
    __cil_tmp17 = __cil_tmp16 << 8;
#line 204
    __cil_tmp18 = (short )__cil_tmp17;
#line 204
    __cil_tmp19 = (int )__cil_tmp18;
#line 204
    __cil_tmp20 = __cil_tmp19 | __cil_tmp15;
#line 204
    *data = (uint16_t )__cil_tmp20;
#line 205
    return ((bool )1);
  } else {

  }
  {
#line 208
  __cil_tmp21 = priv->quiet;
#line 208
  if (! __cil_tmp21) {
    {
#line 209
    __cil_tmp22 = & adapter->name;
#line 209
    __cil_tmp23 = (char *)__cil_tmp22;
#line 209
    __cil_tmp24 = dvo->slave_addr;
#line 209
    drm_ut_debug_printk(4U, "drm", "ivch_read", "Unable to read register 0x%02x from %s:%02x.\n",
                        addr, __cil_tmp23, __cil_tmp24);
    }
  } else {

  }
  }
#line 213
  return ((bool )0);
}
}
#line 217 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static bool ivch_write(struct intel_dvo_device *dvo , int addr , uint16_t data ) 
{ struct ivch_priv *priv ;
  struct i2c_adapter *adapter ;
  u8 out_buf[3U] ;
  struct i2c_msg msg ;
  int tmp ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  bool __cil_tmp13 ;
  char (*__cil_tmp14)[48U] ;
  char *__cil_tmp15 ;
  int __cil_tmp16 ;

  {
  {
#line 219
  __cil_tmp9 = dvo->dev_priv;
#line 219
  priv = (struct ivch_priv *)__cil_tmp9;
#line 220
  adapter = dvo->i2c_bus;
#line 222
  __cil_tmp10 = dvo->slave_addr;
#line 222
  msg.addr = (unsigned short )__cil_tmp10;
#line 222
  msg.flags = (__u16 )0U;
#line 222
  msg.len = (__u16 )3U;
#line 222
  msg.buf = (__u8 *)(& out_buf);
#line 229
  out_buf[0] = (u8 )addr;
#line 230
  out_buf[1] = (u8 )data;
#line 231
  __cil_tmp11 = (int )data;
#line 231
  __cil_tmp12 = __cil_tmp11 >> 8;
#line 231
  out_buf[2] = (u8 )__cil_tmp12;
#line 233
  tmp = i2c_transfer(adapter, & msg, 1);
  }
#line 233
  if (tmp == 1) {
#line 234
    return ((bool )1);
  } else {

  }
  {
#line 236
  __cil_tmp13 = priv->quiet;
#line 236
  if (! __cil_tmp13) {
    {
#line 237
    __cil_tmp14 = & adapter->name;
#line 237
    __cil_tmp15 = (char *)__cil_tmp14;
#line 237
    __cil_tmp16 = dvo->slave_addr;
#line 237
    drm_ut_debug_printk(4U, "drm", "ivch_write", "Unable to write register 0x%02x to %s:%d.\n",
                        addr, __cil_tmp15, __cil_tmp16);
    }
  } else {

  }
  }
#line 241
  return ((bool )0);
}
}
#line 245 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static bool ivch_init(struct intel_dvo_device *dvo , struct i2c_adapter *adapter ) 
{ struct ivch_priv *priv ;
  uint16_t temp ;
  void *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  struct ivch_priv *__cil_tmp8 ;
  unsigned long __cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;
  uint16_t *__cil_tmp17 ;
  uint16_t *__cil_tmp18 ;
  void const   *__cil_tmp19 ;

  {
  {
#line 251
  tmp = kzalloc(6UL, 208U);
#line 251
  priv = (struct ivch_priv *)tmp;
  }
  {
#line 252
  __cil_tmp8 = (struct ivch_priv *)0;
#line 252
  __cil_tmp9 = (unsigned long )__cil_tmp8;
#line 252
  __cil_tmp10 = (unsigned long )priv;
#line 252
  if (__cil_tmp10 == __cil_tmp9) {
#line 253
    return ((bool )0);
  } else {

  }
  }
  {
#line 255
  dvo->i2c_bus = adapter;
#line 256
  dvo->dev_priv = (void *)priv;
#line 257
  priv->quiet = (bool )1;
#line 259
  tmp___0 = ivch_read(dvo, 0, & temp);
  }
#line 259
  if (tmp___0) {
#line 259
    tmp___1 = 0;
  } else {
#line 259
    tmp___1 = 1;
  }
#line 259
  if (tmp___1) {
#line 260
    goto out;
  } else {

  }
#line 261
  priv->quiet = (bool )0;
  {
#line 267
  __cil_tmp11 = dvo->slave_addr;
#line 267
  __cil_tmp12 = (int )temp;
#line 267
  __cil_tmp13 = __cil_tmp12 & 127;
#line 267
  if (__cil_tmp13 != __cil_tmp11) {
    {
#line 268
    __cil_tmp14 = (int )temp;
#line 268
    __cil_tmp15 = __cil_tmp14 & 127;
#line 268
    __cil_tmp16 = dvo->slave_addr;
#line 268
    drm_ut_debug_printk(4U, "drm", "ivch_init", "ivch detect failed due to address mismatch (%d vs %d)\n",
                        __cil_tmp15, __cil_tmp16);
    }
#line 271
    goto out;
  } else {

  }
  }
  {
#line 274
  __cil_tmp17 = & priv->width;
#line 274
  ivch_read(dvo, 32, __cil_tmp17);
#line 275
  __cil_tmp18 = & priv->height;
#line 275
  ivch_read(dvo, 32, __cil_tmp18);
  }
#line 277
  return ((bool )1);
  out: 
  {
#line 280
  __cil_tmp19 = (void const   *)priv;
#line 280
  kfree(__cil_tmp19);
  }
#line 281
  return ((bool )0);
}
}
#line 284 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo ) 
{ 

  {
#line 286
  return ((enum drm_connector_status )1);
}
}
#line 289 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo , struct drm_display_mode *mode ) 
{ int __cil_tmp3 ;

  {
  {
#line 292
  __cil_tmp3 = mode->clock;
#line 292
  if (__cil_tmp3 > 112000) {
#line 293
    return ((enum drm_mode_status )15);
  } else {

  }
  }
#line 295
  return ((enum drm_mode_status )0);
}
}
#line 299 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static void ivch_dpms(struct intel_dvo_device *dvo , int mode ) 
{ int i ;
  uint16_t vr01 ;
  uint16_t vr30 ;
  uint16_t backlight ;
  bool tmp ;
  int tmp___0 ;
  bool tmp___1 ;
  int tmp___2 ;
  int __cil_tmp11 ;
  uint16_t __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  unsigned int __cil_tmp16 ;
  int __cil_tmp17 ;
  uint16_t __cil_tmp18 ;
  int __cil_tmp19 ;
  short __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;

  {
  {
#line 305
  tmp = ivch_read(dvo, 1, & vr01);
  }
#line 305
  if (tmp) {
#line 305
    tmp___0 = 0;
  } else {
#line 305
    tmp___0 = 1;
  }
#line 305
  if (tmp___0) {
#line 306
    return;
  } else {

  }
#line 308
  if (mode == 0) {
#line 309
    backlight = (uint16_t )1U;
  } else {
#line 311
    backlight = (uint16_t )0U;
  }
  {
#line 312
  __cil_tmp11 = (int )backlight;
#line 312
  __cil_tmp12 = (uint16_t )__cil_tmp11;
#line 312
  ivch_write(dvo, 128, __cil_tmp12);
  }
#line 314
  if (mode == 0) {
#line 315
    __cil_tmp13 = (unsigned int )vr01;
#line 315
    __cil_tmp14 = __cil_tmp13 | 5U;
#line 315
    vr01 = (uint16_t )__cil_tmp14;
  } else {
#line 317
    __cil_tmp15 = (unsigned int )vr01;
#line 317
    __cil_tmp16 = __cil_tmp15 & 65530U;
#line 317
    vr01 = (uint16_t )__cil_tmp16;
  }
  {
#line 319
  __cil_tmp17 = (int )vr01;
#line 319
  __cil_tmp18 = (uint16_t )__cil_tmp17;
#line 319
  ivch_write(dvo, 1, __cil_tmp18);
#line 322
  i = 0;
  }
#line 322
  goto ldv_37364;
  ldv_37363: 
  {
#line 323
  tmp___1 = ivch_read(dvo, 48, & vr30);
  }
#line 323
  if (tmp___1) {
#line 323
    tmp___2 = 0;
  } else {
#line 323
    tmp___2 = 1;
  }
#line 323
  if (tmp___2) {
#line 324
    goto ldv_37362;
  } else {

  }
  {
#line 326
  __cil_tmp19 = mode == 0;
#line 326
  __cil_tmp20 = (short )vr30;
#line 326
  __cil_tmp21 = (int )__cil_tmp20;
#line 326
  __cil_tmp22 = __cil_tmp21 >= 0;
#line 326
  if (__cil_tmp22 ^ __cil_tmp19) {
#line 327
    goto ldv_37362;
  } else {

  }
  }
  {
#line 328
  __const_udelay(4295000UL);
#line 322
  i = i + 1;
  }
  ldv_37364: ;
#line 322
  if (i <= 99) {
#line 323
    goto ldv_37363;
  } else {
#line 325
    goto ldv_37362;
  }
  ldv_37362: 
  {
#line 331
  __const_udelay(68720000UL);
  }
#line 332
  return;
}
}
#line 334 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static void ivch_mode_set(struct intel_dvo_device *dvo , struct drm_display_mode *mode ,
                          struct drm_display_mode *adjusted_mode ) 
{ uint16_t vr40 ;
  uint16_t vr01 ;
  uint16_t x_ratio ;
  uint16_t y_ratio ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  unsigned int __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  unsigned int __cil_tmp14 ;
  unsigned int __cil_tmp15 ;
  int __cil_tmp16 ;
  int __cil_tmp17 ;
  int __cil_tmp18 ;
  int __cil_tmp19 ;
  int __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  int __cil_tmp23 ;
  int __cil_tmp24 ;
  int __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  int __cil_tmp28 ;
  int __cil_tmp29 ;
  int __cil_tmp30 ;
  uint16_t __cil_tmp31 ;
  int __cil_tmp32 ;
  uint16_t __cil_tmp33 ;
  unsigned int __cil_tmp34 ;
  unsigned int __cil_tmp35 ;
  unsigned int __cil_tmp36 ;
  unsigned int __cil_tmp37 ;
  unsigned int __cil_tmp38 ;
  unsigned int __cil_tmp39 ;
  int __cil_tmp40 ;
  uint16_t __cil_tmp41 ;
  int __cil_tmp42 ;
  uint16_t __cil_tmp43 ;

  {
#line 338
  vr40 = (uint16_t )0U;
#line 341
  vr01 = (uint16_t )0U;
#line 342
  vr40 = (uint16_t )13312U;
  {
#line 345
  __cil_tmp8 = adjusted_mode->hdisplay;
#line 345
  __cil_tmp9 = mode->hdisplay;
#line 345
  if (__cil_tmp9 != __cil_tmp8) {
#line 345
    goto _L;
  } else {
    {
#line 345
    __cil_tmp10 = adjusted_mode->vdisplay;
#line 345
    __cil_tmp11 = mode->vdisplay;
#line 345
    if (__cil_tmp11 != __cil_tmp10) {
      _L: 
      {
#line 349
      __cil_tmp12 = (unsigned int )vr01;
#line 349
      __cil_tmp13 = __cil_tmp12 | 8U;
#line 349
      vr01 = (uint16_t )__cil_tmp13;
#line 350
      __cil_tmp14 = (unsigned int )vr40;
#line 350
      __cil_tmp15 = __cil_tmp14 | 256U;
#line 350
      vr40 = (uint16_t )__cil_tmp15;
#line 351
      __cil_tmp16 = adjusted_mode->hdisplay;
#line 351
      __cil_tmp17 = __cil_tmp16 + -1;
#line 351
      __cil_tmp18 = mode->hdisplay;
#line 351
      __cil_tmp19 = __cil_tmp18 + -1;
#line 351
      __cil_tmp20 = __cil_tmp19 << 16;
#line 351
      __cil_tmp21 = __cil_tmp20 / __cil_tmp17;
#line 351
      __cil_tmp22 = __cil_tmp21 >> 2;
#line 351
      x_ratio = (uint16_t )__cil_tmp22;
#line 353
      __cil_tmp23 = adjusted_mode->vdisplay;
#line 353
      __cil_tmp24 = __cil_tmp23 + -1;
#line 353
      __cil_tmp25 = mode->vdisplay;
#line 353
      __cil_tmp26 = __cil_tmp25 + -1;
#line 353
      __cil_tmp27 = __cil_tmp26 << 16;
#line 353
      __cil_tmp28 = __cil_tmp27 / __cil_tmp24;
#line 353
      __cil_tmp29 = __cil_tmp28 >> 2;
#line 353
      y_ratio = (uint16_t )__cil_tmp29;
#line 355
      __cil_tmp30 = (int )x_ratio;
#line 355
      __cil_tmp31 = (uint16_t )__cil_tmp30;
#line 355
      ivch_write(dvo, 66, __cil_tmp31);
#line 356
      __cil_tmp32 = (int )y_ratio;
#line 356
      __cil_tmp33 = (uint16_t )__cil_tmp32;
#line 356
      ivch_write(dvo, 65, __cil_tmp33);
      }
    } else {
#line 358
      __cil_tmp34 = (unsigned int )vr01;
#line 358
      __cil_tmp35 = __cil_tmp34 & 65527U;
#line 358
      vr01 = (uint16_t )__cil_tmp35;
#line 359
      __cil_tmp36 = (unsigned int )vr40;
#line 359
      __cil_tmp37 = __cil_tmp36 & 65279U;
#line 359
      vr40 = (uint16_t )__cil_tmp37;
    }
    }
  }
  }
  {
#line 361
  __cil_tmp38 = (unsigned int )vr40;
#line 361
  __cil_tmp39 = __cil_tmp38 & 65023U;
#line 361
  vr40 = (uint16_t )__cil_tmp39;
#line 363
  __cil_tmp40 = (int )vr01;
#line 363
  __cil_tmp41 = (uint16_t )__cil_tmp40;
#line 363
  ivch_write(dvo, 1, __cil_tmp41);
#line 364
  __cil_tmp42 = (int )vr40;
#line 364
  __cil_tmp43 = (uint16_t )__cil_tmp42;
#line 364
  ivch_write(dvo, 64, __cil_tmp43);
#line 366
  ivch_dump_regs(dvo);
  }
#line 367
  return;
}
}
#line 369 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static void ivch_dump_regs(struct intel_dvo_device *dvo ) 
{ uint16_t val ;
  char const   *__cil_tmp3 ;
  char const   *__cil_tmp4 ;
  int __cil_tmp5 ;
  char const   *__cil_tmp6 ;
  char const   *__cil_tmp7 ;
  int __cil_tmp8 ;
  char const   *__cil_tmp9 ;
  char const   *__cil_tmp10 ;
  int __cil_tmp11 ;
  char const   *__cil_tmp12 ;
  char const   *__cil_tmp13 ;
  int __cil_tmp14 ;
  char const   *__cil_tmp15 ;
  char const   *__cil_tmp16 ;
  int __cil_tmp17 ;
  char const   *__cil_tmp18 ;
  char const   *__cil_tmp19 ;
  int __cil_tmp20 ;
  char const   *__cil_tmp21 ;
  char const   *__cil_tmp22 ;
  int __cil_tmp23 ;
  char const   *__cil_tmp24 ;
  char const   *__cil_tmp25 ;
  int __cil_tmp26 ;
  char const   *__cil_tmp27 ;
  char const   *__cil_tmp28 ;
  int __cil_tmp29 ;
  char const   *__cil_tmp30 ;
  char const   *__cil_tmp31 ;
  int __cil_tmp32 ;
  char const   *__cil_tmp33 ;
  char const   *__cil_tmp34 ;
  int __cil_tmp35 ;
  char const   *__cil_tmp36 ;
  char const   *__cil_tmp37 ;
  int __cil_tmp38 ;
  char const   *__cil_tmp39 ;
  char const   *__cil_tmp40 ;
  int __cil_tmp41 ;
  char const   *__cil_tmp42 ;
  char const   *__cil_tmp43 ;
  int __cil_tmp44 ;
  char const   *__cil_tmp45 ;
  char const   *__cil_tmp46 ;
  int __cil_tmp47 ;

  {
  {
#line 373
  ivch_read(dvo, 0, & val);
#line 374
  __cil_tmp3 = (char const   *)0;
#line 374
  __cil_tmp4 = (char const   *)0;
#line 374
  __cil_tmp5 = (int )val;
#line 374
  drm_ut_debug_printk(4U, __cil_tmp3, __cil_tmp4, "VR00: 0x%04x\n", __cil_tmp5);
#line 375
  ivch_read(dvo, 1, & val);
#line 376
  __cil_tmp6 = (char const   *)0;
#line 376
  __cil_tmp7 = (char const   *)0;
#line 376
  __cil_tmp8 = (int )val;
#line 376
  drm_ut_debug_printk(4U, __cil_tmp6, __cil_tmp7, "VR01: 0x%04x\n", __cil_tmp8);
#line 377
  ivch_read(dvo, 48, & val);
#line 378
  __cil_tmp9 = (char const   *)0;
#line 378
  __cil_tmp10 = (char const   *)0;
#line 378
  __cil_tmp11 = (int )val;
#line 378
  drm_ut_debug_printk(4U, __cil_tmp9, __cil_tmp10, "VR30: 0x%04x\n", __cil_tmp11);
#line 379
  ivch_read(dvo, 64, & val);
#line 380
  __cil_tmp12 = (char const   *)0;
#line 380
  __cil_tmp13 = (char const   *)0;
#line 380
  __cil_tmp14 = (int )val;
#line 380
  drm_ut_debug_printk(4U, __cil_tmp12, __cil_tmp13, "VR40: 0x%04x\n", __cil_tmp14);
#line 383
  ivch_read(dvo, 128, & val);
#line 384
  __cil_tmp15 = (char const   *)0;
#line 384
  __cil_tmp16 = (char const   *)0;
#line 384
  __cil_tmp17 = (int )val;
#line 384
  drm_ut_debug_printk(4U, __cil_tmp15, __cil_tmp16, "VR80: 0x%04x\n", __cil_tmp17);
#line 385
  ivch_read(dvo, 129, & val);
#line 386
  __cil_tmp18 = (char const   *)0;
#line 386
  __cil_tmp19 = (char const   *)0;
#line 386
  __cil_tmp20 = (int )val;
#line 386
  drm_ut_debug_printk(4U, __cil_tmp18, __cil_tmp19, "VR81: 0x%04x\n", __cil_tmp20);
#line 387
  ivch_read(dvo, 130, & val);
#line 388
  __cil_tmp21 = (char const   *)0;
#line 388
  __cil_tmp22 = (char const   *)0;
#line 388
  __cil_tmp23 = (int )val;
#line 388
  drm_ut_debug_printk(4U, __cil_tmp21, __cil_tmp22, "VR82: 0x%04x\n", __cil_tmp23);
#line 389
  ivch_read(dvo, 131, & val);
#line 390
  __cil_tmp24 = (char const   *)0;
#line 390
  __cil_tmp25 = (char const   *)0;
#line 390
  __cil_tmp26 = (int )val;
#line 390
  drm_ut_debug_printk(4U, __cil_tmp24, __cil_tmp25, "VR83: 0x%04x\n", __cil_tmp26);
#line 391
  ivch_read(dvo, 132, & val);
#line 392
  __cil_tmp27 = (char const   *)0;
#line 392
  __cil_tmp28 = (char const   *)0;
#line 392
  __cil_tmp29 = (int )val;
#line 392
  drm_ut_debug_printk(4U, __cil_tmp27, __cil_tmp28, "VR84: 0x%04x\n", __cil_tmp29);
#line 393
  ivch_read(dvo, 133, & val);
#line 394
  __cil_tmp30 = (char const   *)0;
#line 394
  __cil_tmp31 = (char const   *)0;
#line 394
  __cil_tmp32 = (int )val;
#line 394
  drm_ut_debug_printk(4U, __cil_tmp30, __cil_tmp31, "VR85: 0x%04x\n", __cil_tmp32);
#line 395
  ivch_read(dvo, 134, & val);
#line 396
  __cil_tmp33 = (char const   *)0;
#line 396
  __cil_tmp34 = (char const   *)0;
#line 396
  __cil_tmp35 = (int )val;
#line 396
  drm_ut_debug_printk(4U, __cil_tmp33, __cil_tmp34, "VR86: 0x%04x\n", __cil_tmp35);
#line 397
  ivch_read(dvo, 135, & val);
#line 398
  __cil_tmp36 = (char const   *)0;
#line 398
  __cil_tmp37 = (char const   *)0;
#line 398
  __cil_tmp38 = (int )val;
#line 398
  drm_ut_debug_printk(4U, __cil_tmp36, __cil_tmp37, "VR87: 0x%04x\n", __cil_tmp38);
#line 399
  ivch_read(dvo, 136, & val);
#line 400
  __cil_tmp39 = (char const   *)0;
#line 400
  __cil_tmp40 = (char const   *)0;
#line 400
  __cil_tmp41 = (int )val;
#line 400
  drm_ut_debug_printk(4U, __cil_tmp39, __cil_tmp40, "VR88: 0x%04x\n", __cil_tmp41);
#line 403
  ivch_read(dvo, 142, & val);
#line 404
  __cil_tmp42 = (char const   *)0;
#line 404
  __cil_tmp43 = (char const   *)0;
#line 404
  __cil_tmp44 = (int )val;
#line 404
  drm_ut_debug_printk(4U, __cil_tmp42, __cil_tmp43, "VR8E: 0x%04x\n", __cil_tmp44);
#line 407
  ivch_read(dvo, 143, & val);
#line 408
  __cil_tmp45 = (char const   *)0;
#line 408
  __cil_tmp46 = (char const   *)0;
#line 408
  __cil_tmp47 = (int )val;
#line 408
  drm_ut_debug_printk(4U, __cil_tmp45, __cil_tmp46, "VR8F: 0x%04x\n", __cil_tmp47);
  }
#line 409
  return;
}
}
#line 411 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
static void ivch_destroy(struct intel_dvo_device *dvo ) 
{ struct ivch_priv *priv ;
  void *__cil_tmp3 ;
  struct ivch_priv *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  void const   *__cil_tmp7 ;

  {
#line 413
  __cil_tmp3 = dvo->dev_priv;
#line 413
  priv = (struct ivch_priv *)__cil_tmp3;
  {
#line 415
  __cil_tmp4 = (struct ivch_priv *)0;
#line 415
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 415
  __cil_tmp6 = (unsigned long )priv;
#line 415
  if (__cil_tmp6 != __cil_tmp5) {
    {
#line 416
    __cil_tmp7 = (void const   *)priv;
#line 416
    kfree(__cil_tmp7);
#line 417
    dvo->dev_priv = (void *)0;
    }
  } else {

  }
  }
#line 419
  return;
}
}
#line 421 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_ivch.c.p"
struct intel_dvo_dev_ops ivch_ops  = 
#line 421
     {& ivch_init, (void (*)(struct intel_dvo_device * ))0, & ivch_dpms, (int (*)(struct intel_dvo_device * ,
                                                                                struct drm_display_mode * ))(& ivch_mode_valid),
    (bool (*)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ))0,
    (void (*)(struct intel_dvo_device * ))0, (void (*)(struct intel_dvo_device * ))0,
    & ivch_mode_set, & ivch_detect, (struct drm_display_mode *(*)(struct intel_dvo_device * ))0,
    & ivch_destroy, & ivch_dump_regs};
#line 101 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static bool tfp410_readb(struct intel_dvo_device *dvo , int addr , uint8_t *ch ) 
{ struct tfp410_priv *tfp ;
  struct i2c_adapter *adapter ;
  u8 out_buf[2U] ;
  u8 in_buf[2U] ;
  struct i2c_msg msgs[2U] ;
  int tmp ;
  void *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  struct i2c_msg *__cil_tmp13 ;
  bool __cil_tmp14 ;
  char (*__cil_tmp15)[48U] ;
  char *__cil_tmp16 ;
  int __cil_tmp17 ;

  {
  {
#line 103
  __cil_tmp10 = dvo->dev_priv;
#line 103
  tfp = (struct tfp410_priv *)__cil_tmp10;
#line 104
  adapter = dvo->i2c_bus;
#line 108
  __cil_tmp11 = dvo->slave_addr;
#line 108
  msgs[0].addr = (unsigned short )__cil_tmp11;
#line 108
  msgs[0].flags = (__u16 )0U;
#line 108
  msgs[0].len = (__u16 )1U;
#line 108
  msgs[0].buf = (__u8 *)(& out_buf);
#line 108
  __cil_tmp12 = dvo->slave_addr;
#line 108
  msgs[1].addr = (unsigned short )__cil_tmp12;
#line 108
  msgs[1].flags = (__u16 )1U;
#line 108
  msgs[1].len = (__u16 )1U;
#line 108
  msgs[1].buf = (__u8 *)(& in_buf);
#line 123
  out_buf[0] = (u8 )addr;
#line 124
  out_buf[1] = (u8 )0U;
#line 126
  __cil_tmp13 = (struct i2c_msg *)(& msgs);
#line 126
  tmp = i2c_transfer(adapter, __cil_tmp13, 2);
  }
#line 126
  if (tmp == 2) {
#line 127
    *ch = in_buf[0];
#line 128
    return ((bool )1);
  } else {

  }
  {
#line 131
  __cil_tmp14 = tfp->quiet;
#line 131
  if (! __cil_tmp14) {
    {
#line 132
    __cil_tmp15 = & adapter->name;
#line 132
    __cil_tmp16 = (char *)__cil_tmp15;
#line 132
    __cil_tmp17 = dvo->slave_addr;
#line 132
    drm_ut_debug_printk(4U, "drm", "tfp410_readb", "Unable to read register 0x%02x from %s:%02x.\n",
                        addr, __cil_tmp16, __cil_tmp17);
    }
  } else {

  }
  }
#line 135
  return ((bool )0);
}
}
#line 138 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static bool tfp410_writeb(struct intel_dvo_device *dvo , int addr , uint8_t ch ) 
{ struct tfp410_priv *tfp ;
  struct i2c_adapter *adapter ;
  uint8_t out_buf[2U] ;
  struct i2c_msg msg ;
  int tmp ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  bool __cil_tmp11 ;
  char (*__cil_tmp12)[48U] ;
  char *__cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 140
  __cil_tmp9 = dvo->dev_priv;
#line 140
  tfp = (struct tfp410_priv *)__cil_tmp9;
#line 141
  adapter = dvo->i2c_bus;
#line 143
  __cil_tmp10 = dvo->slave_addr;
#line 143
  msg.addr = (unsigned short )__cil_tmp10;
#line 143
  msg.flags = (__u16 )0U;
#line 143
  msg.len = (__u16 )2U;
#line 143
  msg.buf = (__u8 *)(& out_buf);
#line 150
  out_buf[0] = (uint8_t )addr;
#line 151
  out_buf[1] = ch;
#line 153
  tmp = i2c_transfer(adapter, & msg, 1);
  }
#line 153
  if (tmp == 1) {
#line 154
    return ((bool )1);
  } else {

  }
  {
#line 156
  __cil_tmp11 = tfp->quiet;
#line 156
  if (! __cil_tmp11) {
    {
#line 157
    __cil_tmp12 = & adapter->name;
#line 157
    __cil_tmp13 = (char *)__cil_tmp12;
#line 157
    __cil_tmp14 = dvo->slave_addr;
#line 157
    drm_ut_debug_printk(4U, "drm", "tfp410_writeb", "Unable to write register 0x%02x to %s:%d.\n",
                        addr, __cil_tmp13, __cil_tmp14);
    }
  } else {

  }
  }
#line 161
  return ((bool )0);
}
}
#line 164 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static int tfp410_getid(struct intel_dvo_device *dvo , int addr ) 
{ uint8_t ch1 ;
  uint8_t ch2 ;
  bool tmp ;
  bool tmp___0 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;

  {
  {
#line 168
  tmp = tfp410_readb(dvo, addr, & ch1);
  }
#line 168
  if ((int )tmp) {
    {
#line 168
    __cil_tmp7 = addr + 1;
#line 168
    tmp___0 = tfp410_readb(dvo, __cil_tmp7, & ch2);
    }
#line 168
    if ((int )tmp___0) {
      {
#line 170
      __cil_tmp8 = (int )ch1;
#line 170
      __cil_tmp9 = (int )ch2;
#line 170
      __cil_tmp10 = __cil_tmp9 << 8;
#line 170
      __cil_tmp11 = __cil_tmp10 & 65535;
#line 170
      return (__cil_tmp11 | __cil_tmp8);
      }
    } else {

    }
  } else {

  }
#line 172
  return (-1);
}
}
#line 176 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static bool tfp410_init(struct intel_dvo_device *dvo , struct i2c_adapter *adapter ) 
{ struct tfp410_priv *tfp ;
  int id ;
  void *tmp ;
  struct tfp410_priv *__cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  char (*__cil_tmp9)[48U] ;
  char *__cil_tmp10 ;
  int __cil_tmp11 ;
  char (*__cil_tmp12)[48U] ;
  char *__cil_tmp13 ;
  int __cil_tmp14 ;
  void const   *__cil_tmp15 ;

  {
  {
#line 183
  tmp = kzalloc(1UL, 208U);
#line 183
  tfp = (struct tfp410_priv *)tmp;
  }
  {
#line 184
  __cil_tmp6 = (struct tfp410_priv *)0;
#line 184
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 184
  __cil_tmp8 = (unsigned long )tfp;
#line 184
  if (__cil_tmp8 == __cil_tmp7) {
#line 185
    return ((bool )0);
  } else {

  }
  }
  {
#line 187
  dvo->i2c_bus = adapter;
#line 188
  dvo->dev_priv = (void *)tfp;
#line 189
  tfp->quiet = (bool )1;
#line 191
  id = tfp410_getid(dvo, 0);
  }
#line 191
  if (id != 332) {
    {
#line 192
    __cil_tmp9 = & adapter->name;
#line 192
    __cil_tmp10 = (char *)__cil_tmp9;
#line 192
    __cil_tmp11 = dvo->slave_addr;
#line 192
    drm_ut_debug_printk(4U, "drm", "tfp410_init", "tfp410 not detected got VID %X: from %s Slave %d.\n",
                        id, __cil_tmp10, __cil_tmp11);
    }
#line 195
    goto out;
  } else {

  }
  {
#line 198
  id = tfp410_getid(dvo, 2);
  }
#line 198
  if (id != 1040) {
    {
#line 199
    __cil_tmp12 = & adapter->name;
#line 199
    __cil_tmp13 = (char *)__cil_tmp12;
#line 199
    __cil_tmp14 = dvo->slave_addr;
#line 199
    drm_ut_debug_printk(4U, "drm", "tfp410_init", "tfp410 not detected got DID %X: from %s Slave %d.\n",
                        id, __cil_tmp13, __cil_tmp14);
    }
#line 202
    goto out;
  } else {

  }
#line 204
  tfp->quiet = (bool )0;
#line 205
  return ((bool )1);
  out: 
  {
#line 207
  __cil_tmp15 = (void const   *)tfp;
#line 207
  kfree(__cil_tmp15);
  }
#line 208
  return ((bool )0);
}
}
#line 211 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo ) 
{ enum drm_connector_status ret ;
  uint8_t ctl2 ;
  bool tmp ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;

  {
  {
#line 213
  ret = (enum drm_connector_status )2;
#line 216
  tmp = tfp410_readb(dvo, 9, & ctl2);
  }
#line 216
  if ((int )tmp) {
    {
#line 217
    __cil_tmp5 = (int )ctl2;
#line 217
    __cil_tmp6 = __cil_tmp5 & 4;
#line 217
    if (__cil_tmp6 != 0) {
#line 218
      ret = (enum drm_connector_status )1;
    } else {
#line 220
      ret = (enum drm_connector_status )2;
    }
    }
  } else {

  }
#line 223
  return (ret);
}
}
#line 226 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo , struct drm_display_mode *mode ) 
{ 

  {
#line 229
  return ((enum drm_mode_status )0);
}
}
#line 232 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static void tfp410_mode_set(struct intel_dvo_device *dvo , struct drm_display_mode *mode ,
                            struct drm_display_mode *adjusted_mode ) 
{ 

  {
#line 241
  return;
}
}
#line 245 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static void tfp410_dpms(struct intel_dvo_device *dvo , int mode ) 
{ uint8_t ctl1 ;
  bool tmp ;
  int tmp___0 ;
  unsigned int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  int __cil_tmp10 ;
  uint8_t __cil_tmp11 ;

  {
  {
#line 249
  tmp = tfp410_readb(dvo, 8, & ctl1);
  }
#line 249
  if (tmp) {
#line 249
    tmp___0 = 0;
  } else {
#line 249
    tmp___0 = 1;
  }
#line 249
  if (tmp___0) {
#line 250
    return;
  } else {

  }
#line 252
  if (mode == 0) {
#line 253
    __cil_tmp6 = (unsigned int )ctl1;
#line 253
    __cil_tmp7 = __cil_tmp6 | 1U;
#line 253
    ctl1 = (uint8_t )__cil_tmp7;
  } else {
#line 255
    __cil_tmp8 = (unsigned int )ctl1;
#line 255
    __cil_tmp9 = __cil_tmp8 & 254U;
#line 255
    ctl1 = (uint8_t )__cil_tmp9;
  }
  {
#line 257
  __cil_tmp10 = (int )ctl1;
#line 257
  __cil_tmp11 = (uint8_t )__cil_tmp10;
#line 257
  tfp410_writeb(dvo, 8, __cil_tmp11);
  }
#line 258
  return;
}
}
#line 260 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static void tfp410_dump_regs(struct intel_dvo_device *dvo ) 
{ uint8_t val ;
  uint8_t val2 ;
  char const   *__cil_tmp4 ;
  char const   *__cil_tmp5 ;
  int __cil_tmp6 ;
  char const   *__cil_tmp7 ;
  char const   *__cil_tmp8 ;
  int __cil_tmp9 ;
  char const   *__cil_tmp10 ;
  char const   *__cil_tmp11 ;
  int __cil_tmp12 ;
  char const   *__cil_tmp13 ;
  char const   *__cil_tmp14 ;
  int __cil_tmp15 ;
  char const   *__cil_tmp16 ;
  char const   *__cil_tmp17 ;
  int __cil_tmp18 ;
  char const   *__cil_tmp19 ;
  char const   *__cil_tmp20 ;
  int __cil_tmp21 ;
  char const   *__cil_tmp22 ;
  char const   *__cil_tmp23 ;
  int __cil_tmp24 ;
  char const   *__cil_tmp25 ;
  char const   *__cil_tmp26 ;
  int __cil_tmp27 ;
  char const   *__cil_tmp28 ;
  char const   *__cil_tmp29 ;
  int __cil_tmp30 ;
  int __cil_tmp31 ;
  char const   *__cil_tmp32 ;
  char const   *__cil_tmp33 ;
  int __cil_tmp34 ;
  int __cil_tmp35 ;
  char const   *__cil_tmp36 ;
  char const   *__cil_tmp37 ;
  int __cil_tmp38 ;
  int __cil_tmp39 ;
  char const   *__cil_tmp40 ;
  char const   *__cil_tmp41 ;
  int __cil_tmp42 ;
  int __cil_tmp43 ;

  {
  {
#line 264
  tfp410_readb(dvo, 4, & val);
#line 265
  __cil_tmp4 = (char const   *)0;
#line 265
  __cil_tmp5 = (char const   *)0;
#line 265
  __cil_tmp6 = (int )val;
#line 265
  drm_ut_debug_printk(4U, __cil_tmp4, __cil_tmp5, "TFP410_REV: 0x%02X\n", __cil_tmp6);
#line 266
  tfp410_readb(dvo, 8, & val);
#line 267
  __cil_tmp7 = (char const   *)0;
#line 267
  __cil_tmp8 = (char const   *)0;
#line 267
  __cil_tmp9 = (int )val;
#line 267
  drm_ut_debug_printk(4U, __cil_tmp7, __cil_tmp8, "TFP410_CTL1: 0x%02X\n", __cil_tmp9);
#line 268
  tfp410_readb(dvo, 9, & val);
#line 269
  __cil_tmp10 = (char const   *)0;
#line 269
  __cil_tmp11 = (char const   *)0;
#line 269
  __cil_tmp12 = (int )val;
#line 269
  drm_ut_debug_printk(4U, __cil_tmp10, __cil_tmp11, "TFP410_CTL2: 0x%02X\n", __cil_tmp12);
#line 270
  tfp410_readb(dvo, 10, & val);
#line 271
  __cil_tmp13 = (char const   *)0;
#line 271
  __cil_tmp14 = (char const   *)0;
#line 271
  __cil_tmp15 = (int )val;
#line 271
  drm_ut_debug_printk(4U, __cil_tmp13, __cil_tmp14, "TFP410_CTL3: 0x%02X\n", __cil_tmp15);
#line 272
  tfp410_readb(dvo, 11, & val);
#line 273
  __cil_tmp16 = (char const   *)0;
#line 273
  __cil_tmp17 = (char const   *)0;
#line 273
  __cil_tmp18 = (int )val;
#line 273
  drm_ut_debug_printk(4U, __cil_tmp16, __cil_tmp17, "TFP410_USERCFG: 0x%02X\n", __cil_tmp18);
#line 274
  tfp410_readb(dvo, 50, & val);
#line 275
  __cil_tmp19 = (char const   *)0;
#line 275
  __cil_tmp20 = (char const   *)0;
#line 275
  __cil_tmp21 = (int )val;
#line 275
  drm_ut_debug_printk(4U, __cil_tmp19, __cil_tmp20, "TFP410_DE_DLY: 0x%02X\n", __cil_tmp21);
#line 276
  tfp410_readb(dvo, 51, & val);
#line 277
  __cil_tmp22 = (char const   *)0;
#line 277
  __cil_tmp23 = (char const   *)0;
#line 277
  __cil_tmp24 = (int )val;
#line 277
  drm_ut_debug_printk(4U, __cil_tmp22, __cil_tmp23, "TFP410_DE_CTL: 0x%02X\n", __cil_tmp24);
#line 278
  tfp410_readb(dvo, 52, & val);
#line 279
  __cil_tmp25 = (char const   *)0;
#line 279
  __cil_tmp26 = (char const   *)0;
#line 279
  __cil_tmp27 = (int )val;
#line 279
  drm_ut_debug_printk(4U, __cil_tmp25, __cil_tmp26, "TFP410_DE_TOP: 0x%02X\n", __cil_tmp27);
#line 280
  tfp410_readb(dvo, 54, & val);
#line 281
  tfp410_readb(dvo, 55, & val2);
#line 282
  __cil_tmp28 = (char const   *)0;
#line 282
  __cil_tmp29 = (char const   *)0;
#line 282
  __cil_tmp30 = (int )val2;
#line 282
  __cil_tmp31 = (int )val;
#line 282
  drm_ut_debug_printk(4U, __cil_tmp28, __cil_tmp29, "TFP410_DE_CNT: 0x%02X%02X\n",
                      __cil_tmp30, __cil_tmp31);
#line 283
  tfp410_readb(dvo, 56, & val);
#line 284
  tfp410_readb(dvo, 57, & val2);
#line 285
  __cil_tmp32 = (char const   *)0;
#line 285
  __cil_tmp33 = (char const   *)0;
#line 285
  __cil_tmp34 = (int )val2;
#line 285
  __cil_tmp35 = (int )val;
#line 285
  drm_ut_debug_printk(4U, __cil_tmp32, __cil_tmp33, "TFP410_DE_LIN: 0x%02X%02X\n",
                      __cil_tmp34, __cil_tmp35);
#line 286
  tfp410_readb(dvo, 58, & val);
#line 287
  tfp410_readb(dvo, 59, & val2);
#line 288
  __cil_tmp36 = (char const   *)0;
#line 288
  __cil_tmp37 = (char const   *)0;
#line 288
  __cil_tmp38 = (int )val2;
#line 288
  __cil_tmp39 = (int )val;
#line 288
  drm_ut_debug_printk(4U, __cil_tmp36, __cil_tmp37, "TFP410_H_RES: 0x%02X%02X\n",
                      __cil_tmp38, __cil_tmp39);
#line 289
  tfp410_readb(dvo, 60, & val);
#line 290
  tfp410_readb(dvo, 61, & val2);
#line 291
  __cil_tmp40 = (char const   *)0;
#line 291
  __cil_tmp41 = (char const   *)0;
#line 291
  __cil_tmp42 = (int )val2;
#line 291
  __cil_tmp43 = (int )val;
#line 291
  drm_ut_debug_printk(4U, __cil_tmp40, __cil_tmp41, "TFP410_V_RES: 0x%02X%02X\n",
                      __cil_tmp42, __cil_tmp43);
  }
#line 292
  return;
}
}
#line 294 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
static void tfp410_destroy(struct intel_dvo_device *dvo ) 
{ struct tfp410_priv *tfp ;
  void *__cil_tmp3 ;
  struct tfp410_priv *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  void const   *__cil_tmp7 ;

  {
#line 296
  __cil_tmp3 = dvo->dev_priv;
#line 296
  tfp = (struct tfp410_priv *)__cil_tmp3;
  {
#line 298
  __cil_tmp4 = (struct tfp410_priv *)0;
#line 298
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 298
  __cil_tmp6 = (unsigned long )tfp;
#line 298
  if (__cil_tmp6 != __cil_tmp5) {
    {
#line 299
    __cil_tmp7 = (void const   *)tfp;
#line 299
    kfree(__cil_tmp7);
#line 300
    dvo->dev_priv = (void *)0;
    }
  } else {

  }
  }
#line 302
  return;
}
}
#line 304 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_tfp410.c.p"
struct intel_dvo_dev_ops tfp410_ops  = 
#line 304
     {& tfp410_init, (void (*)(struct intel_dvo_device * ))0, & tfp410_dpms, (int (*)(struct intel_dvo_device * ,
                                                                                    struct drm_display_mode * ))(& tfp410_mode_valid),
    (bool (*)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ))0,
    (void (*)(struct intel_dvo_device * ))0, (void (*)(struct intel_dvo_device * ))0,
    & tfp410_mode_set, & tfp410_detect, (struct drm_display_mode *(*)(struct intel_dvo_device * ))0,
    & tfp410_destroy, & tfp410_dump_regs};
#line 76 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static bool sil164_readb(struct intel_dvo_device *dvo , int addr , uint8_t *ch ) 
{ struct sil164_priv *sil ;
  struct i2c_adapter *adapter ;
  u8 out_buf[2U] ;
  u8 in_buf[2U] ;
  struct i2c_msg msgs[2U] ;
  int tmp ;
  void *__cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  struct i2c_msg *__cil_tmp13 ;
  bool __cil_tmp14 ;
  char (*__cil_tmp15)[48U] ;
  char *__cil_tmp16 ;
  int __cil_tmp17 ;

  {
  {
#line 78
  __cil_tmp10 = dvo->dev_priv;
#line 78
  sil = (struct sil164_priv *)__cil_tmp10;
#line 79
  adapter = dvo->i2c_bus;
#line 83
  __cil_tmp11 = dvo->slave_addr;
#line 83
  msgs[0].addr = (unsigned short )__cil_tmp11;
#line 83
  msgs[0].flags = (__u16 )0U;
#line 83
  msgs[0].len = (__u16 )1U;
#line 83
  msgs[0].buf = (__u8 *)(& out_buf);
#line 83
  __cil_tmp12 = dvo->slave_addr;
#line 83
  msgs[1].addr = (unsigned short )__cil_tmp12;
#line 83
  msgs[1].flags = (__u16 )1U;
#line 83
  msgs[1].len = (__u16 )1U;
#line 83
  msgs[1].buf = (__u8 *)(& in_buf);
#line 98
  out_buf[0] = (u8 )addr;
#line 99
  out_buf[1] = (u8 )0U;
#line 101
  __cil_tmp13 = (struct i2c_msg *)(& msgs);
#line 101
  tmp = i2c_transfer(adapter, __cil_tmp13, 2);
  }
#line 101
  if (tmp == 2) {
#line 102
    *ch = in_buf[0];
#line 103
    return ((bool )1);
  } else {

  }
  {
#line 106
  __cil_tmp14 = sil->quiet;
#line 106
  if (! __cil_tmp14) {
    {
#line 107
    __cil_tmp15 = & adapter->name;
#line 107
    __cil_tmp16 = (char *)__cil_tmp15;
#line 107
    __cil_tmp17 = dvo->slave_addr;
#line 107
    drm_ut_debug_printk(4U, "drm", "sil164_readb", "Unable to read register 0x%02x from %s:%02x.\n",
                        addr, __cil_tmp16, __cil_tmp17);
    }
  } else {

  }
  }
#line 110
  return ((bool )0);
}
}
#line 113 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static bool sil164_writeb(struct intel_dvo_device *dvo , int addr , uint8_t ch ) 
{ struct sil164_priv *sil ;
  struct i2c_adapter *adapter ;
  uint8_t out_buf[2U] ;
  struct i2c_msg msg ;
  int tmp ;
  void *__cil_tmp9 ;
  int __cil_tmp10 ;
  bool __cil_tmp11 ;
  char (*__cil_tmp12)[48U] ;
  char *__cil_tmp13 ;
  int __cil_tmp14 ;

  {
  {
#line 115
  __cil_tmp9 = dvo->dev_priv;
#line 115
  sil = (struct sil164_priv *)__cil_tmp9;
#line 116
  adapter = dvo->i2c_bus;
#line 118
  __cil_tmp10 = dvo->slave_addr;
#line 118
  msg.addr = (unsigned short )__cil_tmp10;
#line 118
  msg.flags = (__u16 )0U;
#line 118
  msg.len = (__u16 )2U;
#line 118
  msg.buf = (__u8 *)(& out_buf);
#line 125
  out_buf[0] = (uint8_t )addr;
#line 126
  out_buf[1] = ch;
#line 128
  tmp = i2c_transfer(adapter, & msg, 1);
  }
#line 128
  if (tmp == 1) {
#line 129
    return ((bool )1);
  } else {

  }
  {
#line 131
  __cil_tmp11 = sil->quiet;
#line 131
  if (! __cil_tmp11) {
    {
#line 132
    __cil_tmp12 = & adapter->name;
#line 132
    __cil_tmp13 = (char *)__cil_tmp12;
#line 132
    __cil_tmp14 = dvo->slave_addr;
#line 132
    drm_ut_debug_printk(4U, "drm", "sil164_writeb", "Unable to write register 0x%02x to %s:%d.\n",
                        addr, __cil_tmp13, __cil_tmp14);
    }
  } else {

  }
  }
#line 136
  return ((bool )0);
}
}
#line 140 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static bool sil164_init(struct intel_dvo_device *dvo , struct i2c_adapter *adapter ) 
{ struct sil164_priv *sil ;
  unsigned char ch ;
  void *tmp ;
  bool tmp___0 ;
  int tmp___1 ;
  bool tmp___2 ;
  int tmp___3 ;
  struct sil164_priv *__cil_tmp10 ;
  unsigned long __cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned int __cil_tmp13 ;
  int __cil_tmp14 ;
  char (*__cil_tmp15)[48U] ;
  char *__cil_tmp16 ;
  int __cil_tmp17 ;
  unsigned int __cil_tmp18 ;
  int __cil_tmp19 ;
  char (*__cil_tmp20)[48U] ;
  char *__cil_tmp21 ;
  int __cil_tmp22 ;
  void const   *__cil_tmp23 ;

  {
  {
#line 147
  tmp = kzalloc(1UL, 208U);
#line 147
  sil = (struct sil164_priv *)tmp;
  }
  {
#line 148
  __cil_tmp10 = (struct sil164_priv *)0;
#line 148
  __cil_tmp11 = (unsigned long )__cil_tmp10;
#line 148
  __cil_tmp12 = (unsigned long )sil;
#line 148
  if (__cil_tmp12 == __cil_tmp11) {
#line 149
    return ((bool )0);
  } else {

  }
  }
  {
#line 151
  dvo->i2c_bus = adapter;
#line 152
  dvo->dev_priv = (void *)sil;
#line 153
  sil->quiet = (bool )1;
#line 155
  tmp___0 = sil164_readb(dvo, 0, & ch);
  }
#line 155
  if (tmp___0) {
#line 155
    tmp___1 = 0;
  } else {
#line 155
    tmp___1 = 1;
  }
#line 155
  if (tmp___1) {
#line 156
    goto out;
  } else {

  }
  {
#line 158
  __cil_tmp13 = (unsigned int )ch;
#line 158
  if (__cil_tmp13 != 1U) {
    {
#line 159
    __cil_tmp14 = (int )ch;
#line 159
    __cil_tmp15 = & adapter->name;
#line 159
    __cil_tmp16 = (char *)__cil_tmp15;
#line 159
    __cil_tmp17 = dvo->slave_addr;
#line 159
    drm_ut_debug_printk(4U, "drm", "sil164_init", "sil164 not detected got %d: from %s Slave %d.\n",
                        __cil_tmp14, __cil_tmp16, __cil_tmp17);
    }
#line 161
    goto out;
  } else {

  }
  }
  {
#line 164
  tmp___2 = sil164_readb(dvo, 2, & ch);
  }
#line 164
  if (tmp___2) {
#line 164
    tmp___3 = 0;
  } else {
#line 164
    tmp___3 = 1;
  }
#line 164
  if (tmp___3) {
#line 165
    goto out;
  } else {

  }
  {
#line 167
  __cil_tmp18 = (unsigned int )ch;
#line 167
  if (__cil_tmp18 != 6U) {
    {
#line 168
    __cil_tmp19 = (int )ch;
#line 168
    __cil_tmp20 = & adapter->name;
#line 168
    __cil_tmp21 = (char *)__cil_tmp20;
#line 168
    __cil_tmp22 = dvo->slave_addr;
#line 168
    drm_ut_debug_printk(4U, "drm", "sil164_init", "sil164 not detected got %d: from %s Slave %d.\n",
                        __cil_tmp19, __cil_tmp21, __cil_tmp22);
    }
#line 170
    goto out;
  } else {

  }
  }
  {
#line 172
  sil->quiet = (bool )0;
#line 174
  drm_ut_debug_printk(4U, "drm", "sil164_init", "init sil164 dvo controller successfully!\n");
  }
#line 175
  return ((bool )1);
  out: 
  {
#line 178
  __cil_tmp23 = (void const   *)sil;
#line 178
  kfree(__cil_tmp23);
  }
#line 179
  return ((bool )0);
}
}
#line 182 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static enum drm_connector_status sil164_detect(struct intel_dvo_device *dvo ) 
{ uint8_t reg9 ;
  int __cil_tmp3 ;
  int __cil_tmp4 ;

  {
  {
#line 186
  sil164_readb(dvo, 9, & reg9);
  }
  {
#line 188
  __cil_tmp3 = (int )reg9;
#line 188
  __cil_tmp4 = __cil_tmp3 & 2;
#line 188
  if (__cil_tmp4 != 0) {
#line 189
    return ((enum drm_connector_status )1);
  } else {
#line 191
    return ((enum drm_connector_status )2);
  }
  }
}
}
#line 194 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static enum drm_mode_status sil164_mode_valid(struct intel_dvo_device *dvo , struct drm_display_mode *mode ) 
{ 

  {
#line 197
  return ((enum drm_mode_status )0);
}
}
#line 200 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static void sil164_mode_set(struct intel_dvo_device *dvo , struct drm_display_mode *mode ,
                            struct drm_display_mode *adjusted_mode ) 
{ 

  {
#line 215
  return;
}
}
#line 219 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static void sil164_dpms(struct intel_dvo_device *dvo , int mode ) 
{ int ret ;
  unsigned char ch ;
  bool tmp ;
  unsigned int __cil_tmp6 ;
  unsigned int __cil_tmp7 ;
  unsigned int __cil_tmp8 ;
  unsigned int __cil_tmp9 ;
  int __cil_tmp10 ;
  uint8_t __cil_tmp11 ;

  {
  {
#line 224
  tmp = sil164_readb(dvo, 8, & ch);
#line 224
  ret = (int )tmp;
  }
#line 225
  if (ret == 0) {
#line 226
    return;
  } else {

  }
#line 228
  if (mode == 0) {
#line 229
    __cil_tmp6 = (unsigned int )ch;
#line 229
    __cil_tmp7 = __cil_tmp6 | 1U;
#line 229
    ch = (unsigned char )__cil_tmp7;
  } else {
#line 231
    __cil_tmp8 = (unsigned int )ch;
#line 231
    __cil_tmp9 = __cil_tmp8 & 254U;
#line 231
    ch = (unsigned char )__cil_tmp9;
  }
  {
#line 233
  __cil_tmp10 = (int )ch;
#line 233
  __cil_tmp11 = (uint8_t )__cil_tmp10;
#line 233
  sil164_writeb(dvo, 8, __cil_tmp11);
  }
#line 234
  return;
}
}
#line 237 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static void sil164_dump_regs(struct intel_dvo_device *dvo ) 
{ uint8_t val ;
  char const   *__cil_tmp3 ;
  char const   *__cil_tmp4 ;
  int __cil_tmp5 ;
  char const   *__cil_tmp6 ;
  char const   *__cil_tmp7 ;
  int __cil_tmp8 ;
  char const   *__cil_tmp9 ;
  char const   *__cil_tmp10 ;
  int __cil_tmp11 ;
  char const   *__cil_tmp12 ;
  char const   *__cil_tmp13 ;
  int __cil_tmp14 ;
  char const   *__cil_tmp15 ;
  char const   *__cil_tmp16 ;
  int __cil_tmp17 ;

  {
  {
#line 241
  sil164_readb(dvo, 6, & val);
#line 242
  __cil_tmp3 = (char const   *)0;
#line 242
  __cil_tmp4 = (char const   *)0;
#line 242
  __cil_tmp5 = (int )val;
#line 242
  drm_ut_debug_printk(4U, __cil_tmp3, __cil_tmp4, "SIL164_FREQ_LO: 0x%02x\n", __cil_tmp5);
#line 243
  sil164_readb(dvo, 7, & val);
#line 244
  __cil_tmp6 = (char const   *)0;
#line 244
  __cil_tmp7 = (char const   *)0;
#line 244
  __cil_tmp8 = (int )val;
#line 244
  drm_ut_debug_printk(4U, __cil_tmp6, __cil_tmp7, "SIL164_FREQ_HI: 0x%02x\n", __cil_tmp8);
#line 245
  sil164_readb(dvo, 8, & val);
#line 246
  __cil_tmp9 = (char const   *)0;
#line 246
  __cil_tmp10 = (char const   *)0;
#line 246
  __cil_tmp11 = (int )val;
#line 246
  drm_ut_debug_printk(4U, __cil_tmp9, __cil_tmp10, "SIL164_REG8: 0x%02x\n", __cil_tmp11);
#line 247
  sil164_readb(dvo, 9, & val);
#line 248
  __cil_tmp12 = (char const   *)0;
#line 248
  __cil_tmp13 = (char const   *)0;
#line 248
  __cil_tmp14 = (int )val;
#line 248
  drm_ut_debug_printk(4U, __cil_tmp12, __cil_tmp13, "SIL164_REG9: 0x%02x\n", __cil_tmp14);
#line 249
  sil164_readb(dvo, 12, & val);
#line 250
  __cil_tmp15 = (char const   *)0;
#line 250
  __cil_tmp16 = (char const   *)0;
#line 250
  __cil_tmp17 = (int )val;
#line 250
  drm_ut_debug_printk(4U, __cil_tmp15, __cil_tmp16, "SIL164_REGC: 0x%02x\n", __cil_tmp17);
  }
#line 251
  return;
}
}
#line 253 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
static void sil164_destroy(struct intel_dvo_device *dvo ) 
{ struct sil164_priv *sil ;
  void *__cil_tmp3 ;
  struct sil164_priv *__cil_tmp4 ;
  unsigned long __cil_tmp5 ;
  unsigned long __cil_tmp6 ;
  void const   *__cil_tmp7 ;

  {
#line 255
  __cil_tmp3 = dvo->dev_priv;
#line 255
  sil = (struct sil164_priv *)__cil_tmp3;
  {
#line 257
  __cil_tmp4 = (struct sil164_priv *)0;
#line 257
  __cil_tmp5 = (unsigned long )__cil_tmp4;
#line 257
  __cil_tmp6 = (unsigned long )sil;
#line 257
  if (__cil_tmp6 != __cil_tmp5) {
    {
#line 258
    __cil_tmp7 = (void const   *)sil;
#line 258
    kfree(__cil_tmp7);
#line 259
    dvo->dev_priv = (void *)0;
    }
  } else {

  }
  }
#line 261
  return;
}
}
#line 263 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/dvo_sil164.c.p"
struct intel_dvo_dev_ops sil164_ops  = 
#line 263
     {& sil164_init, (void (*)(struct intel_dvo_device * ))0, & sil164_dpms, (int (*)(struct intel_dvo_device * ,
                                                                                    struct drm_display_mode * ))(& sil164_mode_valid),
    (bool (*)(struct intel_dvo_device * , struct drm_display_mode * , struct drm_display_mode * ))0,
    (void (*)(struct intel_dvo_device * ))0, (void (*)(struct intel_dvo_device * ))0,
    & sil164_mode_set, & sil164_detect, (struct drm_display_mode *(*)(struct intel_dvo_device * ))0,
    & sil164_destroy, & sil164_dump_regs};
#line 562 "include/linux/compat.h"
extern void *compat_alloc_user_space(unsigned long  ) ;
#line 1240 "include/drm/drmP.h"
extern long drm_compat_ioctl(struct file * , unsigned int  , unsigned long  ) ;
#line 54 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
static int compat_i915_batchbuffer(struct file *file , unsigned int cmd , unsigned long arg ) 
{ drm_i915_batchbuffer32_t batchbuffer32 ;
  drm_i915_batchbuffer_t *batchbuffer ;
  unsigned long tmp ;
  void *tmp___0 ;
  unsigned long flag ;
  unsigned long roksum ;
  struct thread_info *tmp___1 ;
  long tmp___2 ;
  int __pu_err ;
  int __pu_err___0 ;
  int __pu_err___1 ;
  int __pu_err___2 ;
  int __pu_err___3 ;
  int __pu_err___4 ;
  long tmp___3 ;
  void *__cil_tmp19 ;
  void const   *__cil_tmp20 ;
  int __cil_tmp21 ;
  long __cil_tmp22 ;
  int *__cil_tmp23 ;
  struct __large_struct *__cil_tmp24 ;
  int *__cil_tmp25 ;
  struct __large_struct *__cil_tmp26 ;
  int *__cil_tmp27 ;
  struct __large_struct *__cil_tmp28 ;
  int *__cil_tmp29 ;
  struct __large_struct *__cil_tmp30 ;
  int *__cil_tmp31 ;
  struct __large_struct *__cil_tmp32 ;
  int *__cil_tmp33 ;
  struct __large_struct *__cil_tmp34 ;
  int *__cil_tmp35 ;
  struct __large_struct *__cil_tmp36 ;
  int *__cil_tmp37 ;
  struct __large_struct *__cil_tmp38 ;
  int *__cil_tmp39 ;
  struct __large_struct *__cil_tmp40 ;
  int *__cil_tmp41 ;
  struct __large_struct *__cil_tmp42 ;
  int *__cil_tmp43 ;
  struct __large_struct *__cil_tmp44 ;
  int *__cil_tmp45 ;
  struct __large_struct *__cil_tmp46 ;
  int *__cil_tmp47 ;
  struct __large_struct *__cil_tmp48 ;
  int *__cil_tmp49 ;
  struct __large_struct *__cil_tmp50 ;
  int *__cil_tmp51 ;
  struct __large_struct *__cil_tmp52 ;
  int *__cil_tmp53 ;
  struct __large_struct *__cil_tmp54 ;
  int *__cil_tmp55 ;
  struct __large_struct *__cil_tmp56 ;
  int *__cil_tmp57 ;
  struct __large_struct *__cil_tmp58 ;
  int *__cil_tmp59 ;
  struct __large_struct *__cil_tmp60 ;
  int *__cil_tmp61 ;
  struct __large_struct *__cil_tmp62 ;
  unsigned long __cil_tmp63 ;
  struct drm_clip_rect **__cil_tmp64 ;
  struct __large_struct *__cil_tmp65 ;
  unsigned long __cil_tmp66 ;
  struct drm_clip_rect **__cil_tmp67 ;
  struct __large_struct *__cil_tmp68 ;
  unsigned long __cil_tmp69 ;
  struct drm_clip_rect **__cil_tmp70 ;
  struct __large_struct *__cil_tmp71 ;
  unsigned long __cil_tmp72 ;
  struct drm_clip_rect **__cil_tmp73 ;
  struct __large_struct *__cil_tmp74 ;
  unsigned long __cil_tmp75 ;

  {
  {
#line 60
  __cil_tmp19 = (void *)(& batchbuffer32);
#line 60
  __cil_tmp20 = (void const   *)arg;
#line 60
  tmp = copy_from_user(__cil_tmp19, __cil_tmp20, 24UL);
  }
#line 60
  if (tmp != 0UL) {
#line 62
    return (-14);
  } else {

  }
  {
#line 64
  tmp___0 = compat_alloc_user_space(32UL);
#line 64
  batchbuffer = (drm_i915_batchbuffer_t *)tmp___0;
#line 65
  tmp___1 = current_thread_info();
#line 65
  __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" (batchbuffer),
            "g" (32L), "rm" (tmp___1->addr_limit.seg));
#line 65
  __cil_tmp21 = flag == 0UL;
#line 65
  __cil_tmp22 = (long )__cil_tmp21;
#line 65
  tmp___2 = __builtin_expect(__cil_tmp22, 1L);
  }
#line 72
  if (tmp___2 == 0L) {
#line 74
    return (-14);
  } else {
#line 66
    __pu_err = 0;
#line 66
    if (1) {
#line 66
      goto case_4;
    } else {
#line 66
      goto switch_default;
#line 66
      if (0) {
#line 66
        __cil_tmp23 = & batchbuffer->start;
#line 66
        __cil_tmp24 = (struct __large_struct *)__cil_tmp23;
#line 66
        __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "iq" (batchbuffer32.start),
                             "m" (*__cil_tmp24), "i" (-14), "0" (__pu_err));
#line 66
        goto ldv_34780;
#line 66
        __cil_tmp25 = & batchbuffer->start;
#line 66
        __cil_tmp26 = (struct __large_struct *)__cil_tmp25;
#line 66
        __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (batchbuffer32.start),
                             "m" (*__cil_tmp26), "i" (-14), "0" (__pu_err));
#line 66
        goto ldv_34780;
        case_4: 
#line 66
        __cil_tmp27 = & batchbuffer->start;
#line 66
        __cil_tmp28 = (struct __large_struct *)__cil_tmp27;
#line 66
        __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (batchbuffer32.start),
                             "m" (*__cil_tmp28), "i" (-14), "0" (__pu_err));
#line 66
        goto ldv_34780;
#line 66
        __cil_tmp29 = & batchbuffer->start;
#line 66
        __cil_tmp30 = (struct __large_struct *)__cil_tmp29;
#line 66
        __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "er" (batchbuffer32.start),
                             "m" (*__cil_tmp30), "i" (-14), "0" (__pu_err));
#line 66
        goto ldv_34780;
        switch_default: 
        {
#line 66
        __put_user_bad();
        }
      } else {

      }
    }
    ldv_34780: ;
#line 72
    if (__pu_err != 0) {
#line 74
      return (-14);
    } else {
#line 67
      __pu_err___0 = 0;
#line 67
      if (1) {
#line 67
        goto case_4___0;
      } else {
#line 67
        goto switch_default___0;
#line 67
        if (0) {
#line 67
          __cil_tmp31 = & batchbuffer->used;
#line 67
          __cil_tmp32 = (struct __large_struct *)__cil_tmp31;
#line 67
          __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "iq" (batchbuffer32.used),
                               "m" (*__cil_tmp32), "i" (-14), "0" (__pu_err___0));
#line 67
          goto ldv_34788;
#line 67
          __cil_tmp33 = & batchbuffer->used;
#line 67
          __cil_tmp34 = (struct __large_struct *)__cil_tmp33;
#line 67
          __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (batchbuffer32.used),
                               "m" (*__cil_tmp34), "i" (-14), "0" (__pu_err___0));
#line 67
          goto ldv_34788;
          case_4___0: 
#line 67
          __cil_tmp35 = & batchbuffer->used;
#line 67
          __cil_tmp36 = (struct __large_struct *)__cil_tmp35;
#line 67
          __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (batchbuffer32.used),
                               "m" (*__cil_tmp36), "i" (-14), "0" (__pu_err___0));
#line 67
          goto ldv_34788;
#line 67
          __cil_tmp37 = & batchbuffer->used;
#line 67
          __cil_tmp38 = (struct __large_struct *)__cil_tmp37;
#line 67
          __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "er" (batchbuffer32.used),
                               "m" (*__cil_tmp38), "i" (-14), "0" (__pu_err___0));
#line 67
          goto ldv_34788;
          switch_default___0: 
          {
#line 67
          __put_user_bad();
          }
        } else {

        }
      }
      ldv_34788: ;
#line 72
      if (__pu_err___0 != 0) {
#line 74
        return (-14);
      } else {
#line 68
        __pu_err___1 = 0;
#line 68
        if (1) {
#line 68
          goto case_4___1;
        } else {
#line 68
          goto switch_default___1;
#line 68
          if (0) {
#line 68
            __cil_tmp39 = & batchbuffer->DR1;
#line 68
            __cil_tmp40 = (struct __large_struct *)__cil_tmp39;
#line 68
            __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "iq" (batchbuffer32.DR1),
                                 "m" (*__cil_tmp40), "i" (-14), "0" (__pu_err___1));
#line 68
            goto ldv_34796;
#line 68
            __cil_tmp41 = & batchbuffer->DR1;
#line 68
            __cil_tmp42 = (struct __large_struct *)__cil_tmp41;
#line 68
            __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "ir" (batchbuffer32.DR1),
                                 "m" (*__cil_tmp42), "i" (-14), "0" (__pu_err___1));
#line 68
            goto ldv_34796;
            case_4___1: 
#line 68
            __cil_tmp43 = & batchbuffer->DR1;
#line 68
            __cil_tmp44 = (struct __large_struct *)__cil_tmp43;
#line 68
            __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "ir" (batchbuffer32.DR1),
                                 "m" (*__cil_tmp44), "i" (-14), "0" (__pu_err___1));
#line 68
            goto ldv_34796;
#line 68
            __cil_tmp45 = & batchbuffer->DR1;
#line 68
            __cil_tmp46 = (struct __large_struct *)__cil_tmp45;
#line 68
            __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "er" (batchbuffer32.DR1),
                                 "m" (*__cil_tmp46), "i" (-14), "0" (__pu_err___1));
#line 68
            goto ldv_34796;
            switch_default___1: 
            {
#line 68
            __put_user_bad();
            }
          } else {

          }
        }
        ldv_34796: ;
#line 72
        if (__pu_err___1 != 0) {
#line 74
          return (-14);
        } else {
#line 69
          __pu_err___2 = 0;
#line 69
          if (1) {
#line 69
            goto case_4___2;
          } else {
#line 69
            goto switch_default___2;
#line 69
            if (0) {
#line 69
              __cil_tmp47 = & batchbuffer->DR4;
#line 69
              __cil_tmp48 = (struct __large_struct *)__cil_tmp47;
#line 69
              __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "iq" (batchbuffer32.DR4),
                                   "m" (*__cil_tmp48), "i" (-14), "0" (__pu_err___2));
#line 69
              goto ldv_34804;
#line 69
              __cil_tmp49 = & batchbuffer->DR4;
#line 69
              __cil_tmp50 = (struct __large_struct *)__cil_tmp49;
#line 69
              __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "ir" (batchbuffer32.DR4),
                                   "m" (*__cil_tmp50), "i" (-14), "0" (__pu_err___2));
#line 69
              goto ldv_34804;
              case_4___2: 
#line 69
              __cil_tmp51 = & batchbuffer->DR4;
#line 69
              __cil_tmp52 = (struct __large_struct *)__cil_tmp51;
#line 69
              __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "ir" (batchbuffer32.DR4),
                                   "m" (*__cil_tmp52), "i" (-14), "0" (__pu_err___2));
#line 69
              goto ldv_34804;
#line 69
              __cil_tmp53 = & batchbuffer->DR4;
#line 69
              __cil_tmp54 = (struct __large_struct *)__cil_tmp53;
#line 69
              __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "er" (batchbuffer32.DR4),
                                   "m" (*__cil_tmp54), "i" (-14), "0" (__pu_err___2));
#line 69
              goto ldv_34804;
              switch_default___2: 
              {
#line 69
              __put_user_bad();
              }
            } else {

            }
          }
          ldv_34804: ;
#line 72
          if (__pu_err___2 != 0) {
#line 74
            return (-14);
          } else {
#line 70
            __pu_err___3 = 0;
#line 70
            if (1) {
#line 70
              goto case_4___3;
            } else {
#line 70
              goto switch_default___3;
#line 70
              if (0) {
#line 70
                __cil_tmp55 = & batchbuffer->num_cliprects;
#line 70
                __cil_tmp56 = (struct __large_struct *)__cil_tmp55;
#line 70
                __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "iq" (batchbuffer32.num_cliprects),
                                     "m" (*__cil_tmp56), "i" (-14), "0" (__pu_err___3));
#line 70
                goto ldv_34812;
#line 70
                __cil_tmp57 = & batchbuffer->num_cliprects;
#line 70
                __cil_tmp58 = (struct __large_struct *)__cil_tmp57;
#line 70
                __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "ir" (batchbuffer32.num_cliprects),
                                     "m" (*__cil_tmp58), "i" (-14), "0" (__pu_err___3));
#line 70
                goto ldv_34812;
                case_4___3: 
#line 70
                __cil_tmp59 = & batchbuffer->num_cliprects;
#line 70
                __cil_tmp60 = (struct __large_struct *)__cil_tmp59;
#line 70
                __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "ir" (batchbuffer32.num_cliprects),
                                     "m" (*__cil_tmp60), "i" (-14), "0" (__pu_err___3));
#line 70
                goto ldv_34812;
#line 70
                __cil_tmp61 = & batchbuffer->num_cliprects;
#line 70
                __cil_tmp62 = (struct __large_struct *)__cil_tmp61;
#line 70
                __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "er" (batchbuffer32.num_cliprects),
                                     "m" (*__cil_tmp62), "i" (-14), "0" (__pu_err___3));
#line 70
                goto ldv_34812;
                switch_default___3: 
                {
#line 70
                __put_user_bad();
                }
              } else {

              }
            }
            ldv_34812: ;
#line 72
            if (__pu_err___3 != 0) {
#line 74
              return (-14);
            } else {
#line 72
              __pu_err___4 = 0;
#line 72
              if (1) {
#line 72
                goto case_8___4;
              } else {
#line 72
                goto switch_default___4;
#line 72
                if (0) {
#line 72
                  __cil_tmp63 = (unsigned long )batchbuffer32.cliprects;
#line 72
                  __cil_tmp64 = & batchbuffer->cliprects;
#line 72
                  __cil_tmp65 = (struct __large_struct *)__cil_tmp64;
#line 72
                  __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "iq" ((struct drm_clip_rect *)__cil_tmp63),
                                       "m" (*__cil_tmp65), "i" (-14), "0" (__pu_err___4));
#line 72
                  goto ldv_34820;
#line 72
                  __cil_tmp66 = (unsigned long )batchbuffer32.cliprects;
#line 72
                  __cil_tmp67 = & batchbuffer->cliprects;
#line 72
                  __cil_tmp68 = (struct __large_struct *)__cil_tmp67;
#line 72
                  __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "ir" ((struct drm_clip_rect *)__cil_tmp66),
                                       "m" (*__cil_tmp68), "i" (-14), "0" (__pu_err___4));
#line 72
                  goto ldv_34820;
#line 72
                  __cil_tmp69 = (unsigned long )batchbuffer32.cliprects;
#line 72
                  __cil_tmp70 = & batchbuffer->cliprects;
#line 72
                  __cil_tmp71 = (struct __large_struct *)__cil_tmp70;
#line 72
                  __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "ir" ((struct drm_clip_rect *)__cil_tmp69),
                                       "m" (*__cil_tmp71), "i" (-14), "0" (__pu_err___4));
#line 72
                  goto ldv_34820;
                  case_8___4: 
#line 72
                  __cil_tmp72 = (unsigned long )batchbuffer32.cliprects;
#line 72
                  __cil_tmp73 = & batchbuffer->cliprects;
#line 72
                  __cil_tmp74 = (struct __large_struct *)__cil_tmp73;
#line 72
                  __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "er" ((struct drm_clip_rect *)__cil_tmp72),
                                       "m" (*__cil_tmp74), "i" (-14), "0" (__pu_err___4));
#line 72
                  goto ldv_34820;
                  switch_default___4: 
                  {
#line 72
                  __put_user_bad();
                  }
                } else {

                }
              }
              ldv_34820: ;
#line 72
              if (__pu_err___4 != 0) {
#line 74
                return (-14);
              } else {

              }
            }
          }
        }
      }
    }
  }
  {
#line 76
  __cil_tmp75 = (unsigned long )batchbuffer;
#line 76
  tmp___3 = drm_ioctl(file, 1075864643U, __cil_tmp75);
  }
#line 76
  return ((int )tmp___3);
}
}
#line 89 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
static int compat_i915_cmdbuffer(struct file *file , unsigned int cmd , unsigned long arg ) 
{ drm_i915_cmdbuffer32_t cmdbuffer32 ;
  drm_i915_cmdbuffer_t *cmdbuffer ;
  unsigned long tmp ;
  void *tmp___0 ;
  unsigned long flag ;
  unsigned long roksum ;
  struct thread_info *tmp___1 ;
  long tmp___2 ;
  int __pu_err ;
  int __pu_err___0 ;
  int __pu_err___1 ;
  int __pu_err___2 ;
  int __pu_err___3 ;
  int __pu_err___4 ;
  long tmp___3 ;
  void *__cil_tmp19 ;
  void const   *__cil_tmp20 ;
  int __cil_tmp21 ;
  long __cil_tmp22 ;
  unsigned long __cil_tmp23 ;
  char **__cil_tmp24 ;
  struct __large_struct *__cil_tmp25 ;
  unsigned long __cil_tmp26 ;
  char **__cil_tmp27 ;
  struct __large_struct *__cil_tmp28 ;
  unsigned long __cil_tmp29 ;
  char **__cil_tmp30 ;
  struct __large_struct *__cil_tmp31 ;
  unsigned long __cil_tmp32 ;
  char **__cil_tmp33 ;
  struct __large_struct *__cil_tmp34 ;
  int *__cil_tmp35 ;
  struct __large_struct *__cil_tmp36 ;
  int *__cil_tmp37 ;
  struct __large_struct *__cil_tmp38 ;
  int *__cil_tmp39 ;
  struct __large_struct *__cil_tmp40 ;
  int *__cil_tmp41 ;
  struct __large_struct *__cil_tmp42 ;
  int *__cil_tmp43 ;
  struct __large_struct *__cil_tmp44 ;
  int *__cil_tmp45 ;
  struct __large_struct *__cil_tmp46 ;
  int *__cil_tmp47 ;
  struct __large_struct *__cil_tmp48 ;
  int *__cil_tmp49 ;
  struct __large_struct *__cil_tmp50 ;
  int *__cil_tmp51 ;
  struct __large_struct *__cil_tmp52 ;
  int *__cil_tmp53 ;
  struct __large_struct *__cil_tmp54 ;
  int *__cil_tmp55 ;
  struct __large_struct *__cil_tmp56 ;
  int *__cil_tmp57 ;
  struct __large_struct *__cil_tmp58 ;
  int *__cil_tmp59 ;
  struct __large_struct *__cil_tmp60 ;
  int *__cil_tmp61 ;
  struct __large_struct *__cil_tmp62 ;
  int *__cil_tmp63 ;
  struct __large_struct *__cil_tmp64 ;
  int *__cil_tmp65 ;
  struct __large_struct *__cil_tmp66 ;
  unsigned long __cil_tmp67 ;
  struct drm_clip_rect **__cil_tmp68 ;
  struct __large_struct *__cil_tmp69 ;
  unsigned long __cil_tmp70 ;
  struct drm_clip_rect **__cil_tmp71 ;
  struct __large_struct *__cil_tmp72 ;
  unsigned long __cil_tmp73 ;
  struct drm_clip_rect **__cil_tmp74 ;
  struct __large_struct *__cil_tmp75 ;
  unsigned long __cil_tmp76 ;
  struct drm_clip_rect **__cil_tmp77 ;
  struct __large_struct *__cil_tmp78 ;
  unsigned long __cil_tmp79 ;

  {
  {
#line 95
  __cil_tmp19 = (void *)(& cmdbuffer32);
#line 95
  __cil_tmp20 = (void const   *)arg;
#line 95
  tmp = copy_from_user(__cil_tmp19, __cil_tmp20, 24UL);
  }
#line 95
  if (tmp != 0UL) {
#line 97
    return (-14);
  } else {

  }
  {
#line 99
  tmp___0 = compat_alloc_user_space(32UL);
#line 99
  cmdbuffer = (drm_i915_cmdbuffer_t *)tmp___0;
#line 100
  tmp___1 = current_thread_info();
#line 100
  __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" (cmdbuffer),
            "g" (32L), "rm" (tmp___1->addr_limit.seg));
#line 100
  __cil_tmp21 = flag == 0UL;
#line 100
  __cil_tmp22 = (long )__cil_tmp21;
#line 100
  tmp___2 = __builtin_expect(__cil_tmp22, 1L);
  }
#line 107
  if (tmp___2 == 0L) {
#line 109
    return (-14);
  } else {
#line 101
    __pu_err = 0;
#line 101
    if (1) {
#line 101
      goto case_8;
    } else {
#line 101
      goto switch_default;
#line 101
      if (0) {
#line 101
        __cil_tmp23 = (unsigned long )cmdbuffer32.buf;
#line 101
        __cil_tmp24 = & cmdbuffer->buf;
#line 101
        __cil_tmp25 = (struct __large_struct *)__cil_tmp24;
#line 101
        __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "iq" ((char *)__cil_tmp23),
                             "m" (*__cil_tmp25), "i" (-14), "0" (__pu_err));
#line 101
        goto ldv_34846;
#line 101
        __cil_tmp26 = (unsigned long )cmdbuffer32.buf;
#line 101
        __cil_tmp27 = & cmdbuffer->buf;
#line 101
        __cil_tmp28 = (struct __large_struct *)__cil_tmp27;
#line 101
        __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" ((char *)__cil_tmp26),
                             "m" (*__cil_tmp28), "i" (-14), "0" (__pu_err));
#line 101
        goto ldv_34846;
#line 101
        __cil_tmp29 = (unsigned long )cmdbuffer32.buf;
#line 101
        __cil_tmp30 = & cmdbuffer->buf;
#line 101
        __cil_tmp31 = (struct __large_struct *)__cil_tmp30;
#line 101
        __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" ((char *)__cil_tmp29),
                             "m" (*__cil_tmp31), "i" (-14), "0" (__pu_err));
#line 101
        goto ldv_34846;
        case_8: 
#line 101
        __cil_tmp32 = (unsigned long )cmdbuffer32.buf;
#line 101
        __cil_tmp33 = & cmdbuffer->buf;
#line 101
        __cil_tmp34 = (struct __large_struct *)__cil_tmp33;
#line 101
        __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "er" ((char *)__cil_tmp32),
                             "m" (*__cil_tmp34), "i" (-14), "0" (__pu_err));
#line 101
        goto ldv_34846;
        switch_default: 
        {
#line 101
        __put_user_bad();
        }
      } else {

      }
    }
    ldv_34846: ;
#line 107
    if (__pu_err != 0) {
#line 109
      return (-14);
    } else {
#line 103
      __pu_err___0 = 0;
#line 103
      if (1) {
#line 103
        goto case_4___0;
      } else {
#line 103
        goto switch_default___0;
#line 103
        if (0) {
#line 103
          __cil_tmp35 = & cmdbuffer->sz;
#line 103
          __cil_tmp36 = (struct __large_struct *)__cil_tmp35;
#line 103
          __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "iq" (cmdbuffer32.sz),
                               "m" (*__cil_tmp36), "i" (-14), "0" (__pu_err___0));
#line 103
          goto ldv_34854;
#line 103
          __cil_tmp37 = & cmdbuffer->sz;
#line 103
          __cil_tmp38 = (struct __large_struct *)__cil_tmp37;
#line 103
          __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (cmdbuffer32.sz),
                               "m" (*__cil_tmp38), "i" (-14), "0" (__pu_err___0));
#line 103
          goto ldv_34854;
          case_4___0: 
#line 103
          __cil_tmp39 = & cmdbuffer->sz;
#line 103
          __cil_tmp40 = (struct __large_struct *)__cil_tmp39;
#line 103
          __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (cmdbuffer32.sz),
                               "m" (*__cil_tmp40), "i" (-14), "0" (__pu_err___0));
#line 103
          goto ldv_34854;
#line 103
          __cil_tmp41 = & cmdbuffer->sz;
#line 103
          __cil_tmp42 = (struct __large_struct *)__cil_tmp41;
#line 103
          __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "er" (cmdbuffer32.sz),
                               "m" (*__cil_tmp42), "i" (-14), "0" (__pu_err___0));
#line 103
          goto ldv_34854;
          switch_default___0: 
          {
#line 103
          __put_user_bad();
          }
        } else {

        }
      }
      ldv_34854: ;
#line 107
      if (__pu_err___0 != 0) {
#line 109
        return (-14);
      } else {
#line 104
        __pu_err___1 = 0;
#line 104
        if (1) {
#line 104
          goto case_4___1;
        } else {
#line 104
          goto switch_default___1;
#line 104
          if (0) {
#line 104
            __cil_tmp43 = & cmdbuffer->DR1;
#line 104
            __cil_tmp44 = (struct __large_struct *)__cil_tmp43;
#line 104
            __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "iq" (cmdbuffer32.DR1),
                                 "m" (*__cil_tmp44), "i" (-14), "0" (__pu_err___1));
#line 104
            goto ldv_34862;
#line 104
            __cil_tmp45 = & cmdbuffer->DR1;
#line 104
            __cil_tmp46 = (struct __large_struct *)__cil_tmp45;
#line 104
            __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "ir" (cmdbuffer32.DR1),
                                 "m" (*__cil_tmp46), "i" (-14), "0" (__pu_err___1));
#line 104
            goto ldv_34862;
            case_4___1: 
#line 104
            __cil_tmp47 = & cmdbuffer->DR1;
#line 104
            __cil_tmp48 = (struct __large_struct *)__cil_tmp47;
#line 104
            __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "ir" (cmdbuffer32.DR1),
                                 "m" (*__cil_tmp48), "i" (-14), "0" (__pu_err___1));
#line 104
            goto ldv_34862;
#line 104
            __cil_tmp49 = & cmdbuffer->DR1;
#line 104
            __cil_tmp50 = (struct __large_struct *)__cil_tmp49;
#line 104
            __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "er" (cmdbuffer32.DR1),
                                 "m" (*__cil_tmp50), "i" (-14), "0" (__pu_err___1));
#line 104
            goto ldv_34862;
            switch_default___1: 
            {
#line 104
            __put_user_bad();
            }
          } else {

          }
        }
        ldv_34862: ;
#line 107
        if (__pu_err___1 != 0) {
#line 109
          return (-14);
        } else {
#line 105
          __pu_err___2 = 0;
#line 105
          if (1) {
#line 105
            goto case_4___2;
          } else {
#line 105
            goto switch_default___2;
#line 105
            if (0) {
#line 105
              __cil_tmp51 = & cmdbuffer->DR4;
#line 105
              __cil_tmp52 = (struct __large_struct *)__cil_tmp51;
#line 105
              __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "iq" (cmdbuffer32.DR4),
                                   "m" (*__cil_tmp52), "i" (-14), "0" (__pu_err___2));
#line 105
              goto ldv_34870;
#line 105
              __cil_tmp53 = & cmdbuffer->DR4;
#line 105
              __cil_tmp54 = (struct __large_struct *)__cil_tmp53;
#line 105
              __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "ir" (cmdbuffer32.DR4),
                                   "m" (*__cil_tmp54), "i" (-14), "0" (__pu_err___2));
#line 105
              goto ldv_34870;
              case_4___2: 
#line 105
              __cil_tmp55 = & cmdbuffer->DR4;
#line 105
              __cil_tmp56 = (struct __large_struct *)__cil_tmp55;
#line 105
              __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "ir" (cmdbuffer32.DR4),
                                   "m" (*__cil_tmp56), "i" (-14), "0" (__pu_err___2));
#line 105
              goto ldv_34870;
#line 105
              __cil_tmp57 = & cmdbuffer->DR4;
#line 105
              __cil_tmp58 = (struct __large_struct *)__cil_tmp57;
#line 105
              __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "er" (cmdbuffer32.DR4),
                                   "m" (*__cil_tmp58), "i" (-14), "0" (__pu_err___2));
#line 105
              goto ldv_34870;
              switch_default___2: 
              {
#line 105
              __put_user_bad();
              }
            } else {

            }
          }
          ldv_34870: ;
#line 107
          if (__pu_err___2 != 0) {
#line 109
            return (-14);
          } else {
#line 106
            __pu_err___3 = 0;
#line 106
            if (1) {
#line 106
              goto case_4___3;
            } else {
#line 106
              goto switch_default___3;
#line 106
              if (0) {
#line 106
                __cil_tmp59 = & cmdbuffer->num_cliprects;
#line 106
                __cil_tmp60 = (struct __large_struct *)__cil_tmp59;
#line 106
                __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "iq" (cmdbuffer32.num_cliprects),
                                     "m" (*__cil_tmp60), "i" (-14), "0" (__pu_err___3));
#line 106
                goto ldv_34878;
#line 106
                __cil_tmp61 = & cmdbuffer->num_cliprects;
#line 106
                __cil_tmp62 = (struct __large_struct *)__cil_tmp61;
#line 106
                __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "ir" (cmdbuffer32.num_cliprects),
                                     "m" (*__cil_tmp62), "i" (-14), "0" (__pu_err___3));
#line 106
                goto ldv_34878;
                case_4___3: 
#line 106
                __cil_tmp63 = & cmdbuffer->num_cliprects;
#line 106
                __cil_tmp64 = (struct __large_struct *)__cil_tmp63;
#line 106
                __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "ir" (cmdbuffer32.num_cliprects),
                                     "m" (*__cil_tmp64), "i" (-14), "0" (__pu_err___3));
#line 106
                goto ldv_34878;
#line 106
                __cil_tmp65 = & cmdbuffer->num_cliprects;
#line 106
                __cil_tmp66 = (struct __large_struct *)__cil_tmp65;
#line 106
                __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___3): "er" (cmdbuffer32.num_cliprects),
                                     "m" (*__cil_tmp66), "i" (-14), "0" (__pu_err___3));
#line 106
                goto ldv_34878;
                switch_default___3: 
                {
#line 106
                __put_user_bad();
                }
              } else {

              }
            }
            ldv_34878: ;
#line 107
            if (__pu_err___3 != 0) {
#line 109
              return (-14);
            } else {
#line 107
              __pu_err___4 = 0;
#line 107
              if (1) {
#line 107
                goto case_8___4;
              } else {
#line 107
                goto switch_default___4;
#line 107
                if (0) {
#line 107
                  __cil_tmp67 = (unsigned long )cmdbuffer32.cliprects;
#line 107
                  __cil_tmp68 = & cmdbuffer->cliprects;
#line 107
                  __cil_tmp69 = (struct __large_struct *)__cil_tmp68;
#line 107
                  __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "iq" ((struct drm_clip_rect *)__cil_tmp67),
                                       "m" (*__cil_tmp69), "i" (-14), "0" (__pu_err___4));
#line 107
                  goto ldv_34886;
#line 107
                  __cil_tmp70 = (unsigned long )cmdbuffer32.cliprects;
#line 107
                  __cil_tmp71 = & cmdbuffer->cliprects;
#line 107
                  __cil_tmp72 = (struct __large_struct *)__cil_tmp71;
#line 107
                  __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "ir" ((struct drm_clip_rect *)__cil_tmp70),
                                       "m" (*__cil_tmp72), "i" (-14), "0" (__pu_err___4));
#line 107
                  goto ldv_34886;
#line 107
                  __cil_tmp73 = (unsigned long )cmdbuffer32.cliprects;
#line 107
                  __cil_tmp74 = & cmdbuffer->cliprects;
#line 107
                  __cil_tmp75 = (struct __large_struct *)__cil_tmp74;
#line 107
                  __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "ir" ((struct drm_clip_rect *)__cil_tmp73),
                                       "m" (*__cil_tmp75), "i" (-14), "0" (__pu_err___4));
#line 107
                  goto ldv_34886;
                  case_8___4: 
#line 107
                  __cil_tmp76 = (unsigned long )cmdbuffer32.cliprects;
#line 107
                  __cil_tmp77 = & cmdbuffer->cliprects;
#line 107
                  __cil_tmp78 = (struct __large_struct *)__cil_tmp77;
#line 107
                  __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___4): "er" ((struct drm_clip_rect *)__cil_tmp76),
                                       "m" (*__cil_tmp78), "i" (-14), "0" (__pu_err___4));
#line 107
                  goto ldv_34886;
                  switch_default___4: 
                  {
#line 107
                  __put_user_bad();
                  }
                } else {

                }
              }
              ldv_34886: ;
#line 107
              if (__pu_err___4 != 0) {
#line 109
                return (-14);
              } else {

              }
            }
          }
        }
      }
    }
  }
  {
#line 111
  __cil_tmp79 = (unsigned long )cmdbuffer;
#line 111
  tmp___3 = drm_ioctl(file, 1075864651U, __cil_tmp79);
  }
#line 111
  return ((int )tmp___3);
}
}
#line 119 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
static int compat_i915_irq_emit(struct file *file , unsigned int cmd , unsigned long arg ) 
{ drm_i915_irq_emit32_t req32 ;
  drm_i915_irq_emit_t *request ;
  unsigned long tmp ;
  void *tmp___0 ;
  unsigned long flag ;
  unsigned long roksum ;
  struct thread_info *tmp___1 ;
  long tmp___2 ;
  int __pu_err ;
  long tmp___3 ;
  void *__cil_tmp14 ;
  void const   *__cil_tmp15 ;
  int __cil_tmp16 ;
  long __cil_tmp17 ;
  unsigned long __cil_tmp18 ;
  int **__cil_tmp19 ;
  struct __large_struct *__cil_tmp20 ;
  unsigned long __cil_tmp21 ;
  int **__cil_tmp22 ;
  struct __large_struct *__cil_tmp23 ;
  unsigned long __cil_tmp24 ;
  int **__cil_tmp25 ;
  struct __large_struct *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  int **__cil_tmp28 ;
  struct __large_struct *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;

  {
  {
#line 125
  __cil_tmp14 = (void *)(& req32);
#line 125
  __cil_tmp15 = (void const   *)arg;
#line 125
  tmp = copy_from_user(__cil_tmp14, __cil_tmp15, 4UL);
  }
#line 125
  if (tmp != 0UL) {
#line 126
    return (-14);
  } else {

  }
  {
#line 128
  tmp___0 = compat_alloc_user_space(8UL);
#line 128
  request = (drm_i915_irq_emit_t *)tmp___0;
#line 129
  tmp___1 = current_thread_info();
#line 129
  __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" (request),
            "g" (8L), "rm" (tmp___1->addr_limit.seg));
#line 129
  __cil_tmp16 = flag == 0UL;
#line 129
  __cil_tmp17 = (long )__cil_tmp16;
#line 129
  tmp___2 = __builtin_expect(__cil_tmp17, 1L);
  }
#line 130
  if (tmp___2 == 0L) {
#line 132
    return (-14);
  } else {
#line 130
    __pu_err = 0;
#line 130
    if (1) {
#line 130
      goto case_8;
    } else {
#line 130
      goto switch_default;
#line 130
      if (0) {
#line 130
        __cil_tmp18 = (unsigned long )req32.irq_seq;
#line 130
        __cil_tmp19 = & request->irq_seq;
#line 130
        __cil_tmp20 = (struct __large_struct *)__cil_tmp19;
#line 130
        __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "iq" ((int *)__cil_tmp18),
                             "m" (*__cil_tmp20), "i" (-14), "0" (__pu_err));
#line 130
        goto ldv_34907;
#line 130
        __cil_tmp21 = (unsigned long )req32.irq_seq;
#line 130
        __cil_tmp22 = & request->irq_seq;
#line 130
        __cil_tmp23 = (struct __large_struct *)__cil_tmp22;
#line 130
        __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" ((int *)__cil_tmp21),
                             "m" (*__cil_tmp23), "i" (-14), "0" (__pu_err));
#line 130
        goto ldv_34907;
#line 130
        __cil_tmp24 = (unsigned long )req32.irq_seq;
#line 130
        __cil_tmp25 = & request->irq_seq;
#line 130
        __cil_tmp26 = (struct __large_struct *)__cil_tmp25;
#line 130
        __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" ((int *)__cil_tmp24),
                             "m" (*__cil_tmp26), "i" (-14), "0" (__pu_err));
#line 130
        goto ldv_34907;
        case_8: 
#line 130
        __cil_tmp27 = (unsigned long )req32.irq_seq;
#line 130
        __cil_tmp28 = & request->irq_seq;
#line 130
        __cil_tmp29 = (struct __large_struct *)__cil_tmp28;
#line 130
        __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "er" ((int *)__cil_tmp27),
                             "m" (*__cil_tmp29), "i" (-14), "0" (__pu_err));
#line 130
        goto ldv_34907;
        switch_default: 
        {
#line 130
        __put_user_bad();
        }
      } else {

      }
    }
    ldv_34907: ;
#line 130
    if (__pu_err != 0) {
#line 132
      return (-14);
    } else {

    }
  }
  {
#line 134
  __cil_tmp30 = (unsigned long )request;
#line 134
  tmp___3 = drm_ioctl(file, 3221775428U, __cil_tmp30);
  }
#line 134
  return ((int )tmp___3);
}
}
#line 142 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
static int compat_i915_getparam(struct file *file , unsigned int cmd , unsigned long arg ) 
{ drm_i915_getparam32_t req32 ;
  drm_i915_getparam_t *request ;
  unsigned long tmp ;
  void *tmp___0 ;
  unsigned long flag ;
  unsigned long roksum ;
  struct thread_info *tmp___1 ;
  long tmp___2 ;
  int __pu_err ;
  int __pu_err___0 ;
  long tmp___3 ;
  void *__cil_tmp15 ;
  void const   *__cil_tmp16 ;
  int __cil_tmp17 ;
  long __cil_tmp18 ;
  int *__cil_tmp19 ;
  struct __large_struct *__cil_tmp20 ;
  int *__cil_tmp21 ;
  struct __large_struct *__cil_tmp22 ;
  int *__cil_tmp23 ;
  struct __large_struct *__cil_tmp24 ;
  int *__cil_tmp25 ;
  struct __large_struct *__cil_tmp26 ;
  unsigned long __cil_tmp27 ;
  int **__cil_tmp28 ;
  struct __large_struct *__cil_tmp29 ;
  unsigned long __cil_tmp30 ;
  int **__cil_tmp31 ;
  struct __large_struct *__cil_tmp32 ;
  unsigned long __cil_tmp33 ;
  int **__cil_tmp34 ;
  struct __large_struct *__cil_tmp35 ;
  unsigned long __cil_tmp36 ;
  int **__cil_tmp37 ;
  struct __large_struct *__cil_tmp38 ;
  unsigned long __cil_tmp39 ;

  {
  {
#line 148
  __cil_tmp15 = (void *)(& req32);
#line 148
  __cil_tmp16 = (void const   *)arg;
#line 148
  tmp = copy_from_user(__cil_tmp15, __cil_tmp16, 8UL);
  }
#line 148
  if (tmp != 0UL) {
#line 149
    return (-14);
  } else {

  }
  {
#line 151
  tmp___0 = compat_alloc_user_space(16UL);
#line 151
  request = (drm_i915_getparam_t *)tmp___0;
#line 152
  tmp___1 = current_thread_info();
#line 152
  __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" (request),
            "g" (16L), "rm" (tmp___1->addr_limit.seg));
#line 152
  __cil_tmp17 = flag == 0UL;
#line 152
  __cil_tmp18 = (long )__cil_tmp17;
#line 152
  tmp___2 = __builtin_expect(__cil_tmp18, 1L);
  }
#line 154
  if (tmp___2 == 0L) {
#line 156
    return (-14);
  } else {
#line 153
    __pu_err = 0;
#line 153
    if (1) {
#line 153
      goto case_4;
    } else {
#line 153
      goto switch_default;
#line 153
      if (0) {
#line 153
        __cil_tmp19 = & request->param;
#line 153
        __cil_tmp20 = (struct __large_struct *)__cil_tmp19;
#line 153
        __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "iq" (req32.param),
                             "m" (*__cil_tmp20), "i" (-14), "0" (__pu_err));
#line 153
        goto ldv_34929;
#line 153
        __cil_tmp21 = & request->param;
#line 153
        __cil_tmp22 = (struct __large_struct *)__cil_tmp21;
#line 153
        __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (req32.param),
                             "m" (*__cil_tmp22), "i" (-14), "0" (__pu_err));
#line 153
        goto ldv_34929;
        case_4: 
#line 153
        __cil_tmp23 = & request->param;
#line 153
        __cil_tmp24 = (struct __large_struct *)__cil_tmp23;
#line 153
        __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (req32.param),
                             "m" (*__cil_tmp24), "i" (-14), "0" (__pu_err));
#line 153
        goto ldv_34929;
#line 153
        __cil_tmp25 = & request->param;
#line 153
        __cil_tmp26 = (struct __large_struct *)__cil_tmp25;
#line 153
        __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "er" (req32.param),
                             "m" (*__cil_tmp26), "i" (-14), "0" (__pu_err));
#line 153
        goto ldv_34929;
        switch_default: 
        {
#line 153
        __put_user_bad();
        }
      } else {

      }
    }
    ldv_34929: ;
#line 154
    if (__pu_err != 0) {
#line 156
      return (-14);
    } else {
#line 154
      __pu_err___0 = 0;
#line 154
      if (1) {
#line 154
        goto case_8___0;
      } else {
#line 154
        goto switch_default___0;
#line 154
        if (0) {
#line 154
          __cil_tmp27 = (unsigned long )req32.value;
#line 154
          __cil_tmp28 = & request->value;
#line 154
          __cil_tmp29 = (struct __large_struct *)__cil_tmp28;
#line 154
          __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "iq" ((int *)__cil_tmp27),
                               "m" (*__cil_tmp29), "i" (-14), "0" (__pu_err___0));
#line 154
          goto ldv_34937;
#line 154
          __cil_tmp30 = (unsigned long )req32.value;
#line 154
          __cil_tmp31 = & request->value;
#line 154
          __cil_tmp32 = (struct __large_struct *)__cil_tmp31;
#line 154
          __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" ((int *)__cil_tmp30),
                               "m" (*__cil_tmp32), "i" (-14), "0" (__pu_err___0));
#line 154
          goto ldv_34937;
#line 154
          __cil_tmp33 = (unsigned long )req32.value;
#line 154
          __cil_tmp34 = & request->value;
#line 154
          __cil_tmp35 = (struct __large_struct *)__cil_tmp34;
#line 154
          __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" ((int *)__cil_tmp33),
                               "m" (*__cil_tmp35), "i" (-14), "0" (__pu_err___0));
#line 154
          goto ldv_34937;
          case_8___0: 
#line 154
          __cil_tmp36 = (unsigned long )req32.value;
#line 154
          __cil_tmp37 = & request->value;
#line 154
          __cil_tmp38 = (struct __large_struct *)__cil_tmp37;
#line 154
          __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "er" ((int *)__cil_tmp36),
                               "m" (*__cil_tmp38), "i" (-14), "0" (__pu_err___0));
#line 154
          goto ldv_34937;
          switch_default___0: 
          {
#line 154
          __put_user_bad();
          }
        } else {

        }
      }
      ldv_34937: ;
#line 154
      if (__pu_err___0 != 0) {
#line 156
        return (-14);
      } else {

      }
    }
  }
  {
#line 158
  __cil_tmp39 = (unsigned long )request;
#line 158
  tmp___3 = drm_ioctl(file, 3222299718U, __cil_tmp39);
  }
#line 158
  return ((int )tmp___3);
}
}
#line 169 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
static int compat_i915_alloc(struct file *file , unsigned int cmd , unsigned long arg ) 
{ drm_i915_mem_alloc32_t req32 ;
  drm_i915_mem_alloc_t *request ;
  unsigned long tmp ;
  void *tmp___0 ;
  unsigned long flag ;
  unsigned long roksum ;
  struct thread_info *tmp___1 ;
  long tmp___2 ;
  int __pu_err ;
  int __pu_err___0 ;
  int __pu_err___1 ;
  int __pu_err___2 ;
  long tmp___3 ;
  void *__cil_tmp17 ;
  void const   *__cil_tmp18 ;
  int __cil_tmp19 ;
  long __cil_tmp20 ;
  int *__cil_tmp21 ;
  struct __large_struct *__cil_tmp22 ;
  int *__cil_tmp23 ;
  struct __large_struct *__cil_tmp24 ;
  int *__cil_tmp25 ;
  struct __large_struct *__cil_tmp26 ;
  int *__cil_tmp27 ;
  struct __large_struct *__cil_tmp28 ;
  int *__cil_tmp29 ;
  struct __large_struct *__cil_tmp30 ;
  int *__cil_tmp31 ;
  struct __large_struct *__cil_tmp32 ;
  int *__cil_tmp33 ;
  struct __large_struct *__cil_tmp34 ;
  int *__cil_tmp35 ;
  struct __large_struct *__cil_tmp36 ;
  int *__cil_tmp37 ;
  struct __large_struct *__cil_tmp38 ;
  int *__cil_tmp39 ;
  struct __large_struct *__cil_tmp40 ;
  int *__cil_tmp41 ;
  struct __large_struct *__cil_tmp42 ;
  int *__cil_tmp43 ;
  struct __large_struct *__cil_tmp44 ;
  unsigned long __cil_tmp45 ;
  int **__cil_tmp46 ;
  struct __large_struct *__cil_tmp47 ;
  unsigned long __cil_tmp48 ;
  int **__cil_tmp49 ;
  struct __large_struct *__cil_tmp50 ;
  unsigned long __cil_tmp51 ;
  int **__cil_tmp52 ;
  struct __large_struct *__cil_tmp53 ;
  unsigned long __cil_tmp54 ;
  int **__cil_tmp55 ;
  struct __large_struct *__cil_tmp56 ;
  unsigned long __cil_tmp57 ;

  {
  {
#line 175
  __cil_tmp17 = (void *)(& req32);
#line 175
  __cil_tmp18 = (void const   *)arg;
#line 175
  tmp = copy_from_user(__cil_tmp17, __cil_tmp18, 16UL);
  }
#line 175
  if (tmp != 0UL) {
#line 176
    return (-14);
  } else {

  }
  {
#line 178
  tmp___0 = compat_alloc_user_space(24UL);
#line 178
  request = (drm_i915_mem_alloc_t *)tmp___0;
#line 179
  tmp___1 = current_thread_info();
#line 179
  __asm__  ("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0": "=&r" (flag), "=r" (roksum): "1" (request),
            "g" (24L), "rm" (tmp___1->addr_limit.seg));
#line 179
  __cil_tmp19 = flag == 0UL;
#line 179
  __cil_tmp20 = (long )__cil_tmp19;
#line 179
  tmp___2 = __builtin_expect(__cil_tmp20, 1L);
  }
#line 183
  if (tmp___2 == 0L) {
#line 185
    return (-14);
  } else {
#line 180
    __pu_err = 0;
#line 180
    if (1) {
#line 180
      goto case_4;
    } else {
#line 180
      goto switch_default;
#line 180
      if (0) {
#line 180
        __cil_tmp21 = & request->region;
#line 180
        __cil_tmp22 = (struct __large_struct *)__cil_tmp21;
#line 180
        __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "iq" (req32.region),
                             "m" (*__cil_tmp22), "i" (-14), "0" (__pu_err));
#line 180
        goto ldv_34961;
#line 180
        __cil_tmp23 = & request->region;
#line 180
        __cil_tmp24 = (struct __large_struct *)__cil_tmp23;
#line 180
        __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (req32.region),
                             "m" (*__cil_tmp24), "i" (-14), "0" (__pu_err));
#line 180
        goto ldv_34961;
        case_4: 
#line 180
        __cil_tmp25 = & request->region;
#line 180
        __cil_tmp26 = (struct __large_struct *)__cil_tmp25;
#line 180
        __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "ir" (req32.region),
                             "m" (*__cil_tmp26), "i" (-14), "0" (__pu_err));
#line 180
        goto ldv_34961;
#line 180
        __cil_tmp27 = & request->region;
#line 180
        __cil_tmp28 = (struct __large_struct *)__cil_tmp27;
#line 180
        __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err): "er" (req32.region),
                             "m" (*__cil_tmp28), "i" (-14), "0" (__pu_err));
#line 180
        goto ldv_34961;
        switch_default: 
        {
#line 180
        __put_user_bad();
        }
      } else {

      }
    }
    ldv_34961: ;
#line 183
    if (__pu_err != 0) {
#line 185
      return (-14);
    } else {
#line 181
      __pu_err___0 = 0;
#line 181
      if (1) {
#line 181
        goto case_4___0;
      } else {
#line 181
        goto switch_default___0;
#line 181
        if (0) {
#line 181
          __cil_tmp29 = & request->alignment;
#line 181
          __cil_tmp30 = (struct __large_struct *)__cil_tmp29;
#line 181
          __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "iq" (req32.alignment),
                               "m" (*__cil_tmp30), "i" (-14), "0" (__pu_err___0));
#line 181
          goto ldv_34969;
#line 181
          __cil_tmp31 = & request->alignment;
#line 181
          __cil_tmp32 = (struct __large_struct *)__cil_tmp31;
#line 181
          __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (req32.alignment),
                               "m" (*__cil_tmp32), "i" (-14), "0" (__pu_err___0));
#line 181
          goto ldv_34969;
          case_4___0: 
#line 181
          __cil_tmp33 = & request->alignment;
#line 181
          __cil_tmp34 = (struct __large_struct *)__cil_tmp33;
#line 181
          __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "ir" (req32.alignment),
                               "m" (*__cil_tmp34), "i" (-14), "0" (__pu_err___0));
#line 181
          goto ldv_34969;
#line 181
          __cil_tmp35 = & request->alignment;
#line 181
          __cil_tmp36 = (struct __large_struct *)__cil_tmp35;
#line 181
          __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___0): "er" (req32.alignment),
                               "m" (*__cil_tmp36), "i" (-14), "0" (__pu_err___0));
#line 181
          goto ldv_34969;
          switch_default___0: 
          {
#line 181
          __put_user_bad();
          }
        } else {

        }
      }
      ldv_34969: ;
#line 183
      if (__pu_err___0 != 0) {
#line 185
        return (-14);
      } else {
#line 182
        __pu_err___1 = 0;
#line 182
        if (1) {
#line 182
          goto case_4___1;
        } else {
#line 182
          goto switch_default___1;
#line 182
          if (0) {
#line 182
            __cil_tmp37 = & request->size;
#line 182
            __cil_tmp38 = (struct __large_struct *)__cil_tmp37;
#line 182
            __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "iq" (req32.size),
                                 "m" (*__cil_tmp38), "i" (-14), "0" (__pu_err___1));
#line 182
            goto ldv_34977;
#line 182
            __cil_tmp39 = & request->size;
#line 182
            __cil_tmp40 = (struct __large_struct *)__cil_tmp39;
#line 182
            __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "ir" (req32.size),
                                 "m" (*__cil_tmp40), "i" (-14), "0" (__pu_err___1));
#line 182
            goto ldv_34977;
            case_4___1: 
#line 182
            __cil_tmp41 = & request->size;
#line 182
            __cil_tmp42 = (struct __large_struct *)__cil_tmp41;
#line 182
            __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "ir" (req32.size),
                                 "m" (*__cil_tmp42), "i" (-14), "0" (__pu_err___1));
#line 182
            goto ldv_34977;
#line 182
            __cil_tmp43 = & request->size;
#line 182
            __cil_tmp44 = (struct __large_struct *)__cil_tmp43;
#line 182
            __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___1): "er" (req32.size),
                                 "m" (*__cil_tmp44), "i" (-14), "0" (__pu_err___1));
#line 182
            goto ldv_34977;
            switch_default___1: 
            {
#line 182
            __put_user_bad();
            }
          } else {

          }
        }
        ldv_34977: ;
#line 183
        if (__pu_err___1 != 0) {
#line 185
          return (-14);
        } else {
#line 183
          __pu_err___2 = 0;
#line 183
          if (1) {
#line 183
            goto case_8___2;
          } else {
#line 183
            goto switch_default___2;
#line 183
            if (0) {
#line 183
              __cil_tmp45 = (unsigned long )req32.region_offset;
#line 183
              __cil_tmp46 = & request->region_offset;
#line 183
              __cil_tmp47 = (struct __large_struct *)__cil_tmp46;
#line 183
              __asm__  volatile   ("1:\tmovb %b1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "iq" ((int *)__cil_tmp45),
                                   "m" (*__cil_tmp47), "i" (-14), "0" (__pu_err___2));
#line 183
              goto ldv_34985;
#line 183
              __cil_tmp48 = (unsigned long )req32.region_offset;
#line 183
              __cil_tmp49 = & request->region_offset;
#line 183
              __cil_tmp50 = (struct __large_struct *)__cil_tmp49;
#line 183
              __asm__  volatile   ("1:\tmovw %w1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "ir" ((int *)__cil_tmp48),
                                   "m" (*__cil_tmp50), "i" (-14), "0" (__pu_err___2));
#line 183
              goto ldv_34985;
#line 183
              __cil_tmp51 = (unsigned long )req32.region_offset;
#line 183
              __cil_tmp52 = & request->region_offset;
#line 183
              __cil_tmp53 = (struct __large_struct *)__cil_tmp52;
#line 183
              __asm__  volatile   ("1:\tmovl %k1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "ir" ((int *)__cil_tmp51),
                                   "m" (*__cil_tmp53), "i" (-14), "0" (__pu_err___2));
#line 183
              goto ldv_34985;
              case_8___2: 
#line 183
              __cil_tmp54 = (unsigned long )req32.region_offset;
#line 183
              __cil_tmp55 = & request->region_offset;
#line 183
              __cil_tmp56 = (struct __large_struct *)__cil_tmp55;
#line 183
              __asm__  volatile   ("1:\tmovq %1,%2\n2:\n.section .fixup,\"ax\"\n3:\tmov %3,%0\n\tjmp 2b\n.previous\n .section __ex_table,\"a\"\n .balign 8 \n .quad 1b,3b\n .previous\n": "=r" (__pu_err___2): "er" ((int *)__cil_tmp54),
                                   "m" (*__cil_tmp56), "i" (-14), "0" (__pu_err___2));
#line 183
              goto ldv_34985;
              switch_default___2: 
              {
#line 183
              __put_user_bad();
              }
            } else {

            }
          }
          ldv_34985: ;
#line 183
          if (__pu_err___2 != 0) {
#line 185
            return (-14);
          } else {

          }
        }
      }
    }
  }
  {
#line 187
  __cil_tmp57 = (unsigned long )request;
#line 187
  tmp___3 = drm_ioctl(file, 3222824008U, __cil_tmp57);
  }
#line 187
  return ((int )tmp___3);
}
}
#line 191 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
drm_ioctl_compat_t *i915_compat_ioctls[12U]  = 
#line 191
  {      (drm_ioctl_compat_t *)0,      (drm_ioctl_compat_t *)0,      (drm_ioctl_compat_t *)0,      & compat_i915_batchbuffer, 
        & compat_i915_irq_emit,      (drm_ioctl_compat_t *)0,      & compat_i915_getparam,      (drm_ioctl_compat_t *)0, 
        & compat_i915_alloc,      (drm_ioctl_compat_t *)0,      (drm_ioctl_compat_t *)0,      & compat_i915_cmdbuffer};
#line 208 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/i915_ioc32.c.p"
long i915_compat_ioctl(struct file *filp , unsigned int cmd , unsigned long arg ) 
{ unsigned int nr ;
  drm_ioctl_compat_t *fn ;
  int ret ;
  long tmp ;
  long tmp___0 ;
  drm_ioctl_compat_t *__cil_tmp9 ;
  unsigned long __cil_tmp10 ;
  unsigned long __cil_tmp11 ;

  {
#line 210
  nr = cmd & 255U;
#line 211
  fn = (drm_ioctl_compat_t *)0;
#line 214
  if (nr <= 63U) {
    {
#line 215
    tmp = drm_compat_ioctl(filp, cmd, arg);
    }
#line 215
    return (tmp);
  } else {

  }
#line 217
  if (nr <= 75U) {
#line 218
    fn = i915_compat_ioctls[nr - 64U];
  } else {

  }
  {
#line 220
  __cil_tmp9 = (drm_ioctl_compat_t *)0;
#line 220
  __cil_tmp10 = (unsigned long )__cil_tmp9;
#line 220
  __cil_tmp11 = (unsigned long )fn;
#line 220
  if (__cil_tmp11 != __cil_tmp10) {
    {
#line 221
    ret = (*fn)(filp, cmd, arg);
    }
  } else {
    {
#line 223
    tmp___0 = drm_ioctl(filp, cmd, arg);
#line 223
    ret = (int )tmp___0;
    }
  }
  }
#line 225
  return ((long )ret);
}
}
#line 174 "include/acpi/acpixf.h"
extern acpi_status acpi_get_name(acpi_handle  , u32  , struct acpi_buffer * ) ;
#line 178
extern acpi_status acpi_get_handle(acpi_handle  , acpi_string  , acpi_handle ** ) ;
#line 196
extern acpi_status acpi_evaluate_object(acpi_handle  , acpi_string  , struct acpi_object_list * ,
                                        struct acpi_buffer * ) ;
#line 27 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static struct intel_dsm_priv intel_dsm_priv  ;
#line 29 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static u8 const   intel_dsm_guid[16U]  = 
#line 29
  {      (u8 const   )211U,      (u8 const   )115U,      (u8 const   )216U,      (u8 const   )126U, 
        (u8 const   )208U,      (u8 const   )194U,      (u8 const   )79U,      (u8 const   )78U, 
        (u8 const   )168U,      (u8 const   )84U,      (u8 const   )15U,      (u8 const   )19U, 
        (u8 const   )23U,      (u8 const   )176U,      (u8 const   )28U,      (u8 const   )44U};
#line 37 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static int intel_dsm(acpi_handle handle , int func , int arg ) 
{ struct acpi_buffer output ;
  struct acpi_object_list input ;
  union acpi_object params[4U] ;
  union acpi_object *obj ;
  u32 result ;
  int ret ;
  acpi_status tmp ;
  char *__cil_tmp11 ;
  acpi_object_type __cil_tmp12 ;
  int __cil_tmp13 ;
  acpi_object_type __cil_tmp14 ;
  int __cil_tmp15 ;
  u64 __cil_tmp16 ;
  u32 __cil_tmp17 ;
  u8 *__cil_tmp18 ;
  u8 *__cil_tmp19 ;
  u8 __cil_tmp20 ;
  int __cil_tmp21 ;
  int __cil_tmp22 ;
  u8 *__cil_tmp23 ;
  u8 *__cil_tmp24 ;
  u8 __cil_tmp25 ;
  int __cil_tmp26 ;
  int __cil_tmp27 ;
  u8 *__cil_tmp28 ;
  u8 *__cil_tmp29 ;
  u8 __cil_tmp30 ;
  int __cil_tmp31 ;
  int __cil_tmp32 ;
  u8 *__cil_tmp33 ;
  u8 __cil_tmp34 ;
  int __cil_tmp35 ;
  int __cil_tmp36 ;
  int __cil_tmp37 ;
  int __cil_tmp38 ;
  void const   *__cil_tmp39 ;

  {
  {
#line 39
  output.length = 1152921504606846975ULL;
#line 39
  output.pointer = (void *)0;
#line 44
  ret = 0;
#line 46
  input.count = 4U;
#line 47
  input.pointer = (union acpi_object *)(& params);
#line 48
  params[0].type = 3U;
#line 49
  params[0].buffer.length = 16U;
#line 50
  params[0].buffer.pointer = (u8 *)(& intel_dsm_guid);
#line 51
  params[1].type = 1U;
#line 52
  params[1].integer.value = 1ULL;
#line 53
  params[2].type = 1U;
#line 54
  params[2].integer.value = (u64 )func;
#line 55
  params[3].type = 1U;
#line 56
  params[3].integer.value = (u64 )arg;
#line 58
  __cil_tmp11 = (char *)"_DSM";
#line 58
  tmp = acpi_evaluate_object(handle, __cil_tmp11, & input, & output);
#line 58
  ret = (int )tmp;
  }
#line 59
  if (ret != 0) {
    {
#line 60
    drm_ut_debug_printk(2U, "drm", "intel_dsm", "failed to evaluate _DSM: %d\n", ret);
    }
#line 61
    return (ret);
  } else {

  }
#line 64
  obj = (union acpi_object *)output.pointer;
#line 66
  result = 0U;
  {
#line 68
  __cil_tmp12 = obj->type;
#line 68
  __cil_tmp13 = (int )__cil_tmp12;
#line 68
  if (__cil_tmp13 == 1) {
#line 68
    goto case_1;
  } else {
    {
#line 72
    __cil_tmp14 = obj->type;
#line 72
    __cil_tmp15 = (int )__cil_tmp14;
#line 72
    if (__cil_tmp15 == 3) {
#line 72
      goto case_3;
    } else {
#line 80
      goto switch_default;
#line 67
      if (0) {
        case_1: 
#line 69
        __cil_tmp16 = obj->integer.value;
#line 69
        result = (u32 )__cil_tmp16;
#line 70
        goto ldv_36907;
        case_3: ;
        {
#line 73
        __cil_tmp17 = obj->buffer.length;
#line 73
        if (__cil_tmp17 == 4U) {
#line 74
          __cil_tmp18 = obj->buffer.pointer;
#line 74
          __cil_tmp19 = __cil_tmp18 + 3UL;
#line 74
          __cil_tmp20 = *__cil_tmp19;
#line 74
          __cil_tmp21 = (int )__cil_tmp20;
#line 74
          __cil_tmp22 = __cil_tmp21 << 24;
#line 74
          __cil_tmp23 = obj->buffer.pointer;
#line 74
          __cil_tmp24 = __cil_tmp23 + 2UL;
#line 74
          __cil_tmp25 = *__cil_tmp24;
#line 74
          __cil_tmp26 = (int )__cil_tmp25;
#line 74
          __cil_tmp27 = __cil_tmp26 << 16;
#line 74
          __cil_tmp28 = obj->buffer.pointer;
#line 74
          __cil_tmp29 = __cil_tmp28 + 1UL;
#line 74
          __cil_tmp30 = *__cil_tmp29;
#line 74
          __cil_tmp31 = (int )__cil_tmp30;
#line 74
          __cil_tmp32 = __cil_tmp31 << 8;
#line 74
          __cil_tmp33 = obj->buffer.pointer;
#line 74
          __cil_tmp34 = *__cil_tmp33;
#line 74
          __cil_tmp35 = (int )__cil_tmp34;
#line 74
          __cil_tmp36 = __cil_tmp35 | __cil_tmp32;
#line 74
          __cil_tmp37 = __cil_tmp36 | __cil_tmp27;
#line 74
          __cil_tmp38 = __cil_tmp37 | __cil_tmp22;
#line 74
          result = (u32 )__cil_tmp38;
#line 78
          goto ldv_36907;
        } else {

        }
        }
        switch_default: 
#line 81
        ret = -22;
#line 82
        goto ldv_36907;
      } else {

      }
    }
    }
  }
  }
  ldv_36907: ;
#line 84
  if (result == 2147483650U) {
#line 85
    ret = -19;
  } else {

  }
  {
#line 87
  __cil_tmp39 = (void const   *)output.pointer;
#line 87
  kfree(__cil_tmp39);
  }
#line 88
  return (ret);
}
}
#line 91 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static char *intel_dsm_port_name(u8 id ) 
{ int __cil_tmp2 ;
  int __cil_tmp3 ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;
  int __cil_tmp6 ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  int __cil_tmp11 ;
  int __cil_tmp12 ;
  int __cil_tmp13 ;
  int __cil_tmp14 ;
  int __cil_tmp15 ;
  int __cil_tmp16 ;

  {
  {
#line 94
  __cil_tmp2 = (int )id;
#line 94
  if (__cil_tmp2 == 0) {
#line 94
    goto case_0;
  } else {
    {
#line 96
    __cil_tmp3 = (int )id;
#line 96
    if (__cil_tmp3 == 1) {
#line 96
      goto case_1;
    } else {
      {
#line 98
      __cil_tmp4 = (int )id;
#line 98
      if (__cil_tmp4 == 2) {
#line 98
        goto case_2;
      } else {
        {
#line 100
        __cil_tmp5 = (int )id;
#line 100
        if (__cil_tmp5 == 3) {
#line 100
          goto case_3;
        } else {
          {
#line 102
          __cil_tmp6 = (int )id;
#line 102
          if (__cil_tmp6 == 4) {
#line 102
            goto case_4;
          } else {
            {
#line 104
            __cil_tmp7 = (int )id;
#line 104
            if (__cil_tmp7 == 5) {
#line 104
              goto case_5;
            } else {
              {
#line 106
              __cil_tmp8 = (int )id;
#line 106
              if (__cil_tmp8 == 6) {
#line 106
                goto case_6;
              } else {
                {
#line 108
                __cil_tmp9 = (int )id;
#line 108
                if (__cil_tmp9 == 7) {
#line 108
                  goto case_7;
                } else {
                  {
#line 110
                  __cil_tmp10 = (int )id;
#line 110
                  if (__cil_tmp10 == 8) {
#line 110
                    goto case_8;
                  } else {
                    {
#line 112
                    __cil_tmp11 = (int )id;
#line 112
                    if (__cil_tmp11 == 9) {
#line 112
                      goto case_9;
                    } else {
                      {
#line 114
                      __cil_tmp12 = (int )id;
#line 114
                      if (__cil_tmp12 == 10) {
#line 114
                        goto case_10;
                      } else {
                        {
#line 116
                        __cil_tmp13 = (int )id;
#line 116
                        if (__cil_tmp13 == 11) {
#line 116
                          goto case_11;
                        } else {
                          {
#line 117
                          __cil_tmp14 = (int )id;
#line 117
                          if (__cil_tmp14 == 12) {
#line 117
                            goto case_12;
                          } else {
                            {
#line 118
                            __cil_tmp15 = (int )id;
#line 118
                            if (__cil_tmp15 == 13) {
#line 118
                              goto case_13;
                            } else {
                              {
#line 120
                              __cil_tmp16 = (int )id;
#line 120
                              if (__cil_tmp16 == 14) {
#line 120
                                goto case_14;
                              } else {
#line 122
                                goto switch_default;
#line 93
                                if (0) {
                                  case_0: ;
#line 95
                                  return ((char *)"Reserved");
                                  case_1: ;
#line 97
                                  return ((char *)"Analog VGA");
                                  case_2: ;
#line 99
                                  return ((char *)"LVDS");
                                  case_3: ;
#line 101
                                  return ((char *)"Reserved");
                                  case_4: ;
#line 103
                                  return ((char *)"HDMI/DVI_B");
                                  case_5: ;
#line 105
                                  return ((char *)"HDMI/DVI_C");
                                  case_6: ;
#line 107
                                  return ((char *)"HDMI/DVI_D");
                                  case_7: ;
#line 109
                                  return ((char *)"DisplayPort_A");
                                  case_8: ;
#line 111
                                  return ((char *)"DisplayPort_B");
                                  case_9: ;
#line 113
                                  return ((char *)"DisplayPort_C");
                                  case_10: ;
#line 115
                                  return ((char *)"DisplayPort_D");
                                  case_11: ;
                                  case_12: ;
                                  case_13: ;
#line 119
                                  return ((char *)"Reserved");
                                  case_14: ;
#line 121
                                  return ((char *)"WiDi");
                                  switch_default: ;
#line 123
                                  return ((char *)"bad type");
                                } else {

                                }
                              }
                              }
                            }
                            }
                          }
                          }
                        }
                        }
                      }
                      }
                    }
                    }
                  }
                  }
                }
                }
              }
              }
            }
            }
          }
          }
        }
        }
      }
      }
    }
    }
  }
  }
}
}
#line 127 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static char *intel_dsm_mux_type(u8 type ) 
{ int __cil_tmp2 ;
  int __cil_tmp3 ;
  int __cil_tmp4 ;
  int __cil_tmp5 ;

  {
  {
#line 130
  __cil_tmp2 = (int )type;
#line 130
  if (__cil_tmp2 == 0) {
#line 130
    goto case_0;
  } else {
    {
#line 132
    __cil_tmp3 = (int )type;
#line 132
    if (__cil_tmp3 == 1) {
#line 132
      goto case_1;
    } else {
      {
#line 134
      __cil_tmp4 = (int )type;
#line 134
      if (__cil_tmp4 == 2) {
#line 134
        goto case_2;
      } else {
        {
#line 136
        __cil_tmp5 = (int )type;
#line 136
        if (__cil_tmp5 == 3) {
#line 136
          goto case_3;
        } else {
#line 138
          goto switch_default;
#line 129
          if (0) {
            case_0: ;
#line 131
            return ((char *)"unknown");
            case_1: ;
#line 133
            return ((char *)"No MUX, iGPU only");
            case_2: ;
#line 135
            return ((char *)"No MUX, dGPU only");
            case_3: ;
#line 137
            return ((char *)"MUXed between iGPU and dGPU");
            switch_default: ;
#line 139
            return ((char *)"bad type");
          } else {

          }
        }
        }
      }
      }
    }
    }
  }
  }
}
}
#line 143 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static void intel_dsm_platform_mux_info(void) 
{ struct acpi_buffer output ;
  struct acpi_object_list input ;
  union acpi_object params[4U] ;
  union acpi_object *pkg ;
  int i ;
  int ret ;
  acpi_status tmp ;
  union acpi_object *connector_count ;
  union acpi_object *obj ;
  union acpi_object *connector_id ;
  union acpi_object *info ;
  char *tmp___0 ;
  char *tmp___1 ;
  char *tmp___2 ;
  char *tmp___3 ;
  char *__cil_tmp16 ;
  acpi_object_type __cil_tmp17 ;
  u64 __cil_tmp18 ;
  unsigned long __cil_tmp19 ;
  union acpi_object *__cil_tmp20 ;
  union acpi_object *__cil_tmp21 ;
  u64 __cil_tmp22 ;
  u8 *__cil_tmp23 ;
  u8 __cil_tmp24 ;
  int __cil_tmp25 ;
  u8 __cil_tmp26 ;
  u8 *__cil_tmp27 ;
  u8 *__cil_tmp28 ;
  u8 __cil_tmp29 ;
  int __cil_tmp30 ;
  u8 __cil_tmp31 ;
  u8 *__cil_tmp32 ;
  u8 *__cil_tmp33 ;
  u8 __cil_tmp34 ;
  int __cil_tmp35 ;
  u8 __cil_tmp36 ;
  u8 *__cil_tmp37 ;
  u8 *__cil_tmp38 ;
  u8 __cil_tmp39 ;
  int __cil_tmp40 ;
  u8 __cil_tmp41 ;
  u32 __cil_tmp42 ;
  u32 __cil_tmp43 ;
  void const   *__cil_tmp44 ;

  {
  {
#line 145
  output.length = 1152921504606846975ULL;
#line 145
  output.pointer = (void *)0;
#line 151
  input.count = 4U;
#line 152
  input.pointer = (union acpi_object *)(& params);
#line 153
  params[0].type = 3U;
#line 154
  params[0].buffer.length = 16U;
#line 155
  params[0].buffer.pointer = (u8 *)(& intel_dsm_guid);
#line 156
  params[1].type = 1U;
#line 157
  params[1].integer.value = 1ULL;
#line 158
  params[2].type = 1U;
#line 159
  params[2].integer.value = 1ULL;
#line 160
  params[3].type = 1U;
#line 161
  params[3].integer.value = 0ULL;
#line 163
  __cil_tmp16 = (char *)"_DSM";
#line 163
  tmp = acpi_evaluate_object(intel_dsm_priv.dhandle, __cil_tmp16, & input, & output);
#line 163
  ret = (int )tmp;
  }
#line 165
  if (ret != 0) {
    {
#line 166
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "failed to evaluate _DSM: %d\n",
                        ret);
    }
#line 167
    goto out;
  } else {

  }
#line 170
  pkg = (union acpi_object *)output.pointer;
  {
#line 172
  __cil_tmp17 = pkg->type;
#line 172
  if (__cil_tmp17 == 4U) {
    {
#line 173
    connector_count = pkg->package.elements;
#line 174
    __cil_tmp18 = connector_count->integer.value;
#line 174
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "MUX info connectors: %lld\n",
                        __cil_tmp18);
#line 176
    i = 1;
    }
#line 176
    goto ldv_36953;
    ldv_36952: 
    {
#line 177
    __cil_tmp19 = (unsigned long )i;
#line 177
    __cil_tmp20 = pkg->package.elements;
#line 177
    obj = __cil_tmp20 + __cil_tmp19;
#line 178
    connector_id = obj->package.elements;
#line 180
    __cil_tmp21 = obj->package.elements;
#line 180
    info = __cil_tmp21 + 1UL;
#line 181
    __cil_tmp22 = connector_id->integer.value;
#line 181
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "Connector id: 0x%016llx\n",
                        __cil_tmp22);
#line 183
    __cil_tmp23 = info->buffer.pointer;
#line 183
    __cil_tmp24 = *__cil_tmp23;
#line 183
    __cil_tmp25 = (int )__cil_tmp24;
#line 183
    __cil_tmp26 = (u8 )__cil_tmp25;
#line 183
    tmp___0 = intel_dsm_port_name(__cil_tmp26);
#line 183
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "  port id: %s\n",
                        tmp___0);
#line 185
    __cil_tmp27 = info->buffer.pointer;
#line 185
    __cil_tmp28 = __cil_tmp27 + 1UL;
#line 185
    __cil_tmp29 = *__cil_tmp28;
#line 185
    __cil_tmp30 = (int )__cil_tmp29;
#line 185
    __cil_tmp31 = (u8 )__cil_tmp30;
#line 185
    tmp___1 = intel_dsm_mux_type(__cil_tmp31);
#line 185
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "  display mux info: %s\n",
                        tmp___1);
#line 187
    __cil_tmp32 = info->buffer.pointer;
#line 187
    __cil_tmp33 = __cil_tmp32 + 2UL;
#line 187
    __cil_tmp34 = *__cil_tmp33;
#line 187
    __cil_tmp35 = (int )__cil_tmp34;
#line 187
    __cil_tmp36 = (u8 )__cil_tmp35;
#line 187
    tmp___2 = intel_dsm_mux_type(__cil_tmp36);
#line 187
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "  aux/dc mux info: %s\n",
                        tmp___2);
#line 189
    __cil_tmp37 = info->buffer.pointer;
#line 189
    __cil_tmp38 = __cil_tmp37 + 3UL;
#line 189
    __cil_tmp39 = *__cil_tmp38;
#line 189
    __cil_tmp40 = (int )__cil_tmp39;
#line 189
    __cil_tmp41 = (u8 )__cil_tmp40;
#line 189
    tmp___3 = intel_dsm_mux_type(__cil_tmp41);
#line 189
    drm_ut_debug_printk(2U, "drm", "intel_dsm_platform_mux_info", "  hpd mux info: %s\n",
                        tmp___3);
#line 176
    i = i + 1;
    }
    ldv_36953: ;
    {
#line 176
    __cil_tmp42 = pkg->package.count;
#line 176
    __cil_tmp43 = (u32 )i;
#line 176
    if (__cil_tmp43 < __cil_tmp42) {
#line 177
      goto ldv_36952;
    } else {
#line 179
      goto ldv_36954;
    }
    }
    ldv_36954: ;
  } else {
    {
#line 193
    drm_err("intel_dsm_platform_mux_info", "MUX INFO call failed\n");
    }
  }
  }
  out: 
  {
#line 197
  __cil_tmp44 = (void const   *)output.pointer;
#line 197
  kfree(__cil_tmp44);
  }
#line 198
  return;
}
}
#line 200 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static bool intel_dsm_pci_probe(struct pci_dev *pdev ) 
{ acpi_handle dhandle ;
  acpi_handle intel_handle ;
  acpi_status status ;
  int ret ;
  acpi_handle __cil_tmp6 ;
  unsigned long __cil_tmp7 ;
  unsigned long __cil_tmp8 ;
  char *__cil_tmp9 ;
  acpi_handle **__cil_tmp10 ;

  {
#line 206
  dhandle = pdev->dev.archdata.acpi_handle;
  {
#line 207
  __cil_tmp6 = (acpi_handle )0;
#line 207
  __cil_tmp7 = (unsigned long )__cil_tmp6;
#line 207
  __cil_tmp8 = (unsigned long )dhandle;
#line 207
  if (__cil_tmp8 == __cil_tmp7) {
#line 208
    return ((bool )0);
  } else {

  }
  }
  {
#line 210
  __cil_tmp9 = (char *)"_DSM";
#line 210
  __cil_tmp10 = (acpi_handle **)(& intel_handle);
#line 210
  status = acpi_get_handle(dhandle, __cil_tmp9, __cil_tmp10);
  }
#line 211
  if (status != 0U) {
    {
#line 212
    drm_ut_debug_printk(4U, "drm", "intel_dsm_pci_probe", "no _DSM method for intel device\n");
    }
#line 213
    return ((bool )0);
  } else {

  }
  {
#line 216
  ret = intel_dsm(dhandle, 0, 0);
  }
#line 217
  if (ret < 0) {
    {
#line 218
    drm_err("intel_dsm_pci_probe", "failed to get supported _DSM functions\n");
    }
#line 219
    return ((bool )0);
  } else {

  }
  {
#line 222
  intel_dsm_priv.dhandle = dhandle;
#line 224
  intel_dsm_platform_mux_info();
  }
#line 225
  return ((bool )1);
}
}
#line 228 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
static bool intel_dsm_detect(void) 
{ char acpi_method_name[255U] ;
  struct acpi_buffer buffer ;
  struct pci_dev *pdev ;
  bool has_dsm ;
  int vga_count ;
  bool tmp ;
  int __cil_tmp7 ;
  int __cil_tmp8 ;
  int __cil_tmp9 ;
  int __cil_tmp10 ;
  struct pci_dev *__cil_tmp11 ;
  unsigned long __cil_tmp12 ;
  unsigned long __cil_tmp13 ;
  char *__cil_tmp14 ;

  {
#line 230
  acpi_method_name[0] = (char)0;
#line 231
  buffer.length = 255ULL;
#line 231
  buffer.pointer = (void *)(& acpi_method_name);
#line 232
  pdev = (struct pci_dev *)0;
#line 233
  has_dsm = (bool )0;
#line 234
  vga_count = 0;
#line 236
  goto ldv_36972;
  ldv_36971: 
  {
#line 237
  vga_count = vga_count + 1;
#line 238
  tmp = intel_dsm_pci_probe(pdev);
#line 238
  __cil_tmp7 = (int )tmp;
#line 238
  __cil_tmp8 = (int )has_dsm;
#line 238
  __cil_tmp9 = __cil_tmp8 | __cil_tmp7;
#line 238
  __cil_tmp10 = __cil_tmp9 != 0;
#line 238
  has_dsm = (bool )__cil_tmp10;
  }
  ldv_36972: 
  {
#line 236
  pdev = pci_get_class(196608U, pdev);
  }
  {
#line 236
  __cil_tmp11 = (struct pci_dev *)0;
#line 236
  __cil_tmp12 = (unsigned long )__cil_tmp11;
#line 236
  __cil_tmp13 = (unsigned long )pdev;
#line 236
  if (__cil_tmp13 != __cil_tmp12) {
#line 237
    goto ldv_36971;
  } else {
#line 239
    goto ldv_36973;
  }
  }
  ldv_36973: ;
#line 241
  if (vga_count == 2) {
#line 241
    if ((int )has_dsm) {
      {
#line 242
      acpi_get_name(intel_dsm_priv.dhandle, 0U, & buffer);
#line 243
      __cil_tmp14 = (char *)(& acpi_method_name);
#line 243
      drm_ut_debug_printk(2U, "drm", "intel_dsm_detect", "VGA switcheroo: detected DSM switching method %s handle\n",
                          __cil_tmp14);
      }
#line 245
      return ((bool )1);
    } else {

    }
  } else {

  }
#line 248
  return ((bool )0);
}
}
#line 251 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
void intel_register_dsm_handler(void) 
{ bool tmp ;
  int tmp___0 ;

  {
  {
#line 253
  tmp = intel_dsm_detect();
  }
#line 253
  if (tmp) {
#line 253
    tmp___0 = 0;
  } else {
#line 253
    tmp___0 = 1;
  }
#line 253
  if (tmp___0) {
#line 254
    return;
  } else {

  }
#line 255
  return;
}
}
#line 257 "/anthill/stuff/tacas-comp/work/current--X--drivers/gpu/drm/i915/i915.ko--X--safe-main18linux-3.0.1--X--08_1/linux-3.0.1/csd_deg_dscv/46/dscv_tempdir/dscv/ri/08_1/drivers/gpu/drm/i915/intel_acpi.c.p"
void intel_unregister_dsm_handler(void) 
{ 

  {
#line 259
  return;
}
}