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120#include <linux/types.h>
121#include <linux/module.h>
122#include <linux/kernel.h>
123#include <linux/delay.h>
124#include <linux/blkdev.h>
125#include <linux/interrupt.h>
126#include <linux/pci.h>
127#include <linux/init.h>
128#include <linux/ide.h>
129
130#include <asm/uaccess.h>
131#include <asm/io.h>
132
133#define DRV_NAME "hpt366"
134
135
136#define HPT_RESET_STATE_ENGINE
137#undef HPT_DELAY_INTERRUPT
138#define HPT_SERIALIZE_IO 0
139
140static const char *quirk_drives[] = {
141 "QUANTUM FIREBALLlct08 08",
142 "QUANTUM FIREBALLP KA6.4",
143 "QUANTUM FIREBALLP LM20.4",
144 "QUANTUM FIREBALLP LM20.5",
145 NULL
146};
147
148static const char *bad_ata100_5[] = {
149 "IBM-DTLA-307075",
150 "IBM-DTLA-307060",
151 "IBM-DTLA-307045",
152 "IBM-DTLA-307030",
153 "IBM-DTLA-307020",
154 "IBM-DTLA-307015",
155 "IBM-DTLA-305040",
156 "IBM-DTLA-305030",
157 "IBM-DTLA-305020",
158 "IC35L010AVER07-0",
159 "IC35L020AVER07-0",
160 "IC35L030AVER07-0",
161 "IC35L040AVER07-0",
162 "IC35L060AVER07-0",
163 "WDC AC310200R",
164 NULL
165};
166
167static const char *bad_ata66_4[] = {
168 "IBM-DTLA-307075",
169 "IBM-DTLA-307060",
170 "IBM-DTLA-307045",
171 "IBM-DTLA-307030",
172 "IBM-DTLA-307020",
173 "IBM-DTLA-307015",
174 "IBM-DTLA-305040",
175 "IBM-DTLA-305030",
176 "IBM-DTLA-305020",
177 "IC35L010AVER07-0",
178 "IC35L020AVER07-0",
179 "IC35L030AVER07-0",
180 "IC35L040AVER07-0",
181 "IC35L060AVER07-0",
182 "WDC AC310200R",
183 "MAXTOR STM3320620A",
184 NULL
185};
186
187static const char *bad_ata66_3[] = {
188 "WDC AC310200R",
189 NULL
190};
191
192static const char *bad_ata33[] = {
193 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
194 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
195 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
196 "Maxtor 90510D4",
197 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
198 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
199 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
200 NULL
201};
202
203static u8 xfer_speeds[] = {
204 XFER_UDMA_6,
205 XFER_UDMA_5,
206 XFER_UDMA_4,
207 XFER_UDMA_3,
208 XFER_UDMA_2,
209 XFER_UDMA_1,
210 XFER_UDMA_0,
211
212 XFER_MW_DMA_2,
213 XFER_MW_DMA_1,
214 XFER_MW_DMA_0,
215
216 XFER_PIO_4,
217 XFER_PIO_3,
218 XFER_PIO_2,
219 XFER_PIO_1,
220 XFER_PIO_0
221};
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246
247static u32 forty_base_hpt36x[] = {
248 0x900fd943,
249 0x900fd943,
250 0x900fd943,
251 0x900ad943,
252 0x900bd943,
253 0x9008d943,
254 0x9008d943,
255
256 0xa008d943,
257 0xa010d955,
258 0xa010d9fc,
259
260 0xc008d963,
261 0xc010d974,
262 0xc010d997,
263 0xc010d9c7,
264 0xc018d9d9
265};
266
267static u32 thirty_three_base_hpt36x[] = {
268 0x90c9a731,
269 0x90c9a731,
270 0x90c9a731,
271 0x90cfa731,
272 0x90caa731,
273 0x90cba731,
274 0x90c8a731,
275
276 0xa0c8a731,
277 0xa0c8a732,
278 0xa0c8a797,
279
280 0xc0c8a731,
281 0xc0c8a742,
282 0xc0d0a753,
283 0xc0d0a7a3,
284 0xc0d0a7aa
285};
286
287static u32 twenty_five_base_hpt36x[] = {
288 0x90c98521,
289 0x90c98521,
290 0x90c98521,
291 0x90cf8521,
292 0x90cf8521,
293 0x90cb8521,
294 0x90cb8521,
295
296 0xa0ca8521,
297 0xa0ca8532,
298 0xa0ca8575,
299
300 0xc0ca8521,
301 0xc0ca8532,
302 0xc0ca8542,
303 0xc0d08572,
304 0xc0d08585
305};
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375static u32 thirty_three_base_hpt37x[] = {
376 0x16455031,
377 0x16455031,
378 0x16455031,
379 0x166d5031,
380 0x16495031,
381 0x164d5033,
382 0x16515097,
383
384 0x26515031,
385 0x26515033,
386 0x26515097,
387
388 0x06515021,
389 0x06515022,
390 0x06515033,
391 0x06915065,
392 0x06d1508a
393};
394
395static u32 fifty_base_hpt37x[] = {
396 0x1a861842,
397 0x1a861842,
398 0x1aae1842,
399 0x1a8e1842,
400 0x1a0e1842,
401 0x1a161854,
402 0x1a1a18ea,
403
404 0x2a821842,
405 0x2a821854,
406 0x2a8218ea,
407
408 0x0a821842,
409 0x0a821843,
410 0x0a821855,
411 0x0ac218a8,
412 0x0b02190c
413};
414
415static u32 sixty_six_base_hpt37x[] = {
416 0x1c86fe62,
417 0x1caefe62,
418 0x1c8afe62,
419 0x1c8efe62,
420 0x1c92fe62,
421 0x1c9afe62,
422 0x1c82fe62,
423
424 0x2c82fe62,
425 0x2c82fe66,
426 0x2c82ff2e,
427
428 0x0c82fe62,
429 0x0c82fe84,
430 0x0c82fea6,
431 0x0d02ff26,
432 0x0d42ff7f
433};
434#endif
435
436#define HPT366_DEBUG_DRIVE_INFO 0
437#define HPT371_ALLOW_ATA133_6 1
438#define HPT302_ALLOW_ATA133_6 1
439#define HPT372_ALLOW_ATA133_6 1
440#define HPT370_ALLOW_ATA100_5 0
441#define HPT366_ALLOW_ATA66_4 1
442#define HPT366_ALLOW_ATA66_3 1
443#define HPT366_MAX_DEVS 8
444
445
446enum ata_clock {
447 ATA_CLOCK_25MHZ,
448 ATA_CLOCK_33MHZ,
449 ATA_CLOCK_40MHZ,
450 ATA_CLOCK_50MHZ,
451 ATA_CLOCK_66MHZ,
452 NUM_ATA_CLOCKS
453};
454
455struct hpt_timings {
456 u32 pio_mask;
457 u32 dma_mask;
458 u32 ultra_mask;
459 u32 *clock_table[NUM_ATA_CLOCKS];
460};
461
462
463
464
465
466struct hpt_info {
467 char *chip_name;
468 u8 chip_type;
469 u8 udma_mask;
470 u8 dpll_clk;
471 u8 pci_clk;
472 struct hpt_timings *timings;
473 u8 clock;
474};
475
476
477enum {
478 HPT36x,
479 HPT370,
480 HPT370A,
481 HPT374,
482 HPT372,
483 HPT372A,
484 HPT302,
485 HPT371,
486 HPT372N,
487 HPT302N,
488 HPT371N
489};
490
491static struct hpt_timings hpt36x_timings = {
492 .pio_mask = 0xc1f8ffff,
493 .dma_mask = 0x303800ff,
494 .ultra_mask = 0x30070000,
495 .clock_table = {
496 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
497 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
498 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
499 [ATA_CLOCK_50MHZ] = NULL,
500 [ATA_CLOCK_66MHZ] = NULL
501 }
502};
503
504static struct hpt_timings hpt37x_timings = {
505 .pio_mask = 0xcfc3ffff,
506 .dma_mask = 0x31c001ff,
507 .ultra_mask = 0x303c0000,
508 .clock_table = {
509 [ATA_CLOCK_25MHZ] = NULL,
510 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
511 [ATA_CLOCK_40MHZ] = NULL,
512 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
513 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
514 }
515};
516
517static const struct hpt_info hpt36x __devinitdata = {
518 .chip_name = "HPT36x",
519 .chip_type = HPT36x,
520 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
521 .dpll_clk = 0,
522 .timings = &hpt36x_timings
523};
524
525static const struct hpt_info hpt370 __devinitdata = {
526 .chip_name = "HPT370",
527 .chip_type = HPT370,
528 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
529 .dpll_clk = 48,
530 .timings = &hpt37x_timings
531};
532
533static const struct hpt_info hpt370a __devinitdata = {
534 .chip_name = "HPT370A",
535 .chip_type = HPT370A,
536 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
537 .dpll_clk = 48,
538 .timings = &hpt37x_timings
539};
540
541static const struct hpt_info hpt374 __devinitdata = {
542 .chip_name = "HPT374",
543 .chip_type = HPT374,
544 .udma_mask = ATA_UDMA5,
545 .dpll_clk = 48,
546 .timings = &hpt37x_timings
547};
548
549static const struct hpt_info hpt372 __devinitdata = {
550 .chip_name = "HPT372",
551 .chip_type = HPT372,
552 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
553 .dpll_clk = 55,
554 .timings = &hpt37x_timings
555};
556
557static const struct hpt_info hpt372a __devinitdata = {
558 .chip_name = "HPT372A",
559 .chip_type = HPT372A,
560 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
561 .dpll_clk = 66,
562 .timings = &hpt37x_timings
563};
564
565static const struct hpt_info hpt302 __devinitdata = {
566 .chip_name = "HPT302",
567 .chip_type = HPT302,
568 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
569 .dpll_clk = 66,
570 .timings = &hpt37x_timings
571};
572
573static const struct hpt_info hpt371 __devinitdata = {
574 .chip_name = "HPT371",
575 .chip_type = HPT371,
576 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
577 .dpll_clk = 66,
578 .timings = &hpt37x_timings
579};
580
581static const struct hpt_info hpt372n __devinitdata = {
582 .chip_name = "HPT372N",
583 .chip_type = HPT372N,
584 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
585 .dpll_clk = 77,
586 .timings = &hpt37x_timings
587};
588
589static const struct hpt_info hpt302n __devinitdata = {
590 .chip_name = "HPT302N",
591 .chip_type = HPT302N,
592 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
593 .dpll_clk = 77,
594 .timings = &hpt37x_timings
595};
596
597static const struct hpt_info hpt371n __devinitdata = {
598 .chip_name = "HPT371N",
599 .chip_type = HPT371N,
600 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
601 .dpll_clk = 77,
602 .timings = &hpt37x_timings
603};
604
605static int check_in_drive_list(ide_drive_t *drive, const char **list)
606{
607 char *m = (char *)&drive->id[ATA_ID_PROD];
608
609 while (*list)
610 if (!strcmp(*list++, m))
611 return 1;
612 return 0;
613}
614
615static struct hpt_info *hpt3xx_get_info(struct device *dev)
616{
617 struct ide_host *host = dev_get_drvdata(dev);
618 struct hpt_info *info = (struct hpt_info *)host->host_priv;
619
620 return dev == host->dev[1] ? info + 1 : info;
621}
622
623
624
625
626
627
628static u8 hpt3xx_udma_filter(ide_drive_t *drive)
629{
630 ide_hwif_t *hwif = HWIF(drive);
631 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
632 u8 mask = hwif->ultra_mask;
633
634 switch (info->chip_type) {
635 case HPT36x:
636 if (!HPT366_ALLOW_ATA66_4 ||
637 check_in_drive_list(drive, bad_ata66_4))
638 mask = ATA_UDMA3;
639
640 if (!HPT366_ALLOW_ATA66_3 ||
641 check_in_drive_list(drive, bad_ata66_3))
642 mask = ATA_UDMA2;
643 break;
644 case HPT370:
645 if (!HPT370_ALLOW_ATA100_5 ||
646 check_in_drive_list(drive, bad_ata100_5))
647 mask = ATA_UDMA4;
648 break;
649 case HPT370A:
650 if (!HPT370_ALLOW_ATA100_5 ||
651 check_in_drive_list(drive, bad_ata100_5))
652 return ATA_UDMA4;
653 case HPT372 :
654 case HPT372A:
655 case HPT372N:
656 case HPT374 :
657 if (ata_id_is_sata(drive->id))
658 mask &= ~0x0e;
659
660 default:
661 return mask;
662 }
663
664 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
665}
666
667static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
668{
669 ide_hwif_t *hwif = HWIF(drive);
670 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
671
672 switch (info->chip_type) {
673 case HPT372 :
674 case HPT372A:
675 case HPT372N:
676 case HPT374 :
677 if (ata_id_is_sata(drive->id))
678 return 0x00;
679
680 default:
681 return 0x07;
682 }
683}
684
685static u32 get_speed_setting(u8 speed, struct hpt_info *info)
686{
687 int i;
688
689
690
691
692
693
694
695 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
696 if (xfer_speeds[i] == speed)
697 break;
698
699 return info->timings->clock_table[info->clock][i];
700}
701
702static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
703{
704 ide_hwif_t *hwif = drive->hwif;
705 struct pci_dev *dev = to_pci_dev(hwif->dev);
706 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
707 struct hpt_timings *t = info->timings;
708 u8 itr_addr = 0x40 + (drive->dn * 4);
709 u32 old_itr = 0;
710 u32 new_itr = get_speed_setting(speed, info);
711 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
712 (speed < XFER_UDMA_0 ? t->dma_mask :
713 t->ultra_mask);
714
715 pci_read_config_dword(dev, itr_addr, &old_itr);
716 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
717
718
719
720
721 new_itr &= ~0xc0000000;
722
723 pci_write_config_dword(dev, itr_addr, new_itr);
724}
725
726static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
727{
728 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
729}
730
731static void hpt3xx_quirkproc(ide_drive_t *drive)
732{
733 char *m = (char *)&drive->id[ATA_ID_PROD];
734 const char **list = quirk_drives;
735
736 while (*list)
737 if (strstr(m, *list++)) {
738 drive->quirk_list = 1;
739 return;
740 }
741
742 drive->quirk_list = 0;
743}
744
745static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
746{
747 ide_hwif_t *hwif = HWIF(drive);
748 struct pci_dev *dev = to_pci_dev(hwif->dev);
749 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
750
751 if (drive->quirk_list == 0)
752 return;
753
754 if (info->chip_type >= HPT370) {
755 u8 scr1 = 0;
756
757 pci_read_config_byte(dev, 0x5a, &scr1);
758 if (((scr1 & 0x10) >> 4) != mask) {
759 if (mask)
760 scr1 |= 0x10;
761 else
762 scr1 &= ~0x10;
763 pci_write_config_byte(dev, 0x5a, scr1);
764 }
765 } else if (mask)
766 disable_irq(hwif->irq);
767 else
768 enable_irq(hwif->irq);
769}
770
771
772
773
774
775static void hpt366_dma_lost_irq(ide_drive_t *drive)
776{
777 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
778 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
779
780 pci_read_config_byte(dev, 0x50, &mcr1);
781 pci_read_config_byte(dev, 0x52, &mcr3);
782 pci_read_config_byte(dev, 0x5a, &scr1);
783 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
784 drive->name, __func__, mcr1, mcr3, scr1);
785 if (scr1 & 0x10)
786 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
787 ide_dma_lost_irq(drive);
788}
789
790static void hpt370_clear_engine(ide_drive_t *drive)
791{
792 ide_hwif_t *hwif = HWIF(drive);
793 struct pci_dev *dev = to_pci_dev(hwif->dev);
794
795 pci_write_config_byte(dev, hwif->select_data, 0x37);
796 udelay(10);
797}
798
799static void hpt370_irq_timeout(ide_drive_t *drive)
800{
801 ide_hwif_t *hwif = HWIF(drive);
802 struct pci_dev *dev = to_pci_dev(hwif->dev);
803 u16 bfifo = 0;
804 u8 dma_cmd;
805
806 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
807 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
808
809
810 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
811
812 outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD);
813 hpt370_clear_engine(drive);
814}
815
816static void hpt370_dma_start(ide_drive_t *drive)
817{
818#ifdef HPT_RESET_STATE_ENGINE
819 hpt370_clear_engine(drive);
820#endif
821 ide_dma_start(drive);
822}
823
824static int hpt370_dma_end(ide_drive_t *drive)
825{
826 ide_hwif_t *hwif = HWIF(drive);
827 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
828
829 if (dma_stat & 0x01) {
830
831 udelay(20);
832 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
833 if (dma_stat & 0x01)
834 hpt370_irq_timeout(drive);
835 }
836 return ide_dma_end(drive);
837}
838
839static void hpt370_dma_timeout(ide_drive_t *drive)
840{
841 hpt370_irq_timeout(drive);
842 ide_dma_timeout(drive);
843}
844
845
846static int hpt374_dma_test_irq(ide_drive_t *drive)
847{
848 ide_hwif_t *hwif = HWIF(drive);
849 struct pci_dev *dev = to_pci_dev(hwif->dev);
850 u16 bfifo = 0;
851 u8 dma_stat;
852
853 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
854 if (bfifo & 0x1FF) {
855
856 return 0;
857 }
858
859 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
860
861 if (dma_stat & 4)
862 return 1;
863
864 return 0;
865}
866
867static int hpt374_dma_end(ide_drive_t *drive)
868{
869 ide_hwif_t *hwif = HWIF(drive);
870 struct pci_dev *dev = to_pci_dev(hwif->dev);
871 u8 mcr = 0, mcr_addr = hwif->select_data;
872 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
873
874 pci_read_config_byte(dev, 0x6a, &bwsr);
875 pci_read_config_byte(dev, mcr_addr, &mcr);
876 if (bwsr & mask)
877 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
878 return ide_dma_end(drive);
879}
880
881
882
883
884
885
886
887
888
889static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
890{
891 unsigned long base = hwif->extra_base;
892 u8 scr2 = inb(base + 0x6b);
893
894 if ((scr2 & 0x7f) == mode)
895 return;
896
897
898 outb(0x80, base + 0x63);
899 outb(0x80, base + 0x67);
900
901
902 outb(mode, base + 0x6b);
903 outb(0xc0, base + 0x69);
904
905
906
907
908
909 outb(inb(base + 0x60) | 0x32, base + 0x60);
910 outb(inb(base + 0x64) | 0x32, base + 0x64);
911
912
913 outb(0x00, base + 0x69);
914
915
916 outb(0x00, base + 0x63);
917 outb(0x00, base + 0x67);
918}
919
920
921
922
923
924
925
926
927
928
929static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
930{
931 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
932}
933
934
935
936
937
938
939
940
941static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
942{
943 u32 dpll = (f_high << 16) | f_low | 0x100;
944 u8 scr2;
945 int i;
946
947 pci_write_config_dword(dev, 0x5c, dpll);
948
949
950 for(i = 0; i < 0x5000; ++i) {
951 udelay(50);
952 pci_read_config_byte(dev, 0x5b, &scr2);
953 if (scr2 & 0x80)
954 break;
955 }
956
957 for(i = 0; i < 0x1000; ++i) {
958 pci_read_config_byte(dev, 0x5b, &scr2);
959
960 if(!(scr2 & 0x80))
961 return 0;
962 }
963
964 pci_read_config_dword (dev, 0x5c, &dpll);
965 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
966 return 1;
967}
968
969static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
970{
971 struct ide_host *host = pci_get_drvdata(dev);
972 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
973 u8 chip_type = info->chip_type;
974 u8 new_mcr, old_mcr = 0;
975
976
977
978
979
980 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
981
982 if (chip_type >= HPT374)
983 new_mcr = old_mcr & ~0x07;
984 else if (chip_type >= HPT370) {
985 new_mcr = old_mcr;
986 new_mcr &= ~0x02;
987#ifdef HPT_DELAY_INTERRUPT
988 new_mcr &= ~0x01;
989#else
990 new_mcr |= 0x01;
991#endif
992 } else
993 new_mcr = old_mcr & ~0x80;
994
995 if (new_mcr != old_mcr)
996 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
997}
998
999static unsigned int init_chipset_hpt366(struct pci_dev *dev)
1000{
1001 unsigned long io_base = pci_resource_start(dev, 4);
1002 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
1003 const char *name = DRV_NAME;
1004 u8 pci_clk, dpll_clk = 0;
1005 u8 chip_type;
1006 enum ata_clock clock;
1007
1008 chip_type = info->chip_type;
1009
1010 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1011 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1012 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1013 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1014
1015
1016
1017
1018 if (chip_type >= HPT370) {
1019 u8 scr1 = 0;
1020 u16 f_cnt = 0;
1021 u32 temp = 0;
1022
1023
1024 pci_read_config_byte(dev, 0x5a, &scr1);
1025 if (scr1 & 0x10)
1026 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1027
1028
1029
1030
1031
1032 if (chip_type == HPT372A)
1033 outb(0x0e, io_base + 0x9c);
1034
1035
1036
1037
1038
1039 pci_write_config_byte(dev, 0x5b, 0x23);
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1058 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1059 dev->devfn - 1);
1060 unsigned long io_base = pci_resource_start(dev1, 4);
1061
1062 temp = inl(io_base + 0x90);
1063 pci_dev_put(dev1);
1064 } else
1065 temp = inl(io_base + 0x90);
1066
1067
1068
1069
1070
1071
1072 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1073 int i;
1074
1075 printk(KERN_WARNING "%s %s: no clock data saved by "
1076 "BIOS\n", name, pci_name(dev));
1077
1078
1079 for (temp = i = 0; i < 128; i++) {
1080 pci_read_config_word(dev, 0x78, &f_cnt);
1081 temp += f_cnt & 0x1ff;
1082 mdelay(1);
1083 }
1084 f_cnt = temp / 128;
1085 } else
1086 f_cnt = temp & 0x1ff;
1087
1088 dpll_clk = info->dpll_clk;
1089 pci_clk = (f_cnt * dpll_clk) / 192;
1090
1091
1092 if (pci_clk < 40)
1093 pci_clk = 33;
1094 else if(pci_clk < 45)
1095 pci_clk = 40;
1096 else if(pci_clk < 55)
1097 pci_clk = 50;
1098 else
1099 pci_clk = 66;
1100
1101 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1102 "assuming %d MHz PCI\n", name, pci_name(dev),
1103 dpll_clk, f_cnt, pci_clk);
1104 } else {
1105 u32 itr1 = 0;
1106
1107 pci_read_config_dword(dev, 0x40, &itr1);
1108
1109
1110 switch((itr1 >> 8) & 0x07) {
1111 case 0x09:
1112 pci_clk = 40;
1113 break;
1114 case 0x05:
1115 pci_clk = 25;
1116 break;
1117 case 0x07:
1118 default:
1119 pci_clk = 33;
1120 break;
1121 }
1122 }
1123
1124
1125 switch (pci_clk) {
1126 case 25:
1127 clock = ATA_CLOCK_25MHZ;
1128 break;
1129 case 33:
1130 default:
1131 clock = ATA_CLOCK_33MHZ;
1132 break;
1133 case 40:
1134 clock = ATA_CLOCK_40MHZ;
1135 break;
1136 case 50:
1137 clock = ATA_CLOCK_50MHZ;
1138 break;
1139 case 66:
1140 clock = ATA_CLOCK_66MHZ;
1141 break;
1142 }
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1153 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1154 int adjust;
1155
1156
1157
1158
1159
1160 if (info->udma_mask == ATA_UDMA6) {
1161 dpll_clk = 66;
1162 clock = ATA_CLOCK_66MHZ;
1163 } else if (dpll_clk) {
1164 dpll_clk = 50;
1165 clock = ATA_CLOCK_50MHZ;
1166 }
1167
1168 if (info->timings->clock_table[clock] == NULL) {
1169 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1170 name, pci_name(dev));
1171 return -EIO;
1172 }
1173
1174
1175 pci_write_config_byte(dev, 0x5b, 0x21);
1176
1177
1178
1179
1180
1181 f_low = (pci_clk * 48) / dpll_clk;
1182
1183 for (adjust = 0; adjust < 8; adjust++) {
1184 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1185 break;
1186
1187
1188
1189
1190 if (adjust & 1)
1191 f_low -= adjust >> 1;
1192 else
1193 f_low += adjust >> 1;
1194 }
1195 if (adjust == 8) {
1196 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1197 name, pci_name(dev));
1198 return -EIO;
1199 }
1200
1201 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1202 name, pci_name(dev), dpll_clk);
1203 } else {
1204
1205 dpll_clk = 0;
1206
1207 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1208 name, pci_name(dev), pci_clk);
1209 }
1210
1211
1212 info->dpll_clk = dpll_clk;
1213 info->pci_clk = pci_clk;
1214 info->clock = clock;
1215
1216 if (chip_type >= HPT370) {
1217 u8 mcr1, mcr4;
1218
1219
1220
1221
1222
1223 pci_read_config_byte (dev, 0x50, &mcr1);
1224 pci_read_config_byte (dev, 0x54, &mcr4);
1225 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1226 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1227 udelay(100);
1228 }
1229
1230
1231
1232
1233
1234
1235 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1236 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1237
1238 hpt3xx_disable_fast_irq(dev, 0x50);
1239 hpt3xx_disable_fast_irq(dev, 0x54);
1240
1241 return dev->irq;
1242}
1243
1244static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1245{
1246 struct pci_dev *dev = to_pci_dev(hwif->dev);
1247 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1248 u8 chip_type = info->chip_type;
1249 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1250
1251
1252
1253
1254
1255
1256 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1257
1258
1259
1260
1261
1262 u8 mcr_addr = hwif->select_data + 2;
1263 u16 mcr;
1264
1265 pci_read_config_word(dev, mcr_addr, &mcr);
1266 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1267
1268 pci_read_config_byte(dev, 0x5a, &scr1);
1269 pci_write_config_word(dev, mcr_addr, mcr);
1270 } else if (chip_type >= HPT370) {
1271
1272
1273
1274
1275 u8 scr2 = 0;
1276
1277 pci_read_config_byte(dev, 0x5b, &scr2);
1278 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1279
1280 pci_read_config_byte(dev, 0x5a, &scr1);
1281 pci_write_config_byte(dev, 0x5b, scr2);
1282 } else
1283 pci_read_config_byte(dev, 0x5a, &scr1);
1284
1285 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1286}
1287
1288static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1289{
1290 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1291 int serialize = HPT_SERIALIZE_IO;
1292 u8 chip_type = info->chip_type;
1293
1294
1295 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1296
1297
1298
1299
1300
1301
1302
1303 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1304
1305
1306
1307
1308 serialize = 1;
1309 hwif->rw_disk = &hpt3xxn_rw_disk;
1310 }
1311
1312
1313 if (serialize && hwif->mate)
1314 hwif->serialized = hwif->mate->serialized = 1;
1315}
1316
1317static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1318 const struct ide_port_info *d)
1319{
1320 struct pci_dev *dev = to_pci_dev(hwif->dev);
1321 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1322 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1323
1324 if (base == 0)
1325 return -1;
1326
1327 hwif->dma_base = base;
1328
1329 if (ide_pci_check_simplex(hwif, d) < 0)
1330 return -1;
1331
1332 if (ide_pci_set_master(dev, d->name) < 0)
1333 return -1;
1334
1335 dma_old = inb(base + 2);
1336
1337 local_irq_save(flags);
1338
1339 dma_new = dma_old;
1340 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1341 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1342
1343 if (masterdma & 0x30) dma_new |= 0x20;
1344 if ( slavedma & 0x30) dma_new |= 0x40;
1345 if (dma_new != dma_old)
1346 outb(dma_new, base + 2);
1347
1348 local_irq_restore(flags);
1349
1350 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1351 hwif->name, base, base + 7);
1352
1353 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1354
1355 if (ide_allocate_dma_engine(hwif))
1356 return -1;
1357
1358 hwif->dma_ops = &sff_dma_ops;
1359
1360 return 0;
1361}
1362
1363static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1364{
1365 if (dev2->irq != dev->irq) {
1366
1367 dev2->irq = dev->irq;
1368 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1369 "fixed\n", pci_name(dev2));
1370 }
1371}
1372
1373static void __devinit hpt371_init(struct pci_dev *dev)
1374{
1375 u8 mcr1 = 0;
1376
1377
1378
1379
1380
1381
1382
1383 pci_read_config_byte(dev, 0x50, &mcr1);
1384 if (mcr1 & 0x04)
1385 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1386}
1387
1388static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1389{
1390 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1391
1392
1393
1394
1395
1396 pci_read_config_byte(dev, 0x50, &mcr1);
1397 if (mcr1 & 0x30)
1398 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1399
1400 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1401 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1402
1403 if (pin1 != pin2 && dev->irq == dev2->irq) {
1404 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1405 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1406 return 1;
1407 }
1408
1409 return 0;
1410}
1411
1412#define IDE_HFLAGS_HPT3XX \
1413 (IDE_HFLAG_NO_ATAPI_DMA | \
1414 IDE_HFLAG_OFF_BOARD)
1415
1416static const struct ide_port_ops hpt3xx_port_ops = {
1417 .set_pio_mode = hpt3xx_set_pio_mode,
1418 .set_dma_mode = hpt3xx_set_mode,
1419 .quirkproc = hpt3xx_quirkproc,
1420 .maskproc = hpt3xx_maskproc,
1421 .mdma_filter = hpt3xx_mdma_filter,
1422 .udma_filter = hpt3xx_udma_filter,
1423 .cable_detect = hpt3xx_cable_detect,
1424};
1425
1426static const struct ide_dma_ops hpt37x_dma_ops = {
1427 .dma_host_set = ide_dma_host_set,
1428 .dma_setup = ide_dma_setup,
1429 .dma_exec_cmd = ide_dma_exec_cmd,
1430 .dma_start = ide_dma_start,
1431 .dma_end = hpt374_dma_end,
1432 .dma_test_irq = hpt374_dma_test_irq,
1433 .dma_lost_irq = ide_dma_lost_irq,
1434 .dma_timeout = ide_dma_timeout,
1435};
1436
1437static const struct ide_dma_ops hpt370_dma_ops = {
1438 .dma_host_set = ide_dma_host_set,
1439 .dma_setup = ide_dma_setup,
1440 .dma_exec_cmd = ide_dma_exec_cmd,
1441 .dma_start = hpt370_dma_start,
1442 .dma_end = hpt370_dma_end,
1443 .dma_test_irq = ide_dma_test_irq,
1444 .dma_lost_irq = ide_dma_lost_irq,
1445 .dma_timeout = hpt370_dma_timeout,
1446};
1447
1448static const struct ide_dma_ops hpt36x_dma_ops = {
1449 .dma_host_set = ide_dma_host_set,
1450 .dma_setup = ide_dma_setup,
1451 .dma_exec_cmd = ide_dma_exec_cmd,
1452 .dma_start = ide_dma_start,
1453 .dma_end = ide_dma_end,
1454 .dma_test_irq = ide_dma_test_irq,
1455 .dma_lost_irq = hpt366_dma_lost_irq,
1456 .dma_timeout = ide_dma_timeout,
1457};
1458
1459static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1460 {
1461 .name = DRV_NAME,
1462 .init_chipset = init_chipset_hpt366,
1463 .init_hwif = init_hwif_hpt366,
1464 .init_dma = init_dma_hpt366,
1465
1466
1467
1468
1469
1470
1471 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1472 .port_ops = &hpt3xx_port_ops,
1473 .dma_ops = &hpt36x_dma_ops,
1474 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1475 .pio_mask = ATA_PIO4,
1476 .mwdma_mask = ATA_MWDMA2,
1477 },
1478 {
1479 .name = DRV_NAME,
1480 .init_chipset = init_chipset_hpt366,
1481 .init_hwif = init_hwif_hpt366,
1482 .init_dma = init_dma_hpt366,
1483 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1484 .port_ops = &hpt3xx_port_ops,
1485 .dma_ops = &hpt37x_dma_ops,
1486 .host_flags = IDE_HFLAGS_HPT3XX,
1487 .pio_mask = ATA_PIO4,
1488 .mwdma_mask = ATA_MWDMA2,
1489 }
1490};
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1501{
1502 const struct hpt_info *info = NULL;
1503 struct hpt_info *dyn_info;
1504 struct pci_dev *dev2 = NULL;
1505 struct ide_port_info d;
1506 u8 idx = id->driver_data;
1507 u8 rev = dev->revision;
1508 int ret;
1509
1510 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1511 return -ENODEV;
1512
1513 switch (idx) {
1514 case 0:
1515 if (rev < 3)
1516 info = &hpt36x;
1517 else {
1518 switch (min_t(u8, rev, 6)) {
1519 case 3: info = &hpt370; break;
1520 case 4: info = &hpt370a; break;
1521 case 5: info = &hpt372; break;
1522 case 6: info = &hpt372n; break;
1523 }
1524 idx++;
1525 }
1526 break;
1527 case 1:
1528 info = (rev > 1) ? &hpt372n : &hpt372a;
1529 break;
1530 case 2:
1531 info = (rev > 1) ? &hpt302n : &hpt302;
1532 break;
1533 case 3:
1534 hpt371_init(dev);
1535 info = (rev > 1) ? &hpt371n : &hpt371;
1536 break;
1537 case 4:
1538 info = &hpt374;
1539 break;
1540 case 5:
1541 info = &hpt372n;
1542 break;
1543 }
1544
1545 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1546
1547 d = hpt366_chipsets[min_t(u8, idx, 1)];
1548
1549 d.udma_mask = info->udma_mask;
1550
1551
1552 if (info == &hpt370 || info == &hpt370a)
1553 d.dma_ops = &hpt370_dma_ops;
1554
1555 if (info == &hpt36x || info == &hpt374)
1556 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1557
1558 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1559 if (dyn_info == NULL) {
1560 printk(KERN_ERR "%s %s: out of memory!\n",
1561 d.name, pci_name(dev));
1562 pci_dev_put(dev2);
1563 return -ENOMEM;
1564 }
1565
1566
1567
1568
1569
1570 memcpy(dyn_info, info, sizeof(*dyn_info));
1571
1572 if (dev2) {
1573 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1574
1575 if (info == &hpt374)
1576 hpt374_init(dev, dev2);
1577 else {
1578 if (hpt36x_init(dev, dev2))
1579 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1580 }
1581
1582 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1583 if (ret < 0) {
1584 pci_dev_put(dev2);
1585 kfree(dyn_info);
1586 }
1587 return ret;
1588 }
1589
1590 ret = ide_pci_init_one(dev, &d, dyn_info);
1591 if (ret < 0)
1592 kfree(dyn_info);
1593
1594 return ret;
1595}
1596
1597static void __devexit hpt366_remove(struct pci_dev *dev)
1598{
1599 struct ide_host *host = pci_get_drvdata(dev);
1600 struct ide_info *info = host->host_priv;
1601 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1602
1603 ide_pci_remove(dev);
1604 pci_dev_put(dev2);
1605 kfree(info);
1606}
1607
1608static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
1609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1610 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1611 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1612 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1613 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1614 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1615 { 0, },
1616};
1617MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1618
1619static struct pci_driver hpt366_pci_driver = {
1620 .name = "HPT366_IDE",
1621 .id_table = hpt366_pci_tbl,
1622 .probe = hpt366_init_one,
1623 .remove = __devexit_p(hpt366_remove),
1624 .suspend = ide_pci_suspend,
1625 .resume = ide_pci_resume,
1626};
1627
1628static int __init hpt366_ide_init(void)
1629{
1630 return ide_pci_register_driver(&hpt366_pci_driver);
1631}
1632
1633static void __exit hpt366_ide_exit(void)
1634{
1635 pci_unregister_driver(&hpt366_pci_driver);
1636}
1637
1638module_init(hpt366_ide_init);
1639module_exit(hpt366_ide_exit);
1640
1641MODULE_AUTHOR("Andre Hedrick");
1642MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1643MODULE_LICENSE("GPL");