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52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/kernel.h>
55#include <linux/string.h>
56#include <linux/timer.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/slab.h>
60#include <linux/interrupt.h>
61#include <linux/pci.h>
62#include <linux/netdevice.h>
63#include <linux/init.h>
64#include <linux/mii.h>
65#include <linux/etherdevice.h>
66#include <linux/skbuff.h>
67#include <linux/delay.h>
68#include <linux/ethtool.h>
69#include <linux/crc32.h>
70#include <linux/bitops.h>
71#include <linux/dma-mapping.h>
72
73#include <asm/processor.h>
74#include <asm/io.h>
75#include <asm/irq.h>
76#include <asm/uaccess.h>
77
78#include "sis900.h"
79
80#define SIS900_MODULE_NAME "sis900"
81#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
82
83static char version[] __devinitdata =
84KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
85
86static int max_interrupt_work = 40;
87static int multicast_filter_limit = 128;
88
89static int sis900_debug = -1;
90
91#define SIS900_DEF_MSG \
92 (NETIF_MSG_DRV | \
93 NETIF_MSG_LINK | \
94 NETIF_MSG_RX_ERR | \
95 NETIF_MSG_TX_ERR)
96
97
98#define TX_TIMEOUT (4*HZ)
99
100enum {
101 SIS_900 = 0,
102 SIS_7016
103};
104static const char * card_names[] = {
105 "SiS 900 PCI Fast Ethernet",
106 "SiS 7016 PCI Fast Ethernet"
107};
108static struct pci_device_id sis900_pci_tbl [] = {
109 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_900,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
111 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7016,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
113 {0,}
114};
115MODULE_DEVICE_TABLE (pci, sis900_pci_tbl);
116
117static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex);
118
119static const struct mii_chip_info {
120 const char * name;
121 u16 phy_id0;
122 u16 phy_id1;
123 u8 phy_types;
124#define HOME 0x0001
125#define LAN 0x0002
126#define MIX 0x0003
127#define UNKNOWN 0x0
128} mii_chip_table[] = {
129 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
130 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
131 { "SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, LAN },
132 { "Altimata AC101LF PHY", 0x0022, 0x5520, LAN },
133 { "ADM 7001 LAN PHY", 0x002e, 0xcc60, LAN },
134 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
135 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
136 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
137 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
138 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
139 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
140 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
141 { "VIA 6103 PHY", 0x0101, 0x8f20, LAN },
142 {NULL,},
143};
144
145struct mii_phy {
146 struct mii_phy * next;
147 int phy_addr;
148 u16 phy_id0;
149 u16 phy_id1;
150 u16 status;
151 u8 phy_types;
152};
153
154typedef struct _BufferDesc {
155 u32 link;
156 u32 cmdsts;
157 u32 bufptr;
158} BufferDesc;
159
160struct sis900_private {
161 struct pci_dev * pci_dev;
162
163 spinlock_t lock;
164
165 struct mii_phy * mii;
166 struct mii_phy * first_mii;
167 unsigned int cur_phy;
168 struct mii_if_info mii_info;
169
170 struct timer_list timer;
171 u8 autong_complete;
172
173 u32 msg_enable;
174
175 unsigned int cur_rx, dirty_rx;
176 unsigned int cur_tx, dirty_tx;
177
178
179 struct sk_buff *tx_skbuff[NUM_TX_DESC];
180 struct sk_buff *rx_skbuff[NUM_RX_DESC];
181 BufferDesc *tx_ring;
182 BufferDesc *rx_ring;
183
184 dma_addr_t tx_ring_dma;
185 dma_addr_t rx_ring_dma;
186
187 unsigned int tx_full;
188 u8 host_bridge_rev;
189 u8 chipset_rev;
190};
191
192MODULE_AUTHOR("Jim Huang <cmhuang@sis.com.tw>, Ollie Lho <ollie@sis.com.tw>");
193MODULE_DESCRIPTION("SiS 900 PCI Fast Ethernet driver");
194MODULE_LICENSE("GPL");
195
196module_param(multicast_filter_limit, int, 0444);
197module_param(max_interrupt_work, int, 0444);
198module_param(sis900_debug, int, 0444);
199MODULE_PARM_DESC(multicast_filter_limit, "SiS 900/7016 maximum number of filtered multicast addresses");
200MODULE_PARM_DESC(max_interrupt_work, "SiS 900/7016 maximum events handled per interrupt");
201MODULE_PARM_DESC(sis900_debug, "SiS 900/7016 bitmapped debugging message level");
202
203#ifdef CONFIG_NET_POLL_CONTROLLER
204static void sis900_poll(struct net_device *dev);
205#endif
206static int sis900_open(struct net_device *net_dev);
207static int sis900_mii_probe (struct net_device * net_dev);
208static void sis900_init_rxfilter (struct net_device * net_dev);
209static u16 read_eeprom(long ioaddr, int location);
210static int mdio_read(struct net_device *net_dev, int phy_id, int location);
211static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
212static void sis900_timer(unsigned long data);
213static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
214static void sis900_tx_timeout(struct net_device *net_dev);
215static void sis900_init_tx_ring(struct net_device *net_dev);
216static void sis900_init_rx_ring(struct net_device *net_dev);
217static int sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev);
218static int sis900_rx(struct net_device *net_dev);
219static void sis900_finish_xmit (struct net_device *net_dev);
220static irqreturn_t sis900_interrupt(int irq, void *dev_instance);
221static int sis900_close(struct net_device *net_dev);
222static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
223static u16 sis900_mcast_bitnr(u8 *addr, u8 revision);
224static void set_rx_mode(struct net_device *net_dev);
225static void sis900_reset(struct net_device *net_dev);
226static void sis630_set_eq(struct net_device *net_dev, u8 revision);
227static int sis900_set_config(struct net_device *dev, struct ifmap *map);
228static u16 sis900_default_phy(struct net_device * net_dev);
229static void sis900_set_capability( struct net_device *net_dev ,struct mii_phy *phy);
230static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr);
231static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr);
232static void sis900_set_mode (long ioaddr, int speed, int duplex);
233static const struct ethtool_ops sis900_ethtool_ops;
234
235
236
237
238
239
240
241
242
243
244static int __devinit sis900_get_mac_addr(struct pci_dev * pci_dev, struct net_device *net_dev)
245{
246 long ioaddr = pci_resource_start(pci_dev, 0);
247 u16 signature;
248 int i;
249
250
251 signature = (u16) read_eeprom(ioaddr, EEPROMSignature);
252 if (signature == 0xffff || signature == 0x0000) {
253 printk (KERN_WARNING "%s: Error EERPOM read %x\n",
254 pci_name(pci_dev), signature);
255 return 0;
256 }
257
258
259 for (i = 0; i < 3; i++)
260 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
261
262 return 1;
263}
264
265
266
267
268
269
270
271
272
273
274
275static int __devinit sis630e_get_mac_addr(struct pci_dev * pci_dev,
276 struct net_device *net_dev)
277{
278 struct pci_dev *isa_bridge = NULL;
279 u8 reg;
280 int i;
281
282 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, isa_bridge);
283 if (!isa_bridge)
284 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0018, isa_bridge);
285 if (!isa_bridge) {
286 printk(KERN_WARNING "%s: Can not find ISA bridge\n",
287 pci_name(pci_dev));
288 return 0;
289 }
290 pci_read_config_byte(isa_bridge, 0x48, ®);
291 pci_write_config_byte(isa_bridge, 0x48, reg | 0x40);
292
293 for (i = 0; i < 6; i++) {
294 outb(0x09 + i, 0x70);
295 ((u8 *)(net_dev->dev_addr))[i] = inb(0x71);
296 }
297 pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40);
298 pci_dev_put(isa_bridge);
299
300 return 1;
301}
302
303
304
305
306
307
308
309
310
311
312
313
314static int __devinit sis635_get_mac_addr(struct pci_dev * pci_dev,
315 struct net_device *net_dev)
316{
317 long ioaddr = net_dev->base_addr;
318 u32 rfcrSave;
319 u32 i;
320
321 rfcrSave = inl(rfcr + ioaddr);
322
323 outl(rfcrSave | RELOAD, ioaddr + cr);
324 outl(0, ioaddr + cr);
325
326
327 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
328
329
330 for (i = 0 ; i < 3 ; i++) {
331 outl((i << RFADDR_shift), ioaddr + rfcr);
332 *( ((u16 *)net_dev->dev_addr) + i) = inw(ioaddr + rfdr);
333 }
334
335
336 outl(rfcrSave | RFEN, rfcr + ioaddr);
337
338 return 1;
339}
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357static int __devinit sis96x_get_mac_addr(struct pci_dev * pci_dev,
358 struct net_device *net_dev)
359{
360 long ioaddr = net_dev->base_addr;
361 long ee_addr = ioaddr + mear;
362 u32 waittime = 0;
363 int i;
364
365 outl(EEREQ, ee_addr);
366 while(waittime < 2000) {
367 if(inl(ee_addr) & EEGNT) {
368
369
370 for (i = 0; i < 3; i++)
371 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
372
373 outl(EEDONE, ee_addr);
374 return 1;
375 } else {
376 udelay(1);
377 waittime ++;
378 }
379 }
380 outl(EEDONE, ee_addr);
381 return 0;
382}
383
384
385
386
387
388
389
390
391
392
393
394
395static int __devinit sis900_probe(struct pci_dev *pci_dev,
396 const struct pci_device_id *pci_id)
397{
398 struct sis900_private *sis_priv;
399 struct net_device *net_dev;
400 struct pci_dev *dev;
401 dma_addr_t ring_dma;
402 void *ring_space;
403 long ioaddr;
404 int i, ret;
405 const char *card_name = card_names[pci_id->driver_data];
406 const char *dev_name = pci_name(pci_dev);
407 DECLARE_MAC_BUF(mac);
408
409
410#ifndef MODULE
411 static int printed_version;
412 if (!printed_version++)
413 printk(version);
414#endif
415
416
417 ret = pci_enable_device(pci_dev);
418 if(ret) return ret;
419
420 i = pci_set_dma_mask(pci_dev, DMA_32BIT_MASK);
421 if(i){
422 printk(KERN_ERR "sis900.c: architecture does not support "
423 "32bit PCI busmaster DMA\n");
424 return i;
425 }
426
427 pci_set_master(pci_dev);
428
429 net_dev = alloc_etherdev(sizeof(struct sis900_private));
430 if (!net_dev)
431 return -ENOMEM;
432 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
433
434
435 ioaddr = pci_resource_start(pci_dev, 0);
436 ret = pci_request_regions(pci_dev, "sis900");
437 if (ret)
438 goto err_out;
439
440 sis_priv = net_dev->priv;
441 net_dev->base_addr = ioaddr;
442 net_dev->irq = pci_dev->irq;
443 sis_priv->pci_dev = pci_dev;
444 spin_lock_init(&sis_priv->lock);
445
446 pci_set_drvdata(pci_dev, net_dev);
447
448 ring_space = pci_alloc_consistent(pci_dev, TX_TOTAL_SIZE, &ring_dma);
449 if (!ring_space) {
450 ret = -ENOMEM;
451 goto err_out_cleardev;
452 }
453 sis_priv->tx_ring = (BufferDesc *)ring_space;
454 sis_priv->tx_ring_dma = ring_dma;
455
456 ring_space = pci_alloc_consistent(pci_dev, RX_TOTAL_SIZE, &ring_dma);
457 if (!ring_space) {
458 ret = -ENOMEM;
459 goto err_unmap_tx;
460 }
461 sis_priv->rx_ring = (BufferDesc *)ring_space;
462 sis_priv->rx_ring_dma = ring_dma;
463
464
465 net_dev->open = &sis900_open;
466 net_dev->hard_start_xmit = &sis900_start_xmit;
467 net_dev->stop = &sis900_close;
468 net_dev->set_config = &sis900_set_config;
469 net_dev->set_multicast_list = &set_rx_mode;
470 net_dev->do_ioctl = &mii_ioctl;
471 net_dev->tx_timeout = sis900_tx_timeout;
472 net_dev->watchdog_timeo = TX_TIMEOUT;
473 net_dev->ethtool_ops = &sis900_ethtool_ops;
474
475#ifdef CONFIG_NET_POLL_CONTROLLER
476 net_dev->poll_controller = &sis900_poll;
477#endif
478
479 if (sis900_debug > 0)
480 sis_priv->msg_enable = sis900_debug;
481 else
482 sis_priv->msg_enable = SIS900_DEF_MSG;
483
484 sis_priv->mii_info.dev = net_dev;
485 sis_priv->mii_info.mdio_read = mdio_read;
486 sis_priv->mii_info.mdio_write = mdio_write;
487 sis_priv->mii_info.phy_id_mask = 0x1f;
488 sis_priv->mii_info.reg_num_mask = 0x1f;
489
490
491 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &(sis_priv->chipset_rev));
492 if(netif_msg_probe(sis_priv))
493 printk(KERN_DEBUG "%s: detected revision %2.2x, "
494 "trying to get MAC address...\n",
495 dev_name, sis_priv->chipset_rev);
496
497 ret = 0;
498 if (sis_priv->chipset_rev == SIS630E_900_REV)
499 ret = sis630e_get_mac_addr(pci_dev, net_dev);
500 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
501 ret = sis635_get_mac_addr(pci_dev, net_dev);
502 else if (sis_priv->chipset_rev == SIS96x_900_REV)
503 ret = sis96x_get_mac_addr(pci_dev, net_dev);
504 else
505 ret = sis900_get_mac_addr(pci_dev, net_dev);
506
507 if (ret == 0) {
508 printk(KERN_WARNING "%s: Cannot read MAC address.\n", dev_name);
509 ret = -ENODEV;
510 goto err_unmap_rx;
511 }
512
513
514 if (sis_priv->chipset_rev == SIS630ET_900_REV)
515 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
516
517
518 if (sis900_mii_probe(net_dev) == 0) {
519 printk(KERN_WARNING "%s: Error probing MII device.\n",
520 dev_name);
521 ret = -ENODEV;
522 goto err_unmap_rx;
523 }
524
525
526 dev = pci_get_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, NULL);
527 if (dev) {
528 pci_read_config_byte(dev, PCI_CLASS_REVISION, &sis_priv->host_bridge_rev);
529 pci_dev_put(dev);
530 }
531
532 ret = register_netdev(net_dev);
533 if (ret)
534 goto err_unmap_rx;
535
536
537 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %s\n",
538 net_dev->name, card_name, ioaddr, net_dev->irq,
539 print_mac(mac, net_dev->dev_addr));
540
541
542 ret = (inl(net_dev->base_addr + CFGPMC) & PMESP) >> 27;
543 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
544 printk(KERN_INFO "%s: Wake on LAN only available from suspend to RAM.", net_dev->name);
545
546 return 0;
547
548 err_unmap_rx:
549 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
550 sis_priv->rx_ring_dma);
551 err_unmap_tx:
552 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
553 sis_priv->tx_ring_dma);
554 err_out_cleardev:
555 pci_set_drvdata(pci_dev, NULL);
556 pci_release_regions(pci_dev);
557 err_out:
558 free_netdev(net_dev);
559 return ret;
560}
561
562
563
564
565
566
567
568
569
570
571static int __devinit sis900_mii_probe(struct net_device * net_dev)
572{
573 struct sis900_private * sis_priv = net_dev->priv;
574 const char *dev_name = pci_name(sis_priv->pci_dev);
575 u16 poll_bit = MII_STAT_LINK, status = 0;
576 unsigned long timeout = jiffies + 5 * HZ;
577 int phy_addr;
578
579 sis_priv->mii = NULL;
580
581
582 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
583 struct mii_phy * mii_phy = NULL;
584 u16 mii_status;
585 int i;
586
587 mii_phy = NULL;
588 for(i = 0; i < 2; i++)
589 mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
590
591 if (mii_status == 0xffff || mii_status == 0x0000) {
592 if (netif_msg_probe(sis_priv))
593 printk(KERN_DEBUG "%s: MII at address %d"
594 " not accessible\n",
595 dev_name, phy_addr);
596 continue;
597 }
598
599 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {
600 printk(KERN_WARNING "Cannot allocate mem for struct mii_phy\n");
601 mii_phy = sis_priv->first_mii;
602 while (mii_phy) {
603 struct mii_phy *phy;
604 phy = mii_phy;
605 mii_phy = mii_phy->next;
606 kfree(phy);
607 }
608 return 0;
609 }
610
611 mii_phy->phy_id0 = mdio_read(net_dev, phy_addr, MII_PHY_ID0);
612 mii_phy->phy_id1 = mdio_read(net_dev, phy_addr, MII_PHY_ID1);
613 mii_phy->phy_addr = phy_addr;
614 mii_phy->status = mii_status;
615 mii_phy->next = sis_priv->mii;
616 sis_priv->mii = mii_phy;
617 sis_priv->first_mii = mii_phy;
618
619 for (i = 0; mii_chip_table[i].phy_id1; i++)
620 if ((mii_phy->phy_id0 == mii_chip_table[i].phy_id0 ) &&
621 ((mii_phy->phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){
622 mii_phy->phy_types = mii_chip_table[i].phy_types;
623 if (mii_chip_table[i].phy_types == MIX)
624 mii_phy->phy_types =
625 (mii_status & (MII_STAT_CAN_TX_FDX | MII_STAT_CAN_TX)) ? LAN : HOME;
626 printk(KERN_INFO "%s: %s transceiver found "
627 "at address %d.\n",
628 dev_name,
629 mii_chip_table[i].name,
630 phy_addr);
631 break;
632 }
633
634 if( !mii_chip_table[i].phy_id1 ) {
635 printk(KERN_INFO "%s: Unknown PHY transceiver found at address %d.\n",
636 dev_name, phy_addr);
637 mii_phy->phy_types = UNKNOWN;
638 }
639 }
640
641 if (sis_priv->mii == NULL) {
642 printk(KERN_INFO "%s: No MII transceivers found!\n", dev_name);
643 return 0;
644 }
645
646
647 sis_priv->mii = NULL;
648 sis900_default_phy( net_dev );
649
650
651 if ((sis_priv->mii->phy_id0 == 0x001D) &&
652 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
653 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
654
655
656 if ((sis_priv->mii->phy_id0 == 0x0015) &&
657 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
658 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
659
660 if(status & MII_STAT_LINK){
661 while (poll_bit) {
662 yield();
663
664 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
665 if (time_after_eq(jiffies, timeout)) {
666 printk(KERN_WARNING "%s: reset phy and link down now\n",
667 dev_name);
668 return -ETIME;
669 }
670 }
671 }
672
673 if (sis_priv->chipset_rev == SIS630E_900_REV) {
674
675 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
676 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
677 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
678 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
679
680 }
681
682 if (sis_priv->mii->status & MII_STAT_LINK)
683 netif_carrier_on(net_dev);
684 else
685 netif_carrier_off(net_dev);
686
687 return 1;
688}
689
690
691
692
693
694
695
696
697
698
699static u16 sis900_default_phy(struct net_device * net_dev)
700{
701 struct sis900_private * sis_priv = net_dev->priv;
702 struct mii_phy *phy = NULL, *phy_home = NULL,
703 *default_phy = NULL, *phy_lan = NULL;
704 u16 status;
705
706 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
707 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
708 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
709
710
711 if ((status & MII_STAT_LINK) && !default_phy &&
712 (phy->phy_types != UNKNOWN))
713 default_phy = phy;
714 else {
715 status = mdio_read(net_dev, phy->phy_addr, MII_CONTROL);
716 mdio_write(net_dev, phy->phy_addr, MII_CONTROL,
717 status | MII_CNTL_AUTO | MII_CNTL_ISOLATE);
718 if (phy->phy_types == HOME)
719 phy_home = phy;
720 else if(phy->phy_types == LAN)
721 phy_lan = phy;
722 }
723 }
724
725 if (!default_phy && phy_home)
726 default_phy = phy_home;
727 else if (!default_phy && phy_lan)
728 default_phy = phy_lan;
729 else if (!default_phy)
730 default_phy = sis_priv->first_mii;
731
732 if (sis_priv->mii != default_phy) {
733 sis_priv->mii = default_phy;
734 sis_priv->cur_phy = default_phy->phy_addr;
735 printk(KERN_INFO "%s: Using transceiver found at address %d as default\n",
736 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
737 }
738
739 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
740
741 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
742 status &= (~MII_CNTL_ISOLATE);
743
744 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
745 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
746 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
747
748 return status;
749}
750
751
752
753
754
755
756
757
758
759
760
761static void sis900_set_capability(struct net_device *net_dev, struct mii_phy *phy)
762{
763 u16 cap;
764 u16 status;
765
766 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
767 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
768
769 cap = MII_NWAY_CSMA_CD |
770 ((phy->status & MII_STAT_CAN_TX_FDX)? MII_NWAY_TX_FDX:0) |
771 ((phy->status & MII_STAT_CAN_TX) ? MII_NWAY_TX:0) |
772 ((phy->status & MII_STAT_CAN_T_FDX) ? MII_NWAY_T_FDX:0)|
773 ((phy->status & MII_STAT_CAN_T) ? MII_NWAY_T:0);
774
775 mdio_write(net_dev, phy->phy_addr, MII_ANADV, cap);
776}
777
778
779
780#define eeprom_delay() inl(ee_addr)
781
782
783
784
785
786
787
788
789
790
791static u16 __devinit read_eeprom(long ioaddr, int location)
792{
793 int i;
794 u16 retval = 0;
795 long ee_addr = ioaddr + mear;
796 u32 read_cmd = location | EEread;
797
798 outl(0, ee_addr);
799 eeprom_delay();
800 outl(EECS, ee_addr);
801 eeprom_delay();
802
803
804 for (i = 8; i >= 0; i--) {
805 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
806 outl(dataval, ee_addr);
807 eeprom_delay();
808 outl(dataval | EECLK, ee_addr);
809 eeprom_delay();
810 }
811 outl(EECS, ee_addr);
812 eeprom_delay();
813
814
815 for (i = 16; i > 0; i--) {
816 outl(EECS, ee_addr);
817 eeprom_delay();
818 outl(EECS | EECLK, ee_addr);
819 eeprom_delay();
820 retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
821 eeprom_delay();
822 }
823
824
825 outl(0, ee_addr);
826 eeprom_delay();
827
828 return (retval);
829}
830
831
832
833
834#define mdio_delay() inl(mdio_addr)
835
836static void mdio_idle(long mdio_addr)
837{
838 outl(MDIO | MDDIR, mdio_addr);
839 mdio_delay();
840 outl(MDIO | MDDIR | MDC, mdio_addr);
841}
842
843
844static void mdio_reset(long mdio_addr)
845{
846 int i;
847
848 for (i = 31; i >= 0; i--) {
849 outl(MDDIR | MDIO, mdio_addr);
850 mdio_delay();
851 outl(MDDIR | MDIO | MDC, mdio_addr);
852 mdio_delay();
853 }
854 return;
855}
856
857
858
859
860
861
862
863
864
865
866
867
868static int mdio_read(struct net_device *net_dev, int phy_id, int location)
869{
870 long mdio_addr = net_dev->base_addr + mear;
871 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
872 u16 retval = 0;
873 int i;
874
875 mdio_reset(mdio_addr);
876 mdio_idle(mdio_addr);
877
878 for (i = 15; i >= 0; i--) {
879 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
880 outl(dataval, mdio_addr);
881 mdio_delay();
882 outl(dataval | MDC, mdio_addr);
883 mdio_delay();
884 }
885
886
887 for (i = 16; i > 0; i--) {
888 outl(0, mdio_addr);
889 mdio_delay();
890 retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0);
891 outl(MDC, mdio_addr);
892 mdio_delay();
893 }
894 outl(0x00, mdio_addr);
895
896 return retval;
897}
898
899
900
901
902
903
904
905
906
907
908
909
910
911static void mdio_write(struct net_device *net_dev, int phy_id, int location,
912 int value)
913{
914 long mdio_addr = net_dev->base_addr + mear;
915 int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
916 int i;
917
918 mdio_reset(mdio_addr);
919 mdio_idle(mdio_addr);
920
921
922 for (i = 15; i >= 0; i--) {
923 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
924 outb(dataval, mdio_addr);
925 mdio_delay();
926 outb(dataval | MDC, mdio_addr);
927 mdio_delay();
928 }
929 mdio_delay();
930
931
932 for (i = 15; i >= 0; i--) {
933 int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR;
934 outl(dataval, mdio_addr);
935 mdio_delay();
936 outl(dataval | MDC, mdio_addr);
937 mdio_delay();
938 }
939 mdio_delay();
940
941
942 for (i = 2; i > 0; i--) {
943 outb(0, mdio_addr);
944 mdio_delay();
945 outb(MDC, mdio_addr);
946 mdio_delay();
947 }
948 outl(0x00, mdio_addr);
949
950 return;
951}
952
953
954
955
956
957
958
959
960
961
962
963
964static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr)
965{
966 int i;
967 u16 status;
968
969 for (i = 0; i < 2; i++)
970 status = mdio_read(net_dev, phy_addr, MII_STATUS);
971
972 mdio_write( net_dev, phy_addr, MII_CONTROL, MII_CNTL_RESET );
973
974 return status;
975}
976
977#ifdef CONFIG_NET_POLL_CONTROLLER
978
979
980
981
982
983static void sis900_poll(struct net_device *dev)
984{
985 disable_irq(dev->irq);
986 sis900_interrupt(dev->irq, dev);
987 enable_irq(dev->irq);
988}
989#endif
990
991
992
993
994
995
996
997
998
999static int
1000sis900_open(struct net_device *net_dev)
1001{
1002 struct sis900_private *sis_priv = net_dev->priv;
1003 long ioaddr = net_dev->base_addr;
1004 int ret;
1005
1006
1007 sis900_reset(net_dev);
1008
1009
1010 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1011
1012 ret = request_irq(net_dev->irq, &sis900_interrupt, IRQF_SHARED,
1013 net_dev->name, net_dev);
1014 if (ret)
1015 return ret;
1016
1017 sis900_init_rxfilter(net_dev);
1018
1019 sis900_init_tx_ring(net_dev);
1020 sis900_init_rx_ring(net_dev);
1021
1022 set_rx_mode(net_dev);
1023
1024 netif_start_queue(net_dev);
1025
1026
1027 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1028
1029
1030 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1031 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
1032 outl(IE, ioaddr + ier);
1033
1034 sis900_check_mode(net_dev, sis_priv->mii);
1035
1036
1037
1038 init_timer(&sis_priv->timer);
1039 sis_priv->timer.expires = jiffies + HZ;
1040 sis_priv->timer.data = (unsigned long)net_dev;
1041 sis_priv->timer.function = &sis900_timer;
1042 add_timer(&sis_priv->timer);
1043
1044 return 0;
1045}
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055static void
1056sis900_init_rxfilter (struct net_device * net_dev)
1057{
1058 struct sis900_private *sis_priv = net_dev->priv;
1059 long ioaddr = net_dev->base_addr;
1060 u32 rfcrSave;
1061 u32 i;
1062
1063 rfcrSave = inl(rfcr + ioaddr);
1064
1065
1066 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
1067
1068
1069 for (i = 0 ; i < 3 ; i++) {
1070 u32 w;
1071
1072 w = (u32) *((u16 *)(net_dev->dev_addr)+i);
1073 outl((i << RFADDR_shift), ioaddr + rfcr);
1074 outl(w, ioaddr + rfdr);
1075
1076 if (netif_msg_hw(sis_priv)) {
1077 printk(KERN_DEBUG "%s: Receive Filter Addrss[%d]=%x\n",
1078 net_dev->name, i, inl(ioaddr + rfdr));
1079 }
1080 }
1081
1082
1083 outl(rfcrSave | RFEN, rfcr + ioaddr);
1084}
1085
1086
1087
1088
1089
1090
1091
1092
1093static void
1094sis900_init_tx_ring(struct net_device *net_dev)
1095{
1096 struct sis900_private *sis_priv = net_dev->priv;
1097 long ioaddr = net_dev->base_addr;
1098 int i;
1099
1100 sis_priv->tx_full = 0;
1101 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1102
1103 for (i = 0; i < NUM_TX_DESC; i++) {
1104 sis_priv->tx_skbuff[i] = NULL;
1105
1106 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1107 ((i+1)%NUM_TX_DESC)*sizeof(BufferDesc);
1108 sis_priv->tx_ring[i].cmdsts = 0;
1109 sis_priv->tx_ring[i].bufptr = 0;
1110 }
1111
1112
1113 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1114 if (netif_msg_hw(sis_priv))
1115 printk(KERN_DEBUG "%s: TX descriptor register loaded with: %8.8x\n",
1116 net_dev->name, inl(ioaddr + txdp));
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127static void
1128sis900_init_rx_ring(struct net_device *net_dev)
1129{
1130 struct sis900_private *sis_priv = net_dev->priv;
1131 long ioaddr = net_dev->base_addr;
1132 int i;
1133
1134 sis_priv->cur_rx = 0;
1135 sis_priv->dirty_rx = 0;
1136
1137
1138 for (i = 0; i < NUM_RX_DESC; i++) {
1139 sis_priv->rx_skbuff[i] = NULL;
1140
1141 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1142 ((i+1)%NUM_RX_DESC)*sizeof(BufferDesc);
1143 sis_priv->rx_ring[i].cmdsts = 0;
1144 sis_priv->rx_ring[i].bufptr = 0;
1145 }
1146
1147
1148 for (i = 0; i < NUM_RX_DESC; i++) {
1149 struct sk_buff *skb;
1150
1151 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1152
1153
1154
1155
1156 break;
1157 }
1158 sis_priv->rx_skbuff[i] = skb;
1159 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1160 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
1161 skb->data, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1162 }
1163 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1164
1165
1166 outl(sis_priv->rx_ring_dma, ioaddr + rxdp);
1167 if (netif_msg_hw(sis_priv))
1168 printk(KERN_DEBUG "%s: RX descriptor register loaded with: %8.8x\n",
1169 net_dev->name, inl(ioaddr + rxdp));
1170}
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199static void sis630_set_eq(struct net_device *net_dev, u8 revision)
1200{
1201 struct sis900_private *sis_priv = net_dev->priv;
1202 u16 reg14h, eq_value=0, max_value=0, min_value=0;
1203 int i, maxcount=10;
1204
1205 if ( !(revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1206 revision == SIS630A_900_REV || revision == SIS630ET_900_REV) )
1207 return;
1208
1209 if (netif_carrier_ok(net_dev)) {
1210 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1211 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1212 (0x2200 | reg14h) & 0xBFFF);
1213 for (i=0; i < maxcount; i++) {
1214 eq_value = (0x00F8 & mdio_read(net_dev,
1215 sis_priv->cur_phy, MII_RESV)) >> 3;
1216 if (i == 0)
1217 max_value=min_value=eq_value;
1218 max_value = (eq_value > max_value) ?
1219 eq_value : max_value;
1220 min_value = (eq_value < min_value) ?
1221 eq_value : min_value;
1222 }
1223
1224 if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1225 revision == SIS630ET_900_REV) {
1226 if (max_value < 5)
1227 eq_value = max_value;
1228 else if (max_value >= 5 && max_value < 15)
1229 eq_value = (max_value == min_value) ?
1230 max_value+2 : max_value+1;
1231 else if (max_value >= 15)
1232 eq_value=(max_value == min_value) ?
1233 max_value+6 : max_value+5;
1234 }
1235
1236 if (revision == SIS630A_900_REV &&
1237 (sis_priv->host_bridge_rev == SIS630B0 ||
1238 sis_priv->host_bridge_rev == SIS630B1)) {
1239 if (max_value == 0)
1240 eq_value = 3;
1241 else
1242 eq_value = (max_value + min_value + 1)/2;
1243 }
1244
1245 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1246 reg14h = (reg14h & 0xFF07) | ((eq_value << 3) & 0x00F8);
1247 reg14h = (reg14h | 0x6000) & 0xFDFF;
1248 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1249 } else {
1250 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1251 if (revision == SIS630A_900_REV &&
1252 (sis_priv->host_bridge_rev == SIS630B0 ||
1253 sis_priv->host_bridge_rev == SIS630B1))
1254 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1255 (reg14h | 0x2200) & 0xBFFF);
1256 else
1257 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1258 (reg14h | 0x2000) & 0xBFFF);
1259 }
1260 return;
1261}
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271static void sis900_timer(unsigned long data)
1272{
1273 struct net_device *net_dev = (struct net_device *)data;
1274 struct sis900_private *sis_priv = net_dev->priv;
1275 struct mii_phy *mii_phy = sis_priv->mii;
1276 static const int next_tick = 5*HZ;
1277 u16 status;
1278
1279 if (!sis_priv->autong_complete){
1280 int speed, duplex = 0;
1281
1282 sis900_read_mode(net_dev, &speed, &duplex);
1283 if (duplex){
1284 sis900_set_mode(net_dev->base_addr, speed, duplex);
1285 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1286 netif_start_queue(net_dev);
1287 }
1288
1289 sis_priv->timer.expires = jiffies + HZ;
1290 add_timer(&sis_priv->timer);
1291 return;
1292 }
1293
1294 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1295 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1296
1297
1298 if (!netif_carrier_ok(net_dev)) {
1299 LookForLink:
1300
1301 status = sis900_default_phy(net_dev);
1302 mii_phy = sis_priv->mii;
1303
1304 if (status & MII_STAT_LINK){
1305 sis900_check_mode(net_dev, mii_phy);
1306 netif_carrier_on(net_dev);
1307 }
1308 } else {
1309
1310 if (!(status & MII_STAT_LINK)){
1311 netif_carrier_off(net_dev);
1312 if(netif_msg_link(sis_priv))
1313 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1314
1315
1316 if ((mii_phy->phy_id0 == 0x001D) &&
1317 ((mii_phy->phy_id1 & 0xFFF0) == 0x8000))
1318 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1319
1320 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1321
1322 goto LookForLink;
1323 }
1324 }
1325
1326 sis_priv->timer.expires = jiffies + next_tick;
1327 add_timer(&sis_priv->timer);
1328}
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342static void sis900_check_mode(struct net_device *net_dev, struct mii_phy *mii_phy)
1343{
1344 struct sis900_private *sis_priv = net_dev->priv;
1345 long ioaddr = net_dev->base_addr;
1346 int speed, duplex;
1347
1348 if (mii_phy->phy_types == LAN) {
1349 outl(~EXD & inl(ioaddr + cfg), ioaddr + cfg);
1350 sis900_set_capability(net_dev , mii_phy);
1351 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1352 } else {
1353 outl(EXD | inl(ioaddr + cfg), ioaddr + cfg);
1354 speed = HW_SPEED_HOME;
1355 duplex = FDX_CAPABLE_HALF_SELECTED;
1356 sis900_set_mode(ioaddr, speed, duplex);
1357 sis_priv->autong_complete = 1;
1358 }
1359}
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374static void sis900_set_mode (long ioaddr, int speed, int duplex)
1375{
1376 u32 tx_flags = 0, rx_flags = 0;
1377
1378 if (inl(ioaddr + cfg) & EDB_MASTER_EN) {
1379 tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) |
1380 (TX_FILL_THRESH << TxFILLT_shift);
1381 rx_flags = DMA_BURST_64 << RxMXDMA_shift;
1382 } else {
1383 tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) |
1384 (TX_FILL_THRESH << TxFILLT_shift);
1385 rx_flags = DMA_BURST_512 << RxMXDMA_shift;
1386 }
1387
1388 if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) {
1389 rx_flags |= (RxDRNT_10 << RxDRNT_shift);
1390 tx_flags |= (TxDRNT_10 << TxDRNT_shift);
1391 } else {
1392 rx_flags |= (RxDRNT_100 << RxDRNT_shift);
1393 tx_flags |= (TxDRNT_100 << TxDRNT_shift);
1394 }
1395
1396 if (duplex == FDX_CAPABLE_FULL_SELECTED) {
1397 tx_flags |= (TxCSI | TxHBI);
1398 rx_flags |= RxATX;
1399 }
1400
1401#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1402
1403 rx_flags |= RxAJAB;
1404#endif
1405
1406 outl (tx_flags, ioaddr + txcfg);
1407 outl (rx_flags, ioaddr + rxcfg);
1408}
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr)
1422{
1423 struct sis900_private *sis_priv = net_dev->priv;
1424 int i = 0;
1425 u32 status;
1426
1427 for (i = 0; i < 2; i++)
1428 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1429
1430 if (!(status & MII_STAT_LINK)){
1431 if(netif_msg_link(sis_priv))
1432 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1433 sis_priv->autong_complete = 1;
1434 netif_carrier_off(net_dev);
1435 return;
1436 }
1437
1438
1439 mdio_write(net_dev, phy_addr, MII_CONTROL,
1440 MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1441 sis_priv->autong_complete = 0;
1442}
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex)
1457{
1458 struct sis900_private *sis_priv = net_dev->priv;
1459 struct mii_phy *phy = sis_priv->mii;
1460 int phy_addr = sis_priv->cur_phy;
1461 u32 status;
1462 u16 autoadv, autorec;
1463 int i;
1464
1465 for (i = 0; i < 2; i++)
1466 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1467
1468 if (!(status & MII_STAT_LINK))
1469 return;
1470
1471
1472 autoadv = mdio_read(net_dev, phy_addr, MII_ANADV);
1473 autorec = mdio_read(net_dev, phy_addr, MII_ANLPAR);
1474 status = autoadv & autorec;
1475
1476 *speed = HW_SPEED_10_MBPS;
1477 *duplex = FDX_CAPABLE_HALF_SELECTED;
1478
1479 if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX))
1480 *speed = HW_SPEED_100_MBPS;
1481 if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX))
1482 *duplex = FDX_CAPABLE_FULL_SELECTED;
1483
1484 sis_priv->autong_complete = 1;
1485
1486
1487 if ((phy->phy_id0 == 0x0000) && ((phy->phy_id1 & 0xFFF0) == 0x8200)) {
1488 if (mdio_read(net_dev, phy_addr, MII_CONTROL) & MII_CNTL_FDX)
1489 *duplex = FDX_CAPABLE_FULL_SELECTED;
1490 if (mdio_read(net_dev, phy_addr, 0x0019) & 0x01)
1491 *speed = HW_SPEED_100_MBPS;
1492 }
1493
1494 if(netif_msg_link(sis_priv))
1495 printk(KERN_INFO "%s: Media Link On %s %s-duplex \n",
1496 net_dev->name,
1497 *speed == HW_SPEED_100_MBPS ?
1498 "100mbps" : "10mbps",
1499 *duplex == FDX_CAPABLE_FULL_SELECTED ?
1500 "full" : "half");
1501}
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511static void sis900_tx_timeout(struct net_device *net_dev)
1512{
1513 struct sis900_private *sis_priv = net_dev->priv;
1514 long ioaddr = net_dev->base_addr;
1515 unsigned long flags;
1516 int i;
1517
1518 if(netif_msg_tx_err(sis_priv))
1519 printk(KERN_INFO "%s: Transmit timeout, status %8.8x %8.8x \n",
1520 net_dev->name, inl(ioaddr + cr), inl(ioaddr + isr));
1521
1522
1523 outl(0x0000, ioaddr + imr);
1524
1525
1526 spin_lock_irqsave(&sis_priv->lock, flags);
1527
1528
1529 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1530 for (i = 0; i < NUM_TX_DESC; i++) {
1531 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1532
1533 if (skb) {
1534 pci_unmap_single(sis_priv->pci_dev,
1535 sis_priv->tx_ring[i].bufptr, skb->len,
1536 PCI_DMA_TODEVICE);
1537 dev_kfree_skb_irq(skb);
1538 sis_priv->tx_skbuff[i] = NULL;
1539 sis_priv->tx_ring[i].cmdsts = 0;
1540 sis_priv->tx_ring[i].bufptr = 0;
1541 net_dev->stats.tx_dropped++;
1542 }
1543 }
1544 sis_priv->tx_full = 0;
1545 netif_wake_queue(net_dev);
1546
1547 spin_unlock_irqrestore(&sis_priv->lock, flags);
1548
1549 net_dev->trans_start = jiffies;
1550
1551
1552 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1553
1554
1555 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1556 return;
1557}
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569static int
1570sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
1571{
1572 struct sis900_private *sis_priv = net_dev->priv;
1573 long ioaddr = net_dev->base_addr;
1574 unsigned int entry;
1575 unsigned long flags;
1576 unsigned int index_cur_tx, index_dirty_tx;
1577 unsigned int count_dirty_tx;
1578
1579
1580 if(!sis_priv->autong_complete){
1581 netif_stop_queue(net_dev);
1582 return 1;
1583 }
1584
1585 spin_lock_irqsave(&sis_priv->lock, flags);
1586
1587
1588 entry = sis_priv->cur_tx % NUM_TX_DESC;
1589 sis_priv->tx_skbuff[entry] = skb;
1590
1591
1592 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1593 skb->data, skb->len, PCI_DMA_TODEVICE);
1594 sis_priv->tx_ring[entry].cmdsts = (OWN | skb->len);
1595 outl(TxENA | inl(ioaddr + cr), ioaddr + cr);
1596
1597 sis_priv->cur_tx ++;
1598 index_cur_tx = sis_priv->cur_tx;
1599 index_dirty_tx = sis_priv->dirty_tx;
1600
1601 for (count_dirty_tx = 0; index_cur_tx != index_dirty_tx; index_dirty_tx++)
1602 count_dirty_tx ++;
1603
1604 if (index_cur_tx == index_dirty_tx) {
1605
1606 sis_priv->tx_full = 1;
1607 netif_stop_queue(net_dev);
1608 } else if (count_dirty_tx < NUM_TX_DESC) {
1609
1610 netif_start_queue(net_dev);
1611 } else {
1612
1613 sis_priv->tx_full = 1;
1614 netif_stop_queue(net_dev);
1615 }
1616
1617 spin_unlock_irqrestore(&sis_priv->lock, flags);
1618
1619 net_dev->trans_start = jiffies;
1620
1621 if (netif_msg_tx_queued(sis_priv))
1622 printk(KERN_DEBUG "%s: Queued Tx packet at %p size %d "
1623 "to slot %d.\n",
1624 net_dev->name, skb->data, (int)skb->len, entry);
1625
1626 return 0;
1627}
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
1639{
1640 struct net_device *net_dev = dev_instance;
1641 struct sis900_private *sis_priv = net_dev->priv;
1642 int boguscnt = max_interrupt_work;
1643 long ioaddr = net_dev->base_addr;
1644 u32 status;
1645 unsigned int handled = 0;
1646
1647 spin_lock (&sis_priv->lock);
1648
1649 do {
1650 status = inl(ioaddr + isr);
1651
1652 if ((status & (HIBERR|TxURN|TxERR|TxIDLE|RxORN|RxERR|RxOK)) == 0)
1653
1654 break;
1655 handled = 1;
1656
1657
1658 if (status & (RxORN | RxERR | RxOK))
1659
1660 sis900_rx(net_dev);
1661
1662 if (status & (TxURN | TxERR | TxIDLE))
1663
1664 sis900_finish_xmit(net_dev);
1665
1666
1667 if (status & HIBERR) {
1668 if(netif_msg_intr(sis_priv))
1669 printk(KERN_INFO "%s: Abnormal interrupt, "
1670 "status %#8.8x.\n", net_dev->name, status);
1671 break;
1672 }
1673 if (--boguscnt < 0) {
1674 if(netif_msg_intr(sis_priv))
1675 printk(KERN_INFO "%s: Too much work at interrupt, "
1676 "interrupt status = %#8.8x.\n",
1677 net_dev->name, status);
1678 break;
1679 }
1680 } while (1);
1681
1682 if(netif_msg_intr(sis_priv))
1683 printk(KERN_DEBUG "%s: exiting interrupt, "
1684 "interrupt status = 0x%#8.8x.\n",
1685 net_dev->name, inl(ioaddr + isr));
1686
1687 spin_unlock (&sis_priv->lock);
1688 return IRQ_RETVAL(handled);
1689}
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701static int sis900_rx(struct net_device *net_dev)
1702{
1703 struct sis900_private *sis_priv = net_dev->priv;
1704 long ioaddr = net_dev->base_addr;
1705 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1706 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
1707 int rx_work_limit;
1708
1709 if (netif_msg_rx_status(sis_priv))
1710 printk(KERN_DEBUG "sis900_rx, cur_rx:%4.4d, dirty_rx:%4.4d "
1711 "status:0x%8.8x\n",
1712 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
1713 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1714
1715 while (rx_status & OWN) {
1716 unsigned int rx_size;
1717 unsigned int data_size;
1718
1719 if (--rx_work_limit < 0)
1720 break;
1721
1722 data_size = rx_status & DSIZE;
1723 rx_size = data_size - CRC_SIZE;
1724
1725#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1726
1727 if ((rx_status & TOOLONG) && data_size <= MAX_FRAME_SIZE)
1728 rx_status &= (~ ((unsigned int)TOOLONG));
1729#endif
1730
1731 if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) {
1732
1733 if (netif_msg_rx_err(sis_priv))
1734 printk(KERN_DEBUG "%s: Corrupted packet "
1735 "received, buffer status = 0x%8.8x/%d.\n",
1736 net_dev->name, rx_status, data_size);
1737 net_dev->stats.rx_errors++;
1738 if (rx_status & OVERRUN)
1739 net_dev->stats.rx_over_errors++;
1740 if (rx_status & (TOOLONG|RUNT))
1741 net_dev->stats.rx_length_errors++;
1742 if (rx_status & (RXISERR | FAERR))
1743 net_dev->stats.rx_frame_errors++;
1744 if (rx_status & CRCERR)
1745 net_dev->stats.rx_crc_errors++;
1746
1747 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1748 } else {
1749 struct sk_buff * skb;
1750 struct sk_buff * rx_skb;
1751
1752 pci_unmap_single(sis_priv->pci_dev,
1753 sis_priv->rx_ring[entry].bufptr, RX_BUF_SIZE,
1754 PCI_DMA_FROMDEVICE);
1755
1756
1757
1758 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1759
1760
1761
1762
1763
1764
1765 skb = sis_priv->rx_skbuff[entry];
1766 net_dev->stats.rx_dropped++;
1767 goto refill_rx_ring;
1768 }
1769
1770
1771
1772
1773 if (sis_priv->rx_skbuff[entry] == NULL) {
1774 if (netif_msg_rx_err(sis_priv))
1775 printk(KERN_WARNING "%s: NULL pointer "
1776 "encountered in Rx ring\n"
1777 "cur_rx:%4.4d, dirty_rx:%4.4d\n",
1778 net_dev->name, sis_priv->cur_rx,
1779 sis_priv->dirty_rx);
1780 break;
1781 }
1782
1783
1784 rx_skb = sis_priv->rx_skbuff[entry];
1785 skb_put(rx_skb, rx_size);
1786 rx_skb->protocol = eth_type_trans(rx_skb, net_dev);
1787 netif_rx(rx_skb);
1788
1789
1790 if ((rx_status & BCAST) == MCAST)
1791 net_dev->stats.multicast++;
1792 net_dev->last_rx = jiffies;
1793 net_dev->stats.rx_bytes += rx_size;
1794 net_dev->stats.rx_packets++;
1795 sis_priv->dirty_rx++;
1796refill_rx_ring:
1797 sis_priv->rx_skbuff[entry] = skb;
1798 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1799 sis_priv->rx_ring[entry].bufptr =
1800 pci_map_single(sis_priv->pci_dev, skb->data,
1801 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1802 }
1803 sis_priv->cur_rx++;
1804 entry = sis_priv->cur_rx % NUM_RX_DESC;
1805 rx_status = sis_priv->rx_ring[entry].cmdsts;
1806 }
1807
1808
1809
1810 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1811 struct sk_buff *skb;
1812
1813 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1814
1815 if (sis_priv->rx_skbuff[entry] == NULL) {
1816 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1817
1818
1819
1820
1821 if (netif_msg_rx_err(sis_priv))
1822 printk(KERN_INFO "%s: Memory squeeze, "
1823 "deferring packet.\n",
1824 net_dev->name);
1825 net_dev->stats.rx_dropped++;
1826 break;
1827 }
1828 sis_priv->rx_skbuff[entry] = skb;
1829 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1830 sis_priv->rx_ring[entry].bufptr =
1831 pci_map_single(sis_priv->pci_dev, skb->data,
1832 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1833 }
1834 }
1835
1836 outl(RxENA | inl(ioaddr + cr), ioaddr + cr );
1837
1838 return 0;
1839}
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851static void sis900_finish_xmit (struct net_device *net_dev)
1852{
1853 struct sis900_private *sis_priv = net_dev->priv;
1854
1855 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1856 struct sk_buff *skb;
1857 unsigned int entry;
1858 u32 tx_status;
1859
1860 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1861 tx_status = sis_priv->tx_ring[entry].cmdsts;
1862
1863 if (tx_status & OWN) {
1864
1865
1866
1867 break;
1868 }
1869
1870 if (tx_status & (ABORT | UNDERRUN | OWCOLL)) {
1871
1872 if (netif_msg_tx_err(sis_priv))
1873 printk(KERN_DEBUG "%s: Transmit "
1874 "error, Tx status %8.8x.\n",
1875 net_dev->name, tx_status);
1876 net_dev->stats.tx_errors++;
1877 if (tx_status & UNDERRUN)
1878 net_dev->stats.tx_fifo_errors++;
1879 if (tx_status & ABORT)
1880 net_dev->stats.tx_aborted_errors++;
1881 if (tx_status & NOCARRIER)
1882 net_dev->stats.tx_carrier_errors++;
1883 if (tx_status & OWCOLL)
1884 net_dev->stats.tx_window_errors++;
1885 } else {
1886
1887 net_dev->stats.collisions += (tx_status & COLCNT) >> 16;
1888 net_dev->stats.tx_bytes += tx_status & DSIZE;
1889 net_dev->stats.tx_packets++;
1890 }
1891
1892 skb = sis_priv->tx_skbuff[entry];
1893 pci_unmap_single(sis_priv->pci_dev,
1894 sis_priv->tx_ring[entry].bufptr, skb->len,
1895 PCI_DMA_TODEVICE);
1896 dev_kfree_skb_irq(skb);
1897 sis_priv->tx_skbuff[entry] = NULL;
1898 sis_priv->tx_ring[entry].bufptr = 0;
1899 sis_priv->tx_ring[entry].cmdsts = 0;
1900 }
1901
1902 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1903 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1904
1905
1906 sis_priv->tx_full = 0;
1907 netif_wake_queue (net_dev);
1908 }
1909}
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919static int sis900_close(struct net_device *net_dev)
1920{
1921 long ioaddr = net_dev->base_addr;
1922 struct sis900_private *sis_priv = net_dev->priv;
1923 struct sk_buff *skb;
1924 int i;
1925
1926 netif_stop_queue(net_dev);
1927
1928
1929 outl(0x0000, ioaddr + imr);
1930 outl(0x0000, ioaddr + ier);
1931
1932
1933 outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
1934
1935 del_timer(&sis_priv->timer);
1936
1937 free_irq(net_dev->irq, net_dev);
1938
1939
1940 for (i = 0; i < NUM_RX_DESC; i++) {
1941 skb = sis_priv->rx_skbuff[i];
1942 if (skb) {
1943 pci_unmap_single(sis_priv->pci_dev,
1944 sis_priv->rx_ring[i].bufptr,
1945 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1946 dev_kfree_skb(skb);
1947 sis_priv->rx_skbuff[i] = NULL;
1948 }
1949 }
1950 for (i = 0; i < NUM_TX_DESC; i++) {
1951 skb = sis_priv->tx_skbuff[i];
1952 if (skb) {
1953 pci_unmap_single(sis_priv->pci_dev,
1954 sis_priv->tx_ring[i].bufptr, skb->len,
1955 PCI_DMA_TODEVICE);
1956 dev_kfree_skb(skb);
1957 sis_priv->tx_skbuff[i] = NULL;
1958 }
1959 }
1960
1961
1962
1963 return 0;
1964}
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974static void sis900_get_drvinfo(struct net_device *net_dev,
1975 struct ethtool_drvinfo *info)
1976{
1977 struct sis900_private *sis_priv = net_dev->priv;
1978
1979 strcpy (info->driver, SIS900_MODULE_NAME);
1980 strcpy (info->version, SIS900_DRV_VERSION);
1981 strcpy (info->bus_info, pci_name(sis_priv->pci_dev));
1982}
1983
1984static u32 sis900_get_msglevel(struct net_device *net_dev)
1985{
1986 struct sis900_private *sis_priv = net_dev->priv;
1987 return sis_priv->msg_enable;
1988}
1989
1990static void sis900_set_msglevel(struct net_device *net_dev, u32 value)
1991{
1992 struct sis900_private *sis_priv = net_dev->priv;
1993 sis_priv->msg_enable = value;
1994}
1995
1996static u32 sis900_get_link(struct net_device *net_dev)
1997{
1998 struct sis900_private *sis_priv = net_dev->priv;
1999 return mii_link_ok(&sis_priv->mii_info);
2000}
2001
2002static int sis900_get_settings(struct net_device *net_dev,
2003 struct ethtool_cmd *cmd)
2004{
2005 struct sis900_private *sis_priv = net_dev->priv;
2006 spin_lock_irq(&sis_priv->lock);
2007 mii_ethtool_gset(&sis_priv->mii_info, cmd);
2008 spin_unlock_irq(&sis_priv->lock);
2009 return 0;
2010}
2011
2012static int sis900_set_settings(struct net_device *net_dev,
2013 struct ethtool_cmd *cmd)
2014{
2015 struct sis900_private *sis_priv = net_dev->priv;
2016 int rt;
2017 spin_lock_irq(&sis_priv->lock);
2018 rt = mii_ethtool_sset(&sis_priv->mii_info, cmd);
2019 spin_unlock_irq(&sis_priv->lock);
2020 return rt;
2021}
2022
2023static int sis900_nway_reset(struct net_device *net_dev)
2024{
2025 struct sis900_private *sis_priv = net_dev->priv;
2026 return mii_nway_restart(&sis_priv->mii_info);
2027}
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040static int sis900_set_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2041{
2042 struct sis900_private *sis_priv = net_dev->priv;
2043 long pmctrl_addr = net_dev->base_addr + pmctrl;
2044 u32 cfgpmcsr = 0, pmctrl_bits = 0;
2045
2046 if (wol->wolopts == 0) {
2047 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2048 cfgpmcsr &= ~PME_EN;
2049 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2050 outl(pmctrl_bits, pmctrl_addr);
2051 if (netif_msg_wol(sis_priv))
2052 printk(KERN_DEBUG "%s: Wake on LAN disabled\n", net_dev->name);
2053 return 0;
2054 }
2055
2056 if (wol->wolopts & (WAKE_MAGICSECURE | WAKE_UCAST | WAKE_MCAST
2057 | WAKE_BCAST | WAKE_ARP))
2058 return -EINVAL;
2059
2060 if (wol->wolopts & WAKE_MAGIC)
2061 pmctrl_bits |= MAGICPKT;
2062 if (wol->wolopts & WAKE_PHY)
2063 pmctrl_bits |= LINKON;
2064
2065 outl(pmctrl_bits, pmctrl_addr);
2066
2067 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2068 cfgpmcsr |= PME_EN;
2069 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2070 if (netif_msg_wol(sis_priv))
2071 printk(KERN_DEBUG "%s: Wake on LAN enabled\n", net_dev->name);
2072
2073 return 0;
2074}
2075
2076static void sis900_get_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2077{
2078 long pmctrl_addr = net_dev->base_addr + pmctrl;
2079 u32 pmctrl_bits;
2080
2081 pmctrl_bits = inl(pmctrl_addr);
2082 if (pmctrl_bits & MAGICPKT)
2083 wol->wolopts |= WAKE_MAGIC;
2084 if (pmctrl_bits & LINKON)
2085 wol->wolopts |= WAKE_PHY;
2086
2087 wol->supported = (WAKE_PHY | WAKE_MAGIC);
2088}
2089
2090static const struct ethtool_ops sis900_ethtool_ops = {
2091 .get_drvinfo = sis900_get_drvinfo,
2092 .get_msglevel = sis900_get_msglevel,
2093 .set_msglevel = sis900_set_msglevel,
2094 .get_link = sis900_get_link,
2095 .get_settings = sis900_get_settings,
2096 .set_settings = sis900_set_settings,
2097 .nway_reset = sis900_nway_reset,
2098 .get_wol = sis900_get_wol,
2099 .set_wol = sis900_set_wol
2100};
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2112{
2113 struct sis900_private *sis_priv = net_dev->priv;
2114 struct mii_ioctl_data *data = if_mii(rq);
2115
2116 switch(cmd) {
2117 case SIOCGMIIPHY:
2118 data->phy_id = sis_priv->mii->phy_addr;
2119
2120
2121 case SIOCGMIIREG:
2122 data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2123 return 0;
2124
2125 case SIOCSMIIREG:
2126 if (!capable(CAP_NET_ADMIN))
2127 return -EPERM;
2128 mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2129 return 0;
2130 default:
2131 return -EOPNOTSUPP;
2132 }
2133}
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145static int sis900_set_config(struct net_device *dev, struct ifmap *map)
2146{
2147 struct sis900_private *sis_priv = dev->priv;
2148 struct mii_phy *mii_phy = sis_priv->mii;
2149
2150 u16 status;
2151
2152 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
2153
2154
2155
2156
2157
2158
2159 switch(map->port){
2160 case IF_PORT_UNKNOWN:
2161 dev->if_port = map->port;
2162
2163
2164
2165
2166
2167 netif_carrier_off(dev);
2168
2169
2170 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2171
2172
2173
2174
2175
2176 mdio_write(dev, mii_phy->phy_addr,
2177 MII_CONTROL, status | MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
2178
2179 break;
2180
2181 case IF_PORT_10BASET:
2182 dev->if_port = map->port;
2183
2184
2185
2186
2187
2188
2189 netif_carrier_off(dev);
2190
2191
2192
2193 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2194
2195
2196 mdio_write(dev, mii_phy->phy_addr,
2197 MII_CONTROL, status & ~(MII_CNTL_SPEED |
2198 MII_CNTL_AUTO));
2199 break;
2200
2201 case IF_PORT_100BASET:
2202 case IF_PORT_100BASETX:
2203 dev->if_port = map->port;
2204
2205
2206
2207
2208
2209
2210 netif_carrier_off(dev);
2211
2212
2213
2214 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2215 mdio_write(dev, mii_phy->phy_addr,
2216 MII_CONTROL, (status & ~MII_CNTL_SPEED) |
2217 MII_CNTL_SPEED);
2218
2219 break;
2220
2221 case IF_PORT_10BASE2:
2222 case IF_PORT_AUI:
2223 case IF_PORT_100BASEFX:
2224
2225 return -EOPNOTSUPP;
2226 break;
2227
2228 default:
2229 return -EINVAL;
2230 }
2231 }
2232 return 0;
2233}
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246static inline u16 sis900_mcast_bitnr(u8 *addr, u8 revision)
2247{
2248
2249 u32 crc = ether_crc(6, addr);
2250
2251
2252 if ((revision >= SIS635A_900_REV) || (revision == SIS900B_900_REV))
2253 return ((int)(crc >> 24));
2254 else
2255 return ((int)(crc >> 25));
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267static void set_rx_mode(struct net_device *net_dev)
2268{
2269 long ioaddr = net_dev->base_addr;
2270 struct sis900_private * sis_priv = net_dev->priv;
2271 u16 mc_filter[16] = {0};
2272 int i, table_entries;
2273 u32 rx_mode;
2274
2275
2276 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2277 (sis_priv->chipset_rev == SIS900B_900_REV))
2278 table_entries = 16;
2279 else
2280 table_entries = 8;
2281
2282 if (net_dev->flags & IFF_PROMISC) {
2283
2284 rx_mode = RFPromiscuous;
2285 for (i = 0; i < table_entries; i++)
2286 mc_filter[i] = 0xffff;
2287 } else if ((net_dev->mc_count > multicast_filter_limit) ||
2288 (net_dev->flags & IFF_ALLMULTI)) {
2289
2290 rx_mode = RFAAB | RFAAM;
2291 for (i = 0; i < table_entries; i++)
2292 mc_filter[i] = 0xffff;
2293 } else {
2294
2295
2296
2297 struct dev_mc_list *mclist;
2298 rx_mode = RFAAB;
2299 for (i = 0, mclist = net_dev->mc_list;
2300 mclist && i < net_dev->mc_count;
2301 i++, mclist = mclist->next) {
2302 unsigned int bit_nr =
2303 sis900_mcast_bitnr(mclist->dmi_addr, sis_priv->chipset_rev);
2304 mc_filter[bit_nr >> 4] |= (1 << (bit_nr & 0xf));
2305 }
2306 }
2307
2308
2309 for (i = 0; i < table_entries; i++) {
2310
2311 outl((u32)(0x00000004+i) << RFADDR_shift, ioaddr + rfcr);
2312 outl(mc_filter[i], ioaddr + rfdr);
2313 }
2314
2315 outl(RFEN | rx_mode, ioaddr + rfcr);
2316
2317
2318
2319 if (net_dev->flags & IFF_LOOPBACK) {
2320 u32 cr_saved;
2321
2322 cr_saved = inl(ioaddr + cr);
2323 outl(cr_saved | TxDIS | RxDIS, ioaddr + cr);
2324
2325 outl(inl(ioaddr + txcfg) | TxMLB, ioaddr + txcfg);
2326 outl(inl(ioaddr + rxcfg) | RxATX, ioaddr + rxcfg);
2327
2328 outl(cr_saved, ioaddr + cr);
2329 }
2330
2331 return;
2332}
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343static void sis900_reset(struct net_device *net_dev)
2344{
2345 struct sis900_private * sis_priv = net_dev->priv;
2346 long ioaddr = net_dev->base_addr;
2347 int i = 0;
2348 u32 status = TxRCMP | RxRCMP;
2349
2350 outl(0, ioaddr + ier);
2351 outl(0, ioaddr + imr);
2352 outl(0, ioaddr + rfcr);
2353
2354 outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr);
2355
2356
2357 while (status && (i++ < 1000)) {
2358 status ^= (inl(isr + ioaddr) & status);
2359 }
2360
2361 if( (sis_priv->chipset_rev >= SIS635A_900_REV) ||
2362 (sis_priv->chipset_rev == SIS900B_900_REV) )
2363 outl(PESEL | RND_CNT, ioaddr + cfg);
2364 else
2365 outl(PESEL, ioaddr + cfg);
2366}
2367
2368
2369
2370
2371
2372
2373
2374
2375static void __devexit sis900_remove(struct pci_dev *pci_dev)
2376{
2377 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2378 struct sis900_private * sis_priv = net_dev->priv;
2379 struct mii_phy *phy = NULL;
2380
2381 while (sis_priv->first_mii) {
2382 phy = sis_priv->first_mii;
2383 sis_priv->first_mii = phy->next;
2384 kfree(phy);
2385 }
2386
2387 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2388 sis_priv->rx_ring_dma);
2389 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2390 sis_priv->tx_ring_dma);
2391 unregister_netdev(net_dev);
2392 free_netdev(net_dev);
2393 pci_release_regions(pci_dev);
2394 pci_set_drvdata(pci_dev, NULL);
2395}
2396
2397#ifdef CONFIG_PM
2398
2399static int sis900_suspend(struct pci_dev *pci_dev, pm_message_t state)
2400{
2401 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2402 long ioaddr = net_dev->base_addr;
2403
2404 if(!netif_running(net_dev))
2405 return 0;
2406
2407 netif_stop_queue(net_dev);
2408 netif_device_detach(net_dev);
2409
2410
2411 outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
2412
2413 pci_set_power_state(pci_dev, PCI_D3hot);
2414 pci_save_state(pci_dev);
2415
2416 return 0;
2417}
2418
2419static int sis900_resume(struct pci_dev *pci_dev)
2420{
2421 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2422 struct sis900_private *sis_priv = net_dev->priv;
2423 long ioaddr = net_dev->base_addr;
2424
2425 if(!netif_running(net_dev))
2426 return 0;
2427 pci_restore_state(pci_dev);
2428 pci_set_power_state(pci_dev, PCI_D0);
2429
2430 sis900_init_rxfilter(net_dev);
2431
2432 sis900_init_tx_ring(net_dev);
2433 sis900_init_rx_ring(net_dev);
2434
2435 set_rx_mode(net_dev);
2436
2437 netif_device_attach(net_dev);
2438 netif_start_queue(net_dev);
2439
2440
2441 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
2442
2443
2444 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
2445 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
2446 outl(IE, ioaddr + ier);
2447
2448 sis900_check_mode(net_dev, sis_priv->mii);
2449
2450 return 0;
2451}
2452#endif
2453
2454static struct pci_driver sis900_pci_driver = {
2455 .name = SIS900_MODULE_NAME,
2456 .id_table = sis900_pci_tbl,
2457 .probe = sis900_probe,
2458 .remove = __devexit_p(sis900_remove),
2459#ifdef CONFIG_PM
2460 .suspend = sis900_suspend,
2461 .resume = sis900_resume,
2462#endif
2463};
2464
2465static int __init sis900_init_module(void)
2466{
2467
2468#ifdef MODULE
2469 printk(version);
2470#endif
2471
2472 return pci_register_driver(&sis900_pci_driver);
2473}
2474
2475static void __exit sis900_cleanup_module(void)
2476{
2477 pci_unregister_driver(&sis900_pci_driver);
2478}
2479
2480module_init(sis900_init_module);
2481module_exit(sis900_cleanup_module);
2482