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18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
25#include <linux/dmi.h>
26#include "pci.h"
27
28int isa_dma_bridge_buggy;
29EXPORT_SYMBOL(isa_dma_bridge_buggy);
30int pci_pci_problems;
31EXPORT_SYMBOL(pci_pci_problems);
32int pcie_mch_quirk;
33EXPORT_SYMBOL(pcie_mch_quirk);
34
35#ifdef CONFIG_PCI_QUIRKS
36
37
38
39
40static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
41{
42 dev->broken_parity_status = 1;
43}
44DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
45DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
46
47
48
49static void quirk_passive_release(struct pci_dev *dev)
50{
51 struct pci_dev *d = NULL;
52 unsigned char dlc;
53
54
55
56 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
57 pci_read_config_byte(d, 0x82, &dlc);
58 if (!(dlc & 1<<1)) {
59 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
60 dlc |= 1<<1;
61 pci_write_config_byte(d, 0x82, dlc);
62 }
63 }
64}
65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
66DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
67
68
69
70
71
72
73
74
75static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
76{
77 if (!isa_dma_bridge_buggy) {
78 isa_dma_bridge_buggy=1;
79 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
80 }
81}
82
83
84
85
86DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
87DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
88DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
89DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
90DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
91DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
92DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
93
94
95
96
97static void __devinit quirk_nopcipci(struct pci_dev *dev)
98{
99 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
100 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
101 pci_pci_problems |= PCIPCI_FAIL;
102 }
103}
104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
106
107static void __devinit quirk_nopciamd(struct pci_dev *dev)
108{
109 u8 rev;
110 pci_read_config_byte(dev, 0x08, &rev);
111 if (rev == 0x13) {
112
113 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
114 pci_pci_problems |= PCIAGP_FAIL;
115 }
116}
117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
118
119
120
121
122static void __devinit quirk_triton(struct pci_dev *dev)
123{
124 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
125 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
126 pci_pci_problems |= PCIPCI_TRITON;
127 }
128}
129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
133
134
135
136
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139
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141
142
143
144static void quirk_vialatency(struct pci_dev *dev)
145{
146 struct pci_dev *p;
147 u8 busarb;
148
149
150
151 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
152 if (p!=NULL) {
153
154
155 if (p->revision < 0x40 || p->revision > 0x42)
156 goto exit;
157 } else {
158 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
159 if (p==NULL)
160 goto exit;
161
162 if (p->revision < 0x10 || p->revision > 0x12)
163 goto exit;
164 }
165
166
167
168
169
170
171
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175
176
177
178
179 pci_read_config_byte(dev, 0x76, &busarb);
180
181
182 busarb &= ~(1<<5);
183 busarb |= (1<<4);
184 pci_write_config_byte(dev, 0x76, busarb);
185 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
186exit:
187 pci_dev_put(p);
188}
189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
192
193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
194DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
195DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
196
197
198
199
200static void __devinit quirk_viaetbf(struct pci_dev *dev)
201{
202 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
203 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
204 pci_pci_problems |= PCIPCI_VIAETBF;
205 }
206}
207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
208
209static void __devinit quirk_vsfx(struct pci_dev *dev)
210{
211 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
212 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
213 pci_pci_problems |= PCIPCI_VSFX;
214 }
215}
216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
217
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222
223
224static void __init quirk_alimagik(struct pci_dev *dev)
225{
226 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
227 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
228 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
229 }
230}
231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
233
234
235
236
237
238static void __devinit quirk_natoma(struct pci_dev *dev)
239{
240 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
242 pci_pci_problems |= PCIPCI_NATOMA;
243 }
244}
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
251
252
253
254
255
256static void __devinit quirk_citrine(struct pci_dev *dev)
257{
258 dev->cfg_size = 0xA0;
259}
260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
261
262
263
264
265
266static void __devinit quirk_s3_64M(struct pci_dev *dev)
267{
268 struct resource *r = &dev->resource[0];
269
270 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
271 r->start = 0;
272 r->end = 0x3ffffff;
273 }
274}
275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
277
278static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
279 unsigned size, int nr, const char *name)
280{
281 region &= ~(size-1);
282 if (region) {
283 struct pci_bus_region bus_region;
284 struct resource *res = dev->resource + nr;
285
286 res->name = pci_name(dev);
287 res->start = region;
288 res->end = region + size - 1;
289 res->flags = IORESOURCE_IO;
290
291
292 bus_region.start = res->start;
293 bus_region.end = res->end;
294 pcibios_bus_to_resource(dev, res, &bus_region);
295
296 pci_claim_resource(dev, nr);
297 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
298 }
299}
300
301
302
303
304
305static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
306{
307 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
308
309 request_region(0x3b0, 0x0C, "RadeonIGP");
310 request_region(0x3d3, 0x01, "RadeonIGP");
311}
312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
313
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323
324
325static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
326{
327 u16 region;
328
329 pci_read_config_word(dev, 0xE0, ®ion);
330 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
331 pci_read_config_word(dev, 0xE2, ®ion);
332 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
333}
334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
335
336static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
337{
338 u32 devres;
339 u32 mask, size, base;
340
341 pci_read_config_dword(dev, port, &devres);
342 if ((devres & enable) != enable)
343 return;
344 mask = (devres >> 16) & 15;
345 base = devres & 0xffff;
346 size = 16;
347 for (;;) {
348 unsigned bit = size >> 1;
349 if ((bit & mask) == bit)
350 break;
351 size = bit;
352 }
353
354
355
356
357
358 base &= -size;
359 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
360}
361
362static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
363{
364 u32 devres;
365 u32 mask, size, base;
366
367 pci_read_config_dword(dev, port, &devres);
368 if ((devres & enable) != enable)
369 return;
370 base = devres & 0xffff0000;
371 mask = (devres & 0x3f) << 16;
372 size = 128 << 16;
373 for (;;) {
374 unsigned bit = size >> 1;
375 if ((bit & mask) == bit)
376 break;
377 size = bit;
378 }
379
380
381
382
383 base &= -size;
384 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
385}
386
387
388
389
390
391
392
393static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
394{
395 u32 region, res_a;
396
397 pci_read_config_dword(dev, 0x40, ®ion);
398 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
399 pci_read_config_dword(dev, 0x90, ®ion);
400 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
401
402
403 pci_read_config_dword(dev, 0x5c, &res_a);
404
405 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
406 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
407
408
409
410
411 if (res_a & (1 << 29)) {
412 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
413 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
414 }
415
416 if (res_a & (1 << 30)) {
417 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
418 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
419 }
420 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
421 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
422}
423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
425
426
427
428
429
430
431static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, ®ion);
436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
437
438 pci_read_config_dword(dev, 0x58, ®ion);
439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
440}
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
451
452static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
453{
454 u32 region;
455
456 pci_read_config_dword(dev, 0x40, ®ion);
457 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
458
459 pci_read_config_dword(dev, 0x48, ®ion);
460 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
461}
462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
475DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
476
477
478
479
480
481static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
482{
483 u32 region;
484
485 if (dev->revision & 0x10) {
486 pci_read_config_dword(dev, 0x48, ®ion);
487 region &= PCI_BASE_ADDRESS_IO_MASK;
488 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
489 }
490}
491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
492
493
494
495
496
497
498
499static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
500{
501 u16 hm;
502 u32 smb;
503
504 quirk_vt82c586_acpi(dev);
505
506 pci_read_config_word(dev, 0x70, &hm);
507 hm &= PCI_BASE_ADDRESS_IO_MASK;
508 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
509
510 pci_read_config_dword(dev, 0x90, &smb);
511 smb &= PCI_BASE_ADDRESS_IO_MASK;
512 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
513}
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
515
516
517
518
519
520
521static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
522{
523 u16 pm, smb;
524
525 pci_read_config_word(dev, 0x88, &pm);
526 pm &= PCI_BASE_ADDRESS_IO_MASK;
527 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
528
529 pci_read_config_word(dev, 0xd0, &smb);
530 smb &= PCI_BASE_ADDRESS_IO_MASK;
531 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
534
535
536#ifdef CONFIG_X86_IO_APIC
537
538#include <asm/io_apic.h>
539
540
541
542
543
544
545
546
547static void quirk_via_ioapic(struct pci_dev *dev)
548{
549 u8 tmp;
550
551 if (nr_ioapics < 1)
552 tmp = 0;
553 else
554 tmp = 0x1f;
555
556 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
557 tmp == 0 ? "Disa" : "Ena");
558
559
560 pci_write_config_byte (dev, 0x58, tmp);
561}
562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
563DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
564
565
566
567
568
569
570
571static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
572{
573 u8 misc_control2;
574#define BYPASS_APIC_DEASSERT 8
575
576 pci_read_config_byte(dev, 0x5B, &misc_control2);
577 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
578 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
579 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
580 }
581}
582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
583DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
584
585
586
587
588
589
590
591
592
593
594static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
595{
596 if (dev->revision >= 0x02) {
597 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
598 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
599 }
600}
601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
602
603static void __init quirk_ioapic_rmw(struct pci_dev *dev)
604{
605 if (dev->devfn == 0 && dev->bus->number == 0)
606 sis_apic_bug = 1;
607}
608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
609
610#define AMD8131_revA0 0x01
611#define AMD8131_revB0 0x11
612#define AMD8131_MISC 0x40
613#define AMD8131_NIOAMODE_BIT 0
614static void quirk_amd_8131_ioapic(struct pci_dev *dev)
615{
616 unsigned char tmp;
617
618 if (nr_ioapics == 0)
619 return;
620
621 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
622 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
623 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
624 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
625 pci_write_config_byte( dev, AMD8131_MISC, tmp);
626 }
627}
628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
629DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
630#endif
631
632
633
634
635
636static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
637{
638 if (dev->subordinate && dev->revision <= 0x12) {
639 dev_info(&dev->dev, "AMD8131 rev %x detected; "
640 "disabling PCI-X MMRBC\n", dev->revision);
641 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
642 }
643}
644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
645
646
647
648
649
650
651
652
653
654static void __devinit quirk_via_acpi(struct pci_dev *d)
655{
656
657
658
659 u8 irq;
660 pci_read_config_byte(d, 0x42, &irq);
661 irq &= 0xf;
662 if (irq && (irq != 2))
663 d->irq = irq;
664}
665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
667
668
669
670
671
672
673static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
674
675static void quirk_via_bridge(struct pci_dev *dev)
676{
677
678 switch (dev->device) {
679 case PCI_DEVICE_ID_VIA_82C686:
680
681
682
683 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
684 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
685 break;
686 case PCI_DEVICE_ID_VIA_8237:
687 case PCI_DEVICE_ID_VIA_8237A:
688 via_vlink_dev_lo = 15;
689 break;
690 case PCI_DEVICE_ID_VIA_8235:
691 via_vlink_dev_lo = 16;
692 break;
693 case PCI_DEVICE_ID_VIA_8231:
694 case PCI_DEVICE_ID_VIA_8233_0:
695 case PCI_DEVICE_ID_VIA_8233A:
696 case PCI_DEVICE_ID_VIA_8233C_0:
697 via_vlink_dev_lo = 17;
698 break;
699 }
700}
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723static void quirk_via_vlink(struct pci_dev *dev)
724{
725 u8 irq, new_irq;
726
727
728 if (via_vlink_dev_lo == -1)
729 return;
730
731 new_irq = dev->irq;
732
733
734 if (!new_irq || new_irq > 15)
735 return;
736
737
738 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
739 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
740 return;
741
742
743
744
745 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
746 if (new_irq != irq) {
747 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
748 irq, new_irq);
749 udelay(15);
750 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
751 }
752}
753DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
754
755
756
757
758
759
760
761static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
762{
763 pci_write_config_byte(dev, 0xfc, 0);
764 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
765}
766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
767
768
769
770
771
772
773
774static void quirk_cardbus_legacy(struct pci_dev *dev)
775{
776 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
777 return;
778 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
779}
780DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
781DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
782
783
784
785
786
787
788
789
790static void quirk_amd_ordering(struct pci_dev *dev)
791{
792 u32 pcic;
793 pci_read_config_dword(dev, 0x4C, &pcic);
794 if ((pcic&6)!=6) {
795 pcic |= 6;
796 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
797 pci_write_config_dword(dev, 0x4C, pcic);
798 pci_read_config_dword(dev, 0x84, &pcic);
799 pcic |= (1<<23);
800 pci_write_config_dword(dev, 0x84, pcic);
801 }
802}
803DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
804DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
805
806
807
808
809
810
811
812
813static void __devinit quirk_dunord ( struct pci_dev * dev )
814{
815 struct resource *r = &dev->resource [1];
816 r->start = 0;
817 r->end = 0xffffff;
818}
819DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
820
821
822
823
824
825
826
827static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
828{
829 dev->transparent = 1;
830}
831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
833
834
835
836
837
838
839
840static void quirk_mediagx_master(struct pci_dev *dev)
841{
842 u8 reg;
843 pci_read_config_byte(dev, 0x41, ®);
844 if (reg & 2) {
845 reg &= ~2;
846 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
847 pci_write_config_byte(dev, 0x41, reg);
848 }
849}
850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
851DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
852
853
854
855
856
857
858static void quirk_disable_pxb(struct pci_dev *pdev)
859{
860 u16 config;
861
862 if (pdev->revision != 0x04)
863 return;
864 pci_read_config_word(pdev, 0x40, &config);
865 if (config & (1<<6)) {
866 config &= ~(1<<6);
867 pci_write_config_word(pdev, 0x40, config);
868 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
869 }
870}
871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
872DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
873
874static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
875{
876
877 u8 tmp;
878
879 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
880 if (tmp == 0x01) {
881 pci_read_config_byte(pdev, 0x40, &tmp);
882 pci_write_config_byte(pdev, 0x40, tmp|1);
883 pci_write_config_byte(pdev, 0x9, 1);
884 pci_write_config_byte(pdev, 0xa, 6);
885 pci_write_config_byte(pdev, 0x40, tmp);
886
887 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
888 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
889 }
890}
891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
892DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
894DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
895
896
897
898
899static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
900{
901 u8 prog;
902 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
903 if (prog & 5) {
904 prog &= ~5;
905 pdev->class &= ~5;
906 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
907
908 }
909}
910DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
911
912
913
914
915static void __init quirk_ide_samemode(struct pci_dev *pdev)
916{
917 u8 prog;
918
919 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
920
921 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
922 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
923 prog &= ~5;
924 pdev->class &= ~5;
925 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
926 }
927}
928DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
929
930
931
932
933
934static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
935{
936
937 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
938 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
939}
940DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
941DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
942
943
944
945
946static void __init quirk_eisa_bridge(struct pci_dev *dev)
947{
948 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
949}
950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978static int asus_hides_smbus;
979
980static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
981{
982 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
983 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
984 switch(dev->subsystem_device) {
985 case 0x8025:
986 case 0x8070:
987 case 0x8088:
988 case 0x1626:
989 asus_hides_smbus = 1;
990 }
991 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
992 switch(dev->subsystem_device) {
993 case 0x80b1:
994 case 0x80b2:
995 case 0x8093:
996 asus_hides_smbus = 1;
997 }
998 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
999 switch(dev->subsystem_device) {
1000 case 0x8030:
1001 asus_hides_smbus = 1;
1002 }
1003 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1004 switch (dev->subsystem_device) {
1005 case 0x8070:
1006 asus_hides_smbus = 1;
1007 }
1008 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1009 switch (dev->subsystem_device) {
1010 case 0x80c9:
1011 asus_hides_smbus = 1;
1012 }
1013 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1014 switch (dev->subsystem_device) {
1015 case 0x1751:
1016 case 0x1821:
1017 asus_hides_smbus = 1;
1018 }
1019 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1020 switch (dev->subsystem_device) {
1021 case 0x184b:
1022 case 0x186a:
1023 asus_hides_smbus = 1;
1024 }
1025 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1026 switch (dev->subsystem_device) {
1027 case 0x80f2:
1028 asus_hides_smbus = 1;
1029 }
1030 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1031 switch (dev->subsystem_device) {
1032 case 0x1882:
1033 case 0x1977:
1034 asus_hides_smbus = 1;
1035 }
1036 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1037 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1038 switch(dev->subsystem_device) {
1039 case 0x088C:
1040 case 0x0890:
1041 asus_hides_smbus = 1;
1042 }
1043 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1044 switch (dev->subsystem_device) {
1045 case 0x12bc:
1046 case 0x12bd:
1047 asus_hides_smbus = 1;
1048 }
1049 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1050 switch (dev->subsystem_device) {
1051 case 0x12bf:
1052 asus_hides_smbus = 1;
1053 }
1054 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1055 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1056 switch(dev->subsystem_device) {
1057 case 0xC00C:
1058 asus_hides_smbus = 1;
1059 }
1060 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1061 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1062 switch(dev->subsystem_device) {
1063 case 0x0058:
1064 asus_hides_smbus = 1;
1065 }
1066 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1067 switch(dev->subsystem_device) {
1068 case 0xB16C:
1069
1070
1071
1072 asus_hides_smbus = 1;
1073 }
1074 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1075 switch(dev->subsystem_device) {
1076 case 0x00b8:
1077 case 0x00b9:
1078 asus_hides_smbus = 1;
1079 }
1080 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1081 switch (dev->subsystem_device) {
1082 case 0x001A:
1083
1084
1085
1086 asus_hides_smbus = 1;
1087 }
1088 }
1089}
1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1096DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1099DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1100
1101DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
1103DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1104
1105static void asus_hides_smbus_lpc(struct pci_dev *dev)
1106{
1107 u16 val;
1108
1109 if (likely(!asus_hides_smbus))
1110 return;
1111
1112 pci_read_config_word(dev, 0xF2, &val);
1113 if (val & 0x8) {
1114 pci_write_config_word(dev, 0xF2, val & (~0x8));
1115 pci_read_config_word(dev, 0xF2, &val);
1116 if (val & 0x8)
1117 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1118 else
1119 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1120 }
1121}
1122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1125DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1129DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1130DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1131DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1132DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1133DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1134DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1135DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1136
1137
1138static void __iomem *asus_rcba_base;
1139static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1140{
1141 u32 rcba;
1142
1143 if (likely(!asus_hides_smbus))
1144 return;
1145 WARN_ON(asus_rcba_base);
1146
1147 pci_read_config_dword(dev, 0xF0, &rcba);
1148
1149 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1150 if (asus_rcba_base == NULL)
1151 return;
1152}
1153
1154static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1155{
1156 u32 val;
1157
1158 if (likely(!asus_hides_smbus || !asus_rcba_base))
1159 return;
1160
1161 val = readl(asus_rcba_base + 0x3418);
1162 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1163}
1164
1165static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1166{
1167 if (likely(!asus_hides_smbus || !asus_rcba_base))
1168 return;
1169 iounmap(asus_rcba_base);
1170 asus_rcba_base = NULL;
1171 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1172}
1173
1174static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1175{
1176 asus_hides_smbus_lpc_ich6_suspend(dev);
1177 asus_hides_smbus_lpc_ich6_resume_early(dev);
1178 asus_hides_smbus_lpc_ich6_resume(dev);
1179}
1180DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1181DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1182DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1183DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1184
1185
1186
1187
1188static void quirk_sis_96x_smbus(struct pci_dev *dev)
1189{
1190 u8 val = 0;
1191 pci_read_config_byte(dev, 0x77, &val);
1192 if (val & 0x10) {
1193 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1194 pci_write_config_byte(dev, 0x77, val & ~0x10);
1195 }
1196}
1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1198DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1199DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1200DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1201DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1202DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1203DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1204DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214#define SIS_DETECT_REGISTER 0x40
1215
1216static void quirk_sis_503(struct pci_dev *dev)
1217{
1218 u8 reg;
1219 u16 devid;
1220
1221 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1222 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1223 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1224 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1225 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1226 return;
1227 }
1228
1229
1230
1231
1232
1233
1234 dev->device = devid;
1235 quirk_sis_96x_smbus(dev);
1236}
1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1238DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1239
1240
1241
1242
1243
1244
1245
1246
1247static void asus_hides_ac97_lpc(struct pci_dev *dev)
1248{
1249 u8 val;
1250 int asus_hides_ac97 = 0;
1251
1252 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1253 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1254 asus_hides_ac97 = 1;
1255 }
1256
1257 if (!asus_hides_ac97)
1258 return;
1259
1260 pci_read_config_byte(dev, 0x50, &val);
1261 if (val & 0xc0) {
1262 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1263 pci_read_config_byte(dev, 0x50, &val);
1264 if (val & 0xc0)
1265 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1266 else
1267 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1268 }
1269}
1270DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1271DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1272
1273#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1274
1275
1276
1277
1278
1279
1280static void quirk_jmicron_ata(struct pci_dev *pdev)
1281{
1282 u32 conf1, conf5, class;
1283 u8 hdr;
1284
1285
1286 if (PCI_FUNC(pdev->devfn))
1287 return;
1288
1289 pci_read_config_dword(pdev, 0x40, &conf1);
1290 pci_read_config_dword(pdev, 0x80, &conf5);
1291
1292 conf1 &= ~0x00CFF302;
1293 conf5 &= ~(1 << 24);
1294
1295 switch (pdev->device) {
1296 case PCI_DEVICE_ID_JMICRON_JMB360:
1297
1298 conf1 |= 0x0002A100;
1299 break;
1300
1301 case PCI_DEVICE_ID_JMICRON_JMB365:
1302 case PCI_DEVICE_ID_JMICRON_JMB366:
1303
1304 conf5 |= (1 << 24);
1305
1306 case PCI_DEVICE_ID_JMICRON_JMB361:
1307 case PCI_DEVICE_ID_JMICRON_JMB363:
1308
1309
1310 conf1 |= 0x00C2A1B3;
1311 break;
1312
1313 case PCI_DEVICE_ID_JMICRON_JMB368:
1314
1315 conf1 |= 0x00C00000;
1316 break;
1317 }
1318
1319 pci_write_config_dword(pdev, 0x40, conf1);
1320 pci_write_config_dword(pdev, 0x80, conf5);
1321
1322
1323 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1324 pdev->hdr_type = hdr & 0x7f;
1325 pdev->multifunction = !!(hdr & 0x80);
1326
1327 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1328 pdev->class = class >> 8;
1329}
1330DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1331DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1332DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1333DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1334DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1335DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1336DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1337DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1338DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1339DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1340DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1341DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1342
1343#endif
1344
1345#ifdef CONFIG_X86_IO_APIC
1346static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1347{
1348 int i;
1349
1350 if ((pdev->class >> 8) != 0xff00)
1351 return;
1352
1353
1354
1355
1356 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1357 insert_resource(&iomem_resource, &pdev->resource[0]);
1358
1359
1360
1361 for (i=1; i < 6; i++) {
1362 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1363 }
1364
1365}
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1367#endif
1368
1369static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1370{
1371 pcie_mch_quirk = 1;
1372}
1373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1376
1377
1378
1379
1380
1381
1382static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1383{
1384 pci_msi_off(dev);
1385 dev->no_msi = 1;
1386 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1387}
1388DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1389DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1390DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1391DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1392DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1393
1394
1395
1396
1397
1398static void quirk_intel_pcie_pm(struct pci_dev * dev)
1399{
1400 pci_pm_d3_delay = 120;
1401 dev->no_d1d2 = 1;
1402}
1403
1404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1412DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1413DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1414DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1415DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1416DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1419DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1420DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1421DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1423DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1425
1426
1427
1428
1429
1430
1431static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1432{
1433 struct resource *r = &dev->resource[0];
1434
1435 if (r->start & 0x8) {
1436 r->start = 0;
1437 r->end = 0xf;
1438 }
1439}
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1441 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1442 quirk_tc86c001_ide);
1443
1444static void __devinit quirk_netmos(struct pci_dev *dev)
1445{
1446 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1447 unsigned int num_serial = dev->subsystem_device & 0xf;
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459 switch (dev->device) {
1460 case PCI_DEVICE_ID_NETMOS_9735:
1461 case PCI_DEVICE_ID_NETMOS_9745:
1462 case PCI_DEVICE_ID_NETMOS_9835:
1463 case PCI_DEVICE_ID_NETMOS_9845:
1464 case PCI_DEVICE_ID_NETMOS_9855:
1465 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1466 num_parallel) {
1467 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1468 "%u serial); changing class SERIAL to OTHER "
1469 "(use parport_serial)\n",
1470 dev->device, num_parallel, num_serial);
1471 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1472 (dev->class & 0xff);
1473 }
1474 }
1475}
1476DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1477
1478static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1479{
1480 u16 command, pmcsr;
1481 u8 __iomem *csr;
1482 u8 cmd_hi;
1483 int pm;
1484
1485 switch (dev->device) {
1486
1487 case 0x1029:
1488 case 0x1030 ... 0x1034:
1489 case 0x1038 ... 0x103E:
1490 case 0x1050 ... 0x1057:
1491 case 0x1059:
1492 case 0x1064 ... 0x106B:
1493 case 0x1091 ... 0x1095:
1494 case 0x1209:
1495 case 0x1229:
1496 case 0x2449:
1497 case 0x2459:
1498 case 0x245D:
1499 case 0x27DC:
1500 break;
1501 default:
1502 return;
1503 }
1504
1505
1506
1507
1508
1509
1510
1511
1512 pci_read_config_word(dev, PCI_COMMAND, &command);
1513
1514 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1515 return;
1516
1517
1518
1519
1520
1521 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1522 if (pm) {
1523 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1524 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1525 return;
1526 }
1527
1528
1529 csr = ioremap(pci_resource_start(dev, 0), 8);
1530 if (!csr) {
1531 dev_warn(&dev->dev, "Can't map e100 registers\n");
1532 return;
1533 }
1534
1535 cmd_hi = readb(csr + 3);
1536 if (cmd_hi == 0) {
1537 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1538 "disabling\n");
1539 writeb(1, csr + 3);
1540 }
1541
1542 iounmap(csr);
1543}
1544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1545
1546static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1547{
1548
1549
1550
1551
1552 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1553 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1554 dev->class = PCI_CLASS_STORAGE_SCSI;
1555 }
1556}
1557DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1558
1559
1560static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1561{
1562 u16 en1k;
1563 u8 io_base_lo, io_limit_lo;
1564 unsigned long base, limit;
1565 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1566
1567 pci_read_config_word(dev, 0x40, &en1k);
1568
1569 if (en1k & 0x200) {
1570 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1571
1572 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1573 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1574 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1575 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1576
1577 if (base <= limit) {
1578 res->start = base;
1579 res->end = limit + 0x3ff;
1580 }
1581 }
1582}
1583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1584
1585
1586
1587
1588
1589static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1590{
1591 u16 en1k, iobl_adr, iobl_adr_1k;
1592 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1593
1594 pci_read_config_word(dev, 0x40, &en1k);
1595
1596 if (en1k & 0x200) {
1597 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1598
1599 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1600
1601 if (iobl_adr != iobl_adr_1k) {
1602 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1603 iobl_adr,iobl_adr_1k);
1604 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1605 }
1606 }
1607}
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1609
1610
1611
1612
1613
1614static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1615{
1616 uint8_t b;
1617 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1618 if (!(b & 0x20)) {
1619 pci_write_config_byte(dev, 0xf41, b | 0x20);
1620 dev_info(&dev->dev,
1621 "Linking AER extended capability\n");
1622 }
1623 }
1624}
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1626 quirk_nvidia_ck804_pcie_aer_ext_cap);
1627DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1628 quirk_nvidia_ck804_pcie_aer_ext_cap);
1629
1630static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1631{
1632
1633
1634
1635
1636
1637
1638
1639 uint8_t b;
1640 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1641 if (b & 0x40) {
1642
1643 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1644
1645 dev_info(&dev->dev,
1646 "Disabling VIA CX700 PCI parking\n");
1647 }
1648 }
1649
1650 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1651 if (b != 0) {
1652
1653 pci_write_config_byte(dev, 0x72, 0x0);
1654
1655
1656 pci_write_config_byte(dev, 0x75, 0x1);
1657
1658
1659 pci_write_config_byte(dev, 0x77, 0x0);
1660
1661 dev_info(&dev->dev,
1662 "Disabling VIA CX700 PCI caching\n");
1663 }
1664 }
1665}
1666DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1680{
1681
1682
1683
1684
1685 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
1686 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
1687 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
1688 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
1689 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1690 (dev->revision & 0xf0) == 0x0)) {
1691 if (dev->vpd)
1692 dev->vpd->len = 0x80;
1693 }
1694}
1695
1696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1697 PCI_DEVICE_ID_NX2_5706,
1698 quirk_brcm_570x_limit_vpd);
1699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1700 PCI_DEVICE_ID_NX2_5706S,
1701 quirk_brcm_570x_limit_vpd);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1703 PCI_DEVICE_ID_NX2_5708,
1704 quirk_brcm_570x_limit_vpd);
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1706 PCI_DEVICE_ID_NX2_5708S,
1707 quirk_brcm_570x_limit_vpd);
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1709 PCI_DEVICE_ID_NX2_5709,
1710 quirk_brcm_570x_limit_vpd);
1711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1712 PCI_DEVICE_ID_NX2_5709S,
1713 quirk_brcm_570x_limit_vpd);
1714
1715#ifdef CONFIG_PCI_MSI
1716
1717
1718
1719
1720
1721
1722static void __init quirk_disable_all_msi(struct pci_dev *dev)
1723{
1724 pci_no_msi();
1725 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1726}
1727DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1728DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1729DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
1730DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
1731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
1732
1733
1734static void __devinit quirk_disable_msi(struct pci_dev *dev)
1735{
1736 if (dev->subordinate) {
1737 dev_warn(&dev->dev, "MSI quirk detected; "
1738 "subordinate MSI disabled\n");
1739 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1740 }
1741}
1742DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
1743
1744
1745
1746static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1747{
1748 int pos, ttl = 48;
1749
1750 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1751 while (pos && ttl--) {
1752 u8 flags;
1753
1754 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1755 &flags) == 0)
1756 {
1757 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1758 flags & HT_MSI_FLAGS_ENABLE ?
1759 "enabled" : "disabled");
1760 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1761 }
1762
1763 pos = pci_find_next_ht_capability(dev, pos,
1764 HT_CAPTYPE_MSI_MAPPING);
1765 }
1766 return 0;
1767}
1768
1769
1770static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1771{
1772 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1773 dev_warn(&dev->dev, "MSI quirk detected; "
1774 "subordinate MSI disabled\n");
1775 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1776 }
1777}
1778DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1779 quirk_msi_ht_cap);
1780
1781
1782
1783
1784
1785static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1786{
1787 struct pci_dev *pdev;
1788
1789 if (!dev->subordinate)
1790 return;
1791
1792
1793
1794
1795 pdev = pci_get_slot(dev->bus, 0);
1796 if (!pdev)
1797 return;
1798 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1799 dev_warn(&dev->dev, "MSI quirk detected; "
1800 "subordinate MSI disabled\n");
1801 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1802 }
1803 pci_dev_put(pdev);
1804}
1805DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1806 quirk_nvidia_ck804_msi_ht_cap);
1807
1808
1809static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
1810{
1811 int pos, ttl = 48;
1812
1813 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1814 while (pos && ttl--) {
1815 u8 flags;
1816
1817 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1818 &flags) == 0) {
1819 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1820
1821 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1822 flags | HT_MSI_FLAGS_ENABLE);
1823 }
1824 pos = pci_find_next_ht_capability(dev, pos,
1825 HT_CAPTYPE_MSI_MAPPING);
1826 }
1827}
1828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1829 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1830 ht_enable_msi_mapping);
1831
1832
1833
1834
1835
1836static void __devinit nvenet_msi_disable(struct pci_dev *dev)
1837{
1838 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
1839 dev_info(&dev->dev,
1840 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
1841 dev->no_msi = 1;
1842 }
1843}
1844DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
1845 PCI_DEVICE_ID_NVIDIA_NVENET_15,
1846 nvenet_msi_disable);
1847
1848static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1849{
1850 struct pci_dev *host_bridge;
1851 int pos, ttl = 48;
1852
1853
1854
1855
1856
1857 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1858 if (host_bridge == NULL) {
1859 dev_warn(&dev->dev,
1860 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1861 return;
1862 }
1863
1864 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1865 if (pos != 0) {
1866
1867 ht_enable_msi_mapping(dev);
1868 return;
1869 }
1870
1871
1872 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1873 while (pos && ttl--) {
1874 u8 flags;
1875
1876 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1877 &flags) == 0) {
1878 dev_info(&dev->dev, "Disabling HT MSI mapping");
1879 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1880 flags & ~HT_MSI_FLAGS_ENABLE);
1881 }
1882 pos = pci_find_next_ht_capability(dev, pos,
1883 HT_CAPTYPE_MSI_MAPPING);
1884 }
1885}
1886DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
1887DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
1888
1889static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1890{
1891 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1892}
1893static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1894{
1895 struct pci_dev *p;
1896
1897
1898
1899
1900
1901 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1902 NULL);
1903 if (!p)
1904 return;
1905
1906 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1907 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1908 pci_dev_put(p);
1909}
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1911 PCI_DEVICE_ID_TIGON3_5780,
1912 quirk_msi_intx_disable_bug);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1914 PCI_DEVICE_ID_TIGON3_5780S,
1915 quirk_msi_intx_disable_bug);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1917 PCI_DEVICE_ID_TIGON3_5714,
1918 quirk_msi_intx_disable_bug);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1920 PCI_DEVICE_ID_TIGON3_5714S,
1921 quirk_msi_intx_disable_bug);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1923 PCI_DEVICE_ID_TIGON3_5715,
1924 quirk_msi_intx_disable_bug);
1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1926 PCI_DEVICE_ID_TIGON3_5715S,
1927 quirk_msi_intx_disable_bug);
1928
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
1930 quirk_msi_intx_disable_ati_bug);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
1932 quirk_msi_intx_disable_ati_bug);
1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
1934 quirk_msi_intx_disable_ati_bug);
1935DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
1936 quirk_msi_intx_disable_ati_bug);
1937DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
1938 quirk_msi_intx_disable_ati_bug);
1939
1940DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1941 quirk_msi_intx_disable_bug);
1942DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
1943 quirk_msi_intx_disable_bug);
1944DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
1945 quirk_msi_intx_disable_bug);
1946
1947#endif
1948
1949static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1950{
1951 while (f < end) {
1952 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1953 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1954 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
1955 f->hook(dev);
1956 }
1957 f++;
1958 }
1959}
1960
1961extern struct pci_fixup __start_pci_fixups_early[];
1962extern struct pci_fixup __end_pci_fixups_early[];
1963extern struct pci_fixup __start_pci_fixups_header[];
1964extern struct pci_fixup __end_pci_fixups_header[];
1965extern struct pci_fixup __start_pci_fixups_final[];
1966extern struct pci_fixup __end_pci_fixups_final[];
1967extern struct pci_fixup __start_pci_fixups_enable[];
1968extern struct pci_fixup __end_pci_fixups_enable[];
1969extern struct pci_fixup __start_pci_fixups_resume[];
1970extern struct pci_fixup __end_pci_fixups_resume[];
1971extern struct pci_fixup __start_pci_fixups_resume_early[];
1972extern struct pci_fixup __end_pci_fixups_resume_early[];
1973extern struct pci_fixup __start_pci_fixups_suspend[];
1974extern struct pci_fixup __end_pci_fixups_suspend[];
1975
1976
1977void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1978{
1979 struct pci_fixup *start, *end;
1980
1981 switch(pass) {
1982 case pci_fixup_early:
1983 start = __start_pci_fixups_early;
1984 end = __end_pci_fixups_early;
1985 break;
1986
1987 case pci_fixup_header:
1988 start = __start_pci_fixups_header;
1989 end = __end_pci_fixups_header;
1990 break;
1991
1992 case pci_fixup_final:
1993 start = __start_pci_fixups_final;
1994 end = __end_pci_fixups_final;
1995 break;
1996
1997 case pci_fixup_enable:
1998 start = __start_pci_fixups_enable;
1999 end = __end_pci_fixups_enable;
2000 break;
2001
2002 case pci_fixup_resume:
2003 start = __start_pci_fixups_resume;
2004 end = __end_pci_fixups_resume;
2005 break;
2006
2007 case pci_fixup_resume_early:
2008 start = __start_pci_fixups_resume_early;
2009 end = __end_pci_fixups_resume_early;
2010 break;
2011
2012 case pci_fixup_suspend:
2013 start = __start_pci_fixups_suspend;
2014 end = __end_pci_fixups_suspend;
2015 break;
2016
2017 default:
2018
2019 return;
2020 }
2021 pci_do_fixups(dev, start, end);
2022}
2023#else
2024void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2025#endif
2026EXPORT_SYMBOL(pci_fixup_device);