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34#include "e1000_hw.h"
35
36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static s32 e1000_check_downshift(struct e1000_hw *hw);
45static s32 e1000_check_polarity(struct e1000_hw *hw,
46 e1000_rev_polarity *polarity);
47static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
48static void e1000_clear_vfta(struct e1000_hw *hw);
49static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
50static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
51 bool link_up);
52static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
53static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
54static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
55static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
56static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
57 u16 *max_length);
58static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
59static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
60static s32 e1000_get_software_flag(struct e1000_hw *hw);
61static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
62static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
63static s32 e1000_id_led_init(struct e1000_hw *hw);
64static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
65 u32 cnf_base_addr,
66 u32 cnf_size);
67static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
68static void e1000_init_rx_addrs(struct e1000_hw *hw);
69static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
70static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
71static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
72static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
73static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
74 u16 offset, u8 *sum);
75static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
76 struct e1000_host_mng_command_header
77 *hdr);
78static s32 e1000_mng_write_commit(struct e1000_hw *hw);
79static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
80 struct e1000_phy_info *phy_info);
81static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
82 struct e1000_phy_info *phy_info);
83static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
84 u16 *data);
85static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
86 u16 *data);
87static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
88static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
89 struct e1000_phy_info *phy_info);
90static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
91static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
92static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
93 u8 byte);
94static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
95static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
96static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
97 u16 *data);
98static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
99 u16 data);
100static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
101 u16 *data);
102static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
103 u16 *data);
104static void e1000_release_software_flag(struct e1000_hw *hw);
105static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
106static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
107static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
108static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
109static s32 e1000_wait_autoneg(struct e1000_hw *hw);
110static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
111static s32 e1000_set_phy_type(struct e1000_hw *hw);
112static void e1000_phy_init_script(struct e1000_hw *hw);
113static s32 e1000_setup_copper_link(struct e1000_hw *hw);
114static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
115static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
116static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
117static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
118static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
119static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
120static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
121 u16 count);
122static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
123static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
124static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
125 u16 words, u16 *data);
126static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
127 u16 words, u16 *data);
128static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
129static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
130static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
131static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
132static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
133 u16 phy_data);
134static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
135 u16 *phy_data);
136static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
137static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
138static void e1000_release_eeprom(struct e1000_hw *hw);
139static void e1000_standby_eeprom(struct e1000_hw *hw);
140static s32 e1000_set_vco_speed(struct e1000_hw *hw);
141static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
142static s32 e1000_set_phy_mode(struct e1000_hw *hw);
143static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
144static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
145static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
146static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
147static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
148static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
149
150
151static const
152u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
153 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
154 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
155 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
156 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
157 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
158 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
159 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
160 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
161
162static const
163u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
164 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
165 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
166 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
167 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
168 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
169 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
170 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
171 104, 109, 114, 118, 121, 124};
172
173static DEFINE_SPINLOCK(e1000_eeprom_lock);
174
175
176
177
178
179
180static s32 e1000_set_phy_type(struct e1000_hw *hw)
181{
182 DEBUGFUNC("e1000_set_phy_type");
183
184 if (hw->mac_type == e1000_undefined)
185 return -E1000_ERR_PHY_TYPE;
186
187 switch (hw->phy_id) {
188 case M88E1000_E_PHY_ID:
189 case M88E1000_I_PHY_ID:
190 case M88E1011_I_PHY_ID:
191 case M88E1111_I_PHY_ID:
192 hw->phy_type = e1000_phy_m88;
193 break;
194 case IGP01E1000_I_PHY_ID:
195 if (hw->mac_type == e1000_82541 ||
196 hw->mac_type == e1000_82541_rev_2 ||
197 hw->mac_type == e1000_82547 ||
198 hw->mac_type == e1000_82547_rev_2) {
199 hw->phy_type = e1000_phy_igp;
200 break;
201 }
202 case IGP03E1000_E_PHY_ID:
203 hw->phy_type = e1000_phy_igp_3;
204 break;
205 case IFE_E_PHY_ID:
206 case IFE_PLUS_E_PHY_ID:
207 case IFE_C_E_PHY_ID:
208 hw->phy_type = e1000_phy_ife;
209 break;
210 case GG82563_E_PHY_ID:
211 if (hw->mac_type == e1000_80003es2lan) {
212 hw->phy_type = e1000_phy_gg82563;
213 break;
214 }
215
216 default:
217
218 hw->phy_type = e1000_phy_undefined;
219 return -E1000_ERR_PHY_TYPE;
220 }
221
222 return E1000_SUCCESS;
223}
224
225
226
227
228
229
230static void e1000_phy_init_script(struct e1000_hw *hw)
231{
232 u32 ret_val;
233 u16 phy_saved_data;
234
235 DEBUGFUNC("e1000_phy_init_script");
236
237 if (hw->phy_init_script) {
238 msleep(20);
239
240
241
242 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
243
244
245 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
246
247 msleep(20);
248
249 e1000_write_phy_reg(hw,0x0000,0x0140);
250
251 msleep(5);
252
253 switch (hw->mac_type) {
254 case e1000_82541:
255 case e1000_82547:
256 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
257
258 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
259
260 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
261
262 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
263
264 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
265
266 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
267
268 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
269
270 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
271
272 e1000_write_phy_reg(hw, 0x2010, 0x0008);
273 break;
274
275 case e1000_82541_rev_2:
276 case e1000_82547_rev_2:
277 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
278 break;
279 default:
280 break;
281 }
282
283 e1000_write_phy_reg(hw, 0x0000, 0x3300);
284
285 msleep(20);
286
287
288 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
289
290 if (hw->mac_type == e1000_82547) {
291 u16 fused, fine, coarse;
292
293
294 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
295
296 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
297 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
298
299 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
300 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
301
302 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
303 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
304 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
305 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
306 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
307
308 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
309 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
310 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
311
312 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
313 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
314 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
315 }
316 }
317 }
318}
319
320
321
322
323
324
325s32 e1000_set_mac_type(struct e1000_hw *hw)
326{
327 DEBUGFUNC("e1000_set_mac_type");
328
329 switch (hw->device_id) {
330 case E1000_DEV_ID_82542:
331 switch (hw->revision_id) {
332 case E1000_82542_2_0_REV_ID:
333 hw->mac_type = e1000_82542_rev2_0;
334 break;
335 case E1000_82542_2_1_REV_ID:
336 hw->mac_type = e1000_82542_rev2_1;
337 break;
338 default:
339
340 return -E1000_ERR_MAC_TYPE;
341 }
342 break;
343 case E1000_DEV_ID_82543GC_FIBER:
344 case E1000_DEV_ID_82543GC_COPPER:
345 hw->mac_type = e1000_82543;
346 break;
347 case E1000_DEV_ID_82544EI_COPPER:
348 case E1000_DEV_ID_82544EI_FIBER:
349 case E1000_DEV_ID_82544GC_COPPER:
350 case E1000_DEV_ID_82544GC_LOM:
351 hw->mac_type = e1000_82544;
352 break;
353 case E1000_DEV_ID_82540EM:
354 case E1000_DEV_ID_82540EM_LOM:
355 case E1000_DEV_ID_82540EP:
356 case E1000_DEV_ID_82540EP_LOM:
357 case E1000_DEV_ID_82540EP_LP:
358 hw->mac_type = e1000_82540;
359 break;
360 case E1000_DEV_ID_82545EM_COPPER:
361 case E1000_DEV_ID_82545EM_FIBER:
362 hw->mac_type = e1000_82545;
363 break;
364 case E1000_DEV_ID_82545GM_COPPER:
365 case E1000_DEV_ID_82545GM_FIBER:
366 case E1000_DEV_ID_82545GM_SERDES:
367 hw->mac_type = e1000_82545_rev_3;
368 break;
369 case E1000_DEV_ID_82546EB_COPPER:
370 case E1000_DEV_ID_82546EB_FIBER:
371 case E1000_DEV_ID_82546EB_QUAD_COPPER:
372 hw->mac_type = e1000_82546;
373 break;
374 case E1000_DEV_ID_82546GB_COPPER:
375 case E1000_DEV_ID_82546GB_FIBER:
376 case E1000_DEV_ID_82546GB_SERDES:
377 case E1000_DEV_ID_82546GB_PCIE:
378 case E1000_DEV_ID_82546GB_QUAD_COPPER:
379 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
380 hw->mac_type = e1000_82546_rev_3;
381 break;
382 case E1000_DEV_ID_82541EI:
383 case E1000_DEV_ID_82541EI_MOBILE:
384 case E1000_DEV_ID_82541ER_LOM:
385 hw->mac_type = e1000_82541;
386 break;
387 case E1000_DEV_ID_82541ER:
388 case E1000_DEV_ID_82541GI:
389 case E1000_DEV_ID_82541GI_LF:
390 case E1000_DEV_ID_82541GI_MOBILE:
391 hw->mac_type = e1000_82541_rev_2;
392 break;
393 case E1000_DEV_ID_82547EI:
394 case E1000_DEV_ID_82547EI_MOBILE:
395 hw->mac_type = e1000_82547;
396 break;
397 case E1000_DEV_ID_82547GI:
398 hw->mac_type = e1000_82547_rev_2;
399 break;
400 case E1000_DEV_ID_82571EB_COPPER:
401 case E1000_DEV_ID_82571EB_FIBER:
402 case E1000_DEV_ID_82571EB_SERDES:
403 case E1000_DEV_ID_82571EB_SERDES_DUAL:
404 case E1000_DEV_ID_82571EB_SERDES_QUAD:
405 case E1000_DEV_ID_82571EB_QUAD_COPPER:
406 case E1000_DEV_ID_82571PT_QUAD_COPPER:
407 case E1000_DEV_ID_82571EB_QUAD_FIBER:
408 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
409 hw->mac_type = e1000_82571;
410 break;
411 case E1000_DEV_ID_82572EI_COPPER:
412 case E1000_DEV_ID_82572EI_FIBER:
413 case E1000_DEV_ID_82572EI_SERDES:
414 case E1000_DEV_ID_82572EI:
415 hw->mac_type = e1000_82572;
416 break;
417 case E1000_DEV_ID_82573E:
418 case E1000_DEV_ID_82573E_IAMT:
419 case E1000_DEV_ID_82573L:
420 hw->mac_type = e1000_82573;
421 break;
422 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
423 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
424 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
425 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
426 hw->mac_type = e1000_80003es2lan;
427 break;
428 case E1000_DEV_ID_ICH8_IGP_M_AMT:
429 case E1000_DEV_ID_ICH8_IGP_AMT:
430 case E1000_DEV_ID_ICH8_IGP_C:
431 case E1000_DEV_ID_ICH8_IFE:
432 case E1000_DEV_ID_ICH8_IFE_GT:
433 case E1000_DEV_ID_ICH8_IFE_G:
434 case E1000_DEV_ID_ICH8_IGP_M:
435 hw->mac_type = e1000_ich8lan;
436 break;
437 default:
438
439 return -E1000_ERR_MAC_TYPE;
440 }
441
442 switch (hw->mac_type) {
443 case e1000_ich8lan:
444 hw->swfwhw_semaphore_present = true;
445 hw->asf_firmware_present = true;
446 break;
447 case e1000_80003es2lan:
448 hw->swfw_sync_present = true;
449
450 case e1000_82571:
451 case e1000_82572:
452 case e1000_82573:
453 hw->eeprom_semaphore_present = true;
454
455 case e1000_82541:
456 case e1000_82547:
457 case e1000_82541_rev_2:
458 case e1000_82547_rev_2:
459 hw->asf_firmware_present = true;
460 break;
461 default:
462 break;
463 }
464
465
466
467
468 if (hw->mac_type == e1000_82543)
469 hw->bad_tx_carr_stats_fd = true;
470
471
472 if (hw->mac_type >= e1000_82571)
473 hw->has_manc2h = true;
474
475
476
477
478 if (hw->mac_type == e1000_80003es2lan)
479 hw->rx_needs_kicking = true;
480
481 if (hw->mac_type > e1000_82544)
482 hw->has_smbus = true;
483
484 return E1000_SUCCESS;
485}
486
487
488
489
490
491
492void e1000_set_media_type(struct e1000_hw *hw)
493{
494 u32 status;
495
496 DEBUGFUNC("e1000_set_media_type");
497
498 if (hw->mac_type != e1000_82543) {
499
500 hw->tbi_compatibility_en = false;
501 }
502
503 switch (hw->device_id) {
504 case E1000_DEV_ID_82545GM_SERDES:
505 case E1000_DEV_ID_82546GB_SERDES:
506 case E1000_DEV_ID_82571EB_SERDES:
507 case E1000_DEV_ID_82571EB_SERDES_DUAL:
508 case E1000_DEV_ID_82571EB_SERDES_QUAD:
509 case E1000_DEV_ID_82572EI_SERDES:
510 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
511 hw->media_type = e1000_media_type_internal_serdes;
512 break;
513 default:
514 switch (hw->mac_type) {
515 case e1000_82542_rev2_0:
516 case e1000_82542_rev2_1:
517 hw->media_type = e1000_media_type_fiber;
518 break;
519 case e1000_ich8lan:
520 case e1000_82573:
521
522
523
524 hw->media_type = e1000_media_type_copper;
525 break;
526 default:
527 status = er32(STATUS);
528 if (status & E1000_STATUS_TBIMODE) {
529 hw->media_type = e1000_media_type_fiber;
530
531 hw->tbi_compatibility_en = false;
532 } else {
533 hw->media_type = e1000_media_type_copper;
534 }
535 break;
536 }
537 }
538}
539
540
541
542
543
544
545s32 e1000_reset_hw(struct e1000_hw *hw)
546{
547 u32 ctrl;
548 u32 ctrl_ext;
549 u32 icr;
550 u32 manc;
551 u32 led_ctrl;
552 u32 timeout;
553 u32 extcnf_ctrl;
554 s32 ret_val;
555
556 DEBUGFUNC("e1000_reset_hw");
557
558
559 if (hw->mac_type == e1000_82542_rev2_0) {
560 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
561 e1000_pci_clear_mwi(hw);
562 }
563
564 if (hw->bus_type == e1000_bus_type_pci_express) {
565
566
567
568 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
569 DEBUGOUT("PCI-E Master disable polling has failed.\n");
570 }
571 }
572
573
574 DEBUGOUT("Masking off all interrupts\n");
575 ew32(IMC, 0xffffffff);
576
577
578
579
580
581 ew32(RCTL, 0);
582 ew32(TCTL, E1000_TCTL_PSP);
583 E1000_WRITE_FLUSH();
584
585
586 hw->tbi_compatibility_on = false;
587
588
589
590
591 msleep(10);
592
593 ctrl = er32(CTRL);
594
595
596 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
597 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
598 msleep(5);
599 }
600
601
602
603 if (hw->mac_type == e1000_82573) {
604 timeout = 10;
605
606 extcnf_ctrl = er32(EXTCNF_CTRL);
607 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
608
609 do {
610 ew32(EXTCNF_CTRL, extcnf_ctrl);
611 extcnf_ctrl = er32(EXTCNF_CTRL);
612
613 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
614 break;
615 else
616 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
617
618 msleep(2);
619 timeout--;
620 } while (timeout);
621 }
622
623
624 if (hw->mac_type == e1000_ich8lan) {
625
626 ew32(PBA, E1000_PBA_8K);
627
628 ew32(PBS, E1000_PBS_16K);
629 }
630
631
632
633
634
635
636 DEBUGOUT("Issuing a global reset to MAC\n");
637
638 switch (hw->mac_type) {
639 case e1000_82544:
640 case e1000_82540:
641 case e1000_82545:
642 case e1000_82546:
643 case e1000_82541:
644 case e1000_82541_rev_2:
645
646
647 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
648 break;
649 case e1000_82545_rev_3:
650 case e1000_82546_rev_3:
651
652 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
653 break;
654 case e1000_ich8lan:
655 if (!hw->phy_reset_disable &&
656 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
657
658
659
660
661 ctrl |= E1000_CTRL_PHY_RST;
662 }
663
664 e1000_get_software_flag(hw);
665 ew32(CTRL, (ctrl | E1000_CTRL_RST));
666 msleep(5);
667 break;
668 default:
669 ew32(CTRL, (ctrl | E1000_CTRL_RST));
670 break;
671 }
672
673
674
675
676
677 switch (hw->mac_type) {
678 case e1000_82542_rev2_0:
679 case e1000_82542_rev2_1:
680 case e1000_82543:
681 case e1000_82544:
682
683 udelay(10);
684 ctrl_ext = er32(CTRL_EXT);
685 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
686 ew32(CTRL_EXT, ctrl_ext);
687 E1000_WRITE_FLUSH();
688
689 msleep(2);
690 break;
691 case e1000_82541:
692 case e1000_82541_rev_2:
693 case e1000_82547:
694 case e1000_82547_rev_2:
695
696 msleep(20);
697 break;
698 case e1000_82573:
699 if (!e1000_is_onboard_nvm_eeprom(hw)) {
700 udelay(10);
701 ctrl_ext = er32(CTRL_EXT);
702 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
703 ew32(CTRL_EXT, ctrl_ext);
704 E1000_WRITE_FLUSH();
705 }
706
707 default:
708
709 ret_val = e1000_get_auto_rd_done(hw);
710 if (ret_val)
711 return ret_val;
712 break;
713 }
714
715
716 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
717 manc = er32(MANC);
718 manc &= ~(E1000_MANC_ARP_EN);
719 ew32(MANC, manc);
720 }
721
722 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
723 e1000_phy_init_script(hw);
724
725
726 led_ctrl = er32(LEDCTL);
727 led_ctrl &= IGP_ACTIVITY_LED_MASK;
728 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
729 ew32(LEDCTL, led_ctrl);
730 }
731
732
733 DEBUGOUT("Masking off all interrupts\n");
734 ew32(IMC, 0xffffffff);
735
736
737 icr = er32(ICR);
738
739
740 if (hw->mac_type == e1000_82542_rev2_0) {
741 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
742 e1000_pci_set_mwi(hw);
743 }
744
745 if (hw->mac_type == e1000_ich8lan) {
746 u32 kab = er32(KABGTXD);
747 kab |= E1000_KABGTXD_BGSQLBIAS;
748 ew32(KABGTXD, kab);
749 }
750
751 return E1000_SUCCESS;
752}
753
754
755
756
757
758
759
760
761
762
763static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
764{
765 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
766
767 u32 reg_ctrl, reg_ctrl_ext;
768 u32 reg_tarc0, reg_tarc1;
769 u32 reg_tctl;
770 u32 reg_txdctl, reg_txdctl1;
771
772
773 reg_tarc0 = er32(TARC0);
774 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
775
776
777 reg_txdctl = er32(TXDCTL);
778 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
779 ew32(TXDCTL, reg_txdctl);
780 reg_txdctl1 = er32(TXDCTL1);
781 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
782 ew32(TXDCTL1, reg_txdctl1);
783
784 switch (hw->mac_type) {
785 case e1000_82571:
786 case e1000_82572:
787
788 reg_tarc1 = er32(TARC1);
789 reg_tarc1 &= ~((1 << 30)|(1 << 29));
790
791
792 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
793
794
795 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
796
797
798 reg_tctl = er32(TCTL);
799 if (reg_tctl & E1000_TCTL_MULR)
800 reg_tarc1 &= ~(1 << 28);
801 else
802 reg_tarc1 |= (1 << 28);
803
804 ew32(TARC1, reg_tarc1);
805 break;
806 case e1000_82573:
807 reg_ctrl_ext = er32(CTRL_EXT);
808 reg_ctrl_ext &= ~(1 << 23);
809 reg_ctrl_ext |= (1 << 22);
810
811
812 reg_ctrl = er32(CTRL);
813 reg_ctrl &= ~(1 << 29);
814
815 ew32(CTRL_EXT, reg_ctrl_ext);
816 ew32(CTRL, reg_ctrl);
817 break;
818 case e1000_80003es2lan:
819
820 if ((hw->media_type == e1000_media_type_fiber) ||
821 (hw->media_type == e1000_media_type_internal_serdes)) {
822 reg_tarc0 &= ~(1 << 20);
823 }
824
825
826 reg_tctl = er32(TCTL);
827 reg_tarc1 = er32(TARC1);
828 if (reg_tctl & E1000_TCTL_MULR)
829 reg_tarc1 &= ~(1 << 28);
830 else
831 reg_tarc1 |= (1 << 28);
832
833 ew32(TARC1, reg_tarc1);
834 break;
835 case e1000_ich8lan:
836
837 if ((hw->revision_id < 3) ||
838 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
839 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
840 reg_tarc0 |= ((1 << 29)|(1 << 28));
841
842 reg_ctrl_ext = er32(CTRL_EXT);
843 reg_ctrl_ext |= (1 << 22);
844 ew32(CTRL_EXT, reg_ctrl_ext);
845
846
847 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
848
849
850 reg_tctl = er32(TCTL);
851 reg_tarc1 = er32(TARC1);
852 if (reg_tctl & E1000_TCTL_MULR)
853 reg_tarc1 &= ~(1 << 28);
854 else
855 reg_tarc1 |= (1 << 28);
856
857
858 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
859
860 ew32(TARC1, reg_tarc1);
861 break;
862 default:
863 break;
864 }
865
866 ew32(TARC0, reg_tarc0);
867 }
868}
869
870
871
872
873
874
875
876
877
878
879
880
881s32 e1000_init_hw(struct e1000_hw *hw)
882{
883 u32 ctrl;
884 u32 i;
885 s32 ret_val;
886 u32 mta_size;
887 u32 reg_data;
888 u32 ctrl_ext;
889
890 DEBUGFUNC("e1000_init_hw");
891
892
893 if ((hw->mac_type == e1000_ich8lan) &&
894 ((hw->revision_id < 3) ||
895 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
896 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
897 reg_data = er32(STATUS);
898 reg_data &= ~0x80000000;
899 ew32(STATUS, reg_data);
900 }
901
902
903 ret_val = e1000_id_led_init(hw);
904 if (ret_val) {
905 DEBUGOUT("Error Initializing Identification LED\n");
906 return ret_val;
907 }
908
909
910 e1000_set_media_type(hw);
911
912
913 e1000_initialize_hardware_bits(hw);
914
915
916 DEBUGOUT("Initializing the IEEE VLAN\n");
917
918 if (hw->mac_type != e1000_ich8lan) {
919 if (hw->mac_type < e1000_82545_rev_3)
920 ew32(VET, 0);
921 e1000_clear_vfta(hw);
922 }
923
924
925 if (hw->mac_type == e1000_82542_rev2_0) {
926 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
927 e1000_pci_clear_mwi(hw);
928 ew32(RCTL, E1000_RCTL_RST);
929 E1000_WRITE_FLUSH();
930 msleep(5);
931 }
932
933
934
935
936 e1000_init_rx_addrs(hw);
937
938
939 if (hw->mac_type == e1000_82542_rev2_0) {
940 ew32(RCTL, 0);
941 E1000_WRITE_FLUSH();
942 msleep(1);
943 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
944 e1000_pci_set_mwi(hw);
945 }
946
947
948 DEBUGOUT("Zeroing the MTA\n");
949 mta_size = E1000_MC_TBL_SIZE;
950 if (hw->mac_type == e1000_ich8lan)
951 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
952 for (i = 0; i < mta_size; i++) {
953 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
954
955
956 E1000_WRITE_FLUSH();
957 }
958
959
960
961
962
963
964 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
965 ctrl = er32(CTRL);
966 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
967 }
968
969 switch (hw->mac_type) {
970 case e1000_82545_rev_3:
971 case e1000_82546_rev_3:
972 break;
973 default:
974
975 if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
976 e1000_pcix_set_mmrbc(hw, 2048);
977 break;
978 }
979
980
981 if (hw->mac_type == e1000_ich8lan)
982 msleep(15);
983
984
985 ret_val = e1000_setup_link(hw);
986
987
988 if (hw->mac_type > e1000_82544) {
989 ctrl = er32(TXDCTL);
990 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
991 ew32(TXDCTL, ctrl);
992 }
993
994 if (hw->mac_type == e1000_82573) {
995 e1000_enable_tx_pkt_filtering(hw);
996 }
997
998 switch (hw->mac_type) {
999 default:
1000 break;
1001 case e1000_80003es2lan:
1002
1003 reg_data = er32(TCTL);
1004 reg_data |= E1000_TCTL_RTLC;
1005 ew32(TCTL, reg_data);
1006
1007
1008 reg_data = er32(TCTL_EXT);
1009 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1010 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1011 ew32(TCTL_EXT, reg_data);
1012
1013
1014 reg_data = er32(TIPG);
1015 reg_data &= ~E1000_TIPG_IPGT_MASK;
1016 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1017 ew32(TIPG, reg_data);
1018
1019 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1020 reg_data &= ~0x00100000;
1021 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1022
1023 case e1000_82571:
1024 case e1000_82572:
1025 case e1000_ich8lan:
1026 ctrl = er32(TXDCTL1);
1027 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1028 ew32(TXDCTL1, ctrl);
1029 break;
1030 }
1031
1032
1033 if (hw->mac_type == e1000_82573) {
1034 u32 gcr = er32(GCR);
1035 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1036 ew32(GCR, gcr);
1037 }
1038
1039
1040
1041
1042
1043
1044 e1000_clear_hw_cntrs(hw);
1045
1046
1047
1048 if (hw->mac_type == e1000_ich8lan)
1049 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1050
1051 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1052 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1053 ctrl_ext = er32(CTRL_EXT);
1054
1055
1056 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1057 ew32(CTRL_EXT, ctrl_ext);
1058 }
1059
1060 return ret_val;
1061}
1062
1063
1064
1065
1066
1067
1068static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1069{
1070 u16 eeprom_data;
1071 s32 ret_val;
1072
1073 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1074
1075 if (hw->media_type != e1000_media_type_internal_serdes)
1076 return E1000_SUCCESS;
1077
1078 switch (hw->mac_type) {
1079 case e1000_82545_rev_3:
1080 case e1000_82546_rev_3:
1081 break;
1082 default:
1083 return E1000_SUCCESS;
1084 }
1085
1086 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1087 if (ret_val) {
1088 return ret_val;
1089 }
1090
1091 if (eeprom_data != EEPROM_RESERVED_WORD) {
1092
1093 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1094 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1095 if (ret_val)
1096 return ret_val;
1097 }
1098
1099 return E1000_SUCCESS;
1100}
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113s32 e1000_setup_link(struct e1000_hw *hw)
1114{
1115 u32 ctrl_ext;
1116 s32 ret_val;
1117 u16 eeprom_data;
1118
1119 DEBUGFUNC("e1000_setup_link");
1120
1121
1122
1123 if (e1000_check_phy_reset_block(hw))
1124 return E1000_SUCCESS;
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134 if (hw->fc == E1000_FC_DEFAULT) {
1135 switch (hw->mac_type) {
1136 case e1000_ich8lan:
1137 case e1000_82573:
1138 hw->fc = E1000_FC_FULL;
1139 break;
1140 default:
1141 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1142 1, &eeprom_data);
1143 if (ret_val) {
1144 DEBUGOUT("EEPROM Read Error\n");
1145 return -E1000_ERR_EEPROM;
1146 }
1147 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1148 hw->fc = E1000_FC_NONE;
1149 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1150 EEPROM_WORD0F_ASM_DIR)
1151 hw->fc = E1000_FC_TX_PAUSE;
1152 else
1153 hw->fc = E1000_FC_FULL;
1154 break;
1155 }
1156 }
1157
1158
1159
1160
1161
1162 if (hw->mac_type == e1000_82542_rev2_0)
1163 hw->fc &= (~E1000_FC_TX_PAUSE);
1164
1165 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1166 hw->fc &= (~E1000_FC_RX_PAUSE);
1167
1168 hw->original_fc = hw->fc;
1169
1170 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1171
1172
1173
1174
1175
1176
1177
1178
1179 if (hw->mac_type == e1000_82543) {
1180 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1181 1, &eeprom_data);
1182 if (ret_val) {
1183 DEBUGOUT("EEPROM Read Error\n");
1184 return -E1000_ERR_EEPROM;
1185 }
1186 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1187 SWDPIO__EXT_SHIFT);
1188 ew32(CTRL_EXT, ctrl_ext);
1189 }
1190
1191
1192 ret_val = (hw->media_type == e1000_media_type_copper) ?
1193 e1000_setup_copper_link(hw) :
1194 e1000_setup_fiber_serdes_link(hw);
1195
1196
1197
1198
1199
1200
1201 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1202
1203
1204 if (hw->mac_type != e1000_ich8lan) {
1205 ew32(FCT, FLOW_CONTROL_TYPE);
1206 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1207 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1208 }
1209
1210 ew32(FCTTV, hw->fc_pause_time);
1211
1212
1213
1214
1215
1216
1217
1218 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1219 ew32(FCRTL, 0);
1220 ew32(FCRTH, 0);
1221 } else {
1222
1223
1224
1225 if (hw->fc_send_xon) {
1226 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1227 ew32(FCRTH, hw->fc_high_water);
1228 } else {
1229 ew32(FCRTL, hw->fc_low_water);
1230 ew32(FCRTH, hw->fc_high_water);
1231 }
1232 }
1233 return ret_val;
1234}
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1246{
1247 u32 ctrl;
1248 u32 status;
1249 u32 txcw = 0;
1250 u32 i;
1251 u32 signal = 0;
1252 s32 ret_val;
1253
1254 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1255
1256
1257
1258
1259
1260
1261 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1262 ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1263
1264
1265
1266
1267
1268
1269
1270 ctrl = er32(CTRL);
1271 if (hw->media_type == e1000_media_type_fiber)
1272 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1273
1274 ret_val = e1000_adjust_serdes_amplitude(hw);
1275 if (ret_val)
1276 return ret_val;
1277
1278
1279 ctrl &= ~(E1000_CTRL_LRST);
1280
1281
1282 ret_val = e1000_set_vco_speed(hw);
1283 if (ret_val)
1284 return ret_val;
1285
1286 e1000_config_collision_dist(hw);
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303 switch (hw->fc) {
1304 case E1000_FC_NONE:
1305
1306 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1307 break;
1308 case E1000_FC_RX_PAUSE:
1309
1310
1311
1312
1313
1314
1315 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1316 break;
1317 case E1000_FC_TX_PAUSE:
1318
1319
1320
1321 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1322 break;
1323 case E1000_FC_FULL:
1324
1325 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1326 break;
1327 default:
1328 DEBUGOUT("Flow control param set incorrectly\n");
1329 return -E1000_ERR_CONFIG;
1330 break;
1331 }
1332
1333
1334
1335
1336
1337
1338
1339 DEBUGOUT("Auto-negotiation enabled\n");
1340
1341 ew32(TXCW, txcw);
1342 ew32(CTRL, ctrl);
1343 E1000_WRITE_FLUSH();
1344
1345 hw->txcw = txcw;
1346 msleep(1);
1347
1348
1349
1350
1351
1352
1353
1354 if (hw->media_type == e1000_media_type_internal_serdes ||
1355 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1356 DEBUGOUT("Looking for Link\n");
1357 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1358 msleep(10);
1359 status = er32(STATUS);
1360 if (status & E1000_STATUS_LU) break;
1361 }
1362 if (i == (LINK_UP_TIMEOUT / 10)) {
1363 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1364 hw->autoneg_failed = 1;
1365
1366
1367
1368
1369
1370 ret_val = e1000_check_for_link(hw);
1371 if (ret_val) {
1372 DEBUGOUT("Error while checking for link\n");
1373 return ret_val;
1374 }
1375 hw->autoneg_failed = 0;
1376 } else {
1377 hw->autoneg_failed = 0;
1378 DEBUGOUT("Valid Link Found\n");
1379 }
1380 } else {
1381 DEBUGOUT("No Signal Detected\n");
1382 }
1383 return E1000_SUCCESS;
1384}
1385
1386
1387
1388
1389
1390
1391static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1392{
1393 u32 ctrl;
1394 s32 ret_val;
1395 u16 phy_data;
1396
1397 DEBUGFUNC("e1000_copper_link_preconfig");
1398
1399 ctrl = er32(CTRL);
1400
1401
1402
1403
1404 if (hw->mac_type > e1000_82543) {
1405 ctrl |= E1000_CTRL_SLU;
1406 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1407 ew32(CTRL, ctrl);
1408 } else {
1409 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1410 ew32(CTRL, ctrl);
1411 ret_val = e1000_phy_hw_reset(hw);
1412 if (ret_val)
1413 return ret_val;
1414 }
1415
1416
1417 ret_val = e1000_detect_gig_phy(hw);
1418 if (ret_val) {
1419 DEBUGOUT("Error, did not detect valid phy.\n");
1420 return ret_val;
1421 }
1422 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1423
1424
1425 ret_val = e1000_set_phy_mode(hw);
1426 if (ret_val)
1427 return ret_val;
1428
1429 if ((hw->mac_type == e1000_82545_rev_3) ||
1430 (hw->mac_type == e1000_82546_rev_3)) {
1431 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1432 phy_data |= 0x00000008;
1433 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1434 }
1435
1436 if (hw->mac_type <= e1000_82543 ||
1437 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1438 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1439 hw->phy_reset_disable = false;
1440
1441 return E1000_SUCCESS;
1442}
1443
1444
1445
1446
1447
1448
1449
1450static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1451{
1452 u32 led_ctrl;
1453 s32 ret_val;
1454 u16 phy_data;
1455
1456 DEBUGFUNC("e1000_copper_link_igp_setup");
1457
1458 if (hw->phy_reset_disable)
1459 return E1000_SUCCESS;
1460
1461 ret_val = e1000_phy_reset(hw);
1462 if (ret_val) {
1463 DEBUGOUT("Error Resetting the PHY\n");
1464 return ret_val;
1465 }
1466
1467
1468 msleep(15);
1469 if (hw->mac_type != e1000_ich8lan) {
1470
1471 led_ctrl = er32(LEDCTL);
1472 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1473 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1474 ew32(LEDCTL, led_ctrl);
1475 }
1476
1477
1478 if (hw->phy_type == e1000_phy_igp) {
1479
1480 ret_val = e1000_set_d3_lplu_state(hw, false);
1481 if (ret_val) {
1482 DEBUGOUT("Error Disabling LPLU D3\n");
1483 return ret_val;
1484 }
1485 }
1486
1487
1488 ret_val = e1000_set_d0_lplu_state(hw, false);
1489 if (ret_val) {
1490 DEBUGOUT("Error Disabling LPLU D0\n");
1491 return ret_val;
1492 }
1493
1494 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1495 if (ret_val)
1496 return ret_val;
1497
1498 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1499 hw->dsp_config_state = e1000_dsp_config_disabled;
1500
1501 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1502 hw->mdix = 1;
1503
1504 } else {
1505 hw->dsp_config_state = e1000_dsp_config_enabled;
1506 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1507
1508 switch (hw->mdix) {
1509 case 1:
1510 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1511 break;
1512 case 2:
1513 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1514 break;
1515 case 0:
1516 default:
1517 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1518 break;
1519 }
1520 }
1521 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1522 if (ret_val)
1523 return ret_val;
1524
1525
1526 if (hw->autoneg) {
1527 e1000_ms_type phy_ms_setting = hw->master_slave;
1528
1529 if (hw->ffe_config_state == e1000_ffe_config_active)
1530 hw->ffe_config_state = e1000_ffe_config_enabled;
1531
1532 if (hw->dsp_config_state == e1000_dsp_config_activated)
1533 hw->dsp_config_state = e1000_dsp_config_enabled;
1534
1535
1536
1537
1538 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1539
1540 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1541 &phy_data);
1542 if (ret_val)
1543 return ret_val;
1544 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1545 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1546 phy_data);
1547 if (ret_val)
1548 return ret_val;
1549
1550 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1551 if (ret_val)
1552 return ret_val;
1553 phy_data &= ~CR_1000T_MS_ENABLE;
1554 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1555 if (ret_val)
1556 return ret_val;
1557 }
1558
1559 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1560 if (ret_val)
1561 return ret_val;
1562
1563
1564 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1565 ((phy_data & CR_1000T_MS_VALUE) ?
1566 e1000_ms_force_master :
1567 e1000_ms_force_slave) :
1568 e1000_ms_auto;
1569
1570 switch (phy_ms_setting) {
1571 case e1000_ms_force_master:
1572 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1573 break;
1574 case e1000_ms_force_slave:
1575 phy_data |= CR_1000T_MS_ENABLE;
1576 phy_data &= ~(CR_1000T_MS_VALUE);
1577 break;
1578 case e1000_ms_auto:
1579 phy_data &= ~CR_1000T_MS_ENABLE;
1580 default:
1581 break;
1582 }
1583 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1584 if (ret_val)
1585 return ret_val;
1586 }
1587
1588 return E1000_SUCCESS;
1589}
1590
1591
1592
1593
1594
1595
1596static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1597{
1598 s32 ret_val;
1599 u16 phy_data;
1600 u32 reg_data;
1601
1602 DEBUGFUNC("e1000_copper_link_ggp_setup");
1603
1604 if (!hw->phy_reset_disable) {
1605
1606
1607 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1608 &phy_data);
1609 if (ret_val)
1610 return ret_val;
1611
1612 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1613
1614 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1615
1616 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1617 phy_data);
1618 if (ret_val)
1619 return ret_val;
1620
1621
1622
1623
1624
1625
1626
1627
1628 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1629 if (ret_val)
1630 return ret_val;
1631
1632 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1633
1634 switch (hw->mdix) {
1635 case 1:
1636 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1637 break;
1638 case 2:
1639 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1640 break;
1641 case 0:
1642 default:
1643 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1644 break;
1645 }
1646
1647
1648
1649
1650
1651
1652
1653 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1654 if (hw->disable_polarity_correction == 1)
1655 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1656 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1657
1658 if (ret_val)
1659 return ret_val;
1660
1661
1662 ret_val = e1000_phy_reset(hw);
1663 if (ret_val) {
1664 DEBUGOUT("Error Resetting the PHY\n");
1665 return ret_val;
1666 }
1667 }
1668
1669 if (hw->mac_type == e1000_80003es2lan) {
1670
1671 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1672 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1673 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1674 if (ret_val)
1675 return ret_val;
1676
1677 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1678 if (ret_val)
1679 return ret_val;
1680
1681 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1682 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1683
1684 if (ret_val)
1685 return ret_val;
1686
1687 reg_data = er32(CTRL_EXT);
1688 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1689 ew32(CTRL_EXT, reg_data);
1690
1691 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1692 &phy_data);
1693 if (ret_val)
1694 return ret_val;
1695
1696
1697
1698
1699
1700 if (!e1000_check_mng_mode(hw)) {
1701
1702 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1703 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1704 phy_data);
1705 if (ret_val)
1706 return ret_val;
1707
1708 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1709 &phy_data);
1710 if (ret_val)
1711 return ret_val;
1712
1713 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1714 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1715 phy_data);
1716
1717 if (ret_val)
1718 return ret_val;
1719 }
1720
1721
1722
1723
1724 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1725 &phy_data);
1726 if (ret_val)
1727 return ret_val;
1728 phy_data |= GG82563_ICR_DIS_PADDING;
1729 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1730 phy_data);
1731 if (ret_val)
1732 return ret_val;
1733 }
1734
1735 return E1000_SUCCESS;
1736}
1737
1738
1739
1740
1741
1742
1743static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1744{
1745 s32 ret_val;
1746 u16 phy_data;
1747
1748 DEBUGFUNC("e1000_copper_link_mgp_setup");
1749
1750 if (hw->phy_reset_disable)
1751 return E1000_SUCCESS;
1752
1753
1754 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1755 if (ret_val)
1756 return ret_val;
1757
1758 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1759
1760
1761
1762
1763
1764
1765
1766
1767 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1768
1769 switch (hw->mdix) {
1770 case 1:
1771 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1772 break;
1773 case 2:
1774 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1775 break;
1776 case 3:
1777 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1778 break;
1779 case 0:
1780 default:
1781 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1782 break;
1783 }
1784
1785
1786
1787
1788
1789
1790
1791 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1792 if (hw->disable_polarity_correction == 1)
1793 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1794 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1795 if (ret_val)
1796 return ret_val;
1797
1798 if (hw->phy_revision < M88E1011_I_REV_4) {
1799
1800
1801
1802 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1803 if (ret_val)
1804 return ret_val;
1805
1806 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1807
1808 if ((hw->phy_revision == E1000_REVISION_2) &&
1809 (hw->phy_id == M88E1111_I_PHY_ID)) {
1810
1811 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1812 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1813 ret_val = e1000_write_phy_reg(hw,
1814 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1815 if (ret_val)
1816 return ret_val;
1817 } else {
1818
1819 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1820 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1821 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1822 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1823 ret_val = e1000_write_phy_reg(hw,
1824 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1825 if (ret_val)
1826 return ret_val;
1827 }
1828 }
1829
1830
1831 ret_val = e1000_phy_reset(hw);
1832 if (ret_val) {
1833 DEBUGOUT("Error Resetting the PHY\n");
1834 return ret_val;
1835 }
1836
1837 return E1000_SUCCESS;
1838}
1839
1840
1841
1842
1843
1844
1845
1846static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1847{
1848 s32 ret_val;
1849 u16 phy_data;
1850
1851 DEBUGFUNC("e1000_copper_link_autoneg");
1852
1853
1854
1855
1856 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1857
1858
1859
1860
1861 if (hw->autoneg_advertised == 0)
1862 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1863
1864
1865 if (hw->phy_type == e1000_phy_ife)
1866 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1867
1868 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1869 ret_val = e1000_phy_setup_autoneg(hw);
1870 if (ret_val) {
1871 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1872 return ret_val;
1873 }
1874 DEBUGOUT("Restarting Auto-Neg\n");
1875
1876
1877
1878
1879 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1880 if (ret_val)
1881 return ret_val;
1882
1883 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1884 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1885 if (ret_val)
1886 return ret_val;
1887
1888
1889
1890
1891 if (hw->wait_autoneg_complete) {
1892 ret_val = e1000_wait_autoneg(hw);
1893 if (ret_val) {
1894 DEBUGOUT("Error while waiting for autoneg to complete\n");
1895 return ret_val;
1896 }
1897 }
1898
1899 hw->get_link_status = true;
1900
1901 return E1000_SUCCESS;
1902}
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1917{
1918 s32 ret_val;
1919 DEBUGFUNC("e1000_copper_link_postconfig");
1920
1921 if (hw->mac_type >= e1000_82544) {
1922 e1000_config_collision_dist(hw);
1923 } else {
1924 ret_val = e1000_config_mac_to_phy(hw);
1925 if (ret_val) {
1926 DEBUGOUT("Error configuring MAC to PHY settings\n");
1927 return ret_val;
1928 }
1929 }
1930 ret_val = e1000_config_fc_after_link_up(hw);
1931 if (ret_val) {
1932 DEBUGOUT("Error Configuring Flow Control\n");
1933 return ret_val;
1934 }
1935
1936
1937 if (hw->phy_type == e1000_phy_igp) {
1938 ret_val = e1000_config_dsp_after_link_change(hw, true);
1939 if (ret_val) {
1940 DEBUGOUT("Error Configuring DSP after link up\n");
1941 return ret_val;
1942 }
1943 }
1944
1945 return E1000_SUCCESS;
1946}
1947
1948
1949
1950
1951
1952
1953static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1954{
1955 s32 ret_val;
1956 u16 i;
1957 u16 phy_data;
1958 u16 reg_data;
1959
1960 DEBUGFUNC("e1000_setup_copper_link");
1961
1962 switch (hw->mac_type) {
1963 case e1000_80003es2lan:
1964 case e1000_ich8lan:
1965
1966
1967
1968 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1969 if (ret_val)
1970 return ret_val;
1971 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1972 if (ret_val)
1973 return ret_val;
1974 reg_data |= 0x3F;
1975 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1976 if (ret_val)
1977 return ret_val;
1978 default:
1979 break;
1980 }
1981
1982
1983 ret_val = e1000_copper_link_preconfig(hw);
1984 if (ret_val)
1985 return ret_val;
1986
1987 switch (hw->mac_type) {
1988 case e1000_80003es2lan:
1989
1990 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1991 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1992 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1993 reg_data);
1994 if (ret_val)
1995 return ret_val;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 if (hw->phy_type == e1000_phy_igp ||
2002 hw->phy_type == e1000_phy_igp_3 ||
2003 hw->phy_type == e1000_phy_igp_2) {
2004 ret_val = e1000_copper_link_igp_setup(hw);
2005 if (ret_val)
2006 return ret_val;
2007 } else if (hw->phy_type == e1000_phy_m88) {
2008 ret_val = e1000_copper_link_mgp_setup(hw);
2009 if (ret_val)
2010 return ret_val;
2011 } else if (hw->phy_type == e1000_phy_gg82563) {
2012 ret_val = e1000_copper_link_ggp_setup(hw);
2013 if (ret_val)
2014 return ret_val;
2015 }
2016
2017 if (hw->autoneg) {
2018
2019
2020 ret_val = e1000_copper_link_autoneg(hw);
2021 if (ret_val)
2022 return ret_val;
2023 } else {
2024
2025
2026 DEBUGOUT("Forcing speed and duplex\n");
2027 ret_val = e1000_phy_force_speed_duplex(hw);
2028 if (ret_val) {
2029 DEBUGOUT("Error Forcing Speed and Duplex\n");
2030 return ret_val;
2031 }
2032 }
2033
2034
2035
2036
2037 for (i = 0; i < 10; i++) {
2038 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2039 if (ret_val)
2040 return ret_val;
2041 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2042 if (ret_val)
2043 return ret_val;
2044
2045 if (phy_data & MII_SR_LINK_STATUS) {
2046
2047 ret_val = e1000_copper_link_postconfig(hw);
2048 if (ret_val)
2049 return ret_val;
2050
2051 DEBUGOUT("Valid link established!!!\n");
2052 return E1000_SUCCESS;
2053 }
2054 udelay(10);
2055 }
2056
2057 DEBUGOUT("Unable to establish link!!!\n");
2058 return E1000_SUCCESS;
2059}
2060
2061
2062
2063
2064
2065
2066static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2067{
2068 s32 ret_val = E1000_SUCCESS;
2069 u32 tipg;
2070 u16 reg_data;
2071
2072 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2073
2074 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2075 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2076 reg_data);
2077 if (ret_val)
2078 return ret_val;
2079
2080
2081 tipg = er32(TIPG);
2082 tipg &= ~E1000_TIPG_IPGT_MASK;
2083 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2084 ew32(TIPG, tipg);
2085
2086 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2087
2088 if (ret_val)
2089 return ret_val;
2090
2091 if (duplex == HALF_DUPLEX)
2092 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2093 else
2094 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2095
2096 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2097
2098 return ret_val;
2099}
2100
2101static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2102{
2103 s32 ret_val = E1000_SUCCESS;
2104 u16 reg_data;
2105 u32 tipg;
2106
2107 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2108
2109 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2110 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2111 reg_data);
2112 if (ret_val)
2113 return ret_val;
2114
2115
2116 tipg = er32(TIPG);
2117 tipg &= ~E1000_TIPG_IPGT_MASK;
2118 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2119 ew32(TIPG, tipg);
2120
2121 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2122
2123 if (ret_val)
2124 return ret_val;
2125
2126 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2127 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2128
2129 return ret_val;
2130}
2131
2132
2133
2134
2135
2136
2137s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2138{
2139 s32 ret_val;
2140 u16 mii_autoneg_adv_reg;
2141 u16 mii_1000t_ctrl_reg;
2142
2143 DEBUGFUNC("e1000_phy_setup_autoneg");
2144
2145
2146 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2147 if (ret_val)
2148 return ret_val;
2149
2150 if (hw->phy_type != e1000_phy_ife) {
2151
2152 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2153 if (ret_val)
2154 return ret_val;
2155 } else
2156 mii_1000t_ctrl_reg=0;
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2170 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2171
2172 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2173
2174
2175 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2176 DEBUGOUT("Advertise 10mb Half duplex\n");
2177 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2178 }
2179
2180
2181 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2182 DEBUGOUT("Advertise 10mb Full duplex\n");
2183 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2184 }
2185
2186
2187 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2188 DEBUGOUT("Advertise 100mb Half duplex\n");
2189 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2190 }
2191
2192
2193 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2194 DEBUGOUT("Advertise 100mb Full duplex\n");
2195 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2196 }
2197
2198
2199 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2200 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2201 }
2202
2203
2204 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2205 DEBUGOUT("Advertise 1000mb Full duplex\n");
2206 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2207 if (hw->phy_type == e1000_phy_ife) {
2208 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2209 }
2210 }
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228 switch (hw->fc) {
2229 case E1000_FC_NONE:
2230
2231
2232
2233 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2234 break;
2235 case E1000_FC_RX_PAUSE:
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2246 break;
2247 case E1000_FC_TX_PAUSE:
2248
2249
2250
2251 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2252 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2253 break;
2254 case E1000_FC_FULL:
2255
2256
2257
2258 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2259 break;
2260 default:
2261 DEBUGOUT("Flow control param set incorrectly\n");
2262 return -E1000_ERR_CONFIG;
2263 }
2264
2265 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2266 if (ret_val)
2267 return ret_val;
2268
2269 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2270
2271 if (hw->phy_type != e1000_phy_ife) {
2272 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2273 if (ret_val)
2274 return ret_val;
2275 }
2276
2277 return E1000_SUCCESS;
2278}
2279
2280
2281
2282
2283
2284
2285static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2286{
2287 u32 ctrl;
2288 s32 ret_val;
2289 u16 mii_ctrl_reg;
2290 u16 mii_status_reg;
2291 u16 phy_data;
2292 u16 i;
2293
2294 DEBUGFUNC("e1000_phy_force_speed_duplex");
2295
2296
2297 hw->fc = E1000_FC_NONE;
2298
2299 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2300
2301
2302 ctrl = er32(CTRL);
2303
2304
2305 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2306 ctrl &= ~(DEVICE_SPEED_MASK);
2307
2308
2309 ctrl &= ~E1000_CTRL_ASDE;
2310
2311
2312 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2313 if (ret_val)
2314 return ret_val;
2315
2316
2317
2318 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2319
2320
2321 if (hw->forced_speed_duplex == e1000_100_full ||
2322 hw->forced_speed_duplex == e1000_10_full) {
2323
2324
2325
2326 ctrl |= E1000_CTRL_FD;
2327 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2328 DEBUGOUT("Full Duplex\n");
2329 } else {
2330
2331
2332
2333 ctrl &= ~E1000_CTRL_FD;
2334 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2335 DEBUGOUT("Half Duplex\n");
2336 }
2337
2338
2339 if (hw->forced_speed_duplex == e1000_100_full ||
2340 hw->forced_speed_duplex == e1000_100_half) {
2341
2342 ctrl |= E1000_CTRL_SPD_100;
2343 mii_ctrl_reg |= MII_CR_SPEED_100;
2344 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2345 DEBUGOUT("Forcing 100mb ");
2346 } else {
2347
2348 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2349 mii_ctrl_reg |= MII_CR_SPEED_10;
2350 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2351 DEBUGOUT("Forcing 10mb ");
2352 }
2353
2354 e1000_config_collision_dist(hw);
2355
2356
2357 ew32(CTRL, ctrl);
2358
2359 if ((hw->phy_type == e1000_phy_m88) ||
2360 (hw->phy_type == e1000_phy_gg82563)) {
2361 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2362 if (ret_val)
2363 return ret_val;
2364
2365
2366
2367
2368 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2369 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2370 if (ret_val)
2371 return ret_val;
2372
2373 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2374
2375
2376 mii_ctrl_reg |= MII_CR_RESET;
2377
2378
2379 } else if (hw->phy_type == e1000_phy_ife) {
2380 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2381 if (ret_val)
2382 return ret_val;
2383
2384 phy_data &= ~IFE_PMC_AUTO_MDIX;
2385 phy_data &= ~IFE_PMC_FORCE_MDIX;
2386
2387 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2388 if (ret_val)
2389 return ret_val;
2390
2391 } else {
2392
2393
2394
2395 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2396 if (ret_val)
2397 return ret_val;
2398
2399 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2400 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2401
2402 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2403 if (ret_val)
2404 return ret_val;
2405 }
2406
2407
2408 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2409 if (ret_val)
2410 return ret_val;
2411
2412 udelay(1);
2413
2414
2415
2416
2417
2418
2419
2420
2421 if (hw->wait_autoneg_complete) {
2422
2423 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2424 mii_status_reg = 0;
2425
2426
2427 for (i = PHY_FORCE_TIME; i > 0; i--) {
2428
2429
2430
2431 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2432 if (ret_val)
2433 return ret_val;
2434
2435 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2436 if (ret_val)
2437 return ret_val;
2438
2439 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2440 msleep(100);
2441 }
2442 if ((i == 0) &&
2443 ((hw->phy_type == e1000_phy_m88) ||
2444 (hw->phy_type == e1000_phy_gg82563))) {
2445
2446 ret_val = e1000_phy_reset_dsp(hw);
2447 if (ret_val) {
2448 DEBUGOUT("Error Resetting PHY DSP\n");
2449 return ret_val;
2450 }
2451 }
2452
2453 for (i = PHY_FORCE_TIME; i > 0; i--) {
2454 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2455 msleep(100);
2456
2457
2458
2459 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2460 if (ret_val)
2461 return ret_val;
2462
2463 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2464 if (ret_val)
2465 return ret_val;
2466 }
2467 }
2468
2469 if (hw->phy_type == e1000_phy_m88) {
2470
2471
2472
2473
2474 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2475 if (ret_val)
2476 return ret_val;
2477
2478 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2479 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2480 if (ret_val)
2481 return ret_val;
2482
2483
2484
2485
2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2487 if (ret_val)
2488 return ret_val;
2489
2490 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2491 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2492 if (ret_val)
2493 return ret_val;
2494
2495 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2496 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2497 hw->forced_speed_duplex == e1000_10_half)) {
2498 ret_val = e1000_polarity_reversal_workaround(hw);
2499 if (ret_val)
2500 return ret_val;
2501 }
2502 } else if (hw->phy_type == e1000_phy_gg82563) {
2503
2504
2505
2506 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2507 if (ret_val)
2508 return ret_val;
2509
2510 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2511 if ((hw->forced_speed_duplex == e1000_10_full) ||
2512 (hw->forced_speed_duplex == e1000_10_half))
2513 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2514 else
2515 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2516
2517
2518 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2519
2520 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2521 if (ret_val)
2522 return ret_val;
2523 }
2524 return E1000_SUCCESS;
2525}
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535void e1000_config_collision_dist(struct e1000_hw *hw)
2536{
2537 u32 tctl, coll_dist;
2538
2539 DEBUGFUNC("e1000_config_collision_dist");
2540
2541 if (hw->mac_type < e1000_82543)
2542 coll_dist = E1000_COLLISION_DISTANCE_82542;
2543 else
2544 coll_dist = E1000_COLLISION_DISTANCE;
2545
2546 tctl = er32(TCTL);
2547
2548 tctl &= ~E1000_TCTL_COLD;
2549 tctl |= coll_dist << E1000_COLD_SHIFT;
2550
2551 ew32(TCTL, tctl);
2552 E1000_WRITE_FLUSH();
2553}
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
2565{
2566 u32 ctrl;
2567 s32 ret_val;
2568 u16 phy_data;
2569
2570 DEBUGFUNC("e1000_config_mac_to_phy");
2571
2572
2573
2574 if (hw->mac_type >= e1000_82544)
2575 return E1000_SUCCESS;
2576
2577
2578
2579
2580 ctrl = er32(CTRL);
2581 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2582 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2583
2584
2585
2586
2587 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2588 if (ret_val)
2589 return ret_val;
2590
2591 if (phy_data & M88E1000_PSSR_DPLX)
2592 ctrl |= E1000_CTRL_FD;
2593 else
2594 ctrl &= ~E1000_CTRL_FD;
2595
2596 e1000_config_collision_dist(hw);
2597
2598
2599
2600
2601 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2602 ctrl |= E1000_CTRL_SPD_1000;
2603 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2604 ctrl |= E1000_CTRL_SPD_100;
2605
2606
2607 ew32(CTRL, ctrl);
2608 return E1000_SUCCESS;
2609}
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622s32 e1000_force_mac_fc(struct e1000_hw *hw)
2623{
2624 u32 ctrl;
2625
2626 DEBUGFUNC("e1000_force_mac_fc");
2627
2628
2629 ctrl = er32(CTRL);
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649 switch (hw->fc) {
2650 case E1000_FC_NONE:
2651 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2652 break;
2653 case E1000_FC_RX_PAUSE:
2654 ctrl &= (~E1000_CTRL_TFCE);
2655 ctrl |= E1000_CTRL_RFCE;
2656 break;
2657 case E1000_FC_TX_PAUSE:
2658 ctrl &= (~E1000_CTRL_RFCE);
2659 ctrl |= E1000_CTRL_TFCE;
2660 break;
2661 case E1000_FC_FULL:
2662 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2663 break;
2664 default:
2665 DEBUGOUT("Flow control param set incorrectly\n");
2666 return -E1000_ERR_CONFIG;
2667 }
2668
2669
2670 if (hw->mac_type == e1000_82542_rev2_0)
2671 ctrl &= (~E1000_CTRL_TFCE);
2672
2673 ew32(CTRL, ctrl);
2674 return E1000_SUCCESS;
2675}
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2689{
2690 s32 ret_val;
2691 u16 mii_status_reg;
2692 u16 mii_nway_adv_reg;
2693 u16 mii_nway_lp_ability_reg;
2694 u16 speed;
2695 u16 duplex;
2696
2697 DEBUGFUNC("e1000_config_fc_after_link_up");
2698
2699
2700
2701
2702
2703 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2704 ((hw->media_type == e1000_media_type_internal_serdes) &&
2705 (hw->autoneg_failed)) ||
2706 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2707 ret_val = e1000_force_mac_fc(hw);
2708 if (ret_val) {
2709 DEBUGOUT("Error forcing flow control settings\n");
2710 return ret_val;
2711 }
2712 }
2713
2714
2715
2716
2717
2718
2719 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2720
2721
2722
2723
2724 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2725 if (ret_val)
2726 return ret_val;
2727 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2728 if (ret_val)
2729 return ret_val;
2730
2731 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2732
2733
2734
2735
2736
2737
2738 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2739 &mii_nway_adv_reg);
2740 if (ret_val)
2741 return ret_val;
2742 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2743 &mii_nway_lp_ability_reg);
2744 if (ret_val)
2745 return ret_val;
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2782 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2783
2784
2785
2786
2787
2788
2789 if (hw->original_fc == E1000_FC_FULL) {
2790 hw->fc = E1000_FC_FULL;
2791 DEBUGOUT("Flow Control = FULL.\n");
2792 } else {
2793 hw->fc = E1000_FC_RX_PAUSE;
2794 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2795 }
2796 }
2797
2798
2799
2800
2801
2802
2803
2804
2805 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2806 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2807 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2808 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2809 hw->fc = E1000_FC_TX_PAUSE;
2810 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2811 }
2812
2813
2814
2815
2816
2817
2818
2819
2820 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2821 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2822 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2823 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2824 hw->fc = E1000_FC_RX_PAUSE;
2825 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2826 }
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847 else if ((hw->original_fc == E1000_FC_NONE ||
2848 hw->original_fc == E1000_FC_TX_PAUSE) ||
2849 hw->fc_strict_ieee) {
2850 hw->fc = E1000_FC_NONE;
2851 DEBUGOUT("Flow Control = NONE.\n");
2852 } else {
2853 hw->fc = E1000_FC_RX_PAUSE;
2854 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2855 }
2856
2857
2858
2859
2860
2861 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2862 if (ret_val) {
2863 DEBUGOUT("Error getting link speed and duplex\n");
2864 return ret_val;
2865 }
2866
2867 if (duplex == HALF_DUPLEX)
2868 hw->fc = E1000_FC_NONE;
2869
2870
2871
2872
2873 ret_val = e1000_force_mac_fc(hw);
2874 if (ret_val) {
2875 DEBUGOUT("Error forcing flow control settings\n");
2876 return ret_val;
2877 }
2878 } else {
2879 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2880 }
2881 }
2882 return E1000_SUCCESS;
2883}
2884
2885
2886
2887
2888
2889
2890
2891
2892s32 e1000_check_for_link(struct e1000_hw *hw)
2893{
2894 u32 rxcw = 0;
2895 u32 ctrl;
2896 u32 status;
2897 u32 rctl;
2898 u32 icr;
2899 u32 signal = 0;
2900 s32 ret_val;
2901 u16 phy_data;
2902
2903 DEBUGFUNC("e1000_check_for_link");
2904
2905 ctrl = er32(CTRL);
2906 status = er32(STATUS);
2907
2908
2909
2910
2911
2912 if ((hw->media_type == e1000_media_type_fiber) ||
2913 (hw->media_type == e1000_media_type_internal_serdes)) {
2914 rxcw = er32(RXCW);
2915
2916 if (hw->media_type == e1000_media_type_fiber) {
2917 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2918 if (status & E1000_STATUS_LU)
2919 hw->get_link_status = false;
2920 }
2921 }
2922
2923
2924
2925
2926
2927
2928
2929 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2930
2931
2932
2933
2934
2935 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2936 if (ret_val)
2937 return ret_val;
2938 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2939 if (ret_val)
2940 return ret_val;
2941
2942 if (phy_data & MII_SR_LINK_STATUS) {
2943 hw->get_link_status = false;
2944
2945
2946 e1000_check_downshift(hw);
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2957 (!hw->autoneg) &&
2958 (hw->forced_speed_duplex == e1000_10_full ||
2959 hw->forced_speed_duplex == e1000_10_half)) {
2960 ew32(IMC, 0xffffffff);
2961 ret_val = e1000_polarity_reversal_workaround(hw);
2962 icr = er32(ICR);
2963 ew32(ICS, (icr & ~E1000_ICS_LSC));
2964 ew32(IMS, IMS_ENABLE_MASK);
2965 }
2966
2967 } else {
2968
2969 e1000_config_dsp_after_link_change(hw, false);
2970 return 0;
2971 }
2972
2973
2974
2975
2976 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2977
2978
2979 e1000_config_dsp_after_link_change(hw, true);
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989 if (hw->mac_type >= e1000_82544)
2990 e1000_config_collision_dist(hw);
2991 else {
2992 ret_val = e1000_config_mac_to_phy(hw);
2993 if (ret_val) {
2994 DEBUGOUT("Error configuring MAC to PHY settings\n");
2995 return ret_val;
2996 }
2997 }
2998
2999
3000
3001
3002
3003 ret_val = e1000_config_fc_after_link_up(hw);
3004 if (ret_val) {
3005 DEBUGOUT("Error configuring flow control\n");
3006 return ret_val;
3007 }
3008
3009
3010
3011
3012
3013
3014
3015
3016 if (hw->tbi_compatibility_en) {
3017 u16 speed, duplex;
3018 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3019 if (ret_val) {
3020 DEBUGOUT("Error getting link speed and duplex\n");
3021 return ret_val;
3022 }
3023 if (speed != SPEED_1000) {
3024
3025
3026
3027 if (hw->tbi_compatibility_on) {
3028
3029 rctl = er32(RCTL);
3030 rctl &= ~E1000_RCTL_SBP;
3031 ew32(RCTL, rctl);
3032 hw->tbi_compatibility_on = false;
3033 }
3034 } else {
3035
3036
3037
3038
3039
3040 if (!hw->tbi_compatibility_on) {
3041 hw->tbi_compatibility_on = true;
3042 rctl = er32(RCTL);
3043 rctl |= E1000_RCTL_SBP;
3044 ew32(RCTL, rctl);
3045 }
3046 }
3047 }
3048 }
3049
3050
3051
3052
3053
3054
3055
3056 else if ((((hw->media_type == e1000_media_type_fiber) &&
3057 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3058 (hw->media_type == e1000_media_type_internal_serdes)) &&
3059 (!(status & E1000_STATUS_LU)) &&
3060 (!(rxcw & E1000_RXCW_C))) {
3061 if (hw->autoneg_failed == 0) {
3062 hw->autoneg_failed = 1;
3063 return 0;
3064 }
3065 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3066
3067
3068 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3069
3070
3071 ctrl = er32(CTRL);
3072 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3073 ew32(CTRL, ctrl);
3074
3075
3076 ret_val = e1000_config_fc_after_link_up(hw);
3077 if (ret_val) {
3078 DEBUGOUT("Error configuring flow control\n");
3079 return ret_val;
3080 }
3081 }
3082
3083
3084
3085
3086
3087 else if (((hw->media_type == e1000_media_type_fiber) ||
3088 (hw->media_type == e1000_media_type_internal_serdes)) &&
3089 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3090 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3091 ew32(TXCW, hw->txcw);
3092 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
3093
3094 hw->serdes_link_down = false;
3095 }
3096
3097
3098
3099 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3100 !(E1000_TXCW_ANE & er32(TXCW))) {
3101
3102 udelay(10);
3103 if (E1000_RXCW_SYNCH & er32(RXCW)) {
3104 if (!(rxcw & E1000_RXCW_IV)) {
3105 hw->serdes_link_down = false;
3106 DEBUGOUT("SERDES: Link is up.\n");
3107 }
3108 } else {
3109 hw->serdes_link_down = true;
3110 DEBUGOUT("SERDES: Link is down.\n");
3111 }
3112 }
3113 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3114 (E1000_TXCW_ANE & er32(TXCW))) {
3115 hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
3116 }
3117 return E1000_SUCCESS;
3118}
3119
3120
3121
3122
3123
3124
3125
3126
3127s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3128{
3129 u32 status;
3130 s32 ret_val;
3131 u16 phy_data;
3132
3133 DEBUGFUNC("e1000_get_speed_and_duplex");
3134
3135 if (hw->mac_type >= e1000_82543) {
3136 status = er32(STATUS);
3137 if (status & E1000_STATUS_SPEED_1000) {
3138 *speed = SPEED_1000;
3139 DEBUGOUT("1000 Mbs, ");
3140 } else if (status & E1000_STATUS_SPEED_100) {
3141 *speed = SPEED_100;
3142 DEBUGOUT("100 Mbs, ");
3143 } else {
3144 *speed = SPEED_10;
3145 DEBUGOUT("10 Mbs, ");
3146 }
3147
3148 if (status & E1000_STATUS_FD) {
3149 *duplex = FULL_DUPLEX;
3150 DEBUGOUT("Full Duplex\n");
3151 } else {
3152 *duplex = HALF_DUPLEX;
3153 DEBUGOUT(" Half Duplex\n");
3154 }
3155 } else {
3156 DEBUGOUT("1000 Mbs, Full Duplex\n");
3157 *speed = SPEED_1000;
3158 *duplex = FULL_DUPLEX;
3159 }
3160
3161
3162
3163
3164
3165 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3166 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3167 if (ret_val)
3168 return ret_val;
3169
3170 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3171 *duplex = HALF_DUPLEX;
3172 else {
3173 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3174 if (ret_val)
3175 return ret_val;
3176 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3177 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3178 *duplex = HALF_DUPLEX;
3179 }
3180 }
3181
3182 if ((hw->mac_type == e1000_80003es2lan) &&
3183 (hw->media_type == e1000_media_type_copper)) {
3184 if (*speed == SPEED_1000)
3185 ret_val = e1000_configure_kmrn_for_1000(hw);
3186 else
3187 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3188 if (ret_val)
3189 return ret_val;
3190 }
3191
3192 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3193 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3194 if (ret_val)
3195 return ret_val;
3196 }
3197
3198 return E1000_SUCCESS;
3199}
3200
3201
3202
3203
3204
3205
3206static s32 e1000_wait_autoneg(struct e1000_hw *hw)
3207{
3208 s32 ret_val;
3209 u16 i;
3210 u16 phy_data;
3211
3212 DEBUGFUNC("e1000_wait_autoneg");
3213 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3214
3215
3216 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3217
3218
3219
3220 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3221 if (ret_val)
3222 return ret_val;
3223 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3224 if (ret_val)
3225 return ret_val;
3226 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3227 return E1000_SUCCESS;
3228 }
3229 msleep(100);
3230 }
3231 return E1000_SUCCESS;
3232}
3233
3234
3235
3236
3237
3238
3239
3240static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3241{
3242
3243
3244
3245 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
3246 E1000_WRITE_FLUSH();
3247 udelay(10);
3248}
3249
3250
3251
3252
3253
3254
3255
3256static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3257{
3258
3259
3260
3261 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
3262 E1000_WRITE_FLUSH();
3263 udelay(10);
3264}
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
3276{
3277 u32 ctrl;
3278 u32 mask;
3279
3280
3281
3282
3283
3284 mask = 0x01;
3285 mask <<= (count - 1);
3286
3287 ctrl = er32(CTRL);
3288
3289
3290 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3291
3292 while (mask) {
3293
3294
3295
3296
3297
3298 if (data & mask)
3299 ctrl |= E1000_CTRL_MDIO;
3300 else
3301 ctrl &= ~E1000_CTRL_MDIO;
3302
3303 ew32(CTRL, ctrl);
3304 E1000_WRITE_FLUSH();
3305
3306 udelay(10);
3307
3308 e1000_raise_mdi_clk(hw, &ctrl);
3309 e1000_lower_mdi_clk(hw, &ctrl);
3310
3311 mask = mask >> 1;
3312 }
3313}
3314
3315
3316
3317
3318
3319
3320
3321
3322static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3323{
3324 u32 ctrl;
3325 u16 data = 0;
3326 u8 i;
3327
3328
3329
3330
3331
3332
3333
3334
3335 ctrl = er32(CTRL);
3336
3337
3338 ctrl &= ~E1000_CTRL_MDIO_DIR;
3339 ctrl &= ~E1000_CTRL_MDIO;
3340
3341 ew32(CTRL, ctrl);
3342 E1000_WRITE_FLUSH();
3343
3344
3345
3346
3347
3348 e1000_raise_mdi_clk(hw, &ctrl);
3349 e1000_lower_mdi_clk(hw, &ctrl);
3350
3351 for (data = 0, i = 0; i < 16; i++) {
3352 data = data << 1;
3353 e1000_raise_mdi_clk(hw, &ctrl);
3354 ctrl = er32(CTRL);
3355
3356 if (ctrl & E1000_CTRL_MDIO)
3357 data |= 1;
3358 e1000_lower_mdi_clk(hw, &ctrl);
3359 }
3360
3361 e1000_raise_mdi_clk(hw, &ctrl);
3362 e1000_lower_mdi_clk(hw, &ctrl);
3363
3364 return data;
3365}
3366
3367static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3368{
3369 u32 swfw_sync = 0;
3370 u32 swmask = mask;
3371 u32 fwmask = mask << 16;
3372 s32 timeout = 200;
3373
3374 DEBUGFUNC("e1000_swfw_sync_acquire");
3375
3376 if (hw->swfwhw_semaphore_present)
3377 return e1000_get_software_flag(hw);
3378
3379 if (!hw->swfw_sync_present)
3380 return e1000_get_hw_eeprom_semaphore(hw);
3381
3382 while (timeout) {
3383 if (e1000_get_hw_eeprom_semaphore(hw))
3384 return -E1000_ERR_SWFW_SYNC;
3385
3386 swfw_sync = er32(SW_FW_SYNC);
3387 if (!(swfw_sync & (fwmask | swmask))) {
3388 break;
3389 }
3390
3391
3392
3393 e1000_put_hw_eeprom_semaphore(hw);
3394 mdelay(5);
3395 timeout--;
3396 }
3397
3398 if (!timeout) {
3399 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3400 return -E1000_ERR_SWFW_SYNC;
3401 }
3402
3403 swfw_sync |= swmask;
3404 ew32(SW_FW_SYNC, swfw_sync);
3405
3406 e1000_put_hw_eeprom_semaphore(hw);
3407 return E1000_SUCCESS;
3408}
3409
3410static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3411{
3412 u32 swfw_sync;
3413 u32 swmask = mask;
3414
3415 DEBUGFUNC("e1000_swfw_sync_release");
3416
3417 if (hw->swfwhw_semaphore_present) {
3418 e1000_release_software_flag(hw);
3419 return;
3420 }
3421
3422 if (!hw->swfw_sync_present) {
3423 e1000_put_hw_eeprom_semaphore(hw);
3424 return;
3425 }
3426
3427
3428
3429 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3430
3431
3432 swfw_sync = er32(SW_FW_SYNC);
3433 swfw_sync &= ~swmask;
3434 ew32(SW_FW_SYNC, swfw_sync);
3435
3436 e1000_put_hw_eeprom_semaphore(hw);
3437}
3438
3439
3440
3441
3442
3443
3444
3445s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
3446{
3447 u32 ret_val;
3448 u16 swfw;
3449
3450 DEBUGFUNC("e1000_read_phy_reg");
3451
3452 if ((hw->mac_type == e1000_80003es2lan) &&
3453 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3454 swfw = E1000_SWFW_PHY1_SM;
3455 } else {
3456 swfw = E1000_SWFW_PHY0_SM;
3457 }
3458 if (e1000_swfw_sync_acquire(hw, swfw))
3459 return -E1000_ERR_SWFW_SYNC;
3460
3461 if ((hw->phy_type == e1000_phy_igp ||
3462 hw->phy_type == e1000_phy_igp_3 ||
3463 hw->phy_type == e1000_phy_igp_2) &&
3464 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3465 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3466 (u16)reg_addr);
3467 if (ret_val) {
3468 e1000_swfw_sync_release(hw, swfw);
3469 return ret_val;
3470 }
3471 } else if (hw->phy_type == e1000_phy_gg82563) {
3472 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3473 (hw->mac_type == e1000_80003es2lan)) {
3474
3475 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3476 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3477 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3478 } else {
3479
3480
3481
3482 ret_val = e1000_write_phy_reg_ex(hw,
3483 GG82563_PHY_PAGE_SELECT_ALT,
3484 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3485 }
3486
3487 if (ret_val) {
3488 e1000_swfw_sync_release(hw, swfw);
3489 return ret_val;
3490 }
3491 }
3492 }
3493
3494 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3495 phy_data);
3496
3497 e1000_swfw_sync_release(hw, swfw);
3498 return ret_val;
3499}
3500
3501static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3502 u16 *phy_data)
3503{
3504 u32 i;
3505 u32 mdic = 0;
3506 const u32 phy_addr = 1;
3507
3508 DEBUGFUNC("e1000_read_phy_reg_ex");
3509
3510 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3511 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3512 return -E1000_ERR_PARAM;
3513 }
3514
3515 if (hw->mac_type > e1000_82543) {
3516
3517
3518
3519
3520 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3521 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3522 (E1000_MDIC_OP_READ));
3523
3524 ew32(MDIC, mdic);
3525
3526
3527 for (i = 0; i < 64; i++) {
3528 udelay(50);
3529 mdic = er32(MDIC);
3530 if (mdic & E1000_MDIC_READY) break;
3531 }
3532 if (!(mdic & E1000_MDIC_READY)) {
3533 DEBUGOUT("MDI Read did not complete\n");
3534 return -E1000_ERR_PHY;
3535 }
3536 if (mdic & E1000_MDIC_ERROR) {
3537 DEBUGOUT("MDI Error\n");
3538 return -E1000_ERR_PHY;
3539 }
3540 *phy_data = (u16)mdic;
3541 } else {
3542
3543
3544
3545
3546 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559 mdic = ((reg_addr) | (phy_addr << 5) |
3560 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3561
3562 e1000_shift_out_mdi_bits(hw, mdic, 14);
3563
3564
3565
3566
3567
3568 *phy_data = e1000_shift_in_mdi_bits(hw);
3569 }
3570 return E1000_SUCCESS;
3571}
3572
3573
3574
3575
3576
3577
3578
3579
3580s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
3581{
3582 u32 ret_val;
3583 u16 swfw;
3584
3585 DEBUGFUNC("e1000_write_phy_reg");
3586
3587 if ((hw->mac_type == e1000_80003es2lan) &&
3588 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3589 swfw = E1000_SWFW_PHY1_SM;
3590 } else {
3591 swfw = E1000_SWFW_PHY0_SM;
3592 }
3593 if (e1000_swfw_sync_acquire(hw, swfw))
3594 return -E1000_ERR_SWFW_SYNC;
3595
3596 if ((hw->phy_type == e1000_phy_igp ||
3597 hw->phy_type == e1000_phy_igp_3 ||
3598 hw->phy_type == e1000_phy_igp_2) &&
3599 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3600 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3601 (u16)reg_addr);
3602 if (ret_val) {
3603 e1000_swfw_sync_release(hw, swfw);
3604 return ret_val;
3605 }
3606 } else if (hw->phy_type == e1000_phy_gg82563) {
3607 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3608 (hw->mac_type == e1000_80003es2lan)) {
3609
3610 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3611 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3612 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3613 } else {
3614
3615
3616
3617 ret_val = e1000_write_phy_reg_ex(hw,
3618 GG82563_PHY_PAGE_SELECT_ALT,
3619 (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3620 }
3621
3622 if (ret_val) {
3623 e1000_swfw_sync_release(hw, swfw);
3624 return ret_val;
3625 }
3626 }
3627 }
3628
3629 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3630 phy_data);
3631
3632 e1000_swfw_sync_release(hw, swfw);
3633 return ret_val;
3634}
3635
3636static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3637 u16 phy_data)
3638{
3639 u32 i;
3640 u32 mdic = 0;
3641 const u32 phy_addr = 1;
3642
3643 DEBUGFUNC("e1000_write_phy_reg_ex");
3644
3645 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3646 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3647 return -E1000_ERR_PARAM;
3648 }
3649
3650 if (hw->mac_type > e1000_82543) {
3651
3652
3653
3654
3655 mdic = (((u32)phy_data) |
3656 (reg_addr << E1000_MDIC_REG_SHIFT) |
3657 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3658 (E1000_MDIC_OP_WRITE));
3659
3660 ew32(MDIC, mdic);
3661
3662
3663 for (i = 0; i < 641; i++) {
3664 udelay(5);
3665 mdic = er32(MDIC);
3666 if (mdic & E1000_MDIC_READY) break;
3667 }
3668 if (!(mdic & E1000_MDIC_READY)) {
3669 DEBUGOUT("MDI Write did not complete\n");
3670 return -E1000_ERR_PHY;
3671 }
3672 } else {
3673
3674
3675
3676
3677
3678 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3679
3680
3681
3682
3683
3684
3685
3686 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3687 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3688 mdic <<= 16;
3689 mdic |= (u32)phy_data;
3690
3691 e1000_shift_out_mdi_bits(hw, mdic, 32);
3692 }
3693
3694 return E1000_SUCCESS;
3695}
3696
3697static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
3698{
3699 u32 reg_val;
3700 u16 swfw;
3701 DEBUGFUNC("e1000_read_kmrn_reg");
3702
3703 if ((hw->mac_type == e1000_80003es2lan) &&
3704 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3705 swfw = E1000_SWFW_PHY1_SM;
3706 } else {
3707 swfw = E1000_SWFW_PHY0_SM;
3708 }
3709 if (e1000_swfw_sync_acquire(hw, swfw))
3710 return -E1000_ERR_SWFW_SYNC;
3711
3712
3713 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3714 E1000_KUMCTRLSTA_OFFSET) |
3715 E1000_KUMCTRLSTA_REN;
3716 ew32(KUMCTRLSTA, reg_val);
3717 udelay(2);
3718
3719
3720 reg_val = er32(KUMCTRLSTA);
3721 *data = (u16)reg_val;
3722
3723 e1000_swfw_sync_release(hw, swfw);
3724 return E1000_SUCCESS;
3725}
3726
3727static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
3728{
3729 u32 reg_val;
3730 u16 swfw;
3731 DEBUGFUNC("e1000_write_kmrn_reg");
3732
3733 if ((hw->mac_type == e1000_80003es2lan) &&
3734 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3735 swfw = E1000_SWFW_PHY1_SM;
3736 } else {
3737 swfw = E1000_SWFW_PHY0_SM;
3738 }
3739 if (e1000_swfw_sync_acquire(hw, swfw))
3740 return -E1000_ERR_SWFW_SYNC;
3741
3742 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3743 E1000_KUMCTRLSTA_OFFSET) | data;
3744 ew32(KUMCTRLSTA, reg_val);
3745 udelay(2);
3746
3747 e1000_swfw_sync_release(hw, swfw);
3748 return E1000_SUCCESS;
3749}
3750
3751
3752
3753
3754
3755
3756s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3757{
3758 u32 ctrl, ctrl_ext;
3759 u32 led_ctrl;
3760 s32 ret_val;
3761 u16 swfw;
3762
3763 DEBUGFUNC("e1000_phy_hw_reset");
3764
3765
3766
3767 ret_val = e1000_check_phy_reset_block(hw);
3768 if (ret_val)
3769 return E1000_SUCCESS;
3770
3771 DEBUGOUT("Resetting Phy...\n");
3772
3773 if (hw->mac_type > e1000_82543) {
3774 if ((hw->mac_type == e1000_80003es2lan) &&
3775 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3776 swfw = E1000_SWFW_PHY1_SM;
3777 } else {
3778 swfw = E1000_SWFW_PHY0_SM;
3779 }
3780 if (e1000_swfw_sync_acquire(hw, swfw)) {
3781 DEBUGOUT("Unable to acquire swfw sync\n");
3782 return -E1000_ERR_SWFW_SYNC;
3783 }
3784
3785
3786
3787
3788
3789
3790 ctrl = er32(CTRL);
3791 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3792 E1000_WRITE_FLUSH();
3793
3794 if (hw->mac_type < e1000_82571)
3795 msleep(10);
3796 else
3797 udelay(100);
3798
3799 ew32(CTRL, ctrl);
3800 E1000_WRITE_FLUSH();
3801
3802 if (hw->mac_type >= e1000_82571)
3803 mdelay(10);
3804
3805 e1000_swfw_sync_release(hw, swfw);
3806 } else {
3807
3808
3809
3810 ctrl_ext = er32(CTRL_EXT);
3811 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3812 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3813 ew32(CTRL_EXT, ctrl_ext);
3814 E1000_WRITE_FLUSH();
3815 msleep(10);
3816 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3817 ew32(CTRL_EXT, ctrl_ext);
3818 E1000_WRITE_FLUSH();
3819 }
3820 udelay(150);
3821
3822 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3823
3824 led_ctrl = er32(LEDCTL);
3825 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3826 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3827 ew32(LEDCTL, led_ctrl);
3828 }
3829
3830
3831 ret_val = e1000_get_phy_cfg_done(hw);
3832 if (ret_val != E1000_SUCCESS)
3833 return ret_val;
3834 e1000_release_software_semaphore(hw);
3835
3836 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3837 ret_val = e1000_init_lcd_from_nvm(hw);
3838
3839 return ret_val;
3840}
3841
3842
3843
3844
3845
3846
3847
3848
3849s32 e1000_phy_reset(struct e1000_hw *hw)
3850{
3851 s32 ret_val;
3852 u16 phy_data;
3853
3854 DEBUGFUNC("e1000_phy_reset");
3855
3856
3857
3858 ret_val = e1000_check_phy_reset_block(hw);
3859 if (ret_val)
3860 return E1000_SUCCESS;
3861
3862 switch (hw->phy_type) {
3863 case e1000_phy_igp:
3864 case e1000_phy_igp_2:
3865 case e1000_phy_igp_3:
3866 case e1000_phy_ife:
3867 ret_val = e1000_phy_hw_reset(hw);
3868 if (ret_val)
3869 return ret_val;
3870 break;
3871 default:
3872 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3873 if (ret_val)
3874 return ret_val;
3875
3876 phy_data |= MII_CR_RESET;
3877 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3878 if (ret_val)
3879 return ret_val;
3880
3881 udelay(1);
3882 break;
3883 }
3884
3885 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3886 e1000_phy_init_script(hw);
3887
3888 return E1000_SUCCESS;
3889}
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3901{
3902 s32 reg;
3903 u16 phy_data;
3904 s32 retry = 0;
3905
3906 DEBUGFUNC("e1000_phy_powerdown_workaround");
3907
3908 if (hw->phy_type != e1000_phy_igp_3)
3909 return;
3910
3911 do {
3912
3913 reg = er32(PHY_CTRL);
3914 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3915 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3916
3917
3918 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3919 phy_data |= (1 << 9);
3920 phy_data &= ~(1 << 8);
3921 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3922
3923
3924 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3925 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3926 break;
3927
3928
3929 reg = er32(CTRL);
3930 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3931 retry++;
3932 } while (retry);
3933
3934 return;
3935
3936}
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3953{
3954 s32 ret_val;
3955 s32 reg;
3956 s32 cnt;
3957 u16 phy_data;
3958
3959 if (hw->kmrn_lock_loss_workaround_disabled)
3960 return E1000_SUCCESS;
3961
3962
3963
3964
3965 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3966 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3967
3968 if (phy_data & MII_SR_LINK_STATUS) {
3969 for (cnt = 0; cnt < 10; cnt++) {
3970
3971 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3972 if (ret_val)
3973 return ret_val;
3974
3975 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3976 if (ret_val)
3977 return ret_val;
3978
3979
3980 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3981 return E1000_SUCCESS;
3982
3983
3984 e1000_phy_hw_reset(hw);
3985 mdelay(5);
3986 }
3987
3988 reg = er32(PHY_CTRL);
3989 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3990 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3991
3992
3993 return E1000_ERR_PHY;
3994 }
3995
3996 return E1000_SUCCESS;
3997}
3998
3999
4000
4001
4002
4003
4004static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
4005{
4006 s32 phy_init_status, ret_val;
4007 u16 phy_id_high, phy_id_low;
4008 bool match = false;
4009
4010 DEBUGFUNC("e1000_detect_gig_phy");
4011
4012 if (hw->phy_id != 0)
4013 return E1000_SUCCESS;
4014
4015
4016
4017
4018 if (hw->mac_type == e1000_82571 ||
4019 hw->mac_type == e1000_82572) {
4020 hw->phy_id = IGP01E1000_I_PHY_ID;
4021 hw->phy_type = e1000_phy_igp_2;
4022 return E1000_SUCCESS;
4023 }
4024
4025
4026
4027
4028
4029
4030
4031 if (hw->mac_type == e1000_80003es2lan)
4032 hw->phy_type = e1000_phy_gg82563;
4033
4034
4035 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4036 if (ret_val)
4037 return ret_val;
4038
4039 hw->phy_id = (u32)(phy_id_high << 16);
4040 udelay(20);
4041 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4042 if (ret_val)
4043 return ret_val;
4044
4045 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
4046 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
4047
4048 switch (hw->mac_type) {
4049 case e1000_82543:
4050 if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
4051 break;
4052 case e1000_82544:
4053 if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
4054 break;
4055 case e1000_82540:
4056 case e1000_82545:
4057 case e1000_82545_rev_3:
4058 case e1000_82546:
4059 case e1000_82546_rev_3:
4060 if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
4061 break;
4062 case e1000_82541:
4063 case e1000_82541_rev_2:
4064 case e1000_82547:
4065 case e1000_82547_rev_2:
4066 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
4067 break;
4068 case e1000_82573:
4069 if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
4070 break;
4071 case e1000_80003es2lan:
4072 if (hw->phy_id == GG82563_E_PHY_ID) match = true;
4073 break;
4074 case e1000_ich8lan:
4075 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
4076 if (hw->phy_id == IFE_E_PHY_ID) match = true;
4077 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
4078 if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
4079 break;
4080 default:
4081 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4082 return -E1000_ERR_CONFIG;
4083 }
4084 phy_init_status = e1000_set_phy_type(hw);
4085
4086 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4087 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4088 return E1000_SUCCESS;
4089 }
4090 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4091 return -E1000_ERR_PHY;
4092}
4093
4094
4095
4096
4097
4098
4099static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
4100{
4101 s32 ret_val;
4102 DEBUGFUNC("e1000_phy_reset_dsp");
4103
4104 do {
4105 if (hw->phy_type != e1000_phy_gg82563) {
4106 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4107 if (ret_val) break;
4108 }
4109 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4110 if (ret_val) break;
4111 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4112 if (ret_val) break;
4113 ret_val = E1000_SUCCESS;
4114 } while (0);
4115
4116 return ret_val;
4117}
4118
4119
4120
4121
4122
4123
4124
4125static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
4126 struct e1000_phy_info *phy_info)
4127{
4128 s32 ret_val;
4129 u16 phy_data, min_length, max_length, average;
4130 e1000_rev_polarity polarity;
4131
4132 DEBUGFUNC("e1000_phy_igp_get_info");
4133
4134
4135
4136 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4137
4138
4139 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4140
4141
4142 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4143
4144
4145 ret_val = e1000_check_polarity(hw, &polarity);
4146 if (ret_val)
4147 return ret_val;
4148
4149 phy_info->cable_polarity = polarity;
4150
4151 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4152 if (ret_val)
4153 return ret_val;
4154
4155 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4156 IGP01E1000_PSSR_MDIX_SHIFT);
4157
4158 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4159 IGP01E1000_PSSR_SPEED_1000MBPS) {
4160
4161 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4162 if (ret_val)
4163 return ret_val;
4164
4165 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4166 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4167 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4168 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4169 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4170 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4171
4172
4173 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4174 if (ret_val)
4175 return ret_val;
4176
4177
4178 average = (max_length + min_length) / 2;
4179
4180 if (average <= e1000_igp_cable_length_50)
4181 phy_info->cable_length = e1000_cable_length_50;
4182 else if (average <= e1000_igp_cable_length_80)
4183 phy_info->cable_length = e1000_cable_length_50_80;
4184 else if (average <= e1000_igp_cable_length_110)
4185 phy_info->cable_length = e1000_cable_length_80_110;
4186 else if (average <= e1000_igp_cable_length_140)
4187 phy_info->cable_length = e1000_cable_length_110_140;
4188 else
4189 phy_info->cable_length = e1000_cable_length_140;
4190 }
4191
4192 return E1000_SUCCESS;
4193}
4194
4195
4196
4197
4198
4199
4200
4201static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
4202 struct e1000_phy_info *phy_info)
4203{
4204 s32 ret_val;
4205 u16 phy_data;
4206 e1000_rev_polarity polarity;
4207
4208 DEBUGFUNC("e1000_phy_ife_get_info");
4209
4210 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4211 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4212
4213 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4214 if (ret_val)
4215 return ret_val;
4216 phy_info->polarity_correction =
4217 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4218 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4219 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4220
4221 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4222 ret_val = e1000_check_polarity(hw, &polarity);
4223 if (ret_val)
4224 return ret_val;
4225 } else {
4226
4227 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4228 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4229 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4230 }
4231 phy_info->cable_polarity = polarity;
4232
4233 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4234 if (ret_val)
4235 return ret_val;
4236
4237 phy_info->mdix_mode = (e1000_auto_x_mode)
4238 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4239 IFE_PMC_MDIX_MODE_SHIFT);
4240
4241 return E1000_SUCCESS;
4242}
4243
4244
4245
4246
4247
4248
4249
4250static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
4251 struct e1000_phy_info *phy_info)
4252{
4253 s32 ret_val;
4254 u16 phy_data;
4255 e1000_rev_polarity polarity;
4256
4257 DEBUGFUNC("e1000_phy_m88_get_info");
4258
4259
4260
4261 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4262
4263 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4264 if (ret_val)
4265 return ret_val;
4266
4267 phy_info->extended_10bt_distance =
4268 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4269 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4270 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4271
4272 phy_info->polarity_correction =
4273 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4274 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4275 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4276
4277
4278 ret_val = e1000_check_polarity(hw, &polarity);
4279 if (ret_val)
4280 return ret_val;
4281 phy_info->cable_polarity = polarity;
4282
4283 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4284 if (ret_val)
4285 return ret_val;
4286
4287 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4288 M88E1000_PSSR_MDIX_SHIFT);
4289
4290 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4291
4292
4293
4294 if (hw->phy_type != e1000_phy_gg82563) {
4295 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4296 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4297 } else {
4298 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4299 &phy_data);
4300 if (ret_val)
4301 return ret_val;
4302
4303 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4304 }
4305
4306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4307 if (ret_val)
4308 return ret_val;
4309
4310 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4311 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4312 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4313 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4314 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4315 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4316
4317 }
4318
4319 return E1000_SUCCESS;
4320}
4321
4322
4323
4324
4325
4326
4327
4328s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
4329{
4330 s32 ret_val;
4331 u16 phy_data;
4332
4333 DEBUGFUNC("e1000_phy_get_info");
4334
4335 phy_info->cable_length = e1000_cable_length_undefined;
4336 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4337 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4338 phy_info->downshift = e1000_downshift_undefined;
4339 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4340 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4341 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4342 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4343
4344 if (hw->media_type != e1000_media_type_copper) {
4345 DEBUGOUT("PHY info is only valid for copper media\n");
4346 return -E1000_ERR_CONFIG;
4347 }
4348
4349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4350 if (ret_val)
4351 return ret_val;
4352
4353 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4354 if (ret_val)
4355 return ret_val;
4356
4357 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4358 DEBUGOUT("PHY info is only valid if link is up\n");
4359 return -E1000_ERR_CONFIG;
4360 }
4361
4362 if (hw->phy_type == e1000_phy_igp ||
4363 hw->phy_type == e1000_phy_igp_3 ||
4364 hw->phy_type == e1000_phy_igp_2)
4365 return e1000_phy_igp_get_info(hw, phy_info);
4366 else if (hw->phy_type == e1000_phy_ife)
4367 return e1000_phy_ife_get_info(hw, phy_info);
4368 else
4369 return e1000_phy_m88_get_info(hw, phy_info);
4370}
4371
4372s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
4373{
4374 DEBUGFUNC("e1000_validate_mdi_settings");
4375
4376 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4377 DEBUGOUT("Invalid MDI setting detected\n");
4378 hw->mdix = 1;
4379 return -E1000_ERR_CONFIG;
4380 }
4381 return E1000_SUCCESS;
4382}
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4393{
4394 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4395 u32 eecd = er32(EECD);
4396 s32 ret_val = E1000_SUCCESS;
4397 u16 eeprom_size;
4398
4399 DEBUGFUNC("e1000_init_eeprom_params");
4400
4401 switch (hw->mac_type) {
4402 case e1000_82542_rev2_0:
4403 case e1000_82542_rev2_1:
4404 case e1000_82543:
4405 case e1000_82544:
4406 eeprom->type = e1000_eeprom_microwire;
4407 eeprom->word_size = 64;
4408 eeprom->opcode_bits = 3;
4409 eeprom->address_bits = 6;
4410 eeprom->delay_usec = 50;
4411 eeprom->use_eerd = false;
4412 eeprom->use_eewr = false;
4413 break;
4414 case e1000_82540:
4415 case e1000_82545:
4416 case e1000_82545_rev_3:
4417 case e1000_82546:
4418 case e1000_82546_rev_3:
4419 eeprom->type = e1000_eeprom_microwire;
4420 eeprom->opcode_bits = 3;
4421 eeprom->delay_usec = 50;
4422 if (eecd & E1000_EECD_SIZE) {
4423 eeprom->word_size = 256;
4424 eeprom->address_bits = 8;
4425 } else {
4426 eeprom->word_size = 64;
4427 eeprom->address_bits = 6;
4428 }
4429 eeprom->use_eerd = false;
4430 eeprom->use_eewr = false;
4431 break;
4432 case e1000_82541:
4433 case e1000_82541_rev_2:
4434 case e1000_82547:
4435 case e1000_82547_rev_2:
4436 if (eecd & E1000_EECD_TYPE) {
4437 eeprom->type = e1000_eeprom_spi;
4438 eeprom->opcode_bits = 8;
4439 eeprom->delay_usec = 1;
4440 if (eecd & E1000_EECD_ADDR_BITS) {
4441 eeprom->page_size = 32;
4442 eeprom->address_bits = 16;
4443 } else {
4444 eeprom->page_size = 8;
4445 eeprom->address_bits = 8;
4446 }
4447 } else {
4448 eeprom->type = e1000_eeprom_microwire;
4449 eeprom->opcode_bits = 3;
4450 eeprom->delay_usec = 50;
4451 if (eecd & E1000_EECD_ADDR_BITS) {
4452 eeprom->word_size = 256;
4453 eeprom->address_bits = 8;
4454 } else {
4455 eeprom->word_size = 64;
4456 eeprom->address_bits = 6;
4457 }
4458 }
4459 eeprom->use_eerd = false;
4460 eeprom->use_eewr = false;
4461 break;
4462 case e1000_82571:
4463 case e1000_82572:
4464 eeprom->type = e1000_eeprom_spi;
4465 eeprom->opcode_bits = 8;
4466 eeprom->delay_usec = 1;
4467 if (eecd & E1000_EECD_ADDR_BITS) {
4468 eeprom->page_size = 32;
4469 eeprom->address_bits = 16;
4470 } else {
4471 eeprom->page_size = 8;
4472 eeprom->address_bits = 8;
4473 }
4474 eeprom->use_eerd = false;
4475 eeprom->use_eewr = false;
4476 break;
4477 case e1000_82573:
4478 eeprom->type = e1000_eeprom_spi;
4479 eeprom->opcode_bits = 8;
4480 eeprom->delay_usec = 1;
4481 if (eecd & E1000_EECD_ADDR_BITS) {
4482 eeprom->page_size = 32;
4483 eeprom->address_bits = 16;
4484 } else {
4485 eeprom->page_size = 8;
4486 eeprom->address_bits = 8;
4487 }
4488 eeprom->use_eerd = true;
4489 eeprom->use_eewr = true;
4490 if (!e1000_is_onboard_nvm_eeprom(hw)) {
4491 eeprom->type = e1000_eeprom_flash;
4492 eeprom->word_size = 2048;
4493
4494
4495
4496 eecd &= ~E1000_EECD_AUPDEN;
4497 ew32(EECD, eecd);
4498 }
4499 break;
4500 case e1000_80003es2lan:
4501 eeprom->type = e1000_eeprom_spi;
4502 eeprom->opcode_bits = 8;
4503 eeprom->delay_usec = 1;
4504 if (eecd & E1000_EECD_ADDR_BITS) {
4505 eeprom->page_size = 32;
4506 eeprom->address_bits = 16;
4507 } else {
4508 eeprom->page_size = 8;
4509 eeprom->address_bits = 8;
4510 }
4511 eeprom->use_eerd = true;
4512 eeprom->use_eewr = false;
4513 break;
4514 case e1000_ich8lan:
4515 {
4516 s32 i = 0;
4517 u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4518
4519 eeprom->type = e1000_eeprom_ich8;
4520 eeprom->use_eerd = false;
4521 eeprom->use_eewr = false;
4522 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4523
4524
4525
4526 if (hw->eeprom_shadow_ram != NULL) {
4527 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4528 hw->eeprom_shadow_ram[i].modified = false;
4529 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4530 }
4531 }
4532
4533 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4534 ICH_FLASH_SECTOR_SIZE;
4535
4536 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4537 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4538
4539 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4540
4541 hw->flash_bank_size /= 2 * sizeof(u16);
4542
4543 break;
4544 }
4545 default:
4546 break;
4547 }
4548
4549 if (eeprom->type == e1000_eeprom_spi) {
4550
4551
4552
4553 if (hw->mac_type <= e1000_82547_rev_2) {
4554
4555 eeprom->word_size = 64;
4556 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4557 if (ret_val)
4558 return ret_val;
4559 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4560
4561
4562
4563 if (eeprom_size)
4564 eeprom_size++;
4565 } else {
4566 eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4567 E1000_EECD_SIZE_EX_SHIFT);
4568 }
4569
4570 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4571 }
4572 return ret_val;
4573}
4574
4575
4576
4577
4578
4579
4580
4581static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
4582{
4583
4584
4585
4586 *eecd = *eecd | E1000_EECD_SK;
4587 ew32(EECD, *eecd);
4588 E1000_WRITE_FLUSH();
4589 udelay(hw->eeprom.delay_usec);
4590}
4591
4592
4593
4594
4595
4596
4597
4598static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
4599{
4600
4601
4602
4603 *eecd = *eecd & ~E1000_EECD_SK;
4604 ew32(EECD, *eecd);
4605 E1000_WRITE_FLUSH();
4606 udelay(hw->eeprom.delay_usec);
4607}
4608
4609
4610
4611
4612
4613
4614
4615
4616static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4617{
4618 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4619 u32 eecd;
4620 u32 mask;
4621
4622
4623
4624
4625
4626 mask = 0x01 << (count - 1);
4627 eecd = er32(EECD);
4628 if (eeprom->type == e1000_eeprom_microwire) {
4629 eecd &= ~E1000_EECD_DO;
4630 } else if (eeprom->type == e1000_eeprom_spi) {
4631 eecd |= E1000_EECD_DO;
4632 }
4633 do {
4634
4635
4636
4637
4638
4639 eecd &= ~E1000_EECD_DI;
4640
4641 if (data & mask)
4642 eecd |= E1000_EECD_DI;
4643
4644 ew32(EECD, eecd);
4645 E1000_WRITE_FLUSH();
4646
4647 udelay(eeprom->delay_usec);
4648
4649 e1000_raise_ee_clk(hw, &eecd);
4650 e1000_lower_ee_clk(hw, &eecd);
4651
4652 mask = mask >> 1;
4653
4654 } while (mask);
4655
4656
4657 eecd &= ~E1000_EECD_DI;
4658 ew32(EECD, eecd);
4659}
4660
4661
4662
4663
4664
4665
4666static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
4667{
4668 u32 eecd;
4669 u32 i;
4670 u16 data;
4671
4672
4673
4674
4675
4676
4677
4678
4679 eecd = er32(EECD);
4680
4681 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4682 data = 0;
4683
4684 for (i = 0; i < count; i++) {
4685 data = data << 1;
4686 e1000_raise_ee_clk(hw, &eecd);
4687
4688 eecd = er32(EECD);
4689
4690 eecd &= ~(E1000_EECD_DI);
4691 if (eecd & E1000_EECD_DO)
4692 data |= 1;
4693
4694 e1000_lower_ee_clk(hw, &eecd);
4695 }
4696
4697 return data;
4698}
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4709{
4710 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4711 u32 eecd, i=0;
4712
4713 DEBUGFUNC("e1000_acquire_eeprom");
4714
4715 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4716 return -E1000_ERR_SWFW_SYNC;
4717 eecd = er32(EECD);
4718
4719 if (hw->mac_type != e1000_82573) {
4720
4721 if (hw->mac_type > e1000_82544) {
4722 eecd |= E1000_EECD_REQ;
4723 ew32(EECD, eecd);
4724 eecd = er32(EECD);
4725 while ((!(eecd & E1000_EECD_GNT)) &&
4726 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4727 i++;
4728 udelay(5);
4729 eecd = er32(EECD);
4730 }
4731 if (!(eecd & E1000_EECD_GNT)) {
4732 eecd &= ~E1000_EECD_REQ;
4733 ew32(EECD, eecd);
4734 DEBUGOUT("Could not acquire EEPROM grant\n");
4735 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4736 return -E1000_ERR_EEPROM;
4737 }
4738 }
4739 }
4740
4741
4742
4743 if (eeprom->type == e1000_eeprom_microwire) {
4744
4745 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4746 ew32(EECD, eecd);
4747
4748
4749 eecd |= E1000_EECD_CS;
4750 ew32(EECD, eecd);
4751 } else if (eeprom->type == e1000_eeprom_spi) {
4752
4753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4754 ew32(EECD, eecd);
4755 udelay(1);
4756 }
4757
4758 return E1000_SUCCESS;
4759}
4760
4761
4762
4763
4764
4765
4766static void e1000_standby_eeprom(struct e1000_hw *hw)
4767{
4768 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4769 u32 eecd;
4770
4771 eecd = er32(EECD);
4772
4773 if (eeprom->type == e1000_eeprom_microwire) {
4774 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4775 ew32(EECD, eecd);
4776 E1000_WRITE_FLUSH();
4777 udelay(eeprom->delay_usec);
4778
4779
4780 eecd |= E1000_EECD_SK;
4781 ew32(EECD, eecd);
4782 E1000_WRITE_FLUSH();
4783 udelay(eeprom->delay_usec);
4784
4785
4786 eecd |= E1000_EECD_CS;
4787 ew32(EECD, eecd);
4788 E1000_WRITE_FLUSH();
4789 udelay(eeprom->delay_usec);
4790
4791
4792 eecd &= ~E1000_EECD_SK;
4793 ew32(EECD, eecd);
4794 E1000_WRITE_FLUSH();
4795 udelay(eeprom->delay_usec);
4796 } else if (eeprom->type == e1000_eeprom_spi) {
4797
4798 eecd |= E1000_EECD_CS;
4799 ew32(EECD, eecd);
4800 E1000_WRITE_FLUSH();
4801 udelay(eeprom->delay_usec);
4802 eecd &= ~E1000_EECD_CS;
4803 ew32(EECD, eecd);
4804 E1000_WRITE_FLUSH();
4805 udelay(eeprom->delay_usec);
4806 }
4807}
4808
4809
4810
4811
4812
4813
4814static void e1000_release_eeprom(struct e1000_hw *hw)
4815{
4816 u32 eecd;
4817
4818 DEBUGFUNC("e1000_release_eeprom");
4819
4820 eecd = er32(EECD);
4821
4822 if (hw->eeprom.type == e1000_eeprom_spi) {
4823 eecd |= E1000_EECD_CS;
4824 eecd &= ~E1000_EECD_SK;
4825
4826 ew32(EECD, eecd);
4827
4828 udelay(hw->eeprom.delay_usec);
4829 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4830
4831
4832
4833 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4834
4835 ew32(EECD, eecd);
4836
4837
4838 eecd |= E1000_EECD_SK;
4839 ew32(EECD, eecd);
4840 E1000_WRITE_FLUSH();
4841 udelay(hw->eeprom.delay_usec);
4842
4843
4844 eecd &= ~E1000_EECD_SK;
4845 ew32(EECD, eecd);
4846 E1000_WRITE_FLUSH();
4847 udelay(hw->eeprom.delay_usec);
4848 }
4849
4850
4851 if (hw->mac_type > e1000_82544) {
4852 eecd &= ~E1000_EECD_REQ;
4853 ew32(EECD, eecd);
4854 }
4855
4856 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4857}
4858
4859
4860
4861
4862
4863
4864static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4865{
4866 u16 retry_count = 0;
4867 u8 spi_stat_reg;
4868
4869 DEBUGFUNC("e1000_spi_eeprom_ready");
4870
4871
4872
4873
4874
4875
4876 retry_count = 0;
4877 do {
4878 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4879 hw->eeprom.opcode_bits);
4880 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
4881 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4882 break;
4883
4884 udelay(5);
4885 retry_count += 5;
4886
4887 e1000_standby_eeprom(hw);
4888 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4889
4890
4891
4892
4893 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4894 DEBUGOUT("SPI EEPROM Status error\n");
4895 return -E1000_ERR_EEPROM;
4896 }
4897
4898 return E1000_SUCCESS;
4899}
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4910{
4911 s32 ret;
4912 spin_lock(&e1000_eeprom_lock);
4913 ret = e1000_do_read_eeprom(hw, offset, words, data);
4914 spin_unlock(&e1000_eeprom_lock);
4915 return ret;
4916}
4917
4918static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4919{
4920 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4921 u32 i = 0;
4922
4923 DEBUGFUNC("e1000_read_eeprom");
4924
4925
4926 if (eeprom->word_size == 0)
4927 e1000_init_eeprom_params(hw);
4928
4929
4930
4931
4932 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4933 (words == 0)) {
4934 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4935 return -E1000_ERR_EEPROM;
4936 }
4937
4938
4939
4940
4941
4942 if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
4943
4944 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4945 return -E1000_ERR_EEPROM;
4946 }
4947
4948
4949 if (eeprom->use_eerd)
4950 return e1000_read_eeprom_eerd(hw, offset, words, data);
4951
4952
4953 if (eeprom->type == e1000_eeprom_ich8)
4954 return e1000_read_eeprom_ich8(hw, offset, words, data);
4955
4956
4957
4958 if (eeprom->type == e1000_eeprom_spi) {
4959 u16 word_in;
4960 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
4961
4962 if (e1000_spi_eeprom_ready(hw)) {
4963 e1000_release_eeprom(hw);
4964 return -E1000_ERR_EEPROM;
4965 }
4966
4967 e1000_standby_eeprom(hw);
4968
4969
4970 if ((eeprom->address_bits == 8) && (offset >= 128))
4971 read_opcode |= EEPROM_A8_OPCODE_SPI;
4972
4973
4974 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4975 e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
4976
4977
4978
4979
4980
4981
4982 for (i = 0; i < words; i++) {
4983 word_in = e1000_shift_in_ee_bits(hw, 16);
4984 data[i] = (word_in >> 8) | (word_in << 8);
4985 }
4986 } else if (eeprom->type == e1000_eeprom_microwire) {
4987 for (i = 0; i < words; i++) {
4988
4989 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4990 eeprom->opcode_bits);
4991 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
4992 eeprom->address_bits);
4993
4994
4995
4996 data[i] = e1000_shift_in_ee_bits(hw, 16);
4997 e1000_standby_eeprom(hw);
4998 }
4999 }
5000
5001
5002 e1000_release_eeprom(hw);
5003
5004 return E1000_SUCCESS;
5005}
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
5016 u16 *data)
5017{
5018 u32 i, eerd = 0;
5019 s32 error = 0;
5020
5021 for (i = 0; i < words; i++) {
5022 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5023 E1000_EEPROM_RW_REG_START;
5024
5025 ew32(EERD, eerd);
5026 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5027
5028 if (error) {
5029 break;
5030 }
5031 data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
5032
5033 }
5034
5035 return error;
5036}
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
5047 u16 *data)
5048{
5049 u32 register_value = 0;
5050 u32 i = 0;
5051 s32 error = 0;
5052
5053 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5054 return -E1000_ERR_SWFW_SYNC;
5055
5056 for (i = 0; i < words; i++) {
5057 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5058 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5059 E1000_EEPROM_RW_REG_START;
5060
5061 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5062 if (error) {
5063 break;
5064 }
5065
5066 ew32(EEWR, register_value);
5067
5068 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5069
5070 if (error) {
5071 break;
5072 }
5073 }
5074
5075 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5076 return error;
5077}
5078
5079
5080
5081
5082
5083
5084static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5085{
5086 u32 attempts = 100000;
5087 u32 i, reg = 0;
5088 s32 done = E1000_ERR_EEPROM;
5089
5090 for (i = 0; i < attempts; i++) {
5091 if (eerd == E1000_EEPROM_POLL_READ)
5092 reg = er32(EERD);
5093 else
5094 reg = er32(EEWR);
5095
5096 if (reg & E1000_EEPROM_RW_REG_DONE) {
5097 done = E1000_SUCCESS;
5098 break;
5099 }
5100 udelay(5);
5101 }
5102
5103 return done;
5104}
5105
5106
5107
5108
5109
5110
5111static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5112{
5113 u32 eecd = 0;
5114
5115 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5116
5117 if (hw->mac_type == e1000_ich8lan)
5118 return false;
5119
5120 if (hw->mac_type == e1000_82573) {
5121 eecd = er32(EECD);
5122
5123
5124 eecd = ((eecd >> 15) & 0x03);
5125
5126
5127 if (eecd == 0x03) {
5128 return false;
5129 }
5130 }
5131 return true;
5132}
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5144{
5145 u16 checksum = 0;
5146 u16 i, eeprom_data;
5147
5148 DEBUGFUNC("e1000_validate_eeprom_checksum");
5149
5150 if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
5151
5152
5153 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5154 if ((eeprom_data & 0x10) == 0) {
5155
5156
5157
5158
5159 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5160 if ((eeprom_data & 0x8000) == 0) {
5161 eeprom_data |= 0x8000;
5162 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5163 e1000_update_eeprom_checksum(hw);
5164 }
5165 }
5166 }
5167
5168 if (hw->mac_type == e1000_ich8lan) {
5169
5170
5171
5172
5173
5174 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5175 if ((eeprom_data & 0x40) == 0) {
5176 eeprom_data |= 0x40;
5177 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5178 e1000_update_eeprom_checksum(hw);
5179 }
5180 }
5181
5182 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5183 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5184 DEBUGOUT("EEPROM Read Error\n");
5185 return -E1000_ERR_EEPROM;
5186 }
5187 checksum += eeprom_data;
5188 }
5189
5190 if (checksum == (u16)EEPROM_SUM)
5191 return E1000_SUCCESS;
5192 else {
5193 DEBUGOUT("EEPROM Checksum Invalid\n");
5194 return -E1000_ERR_EEPROM;
5195 }
5196}
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5207{
5208 u32 ctrl_ext;
5209 u16 checksum = 0;
5210 u16 i, eeprom_data;
5211
5212 DEBUGFUNC("e1000_update_eeprom_checksum");
5213
5214 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5215 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5216 DEBUGOUT("EEPROM Read Error\n");
5217 return -E1000_ERR_EEPROM;
5218 }
5219 checksum += eeprom_data;
5220 }
5221 checksum = (u16)EEPROM_SUM - checksum;
5222 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5223 DEBUGOUT("EEPROM Write Error\n");
5224 return -E1000_ERR_EEPROM;
5225 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5226 e1000_commit_shadow_ram(hw);
5227 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5228 e1000_commit_shadow_ram(hw);
5229
5230
5231 ctrl_ext = er32(CTRL_EXT);
5232 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5233 ew32(CTRL_EXT, ctrl_ext);
5234 msleep(10);
5235 }
5236 return E1000_SUCCESS;
5237}
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5251{
5252 s32 ret;
5253 spin_lock(&e1000_eeprom_lock);
5254 ret = e1000_do_write_eeprom(hw, offset, words, data);
5255 spin_unlock(&e1000_eeprom_lock);
5256 return ret;
5257}
5258
5259
5260static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5261{
5262 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5263 s32 status = 0;
5264
5265 DEBUGFUNC("e1000_write_eeprom");
5266
5267
5268 if (eeprom->word_size == 0)
5269 e1000_init_eeprom_params(hw);
5270
5271
5272
5273
5274 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5275 (words == 0)) {
5276 DEBUGOUT("\"words\" parameter out of bounds\n");
5277 return -E1000_ERR_EEPROM;
5278 }
5279
5280
5281 if (eeprom->use_eewr)
5282 return e1000_write_eeprom_eewr(hw, offset, words, data);
5283
5284 if (eeprom->type == e1000_eeprom_ich8)
5285 return e1000_write_eeprom_ich8(hw, offset, words, data);
5286
5287
5288 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5289 return -E1000_ERR_EEPROM;
5290
5291 if (eeprom->type == e1000_eeprom_microwire) {
5292 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5293 } else {
5294 status = e1000_write_eeprom_spi(hw, offset, words, data);
5295 msleep(10);
5296 }
5297
5298
5299 e1000_release_eeprom(hw);
5300
5301 return status;
5302}
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
5314 u16 *data)
5315{
5316 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5317 u16 widx = 0;
5318
5319 DEBUGFUNC("e1000_write_eeprom_spi");
5320
5321 while (widx < words) {
5322 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
5323
5324 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5325
5326 e1000_standby_eeprom(hw);
5327
5328
5329 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5330 eeprom->opcode_bits);
5331
5332 e1000_standby_eeprom(hw);
5333
5334
5335 if ((eeprom->address_bits == 8) && (offset >= 128))
5336 write_opcode |= EEPROM_A8_OPCODE_SPI;
5337
5338
5339 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5340
5341 e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
5342 eeprom->address_bits);
5343
5344
5345
5346
5347 while (widx < words) {
5348 u16 word_out = data[widx];
5349 word_out = (word_out >> 8) | (word_out << 8);
5350 e1000_shift_out_ee_bits(hw, word_out, 16);
5351 widx++;
5352
5353
5354
5355
5356
5357 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5358 e1000_standby_eeprom(hw);
5359 break;
5360 }
5361 }
5362 }
5363
5364 return E1000_SUCCESS;
5365}
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
5377 u16 words, u16 *data)
5378{
5379 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5380 u32 eecd;
5381 u16 words_written = 0;
5382 u16 i = 0;
5383
5384 DEBUGFUNC("e1000_write_eeprom_microwire");
5385
5386
5387
5388
5389
5390
5391
5392 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5393 (u16)(eeprom->opcode_bits + 2));
5394
5395 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5396
5397
5398 e1000_standby_eeprom(hw);
5399
5400 while (words_written < words) {
5401
5402 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5403 eeprom->opcode_bits);
5404
5405 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
5406 eeprom->address_bits);
5407
5408
5409 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5410
5411
5412
5413
5414 e1000_standby_eeprom(hw);
5415
5416
5417
5418
5419
5420 for (i = 0; i < 200; i++) {
5421 eecd = er32(EECD);
5422 if (eecd & E1000_EECD_DO) break;
5423 udelay(50);
5424 }
5425 if (i == 200) {
5426 DEBUGOUT("EEPROM Write did not complete\n");
5427 return -E1000_ERR_EEPROM;
5428 }
5429
5430
5431 e1000_standby_eeprom(hw);
5432
5433 words_written++;
5434 }
5435
5436
5437
5438
5439
5440
5441
5442 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5443 (u16)(eeprom->opcode_bits + 2));
5444
5445 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5446
5447 return E1000_SUCCESS;
5448}
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5461{
5462 u32 attempts = 100000;
5463 u32 eecd = 0;
5464 u32 flop = 0;
5465 u32 i = 0;
5466 s32 error = E1000_SUCCESS;
5467 u32 old_bank_offset = 0;
5468 u32 new_bank_offset = 0;
5469 u8 low_byte = 0;
5470 u8 high_byte = 0;
5471 bool sector_write_failed = false;
5472
5473 if (hw->mac_type == e1000_82573) {
5474
5475 flop = er32(FLOP);
5476 for (i=0; i < attempts; i++) {
5477 eecd = er32(EECD);
5478 if ((eecd & E1000_EECD_FLUPD) == 0) {
5479 break;
5480 }
5481 udelay(5);
5482 }
5483
5484 if (i == attempts) {
5485 return -E1000_ERR_EEPROM;
5486 }
5487
5488
5489 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5490 ew32(HICR, E1000_HICR_FW_RESET);
5491 }
5492
5493
5494 ew32(EECD, eecd | E1000_EECD_FLUPD);
5495
5496 for (i=0; i < attempts; i++) {
5497 eecd = er32(EECD);
5498 if ((eecd & E1000_EECD_FLUPD) == 0) {
5499 break;
5500 }
5501 udelay(5);
5502 }
5503
5504 if (i == attempts) {
5505 return -E1000_ERR_EEPROM;
5506 }
5507 }
5508
5509 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5510
5511
5512
5513 if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
5514 new_bank_offset = hw->flash_bank_size * 2;
5515 old_bank_offset = 0;
5516 e1000_erase_ich8_4k_segment(hw, 1);
5517 } else {
5518 old_bank_offset = hw->flash_bank_size * 2;
5519 new_bank_offset = 0;
5520 e1000_erase_ich8_4k_segment(hw, 0);
5521 }
5522
5523 sector_write_failed = false;
5524
5525
5526 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5527
5528
5529
5530 if (hw->eeprom_shadow_ram[i].modified) {
5531 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
5532 udelay(100);
5533 error = e1000_verify_write_ich8_byte(hw,
5534 (i << 1) + new_bank_offset, low_byte);
5535
5536 if (error != E1000_SUCCESS)
5537 sector_write_failed = true;
5538 else {
5539 high_byte =
5540 (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5541 udelay(100);
5542 }
5543 } else {
5544 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5545 &low_byte);
5546 udelay(100);
5547 error = e1000_verify_write_ich8_byte(hw,
5548 (i << 1) + new_bank_offset, low_byte);
5549
5550 if (error != E1000_SUCCESS)
5551 sector_write_failed = true;
5552 else {
5553 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5554 &high_byte);
5555 udelay(100);
5556 }
5557 }
5558
5559
5560
5561
5562 if (!sector_write_failed) {
5563
5564
5565
5566
5567
5568
5569 if (i == E1000_ICH_NVM_SIG_WORD)
5570 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5571
5572 error = e1000_verify_write_ich8_byte(hw,
5573 (i << 1) + new_bank_offset + 1, high_byte);
5574 if (error != E1000_SUCCESS)
5575 sector_write_failed = true;
5576
5577 } else {
5578
5579
5580 break;
5581 }
5582 }
5583
5584
5585
5586 if (!sector_write_failed) {
5587
5588
5589
5590
5591 e1000_read_ich8_byte(hw,
5592 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5593 &high_byte);
5594 high_byte &= 0xBF;
5595 error = e1000_verify_write_ich8_byte(hw,
5596 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5597
5598
5599
5600
5601 if (error == E1000_SUCCESS) {
5602 error = e1000_verify_write_ich8_byte(hw,
5603 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5604 }
5605
5606
5607 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5608 hw->eeprom_shadow_ram[i].modified = false;
5609 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5610 }
5611 }
5612 }
5613
5614 return error;
5615}
5616
5617
5618
5619
5620
5621
5622
5623s32 e1000_read_mac_addr(struct e1000_hw *hw)
5624{
5625 u16 offset;
5626 u16 eeprom_data, i;
5627
5628 DEBUGFUNC("e1000_read_mac_addr");
5629
5630 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5631 offset = i >> 1;
5632 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5633 DEBUGOUT("EEPROM Read Error\n");
5634 return -E1000_ERR_EEPROM;
5635 }
5636 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
5637 hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
5638 }
5639
5640 switch (hw->mac_type) {
5641 default:
5642 break;
5643 case e1000_82546:
5644 case e1000_82546_rev_3:
5645 case e1000_82571:
5646 case e1000_80003es2lan:
5647 if (er32(STATUS) & E1000_STATUS_FUNC_1)
5648 hw->perm_mac_addr[5] ^= 0x01;
5649 break;
5650 }
5651
5652 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5653 hw->mac_addr[i] = hw->perm_mac_addr[i];
5654 return E1000_SUCCESS;
5655}
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666static void e1000_init_rx_addrs(struct e1000_hw *hw)
5667{
5668 u32 i;
5669 u32 rar_num;
5670
5671 DEBUGFUNC("e1000_init_rx_addrs");
5672
5673
5674 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5675
5676 e1000_rar_set(hw, hw->mac_addr, 0);
5677
5678 rar_num = E1000_RAR_ENTRIES;
5679
5680
5681
5682
5683 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
5684 rar_num -= 1;
5685 if (hw->mac_type == e1000_ich8lan)
5686 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5687
5688
5689 DEBUGOUT("Clearing RAR[1-15]\n");
5690 for (i = 1; i < rar_num; i++) {
5691 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5692 E1000_WRITE_FLUSH();
5693 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5694 E1000_WRITE_FLUSH();
5695 }
5696}
5697
5698
5699
5700
5701
5702
5703
5704u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
5705{
5706 u32 hash_value = 0;
5707
5708
5709
5710
5711 switch (hw->mc_filter_type) {
5712
5713
5714
5715
5716 case 0:
5717 if (hw->mac_type == e1000_ich8lan) {
5718
5719 hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2));
5720 } else {
5721
5722 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5723 }
5724 break;
5725 case 1:
5726 if (hw->mac_type == e1000_ich8lan) {
5727
5728 hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3));
5729 } else {
5730
5731 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
5732 }
5733 break;
5734 case 2:
5735 if (hw->mac_type == e1000_ich8lan) {
5736
5737 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5738 } else {
5739
5740 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5741 }
5742 break;
5743 case 3:
5744 if (hw->mac_type == e1000_ich8lan) {
5745
5746 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5747 } else {
5748
5749 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
5750 }
5751 break;
5752 }
5753
5754 hash_value &= 0xFFF;
5755 if (hw->mac_type == e1000_ich8lan)
5756 hash_value &= 0x3FF;
5757
5758 return hash_value;
5759}
5760
5761
5762
5763
5764
5765
5766
5767void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
5768{
5769 u32 hash_bit, hash_reg;
5770 u32 mta;
5771 u32 temp;
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781 hash_reg = (hash_value >> 5) & 0x7F;
5782 if (hw->mac_type == e1000_ich8lan)
5783 hash_reg &= 0x1F;
5784
5785 hash_bit = hash_value & 0x1F;
5786
5787 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5788
5789 mta |= (1 << hash_bit);
5790
5791
5792
5793
5794
5795 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5796 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5797 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5798 E1000_WRITE_FLUSH();
5799 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5800 E1000_WRITE_FLUSH();
5801 } else {
5802 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5803 E1000_WRITE_FLUSH();
5804 }
5805}
5806
5807
5808
5809
5810
5811
5812
5813
5814void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
5815{
5816 u32 rar_low, rar_high;
5817
5818
5819
5820
5821 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
5822 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
5823 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843 switch (hw->mac_type) {
5844 case e1000_82571:
5845 case e1000_82572:
5846 case e1000_80003es2lan:
5847 if (hw->leave_av_bit_off)
5848 break;
5849 default:
5850
5851 rar_high |= E1000_RAH_AV;
5852 break;
5853 }
5854
5855 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5856 E1000_WRITE_FLUSH();
5857 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5858 E1000_WRITE_FLUSH();
5859}
5860
5861
5862
5863
5864
5865
5866
5867
5868void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5869{
5870 u32 temp;
5871
5872 if (hw->mac_type == e1000_ich8lan)
5873 return;
5874
5875 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5876 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5877 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5878 E1000_WRITE_FLUSH();
5879 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5880 E1000_WRITE_FLUSH();
5881 } else {
5882 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5883 E1000_WRITE_FLUSH();
5884 }
5885}
5886
5887
5888
5889
5890
5891
5892static void e1000_clear_vfta(struct e1000_hw *hw)
5893{
5894 u32 offset;
5895 u32 vfta_value = 0;
5896 u32 vfta_offset = 0;
5897 u32 vfta_bit_in_reg = 0;
5898
5899 if (hw->mac_type == e1000_ich8lan)
5900 return;
5901
5902 if (hw->mac_type == e1000_82573) {
5903 if (hw->mng_cookie.vlan_id != 0) {
5904
5905
5906
5907
5908 vfta_offset = (hw->mng_cookie.vlan_id >>
5909 E1000_VFTA_ENTRY_SHIFT) &
5910 E1000_VFTA_ENTRY_MASK;
5911 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5912 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5913 }
5914 }
5915 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5916
5917
5918
5919 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5920 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5921 E1000_WRITE_FLUSH();
5922 }
5923}
5924
5925static s32 e1000_id_led_init(struct e1000_hw *hw)
5926{
5927 u32 ledctl;
5928 const u32 ledctl_mask = 0x000000FF;
5929 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5930 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5931 u16 eeprom_data, i, temp;
5932 const u16 led_mask = 0x0F;
5933
5934 DEBUGFUNC("e1000_id_led_init");
5935
5936 if (hw->mac_type < e1000_82540) {
5937
5938 return E1000_SUCCESS;
5939 }
5940
5941 ledctl = er32(LEDCTL);
5942 hw->ledctl_default = ledctl;
5943 hw->ledctl_mode1 = hw->ledctl_default;
5944 hw->ledctl_mode2 = hw->ledctl_default;
5945
5946 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5947 DEBUGOUT("EEPROM Read Error\n");
5948 return -E1000_ERR_EEPROM;
5949 }
5950
5951 if ((hw->mac_type == e1000_82573) &&
5952 (eeprom_data == ID_LED_RESERVED_82573))
5953 eeprom_data = ID_LED_DEFAULT_82573;
5954 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5955 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5956 if (hw->mac_type == e1000_ich8lan)
5957 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5958 else
5959 eeprom_data = ID_LED_DEFAULT;
5960 }
5961
5962 for (i = 0; i < 4; i++) {
5963 temp = (eeprom_data >> (i << 2)) & led_mask;
5964 switch (temp) {
5965 case ID_LED_ON1_DEF2:
5966 case ID_LED_ON1_ON2:
5967 case ID_LED_ON1_OFF2:
5968 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5969 hw->ledctl_mode1 |= ledctl_on << (i << 3);
5970 break;
5971 case ID_LED_OFF1_DEF2:
5972 case ID_LED_OFF1_ON2:
5973 case ID_LED_OFF1_OFF2:
5974 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5975 hw->ledctl_mode1 |= ledctl_off << (i << 3);
5976 break;
5977 default:
5978
5979 break;
5980 }
5981 switch (temp) {
5982 case ID_LED_DEF1_ON2:
5983 case ID_LED_ON1_ON2:
5984 case ID_LED_OFF1_ON2:
5985 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5986 hw->ledctl_mode2 |= ledctl_on << (i << 3);
5987 break;
5988 case ID_LED_DEF1_OFF2:
5989 case ID_LED_ON1_OFF2:
5990 case ID_LED_OFF1_OFF2:
5991 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5992 hw->ledctl_mode2 |= ledctl_off << (i << 3);
5993 break;
5994 default:
5995
5996 break;
5997 }
5998 }
5999 return E1000_SUCCESS;
6000}
6001
6002
6003
6004
6005
6006
6007s32 e1000_setup_led(struct e1000_hw *hw)
6008{
6009 u32 ledctl;
6010 s32 ret_val = E1000_SUCCESS;
6011
6012 DEBUGFUNC("e1000_setup_led");
6013
6014 switch (hw->mac_type) {
6015 case e1000_82542_rev2_0:
6016 case e1000_82542_rev2_1:
6017 case e1000_82543:
6018 case e1000_82544:
6019
6020 break;
6021 case e1000_82541:
6022 case e1000_82547:
6023 case e1000_82541_rev_2:
6024 case e1000_82547_rev_2:
6025
6026 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6027 &hw->phy_spd_default);
6028 if (ret_val)
6029 return ret_val;
6030 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6031 (u16)(hw->phy_spd_default &
6032 ~IGP01E1000_GMII_SPD));
6033 if (ret_val)
6034 return ret_val;
6035
6036 default:
6037 if (hw->media_type == e1000_media_type_fiber) {
6038 ledctl = er32(LEDCTL);
6039
6040 hw->ledctl_default = ledctl;
6041
6042 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6043 E1000_LEDCTL_LED0_BLINK |
6044 E1000_LEDCTL_LED0_MODE_MASK);
6045 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6046 E1000_LEDCTL_LED0_MODE_SHIFT);
6047 ew32(LEDCTL, ledctl);
6048 } else if (hw->media_type == e1000_media_type_copper)
6049 ew32(LEDCTL, hw->ledctl_mode1);
6050 break;
6051 }
6052
6053 return E1000_SUCCESS;
6054}
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065s32 e1000_blink_led_start(struct e1000_hw *hw)
6066{
6067 s16 i;
6068 u32 ledctl_blink = 0;
6069
6070 DEBUGFUNC("e1000_id_led_blink_on");
6071
6072 if (hw->mac_type < e1000_82571) {
6073
6074 return E1000_SUCCESS;
6075 }
6076 if (hw->media_type == e1000_media_type_fiber) {
6077
6078 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6079 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6080 } else {
6081
6082 ledctl_blink = hw->ledctl_mode2;
6083 for (i=0; i < 4; i++)
6084 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6085 E1000_LEDCTL_MODE_LED_ON)
6086 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6087 }
6088
6089 ew32(LEDCTL, ledctl_blink);
6090
6091 return E1000_SUCCESS;
6092}
6093
6094
6095
6096
6097
6098
6099s32 e1000_cleanup_led(struct e1000_hw *hw)
6100{
6101 s32 ret_val = E1000_SUCCESS;
6102
6103 DEBUGFUNC("e1000_cleanup_led");
6104
6105 switch (hw->mac_type) {
6106 case e1000_82542_rev2_0:
6107 case e1000_82542_rev2_1:
6108 case e1000_82543:
6109 case e1000_82544:
6110
6111 break;
6112 case e1000_82541:
6113 case e1000_82547:
6114 case e1000_82541_rev_2:
6115 case e1000_82547_rev_2:
6116
6117 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6118 hw->phy_spd_default);
6119 if (ret_val)
6120 return ret_val;
6121
6122 default:
6123 if (hw->phy_type == e1000_phy_ife) {
6124 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6125 break;
6126 }
6127
6128 ew32(LEDCTL, hw->ledctl_default);
6129 break;
6130 }
6131
6132 return E1000_SUCCESS;
6133}
6134
6135
6136
6137
6138
6139
6140s32 e1000_led_on(struct e1000_hw *hw)
6141{
6142 u32 ctrl = er32(CTRL);
6143
6144 DEBUGFUNC("e1000_led_on");
6145
6146 switch (hw->mac_type) {
6147 case e1000_82542_rev2_0:
6148 case e1000_82542_rev2_1:
6149 case e1000_82543:
6150
6151 ctrl |= E1000_CTRL_SWDPIN0;
6152 ctrl |= E1000_CTRL_SWDPIO0;
6153 break;
6154 case e1000_82544:
6155 if (hw->media_type == e1000_media_type_fiber) {
6156
6157 ctrl |= E1000_CTRL_SWDPIN0;
6158 ctrl |= E1000_CTRL_SWDPIO0;
6159 } else {
6160
6161 ctrl &= ~E1000_CTRL_SWDPIN0;
6162 ctrl |= E1000_CTRL_SWDPIO0;
6163 }
6164 break;
6165 default:
6166 if (hw->media_type == e1000_media_type_fiber) {
6167
6168 ctrl &= ~E1000_CTRL_SWDPIN0;
6169 ctrl |= E1000_CTRL_SWDPIO0;
6170 } else if (hw->phy_type == e1000_phy_ife) {
6171 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6172 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6173 } else if (hw->media_type == e1000_media_type_copper) {
6174 ew32(LEDCTL, hw->ledctl_mode2);
6175 return E1000_SUCCESS;
6176 }
6177 break;
6178 }
6179
6180 ew32(CTRL, ctrl);
6181
6182 return E1000_SUCCESS;
6183}
6184
6185
6186
6187
6188
6189
6190s32 e1000_led_off(struct e1000_hw *hw)
6191{
6192 u32 ctrl = er32(CTRL);
6193
6194 DEBUGFUNC("e1000_led_off");
6195
6196 switch (hw->mac_type) {
6197 case e1000_82542_rev2_0:
6198 case e1000_82542_rev2_1:
6199 case e1000_82543:
6200
6201 ctrl &= ~E1000_CTRL_SWDPIN0;
6202 ctrl |= E1000_CTRL_SWDPIO0;
6203 break;
6204 case e1000_82544:
6205 if (hw->media_type == e1000_media_type_fiber) {
6206
6207 ctrl &= ~E1000_CTRL_SWDPIN0;
6208 ctrl |= E1000_CTRL_SWDPIO0;
6209 } else {
6210
6211 ctrl |= E1000_CTRL_SWDPIN0;
6212 ctrl |= E1000_CTRL_SWDPIO0;
6213 }
6214 break;
6215 default:
6216 if (hw->media_type == e1000_media_type_fiber) {
6217
6218 ctrl |= E1000_CTRL_SWDPIN0;
6219 ctrl |= E1000_CTRL_SWDPIO0;
6220 } else if (hw->phy_type == e1000_phy_ife) {
6221 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6222 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6223 } else if (hw->media_type == e1000_media_type_copper) {
6224 ew32(LEDCTL, hw->ledctl_mode1);
6225 return E1000_SUCCESS;
6226 }
6227 break;
6228 }
6229
6230 ew32(CTRL, ctrl);
6231
6232 return E1000_SUCCESS;
6233}
6234
6235
6236
6237
6238
6239
6240static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6241{
6242 volatile u32 temp;
6243
6244 temp = er32(CRCERRS);
6245 temp = er32(SYMERRS);
6246 temp = er32(MPC);
6247 temp = er32(SCC);
6248 temp = er32(ECOL);
6249 temp = er32(MCC);
6250 temp = er32(LATECOL);
6251 temp = er32(COLC);
6252 temp = er32(DC);
6253 temp = er32(SEC);
6254 temp = er32(RLEC);
6255 temp = er32(XONRXC);
6256 temp = er32(XONTXC);
6257 temp = er32(XOFFRXC);
6258 temp = er32(XOFFTXC);
6259 temp = er32(FCRUC);
6260
6261 if (hw->mac_type != e1000_ich8lan) {
6262 temp = er32(PRC64);
6263 temp = er32(PRC127);
6264 temp = er32(PRC255);
6265 temp = er32(PRC511);
6266 temp = er32(PRC1023);
6267 temp = er32(PRC1522);
6268 }
6269
6270 temp = er32(GPRC);
6271 temp = er32(BPRC);
6272 temp = er32(MPRC);
6273 temp = er32(GPTC);
6274 temp = er32(GORCL);
6275 temp = er32(GORCH);
6276 temp = er32(GOTCL);
6277 temp = er32(GOTCH);
6278 temp = er32(RNBC);
6279 temp = er32(RUC);
6280 temp = er32(RFC);
6281 temp = er32(ROC);
6282 temp = er32(RJC);
6283 temp = er32(TORL);
6284 temp = er32(TORH);
6285 temp = er32(TOTL);
6286 temp = er32(TOTH);
6287 temp = er32(TPR);
6288 temp = er32(TPT);
6289
6290 if (hw->mac_type != e1000_ich8lan) {
6291 temp = er32(PTC64);
6292 temp = er32(PTC127);
6293 temp = er32(PTC255);
6294 temp = er32(PTC511);
6295 temp = er32(PTC1023);
6296 temp = er32(PTC1522);
6297 }
6298
6299 temp = er32(MPTC);
6300 temp = er32(BPTC);
6301
6302 if (hw->mac_type < e1000_82543) return;
6303
6304 temp = er32(ALGNERRC);
6305 temp = er32(RXERRC);
6306 temp = er32(TNCRS);
6307 temp = er32(CEXTERR);
6308 temp = er32(TSCTC);
6309 temp = er32(TSCTFC);
6310
6311 if (hw->mac_type <= e1000_82544) return;
6312
6313 temp = er32(MGTPRC);
6314 temp = er32(MGTPDC);
6315 temp = er32(MGTPTC);
6316
6317 if (hw->mac_type <= e1000_82547_rev_2) return;
6318
6319 temp = er32(IAC);
6320 temp = er32(ICRXOC);
6321
6322 if (hw->mac_type == e1000_ich8lan) return;
6323
6324 temp = er32(ICRXPTC);
6325 temp = er32(ICRXATC);
6326 temp = er32(ICTXPTC);
6327 temp = er32(ICTXATC);
6328 temp = er32(ICTXQEC);
6329 temp = er32(ICTXQMTC);
6330 temp = er32(ICRXDMTC);
6331}
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343void e1000_reset_adaptive(struct e1000_hw *hw)
6344{
6345 DEBUGFUNC("e1000_reset_adaptive");
6346
6347 if (hw->adaptive_ifs) {
6348 if (!hw->ifs_params_forced) {
6349 hw->current_ifs_val = 0;
6350 hw->ifs_min_val = IFS_MIN;
6351 hw->ifs_max_val = IFS_MAX;
6352 hw->ifs_step_size = IFS_STEP;
6353 hw->ifs_ratio = IFS_RATIO;
6354 }
6355 hw->in_ifs_mode = false;
6356 ew32(AIT, 0);
6357 } else {
6358 DEBUGOUT("Not in Adaptive IFS mode!\n");
6359 }
6360}
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370void e1000_update_adaptive(struct e1000_hw *hw)
6371{
6372 DEBUGFUNC("e1000_update_adaptive");
6373
6374 if (hw->adaptive_ifs) {
6375 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6376 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6377 hw->in_ifs_mode = true;
6378 if (hw->current_ifs_val < hw->ifs_max_val) {
6379 if (hw->current_ifs_val == 0)
6380 hw->current_ifs_val = hw->ifs_min_val;
6381 else
6382 hw->current_ifs_val += hw->ifs_step_size;
6383 ew32(AIT, hw->current_ifs_val);
6384 }
6385 }
6386 } else {
6387 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6388 hw->current_ifs_val = 0;
6389 hw->in_ifs_mode = false;
6390 ew32(AIT, 0);
6391 }
6392 }
6393 } else {
6394 DEBUGOUT("Not in Adaptive IFS mode!\n");
6395 }
6396}
6397
6398
6399
6400
6401
6402
6403
6404
6405void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
6406 u32 frame_len, u8 *mac_addr)
6407{
6408 u64 carry_bit;
6409
6410
6411 frame_len--;
6412
6413
6414
6415
6416
6417 stats->crcerrs--;
6418
6419 stats->gprc++;
6420
6421
6422 carry_bit = 0x80000000 & stats->gorcl;
6423 stats->gorcl += frame_len;
6424
6425
6426
6427
6428
6429
6430
6431 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6432 stats->gorch++;
6433
6434
6435
6436
6437 if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
6438
6439 stats->bprc++;
6440 else if (*mac_addr & 0x01)
6441
6442 stats->mprc++;
6443
6444 if (frame_len == hw->max_frame_size) {
6445
6446
6447
6448 if (stats->roc > 0)
6449 stats->roc--;
6450 }
6451
6452
6453
6454
6455 if (frame_len == 64) {
6456 stats->prc64++;
6457 stats->prc127--;
6458 } else if (frame_len == 127) {
6459 stats->prc127++;
6460 stats->prc255--;
6461 } else if (frame_len == 255) {
6462 stats->prc255++;
6463 stats->prc511--;
6464 } else if (frame_len == 511) {
6465 stats->prc511++;
6466 stats->prc1023--;
6467 } else if (frame_len == 1023) {
6468 stats->prc1023++;
6469 stats->prc1522--;
6470 } else if (frame_len == 1522) {
6471 stats->prc1522++;
6472 }
6473}
6474
6475
6476
6477
6478
6479
6480void e1000_get_bus_info(struct e1000_hw *hw)
6481{
6482 s32 ret_val;
6483 u16 pci_ex_link_status;
6484 u32 status;
6485
6486 switch (hw->mac_type) {
6487 case e1000_82542_rev2_0:
6488 case e1000_82542_rev2_1:
6489 hw->bus_type = e1000_bus_type_pci;
6490 hw->bus_speed = e1000_bus_speed_unknown;
6491 hw->bus_width = e1000_bus_width_unknown;
6492 break;
6493 case e1000_82571:
6494 case e1000_82572:
6495 case e1000_82573:
6496 case e1000_80003es2lan:
6497 hw->bus_type = e1000_bus_type_pci_express;
6498 hw->bus_speed = e1000_bus_speed_2500;
6499 ret_val = e1000_read_pcie_cap_reg(hw,
6500 PCI_EX_LINK_STATUS,
6501 &pci_ex_link_status);
6502 if (ret_val)
6503 hw->bus_width = e1000_bus_width_unknown;
6504 else
6505 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6506 PCI_EX_LINK_WIDTH_SHIFT;
6507 break;
6508 case e1000_ich8lan:
6509 hw->bus_type = e1000_bus_type_pci_express;
6510 hw->bus_speed = e1000_bus_speed_2500;
6511 hw->bus_width = e1000_bus_width_pciex_1;
6512 break;
6513 default:
6514 status = er32(STATUS);
6515 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6516 e1000_bus_type_pcix : e1000_bus_type_pci;
6517
6518 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6519 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6520 e1000_bus_speed_66 : e1000_bus_speed_120;
6521 } else if (hw->bus_type == e1000_bus_type_pci) {
6522 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6523 e1000_bus_speed_66 : e1000_bus_speed_33;
6524 } else {
6525 switch (status & E1000_STATUS_PCIX_SPEED) {
6526 case E1000_STATUS_PCIX_SPEED_66:
6527 hw->bus_speed = e1000_bus_speed_66;
6528 break;
6529 case E1000_STATUS_PCIX_SPEED_100:
6530 hw->bus_speed = e1000_bus_speed_100;
6531 break;
6532 case E1000_STATUS_PCIX_SPEED_133:
6533 hw->bus_speed = e1000_bus_speed_133;
6534 break;
6535 default:
6536 hw->bus_speed = e1000_bus_speed_reserved;
6537 break;
6538 }
6539 }
6540 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6541 e1000_bus_width_64 : e1000_bus_width_32;
6542 break;
6543 }
6544}
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
6555{
6556 unsigned long io_addr = hw->io_base;
6557 unsigned long io_data = hw->io_base + 4;
6558
6559 e1000_io_write(hw, io_addr, offset);
6560 e1000_io_write(hw, io_data, value);
6561}
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6579 u16 *max_length)
6580{
6581 s32 ret_val;
6582 u16 agc_value = 0;
6583 u16 i, phy_data;
6584 u16 cable_length;
6585
6586 DEBUGFUNC("e1000_get_cable_length");
6587
6588 *min_length = *max_length = 0;
6589
6590
6591 if (hw->phy_type == e1000_phy_m88) {
6592
6593 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6594 &phy_data);
6595 if (ret_val)
6596 return ret_val;
6597 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6598 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6599
6600
6601 switch (cable_length) {
6602 case e1000_cable_length_50:
6603 *min_length = 0;
6604 *max_length = e1000_igp_cable_length_50;
6605 break;
6606 case e1000_cable_length_50_80:
6607 *min_length = e1000_igp_cable_length_50;
6608 *max_length = e1000_igp_cable_length_80;
6609 break;
6610 case e1000_cable_length_80_110:
6611 *min_length = e1000_igp_cable_length_80;
6612 *max_length = e1000_igp_cable_length_110;
6613 break;
6614 case e1000_cable_length_110_140:
6615 *min_length = e1000_igp_cable_length_110;
6616 *max_length = e1000_igp_cable_length_140;
6617 break;
6618 case e1000_cable_length_140:
6619 *min_length = e1000_igp_cable_length_140;
6620 *max_length = e1000_igp_cable_length_170;
6621 break;
6622 default:
6623 return -E1000_ERR_PHY;
6624 break;
6625 }
6626 } else if (hw->phy_type == e1000_phy_gg82563) {
6627 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6628 &phy_data);
6629 if (ret_val)
6630 return ret_val;
6631 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6632
6633 switch (cable_length) {
6634 case e1000_gg_cable_length_60:
6635 *min_length = 0;
6636 *max_length = e1000_igp_cable_length_60;
6637 break;
6638 case e1000_gg_cable_length_60_115:
6639 *min_length = e1000_igp_cable_length_60;
6640 *max_length = e1000_igp_cable_length_115;
6641 break;
6642 case e1000_gg_cable_length_115_150:
6643 *min_length = e1000_igp_cable_length_115;
6644 *max_length = e1000_igp_cable_length_150;
6645 break;
6646 case e1000_gg_cable_length_150:
6647 *min_length = e1000_igp_cable_length_150;
6648 *max_length = e1000_igp_cable_length_180;
6649 break;
6650 default:
6651 return -E1000_ERR_PHY;
6652 break;
6653 }
6654 } else if (hw->phy_type == e1000_phy_igp) {
6655 u16 cur_agc_value;
6656 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6657 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6658 {IGP01E1000_PHY_AGC_A,
6659 IGP01E1000_PHY_AGC_B,
6660 IGP01E1000_PHY_AGC_C,
6661 IGP01E1000_PHY_AGC_D};
6662
6663 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6664
6665 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6666 if (ret_val)
6667 return ret_val;
6668
6669 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6670
6671
6672 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6673 (cur_agc_value == 0))
6674 return -E1000_ERR_PHY;
6675
6676 agc_value += cur_agc_value;
6677
6678
6679 if (min_agc_value > cur_agc_value)
6680 min_agc_value = cur_agc_value;
6681 }
6682
6683
6684 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6685 agc_value -= min_agc_value;
6686
6687
6688 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6689 } else {
6690
6691 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6692 }
6693
6694
6695 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6696 IGP01E1000_AGC_RANGE) > 0) ?
6697 (e1000_igp_cable_length_table[agc_value] -
6698 IGP01E1000_AGC_RANGE) : 0;
6699 *max_length = e1000_igp_cable_length_table[agc_value] +
6700 IGP01E1000_AGC_RANGE;
6701 } else if (hw->phy_type == e1000_phy_igp_2 ||
6702 hw->phy_type == e1000_phy_igp_3) {
6703 u16 cur_agc_index, max_agc_index = 0;
6704 u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6705 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6706 {IGP02E1000_PHY_AGC_A,
6707 IGP02E1000_PHY_AGC_B,
6708 IGP02E1000_PHY_AGC_C,
6709 IGP02E1000_PHY_AGC_D};
6710
6711 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6712 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6713 if (ret_val)
6714 return ret_val;
6715
6716
6717
6718
6719 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6720 IGP02E1000_AGC_LENGTH_MASK;
6721
6722
6723 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6724 (cur_agc_index == 0))
6725 return -E1000_ERR_PHY;
6726
6727
6728 if (e1000_igp_2_cable_length_table[min_agc_index] >
6729 e1000_igp_2_cable_length_table[cur_agc_index])
6730 min_agc_index = cur_agc_index;
6731 if (e1000_igp_2_cable_length_table[max_agc_index] <
6732 e1000_igp_2_cable_length_table[cur_agc_index])
6733 max_agc_index = cur_agc_index;
6734
6735 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6736 }
6737
6738 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6739 e1000_igp_2_cable_length_table[max_agc_index]);
6740 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6741
6742
6743 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6744 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6745 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6746 }
6747
6748 return E1000_SUCCESS;
6749}
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764
6765
6766
6767static s32 e1000_check_polarity(struct e1000_hw *hw,
6768 e1000_rev_polarity *polarity)
6769{
6770 s32 ret_val;
6771 u16 phy_data;
6772
6773 DEBUGFUNC("e1000_check_polarity");
6774
6775 if ((hw->phy_type == e1000_phy_m88) ||
6776 (hw->phy_type == e1000_phy_gg82563)) {
6777
6778 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6779 &phy_data);
6780 if (ret_val)
6781 return ret_val;
6782 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6783 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6784 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6785
6786 } else if (hw->phy_type == e1000_phy_igp ||
6787 hw->phy_type == e1000_phy_igp_3 ||
6788 hw->phy_type == e1000_phy_igp_2) {
6789
6790 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6791 &phy_data);
6792 if (ret_val)
6793 return ret_val;
6794
6795
6796
6797 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6798 IGP01E1000_PSSR_SPEED_1000MBPS) {
6799
6800
6801 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6802 &phy_data);
6803 if (ret_val)
6804 return ret_val;
6805
6806
6807 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6808 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6809 } else {
6810
6811
6812 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6813 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6814 }
6815 } else if (hw->phy_type == e1000_phy_ife) {
6816 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6817 &phy_data);
6818 if (ret_val)
6819 return ret_val;
6820 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6821 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6822 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6823 }
6824 return E1000_SUCCESS;
6825}
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839
6840
6841
6842static s32 e1000_check_downshift(struct e1000_hw *hw)
6843{
6844 s32 ret_val;
6845 u16 phy_data;
6846
6847 DEBUGFUNC("e1000_check_downshift");
6848
6849 if (hw->phy_type == e1000_phy_igp ||
6850 hw->phy_type == e1000_phy_igp_3 ||
6851 hw->phy_type == e1000_phy_igp_2) {
6852 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6853 &phy_data);
6854 if (ret_val)
6855 return ret_val;
6856
6857 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6858 } else if ((hw->phy_type == e1000_phy_m88) ||
6859 (hw->phy_type == e1000_phy_gg82563)) {
6860 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6861 &phy_data);
6862 if (ret_val)
6863 return ret_val;
6864
6865 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6866 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6867 } else if (hw->phy_type == e1000_phy_ife) {
6868
6869 hw->speed_downgraded = false;
6870 }
6871
6872 return E1000_SUCCESS;
6873}
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
6888{
6889 s32 ret_val;
6890 u16 phy_data, phy_saved_data, speed, duplex, i;
6891 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6892 {IGP01E1000_PHY_AGC_PARAM_A,
6893 IGP01E1000_PHY_AGC_PARAM_B,
6894 IGP01E1000_PHY_AGC_PARAM_C,
6895 IGP01E1000_PHY_AGC_PARAM_D};
6896 u16 min_length, max_length;
6897
6898 DEBUGFUNC("e1000_config_dsp_after_link_change");
6899
6900 if (hw->phy_type != e1000_phy_igp)
6901 return E1000_SUCCESS;
6902
6903 if (link_up) {
6904 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6905 if (ret_val) {
6906 DEBUGOUT("Error getting link speed and duplex\n");
6907 return ret_val;
6908 }
6909
6910 if (speed == SPEED_1000) {
6911
6912 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6913 if (ret_val)
6914 return ret_val;
6915
6916 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6917 min_length >= e1000_igp_cable_length_50) {
6918
6919 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6920 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6921 &phy_data);
6922 if (ret_val)
6923 return ret_val;
6924
6925 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6926
6927 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6928 phy_data);
6929 if (ret_val)
6930 return ret_val;
6931 }
6932 hw->dsp_config_state = e1000_dsp_config_activated;
6933 }
6934
6935 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6936 (min_length < e1000_igp_cable_length_50)) {
6937
6938 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6939 u32 idle_errs = 0;
6940
6941
6942 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6943 &phy_data);
6944 if (ret_val)
6945 return ret_val;
6946
6947 for (i = 0; i < ffe_idle_err_timeout; i++) {
6948 udelay(1000);
6949 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6950 &phy_data);
6951 if (ret_val)
6952 return ret_val;
6953
6954 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
6955 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
6956 hw->ffe_config_state = e1000_ffe_config_active;
6957
6958 ret_val = e1000_write_phy_reg(hw,
6959 IGP01E1000_PHY_DSP_FFE,
6960 IGP01E1000_PHY_DSP_FFE_CM_CP);
6961 if (ret_val)
6962 return ret_val;
6963 break;
6964 }
6965
6966 if (idle_errs)
6967 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
6968 }
6969 }
6970 }
6971 } else {
6972 if (hw->dsp_config_state == e1000_dsp_config_activated) {
6973
6974
6975 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6976
6977 if (ret_val)
6978 return ret_val;
6979
6980
6981 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6982
6983 if (ret_val)
6984 return ret_val;
6985
6986 mdelay(20);
6987
6988 ret_val = e1000_write_phy_reg(hw, 0x0000,
6989 IGP01E1000_IEEE_FORCE_GIGA);
6990 if (ret_val)
6991 return ret_val;
6992 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6993 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
6994 if (ret_val)
6995 return ret_val;
6996
6997 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6998 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
6999
7000 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7001 if (ret_val)
7002 return ret_val;
7003 }
7004
7005 ret_val = e1000_write_phy_reg(hw, 0x0000,
7006 IGP01E1000_IEEE_RESTART_AUTONEG);
7007 if (ret_val)
7008 return ret_val;
7009
7010 mdelay(20);
7011
7012
7013 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7014
7015 if (ret_val)
7016 return ret_val;
7017
7018 hw->dsp_config_state = e1000_dsp_config_enabled;
7019 }
7020
7021 if (hw->ffe_config_state == e1000_ffe_config_active) {
7022
7023
7024 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7025
7026 if (ret_val)
7027 return ret_val;
7028
7029
7030 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7031
7032 if (ret_val)
7033 return ret_val;
7034
7035 mdelay(20);
7036
7037 ret_val = e1000_write_phy_reg(hw, 0x0000,
7038 IGP01E1000_IEEE_FORCE_GIGA);
7039 if (ret_val)
7040 return ret_val;
7041 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7042 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7043 if (ret_val)
7044 return ret_val;
7045
7046 ret_val = e1000_write_phy_reg(hw, 0x0000,
7047 IGP01E1000_IEEE_RESTART_AUTONEG);
7048 if (ret_val)
7049 return ret_val;
7050
7051 mdelay(20);
7052
7053
7054 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7055
7056 if (ret_val)
7057 return ret_val;
7058
7059 hw->ffe_config_state = e1000_ffe_config_enabled;
7060 }
7061 }
7062 return E1000_SUCCESS;
7063}
7064
7065
7066
7067
7068
7069
7070
7071
7072
7073static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7074{
7075 s32 ret_val;
7076 u16 eeprom_data;
7077
7078 DEBUGFUNC("e1000_set_phy_mode");
7079
7080 if ((hw->mac_type == e1000_82545_rev_3) &&
7081 (hw->media_type == e1000_media_type_copper)) {
7082 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7083 if (ret_val) {
7084 return ret_val;
7085 }
7086
7087 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7088 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7089 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7090 if (ret_val)
7091 return ret_val;
7092 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7093 if (ret_val)
7094 return ret_val;
7095
7096 hw->phy_reset_disable = false;
7097 }
7098 }
7099
7100 return E1000_SUCCESS;
7101}
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7118{
7119 u32 phy_ctrl = 0;
7120 s32 ret_val;
7121 u16 phy_data;
7122 DEBUGFUNC("e1000_set_d3_lplu_state");
7123
7124 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7125 && hw->phy_type != e1000_phy_igp_3)
7126 return E1000_SUCCESS;
7127
7128
7129
7130
7131 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7132 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7133 if (ret_val)
7134 return ret_val;
7135 } else if (hw->mac_type == e1000_ich8lan) {
7136
7137
7138
7139 phy_ctrl = er32(PHY_CTRL);
7140 } else {
7141 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7142 if (ret_val)
7143 return ret_val;
7144 }
7145
7146 if (!active) {
7147 if (hw->mac_type == e1000_82541_rev_2 ||
7148 hw->mac_type == e1000_82547_rev_2) {
7149 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7150 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7151 if (ret_val)
7152 return ret_val;
7153 } else {
7154 if (hw->mac_type == e1000_ich8lan) {
7155 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7156 ew32(PHY_CTRL, phy_ctrl);
7157 } else {
7158 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7159 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7160 phy_data);
7161 if (ret_val)
7162 return ret_val;
7163 }
7164 }
7165
7166
7167
7168
7169
7170 if (hw->smart_speed == e1000_smart_speed_on) {
7171 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7172 &phy_data);
7173 if (ret_val)
7174 return ret_val;
7175
7176 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7177 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7178 phy_data);
7179 if (ret_val)
7180 return ret_val;
7181 } else if (hw->smart_speed == e1000_smart_speed_off) {
7182 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7183 &phy_data);
7184 if (ret_val)
7185 return ret_val;
7186
7187 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7188 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7189 phy_data);
7190 if (ret_val)
7191 return ret_val;
7192 }
7193
7194 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7195 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7196 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7197
7198 if (hw->mac_type == e1000_82541_rev_2 ||
7199 hw->mac_type == e1000_82547_rev_2) {
7200 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7201 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7202 if (ret_val)
7203 return ret_val;
7204 } else {
7205 if (hw->mac_type == e1000_ich8lan) {
7206 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7207 ew32(PHY_CTRL, phy_ctrl);
7208 } else {
7209 phy_data |= IGP02E1000_PM_D3_LPLU;
7210 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7211 phy_data);
7212 if (ret_val)
7213 return ret_val;
7214 }
7215 }
7216
7217
7218 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7219 if (ret_val)
7220 return ret_val;
7221
7222 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7223 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7224 if (ret_val)
7225 return ret_val;
7226
7227 }
7228 return E1000_SUCCESS;
7229}
7230
7231
7232
7233
7234
7235
7236
7237
7238
7239
7240
7241
7242
7243
7244
7245static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7246{
7247 u32 phy_ctrl = 0;
7248 s32 ret_val;
7249 u16 phy_data;
7250 DEBUGFUNC("e1000_set_d0_lplu_state");
7251
7252 if (hw->mac_type <= e1000_82547_rev_2)
7253 return E1000_SUCCESS;
7254
7255 if (hw->mac_type == e1000_ich8lan) {
7256 phy_ctrl = er32(PHY_CTRL);
7257 } else {
7258 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7259 if (ret_val)
7260 return ret_val;
7261 }
7262
7263 if (!active) {
7264 if (hw->mac_type == e1000_ich8lan) {
7265 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7266 ew32(PHY_CTRL, phy_ctrl);
7267 } else {
7268 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7269 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7270 if (ret_val)
7271 return ret_val;
7272 }
7273
7274
7275
7276
7277
7278 if (hw->smart_speed == e1000_smart_speed_on) {
7279 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7280 &phy_data);
7281 if (ret_val)
7282 return ret_val;
7283
7284 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7285 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7286 phy_data);
7287 if (ret_val)
7288 return ret_val;
7289 } else if (hw->smart_speed == e1000_smart_speed_off) {
7290 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7291 &phy_data);
7292 if (ret_val)
7293 return ret_val;
7294
7295 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7296 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7297 phy_data);
7298 if (ret_val)
7299 return ret_val;
7300 }
7301
7302
7303 } else {
7304
7305 if (hw->mac_type == e1000_ich8lan) {
7306 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7307 ew32(PHY_CTRL, phy_ctrl);
7308 } else {
7309 phy_data |= IGP02E1000_PM_D0_LPLU;
7310 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7311 if (ret_val)
7312 return ret_val;
7313 }
7314
7315
7316 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7317 if (ret_val)
7318 return ret_val;
7319
7320 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7321 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7322 if (ret_val)
7323 return ret_val;
7324
7325 }
7326 return E1000_SUCCESS;
7327}
7328
7329
7330
7331
7332
7333
7334static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7335{
7336 s32 ret_val;
7337 u16 default_page = 0;
7338 u16 phy_data;
7339
7340 DEBUGFUNC("e1000_set_vco_speed");
7341
7342 switch (hw->mac_type) {
7343 case e1000_82545_rev_3:
7344 case e1000_82546_rev_3:
7345 break;
7346 default:
7347 return E1000_SUCCESS;
7348 }
7349
7350
7351
7352 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7353 if (ret_val)
7354 return ret_val;
7355
7356 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7357 if (ret_val)
7358 return ret_val;
7359
7360 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7361 if (ret_val)
7362 return ret_val;
7363
7364 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7365 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7366 if (ret_val)
7367 return ret_val;
7368
7369
7370
7371 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7372 if (ret_val)
7373 return ret_val;
7374
7375 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7376 if (ret_val)
7377 return ret_val;
7378
7379 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7380 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7381 if (ret_val)
7382 return ret_val;
7383
7384 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7385 if (ret_val)
7386 return ret_val;
7387
7388 return E1000_SUCCESS;
7389}
7390
7391
7392
7393
7394
7395
7396
7397static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer)
7398{
7399 u8 i;
7400 u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7401 u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7402
7403 length = (length >> 2);
7404 offset = (offset >> 2);
7405
7406 for (i = 0; i < length; i++) {
7407 *((u32 *)buffer + i) =
7408 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7409 }
7410 return E1000_SUCCESS;
7411}
7412
7413
7414
7415
7416
7417
7418
7419
7420
7421
7422
7423static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7424{
7425 u32 hicr;
7426 u8 i;
7427
7428
7429 hicr = er32(HICR);
7430 if ((hicr & E1000_HICR_EN) == 0) {
7431 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7432 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7433 }
7434
7435 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7436 hicr = er32(HICR);
7437 if (!(hicr & E1000_HICR_C))
7438 break;
7439 mdelay(1);
7440 }
7441
7442 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7443 DEBUGOUT("Previous command timeout failed .\n");
7444 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7445 }
7446 return E1000_SUCCESS;
7447}
7448
7449
7450
7451
7452
7453
7454
7455
7456static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
7457 u16 offset, u8 *sum)
7458{
7459 u8 *tmp;
7460 u8 *bufptr = buffer;
7461 u32 data = 0;
7462 u16 remaining, i, j, prev_bytes;
7463
7464
7465
7466 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7467 return -E1000_ERR_PARAM;
7468 }
7469
7470 tmp = (u8 *)&data;
7471 prev_bytes = offset & 0x3;
7472 offset &= 0xFFFC;
7473 offset >>= 2;
7474
7475 if (prev_bytes) {
7476 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7477 for (j = prev_bytes; j < sizeof(u32); j++) {
7478 *(tmp + j) = *bufptr++;
7479 *sum += *(tmp + j);
7480 }
7481 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7482 length -= j - prev_bytes;
7483 offset++;
7484 }
7485
7486 remaining = length & 0x3;
7487 length -= remaining;
7488
7489
7490 length >>= 2;
7491
7492
7493
7494 for (i = 0; i < length; i++) {
7495 for (j = 0; j < sizeof(u32); j++) {
7496 *(tmp + j) = *bufptr++;
7497 *sum += *(tmp + j);
7498 }
7499
7500 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7501 }
7502 if (remaining) {
7503 for (j = 0; j < sizeof(u32); j++) {
7504 if (j < remaining)
7505 *(tmp + j) = *bufptr++;
7506 else
7507 *(tmp + j) = 0;
7508
7509 *sum += *(tmp + j);
7510 }
7511 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7512 }
7513
7514 return E1000_SUCCESS;
7515}
7516
7517
7518
7519
7520
7521
7522
7523static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
7524 struct e1000_host_mng_command_header *hdr)
7525{
7526 u16 i;
7527 u8 sum;
7528 u8 *buffer;
7529
7530
7531
7532
7533 u16 length = sizeof(struct e1000_host_mng_command_header);
7534
7535 sum = hdr->checksum;
7536 hdr->checksum = 0;
7537
7538 buffer = (u8 *)hdr;
7539 i = length;
7540 while (i--)
7541 sum += buffer[i];
7542
7543 hdr->checksum = 0 - sum;
7544
7545 length >>= 2;
7546
7547 for (i = 0; i < length; i++) {
7548 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i));
7549 E1000_WRITE_FLUSH();
7550 }
7551
7552 return E1000_SUCCESS;
7553}
7554
7555
7556
7557
7558
7559
7560
7561
7562static s32 e1000_mng_write_commit(struct e1000_hw *hw)
7563{
7564 u32 hicr;
7565
7566 hicr = er32(HICR);
7567
7568 ew32(HICR, hicr | E1000_HICR_C);
7569
7570 return E1000_SUCCESS;
7571}
7572
7573
7574
7575
7576
7577
7578
7579bool e1000_check_mng_mode(struct e1000_hw *hw)
7580{
7581 u32 fwsm;
7582
7583 fwsm = er32(FWSM);
7584
7585 if (hw->mac_type == e1000_ich8lan) {
7586 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7587 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7588 return true;
7589 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7590 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7591 return true;
7592
7593 return false;
7594}
7595
7596
7597
7598
7599
7600s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
7601{
7602 s32 ret_val;
7603 struct e1000_host_mng_command_header hdr;
7604
7605 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7606 hdr.command_length = length;
7607 hdr.reserved1 = 0;
7608 hdr.reserved2 = 0;
7609 hdr.checksum = 0;
7610
7611 ret_val = e1000_mng_enable_host_if(hw);
7612 if (ret_val == E1000_SUCCESS) {
7613 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7614 &(hdr.checksum));
7615 if (ret_val == E1000_SUCCESS) {
7616 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7617 if (ret_val == E1000_SUCCESS)
7618 ret_val = e1000_mng_write_commit(hw);
7619 }
7620 }
7621 return ret_val;
7622}
7623
7624
7625
7626
7627
7628
7629
7630static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
7631{
7632 u8 sum = 0;
7633 u32 i;
7634
7635 if (!buffer)
7636 return 0;
7637
7638 for (i=0; i < length; i++)
7639 sum += buffer[i];
7640
7641 return (u8)(0 - sum);
7642}
7643
7644
7645
7646
7647
7648
7649bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7650{
7651
7652
7653 s32 ret_val, checksum;
7654 bool tx_filter = false;
7655 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7656 u8 *buffer = (u8 *) &(hw->mng_cookie);
7657
7658 if (e1000_check_mng_mode(hw)) {
7659 ret_val = e1000_mng_enable_host_if(hw);
7660 if (ret_val == E1000_SUCCESS) {
7661 ret_val = e1000_host_if_read_cookie(hw, buffer);
7662 if (ret_val == E1000_SUCCESS) {
7663 checksum = hdr->checksum;
7664 hdr->checksum = 0;
7665 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7666 checksum == e1000_calculate_mng_checksum((char *)buffer,
7667 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7668 if (hdr->status &
7669 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7670 tx_filter = true;
7671 } else
7672 tx_filter = true;
7673 } else
7674 tx_filter = true;
7675 }
7676 }
7677
7678 hw->tx_pkt_filtering = tx_filter;
7679 return tx_filter;
7680}
7681
7682
7683
7684
7685
7686
7687
7688
7689
7690u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7691{
7692 u32 manc;
7693 u32 fwsm, factps;
7694
7695 if (hw->asf_firmware_present) {
7696 manc = er32(MANC);
7697
7698 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7699 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7700 return false;
7701 if (e1000_arc_subsystem_valid(hw)) {
7702 fwsm = er32(FWSM);
7703 factps = er32(FACTPS);
7704
7705 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7706 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7707 return true;
7708 } else
7709 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7710 return true;
7711 }
7712 return false;
7713}
7714
7715static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7716{
7717 s32 ret_val;
7718 u16 mii_status_reg;
7719 u16 i;
7720
7721
7722
7723
7724
7725 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7726 if (ret_val)
7727 return ret_val;
7728 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7729 if (ret_val)
7730 return ret_val;
7731
7732 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7733 if (ret_val)
7734 return ret_val;
7735
7736
7737 for (i = PHY_FORCE_TIME; i > 0; i--) {
7738
7739
7740
7741
7742 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7743 if (ret_val)
7744 return ret_val;
7745
7746 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7747 if (ret_val)
7748 return ret_val;
7749
7750 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7751 mdelay(100);
7752 }
7753
7754
7755 mdelay(1000);
7756
7757
7758
7759 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7760 if (ret_val)
7761 return ret_val;
7762 mdelay(50);
7763 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7764 if (ret_val)
7765 return ret_val;
7766 mdelay(50);
7767 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7768 if (ret_val)
7769 return ret_val;
7770 mdelay(50);
7771 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7772 if (ret_val)
7773 return ret_val;
7774
7775 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7776 if (ret_val)
7777 return ret_val;
7778
7779
7780 for (i = PHY_FORCE_TIME; i > 0; i--) {
7781
7782
7783
7784
7785 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7786 if (ret_val)
7787 return ret_val;
7788
7789 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7790 if (ret_val)
7791 return ret_val;
7792
7793 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7794 mdelay(100);
7795 }
7796 return E1000_SUCCESS;
7797}
7798
7799
7800
7801
7802
7803
7804
7805
7806
7807
7808static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7809{
7810 u32 ctrl;
7811
7812 DEBUGFUNC("e1000_set_pci_express_master_disable");
7813
7814 if (hw->bus_type != e1000_bus_type_pci_express)
7815 return;
7816
7817 ctrl = er32(CTRL);
7818 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7819 ew32(CTRL, ctrl);
7820}
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7834{
7835 s32 timeout = MASTER_DISABLE_TIMEOUT;
7836
7837 DEBUGFUNC("e1000_disable_pciex_master");
7838
7839 if (hw->bus_type != e1000_bus_type_pci_express)
7840 return E1000_SUCCESS;
7841
7842 e1000_set_pci_express_master_disable(hw);
7843
7844 while (timeout) {
7845 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7846 break;
7847 else
7848 udelay(100);
7849 timeout--;
7850 }
7851
7852 if (!timeout) {
7853 DEBUGOUT("Master requests are pending.\n");
7854 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7855 }
7856
7857 return E1000_SUCCESS;
7858}
7859
7860
7861
7862
7863
7864
7865
7866
7867
7868
7869
7870static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7871{
7872 s32 timeout = AUTO_READ_DONE_TIMEOUT;
7873
7874 DEBUGFUNC("e1000_get_auto_rd_done");
7875
7876 switch (hw->mac_type) {
7877 default:
7878 msleep(5);
7879 break;
7880 case e1000_82571:
7881 case e1000_82572:
7882 case e1000_82573:
7883 case e1000_80003es2lan:
7884 case e1000_ich8lan:
7885 while (timeout) {
7886 if (er32(EECD) & E1000_EECD_AUTO_RD)
7887 break;
7888 else msleep(1);
7889 timeout--;
7890 }
7891
7892 if (!timeout) {
7893 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7894 return -E1000_ERR_RESET;
7895 }
7896 break;
7897 }
7898
7899
7900
7901
7902 if (hw->mac_type == e1000_82573)
7903 msleep(25);
7904
7905 return E1000_SUCCESS;
7906}
7907
7908
7909
7910
7911
7912
7913
7914
7915
7916
7917static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7918{
7919 s32 timeout = PHY_CFG_TIMEOUT;
7920 u32 cfg_mask = E1000_EEPROM_CFG_DONE;
7921
7922 DEBUGFUNC("e1000_get_phy_cfg_done");
7923
7924 switch (hw->mac_type) {
7925 default:
7926 mdelay(10);
7927 break;
7928 case e1000_80003es2lan:
7929
7930 if (er32(STATUS) & E1000_STATUS_FUNC_1)
7931 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7932
7933 case e1000_82571:
7934 case e1000_82572:
7935 while (timeout) {
7936 if (er32(EEMNGCTL) & cfg_mask)
7937 break;
7938 else
7939 msleep(1);
7940 timeout--;
7941 }
7942 if (!timeout) {
7943 DEBUGOUT("MNG configuration cycle has not completed.\n");
7944 return -E1000_ERR_RESET;
7945 }
7946 break;
7947 }
7948
7949 return E1000_SUCCESS;
7950}
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961
7962
7963static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7964{
7965 s32 timeout;
7966 u32 swsm;
7967
7968 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
7969
7970 if (!hw->eeprom_semaphore_present)
7971 return E1000_SUCCESS;
7972
7973 if (hw->mac_type == e1000_80003es2lan) {
7974
7975 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7976 return -E1000_ERR_EEPROM;
7977 }
7978
7979
7980 timeout = hw->eeprom.word_size + 1;
7981 while (timeout) {
7982 swsm = er32(SWSM);
7983 swsm |= E1000_SWSM_SWESMBI;
7984 ew32(SWSM, swsm);
7985
7986 swsm = er32(SWSM);
7987 if (swsm & E1000_SWSM_SWESMBI)
7988 break;
7989
7990 udelay(50);
7991 timeout--;
7992 }
7993
7994 if (!timeout) {
7995
7996 e1000_put_hw_eeprom_semaphore(hw);
7997 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
7998 return -E1000_ERR_EEPROM;
7999 }
8000
8001 return E1000_SUCCESS;
8002}
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8013{
8014 u32 swsm;
8015
8016 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8017
8018 if (!hw->eeprom_semaphore_present)
8019 return;
8020
8021 swsm = er32(SWSM);
8022 if (hw->mac_type == e1000_80003es2lan) {
8023
8024 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8025 } else
8026 swsm &= ~(E1000_SWSM_SWESMBI);
8027 ew32(SWSM, swsm);
8028}
8029
8030
8031
8032
8033
8034
8035
8036
8037
8038
8039
8040static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
8041{
8042 s32 timeout = hw->eeprom.word_size + 1;
8043 u32 swsm;
8044
8045 DEBUGFUNC("e1000_get_software_semaphore");
8046
8047 if (hw->mac_type != e1000_80003es2lan) {
8048 return E1000_SUCCESS;
8049 }
8050
8051 while (timeout) {
8052 swsm = er32(SWSM);
8053
8054 if (!(swsm & E1000_SWSM_SMBI))
8055 break;
8056 mdelay(1);
8057 timeout--;
8058 }
8059
8060 if (!timeout) {
8061 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8062 return -E1000_ERR_RESET;
8063 }
8064
8065 return E1000_SUCCESS;
8066}
8067
8068
8069
8070
8071
8072
8073
8074
8075static void e1000_release_software_semaphore(struct e1000_hw *hw)
8076{
8077 u32 swsm;
8078
8079 DEBUGFUNC("e1000_release_software_semaphore");
8080
8081 if (hw->mac_type != e1000_80003es2lan) {
8082 return;
8083 }
8084
8085 swsm = er32(SWSM);
8086
8087 swsm &= ~E1000_SWSM_SMBI;
8088 ew32(SWSM, swsm);
8089}
8090
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101
8102s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
8103{
8104 u32 manc = 0;
8105 u32 fwsm = 0;
8106
8107 if (hw->mac_type == e1000_ich8lan) {
8108 fwsm = er32(FWSM);
8109 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8110 : E1000_BLK_PHY_RESET;
8111 }
8112
8113 if (hw->mac_type > e1000_82547_rev_2)
8114 manc = er32(MANC);
8115 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8116 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8117}
8118
8119static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8120{
8121 u32 fwsm;
8122
8123
8124
8125
8126
8127
8128 switch (hw->mac_type) {
8129 case e1000_82571:
8130 case e1000_82572:
8131 case e1000_82573:
8132 case e1000_80003es2lan:
8133 fwsm = er32(FWSM);
8134 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8135 return true;
8136 break;
8137 case e1000_ich8lan:
8138 return true;
8139 default:
8140 break;
8141 }
8142 return false;
8143}
8144
8145
8146
8147
8148
8149
8150
8151
8152
8153
8154
8155static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8156{
8157 u32 gcr_reg = 0;
8158
8159 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8160
8161 if (hw->bus_type == e1000_bus_type_unknown)
8162 e1000_get_bus_info(hw);
8163
8164 if (hw->bus_type != e1000_bus_type_pci_express)
8165 return E1000_SUCCESS;
8166
8167 if (no_snoop) {
8168 gcr_reg = er32(GCR);
8169 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8170 gcr_reg |= no_snoop;
8171 ew32(GCR, gcr_reg);
8172 }
8173 if (hw->mac_type == e1000_ich8lan) {
8174 u32 ctrl_ext;
8175
8176 ew32(GCR, PCI_EX_82566_SNOOP_ALL);
8177
8178 ctrl_ext = er32(CTRL_EXT);
8179 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8180 ew32(CTRL_EXT, ctrl_ext);
8181 }
8182
8183 return E1000_SUCCESS;
8184}
8185
8186
8187
8188
8189
8190
8191
8192
8193
8194
8195static s32 e1000_get_software_flag(struct e1000_hw *hw)
8196{
8197 s32 timeout = PHY_CFG_TIMEOUT;
8198 u32 extcnf_ctrl;
8199
8200 DEBUGFUNC("e1000_get_software_flag");
8201
8202 if (hw->mac_type == e1000_ich8lan) {
8203 while (timeout) {
8204 extcnf_ctrl = er32(EXTCNF_CTRL);
8205 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8206 ew32(EXTCNF_CTRL, extcnf_ctrl);
8207
8208 extcnf_ctrl = er32(EXTCNF_CTRL);
8209 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8210 break;
8211 mdelay(1);
8212 timeout--;
8213 }
8214
8215 if (!timeout) {
8216 DEBUGOUT("FW or HW locks the resource too long.\n");
8217 return -E1000_ERR_CONFIG;
8218 }
8219 }
8220
8221 return E1000_SUCCESS;
8222}
8223
8224
8225
8226
8227
8228
8229
8230
8231
8232
8233static void e1000_release_software_flag(struct e1000_hw *hw)
8234{
8235 u32 extcnf_ctrl;
8236
8237 DEBUGFUNC("e1000_release_software_flag");
8238
8239 if (hw->mac_type == e1000_ich8lan) {
8240 extcnf_ctrl= er32(EXTCNF_CTRL);
8241 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8242 ew32(EXTCNF_CTRL, extcnf_ctrl);
8243 }
8244
8245 return;
8246}
8247
8248
8249
8250
8251
8252
8253
8254
8255
8256
8257static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8258 u16 *data)
8259{
8260 s32 error = E1000_SUCCESS;
8261 u32 flash_bank = 0;
8262 u32 act_offset = 0;
8263 u32 bank_offset = 0;
8264 u16 word = 0;
8265 u16 i = 0;
8266
8267
8268
8269
8270
8271
8272
8273 flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8274
8275
8276 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8277
8278 error = e1000_get_software_flag(hw);
8279 if (error != E1000_SUCCESS)
8280 return error;
8281
8282 for (i = 0; i < words; i++) {
8283 if (hw->eeprom_shadow_ram != NULL &&
8284 hw->eeprom_shadow_ram[offset+i].modified) {
8285 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8286 } else {
8287
8288 act_offset = bank_offset + ((offset + i) * 2);
8289 error = e1000_read_ich8_word(hw, act_offset, &word);
8290 if (error != E1000_SUCCESS)
8291 break;
8292 data[i] = word;
8293 }
8294 }
8295
8296 e1000_release_software_flag(hw);
8297
8298 return error;
8299}
8300
8301
8302
8303
8304
8305
8306
8307
8308
8309
8310
8311
8312static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8313 u16 *data)
8314{
8315 u32 i = 0;
8316 s32 error = E1000_SUCCESS;
8317
8318 error = e1000_get_software_flag(hw);
8319 if (error != E1000_SUCCESS)
8320 return error;
8321
8322
8323
8324
8325
8326
8327
8328
8329 if (hw->eeprom_shadow_ram != NULL) {
8330 for (i = 0; i < words; i++) {
8331 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8332 hw->eeprom_shadow_ram[offset+i].modified = true;
8333 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8334 } else {
8335 error = -E1000_ERR_EEPROM;
8336 break;
8337 }
8338 }
8339 } else {
8340
8341
8342
8343
8344 error = -E1000_ERR_EEPROM;
8345 }
8346
8347 e1000_release_software_flag(hw);
8348
8349 return error;
8350}
8351
8352
8353
8354
8355
8356
8357
8358static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
8359{
8360 union ich8_hws_flash_status hsfsts;
8361 s32 error = E1000_ERR_EEPROM;
8362 s32 i = 0;
8363
8364 DEBUGFUNC("e1000_ich8_cycle_init");
8365
8366 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8367
8368
8369 if (hsfsts.hsf_status.fldesvalid == 0) {
8370 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8371 return error;
8372 }
8373
8374
8375
8376 hsfsts.hsf_status.flcerr = 1;
8377 hsfsts.hsf_status.dael = 1;
8378
8379 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8380
8381
8382
8383
8384
8385
8386
8387
8388
8389
8390 if (hsfsts.hsf_status.flcinprog == 0) {
8391
8392
8393 hsfsts.hsf_status.flcdone = 1;
8394 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8395 error = E1000_SUCCESS;
8396 } else {
8397
8398
8399 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8400 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8401 if (hsfsts.hsf_status.flcinprog == 0) {
8402 error = E1000_SUCCESS;
8403 break;
8404 }
8405 udelay(1);
8406 }
8407 if (error == E1000_SUCCESS) {
8408
8409
8410 hsfsts.hsf_status.flcdone = 1;
8411 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8412 } else {
8413 DEBUGOUT("Flash controller busy, cannot get access");
8414 }
8415 }
8416 return error;
8417}
8418
8419
8420
8421
8422
8423
8424static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
8425{
8426 union ich8_hws_flash_ctrl hsflctl;
8427 union ich8_hws_flash_status hsfsts;
8428 s32 error = E1000_ERR_EEPROM;
8429 u32 i = 0;
8430
8431
8432 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8433 hsflctl.hsf_ctrl.flcgo = 1;
8434 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8435
8436
8437 do {
8438 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8439 if (hsfsts.hsf_status.flcdone == 1)
8440 break;
8441 udelay(1);
8442 i++;
8443 } while (i < timeout);
8444 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8445 error = E1000_SUCCESS;
8446 }
8447 return error;
8448}
8449
8450
8451
8452
8453
8454
8455
8456
8457
8458static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8459 u16 *data)
8460{
8461 union ich8_hws_flash_status hsfsts;
8462 union ich8_hws_flash_ctrl hsflctl;
8463 u32 flash_linear_address;
8464 u32 flash_data = 0;
8465 s32 error = -E1000_ERR_EEPROM;
8466 s32 count = 0;
8467
8468 DEBUGFUNC("e1000_read_ich8_data");
8469
8470 if (size < 1 || size > 2 || data == NULL ||
8471 index > ICH_FLASH_LINEAR_ADDR_MASK)
8472 return error;
8473
8474 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8475 hw->flash_base_addr;
8476
8477 do {
8478 udelay(1);
8479
8480 error = e1000_ich8_cycle_init(hw);
8481 if (error != E1000_SUCCESS)
8482 break;
8483
8484 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8485
8486 hsflctl.hsf_ctrl.fldbcount = size - 1;
8487 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8488 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8489
8490
8491
8492
8493
8494 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8495
8496 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8497
8498
8499
8500
8501 if (error == E1000_SUCCESS) {
8502 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8503 if (size == 1) {
8504 *data = (u8)(flash_data & 0x000000FF);
8505 } else if (size == 2) {
8506 *data = (u16)(flash_data & 0x0000FFFF);
8507 }
8508 break;
8509 } else {
8510
8511
8512
8513
8514 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8515 if (hsfsts.hsf_status.flcerr == 1) {
8516
8517 continue;
8518 } else if (hsfsts.hsf_status.flcdone == 0) {
8519 DEBUGOUT("Timeout error - flash cycle did not complete.");
8520 break;
8521 }
8522 }
8523 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8524
8525 return error;
8526}
8527
8528
8529
8530
8531
8532
8533
8534
8535
8536static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
8537 u16 data)
8538{
8539 union ich8_hws_flash_status hsfsts;
8540 union ich8_hws_flash_ctrl hsflctl;
8541 u32 flash_linear_address;
8542 u32 flash_data = 0;
8543 s32 error = -E1000_ERR_EEPROM;
8544 s32 count = 0;
8545
8546 DEBUGFUNC("e1000_write_ich8_data");
8547
8548 if (size < 1 || size > 2 || data > size * 0xff ||
8549 index > ICH_FLASH_LINEAR_ADDR_MASK)
8550 return error;
8551
8552 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8553 hw->flash_base_addr;
8554
8555 do {
8556 udelay(1);
8557
8558 error = e1000_ich8_cycle_init(hw);
8559 if (error != E1000_SUCCESS)
8560 break;
8561
8562 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8563
8564 hsflctl.hsf_ctrl.fldbcount = size -1;
8565 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8566 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8567
8568
8569
8570 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8571
8572 if (size == 1)
8573 flash_data = (u32)data & 0x00FF;
8574 else
8575 flash_data = (u32)data;
8576
8577 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8578
8579
8580
8581 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8582 if (error == E1000_SUCCESS) {
8583 break;
8584 } else {
8585
8586
8587
8588
8589 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8590 if (hsfsts.hsf_status.flcerr == 1) {
8591
8592 continue;
8593 } else if (hsfsts.hsf_status.flcdone == 0) {
8594 DEBUGOUT("Timeout error - flash cycle did not complete.");
8595 break;
8596 }
8597 }
8598 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8599
8600 return error;
8601}
8602
8603
8604
8605
8606
8607
8608
8609
8610static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data)
8611{
8612 s32 status = E1000_SUCCESS;
8613 u16 word = 0;
8614
8615 status = e1000_read_ich8_data(hw, index, 1, &word);
8616 if (status == E1000_SUCCESS) {
8617 *data = (u8)word;
8618 }
8619
8620 return status;
8621}
8622
8623
8624
8625
8626
8627
8628
8629
8630
8631
8632static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
8633{
8634 s32 error = E1000_SUCCESS;
8635 s32 program_retries = 0;
8636
8637 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8638
8639 error = e1000_write_ich8_byte(hw, index, byte);
8640
8641 if (error != E1000_SUCCESS) {
8642 for (program_retries = 0; program_retries < 100; program_retries++) {
8643 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8644 error = e1000_write_ich8_byte(hw, index, byte);
8645 udelay(100);
8646 if (error == E1000_SUCCESS)
8647 break;
8648 }
8649 }
8650
8651 if (program_retries == 100)
8652 error = E1000_ERR_EEPROM;
8653
8654 return error;
8655}
8656
8657
8658
8659
8660
8661
8662
8663
8664static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
8665{
8666 s32 status = E1000_SUCCESS;
8667 u16 word = (u16)data;
8668
8669 status = e1000_write_ich8_data(hw, index, 1, word);
8670
8671 return status;
8672}
8673
8674
8675
8676
8677
8678
8679
8680
8681static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
8682{
8683 s32 status = E1000_SUCCESS;
8684 status = e1000_read_ich8_data(hw, index, 2, data);
8685 return status;
8686}
8687
8688
8689
8690
8691
8692
8693
8694
8695
8696
8697
8698
8699static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
8700{
8701 union ich8_hws_flash_status hsfsts;
8702 union ich8_hws_flash_ctrl hsflctl;
8703 u32 flash_linear_address;
8704 s32 count = 0;
8705 s32 error = E1000_ERR_EEPROM;
8706 s32 iteration;
8707 s32 sub_sector_size = 0;
8708 s32 bank_size;
8709 s32 j = 0;
8710 s32 error_flag = 0;
8711
8712 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8713
8714
8715
8716
8717
8718
8719
8720
8721
8722
8723 if (hsfsts.hsf_status.berasesz == 0x0) {
8724
8725 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8726 bank_size = ICH_FLASH_SECTOR_SIZE;
8727 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8728 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8729 bank_size = ICH_FLASH_SEG_SIZE_4K;
8730 iteration = 1;
8731 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8732 bank_size = ICH_FLASH_SEG_SIZE_64K;
8733 iteration = 1;
8734 } else {
8735 return error;
8736 }
8737
8738 for (j = 0; j < iteration ; j++) {
8739 do {
8740 count++;
8741
8742 error = e1000_ich8_cycle_init(hw);
8743 if (error != E1000_SUCCESS) {
8744 error_flag = 1;
8745 break;
8746 }
8747
8748
8749
8750 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8751 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8752 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8753
8754
8755
8756
8757
8758 flash_linear_address = bank * bank_size + j * sub_sector_size;
8759 flash_linear_address += hw->flash_base_addr;
8760 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8761
8762 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8763
8764 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8765
8766
8767 if (error == E1000_SUCCESS) {
8768 break;
8769 } else {
8770 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8771 if (hsfsts.hsf_status.flcerr == 1) {
8772
8773 continue;
8774 } else if (hsfsts.hsf_status.flcdone == 0) {
8775 error_flag = 1;
8776 break;
8777 }
8778 }
8779 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8780 if (error_flag == 1)
8781 break;
8782 }
8783 if (error_flag != 1)
8784 error = E1000_SUCCESS;
8785 return error;
8786}
8787
8788static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8789 u32 cnf_base_addr,
8790 u32 cnf_size)
8791{
8792 u32 ret_val = E1000_SUCCESS;
8793 u16 word_addr, reg_data, reg_addr;
8794 u16 i;
8795
8796
8797 word_addr = (u16)(cnf_base_addr << 1);
8798
8799
8800 for (i = 0; i < cnf_size; i++) {
8801 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
8802 if (ret_val)
8803 return ret_val;
8804
8805 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
8806 if (ret_val)
8807 return ret_val;
8808
8809 ret_val = e1000_get_software_flag(hw);
8810 if (ret_val != E1000_SUCCESS)
8811 return ret_val;
8812
8813 ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
8814
8815 e1000_release_software_flag(hw);
8816 }
8817
8818 return ret_val;
8819}
8820
8821
8822
8823
8824
8825
8826
8827
8828
8829
8830static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8831{
8832 u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8833
8834 if (hw->phy_type != e1000_phy_igp_3)
8835 return E1000_SUCCESS;
8836
8837
8838 reg_data = er32(FEXTNVM);
8839 if (!(reg_data & FEXTNVM_SW_CONFIG))
8840 return E1000_SUCCESS;
8841
8842
8843 loop = 0;
8844 do {
8845 reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
8846 udelay(100);
8847 loop++;
8848 } while ((!reg_data) && (loop < 50));
8849
8850
8851 reg_data = er32(STATUS);
8852 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8853 ew32(STATUS, reg_data);
8854
8855
8856
8857 reg_data = er32(EXTCNF_CTRL);
8858 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8859 reg_data = er32(EXTCNF_SIZE);
8860 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8861 cnf_size >>= 16;
8862 if (cnf_size) {
8863 reg_data = er32(EXTCNF_CTRL);
8864 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8865
8866 cnf_base_addr >>= 16;
8867
8868
8869 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
8870 cnf_size);
8871 if (ret_val)
8872 return ret_val;
8873 }
8874 }
8875
8876 return E1000_SUCCESS;
8877}
8878