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8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
25#include <linux/in.h>
26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
34#include <linux/delay.h>
35#include <linux/mm.h>
36
37#include "qla3xxx.h"
38
39#define DRV_NAME "qla3xxx"
40#define DRV_STRING "QLogic ISP3XXX Network Driver"
41#define DRV_VERSION "v2.03.00-k5"
42#define PFX DRV_NAME " "
43
44static const char ql3xxx_driver_name[] = DRV_NAME;
45static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47MODULE_AUTHOR("QLogic Corporation");
48MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
49MODULE_LICENSE("GPL");
50MODULE_VERSION(DRV_VERSION);
51
52static const u32 default_msg
53 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
54 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
55
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60static int msi;
61module_param(msi, int, 0);
62MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
63
64static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
65 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
67
68 {0,}
69};
70
71MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
72
73
74
75
76typedef enum {
77 PHY_TYPE_UNKNOWN = 0,
78 PHY_VITESSE_VSC8211,
79 PHY_AGERE_ET1011C,
80 MAX_PHY_DEV_TYPES
81} PHY_DEVICE_et;
82
83typedef struct {
84 PHY_DEVICE_et phyDevice;
85 u32 phyIdOUI;
86 u16 phyIdModel;
87 char *name;
88} PHY_DEVICE_INFO_t;
89
90static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
91 {{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
92 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
93 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
94};
95
96
97
98
99
100static int ql_sem_spinlock(struct ql3_adapter *qdev,
101 u32 sem_mask, u32 sem_bits)
102{
103 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
104 u32 value;
105 unsigned int seconds = 3;
106
107 do {
108 writel((sem_mask | sem_bits),
109 &port_regs->CommonRegs.semaphoreReg);
110 value = readl(&port_regs->CommonRegs.semaphoreReg);
111 if ((value & (sem_mask >> 16)) == sem_bits)
112 return 0;
113 ssleep(1);
114 } while(--seconds);
115 return -1;
116}
117
118static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
119{
120 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
121 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
122 readl(&port_regs->CommonRegs.semaphoreReg);
123}
124
125static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
126{
127 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
128 u32 value;
129
130 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
131 value = readl(&port_regs->CommonRegs.semaphoreReg);
132 return ((value & (sem_mask >> 16)) == sem_bits);
133}
134
135
136
137
138static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
139{
140 int i = 0;
141
142 while (1) {
143 if (!ql_sem_lock(qdev,
144 QL_DRVR_SEM_MASK,
145 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
146 * 2) << 1)) {
147 if (i < 10) {
148 ssleep(1);
149 i++;
150 } else {
151 printk(KERN_ERR PFX "%s: Timed out waiting for "
152 "driver lock...\n",
153 qdev->ndev->name);
154 return 0;
155 }
156 } else {
157 printk(KERN_DEBUG PFX
158 "%s: driver lock acquired.\n",
159 qdev->ndev->name);
160 return 1;
161 }
162 }
163}
164
165static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
166{
167 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
168
169 writel(((ISP_CONTROL_NP_MASK << 16) | page),
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
172 qdev->current_page = page;
173}
174
175static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
176 u32 __iomem * reg)
177{
178 u32 value;
179 unsigned long hw_flags;
180
181 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
182 value = readl(reg);
183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
184
185 return value;
186}
187
188static u32 ql_read_common_reg(struct ql3_adapter *qdev,
189 u32 __iomem * reg)
190{
191 return readl(reg);
192}
193
194static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
195{
196 u32 value;
197 unsigned long hw_flags;
198
199 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
200
201 if (qdev->current_page != 0)
202 ql_set_register_page(qdev,0);
203 value = readl(reg);
204
205 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
206 return value;
207}
208
209static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
210{
211 if (qdev->current_page != 0)
212 ql_set_register_page(qdev,0);
213 return readl(reg);
214}
215
216static void ql_write_common_reg_l(struct ql3_adapter *qdev,
217 u32 __iomem *reg, u32 value)
218{
219 unsigned long hw_flags;
220
221 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
222 writel(value, reg);
223 readl(reg);
224 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
225 return;
226}
227
228static void ql_write_common_reg(struct ql3_adapter *qdev,
229 u32 __iomem *reg, u32 value)
230{
231 writel(value, reg);
232 readl(reg);
233 return;
234}
235
236static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
238{
239 writel(value, reg);
240 readl(reg);
241 udelay(1);
242 return;
243}
244
245static void ql_write_page0_reg(struct ql3_adapter *qdev,
246 u32 __iomem *reg, u32 value)
247{
248 if (qdev->current_page != 0)
249 ql_set_register_page(qdev,0);
250 writel(value, reg);
251 readl(reg);
252 return;
253}
254
255
256
257
258static void ql_write_page1_reg(struct ql3_adapter *qdev,
259 u32 __iomem *reg, u32 value)
260{
261 if (qdev->current_page != 1)
262 ql_set_register_page(qdev,1);
263 writel(value, reg);
264 readl(reg);
265 return;
266}
267
268
269
270
271static void ql_write_page2_reg(struct ql3_adapter *qdev,
272 u32 __iomem *reg, u32 value)
273{
274 if (qdev->current_page != 2)
275 ql_set_register_page(qdev,2);
276 writel(value, reg);
277 readl(reg);
278 return;
279}
280
281static void ql_disable_interrupts(struct ql3_adapter *qdev)
282{
283 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
284
285 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
286 (ISP_IMR_ENABLE_INT << 16));
287
288}
289
290static void ql_enable_interrupts(struct ql3_adapter *qdev)
291{
292 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
293
294 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
295 ((0xff << 16) | ISP_IMR_ENABLE_INT));
296
297}
298
299static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
300 struct ql_rcv_buf_cb *lrg_buf_cb)
301{
302 dma_addr_t map;
303 int err;
304 lrg_buf_cb->next = NULL;
305
306 if (qdev->lrg_buf_free_tail == NULL) {
307 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
308 } else {
309 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
310 qdev->lrg_buf_free_tail = lrg_buf_cb;
311 }
312
313 if (!lrg_buf_cb->skb) {
314 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
315 qdev->lrg_buffer_len);
316 if (unlikely(!lrg_buf_cb->skb)) {
317 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
318 qdev->ndev->name);
319 qdev->lrg_buf_skb_check++;
320 } else {
321
322
323
324
325 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
326 map = pci_map_single(qdev->pdev,
327 lrg_buf_cb->skb->data,
328 qdev->lrg_buffer_len -
329 QL_HEADER_SPACE,
330 PCI_DMA_FROMDEVICE);
331 err = pci_dma_mapping_error(qdev->pdev, map);
332 if(err) {
333 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
334 qdev->ndev->name, err);
335 dev_kfree_skb(lrg_buf_cb->skb);
336 lrg_buf_cb->skb = NULL;
337
338 qdev->lrg_buf_skb_check++;
339 return;
340 }
341
342 lrg_buf_cb->buf_phy_addr_low =
343 cpu_to_le32(LS_64BITS(map));
344 lrg_buf_cb->buf_phy_addr_high =
345 cpu_to_le32(MS_64BITS(map));
346 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
347 pci_unmap_len_set(lrg_buf_cb, maplen,
348 qdev->lrg_buffer_len -
349 QL_HEADER_SPACE);
350 }
351 }
352
353 qdev->lrg_buf_free_count++;
354}
355
356static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
357 *qdev)
358{
359 struct ql_rcv_buf_cb *lrg_buf_cb;
360
361 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
362 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
363 qdev->lrg_buf_free_tail = NULL;
364 qdev->lrg_buf_free_count--;
365 }
366
367 return lrg_buf_cb;
368}
369
370static u32 addrBits = EEPROM_NO_ADDR_BITS;
371static u32 dataBits = EEPROM_NO_DATA_BITS;
372
373static void fm93c56a_deselect(struct ql3_adapter *qdev);
374static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
375 unsigned short *value);
376
377
378
379
380static void fm93c56a_select(struct ql3_adapter *qdev)
381{
382 struct ql3xxx_port_registers __iomem *port_regs =
383 qdev->mem_map_registers;
384
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
386 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
387 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
388 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
389 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
390}
391
392
393
394
395static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
396{
397 int i;
398 u32 mask;
399 u32 dataBit;
400 u32 previousBit;
401 struct ql3xxx_port_registers __iomem *port_regs =
402 qdev->mem_map_registers;
403
404
405 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
406 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1);
408 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
409 ISP_NVRAM_MASK | qdev->
410 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
411 AUBURN_EEPROM_CLK_RISE);
412 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
413 ISP_NVRAM_MASK | qdev->
414 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
415 AUBURN_EEPROM_CLK_FALL);
416
417 mask = 1 << (FM93C56A_CMD_BITS - 1);
418
419 previousBit = 0xffff;
420 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
421 dataBit =
422 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
423 if (previousBit != dataBit) {
424
425
426
427
428 ql_write_nvram_reg(qdev,
429 &port_regs->CommonRegs.
430 serialPortInterfaceReg,
431 ISP_NVRAM_MASK | qdev->
432 eeprom_cmd_data | dataBit);
433 previousBit = dataBit;
434 }
435 ql_write_nvram_reg(qdev,
436 &port_regs->CommonRegs.
437 serialPortInterfaceReg,
438 ISP_NVRAM_MASK | qdev->
439 eeprom_cmd_data | dataBit |
440 AUBURN_EEPROM_CLK_RISE);
441 ql_write_nvram_reg(qdev,
442 &port_regs->CommonRegs.
443 serialPortInterfaceReg,
444 ISP_NVRAM_MASK | qdev->
445 eeprom_cmd_data | dataBit |
446 AUBURN_EEPROM_CLK_FALL);
447 cmd = cmd << 1;
448 }
449
450 mask = 1 << (addrBits - 1);
451
452 previousBit = 0xffff;
453 for (i = 0; i < addrBits; i++) {
454 dataBit =
455 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
456 AUBURN_EEPROM_DO_0;
457 if (previousBit != dataBit) {
458
459
460
461
462 ql_write_nvram_reg(qdev,
463 &port_regs->CommonRegs.
464 serialPortInterfaceReg,
465 ISP_NVRAM_MASK | qdev->
466 eeprom_cmd_data | dataBit);
467 previousBit = dataBit;
468 }
469 ql_write_nvram_reg(qdev,
470 &port_regs->CommonRegs.
471 serialPortInterfaceReg,
472 ISP_NVRAM_MASK | qdev->
473 eeprom_cmd_data | dataBit |
474 AUBURN_EEPROM_CLK_RISE);
475 ql_write_nvram_reg(qdev,
476 &port_regs->CommonRegs.
477 serialPortInterfaceReg,
478 ISP_NVRAM_MASK | qdev->
479 eeprom_cmd_data | dataBit |
480 AUBURN_EEPROM_CLK_FALL);
481 eepromAddr = eepromAddr << 1;
482 }
483}
484
485
486
487
488static void fm93c56a_deselect(struct ql3_adapter *qdev)
489{
490 struct ql3xxx_port_registers __iomem *port_regs =
491 qdev->mem_map_registers;
492 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
493 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
494 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
495}
496
497
498
499
500static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
501{
502 int i;
503 u32 data = 0;
504 u32 dataBit;
505 struct ql3xxx_port_registers __iomem *port_regs =
506 qdev->mem_map_registers;
507
508
509
510 for (i = 0; i < dataBits; i++) {
511 ql_write_nvram_reg(qdev,
512 &port_regs->CommonRegs.
513 serialPortInterfaceReg,
514 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
515 AUBURN_EEPROM_CLK_RISE);
516 ql_write_nvram_reg(qdev,
517 &port_regs->CommonRegs.
518 serialPortInterfaceReg,
519 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
520 AUBURN_EEPROM_CLK_FALL);
521 dataBit =
522 (ql_read_common_reg
523 (qdev,
524 &port_regs->CommonRegs.
525 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
526 data = (data << 1) | dataBit;
527 }
528 *value = (u16) data;
529}
530
531
532
533
534static void eeprom_readword(struct ql3_adapter *qdev,
535 u32 eepromAddr, unsigned short *value)
536{
537 fm93c56a_select(qdev);
538 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
539 fm93c56a_datain(qdev, value);
540 fm93c56a_deselect(qdev);
541}
542
543static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
544{
545 __le16 *p = (__le16 *)ndev->dev_addr;
546 p[0] = cpu_to_le16(addr[0]);
547 p[1] = cpu_to_le16(addr[1]);
548 p[2] = cpu_to_le16(addr[2]);
549}
550
551static int ql_get_nvram_params(struct ql3_adapter *qdev)
552{
553 u16 *pEEPROMData;
554 u16 checksum = 0;
555 u32 index;
556 unsigned long hw_flags;
557
558 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
559
560 pEEPROMData = (u16 *) & qdev->nvram_data;
561 qdev->eeprom_cmd_data = 0;
562 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
563 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
564 2) << 10)) {
565 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
566 __func__);
567 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
568 return -1;
569 }
570
571 for (index = 0; index < EEPROM_SIZE; index++) {
572 eeprom_readword(qdev, index, pEEPROMData);
573 checksum += *pEEPROMData;
574 pEEPROMData++;
575 }
576 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
577
578 if (checksum != 0) {
579 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
580 qdev->ndev->name, checksum);
581 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
582 return -1;
583 }
584
585 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
586 return checksum;
587}
588
589static const u32 PHYAddr[2] = {
590 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
591};
592
593static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
594{
595 struct ql3xxx_port_registers __iomem *port_regs =
596 qdev->mem_map_registers;
597 u32 temp;
598 int count = 1000;
599
600 while (count) {
601 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
602 if (!(temp & MAC_MII_STATUS_BSY))
603 return 0;
604 udelay(10);
605 count--;
606 }
607 return -1;
608}
609
610static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
611{
612 struct ql3xxx_port_registers __iomem *port_regs =
613 qdev->mem_map_registers;
614 u32 scanControl;
615
616 if (qdev->numPorts > 1) {
617
618 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
619 } else {
620 scanControl = MAC_MII_CONTROL_SC;
621 }
622
623
624
625
626
627
628
629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
630 PHYAddr[0] | MII_SCAN_REGISTER);
631
632 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
633 (scanControl) |
634 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
635}
636
637static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
638{
639 u8 ret;
640 struct ql3xxx_port_registers __iomem *port_regs =
641 qdev->mem_map_registers;
642
643
644 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
645 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
646
647 ret = 1;
648 } else {
649
650 ret = 0;
651 }
652
653
654
655
656
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
658 PHYAddr[0] | MII_SCAN_REGISTER);
659
660 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
661 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
662 MAC_MII_CONTROL_RC) << 16));
663
664 return ret;
665}
666
667static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
668 u16 regAddr, u16 value, u32 phyAddr)
669{
670 struct ql3xxx_port_registers __iomem *port_regs =
671 qdev->mem_map_registers;
672 u8 scanWasEnabled;
673
674 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
675
676 if (ql_wait_for_mii_ready(qdev)) {
677 if (netif_msg_link(qdev))
678 printk(KERN_WARNING PFX
679 "%s Timed out waiting for management port to "
680 "get free before issuing command.\n",
681 qdev->ndev->name);
682 return -1;
683 }
684
685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
686 phyAddr | regAddr);
687
688 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
689
690
691 if (ql_wait_for_mii_ready(qdev)) {
692 if (netif_msg_link(qdev))
693 printk(KERN_WARNING PFX
694 "%s: Timed out waiting for management port to "
695 "get free before issuing command.\n",
696 qdev->ndev->name);
697 return -1;
698 }
699
700 if (scanWasEnabled)
701 ql_mii_enable_scan_mode(qdev);
702
703 return 0;
704}
705
706static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
707 u16 * value, u32 phyAddr)
708{
709 struct ql3xxx_port_registers __iomem *port_regs =
710 qdev->mem_map_registers;
711 u8 scanWasEnabled;
712 u32 temp;
713
714 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
715
716 if (ql_wait_for_mii_ready(qdev)) {
717 if (netif_msg_link(qdev))
718 printk(KERN_WARNING PFX
719 "%s: Timed out waiting for management port to "
720 "get free before issuing command.\n",
721 qdev->ndev->name);
722 return -1;
723 }
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
726 phyAddr | regAddr);
727
728 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
729 (MAC_MII_CONTROL_RC << 16));
730
731 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
732 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
733
734
735 if (ql_wait_for_mii_ready(qdev)) {
736 if (netif_msg_link(qdev))
737 printk(KERN_WARNING PFX
738 "%s: Timed out waiting for management port to "
739 "get free after issuing command.\n",
740 qdev->ndev->name);
741 return -1;
742 }
743
744 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
745 *value = (u16) temp;
746
747 if (scanWasEnabled)
748 ql_mii_enable_scan_mode(qdev);
749
750 return 0;
751}
752
753static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
754{
755 struct ql3xxx_port_registers __iomem *port_regs =
756 qdev->mem_map_registers;
757
758 ql_mii_disable_scan_mode(qdev);
759
760 if (ql_wait_for_mii_ready(qdev)) {
761 if (netif_msg_link(qdev))
762 printk(KERN_WARNING PFX
763 "%s: Timed out waiting for management port to "
764 "get free before issuing command.\n",
765 qdev->ndev->name);
766 return -1;
767 }
768
769 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
770 qdev->PHYAddr | regAddr);
771
772 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
773
774
775 if (ql_wait_for_mii_ready(qdev)) {
776 if (netif_msg_link(qdev))
777 printk(KERN_WARNING PFX
778 "%s: Timed out waiting for management port to "
779 "get free before issuing command.\n",
780 qdev->ndev->name);
781 return -1;
782 }
783
784 ql_mii_enable_scan_mode(qdev);
785
786 return 0;
787}
788
789static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
790{
791 u32 temp;
792 struct ql3xxx_port_registers __iomem *port_regs =
793 qdev->mem_map_registers;
794
795 ql_mii_disable_scan_mode(qdev);
796
797 if (ql_wait_for_mii_ready(qdev)) {
798 if (netif_msg_link(qdev))
799 printk(KERN_WARNING PFX
800 "%s: Timed out waiting for management port to "
801 "get free before issuing command.\n",
802 qdev->ndev->name);
803 return -1;
804 }
805
806 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
807 qdev->PHYAddr | regAddr);
808
809 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
810 (MAC_MII_CONTROL_RC << 16));
811
812 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
813 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
814
815
816 if (ql_wait_for_mii_ready(qdev)) {
817 if (netif_msg_link(qdev))
818 printk(KERN_WARNING PFX
819 "%s: Timed out waiting for management port to "
820 "get free before issuing command.\n",
821 qdev->ndev->name);
822 return -1;
823 }
824
825 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
826 *value = (u16) temp;
827
828 ql_mii_enable_scan_mode(qdev);
829
830 return 0;
831}
832
833static void ql_petbi_reset(struct ql3_adapter *qdev)
834{
835 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
836}
837
838static void ql_petbi_start_neg(struct ql3_adapter *qdev)
839{
840 u16 reg;
841
842
843 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
844 reg |= PETBI_TBI_AUTO_SENSE;
845 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
846
847 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
848 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
849
850 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
851 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
852 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
853
854}
855
856static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
857{
858 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
859 PHYAddr[qdev->mac_index]);
860}
861
862static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
863{
864 u16 reg;
865
866
867 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
868 PHYAddr[qdev->mac_index]);
869 reg |= PETBI_TBI_AUTO_SENSE;
870 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
871 PHYAddr[qdev->mac_index]);
872
873 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
874 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
875 PHYAddr[qdev->mac_index]);
876
877 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
878 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
879 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
880 PHYAddr[qdev->mac_index]);
881}
882
883static void ql_petbi_init(struct ql3_adapter *qdev)
884{
885 ql_petbi_reset(qdev);
886 ql_petbi_start_neg(qdev);
887}
888
889static void ql_petbi_init_ex(struct ql3_adapter *qdev)
890{
891 ql_petbi_reset_ex(qdev);
892 ql_petbi_start_neg_ex(qdev);
893}
894
895static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
896{
897 u16 reg;
898
899 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
900 return 0;
901
902 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
903}
904
905static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
906{
907 printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
908
909 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
910
911 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
912
913 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
914
915 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
916
917 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
918
919 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
920
921 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
922
923 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
924
925 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
926
927 ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
928
929
930
931
932
933 ql_mii_write_reg(qdev, 0x12, 0x840a);
934 ql_mii_write_reg(qdev, 0x00, 0x1140);
935 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
936}
937
938static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
939 u16 phyIdReg0, u16 phyIdReg1)
940{
941 PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
942 u32 oui;
943 u16 model;
944 int i;
945
946 if (phyIdReg0 == 0xffff) {
947 return result;
948 }
949
950 if (phyIdReg1 == 0xffff) {
951 return result;
952 }
953
954
955 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
956
957 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
958
959
960 for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
961 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
962 {
963 result = PHY_DEVICES[i].phyDevice;
964
965 printk(KERN_INFO "%s: Phy: %s\n",
966 qdev->ndev->name, PHY_DEVICES[i].name);
967
968 break;
969 }
970 }
971
972 return result;
973}
974
975static int ql_phy_get_speed(struct ql3_adapter *qdev)
976{
977 u16 reg;
978
979 switch(qdev->phyType) {
980 case PHY_AGERE_ET1011C:
981 {
982 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
983 return 0;
984
985 reg = (reg >> 8) & 3;
986 break;
987 }
988 default:
989 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
990 return 0;
991
992 reg = (((reg & 0x18) >> 3) & 3);
993 }
994
995 switch(reg) {
996 case 2:
997 return SPEED_1000;
998 case 1:
999 return SPEED_100;
1000 case 0:
1001 return SPEED_10;
1002 default:
1003 return -1;
1004 }
1005}
1006
1007static int ql_is_full_dup(struct ql3_adapter *qdev)
1008{
1009 u16 reg;
1010
1011 switch(qdev->phyType) {
1012 case PHY_AGERE_ET1011C:
1013 {
1014 if (ql_mii_read_reg(qdev, 0x1A, ®))
1015 return 0;
1016
1017 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1018 }
1019 case PHY_VITESSE_VSC8211:
1020 default:
1021 {
1022 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
1023 return 0;
1024 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1025 }
1026 }
1027}
1028
1029static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1030{
1031 u16 reg;
1032
1033 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
1034 return 0;
1035
1036 return (reg & PHY_NEG_PAUSE) != 0;
1037}
1038
1039static int PHY_Setup(struct ql3_adapter *qdev)
1040{
1041 u16 reg1;
1042 u16 reg2;
1043 bool agereAddrChangeNeeded = false;
1044 u32 miiAddr = 0;
1045 int err;
1046
1047
1048 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
1049 if(err != 0) {
1050 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1051 qdev->ndev->name);
1052 return err;
1053 }
1054
1055 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
1056 if(err != 0) {
1057 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1058 qdev->ndev->name);
1059 return err;
1060 }
1061
1062
1063 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1064
1065
1066
1067 if (qdev->mac_index == 0) {
1068 miiAddr = MII_AGERE_ADDR_1;
1069 } else {
1070 miiAddr = MII_AGERE_ADDR_2;
1071 }
1072
1073 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1074 if(err != 0) {
1075 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1076 qdev->ndev->name);
1077 return err;
1078 }
1079
1080 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1081 if(err != 0) {
1082 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1083 qdev->ndev->name);
1084 return err;
1085 }
1086
1087
1088 agereAddrChangeNeeded = true;
1089 }
1090
1091
1092
1093 qdev->phyType = getPhyType(qdev, reg1, reg2);
1094
1095 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1096
1097 phyAgereSpecificInit(qdev, miiAddr);
1098 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1099 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1100 return -EIO;
1101 }
1102
1103 return 0;
1104}
1105
1106
1107
1108
1109static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1110{
1111 struct ql3xxx_port_registers __iomem *port_regs =
1112 qdev->mem_map_registers;
1113 u32 value;
1114
1115 if (enable)
1116 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1117 else
1118 value = (MAC_CONFIG_REG_PE << 16);
1119
1120 if (qdev->mac_index)
1121 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1122 else
1123 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1124}
1125
1126
1127
1128
1129static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1130{
1131 struct ql3xxx_port_registers __iomem *port_regs =
1132 qdev->mem_map_registers;
1133 u32 value;
1134
1135 if (enable)
1136 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1137 else
1138 value = (MAC_CONFIG_REG_SR << 16);
1139
1140 if (qdev->mac_index)
1141 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1142 else
1143 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1144}
1145
1146
1147
1148
1149static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1150{
1151 struct ql3xxx_port_registers __iomem *port_regs =
1152 qdev->mem_map_registers;
1153 u32 value;
1154
1155 if (enable)
1156 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1157 else
1158 value = (MAC_CONFIG_REG_GM << 16);
1159
1160 if (qdev->mac_index)
1161 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1162 else
1163 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1164}
1165
1166
1167
1168
1169static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1170{
1171 struct ql3xxx_port_registers __iomem *port_regs =
1172 qdev->mem_map_registers;
1173 u32 value;
1174
1175 if (enable)
1176 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1177 else
1178 value = (MAC_CONFIG_REG_FD << 16);
1179
1180 if (qdev->mac_index)
1181 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1182 else
1183 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1184}
1185
1186
1187
1188
1189static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1190{
1191 struct ql3xxx_port_registers __iomem *port_regs =
1192 qdev->mem_map_registers;
1193 u32 value;
1194
1195 if (enable)
1196 value =
1197 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1198 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1199 else
1200 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1201
1202 if (qdev->mac_index)
1203 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1204 else
1205 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1206}
1207
1208
1209
1210
1211static int ql_is_fiber(struct ql3_adapter *qdev)
1212{
1213 struct ql3xxx_port_registers __iomem *port_regs =
1214 qdev->mem_map_registers;
1215 u32 bitToCheck = 0;
1216 u32 temp;
1217
1218 switch (qdev->mac_index) {
1219 case 0:
1220 bitToCheck = PORT_STATUS_SM0;
1221 break;
1222 case 1:
1223 bitToCheck = PORT_STATUS_SM1;
1224 break;
1225 }
1226
1227 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228 return (temp & bitToCheck) != 0;
1229}
1230
1231static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1232{
1233 u16 reg;
1234 ql_mii_read_reg(qdev, 0x00, ®);
1235 return (reg & 0x1000) != 0;
1236}
1237
1238
1239
1240
1241static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1242{
1243 struct ql3xxx_port_registers __iomem *port_regs =
1244 qdev->mem_map_registers;
1245 u32 bitToCheck = 0;
1246 u32 temp;
1247
1248 switch (qdev->mac_index) {
1249 case 0:
1250 bitToCheck = PORT_STATUS_AC0;
1251 break;
1252 case 1:
1253 bitToCheck = PORT_STATUS_AC1;
1254 break;
1255 }
1256
1257 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1258 if (temp & bitToCheck) {
1259 if (netif_msg_link(qdev))
1260 printk(KERN_INFO PFX
1261 "%s: Auto-Negotiate complete.\n",
1262 qdev->ndev->name);
1263 return 1;
1264 } else {
1265 if (netif_msg_link(qdev))
1266 printk(KERN_WARNING PFX
1267 "%s: Auto-Negotiate incomplete.\n",
1268 qdev->ndev->name);
1269 return 0;
1270 }
1271}
1272
1273
1274
1275
1276static int ql_is_neg_pause(struct ql3_adapter *qdev)
1277{
1278 if (ql_is_fiber(qdev))
1279 return ql_is_petbi_neg_pause(qdev);
1280 else
1281 return ql_is_phy_neg_pause(qdev);
1282}
1283
1284static int ql_auto_neg_error(struct ql3_adapter *qdev)
1285{
1286 struct ql3xxx_port_registers __iomem *port_regs =
1287 qdev->mem_map_registers;
1288 u32 bitToCheck = 0;
1289 u32 temp;
1290
1291 switch (qdev->mac_index) {
1292 case 0:
1293 bitToCheck = PORT_STATUS_AE0;
1294 break;
1295 case 1:
1296 bitToCheck = PORT_STATUS_AE1;
1297 break;
1298 }
1299 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1300 return (temp & bitToCheck) != 0;
1301}
1302
1303static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1304{
1305 if (ql_is_fiber(qdev))
1306 return SPEED_1000;
1307 else
1308 return ql_phy_get_speed(qdev);
1309}
1310
1311static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1312{
1313 if (ql_is_fiber(qdev))
1314 return 1;
1315 else
1316 return ql_is_full_dup(qdev);
1317}
1318
1319
1320
1321
1322static int ql_link_down_detect(struct ql3_adapter *qdev)
1323{
1324 struct ql3xxx_port_registers __iomem *port_regs =
1325 qdev->mem_map_registers;
1326 u32 bitToCheck = 0;
1327 u32 temp;
1328
1329 switch (qdev->mac_index) {
1330 case 0:
1331 bitToCheck = ISP_CONTROL_LINK_DN_0;
1332 break;
1333 case 1:
1334 bitToCheck = ISP_CONTROL_LINK_DN_1;
1335 break;
1336 }
1337
1338 temp =
1339 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1340 return (temp & bitToCheck) != 0;
1341}
1342
1343
1344
1345
1346static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1347{
1348 struct ql3xxx_port_registers __iomem *port_regs =
1349 qdev->mem_map_registers;
1350
1351 switch (qdev->mac_index) {
1352 case 0:
1353 ql_write_common_reg(qdev,
1354 &port_regs->CommonRegs.ispControlStatus,
1355 (ISP_CONTROL_LINK_DN_0) |
1356 (ISP_CONTROL_LINK_DN_0 << 16));
1357 break;
1358
1359 case 1:
1360 ql_write_common_reg(qdev,
1361 &port_regs->CommonRegs.ispControlStatus,
1362 (ISP_CONTROL_LINK_DN_1) |
1363 (ISP_CONTROL_LINK_DN_1 << 16));
1364 break;
1365
1366 default:
1367 return 1;
1368 }
1369
1370 return 0;
1371}
1372
1373
1374
1375
1376static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1377{
1378 struct ql3xxx_port_registers __iomem *port_regs =
1379 qdev->mem_map_registers;
1380 u32 bitToCheck = 0;
1381 u32 temp;
1382
1383 switch (qdev->mac_index) {
1384 case 0:
1385 bitToCheck = PORT_STATUS_F1_ENABLED;
1386 break;
1387 case 1:
1388 bitToCheck = PORT_STATUS_F3_ENABLED;
1389 break;
1390 default:
1391 break;
1392 }
1393
1394 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1395 if (temp & bitToCheck) {
1396 if (netif_msg_link(qdev))
1397 printk(KERN_DEBUG PFX
1398 "%s: is not link master.\n", qdev->ndev->name);
1399 return 0;
1400 } else {
1401 if (netif_msg_link(qdev))
1402 printk(KERN_DEBUG PFX
1403 "%s: is link master.\n", qdev->ndev->name);
1404 return 1;
1405 }
1406}
1407
1408static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1409{
1410 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1411 PHYAddr[qdev->mac_index]);
1412}
1413
1414static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1415{
1416 u16 reg;
1417 u16 portConfiguration;
1418
1419 if(qdev->phyType == PHY_AGERE_ET1011C) {
1420
1421 ql_mii_write_reg(qdev, 0x13, 0x0000);
1422 }
1423
1424 if(qdev->mac_index == 0)
1425 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1426 else
1427 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1428
1429
1430
1431 if(portConfiguration == 0)
1432 portConfiguration = PORT_CONFIG_DEFAULT;
1433
1434
1435 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1436 PHYAddr[qdev->mac_index]);
1437 reg &= ~PHY_GIG_ALL_PARAMS;
1438
1439 if(portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1440 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1441 reg |= PHY_GIG_ADV_1000F;
1442 else
1443 reg |= PHY_GIG_ADV_1000H;
1444 }
1445
1446 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1447 PHYAddr[qdev->mac_index]);
1448
1449
1450 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1451 PHYAddr[qdev->mac_index]);
1452 reg &= ~PHY_NEG_ALL_PARAMS;
1453
1454 if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1455 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1456
1457 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1458 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1459 reg |= PHY_NEG_ADV_100F;
1460
1461 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1462 reg |= PHY_NEG_ADV_10F;
1463 }
1464
1465 if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1466 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1467 reg |= PHY_NEG_ADV_100H;
1468
1469 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1470 reg |= PHY_NEG_ADV_10H;
1471 }
1472
1473 if(portConfiguration &
1474 PORT_CONFIG_1000MB_SPEED) {
1475 reg |= 1;
1476 }
1477
1478 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1479 PHYAddr[qdev->mac_index]);
1480
1481 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1482
1483 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1484 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1485 PHYAddr[qdev->mac_index]);
1486}
1487
1488static void ql_phy_init_ex(struct ql3_adapter *qdev)
1489{
1490 ql_phy_reset_ex(qdev);
1491 PHY_Setup(qdev);
1492 ql_phy_start_neg_ex(qdev);
1493}
1494
1495
1496
1497
1498static u32 ql_get_link_state(struct ql3_adapter *qdev)
1499{
1500 struct ql3xxx_port_registers __iomem *port_regs =
1501 qdev->mem_map_registers;
1502 u32 bitToCheck = 0;
1503 u32 temp, linkState;
1504
1505 switch (qdev->mac_index) {
1506 case 0:
1507 bitToCheck = PORT_STATUS_UP0;
1508 break;
1509 case 1:
1510 bitToCheck = PORT_STATUS_UP1;
1511 break;
1512 }
1513 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1514 if (temp & bitToCheck) {
1515 linkState = LS_UP;
1516 } else {
1517 linkState = LS_DOWN;
1518 }
1519 return linkState;
1520}
1521
1522static int ql_port_start(struct ql3_adapter *qdev)
1523{
1524 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1525 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1526 2) << 7)) {
1527 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1528 qdev->ndev->name);
1529 return -1;
1530 }
1531
1532 if (ql_is_fiber(qdev)) {
1533 ql_petbi_init(qdev);
1534 } else {
1535
1536 ql_phy_init_ex(qdev);
1537 }
1538
1539 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1540 return 0;
1541}
1542
1543static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1544{
1545
1546 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1547 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1548 2) << 7))
1549 return -1;
1550
1551 if (!ql_auto_neg_error(qdev)) {
1552 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1553
1554 if (netif_msg_link(qdev))
1555 printk(KERN_DEBUG PFX
1556 "%s: Configuring link.\n",
1557 qdev->ndev->
1558 name);
1559 ql_mac_cfg_soft_reset(qdev, 1);
1560 ql_mac_cfg_gig(qdev,
1561 (ql_get_link_speed
1562 (qdev) ==
1563 SPEED_1000));
1564 ql_mac_cfg_full_dup(qdev,
1565 ql_is_link_full_dup
1566 (qdev));
1567 ql_mac_cfg_pause(qdev,
1568 ql_is_neg_pause
1569 (qdev));
1570 ql_mac_cfg_soft_reset(qdev, 0);
1571
1572
1573 if (netif_msg_link(qdev))
1574 printk(KERN_DEBUG PFX
1575 "%s: Enabling mac.\n",
1576 qdev->ndev->
1577 name);
1578 ql_mac_enable(qdev, 1);
1579 }
1580
1581 qdev->port_link_state = LS_UP;
1582 netif_start_queue(qdev->ndev);
1583 netif_carrier_on(qdev->ndev);
1584 if (netif_msg_link(qdev))
1585 printk(KERN_INFO PFX
1586 "%s: Link is up at %d Mbps, %s duplex.\n",
1587 qdev->ndev->name,
1588 ql_get_link_speed(qdev),
1589 ql_is_link_full_dup(qdev)
1590 ? "full" : "half");
1591
1592 } else {
1593
1594 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1595 if (netif_msg_link(qdev))
1596 printk(KERN_DEBUG PFX
1597 "%s: Remote error detected. "
1598 "Calling ql_port_start().\n",
1599 qdev->ndev->
1600 name);
1601
1602
1603
1604
1605 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1606 if(ql_port_start(qdev)) {
1607 return -1;
1608 } else
1609 return 0;
1610 }
1611 }
1612 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1613 return 0;
1614}
1615
1616static void ql_link_state_machine_work(struct work_struct *work)
1617{
1618 struct ql3_adapter *qdev =
1619 container_of(work, struct ql3_adapter, link_state_work.work);
1620
1621 u32 curr_link_state;
1622 unsigned long hw_flags;
1623
1624 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1625
1626 curr_link_state = ql_get_link_state(qdev);
1627
1628 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1629 if (netif_msg_link(qdev))
1630 printk(KERN_INFO PFX
1631 "%s: Reset in progress, skip processing link "
1632 "state.\n", qdev->ndev->name);
1633
1634 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1635
1636
1637 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);\
1638
1639 return;
1640 }
1641
1642 switch (qdev->port_link_state) {
1643 default:
1644 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1645 ql_port_start(qdev);
1646 }
1647 qdev->port_link_state = LS_DOWN;
1648
1649
1650 case LS_DOWN:
1651 if (curr_link_state == LS_UP) {
1652 if (netif_msg_link(qdev))
1653 printk(KERN_INFO PFX "%s: Link is up.\n",
1654 qdev->ndev->name);
1655 if (ql_is_auto_neg_complete(qdev))
1656 ql_finish_auto_neg(qdev);
1657
1658 if (qdev->port_link_state == LS_UP)
1659 ql_link_down_detect_clear(qdev);
1660
1661 qdev->port_link_state = LS_UP;
1662 }
1663 break;
1664
1665 case LS_UP:
1666
1667
1668
1669
1670 if (curr_link_state == LS_DOWN) {
1671 if (netif_msg_link(qdev))
1672 printk(KERN_INFO PFX "%s: Link is down.\n",
1673 qdev->ndev->name);
1674 qdev->port_link_state = LS_DOWN;
1675 }
1676 if (ql_link_down_detect(qdev))
1677 qdev->port_link_state = LS_DOWN;
1678 break;
1679 }
1680 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1681
1682
1683 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1684}
1685
1686
1687
1688
1689static void ql_get_phy_owner(struct ql3_adapter *qdev)
1690{
1691 if (ql_this_adapter_controls_port(qdev))
1692 set_bit(QL_LINK_MASTER,&qdev->flags);
1693 else
1694 clear_bit(QL_LINK_MASTER,&qdev->flags);
1695}
1696
1697
1698
1699
1700static void ql_init_scan_mode(struct ql3_adapter *qdev)
1701{
1702 ql_mii_enable_scan_mode(qdev);
1703
1704 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1705 if (ql_this_adapter_controls_port(qdev))
1706 ql_petbi_init_ex(qdev);
1707 } else {
1708 if (ql_this_adapter_controls_port(qdev))
1709 ql_phy_init_ex(qdev);
1710 }
1711}
1712
1713
1714
1715
1716
1717
1718
1719static int ql_mii_setup(struct ql3_adapter *qdev)
1720{
1721 u32 reg;
1722 struct ql3xxx_port_registers __iomem *port_regs =
1723 qdev->mem_map_registers;
1724
1725 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1726 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1727 2) << 7))
1728 return -1;
1729
1730 if (qdev->device_id == QL3032_DEVICE_ID)
1731 ql_write_page0_reg(qdev,
1732 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1733
1734
1735 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1736
1737 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1738 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1739
1740 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1741 return 0;
1742}
1743
1744static u32 ql_supported_modes(struct ql3_adapter *qdev)
1745{
1746 u32 supported;
1747
1748 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1749 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1750 | SUPPORTED_Autoneg;
1751 } else {
1752 supported = SUPPORTED_10baseT_Half
1753 | SUPPORTED_10baseT_Full
1754 | SUPPORTED_100baseT_Half
1755 | SUPPORTED_100baseT_Full
1756 | SUPPORTED_1000baseT_Half
1757 | SUPPORTED_1000baseT_Full
1758 | SUPPORTED_Autoneg | SUPPORTED_TP;
1759 }
1760
1761 return supported;
1762}
1763
1764static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1765{
1766 int status;
1767 unsigned long hw_flags;
1768 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1769 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1770 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1771 2) << 7)) {
1772 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1773 return 0;
1774 }
1775 status = ql_is_auto_cfg(qdev);
1776 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1777 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1778 return status;
1779}
1780
1781static u32 ql_get_speed(struct ql3_adapter *qdev)
1782{
1783 u32 status;
1784 unsigned long hw_flags;
1785 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1786 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1787 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1788 2) << 7)) {
1789 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1790 return 0;
1791 }
1792 status = ql_get_link_speed(qdev);
1793 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1794 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1795 return status;
1796}
1797
1798static int ql_get_full_dup(struct ql3_adapter *qdev)
1799{
1800 int status;
1801 unsigned long hw_flags;
1802 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1803 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1804 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1805 2) << 7)) {
1806 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1807 return 0;
1808 }
1809 status = ql_is_link_full_dup(qdev);
1810 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1811 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1812 return status;
1813}
1814
1815
1816static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1817{
1818 struct ql3_adapter *qdev = netdev_priv(ndev);
1819
1820 ecmd->transceiver = XCVR_INTERNAL;
1821 ecmd->supported = ql_supported_modes(qdev);
1822
1823 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1824 ecmd->port = PORT_FIBRE;
1825 } else {
1826 ecmd->port = PORT_TP;
1827 ecmd->phy_address = qdev->PHYAddr;
1828 }
1829 ecmd->advertising = ql_supported_modes(qdev);
1830 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1831 ecmd->speed = ql_get_speed(qdev);
1832 ecmd->duplex = ql_get_full_dup(qdev);
1833 return 0;
1834}
1835
1836static void ql_get_drvinfo(struct net_device *ndev,
1837 struct ethtool_drvinfo *drvinfo)
1838{
1839 struct ql3_adapter *qdev = netdev_priv(ndev);
1840 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1841 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1842 strncpy(drvinfo->fw_version, "N/A", 32);
1843 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1844 drvinfo->regdump_len = 0;
1845 drvinfo->eedump_len = 0;
1846}
1847
1848static u32 ql_get_msglevel(struct net_device *ndev)
1849{
1850 struct ql3_adapter *qdev = netdev_priv(ndev);
1851 return qdev->msg_enable;
1852}
1853
1854static void ql_set_msglevel(struct net_device *ndev, u32 value)
1855{
1856 struct ql3_adapter *qdev = netdev_priv(ndev);
1857 qdev->msg_enable = value;
1858}
1859
1860static void ql_get_pauseparam(struct net_device *ndev,
1861 struct ethtool_pauseparam *pause)
1862{
1863 struct ql3_adapter *qdev = netdev_priv(ndev);
1864 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1865
1866 u32 reg;
1867 if(qdev->mac_index == 0)
1868 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1869 else
1870 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1871
1872 pause->autoneg = ql_get_auto_cfg_status(qdev);
1873 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1874 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1875}
1876
1877static const struct ethtool_ops ql3xxx_ethtool_ops = {
1878 .get_settings = ql_get_settings,
1879 .get_drvinfo = ql_get_drvinfo,
1880 .get_link = ethtool_op_get_link,
1881 .get_msglevel = ql_get_msglevel,
1882 .set_msglevel = ql_set_msglevel,
1883 .get_pauseparam = ql_get_pauseparam,
1884};
1885
1886static int ql_populate_free_queue(struct ql3_adapter *qdev)
1887{
1888 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1889 dma_addr_t map;
1890 int err;
1891
1892 while (lrg_buf_cb) {
1893 if (!lrg_buf_cb->skb) {
1894 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1895 qdev->lrg_buffer_len);
1896 if (unlikely(!lrg_buf_cb->skb)) {
1897 printk(KERN_DEBUG PFX
1898 "%s: Failed netdev_alloc_skb().\n",
1899 qdev->ndev->name);
1900 break;
1901 } else {
1902
1903
1904
1905
1906 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1907 map = pci_map_single(qdev->pdev,
1908 lrg_buf_cb->skb->data,
1909 qdev->lrg_buffer_len -
1910 QL_HEADER_SPACE,
1911 PCI_DMA_FROMDEVICE);
1912
1913 err = pci_dma_mapping_error(qdev->pdev, map);
1914 if(err) {
1915 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1916 qdev->ndev->name, err);
1917 dev_kfree_skb(lrg_buf_cb->skb);
1918 lrg_buf_cb->skb = NULL;
1919 break;
1920 }
1921
1922
1923 lrg_buf_cb->buf_phy_addr_low =
1924 cpu_to_le32(LS_64BITS(map));
1925 lrg_buf_cb->buf_phy_addr_high =
1926 cpu_to_le32(MS_64BITS(map));
1927 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1928 pci_unmap_len_set(lrg_buf_cb, maplen,
1929 qdev->lrg_buffer_len -
1930 QL_HEADER_SPACE);
1931 --qdev->lrg_buf_skb_check;
1932 if (!qdev->lrg_buf_skb_check)
1933 return 1;
1934 }
1935 }
1936 lrg_buf_cb = lrg_buf_cb->next;
1937 }
1938 return 0;
1939}
1940
1941
1942
1943
1944static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1945{
1946 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1947 if (qdev->small_buf_release_cnt >= 16) {
1948 while (qdev->small_buf_release_cnt >= 16) {
1949 qdev->small_buf_q_producer_index++;
1950
1951 if (qdev->small_buf_q_producer_index ==
1952 NUM_SBUFQ_ENTRIES)
1953 qdev->small_buf_q_producer_index = 0;
1954 qdev->small_buf_release_cnt -= 8;
1955 }
1956 wmb();
1957 writel(qdev->small_buf_q_producer_index,
1958 &port_regs->CommonRegs.rxSmallQProducerIndex);
1959 }
1960}
1961
1962
1963
1964
1965static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1966{
1967 struct bufq_addr_element *lrg_buf_q_ele;
1968 int i;
1969 struct ql_rcv_buf_cb *lrg_buf_cb;
1970 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1971
1972 if ((qdev->lrg_buf_free_count >= 8)
1973 && (qdev->lrg_buf_release_cnt >= 16)) {
1974
1975 if (qdev->lrg_buf_skb_check)
1976 if (!ql_populate_free_queue(qdev))
1977 return;
1978
1979 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1980
1981 while ((qdev->lrg_buf_release_cnt >= 16)
1982 && (qdev->lrg_buf_free_count >= 8)) {
1983
1984 for (i = 0; i < 8; i++) {
1985 lrg_buf_cb =
1986 ql_get_from_lrg_buf_free_list(qdev);
1987 lrg_buf_q_ele->addr_high =
1988 lrg_buf_cb->buf_phy_addr_high;
1989 lrg_buf_q_ele->addr_low =
1990 lrg_buf_cb->buf_phy_addr_low;
1991 lrg_buf_q_ele++;
1992
1993 qdev->lrg_buf_release_cnt--;
1994 }
1995
1996 qdev->lrg_buf_q_producer_index++;
1997
1998 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1999 qdev->lrg_buf_q_producer_index = 0;
2000
2001 if (qdev->lrg_buf_q_producer_index ==
2002 (qdev->num_lbufq_entries - 1)) {
2003 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2004 }
2005 }
2006 wmb();
2007 qdev->lrg_buf_next_free = lrg_buf_q_ele;
2008 writel(qdev->lrg_buf_q_producer_index,
2009 &port_regs->CommonRegs.rxLargeQProducerIndex);
2010 }
2011}
2012
2013static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2014 struct ob_mac_iocb_rsp *mac_rsp)
2015{
2016 struct ql_tx_buf_cb *tx_cb;
2017 int i;
2018 int retval = 0;
2019
2020 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2021 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2022 }
2023
2024 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
2025
2026
2027 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2028 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2029
2030 qdev->ndev->stats.tx_errors++;
2031 retval = -EIO;
2032 goto frame_not_sent;
2033 }
2034
2035 if(tx_cb->seg_count == 0) {
2036 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2037
2038 qdev->ndev->stats.tx_errors++;
2039 retval = -EIO;
2040 goto invalid_seg_count;
2041 }
2042
2043 pci_unmap_single(qdev->pdev,
2044 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2045 pci_unmap_len(&tx_cb->map[0], maplen),
2046 PCI_DMA_TODEVICE);
2047 tx_cb->seg_count--;
2048 if (tx_cb->seg_count) {
2049 for (i = 1; i < tx_cb->seg_count; i++) {
2050 pci_unmap_page(qdev->pdev,
2051 pci_unmap_addr(&tx_cb->map[i],
2052 mapaddr),
2053 pci_unmap_len(&tx_cb->map[i], maplen),
2054 PCI_DMA_TODEVICE);
2055 }
2056 }
2057 qdev->ndev->stats.tx_packets++;
2058 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
2059
2060frame_not_sent:
2061 dev_kfree_skb_irq(tx_cb->skb);
2062 tx_cb->skb = NULL;
2063
2064invalid_seg_count:
2065 atomic_inc(&qdev->tx_count);
2066}
2067
2068static void ql_get_sbuf(struct ql3_adapter *qdev)
2069{
2070 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2071 qdev->small_buf_index = 0;
2072 qdev->small_buf_release_cnt++;
2073}
2074
2075static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
2076{
2077 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2078 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2079 qdev->lrg_buf_release_cnt++;
2080 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2081 qdev->lrg_buf_index = 0;
2082 return(lrg_buf_cb);
2083}
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2098 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2099{
2100 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2101 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2102 struct sk_buff *skb;
2103 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2104
2105
2106
2107
2108 ql_get_sbuf(qdev);
2109
2110 if (qdev->device_id == QL3022_DEVICE_ID)
2111 lrg_buf_cb1 = ql_get_lbuf(qdev);
2112
2113
2114 lrg_buf_cb2 = ql_get_lbuf(qdev);
2115 skb = lrg_buf_cb2->skb;
2116
2117 qdev->ndev->stats.rx_packets++;
2118 qdev->ndev->stats.rx_bytes += length;
2119
2120 skb_put(skb, length);
2121 pci_unmap_single(qdev->pdev,
2122 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2123 pci_unmap_len(lrg_buf_cb2, maplen),
2124 PCI_DMA_FROMDEVICE);
2125 prefetch(skb->data);
2126 skb->ip_summed = CHECKSUM_NONE;
2127 skb->protocol = eth_type_trans(skb, qdev->ndev);
2128
2129 netif_receive_skb(skb);
2130 qdev->ndev->last_rx = jiffies;
2131 lrg_buf_cb2->skb = NULL;
2132
2133 if (qdev->device_id == QL3022_DEVICE_ID)
2134 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2135 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2136}
2137
2138static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2139 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2140{
2141 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2142 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2143 struct sk_buff *skb1 = NULL, *skb2;
2144 struct net_device *ndev = qdev->ndev;
2145 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2146 u16 size = 0;
2147
2148
2149
2150
2151
2152 ql_get_sbuf(qdev);
2153
2154 if (qdev->device_id == QL3022_DEVICE_ID) {
2155
2156 lrg_buf_cb1 = ql_get_lbuf(qdev);
2157 skb1 = lrg_buf_cb1->skb;
2158 size = ETH_HLEN;
2159 if (*((u16 *) skb1->data) != 0xFFFF)
2160 size += VLAN_ETH_HLEN - ETH_HLEN;
2161 }
2162
2163
2164 lrg_buf_cb2 = ql_get_lbuf(qdev);
2165 skb2 = lrg_buf_cb2->skb;
2166
2167 skb_put(skb2, length);
2168 pci_unmap_single(qdev->pdev,
2169 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2170 pci_unmap_len(lrg_buf_cb2, maplen),
2171 PCI_DMA_FROMDEVICE);
2172 prefetch(skb2->data);
2173
2174 skb2->ip_summed = CHECKSUM_NONE;
2175 if (qdev->device_id == QL3022_DEVICE_ID) {
2176
2177
2178
2179
2180 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2181 skb_push(skb2, size), size);
2182 } else {
2183 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2184 if (checksum &
2185 (IB_IP_IOCB_RSP_3032_ICE |
2186 IB_IP_IOCB_RSP_3032_CE)) {
2187 printk(KERN_ERR
2188 "%s: Bad checksum for this %s packet, checksum = %x.\n",
2189 __func__,
2190 ((checksum &
2191 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2192 "UDP"),checksum);
2193 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2194 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2195 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2196 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2197 }
2198 }
2199 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2200
2201 netif_receive_skb(skb2);
2202 ndev->stats.rx_packets++;
2203 ndev->stats.rx_bytes += length;
2204 ndev->last_rx = jiffies;
2205 lrg_buf_cb2->skb = NULL;
2206
2207 if (qdev->device_id == QL3022_DEVICE_ID)
2208 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2209 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2210}
2211
2212static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2213 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2214{
2215 struct net_rsp_iocb *net_rsp;
2216 struct net_device *ndev = qdev->ndev;
2217 int work_done = 0;
2218
2219
2220 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2221 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2222
2223 net_rsp = qdev->rsp_current;
2224 rmb();
2225
2226
2227
2228
2229 if (qdev->device_id == QL3032_DEVICE_ID)
2230 net_rsp->opcode &= 0x7f;
2231 switch (net_rsp->opcode) {
2232
2233 case OPCODE_OB_MAC_IOCB_FN0:
2234 case OPCODE_OB_MAC_IOCB_FN2:
2235 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2236 net_rsp);
2237 (*tx_cleaned)++;
2238 break;
2239
2240 case OPCODE_IB_MAC_IOCB:
2241 case OPCODE_IB_3032_MAC_IOCB:
2242 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2243 net_rsp);
2244 (*rx_cleaned)++;
2245 break;
2246
2247 case OPCODE_IB_IP_IOCB:
2248 case OPCODE_IB_3032_IP_IOCB:
2249 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2250 net_rsp);
2251 (*rx_cleaned)++;
2252 break;
2253 default:
2254 {
2255 u32 *tmp = (u32 *) net_rsp;
2256 printk(KERN_ERR PFX
2257 "%s: Hit default case, not "
2258 "handled!\n"
2259 " dropping the packet, opcode = "
2260 "%x.\n",
2261 ndev->name, net_rsp->opcode);
2262 printk(KERN_ERR PFX
2263 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2264 (unsigned long int)tmp[0],
2265 (unsigned long int)tmp[1],
2266 (unsigned long int)tmp[2],
2267 (unsigned long int)tmp[3]);
2268 }
2269 }
2270
2271 qdev->rsp_consumer_index++;
2272
2273 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2274 qdev->rsp_consumer_index = 0;
2275 qdev->rsp_current = qdev->rsp_q_virt_addr;
2276 } else {
2277 qdev->rsp_current++;
2278 }
2279
2280 work_done = *tx_cleaned + *rx_cleaned;
2281 }
2282
2283 return work_done;
2284}
2285
2286static int ql_poll(struct napi_struct *napi, int budget)
2287{
2288 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2289 struct net_device *ndev = qdev->ndev;
2290 int rx_cleaned = 0, tx_cleaned = 0;
2291 unsigned long hw_flags;
2292 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2293
2294 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2295
2296 if (tx_cleaned + rx_cleaned != budget) {
2297 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2298 __netif_rx_complete(ndev, napi);
2299 ql_update_small_bufq_prod_index(qdev);
2300 ql_update_lrg_bufq_prod_index(qdev);
2301 writel(qdev->rsp_consumer_index,
2302 &port_regs->CommonRegs.rspQConsumerIndex);
2303 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2304
2305 ql_enable_interrupts(qdev);
2306 }
2307 return tx_cleaned + rx_cleaned;
2308}
2309
2310static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2311{
2312
2313 struct net_device *ndev = dev_id;
2314 struct ql3_adapter *qdev = netdev_priv(ndev);
2315 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2316 u32 value;
2317 int handled = 1;
2318 u32 var;
2319
2320 port_regs = qdev->mem_map_registers;
2321
2322 value =
2323 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2324
2325 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2326 spin_lock(&qdev->adapter_lock);
2327 netif_stop_queue(qdev->ndev);
2328 netif_carrier_off(qdev->ndev);
2329 ql_disable_interrupts(qdev);
2330 qdev->port_link_state = LS_DOWN;
2331 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2332
2333 if (value & ISP_CONTROL_FE) {
2334
2335
2336
2337 var =
2338 ql_read_page0_reg_l(qdev,
2339 &port_regs->PortFatalErrStatus);
2340 printk(KERN_WARNING PFX
2341 "%s: Resetting chip. PortFatalErrStatus "
2342 "register = 0x%x\n", ndev->name, var);
2343 set_bit(QL_RESET_START,&qdev->flags) ;
2344 } else {
2345
2346
2347
2348 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2349 printk(KERN_ERR PFX
2350 "%s: Another function issued a reset to the "
2351 "chip. ISR value = %x.\n", ndev->name, value);
2352 }
2353 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2354 spin_unlock(&qdev->adapter_lock);
2355 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2356 ql_disable_interrupts(qdev);
2357 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2358 __netif_rx_schedule(ndev, &qdev->napi);
2359 }
2360 } else {
2361 return IRQ_NONE;
2362 }
2363
2364 return IRQ_RETVAL(handled);
2365}
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376static int ql_get_seg_count(struct ql3_adapter *qdev,
2377 unsigned short frags)
2378{
2379 if (qdev->device_id == QL3022_DEVICE_ID)
2380 return 1;
2381
2382 switch(frags) {
2383 case 0: return 1;
2384 case 1: return 2;
2385 case 2: return 3;
2386 case 3: return 5;
2387 case 4: return 6;
2388 case 5: return 7;
2389 case 6: return 8;
2390 case 7: return 10;
2391 case 8: return 11;
2392 case 9: return 12;
2393 case 10: return 13;
2394 case 11: return 15;
2395 case 12: return 16;
2396 case 13: return 17;
2397 case 14: return 18;
2398 case 15: return 20;
2399 case 16: return 21;
2400 case 17: return 22;
2401 case 18: return 23;
2402 }
2403 return -1;
2404}
2405
2406static void ql_hw_csum_setup(const struct sk_buff *skb,
2407 struct ob_mac_iocb_req *mac_iocb_ptr)
2408{
2409 const struct iphdr *ip = ip_hdr(skb);
2410
2411 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2412 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2413
2414 if (ip->protocol == IPPROTO_TCP) {
2415 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2416 OB_3032MAC_IOCB_REQ_IC;
2417 } else {
2418 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2419 OB_3032MAC_IOCB_REQ_IC;
2420 }
2421
2422}
2423
2424
2425
2426
2427
2428static int ql_send_map(struct ql3_adapter *qdev,
2429 struct ob_mac_iocb_req *mac_iocb_ptr,
2430 struct ql_tx_buf_cb *tx_cb,
2431 struct sk_buff *skb)
2432{
2433 struct oal *oal;
2434 struct oal_entry *oal_entry;
2435 int len = skb_headlen(skb);
2436 dma_addr_t map;
2437 int err;
2438 int completed_segs, i;
2439 int seg_cnt, seg = 0;
2440 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2441
2442 seg_cnt = tx_cb->seg_count;
2443
2444
2445
2446 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2447
2448 err = pci_dma_mapping_error(qdev->pdev, map);
2449 if(err) {
2450 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2451 qdev->ndev->name, err);
2452
2453 return NETDEV_TX_BUSY;
2454 }
2455
2456 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2457 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2458 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2459 oal_entry->len = cpu_to_le32(len);
2460 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2461 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2462 seg++;
2463
2464 if (seg_cnt == 1) {
2465
2466 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2467 } else {
2468 oal = tx_cb->oal;
2469 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2470 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2471 oal_entry++;
2472 if ((seg == 2 && seg_cnt > 3) ||
2473 (seg == 7 && seg_cnt > 8) ||
2474 (seg == 12 && seg_cnt > 13) ||
2475 (seg == 17 && seg_cnt > 18)) {
2476
2477 map = pci_map_single(qdev->pdev, oal,
2478 sizeof(struct oal),
2479 PCI_DMA_TODEVICE);
2480
2481 err = pci_dma_mapping_error(qdev->pdev, map);
2482 if(err) {
2483
2484 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2485 qdev->ndev->name, err);
2486 goto map_error;
2487 }
2488
2489 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2490 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2491 oal_entry->len =
2492 cpu_to_le32(sizeof(struct oal) |
2493 OAL_CONT_ENTRY);
2494 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2495 map);
2496 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2497 sizeof(struct oal));
2498 oal_entry = (struct oal_entry *)oal;
2499 oal++;
2500 seg++;
2501 }
2502
2503 map =
2504 pci_map_page(qdev->pdev, frag->page,
2505 frag->page_offset, frag->size,
2506 PCI_DMA_TODEVICE);
2507
2508 err = pci_dma_mapping_error(qdev->pdev, map);
2509 if(err) {
2510 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2511 qdev->ndev->name, err);
2512 goto map_error;
2513 }
2514
2515 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2516 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2517 oal_entry->len = cpu_to_le32(frag->size);
2518 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2519 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2520 frag->size);
2521 }
2522
2523 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2524 }
2525
2526 return NETDEV_TX_OK;
2527
2528map_error:
2529
2530
2531
2532
2533
2534 seg = 1;
2535 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2536 oal = tx_cb->oal;
2537 for (i=0; i<completed_segs; i++,seg++) {
2538 oal_entry++;
2539
2540 if((seg == 2 && seg_cnt > 3) ||
2541 (seg == 7 && seg_cnt > 8) ||
2542 (seg == 12 && seg_cnt > 13) ||
2543 (seg == 17 && seg_cnt > 18)) {
2544 pci_unmap_single(qdev->pdev,
2545 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2546 pci_unmap_len(&tx_cb->map[seg], maplen),
2547 PCI_DMA_TODEVICE);
2548 oal++;
2549 seg++;
2550 }
2551
2552 pci_unmap_page(qdev->pdev,
2553 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2554 pci_unmap_len(&tx_cb->map[seg], maplen),
2555 PCI_DMA_TODEVICE);
2556 }
2557
2558 pci_unmap_single(qdev->pdev,
2559 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2560 pci_unmap_addr(&tx_cb->map[0], maplen),
2561 PCI_DMA_TODEVICE);
2562
2563 return NETDEV_TX_BUSY;
2564
2565}
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2579{
2580 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2581 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2582 struct ql_tx_buf_cb *tx_cb;
2583 u32 tot_len = skb->len;
2584 struct ob_mac_iocb_req *mac_iocb_ptr;
2585
2586 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2587 return NETDEV_TX_BUSY;
2588 }
2589
2590 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2591 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2592 (skb_shinfo(skb)->nr_frags))) == -1) {
2593 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2594 return NETDEV_TX_OK;
2595 }
2596
2597 mac_iocb_ptr = tx_cb->queue_entry;
2598 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2599 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2600 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2601 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2602 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2603 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2604 tx_cb->skb = skb;
2605 if (qdev->device_id == QL3032_DEVICE_ID &&
2606 skb->ip_summed == CHECKSUM_PARTIAL)
2607 ql_hw_csum_setup(skb, mac_iocb_ptr);
2608
2609 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2610 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2611 return NETDEV_TX_BUSY;
2612 }
2613
2614 wmb();
2615 qdev->req_producer_index++;
2616 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2617 qdev->req_producer_index = 0;
2618 wmb();
2619 ql_write_common_reg_l(qdev,
2620 &port_regs->CommonRegs.reqQProducerIndex,
2621 qdev->req_producer_index);
2622
2623 ndev->trans_start = jiffies;
2624 if (netif_msg_tx_queued(qdev))
2625 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2626 ndev->name, qdev->req_producer_index, skb->len);
2627
2628 atomic_dec(&qdev->tx_count);
2629 return NETDEV_TX_OK;
2630}
2631
2632static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2633{
2634 qdev->req_q_size =
2635 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2636
2637 qdev->req_q_virt_addr =
2638 pci_alloc_consistent(qdev->pdev,
2639 (size_t) qdev->req_q_size,
2640 &qdev->req_q_phy_addr);
2641
2642 if ((qdev->req_q_virt_addr == NULL) ||
2643 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2644 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2645 qdev->ndev->name);
2646 return -ENOMEM;
2647 }
2648
2649 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2650
2651 qdev->rsp_q_virt_addr =
2652 pci_alloc_consistent(qdev->pdev,
2653 (size_t) qdev->rsp_q_size,
2654 &qdev->rsp_q_phy_addr);
2655
2656 if ((qdev->rsp_q_virt_addr == NULL) ||
2657 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2658 printk(KERN_ERR PFX
2659 "%s: rspQ allocation failed\n",
2660 qdev->ndev->name);
2661 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2662 qdev->req_q_virt_addr,
2663 qdev->req_q_phy_addr);
2664 return -ENOMEM;
2665 }
2666
2667 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2668
2669 return 0;
2670}
2671
2672static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2673{
2674 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2675 printk(KERN_INFO PFX
2676 "%s: Already done.\n", qdev->ndev->name);
2677 return;
2678 }
2679
2680 pci_free_consistent(qdev->pdev,
2681 qdev->req_q_size,
2682 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2683
2684 qdev->req_q_virt_addr = NULL;
2685
2686 pci_free_consistent(qdev->pdev,
2687 qdev->rsp_q_size,
2688 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2689
2690 qdev->rsp_q_virt_addr = NULL;
2691
2692 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2693}
2694
2695static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2696{
2697
2698 qdev->lrg_buf_q_size =
2699 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2700 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2701 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2702 else
2703 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2704
2705 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2706 if (qdev->lrg_buf == NULL) {
2707 printk(KERN_ERR PFX
2708 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2709 return -ENOMEM;
2710 }
2711
2712 qdev->lrg_buf_q_alloc_virt_addr =
2713 pci_alloc_consistent(qdev->pdev,
2714 qdev->lrg_buf_q_alloc_size,
2715 &qdev->lrg_buf_q_alloc_phy_addr);
2716
2717 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2718 printk(KERN_ERR PFX
2719 "%s: lBufQ failed\n", qdev->ndev->name);
2720 return -ENOMEM;
2721 }
2722 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2723 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2724
2725
2726 qdev->small_buf_q_size =
2727 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2728 if (qdev->small_buf_q_size < PAGE_SIZE)
2729 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2730 else
2731 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2732
2733 qdev->small_buf_q_alloc_virt_addr =
2734 pci_alloc_consistent(qdev->pdev,
2735 qdev->small_buf_q_alloc_size,
2736 &qdev->small_buf_q_alloc_phy_addr);
2737
2738 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2739 printk(KERN_ERR PFX
2740 "%s: Small Buffer Queue allocation failed.\n",
2741 qdev->ndev->name);
2742 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2743 qdev->lrg_buf_q_alloc_virt_addr,
2744 qdev->lrg_buf_q_alloc_phy_addr);
2745 return -ENOMEM;
2746 }
2747
2748 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2749 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2750 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2751 return 0;
2752}
2753
2754static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2755{
2756 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2757 printk(KERN_INFO PFX
2758 "%s: Already done.\n", qdev->ndev->name);
2759 return;
2760 }
2761 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2762 pci_free_consistent(qdev->pdev,
2763 qdev->lrg_buf_q_alloc_size,
2764 qdev->lrg_buf_q_alloc_virt_addr,
2765 qdev->lrg_buf_q_alloc_phy_addr);
2766
2767 qdev->lrg_buf_q_virt_addr = NULL;
2768
2769 pci_free_consistent(qdev->pdev,
2770 qdev->small_buf_q_alloc_size,
2771 qdev->small_buf_q_alloc_virt_addr,
2772 qdev->small_buf_q_alloc_phy_addr);
2773
2774 qdev->small_buf_q_virt_addr = NULL;
2775
2776 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2777}
2778
2779static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2780{
2781 int i;
2782 struct bufq_addr_element *small_buf_q_entry;
2783
2784
2785 qdev->small_buf_total_size =
2786 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2787 QL_SMALL_BUFFER_SIZE);
2788
2789 qdev->small_buf_virt_addr =
2790 pci_alloc_consistent(qdev->pdev,
2791 qdev->small_buf_total_size,
2792 &qdev->small_buf_phy_addr);
2793
2794 if (qdev->small_buf_virt_addr == NULL) {
2795 printk(KERN_ERR PFX
2796 "%s: Failed to get small buffer memory.\n",
2797 qdev->ndev->name);
2798 return -ENOMEM;
2799 }
2800
2801 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2802 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2803
2804 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2805
2806
2807 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2808 small_buf_q_entry->addr_high =
2809 cpu_to_le32(qdev->small_buf_phy_addr_high);
2810 small_buf_q_entry->addr_low =
2811 cpu_to_le32(qdev->small_buf_phy_addr_low +
2812 (i * QL_SMALL_BUFFER_SIZE));
2813 small_buf_q_entry++;
2814 }
2815 qdev->small_buf_index = 0;
2816 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2817 return 0;
2818}
2819
2820static void ql_free_small_buffers(struct ql3_adapter *qdev)
2821{
2822 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2823 printk(KERN_INFO PFX
2824 "%s: Already done.\n", qdev->ndev->name);
2825 return;
2826 }
2827 if (qdev->small_buf_virt_addr != NULL) {
2828 pci_free_consistent(qdev->pdev,
2829 qdev->small_buf_total_size,
2830 qdev->small_buf_virt_addr,
2831 qdev->small_buf_phy_addr);
2832
2833 qdev->small_buf_virt_addr = NULL;
2834 }
2835}
2836
2837static void ql_free_large_buffers(struct ql3_adapter *qdev)
2838{
2839 int i = 0;
2840 struct ql_rcv_buf_cb *lrg_buf_cb;
2841
2842 for (i = 0; i < qdev->num_large_buffers; i++) {
2843 lrg_buf_cb = &qdev->lrg_buf[i];
2844 if (lrg_buf_cb->skb) {
2845 dev_kfree_skb(lrg_buf_cb->skb);
2846 pci_unmap_single(qdev->pdev,
2847 pci_unmap_addr(lrg_buf_cb, mapaddr),
2848 pci_unmap_len(lrg_buf_cb, maplen),
2849 PCI_DMA_FROMDEVICE);
2850 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2851 } else {
2852 break;
2853 }
2854 }
2855}
2856
2857static void ql_init_large_buffers(struct ql3_adapter *qdev)
2858{
2859 int i;
2860 struct ql_rcv_buf_cb *lrg_buf_cb;
2861 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2862
2863 for (i = 0; i < qdev->num_large_buffers; i++) {
2864 lrg_buf_cb = &qdev->lrg_buf[i];
2865 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2866 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2867 buf_addr_ele++;
2868 }
2869 qdev->lrg_buf_index = 0;
2870 qdev->lrg_buf_skb_check = 0;
2871}
2872
2873static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2874{
2875 int i;
2876 struct ql_rcv_buf_cb *lrg_buf_cb;
2877 struct sk_buff *skb;
2878 dma_addr_t map;
2879 int err;
2880
2881 for (i = 0; i < qdev->num_large_buffers; i++) {
2882 skb = netdev_alloc_skb(qdev->ndev,
2883 qdev->lrg_buffer_len);
2884 if (unlikely(!skb)) {
2885
2886 printk(KERN_ERR PFX
2887 "%s: large buff alloc failed, "
2888 "for %d bytes at index %d.\n",
2889 qdev->ndev->name,
2890 qdev->lrg_buffer_len * 2, i);
2891 ql_free_large_buffers(qdev);
2892 return -ENOMEM;
2893 } else {
2894
2895 lrg_buf_cb = &qdev->lrg_buf[i];
2896 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2897 lrg_buf_cb->index = i;
2898 lrg_buf_cb->skb = skb;
2899
2900
2901
2902
2903 skb_reserve(skb, QL_HEADER_SPACE);
2904 map = pci_map_single(qdev->pdev,
2905 skb->data,
2906 qdev->lrg_buffer_len -
2907 QL_HEADER_SPACE,
2908 PCI_DMA_FROMDEVICE);
2909
2910 err = pci_dma_mapping_error(qdev->pdev, map);
2911 if(err) {
2912 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2913 qdev->ndev->name, err);
2914 ql_free_large_buffers(qdev);
2915 return -ENOMEM;
2916 }
2917
2918 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2919 pci_unmap_len_set(lrg_buf_cb, maplen,
2920 qdev->lrg_buffer_len -
2921 QL_HEADER_SPACE);
2922 lrg_buf_cb->buf_phy_addr_low =
2923 cpu_to_le32(LS_64BITS(map));
2924 lrg_buf_cb->buf_phy_addr_high =
2925 cpu_to_le32(MS_64BITS(map));
2926 }
2927 }
2928 return 0;
2929}
2930
2931static void ql_free_send_free_list(struct ql3_adapter *qdev)
2932{
2933 struct ql_tx_buf_cb *tx_cb;
2934 int i;
2935
2936 tx_cb = &qdev->tx_buf[0];
2937 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2938 if (tx_cb->oal) {
2939 kfree(tx_cb->oal);
2940 tx_cb->oal = NULL;
2941 }
2942 tx_cb++;
2943 }
2944}
2945
2946static int ql_create_send_free_list(struct ql3_adapter *qdev)
2947{
2948 struct ql_tx_buf_cb *tx_cb;
2949 int i;
2950 struct ob_mac_iocb_req *req_q_curr =
2951 qdev->req_q_virt_addr;
2952
2953
2954 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2955
2956 tx_cb = &qdev->tx_buf[i];
2957 tx_cb->skb = NULL;
2958 tx_cb->queue_entry = req_q_curr;
2959 req_q_curr++;
2960 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2961 if (tx_cb->oal == NULL)
2962 return -1;
2963 }
2964 return 0;
2965}
2966
2967static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2968{
2969 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2970 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2971 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2972 }
2973 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2974
2975
2976
2977 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2978 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2979 } else {
2980 printk(KERN_ERR PFX
2981 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2982 qdev->ndev->name);
2983 return -ENOMEM;
2984 }
2985 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2986 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2987 qdev->max_frame_size =
2988 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2989
2990
2991
2992
2993
2994
2995 qdev->shadow_reg_virt_addr =
2996 pci_alloc_consistent(qdev->pdev,
2997 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2998
2999 if (qdev->shadow_reg_virt_addr != NULL) {
3000 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3001 qdev->req_consumer_index_phy_addr_high =
3002 MS_64BITS(qdev->shadow_reg_phy_addr);
3003 qdev->req_consumer_index_phy_addr_low =
3004 LS_64BITS(qdev->shadow_reg_phy_addr);
3005
3006 qdev->prsp_producer_index =
3007 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3008 qdev->rsp_producer_index_phy_addr_high =
3009 qdev->req_consumer_index_phy_addr_high;
3010 qdev->rsp_producer_index_phy_addr_low =
3011 qdev->req_consumer_index_phy_addr_low + 8;
3012 } else {
3013 printk(KERN_ERR PFX
3014 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3015 return -ENOMEM;
3016 }
3017
3018 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3019 printk(KERN_ERR PFX
3020 "%s: ql_alloc_net_req_rsp_queues failed.\n",
3021 qdev->ndev->name);
3022 goto err_req_rsp;
3023 }
3024
3025 if (ql_alloc_buffer_queues(qdev) != 0) {
3026 printk(KERN_ERR PFX
3027 "%s: ql_alloc_buffer_queues failed.\n",
3028 qdev->ndev->name);
3029 goto err_buffer_queues;
3030 }
3031
3032 if (ql_alloc_small_buffers(qdev) != 0) {
3033 printk(KERN_ERR PFX
3034 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3035 goto err_small_buffers;
3036 }
3037
3038 if (ql_alloc_large_buffers(qdev) != 0) {
3039 printk(KERN_ERR PFX
3040 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3041 goto err_small_buffers;
3042 }
3043
3044
3045 ql_init_large_buffers(qdev);
3046 if (ql_create_send_free_list(qdev))
3047 goto err_free_list;
3048
3049 qdev->rsp_current = qdev->rsp_q_virt_addr;
3050
3051 return 0;
3052err_free_list:
3053 ql_free_send_free_list(qdev);
3054err_small_buffers:
3055 ql_free_buffer_queues(qdev);
3056err_buffer_queues:
3057 ql_free_net_req_rsp_queues(qdev);
3058err_req_rsp:
3059 pci_free_consistent(qdev->pdev,
3060 PAGE_SIZE,
3061 qdev->shadow_reg_virt_addr,
3062 qdev->shadow_reg_phy_addr);
3063
3064 return -ENOMEM;
3065}
3066
3067static void ql_free_mem_resources(struct ql3_adapter *qdev)
3068{
3069 ql_free_send_free_list(qdev);
3070 ql_free_large_buffers(qdev);
3071 ql_free_small_buffers(qdev);
3072 ql_free_buffer_queues(qdev);
3073 ql_free_net_req_rsp_queues(qdev);
3074 if (qdev->shadow_reg_virt_addr != NULL) {
3075 pci_free_consistent(qdev->pdev,
3076 PAGE_SIZE,
3077 qdev->shadow_reg_virt_addr,
3078 qdev->shadow_reg_phy_addr);
3079 qdev->shadow_reg_virt_addr = NULL;
3080 }
3081}
3082
3083static int ql_init_misc_registers(struct ql3_adapter *qdev)
3084{
3085 struct ql3xxx_local_ram_registers __iomem *local_ram =
3086 (void __iomem *)qdev->mem_map_registers;
3087
3088 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3089 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3090 2) << 4))
3091 return -1;
3092
3093 ql_write_page2_reg(qdev,
3094 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3095
3096 ql_write_page2_reg(qdev,
3097 &local_ram->maxBufletCount,
3098 qdev->nvram_data.bufletCount);
3099
3100 ql_write_page2_reg(qdev,
3101 &local_ram->freeBufletThresholdLow,
3102 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3103 (qdev->nvram_data.tcpWindowThreshold0));
3104
3105 ql_write_page2_reg(qdev,
3106 &local_ram->freeBufletThresholdHigh,
3107 qdev->nvram_data.tcpWindowThreshold50);
3108
3109 ql_write_page2_reg(qdev,
3110 &local_ram->ipHashTableBase,
3111 (qdev->nvram_data.ipHashTableBaseHi << 16) |
3112 qdev->nvram_data.ipHashTableBaseLo);
3113 ql_write_page2_reg(qdev,
3114 &local_ram->ipHashTableCount,
3115 qdev->nvram_data.ipHashTableSize);
3116 ql_write_page2_reg(qdev,
3117 &local_ram->tcpHashTableBase,
3118 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3119 qdev->nvram_data.tcpHashTableBaseLo);
3120 ql_write_page2_reg(qdev,
3121 &local_ram->tcpHashTableCount,
3122 qdev->nvram_data.tcpHashTableSize);
3123 ql_write_page2_reg(qdev,
3124 &local_ram->ncbBase,
3125 (qdev->nvram_data.ncbTableBaseHi << 16) |
3126 qdev->nvram_data.ncbTableBaseLo);
3127 ql_write_page2_reg(qdev,
3128 &local_ram->maxNcbCount,
3129 qdev->nvram_data.ncbTableSize);
3130 ql_write_page2_reg(qdev,
3131 &local_ram->drbBase,
3132 (qdev->nvram_data.drbTableBaseHi << 16) |
3133 qdev->nvram_data.drbTableBaseLo);
3134 ql_write_page2_reg(qdev,
3135 &local_ram->maxDrbCount,
3136 qdev->nvram_data.drbTableSize);
3137 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3138 return 0;
3139}
3140
3141static int ql_adapter_initialize(struct ql3_adapter *qdev)
3142{
3143 u32 value;
3144 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3145 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3146 (void __iomem *)port_regs;
3147 u32 delay = 10;
3148 int status = 0;
3149
3150 if(ql_mii_setup(qdev))
3151 return -1;
3152
3153
3154 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3155 (ISP_SERIAL_PORT_IF_WE |
3156 (ISP_SERIAL_PORT_IF_WE << 16)));
3157
3158 qdev->port_link_state = LS_DOWN;
3159 netif_carrier_off(qdev->ndev);
3160
3161
3162 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3163 (ISP_SERIAL_PORT_IF_SDE |
3164 (ISP_SERIAL_PORT_IF_SDE << 16)));
3165
3166
3167 *((u32 *) (qdev->preq_consumer_index)) = 0;
3168 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3169 qdev->req_producer_index = 0;
3170
3171 ql_write_page1_reg(qdev,
3172 &hmem_regs->reqConsumerIndexAddrHigh,
3173 qdev->req_consumer_index_phy_addr_high);
3174 ql_write_page1_reg(qdev,
3175 &hmem_regs->reqConsumerIndexAddrLow,
3176 qdev->req_consumer_index_phy_addr_low);
3177
3178 ql_write_page1_reg(qdev,
3179 &hmem_regs->reqBaseAddrHigh,
3180 MS_64BITS(qdev->req_q_phy_addr));
3181 ql_write_page1_reg(qdev,
3182 &hmem_regs->reqBaseAddrLow,
3183 LS_64BITS(qdev->req_q_phy_addr));
3184 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3185
3186
3187 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3188 qdev->rsp_consumer_index = 0;
3189 qdev->rsp_current = qdev->rsp_q_virt_addr;
3190
3191 ql_write_page1_reg(qdev,
3192 &hmem_regs->rspProducerIndexAddrHigh,
3193 qdev->rsp_producer_index_phy_addr_high);
3194
3195 ql_write_page1_reg(qdev,
3196 &hmem_regs->rspProducerIndexAddrLow,
3197 qdev->rsp_producer_index_phy_addr_low);
3198
3199 ql_write_page1_reg(qdev,
3200 &hmem_regs->rspBaseAddrHigh,
3201 MS_64BITS(qdev->rsp_q_phy_addr));
3202
3203 ql_write_page1_reg(qdev,
3204 &hmem_regs->rspBaseAddrLow,
3205 LS_64BITS(qdev->rsp_q_phy_addr));
3206
3207 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3208
3209
3210 ql_write_page1_reg(qdev,
3211 &hmem_regs->rxLargeQBaseAddrHigh,
3212 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3213
3214 ql_write_page1_reg(qdev,
3215 &hmem_regs->rxLargeQBaseAddrLow,
3216 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3217
3218 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3219
3220 ql_write_page1_reg(qdev,
3221 &hmem_regs->rxLargeBufferLength,
3222 qdev->lrg_buffer_len);
3223
3224
3225 ql_write_page1_reg(qdev,
3226 &hmem_regs->rxSmallQBaseAddrHigh,
3227 MS_64BITS(qdev->small_buf_q_phy_addr));
3228
3229 ql_write_page1_reg(qdev,
3230 &hmem_regs->rxSmallQBaseAddrLow,
3231 LS_64BITS(qdev->small_buf_q_phy_addr));
3232
3233 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3234 ql_write_page1_reg(qdev,
3235 &hmem_regs->rxSmallBufferLength,
3236 QL_SMALL_BUFFER_SIZE);
3237
3238 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3239 qdev->small_buf_release_cnt = 8;
3240 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3241 qdev->lrg_buf_release_cnt = 8;
3242 qdev->lrg_buf_next_free =
3243 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3244 qdev->small_buf_index = 0;
3245 qdev->lrg_buf_index = 0;
3246 qdev->lrg_buf_free_count = 0;
3247 qdev->lrg_buf_free_head = NULL;
3248 qdev->lrg_buf_free_tail = NULL;
3249
3250 ql_write_common_reg(qdev,
3251 &port_regs->CommonRegs.
3252 rxSmallQProducerIndex,
3253 qdev->small_buf_q_producer_index);
3254 ql_write_common_reg(qdev,
3255 &port_regs->CommonRegs.
3256 rxLargeQProducerIndex,
3257 qdev->lrg_buf_q_producer_index);
3258
3259
3260
3261
3262
3263 clear_bit(QL_LINK_MASTER, &qdev->flags);
3264 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3265 if ((value & PORT_STATUS_IC) == 0) {
3266
3267
3268 if(ql_init_misc_registers(qdev)) {
3269 status = -1;
3270 goto out;
3271 }
3272
3273 value = qdev->nvram_data.tcpMaxWindowSize;
3274 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3275
3276 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3277
3278 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3279 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3280 * 2) << 13)) {
3281 status = -1;
3282 goto out;
3283 }
3284 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3285 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3286 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3287 16) | (INTERNAL_CHIP_SD |
3288 INTERNAL_CHIP_WE)));
3289 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3290 }
3291
3292 if (qdev->mac_index)
3293 ql_write_page0_reg(qdev,
3294 &port_regs->mac1MaxFrameLengthReg,
3295 qdev->max_frame_size);
3296 else
3297 ql_write_page0_reg(qdev,
3298 &port_regs->mac0MaxFrameLengthReg,
3299 qdev->max_frame_size);
3300
3301 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3302 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3303 2) << 7)) {
3304 status = -1;
3305 goto out;
3306 }
3307
3308 PHY_Setup(qdev);
3309 ql_init_scan_mode(qdev);
3310 ql_get_phy_owner(qdev);
3311
3312
3313
3314
3315 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3316 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3317 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3318 ((qdev->ndev->dev_addr[2] << 24)
3319 | (qdev->ndev->dev_addr[3] << 16)
3320 | (qdev->ndev->dev_addr[4] << 8)
3321 | qdev->ndev->dev_addr[5]));
3322
3323
3324 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3325 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3326 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3327 ((qdev->ndev->dev_addr[0] << 8)
3328 | qdev->ndev->dev_addr[1]));
3329
3330
3331 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3332 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3333 MAC_ADDR_INDIRECT_PTR_REG_PE));
3334
3335
3336 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3337 ((IP_ADDR_INDEX_REG_MASK << 16) |
3338 (qdev->mac_index << 2)));
3339 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3340
3341 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3342 ((IP_ADDR_INDEX_REG_MASK << 16) |
3343 ((qdev->mac_index << 2) + 1)));
3344 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3345
3346 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3347
3348
3349 ql_write_page0_reg(qdev,
3350 &port_regs->portControl,
3351 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3352
3353 do {
3354 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3355 if (value & PORT_STATUS_IC)
3356 break;
3357 msleep(500);
3358 } while (--delay);
3359
3360 if (delay == 0) {
3361 printk(KERN_ERR PFX
3362 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3363 status = -1;
3364 goto out;
3365 }
3366
3367
3368 if (qdev->device_id == QL3032_DEVICE_ID) {
3369 value =
3370 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3371 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3372 QL3032_PORT_CONTROL_ET);
3373 ql_write_page0_reg(qdev, &port_regs->functionControl,
3374 ((value << 16) | value));
3375 } else {
3376 value =
3377 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3378 PORT_CONTROL_HH);
3379 ql_write_page0_reg(qdev, &port_regs->portControl,
3380 ((value << 16) | value));
3381 }
3382
3383
3384out:
3385 return status;
3386}
3387
3388
3389
3390
3391static int ql_adapter_reset(struct ql3_adapter *qdev)
3392{
3393 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3394 int status = 0;
3395 u16 value;
3396 int max_wait_time;
3397
3398 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3399 clear_bit(QL_RESET_DONE, &qdev->flags);
3400
3401
3402
3403
3404 printk(KERN_DEBUG PFX
3405 "%s: Issue soft reset to chip.\n",
3406 qdev->ndev->name);
3407 ql_write_common_reg(qdev,
3408 &port_regs->CommonRegs.ispControlStatus,
3409 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3410
3411
3412 printk(KERN_DEBUG PFX
3413 "%s: Wait 10 milliseconds for reset to complete.\n",
3414 qdev->ndev->name);
3415
3416
3417 max_wait_time = 5;
3418 do {
3419 value =
3420 ql_read_common_reg(qdev,
3421 &port_regs->CommonRegs.ispControlStatus);
3422 if ((value & ISP_CONTROL_SR) == 0)
3423 break;
3424
3425 ssleep(1);
3426 } while ((--max_wait_time));
3427
3428
3429
3430
3431
3432 value =
3433 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3434 if (value & ISP_CONTROL_RI) {
3435 printk(KERN_DEBUG PFX
3436 "ql_adapter_reset: clearing RI after reset.\n");
3437 ql_write_common_reg(qdev,
3438 &port_regs->CommonRegs.
3439 ispControlStatus,
3440 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3441 }
3442
3443 if (max_wait_time == 0) {
3444
3445 ql_write_common_reg(qdev,
3446 &port_regs->CommonRegs.
3447 ispControlStatus,
3448 ((ISP_CONTROL_FSR << 16) |
3449 ISP_CONTROL_FSR));
3450
3451
3452
3453
3454 max_wait_time = 5;
3455 do {
3456 value =
3457 ql_read_common_reg(qdev,
3458 &port_regs->CommonRegs.
3459 ispControlStatus);
3460 if ((value & ISP_CONTROL_FSR) == 0) {
3461 break;
3462 }
3463 ssleep(1);
3464 } while ((--max_wait_time));
3465 }
3466 if (max_wait_time == 0)
3467 status = 1;
3468
3469 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3470 set_bit(QL_RESET_DONE, &qdev->flags);
3471 return status;
3472}
3473
3474static void ql_set_mac_info(struct ql3_adapter *qdev)
3475{
3476 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3477 u32 value, port_status;
3478 u8 func_number;
3479
3480
3481 value =
3482 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3483 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3484 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3485 switch (value & ISP_CONTROL_FN_MASK) {
3486 case ISP_CONTROL_FN0_NET:
3487 qdev->mac_index = 0;
3488 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3489 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3490 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3491 if (port_status & PORT_STATUS_SM0)
3492 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3493 else
3494 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3495 break;
3496
3497 case ISP_CONTROL_FN1_NET:
3498 qdev->mac_index = 1;
3499 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3500 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3501 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3502 if (port_status & PORT_STATUS_SM1)
3503 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3504 else
3505 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3506 break;
3507
3508 case ISP_CONTROL_FN0_SCSI:
3509 case ISP_CONTROL_FN1_SCSI:
3510 default:
3511 printk(KERN_DEBUG PFX
3512 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3513 qdev->ndev->name,value);
3514 break;
3515 }
3516 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3517}
3518
3519static void ql_display_dev_info(struct net_device *ndev)
3520{
3521 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3522 struct pci_dev *pdev = qdev->pdev;
3523 DECLARE_MAC_BUF(mac);
3524
3525 printk(KERN_INFO PFX
3526 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3527 DRV_NAME, qdev->index, qdev->chip_rev_id,
3528 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3529 qdev->pci_slot);
3530 printk(KERN_INFO PFX
3531 "%s Interface.\n",
3532 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3533
3534
3535
3536
3537 printk(KERN_INFO PFX
3538 "Bus interface is %s %s.\n",
3539 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3540 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3541
3542 printk(KERN_INFO PFX
3543 "mem IO base address adjusted = 0x%p\n",
3544 qdev->mem_map_registers);
3545 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3546
3547 if (netif_msg_probe(qdev))
3548 printk(KERN_INFO PFX
3549 "%s: MAC address %s\n",
3550 ndev->name, print_mac(mac, ndev->dev_addr));
3551}
3552
3553static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3554{
3555 struct net_device *ndev = qdev->ndev;
3556 int retval = 0;
3557
3558 netif_stop_queue(ndev);
3559 netif_carrier_off(ndev);
3560
3561 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3562 clear_bit(QL_LINK_MASTER,&qdev->flags);
3563
3564 ql_disable_interrupts(qdev);
3565
3566 free_irq(qdev->pdev->irq, ndev);
3567
3568 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3569 printk(KERN_INFO PFX
3570 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3571 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3572 pci_disable_msi(qdev->pdev);
3573 }
3574
3575 del_timer_sync(&qdev->adapter_timer);
3576
3577 napi_disable(&qdev->napi);
3578
3579 if (do_reset) {
3580 int soft_reset;
3581 unsigned long hw_flags;
3582
3583 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3584 if (ql_wait_for_drvr_lock(qdev)) {
3585 if ((soft_reset = ql_adapter_reset(qdev))) {
3586 printk(KERN_ERR PFX
3587 "%s: ql_adapter_reset(%d) FAILED!\n",
3588 ndev->name, qdev->index);
3589 }
3590 printk(KERN_ERR PFX
3591 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3592 } else {
3593 printk(KERN_ERR PFX
3594 "%s: Could not acquire driver lock to do "
3595 "reset!\n", ndev->name);
3596 retval = -1;
3597 }
3598 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3599 }
3600 ql_free_mem_resources(qdev);
3601 return retval;
3602}
3603
3604static int ql_adapter_up(struct ql3_adapter *qdev)
3605{
3606 struct net_device *ndev = qdev->ndev;
3607 int err;
3608 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3609 unsigned long hw_flags;
3610
3611 if (ql_alloc_mem_resources(qdev)) {
3612 printk(KERN_ERR PFX
3613 "%s Unable to allocate buffers.\n", ndev->name);
3614 return -ENOMEM;
3615 }
3616
3617 if (qdev->msi) {
3618 if (pci_enable_msi(qdev->pdev)) {
3619 printk(KERN_ERR PFX
3620 "%s: User requested MSI, but MSI failed to "
3621 "initialize. Continuing without MSI.\n",
3622 qdev->ndev->name);
3623 qdev->msi = 0;
3624 } else {
3625 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3626 set_bit(QL_MSI_ENABLED,&qdev->flags);
3627 irq_flags &= ~IRQF_SHARED;
3628 }
3629 }
3630
3631 if ((err = request_irq(qdev->pdev->irq,
3632 ql3xxx_isr,
3633 irq_flags, ndev->name, ndev))) {
3634 printk(KERN_ERR PFX
3635 "%s: Failed to reserve interrupt %d already in use.\n",
3636 ndev->name, qdev->pdev->irq);
3637 goto err_irq;
3638 }
3639
3640 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3641
3642 if ((err = ql_wait_for_drvr_lock(qdev))) {
3643 if ((err = ql_adapter_initialize(qdev))) {
3644 printk(KERN_ERR PFX
3645 "%s: Unable to initialize adapter.\n",
3646 ndev->name);
3647 goto err_init;
3648 }
3649 printk(KERN_ERR PFX
3650 "%s: Releaseing driver lock.\n",ndev->name);
3651 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3652 } else {
3653 printk(KERN_ERR PFX
3654 "%s: Could not aquire driver lock.\n",
3655 ndev->name);
3656 goto err_lock;
3657 }
3658
3659 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3660
3661 set_bit(QL_ADAPTER_UP,&qdev->flags);
3662
3663 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3664
3665 napi_enable(&qdev->napi);
3666 ql_enable_interrupts(qdev);
3667 return 0;
3668
3669err_init:
3670 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3671err_lock:
3672 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3673 free_irq(qdev->pdev->irq, ndev);
3674err_irq:
3675 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3676 printk(KERN_INFO PFX
3677 "%s: calling pci_disable_msi().\n",
3678 qdev->ndev->name);
3679 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3680 pci_disable_msi(qdev->pdev);
3681 }
3682 return err;
3683}
3684
3685static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3686{
3687 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3688 printk(KERN_ERR PFX
3689 "%s: Driver up/down cycle failed, "
3690 "closing device\n",qdev->ndev->name);
3691 rtnl_lock();
3692 dev_close(qdev->ndev);
3693 rtnl_unlock();
3694 return -1;
3695 }
3696 return 0;
3697}
3698
3699static int ql3xxx_close(struct net_device *ndev)
3700{
3701 struct ql3_adapter *qdev = netdev_priv(ndev);
3702
3703
3704
3705
3706
3707 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3708 msleep(50);
3709
3710 ql_adapter_down(qdev,QL_DO_RESET);
3711 return 0;
3712}
3713
3714static int ql3xxx_open(struct net_device *ndev)
3715{
3716 struct ql3_adapter *qdev = netdev_priv(ndev);
3717 return (ql_adapter_up(qdev));
3718}
3719
3720static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3721{
3722 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3723 struct ql3xxx_port_registers __iomem *port_regs =
3724 qdev->mem_map_registers;
3725 struct sockaddr *addr = p;
3726 unsigned long hw_flags;
3727
3728 if (netif_running(ndev))
3729 return -EBUSY;
3730
3731 if (!is_valid_ether_addr(addr->sa_data))
3732 return -EADDRNOTAVAIL;
3733
3734 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3735
3736 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3737
3738 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3739 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3740 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3741 ((ndev->dev_addr[2] << 24) | (ndev->
3742 dev_addr[3] << 16) |
3743 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3744
3745
3746 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3747 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3748 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3749 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3750 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3751
3752 return 0;
3753}
3754
3755static void ql3xxx_tx_timeout(struct net_device *ndev)
3756{
3757 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3758
3759 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3760
3761
3762
3763 netif_stop_queue(ndev);
3764
3765
3766
3767
3768 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3769}
3770
3771static void ql_reset_work(struct work_struct *work)
3772{
3773 struct ql3_adapter *qdev =
3774 container_of(work, struct ql3_adapter, reset_work.work);
3775 struct net_device *ndev = qdev->ndev;
3776 u32 value;
3777 struct ql_tx_buf_cb *tx_cb;
3778 int max_wait_time, i;
3779 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3780 unsigned long hw_flags;
3781
3782 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3783 clear_bit(QL_LINK_MASTER,&qdev->flags);
3784
3785
3786
3787
3788 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3789 int j;
3790 tx_cb = &qdev->tx_buf[i];
3791 if (tx_cb->skb) {
3792 printk(KERN_DEBUG PFX
3793 "%s: Freeing lost SKB.\n",
3794 qdev->ndev->name);
3795 pci_unmap_single(qdev->pdev,
3796 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3797 pci_unmap_len(&tx_cb->map[0], maplen),
3798 PCI_DMA_TODEVICE);
3799 for(j=1;j<tx_cb->seg_count;j++) {
3800 pci_unmap_page(qdev->pdev,
3801 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3802 pci_unmap_len(&tx_cb->map[j],maplen),
3803 PCI_DMA_TODEVICE);
3804 }
3805 dev_kfree_skb(tx_cb->skb);
3806 tx_cb->skb = NULL;
3807 }
3808 }
3809
3810 printk(KERN_ERR PFX
3811 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3812 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3813 ql_write_common_reg(qdev,
3814 &port_regs->CommonRegs.
3815 ispControlStatus,
3816 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3817
3818
3819
3820 max_wait_time = 10;
3821 do {
3822 value = ql_read_common_reg(qdev,
3823 &port_regs->CommonRegs.
3824
3825 ispControlStatus);
3826 if ((value & ISP_CONTROL_SR) == 0) {
3827 printk(KERN_DEBUG PFX
3828 "%s: reset completed.\n",
3829 qdev->ndev->name);
3830 break;
3831 }
3832
3833 if (value & ISP_CONTROL_RI) {
3834 printk(KERN_DEBUG PFX
3835 "%s: clearing NRI after reset.\n",
3836 qdev->ndev->name);
3837 ql_write_common_reg(qdev,
3838 &port_regs->
3839 CommonRegs.
3840 ispControlStatus,
3841 ((ISP_CONTROL_RI <<
3842 16) | ISP_CONTROL_RI));
3843 }
3844
3845 ssleep(1);
3846 } while (--max_wait_time);
3847 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3848
3849 if (value & ISP_CONTROL_SR) {
3850
3851
3852
3853
3854
3855 printk(KERN_ERR PFX
3856 "%s: Timed out waiting for reset to "
3857 "complete.\n", ndev->name);
3858 printk(KERN_ERR PFX
3859 "%s: Do a reset.\n", ndev->name);
3860 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3861 clear_bit(QL_RESET_START,&qdev->flags);
3862 ql_cycle_adapter(qdev,QL_DO_RESET);
3863 return;
3864 }
3865
3866 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3867 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3868 clear_bit(QL_RESET_START,&qdev->flags);
3869 ql_cycle_adapter(qdev,QL_NO_RESET);
3870 }
3871}
3872
3873static void ql_tx_timeout_work(struct work_struct *work)
3874{
3875 struct ql3_adapter *qdev =
3876 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3877
3878 ql_cycle_adapter(qdev, QL_DO_RESET);
3879}
3880
3881static void ql_get_board_info(struct ql3_adapter *qdev)
3882{
3883 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3884 u32 value;
3885
3886 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3887
3888 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3889 if (value & PORT_STATUS_64)
3890 qdev->pci_width = 64;
3891 else
3892 qdev->pci_width = 32;
3893 if (value & PORT_STATUS_X)
3894 qdev->pci_x = 1;
3895 else
3896 qdev->pci_x = 0;
3897 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3898}
3899
3900static void ql3xxx_timer(unsigned long ptr)
3901{
3902 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3903 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3904}
3905
3906static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3907 const struct pci_device_id *pci_entry)
3908{
3909 struct net_device *ndev = NULL;
3910 struct ql3_adapter *qdev = NULL;
3911 static int cards_found = 0;
3912 int pci_using_dac, err;
3913
3914 err = pci_enable_device(pdev);
3915 if (err) {
3916 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3917 pci_name(pdev));
3918 goto err_out;
3919 }
3920
3921 err = pci_request_regions(pdev, DRV_NAME);
3922 if (err) {
3923 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3924 pci_name(pdev));
3925 goto err_out_disable_pdev;
3926 }
3927
3928 pci_set_master(pdev);
3929
3930 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3931 pci_using_dac = 1;
3932 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3933 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3934 pci_using_dac = 0;
3935 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3936 }
3937
3938 if (err) {
3939 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3940 pci_name(pdev));
3941 goto err_out_free_regions;
3942 }
3943
3944 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3945 if (!ndev) {
3946 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3947 pci_name(pdev));
3948 err = -ENOMEM;
3949 goto err_out_free_regions;
3950 }
3951
3952 SET_NETDEV_DEV(ndev, &pdev->dev);
3953
3954 pci_set_drvdata(pdev, ndev);
3955
3956 qdev = netdev_priv(ndev);
3957 qdev->index = cards_found;
3958 qdev->ndev = ndev;
3959 qdev->pdev = pdev;
3960 qdev->device_id = pci_entry->device;
3961 qdev->port_link_state = LS_DOWN;
3962 if (msi)
3963 qdev->msi = 1;
3964
3965 qdev->msg_enable = netif_msg_init(debug, default_msg);
3966
3967 if (pci_using_dac)
3968 ndev->features |= NETIF_F_HIGHDMA;
3969 if (qdev->device_id == QL3032_DEVICE_ID)
3970 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3971
3972 qdev->mem_map_registers =
3973 ioremap_nocache(pci_resource_start(pdev, 1),
3974 pci_resource_len(qdev->pdev, 1));
3975 if (!qdev->mem_map_registers) {
3976 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3977 pci_name(pdev));
3978 err = -EIO;
3979 goto err_out_free_ndev;
3980 }
3981
3982 spin_lock_init(&qdev->adapter_lock);
3983 spin_lock_init(&qdev->hw_lock);
3984
3985
3986 ndev->open = ql3xxx_open;
3987 ndev->hard_start_xmit = ql3xxx_send;
3988 ndev->stop = ql3xxx_close;
3989
3990
3991
3992
3993
3994 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3995 ndev->set_mac_address = ql3xxx_set_mac_address;
3996 ndev->tx_timeout = ql3xxx_tx_timeout;
3997 ndev->watchdog_timeo = 5 * HZ;
3998
3999 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
4000
4001 ndev->irq = pdev->irq;
4002
4003
4004 if (ql_get_nvram_params(qdev)) {
4005 printk(KERN_ALERT PFX
4006 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4007 qdev->index);
4008 err = -EIO;
4009 goto err_out_iounmap;
4010 }
4011
4012 ql_set_mac_info(qdev);
4013
4014
4015 if (qdev->mac_index) {
4016 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
4017 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
4018 } else {
4019 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
4020 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
4021 }
4022 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4023
4024 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4025
4026
4027 ql_get_board_info(qdev);
4028
4029
4030
4031
4032
4033 if (qdev->pci_x) {
4034 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4035 }
4036
4037 err = register_netdev(ndev);
4038 if (err) {
4039 printk(KERN_ERR PFX "%s: cannot register net device\n",
4040 pci_name(pdev));
4041 goto err_out_iounmap;
4042 }
4043
4044
4045
4046 netif_carrier_off(ndev);
4047 netif_stop_queue(ndev);
4048
4049 qdev->workqueue = create_singlethread_workqueue(ndev->name);
4050 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4051 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
4052 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
4053
4054 init_timer(&qdev->adapter_timer);
4055 qdev->adapter_timer.function = ql3xxx_timer;
4056 qdev->adapter_timer.expires = jiffies + HZ * 2;
4057 qdev->adapter_timer.data = (unsigned long)qdev;
4058
4059 if(!cards_found) {
4060 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4061 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4062 DRV_NAME, DRV_VERSION);
4063 }
4064 ql_display_dev_info(ndev);
4065
4066 cards_found++;
4067 return 0;
4068
4069err_out_iounmap:
4070 iounmap(qdev->mem_map_registers);
4071err_out_free_ndev:
4072 free_netdev(ndev);
4073err_out_free_regions:
4074 pci_release_regions(pdev);
4075err_out_disable_pdev:
4076 pci_disable_device(pdev);
4077 pci_set_drvdata(pdev, NULL);
4078err_out:
4079 return err;
4080}
4081
4082static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4083{
4084 struct net_device *ndev = pci_get_drvdata(pdev);
4085 struct ql3_adapter *qdev = netdev_priv(ndev);
4086
4087 unregister_netdev(ndev);
4088 qdev = netdev_priv(ndev);
4089
4090 ql_disable_interrupts(qdev);
4091
4092 if (qdev->workqueue) {
4093 cancel_delayed_work(&qdev->reset_work);
4094 cancel_delayed_work(&qdev->tx_timeout_work);
4095 destroy_workqueue(qdev->workqueue);
4096 qdev->workqueue = NULL;
4097 }
4098
4099 iounmap(qdev->mem_map_registers);
4100 pci_release_regions(pdev);
4101 pci_set_drvdata(pdev, NULL);
4102 free_netdev(ndev);
4103}
4104
4105static struct pci_driver ql3xxx_driver = {
4106
4107 .name = DRV_NAME,
4108 .id_table = ql3xxx_pci_tbl,
4109 .probe = ql3xxx_probe,
4110 .remove = __devexit_p(ql3xxx_remove),
4111};
4112
4113static int __init ql3xxx_init_module(void)
4114{
4115 return pci_register_driver(&ql3xxx_driver);
4116}
4117
4118static void __exit ql3xxx_exit(void)
4119{
4120 pci_unregister_driver(&ql3xxx_driver);
4121}
4122
4123module_init(ql3xxx_init_module);
4124module_exit(ql3xxx_exit);