Showing error 1790

User: Jiri Slaby
Error type: Invalid Pointer Dereference
Error type description: A pointer which is invalid is being dereferenced
File location: drivers/char/synclink.c
Line in file: 1366
Project: Linux Kernel
Project version: 2.6.28
Tools: Smatch (1.59)
Entered: 2013-09-11 08:47:26 UTC


Source:

   1/*
   2 * linux/drivers/char/synclink.c
   3 *
   4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
   5 *
   6 * Device driver for Microgate SyncLink ISA and PCI
   7 * high speed multiprotocol serial adapters.
   8 *
   9 * written by Paul Fulghum for Microgate Corporation
  10 * paulkf@microgate.com
  11 *
  12 * Microgate and SyncLink are trademarks of Microgate Corporation
  13 *
  14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  15 *
  16 * Original release 01/11/99
  17 *
  18 * This code is released under the GNU General Public License (GPL)
  19 *
  20 * This driver is primarily intended for use in synchronous
  21 * HDLC mode. Asynchronous mode is also provided.
  22 *
  23 * When operating in synchronous mode, each call to mgsl_write()
  24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
  25 * will start assembling an HDLC frame that will not be sent until
  26 * mgsl_flush_chars or mgsl_write is called.
  27 * 
  28 * Synchronous receive data is reported as complete frames. To accomplish
  29 * this, the TTY flip buffer is bypassed (too small to hold largest
  30 * frame and may fragment frames) and the line discipline
  31 * receive entry point is called directly.
  32 *
  33 * This driver has been tested with a slightly modified ppp.c driver
  34 * for synchronous PPP.
  35 *
  36 * 2000/02/16
  37 * Added interface for syncppp.c driver (an alternate synchronous PPP
  38 * implementation that also supports Cisco HDLC). Each device instance
  39 * registers as a tty device AND a network device (if dosyncppp option
  40 * is set for the device). The functionality is determined by which
  41 * device interface is opened.
  42 *
  43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  46 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  53 * OF THE POSSIBILITY OF SUCH DAMAGE.
  54 */
  55
  56#if defined(__i386__)
  57#  define BREAKPOINT() asm("   int $3");
  58#else
  59#  define BREAKPOINT() { }
  60#endif
  61
  62#define MAX_ISA_DEVICES 10
  63#define MAX_PCI_DEVICES 10
  64#define MAX_TOTAL_DEVICES 20
  65
  66#include <linux/module.h>
  67#include <linux/errno.h>
  68#include <linux/signal.h>
  69#include <linux/sched.h>
  70#include <linux/timer.h>
  71#include <linux/interrupt.h>
  72#include <linux/pci.h>
  73#include <linux/tty.h>
  74#include <linux/tty_flip.h>
  75#include <linux/serial.h>
  76#include <linux/major.h>
  77#include <linux/string.h>
  78#include <linux/fcntl.h>
  79#include <linux/ptrace.h>
  80#include <linux/ioport.h>
  81#include <linux/mm.h>
  82#include <linux/slab.h>
  83#include <linux/delay.h>
  84#include <linux/netdevice.h>
  85#include <linux/vmalloc.h>
  86#include <linux/init.h>
  87#include <linux/ioctl.h>
  88#include <linux/synclink.h>
  89
  90#include <asm/system.h>
  91#include <asm/io.h>
  92#include <asm/irq.h>
  93#include <asm/dma.h>
  94#include <linux/bitops.h>
  95#include <asm/types.h>
  96#include <linux/termios.h>
  97#include <linux/workqueue.h>
  98#include <linux/hdlc.h>
  99#include <linux/dma-mapping.h>
 100
 101#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
 102#define SYNCLINK_GENERIC_HDLC 1
 103#else
 104#define SYNCLINK_GENERIC_HDLC 0
 105#endif
 106
 107#define GET_USER(error,value,addr) error = get_user(value,addr)
 108#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
 109#define PUT_USER(error,value,addr) error = put_user(value,addr)
 110#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
 111
 112#include <asm/uaccess.h>
 113
 114#define RCLRVALUE 0xffff
 115
 116static MGSL_PARAMS default_params = {
 117        MGSL_MODE_HDLC,                        /* unsigned long mode */
 118        0,                                /* unsigned char loopback; */
 119        HDLC_FLAG_UNDERRUN_ABORT15,        /* unsigned short flags; */
 120        HDLC_ENCODING_NRZI_SPACE,        /* unsigned char encoding; */
 121        0,                                /* unsigned long clock_speed; */
 122        0xff,                                /* unsigned char addr_filter; */
 123        HDLC_CRC_16_CCITT,                /* unsigned short crc_type; */
 124        HDLC_PREAMBLE_LENGTH_8BITS,        /* unsigned char preamble_length; */
 125        HDLC_PREAMBLE_PATTERN_NONE,        /* unsigned char preamble; */
 126        9600,                                /* unsigned long data_rate; */
 127        8,                                /* unsigned char data_bits; */
 128        1,                                /* unsigned char stop_bits; */
 129        ASYNC_PARITY_NONE                /* unsigned char parity; */
 130};
 131
 132#define SHARED_MEM_ADDRESS_SIZE 0x40000
 133#define BUFFERLISTSIZE 4096
 134#define DMABUFFERSIZE 4096
 135#define MAXRXFRAMES 7
 136
 137typedef struct _DMABUFFERENTRY
 138{
 139        u32 phys_addr;        /* 32-bit flat physical address of data buffer */
 140        volatile u16 count;        /* buffer size/data count */
 141        volatile u16 status;        /* Control/status field */
 142        volatile u16 rcc;        /* character count field */
 143        u16 reserved;        /* padding required by 16C32 */
 144        u32 link;        /* 32-bit flat link to next buffer entry */
 145        char *virt_addr;        /* virtual address of data buffer */
 146        u32 phys_entry;        /* physical address of this buffer entry */
 147        dma_addr_t dma_addr;
 148} DMABUFFERENTRY, *DMAPBUFFERENTRY;
 149
 150/* The queue of BH actions to be performed */
 151
 152#define BH_RECEIVE  1
 153#define BH_TRANSMIT 2
 154#define BH_STATUS   4
 155
 156#define IO_PIN_SHUTDOWN_LIMIT 100
 157
 158struct        _input_signal_events {
 159        int        ri_up;        
 160        int        ri_down;
 161        int        dsr_up;
 162        int        dsr_down;
 163        int        dcd_up;
 164        int        dcd_down;
 165        int        cts_up;
 166        int        cts_down;
 167};
 168
 169/* transmit holding buffer definitions*/
 170#define MAX_TX_HOLDING_BUFFERS 5
 171struct tx_holding_buffer {
 172        int        buffer_size;
 173        unsigned char *        buffer;
 174};
 175
 176
 177/*
 178 * Device instance data structure
 179 */
 180 
 181struct mgsl_struct {
 182        int                        magic;
 183        struct tty_port                port;
 184        int                        line;
 185        int                     hw_version;
 186        
 187        struct mgsl_icount        icount;
 188        
 189        int                        timeout;
 190        int                        x_char;                /* xon/xoff character */
 191        u16                        read_status_mask;
 192        u16                        ignore_status_mask;        
 193        unsigned char                 *xmit_buf;
 194        int                        xmit_head;
 195        int                        xmit_tail;
 196        int                        xmit_cnt;
 197        
 198        wait_queue_head_t        status_event_wait_q;
 199        wait_queue_head_t        event_wait_q;
 200        struct timer_list        tx_timer;        /* HDLC transmit timeout timer */
 201        struct mgsl_struct        *next_device;        /* device list link */
 202        
 203        spinlock_t irq_spinlock;                /* spinlock for synchronizing with ISR */
 204        struct work_struct task;                /* task structure for scheduling bh */
 205
 206        u32 EventMask;                        /* event trigger mask */
 207        u32 RecordedEvents;                /* pending events */
 208
 209        u32 max_frame_size;                /* as set by device config */
 210
 211        u32 pending_bh;
 212
 213        bool bh_running;                /* Protection from multiple */
 214        int isr_overflow;
 215        bool bh_requested;
 216        
 217        int dcd_chkcount;                /* check counts to prevent */
 218        int cts_chkcount;                /* too many IRQs if a signal */
 219        int dsr_chkcount;                /* is floating */
 220        int ri_chkcount;
 221
 222        char *buffer_list;                /* virtual address of Rx & Tx buffer lists */
 223        u32 buffer_list_phys;
 224        dma_addr_t buffer_list_dma_addr;
 225
 226        unsigned int rx_buffer_count;        /* count of total allocated Rx buffers */
 227        DMABUFFERENTRY *rx_buffer_list;        /* list of receive buffer entries */
 228        unsigned int current_rx_buffer;
 229
 230        int num_tx_dma_buffers;                /* number of tx dma frames required */
 231         int tx_dma_buffers_used;
 232        unsigned int tx_buffer_count;        /* count of total allocated Tx buffers */
 233        DMABUFFERENTRY *tx_buffer_list;        /* list of transmit buffer entries */
 234        int start_tx_dma_buffer;        /* tx dma buffer to start tx dma operation */
 235        int current_tx_buffer;          /* next tx dma buffer to be loaded */
 236        
 237        unsigned char *intermediate_rxbuffer;
 238
 239        int num_tx_holding_buffers;        /* number of tx holding buffer allocated */
 240        int get_tx_holding_index;          /* next tx holding buffer for adapter to load */
 241        int put_tx_holding_index;          /* next tx holding buffer to store user request */
 242        int tx_holding_count;                /* number of tx holding buffers waiting */
 243        struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
 244
 245        bool rx_enabled;
 246        bool rx_overflow;
 247        bool rx_rcc_underrun;
 248
 249        bool tx_enabled;
 250        bool tx_active;
 251        u32 idle_mode;
 252
 253        u16 cmr_value;
 254        u16 tcsr_value;
 255
 256        char device_name[25];                /* device instance name */
 257
 258        unsigned int bus_type;        /* expansion bus type (ISA,EISA,PCI) */
 259        unsigned char bus;                /* expansion bus number (zero based) */
 260        unsigned char function;                /* PCI device number */
 261
 262        unsigned int io_base;                /* base I/O address of adapter */
 263        unsigned int io_addr_size;        /* size of the I/O address range */
 264        bool io_addr_requested;                /* true if I/O address requested */
 265        
 266        unsigned int irq_level;                /* interrupt level */
 267        unsigned long irq_flags;
 268        bool irq_requested;                /* true if IRQ requested */
 269        
 270        unsigned int dma_level;                /* DMA channel */
 271        bool dma_requested;                /* true if dma channel requested */
 272
 273        u16 mbre_bit;
 274        u16 loopback_bits;
 275        u16 usc_idle_mode;
 276
 277        MGSL_PARAMS params;                /* communications parameters */
 278
 279        unsigned char serial_signals;        /* current serial signal states */
 280
 281        bool irq_occurred;                /* for diagnostics use */
 282        unsigned int init_error;        /* Initialization startup error                 (DIAGS)        */
 283        int        fDiagnosticsmode;        /* Driver in Diagnostic mode?                        (DIAGS)        */
 284
 285        u32 last_mem_alloc;
 286        unsigned char* memory_base;        /* shared memory address (PCI only) */
 287        u32 phys_memory_base;
 288        bool shared_mem_requested;
 289
 290        unsigned char* lcr_base;        /* local config registers (PCI only) */
 291        u32 phys_lcr_base;
 292        u32 lcr_offset;
 293        bool lcr_mem_requested;
 294
 295        u32 misc_ctrl_value;
 296        char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 297        char char_buf[MAX_ASYNC_BUFFER_SIZE];        
 298        bool drop_rts_on_tx_done;
 299
 300        bool loopmode_insert_requested;
 301        bool loopmode_send_done_requested;
 302        
 303        struct        _input_signal_events        input_signal_events;
 304
 305        /* generic HDLC device parts */
 306        int netcount;
 307        spinlock_t netlock;
 308
 309#if SYNCLINK_GENERIC_HDLC
 310        struct net_device *netdev;
 311#endif
 312};
 313
 314#define MGSL_MAGIC 0x5401
 315
 316/*
 317 * The size of the serial xmit buffer is 1 page, or 4096 bytes
 318 */
 319#ifndef SERIAL_XMIT_SIZE
 320#define SERIAL_XMIT_SIZE 4096
 321#endif
 322
 323/*
 324 * These macros define the offsets used in calculating the
 325 * I/O address of the specified USC registers.
 326 */
 327
 328
 329#define DCPIN 2                /* Bit 1 of I/O address */
 330#define SDPIN 4                /* Bit 2 of I/O address */
 331
 332#define DCAR 0                /* DMA command/address register */
 333#define CCAR SDPIN                /* channel command/address register */
 334#define DATAREG DCPIN + SDPIN        /* serial data register */
 335#define MSBONLY 0x41
 336#define LSBONLY 0x40
 337
 338/*
 339 * These macros define the register address (ordinal number)
 340 * used for writing address/value pairs to the USC.
 341 */
 342
 343#define CMR        0x02        /* Channel mode Register */
 344#define CCSR        0x04        /* Channel Command/status Register */
 345#define CCR        0x06        /* Channel Control Register */
 346#define PSR        0x08        /* Port status Register */
 347#define PCR        0x0a        /* Port Control Register */
 348#define TMDR        0x0c        /* Test mode Data Register */
 349#define TMCR        0x0e        /* Test mode Control Register */
 350#define CMCR        0x10        /* Clock mode Control Register */
 351#define HCR        0x12        /* Hardware Configuration Register */
 352#define IVR        0x14        /* Interrupt Vector Register */
 353#define IOCR        0x16        /* Input/Output Control Register */
 354#define ICR        0x18        /* Interrupt Control Register */
 355#define DCCR        0x1a        /* Daisy Chain Control Register */
 356#define MISR        0x1c        /* Misc Interrupt status Register */
 357#define SICR        0x1e        /* status Interrupt Control Register */
 358#define RDR        0x20        /* Receive Data Register */
 359#define RMR        0x22        /* Receive mode Register */
 360#define RCSR        0x24        /* Receive Command/status Register */
 361#define RICR        0x26        /* Receive Interrupt Control Register */
 362#define RSR        0x28        /* Receive Sync Register */
 363#define RCLR        0x2a        /* Receive count Limit Register */
 364#define RCCR        0x2c        /* Receive Character count Register */
 365#define TC0R        0x2e        /* Time Constant 0 Register */
 366#define TDR        0x30        /* Transmit Data Register */
 367#define TMR        0x32        /* Transmit mode Register */
 368#define TCSR        0x34        /* Transmit Command/status Register */
 369#define TICR        0x36        /* Transmit Interrupt Control Register */
 370#define TSR        0x38        /* Transmit Sync Register */
 371#define TCLR        0x3a        /* Transmit count Limit Register */
 372#define TCCR        0x3c        /* Transmit Character count Register */
 373#define TC1R        0x3e        /* Time Constant 1 Register */
 374
 375
 376/*
 377 * MACRO DEFINITIONS FOR DMA REGISTERS
 378 */
 379
 380#define DCR        0x06        /* DMA Control Register (shared) */
 381#define DACR        0x08        /* DMA Array count Register (shared) */
 382#define BDCR        0x12        /* Burst/Dwell Control Register (shared) */
 383#define DIVR        0x14        /* DMA Interrupt Vector Register (shared) */        
 384#define DICR        0x18        /* DMA Interrupt Control Register (shared) */
 385#define CDIR        0x1a        /* Clear DMA Interrupt Register (shared) */
 386#define SDIR        0x1c        /* Set DMA Interrupt Register (shared) */
 387
 388#define TDMR        0x02        /* Transmit DMA mode Register */
 389#define TDIAR        0x1e        /* Transmit DMA Interrupt Arm Register */
 390#define TBCR        0x2a        /* Transmit Byte count Register */
 391#define TARL        0x2c        /* Transmit Address Register (low) */
 392#define TARU        0x2e        /* Transmit Address Register (high) */
 393#define NTBCR        0x3a        /* Next Transmit Byte count Register */
 394#define NTARL        0x3c        /* Next Transmit Address Register (low) */
 395#define NTARU        0x3e        /* Next Transmit Address Register (high) */
 396
 397#define RDMR        0x82        /* Receive DMA mode Register (non-shared) */
 398#define RDIAR        0x9e        /* Receive DMA Interrupt Arm Register */
 399#define RBCR        0xaa        /* Receive Byte count Register */
 400#define RARL        0xac        /* Receive Address Register (low) */
 401#define RARU        0xae        /* Receive Address Register (high) */
 402#define NRBCR        0xba        /* Next Receive Byte count Register */
 403#define NRARL        0xbc        /* Next Receive Address Register (low) */
 404#define NRARU        0xbe        /* Next Receive Address Register (high) */
 405
 406
 407/*
 408 * MACRO DEFINITIONS FOR MODEM STATUS BITS
 409 */
 410
 411#define MODEMSTATUS_DTR 0x80
 412#define MODEMSTATUS_DSR 0x40
 413#define MODEMSTATUS_RTS 0x20
 414#define MODEMSTATUS_CTS 0x10
 415#define MODEMSTATUS_RI  0x04
 416#define MODEMSTATUS_DCD 0x01
 417
 418
 419/*
 420 * Channel Command/Address Register (CCAR) Command Codes
 421 */
 422
 423#define RTCmd_Null                        0x0000
 424#define RTCmd_ResetHighestIus                0x1000
 425#define RTCmd_TriggerChannelLoadDma        0x2000
 426#define RTCmd_TriggerRxDma                0x2800
 427#define RTCmd_TriggerTxDma                0x3000
 428#define RTCmd_TriggerRxAndTxDma                0x3800
 429#define RTCmd_PurgeRxFifo                0x4800
 430#define RTCmd_PurgeTxFifo                0x5000
 431#define RTCmd_PurgeRxAndTxFifo                0x5800
 432#define RTCmd_LoadRcc                        0x6800
 433#define RTCmd_LoadTcc                        0x7000
 434#define RTCmd_LoadRccAndTcc                0x7800
 435#define RTCmd_LoadTC0                        0x8800
 436#define RTCmd_LoadTC1                        0x9000
 437#define RTCmd_LoadTC0AndTC1                0x9800
 438#define RTCmd_SerialDataLSBFirst        0xa000
 439#define RTCmd_SerialDataMSBFirst        0xa800
 440#define RTCmd_SelectBigEndian                0xb000
 441#define RTCmd_SelectLittleEndian        0xb800
 442
 443
 444/*
 445 * DMA Command/Address Register (DCAR) Command Codes
 446 */
 447
 448#define DmaCmd_Null                        0x0000
 449#define DmaCmd_ResetTxChannel                0x1000
 450#define DmaCmd_ResetRxChannel                0x1200
 451#define DmaCmd_StartTxChannel                0x2000
 452#define DmaCmd_StartRxChannel                0x2200
 453#define DmaCmd_ContinueTxChannel        0x3000
 454#define DmaCmd_ContinueRxChannel        0x3200
 455#define DmaCmd_PauseTxChannel                0x4000
 456#define DmaCmd_PauseRxChannel                0x4200
 457#define DmaCmd_AbortTxChannel                0x5000
 458#define DmaCmd_AbortRxChannel                0x5200
 459#define DmaCmd_InitTxChannel                0x7000
 460#define DmaCmd_InitRxChannel                0x7200
 461#define DmaCmd_ResetHighestDmaIus        0x8000
 462#define DmaCmd_ResetAllChannels                0x9000
 463#define DmaCmd_StartAllChannels                0xa000
 464#define DmaCmd_ContinueAllChannels        0xb000
 465#define DmaCmd_PauseAllChannels                0xc000
 466#define DmaCmd_AbortAllChannels                0xd000
 467#define DmaCmd_InitAllChannels                0xf000
 468
 469#define TCmd_Null                        0x0000
 470#define TCmd_ClearTxCRC                        0x2000
 471#define TCmd_SelectTicrTtsaData                0x4000
 472#define TCmd_SelectTicrTxFifostatus        0x5000
 473#define TCmd_SelectTicrIntLevel                0x6000
 474#define TCmd_SelectTicrdma_level                0x7000
 475#define TCmd_SendFrame                        0x8000
 476#define TCmd_SendAbort                        0x9000
 477#define TCmd_EnableDleInsertion                0xc000
 478#define TCmd_DisableDleInsertion        0xd000
 479#define TCmd_ClearEofEom                0xe000
 480#define TCmd_SetEofEom                        0xf000
 481
 482#define RCmd_Null                        0x0000
 483#define RCmd_ClearRxCRC                        0x2000
 484#define RCmd_EnterHuntmode                0x3000
 485#define RCmd_SelectRicrRtsaData                0x4000
 486#define RCmd_SelectRicrRxFifostatus        0x5000
 487#define RCmd_SelectRicrIntLevel                0x6000
 488#define RCmd_SelectRicrdma_level                0x7000
 489
 490/*
 491 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
 492 */
 493 
 494#define RECEIVE_STATUS                BIT5
 495#define RECEIVE_DATA                BIT4
 496#define TRANSMIT_STATUS                BIT3
 497#define TRANSMIT_DATA                BIT2
 498#define IO_PIN                        BIT1
 499#define MISC                        BIT0
 500
 501
 502/*
 503 * Receive status Bits in Receive Command/status Register RCSR
 504 */
 505
 506#define RXSTATUS_SHORT_FRAME                BIT8
 507#define RXSTATUS_CODE_VIOLATION                BIT8
 508#define RXSTATUS_EXITED_HUNT                BIT7
 509#define RXSTATUS_IDLE_RECEIVED                BIT6
 510#define RXSTATUS_BREAK_RECEIVED                BIT5
 511#define RXSTATUS_ABORT_RECEIVED                BIT5
 512#define RXSTATUS_RXBOUND                BIT4
 513#define RXSTATUS_CRC_ERROR                BIT3
 514#define RXSTATUS_FRAMING_ERROR                BIT3
 515#define RXSTATUS_ABORT                        BIT2
 516#define RXSTATUS_PARITY_ERROR                BIT2
 517#define RXSTATUS_OVERRUN                BIT1
 518#define RXSTATUS_DATA_AVAILABLE                BIT0
 519#define RXSTATUS_ALL                        0x01f6
 520#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
 521
 522/*
 523 * Values for setting transmit idle mode in 
 524 * Transmit Control/status Register (TCSR)
 525 */
 526#define IDLEMODE_FLAGS                        0x0000
 527#define IDLEMODE_ALT_ONE_ZERO                0x0100
 528#define IDLEMODE_ZERO                        0x0200
 529#define IDLEMODE_ONE                        0x0300
 530#define IDLEMODE_ALT_MARK_SPACE                0x0500
 531#define IDLEMODE_SPACE                        0x0600
 532#define IDLEMODE_MARK                        0x0700
 533#define IDLEMODE_MASK                        0x0700
 534
 535/*
 536 * IUSC revision identifiers
 537 */
 538#define        IUSC_SL1660                        0x4d44
 539#define IUSC_PRE_SL1660                        0x4553
 540
 541/*
 542 * Transmit status Bits in Transmit Command/status Register (TCSR)
 543 */
 544
 545#define TCSR_PRESERVE                        0x0F00
 546
 547#define TCSR_UNDERWAIT                        BIT11
 548#define TXSTATUS_PREAMBLE_SENT                BIT7
 549#define TXSTATUS_IDLE_SENT                BIT6
 550#define TXSTATUS_ABORT_SENT                BIT5
 551#define TXSTATUS_EOF_SENT                BIT4
 552#define TXSTATUS_EOM_SENT                BIT4
 553#define TXSTATUS_CRC_SENT                BIT3
 554#define TXSTATUS_ALL_SENT                BIT2
 555#define TXSTATUS_UNDERRUN                BIT1
 556#define TXSTATUS_FIFO_EMPTY                BIT0
 557#define TXSTATUS_ALL                        0x00fa
 558#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
 559                                
 560
 561#define MISCSTATUS_RXC_LATCHED                BIT15
 562#define MISCSTATUS_RXC                        BIT14
 563#define MISCSTATUS_TXC_LATCHED                BIT13
 564#define MISCSTATUS_TXC                        BIT12
 565#define MISCSTATUS_RI_LATCHED                BIT11
 566#define MISCSTATUS_RI                        BIT10
 567#define MISCSTATUS_DSR_LATCHED                BIT9
 568#define MISCSTATUS_DSR                        BIT8
 569#define MISCSTATUS_DCD_LATCHED                BIT7
 570#define MISCSTATUS_DCD                        BIT6
 571#define MISCSTATUS_CTS_LATCHED                BIT5
 572#define MISCSTATUS_CTS                        BIT4
 573#define MISCSTATUS_RCC_UNDERRUN                BIT3
 574#define MISCSTATUS_DPLL_NO_SYNC                BIT2
 575#define MISCSTATUS_BRG1_ZERO                BIT1
 576#define MISCSTATUS_BRG0_ZERO                BIT0
 577
 578#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
 579#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
 580
 581#define SICR_RXC_ACTIVE                        BIT15
 582#define SICR_RXC_INACTIVE                BIT14
 583#define SICR_RXC                        (BIT15+BIT14)
 584#define SICR_TXC_ACTIVE                        BIT13
 585#define SICR_TXC_INACTIVE                BIT12
 586#define SICR_TXC                        (BIT13+BIT12)
 587#define SICR_RI_ACTIVE                        BIT11
 588#define SICR_RI_INACTIVE                BIT10
 589#define SICR_RI                                (BIT11+BIT10)
 590#define SICR_DSR_ACTIVE                        BIT9
 591#define SICR_DSR_INACTIVE                BIT8
 592#define SICR_DSR                        (BIT9+BIT8)
 593#define SICR_DCD_ACTIVE                        BIT7
 594#define SICR_DCD_INACTIVE                BIT6
 595#define SICR_DCD                        (BIT7+BIT6)
 596#define SICR_CTS_ACTIVE                        BIT5
 597#define SICR_CTS_INACTIVE                BIT4
 598#define SICR_CTS                        (BIT5+BIT4)
 599#define SICR_RCC_UNDERFLOW                BIT3
 600#define SICR_DPLL_NO_SYNC                BIT2
 601#define SICR_BRG1_ZERO                        BIT1
 602#define SICR_BRG0_ZERO                        BIT0
 603
 604void usc_DisableMasterIrqBit( struct mgsl_struct *info );
 605void usc_EnableMasterIrqBit( struct mgsl_struct *info );
 606void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 607void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 608void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
 609
 610#define usc_EnableInterrupts( a, b ) \
 611        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
 612
 613#define usc_DisableInterrupts( a, b ) \
 614        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
 615
 616#define usc_EnableMasterIrqBit(a) \
 617        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
 618
 619#define usc_DisableMasterIrqBit(a) \
 620        usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
 621
 622#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
 623
 624/*
 625 * Transmit status Bits in Transmit Control status Register (TCSR)
 626 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
 627 */
 628
 629#define TXSTATUS_PREAMBLE_SENT        BIT7
 630#define TXSTATUS_IDLE_SENT        BIT6
 631#define TXSTATUS_ABORT_SENT        BIT5
 632#define TXSTATUS_EOF                BIT4
 633#define TXSTATUS_CRC_SENT        BIT3
 634#define TXSTATUS_ALL_SENT        BIT2
 635#define TXSTATUS_UNDERRUN        BIT1
 636#define TXSTATUS_FIFO_EMPTY        BIT0
 637
 638#define DICR_MASTER                BIT15
 639#define DICR_TRANSMIT                BIT0
 640#define DICR_RECEIVE                BIT1
 641
 642#define usc_EnableDmaInterrupts(a,b) \
 643        usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
 644
 645#define usc_DisableDmaInterrupts(a,b) \
 646        usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
 647
 648#define usc_EnableStatusIrqs(a,b) \
 649        usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
 650
 651#define usc_DisablestatusIrqs(a,b) \
 652        usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
 653
 654/* Transmit status Bits in Transmit Control status Register (TCSR) */
 655/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
 656
 657
 658#define DISABLE_UNCONDITIONAL    0
 659#define DISABLE_END_OF_FRAME     1
 660#define ENABLE_UNCONDITIONAL     2
 661#define ENABLE_AUTO_CTS          3
 662#define ENABLE_AUTO_DCD          3
 663#define usc_EnableTransmitter(a,b) \
 664        usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
 665#define usc_EnableReceiver(a,b) \
 666        usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
 667
 668static u16  usc_InDmaReg( struct mgsl_struct *info, u16 Port );
 669static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
 670static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
 671
 672static u16  usc_InReg( struct mgsl_struct *info, u16 Port );
 673static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
 674static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
 675void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
 676void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
 677
 678#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
 679#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
 680
 681#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
 682
 683static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
 684static void usc_start_receiver( struct mgsl_struct *info );
 685static void usc_stop_receiver( struct mgsl_struct *info );
 686
 687static void usc_start_transmitter( struct mgsl_struct *info );
 688static void usc_stop_transmitter( struct mgsl_struct *info );
 689static void usc_set_txidle( struct mgsl_struct *info );
 690static void usc_load_txfifo( struct mgsl_struct *info );
 691
 692static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
 693static void usc_enable_loopback( struct mgsl_struct *info, int enable );
 694
 695static void usc_get_serial_signals( struct mgsl_struct *info );
 696static void usc_set_serial_signals( struct mgsl_struct *info );
 697
 698static void usc_reset( struct mgsl_struct *info );
 699
 700static void usc_set_sync_mode( struct mgsl_struct *info );
 701static void usc_set_sdlc_mode( struct mgsl_struct *info );
 702static void usc_set_async_mode( struct mgsl_struct *info );
 703static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
 704
 705static void usc_loopback_frame( struct mgsl_struct *info );
 706
 707static void mgsl_tx_timeout(unsigned long context);
 708
 709
 710static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
 711static void usc_loopmode_insert_request( struct mgsl_struct * info );
 712static int usc_loopmode_active( struct mgsl_struct * info);
 713static void usc_loopmode_send_done( struct mgsl_struct * info );
 714
 715static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
 716
 717#if SYNCLINK_GENERIC_HDLC
 718#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 719static void hdlcdev_tx_done(struct mgsl_struct *info);
 720static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
 721static int  hdlcdev_init(struct mgsl_struct *info);
 722static void hdlcdev_exit(struct mgsl_struct *info);
 723#endif
 724
 725/*
 726 * Defines a BUS descriptor value for the PCI adapter
 727 * local bus address ranges.
 728 */
 729
 730#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
 731(0x00400020 + \
 732((WrHold) << 30) + \
 733((WrDly)  << 28) + \
 734((RdDly)  << 26) + \
 735((Nwdd)   << 20) + \
 736((Nwad)   << 15) + \
 737((Nxda)   << 13) + \
 738((Nrdd)   << 11) + \
 739((Nrad)   <<  6) )
 740
 741static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
 742
 743/*
 744 * Adapter diagnostic routines
 745 */
 746static bool mgsl_register_test( struct mgsl_struct *info );
 747static bool mgsl_irq_test( struct mgsl_struct *info );
 748static bool mgsl_dma_test( struct mgsl_struct *info );
 749static bool mgsl_memory_test( struct mgsl_struct *info );
 750static int mgsl_adapter_test( struct mgsl_struct *info );
 751
 752/*
 753 * device and resource management routines
 754 */
 755static int mgsl_claim_resources(struct mgsl_struct *info);
 756static void mgsl_release_resources(struct mgsl_struct *info);
 757static void mgsl_add_device(struct mgsl_struct *info);
 758static struct mgsl_struct* mgsl_allocate_device(void);
 759
 760/*
 761 * DMA buffer manupulation functions.
 762 */
 763static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
 764static bool mgsl_get_rx_frame( struct mgsl_struct *info );
 765static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
 766static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
 767static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
 768static int num_free_tx_dma_buffers(struct mgsl_struct *info);
 769static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
 770static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
 771
 772/*
 773 * DMA and Shared Memory buffer allocation and formatting
 774 */
 775static int  mgsl_allocate_dma_buffers(struct mgsl_struct *info);
 776static void mgsl_free_dma_buffers(struct mgsl_struct *info);
 777static int  mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 778static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 779static int  mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
 780static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
 781static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 782static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 783static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
 784static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
 785static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
 786static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
 787
 788/*
 789 * Bottom half interrupt handlers
 790 */
 791static void mgsl_bh_handler(struct work_struct *work);
 792static void mgsl_bh_receive(struct mgsl_struct *info);
 793static void mgsl_bh_transmit(struct mgsl_struct *info);
 794static void mgsl_bh_status(struct mgsl_struct *info);
 795
 796/*
 797 * Interrupt handler routines and dispatch table.
 798 */
 799static void mgsl_isr_null( struct mgsl_struct *info );
 800static void mgsl_isr_transmit_data( struct mgsl_struct *info );
 801static void mgsl_isr_receive_data( struct mgsl_struct *info );
 802static void mgsl_isr_receive_status( struct mgsl_struct *info );
 803static void mgsl_isr_transmit_status( struct mgsl_struct *info );
 804static void mgsl_isr_io_pin( struct mgsl_struct *info );
 805static void mgsl_isr_misc( struct mgsl_struct *info );
 806static void mgsl_isr_receive_dma( struct mgsl_struct *info );
 807static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
 808
 809typedef void (*isr_dispatch_func)(struct mgsl_struct *);
 810
 811static isr_dispatch_func UscIsrTable[7] =
 812{
 813        mgsl_isr_null,
 814        mgsl_isr_misc,
 815        mgsl_isr_io_pin,
 816        mgsl_isr_transmit_data,
 817        mgsl_isr_transmit_status,
 818        mgsl_isr_receive_data,
 819        mgsl_isr_receive_status
 820};
 821
 822/*
 823 * ioctl call handlers
 824 */
 825static int tiocmget(struct tty_struct *tty, struct file *file);
 826static int tiocmset(struct tty_struct *tty, struct file *file,
 827                    unsigned int set, unsigned int clear);
 828static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
 829        __user *user_icount);
 830static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS  __user *user_params);
 831static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS  __user *new_params);
 832static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
 833static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
 834static int mgsl_txenable(struct mgsl_struct * info, int enable);
 835static int mgsl_txabort(struct mgsl_struct * info);
 836static int mgsl_rxenable(struct mgsl_struct * info, int enable);
 837static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
 838static int mgsl_loopmode_send_done( struct mgsl_struct * info );
 839
 840/* set non-zero on successful registration with PCI subsystem */
 841static bool pci_registered;
 842
 843/*
 844 * Global linked list of SyncLink devices
 845 */
 846static struct mgsl_struct *mgsl_device_list;
 847static int mgsl_device_count;
 848
 849/*
 850 * Set this param to non-zero to load eax with the
 851 * .text section address and breakpoint on module load.
 852 * This is useful for use with gdb and add-symbol-file command.
 853 */
 854static int break_on_load;
 855
 856/*
 857 * Driver major number, defaults to zero to get auto
 858 * assigned major number. May be forced as module parameter.
 859 */
 860static int ttymajor;
 861
 862/*
 863 * Array of user specified options for ISA adapters.
 864 */
 865static int io[MAX_ISA_DEVICES];
 866static int irq[MAX_ISA_DEVICES];
 867static int dma[MAX_ISA_DEVICES];
 868static int debug_level;
 869static int maxframe[MAX_TOTAL_DEVICES];
 870static int txdmabufs[MAX_TOTAL_DEVICES];
 871static int txholdbufs[MAX_TOTAL_DEVICES];
 872        
 873module_param(break_on_load, bool, 0);
 874module_param(ttymajor, int, 0);
 875module_param_array(io, int, NULL, 0);
 876module_param_array(irq, int, NULL, 0);
 877module_param_array(dma, int, NULL, 0);
 878module_param(debug_level, int, 0);
 879module_param_array(maxframe, int, NULL, 0);
 880module_param_array(txdmabufs, int, NULL, 0);
 881module_param_array(txholdbufs, int, NULL, 0);
 882
 883static char *driver_name = "SyncLink serial driver";
 884static char *driver_version = "$Revision: 4.38 $";
 885
 886static int synclink_init_one (struct pci_dev *dev,
 887                                     const struct pci_device_id *ent);
 888static void synclink_remove_one (struct pci_dev *dev);
 889
 890static struct pci_device_id synclink_pci_tbl[] = {
 891        { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
 892        { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
 893        { 0, }, /* terminate list */
 894};
 895MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
 896
 897MODULE_LICENSE("GPL");
 898
 899static struct pci_driver synclink_pci_driver = {
 900        .name                = "synclink",
 901        .id_table        = synclink_pci_tbl,
 902        .probe                = synclink_init_one,
 903        .remove                = __devexit_p(synclink_remove_one),
 904};
 905
 906static struct tty_driver *serial_driver;
 907
 908/* number of characters left in xmit buffer before we ask for more */
 909#define WAKEUP_CHARS 256
 910
 911
 912static void mgsl_change_params(struct mgsl_struct *info);
 913static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
 914
 915/*
 916 * 1st function defined in .text section. Calling this function in
 917 * init_module() followed by a breakpoint allows a remote debugger
 918 * (gdb) to get the .text address for the add-symbol-file command.
 919 * This allows remote debugging of dynamically loadable modules.
 920 */
 921static void* mgsl_get_text_ptr(void)
 922{
 923        return mgsl_get_text_ptr;
 924}
 925
 926static inline int mgsl_paranoia_check(struct mgsl_struct *info,
 927                                        char *name, const char *routine)
 928{
 929#ifdef MGSL_PARANOIA_CHECK
 930        static const char *badmagic =
 931                "Warning: bad magic number for mgsl struct (%s) in %s\n";
 932        static const char *badinfo =
 933                "Warning: null mgsl_struct for (%s) in %s\n";
 934
 935        if (!info) {
 936                printk(badinfo, name, routine);
 937                return 1;
 938        }
 939        if (info->magic != MGSL_MAGIC) {
 940                printk(badmagic, name, routine);
 941                return 1;
 942        }
 943#else
 944        if (!info)
 945                return 1;
 946#endif
 947        return 0;
 948}
 949
 950/**
 951 * line discipline callback wrappers
 952 *
 953 * The wrappers maintain line discipline references
 954 * while calling into the line discipline.
 955 *
 956 * ldisc_receive_buf  - pass receive data to line discipline
 957 */
 958
 959static void ldisc_receive_buf(struct tty_struct *tty,
 960                              const __u8 *data, char *flags, int count)
 961{
 962        struct tty_ldisc *ld;
 963        if (!tty)
 964                return;
 965        ld = tty_ldisc_ref(tty);
 966        if (ld) {
 967                if (ld->ops->receive_buf)
 968                        ld->ops->receive_buf(tty, data, flags, count);
 969                tty_ldisc_deref(ld);
 970        }
 971}
 972
 973/* mgsl_stop()                throttle (stop) transmitter
 974 *         
 975 * Arguments:                tty        pointer to tty info structure
 976 * Return Value:        None
 977 */
 978static void mgsl_stop(struct tty_struct *tty)
 979{
 980        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
 981        unsigned long flags;
 982        
 983        if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
 984                return;
 985        
 986        if ( debug_level >= DEBUG_LEVEL_INFO )
 987                printk("mgsl_stop(%s)\n",info->device_name);        
 988                
 989        spin_lock_irqsave(&info->irq_spinlock,flags);
 990        if (info->tx_enabled)
 991                 usc_stop_transmitter(info);
 992        spin_unlock_irqrestore(&info->irq_spinlock,flags);
 993        
 994}        /* end of mgsl_stop() */
 995
 996/* mgsl_start()                release (start) transmitter
 997 *         
 998 * Arguments:                tty        pointer to tty info structure
 999 * Return Value:        None
1000 */
1001static void mgsl_start(struct tty_struct *tty)
1002{
1003        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1004        unsigned long flags;
1005        
1006        if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1007                return;
1008        
1009        if ( debug_level >= DEBUG_LEVEL_INFO )
1010                printk("mgsl_start(%s)\n",info->device_name);        
1011                
1012        spin_lock_irqsave(&info->irq_spinlock,flags);
1013        if (!info->tx_enabled)
1014                 usc_start_transmitter(info);
1015        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1016        
1017}        /* end of mgsl_start() */
1018
1019/*
1020 * Bottom half work queue access functions
1021 */
1022
1023/* mgsl_bh_action()        Return next bottom half action to perform.
1024 * Return Value:        BH action code or 0 if nothing to do.
1025 */
1026static int mgsl_bh_action(struct mgsl_struct *info)
1027{
1028        unsigned long flags;
1029        int rc = 0;
1030        
1031        spin_lock_irqsave(&info->irq_spinlock,flags);
1032
1033        if (info->pending_bh & BH_RECEIVE) {
1034                info->pending_bh &= ~BH_RECEIVE;
1035                rc = BH_RECEIVE;
1036        } else if (info->pending_bh & BH_TRANSMIT) {
1037                info->pending_bh &= ~BH_TRANSMIT;
1038                rc = BH_TRANSMIT;
1039        } else if (info->pending_bh & BH_STATUS) {
1040                info->pending_bh &= ~BH_STATUS;
1041                rc = BH_STATUS;
1042        }
1043
1044        if (!rc) {
1045                /* Mark BH routine as complete */
1046                info->bh_running = false;
1047                info->bh_requested = false;
1048        }
1049        
1050        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1051        
1052        return rc;
1053}
1054
1055/*
1056 *         Perform bottom half processing of work items queued by ISR.
1057 */
1058static void mgsl_bh_handler(struct work_struct *work)
1059{
1060        struct mgsl_struct *info =
1061                container_of(work, struct mgsl_struct, task);
1062        int action;
1063
1064        if (!info)
1065                return;
1066                
1067        if ( debug_level >= DEBUG_LEVEL_BH )
1068                printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1069                        __FILE__,__LINE__,info->device_name);
1070        
1071        info->bh_running = true;
1072
1073        while((action = mgsl_bh_action(info)) != 0) {
1074        
1075                /* Process work item */
1076                if ( debug_level >= DEBUG_LEVEL_BH )
1077                        printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1078                                __FILE__,__LINE__,action);
1079
1080                switch (action) {
1081                
1082                case BH_RECEIVE:
1083                        mgsl_bh_receive(info);
1084                        break;
1085                case BH_TRANSMIT:
1086                        mgsl_bh_transmit(info);
1087                        break;
1088                case BH_STATUS:
1089                        mgsl_bh_status(info);
1090                        break;
1091                default:
1092                        /* unknown work item ID */
1093                        printk("Unknown work item ID=%08X!\n", action);
1094                        break;
1095                }
1096        }
1097
1098        if ( debug_level >= DEBUG_LEVEL_BH )
1099                printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1100                        __FILE__,__LINE__,info->device_name);
1101}
1102
1103static void mgsl_bh_receive(struct mgsl_struct *info)
1104{
1105        bool (*get_rx_frame)(struct mgsl_struct *info) =
1106                (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1107
1108        if ( debug_level >= DEBUG_LEVEL_BH )
1109                printk( "%s(%d):mgsl_bh_receive(%s)\n",
1110                        __FILE__,__LINE__,info->device_name);
1111        
1112        do
1113        {
1114                if (info->rx_rcc_underrun) {
1115                        unsigned long flags;
1116                        spin_lock_irqsave(&info->irq_spinlock,flags);
1117                        usc_start_receiver(info);
1118                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1119                        return;
1120                }
1121        } while(get_rx_frame(info));
1122}
1123
1124static void mgsl_bh_transmit(struct mgsl_struct *info)
1125{
1126        struct tty_struct *tty = info->port.tty;
1127        unsigned long flags;
1128        
1129        if ( debug_level >= DEBUG_LEVEL_BH )
1130                printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1131                        __FILE__,__LINE__,info->device_name);
1132
1133        if (tty)
1134                tty_wakeup(tty);
1135
1136        /* if transmitter idle and loopmode_send_done_requested
1137         * then start echoing RxD to TxD
1138         */
1139        spin_lock_irqsave(&info->irq_spinlock,flags);
1140         if ( !info->tx_active && info->loopmode_send_done_requested )
1141                 usc_loopmode_send_done( info );
1142        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1143}
1144
1145static void mgsl_bh_status(struct mgsl_struct *info)
1146{
1147        if ( debug_level >= DEBUG_LEVEL_BH )
1148                printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1149                        __FILE__,__LINE__,info->device_name);
1150
1151        info->ri_chkcount = 0;
1152        info->dsr_chkcount = 0;
1153        info->dcd_chkcount = 0;
1154        info->cts_chkcount = 0;
1155}
1156
1157/* mgsl_isr_receive_status()
1158 * 
1159 *        Service a receive status interrupt. The type of status
1160 *        interrupt is indicated by the state of the RCSR.
1161 *        This is only used for HDLC mode.
1162 *
1163 * Arguments:                info        pointer to device instance data
1164 * Return Value:        None
1165 */
1166static void mgsl_isr_receive_status( struct mgsl_struct *info )
1167{
1168        u16 status = usc_InReg( info, RCSR );
1169
1170        if ( debug_level >= DEBUG_LEVEL_ISR )        
1171                printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1172                        __FILE__,__LINE__,status);
1173                        
1174         if ( (status & RXSTATUS_ABORT_RECEIVED) && 
1175                info->loopmode_insert_requested &&
1176                 usc_loopmode_active(info) )
1177         {
1178                ++info->icount.rxabort;
1179                 info->loopmode_insert_requested = false;
1180 
1181                 /* clear CMR:13 to start echoing RxD to TxD */
1182                info->cmr_value &= ~BIT13;
1183                 usc_OutReg(info, CMR, info->cmr_value);
1184 
1185                /* disable received abort irq (no longer required) */
1186                 usc_OutReg(info, RICR,
1187                         (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1188         }
1189
1190        if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1191                if (status & RXSTATUS_EXITED_HUNT)
1192                        info->icount.exithunt++;
1193                if (status & RXSTATUS_IDLE_RECEIVED)
1194                        info->icount.rxidle++;
1195                wake_up_interruptible(&info->event_wait_q);
1196        }
1197
1198        if (status & RXSTATUS_OVERRUN){
1199                info->icount.rxover++;
1200                usc_process_rxoverrun_sync( info );
1201        }
1202
1203        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1204        usc_UnlatchRxstatusBits( info, status );
1205
1206}        /* end of mgsl_isr_receive_status() */
1207
1208/* mgsl_isr_transmit_status()
1209 * 
1210 *         Service a transmit status interrupt
1211 *        HDLC mode :end of transmit frame
1212 *        Async mode:all data is sent
1213 *         transmit status is indicated by bits in the TCSR.
1214 * 
1215 * Arguments:                info               pointer to device instance data
1216 * Return Value:        None
1217 */
1218static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1219{
1220        u16 status = usc_InReg( info, TCSR );
1221
1222        if ( debug_level >= DEBUG_LEVEL_ISR )        
1223                printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1224                        __FILE__,__LINE__,status);
1225        
1226        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1227        usc_UnlatchTxstatusBits( info, status );
1228        
1229        if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1230        {
1231                /* finished sending HDLC abort. This may leave        */
1232                /* the TxFifo with data from the aborted frame        */
1233                /* so purge the TxFifo. Also shutdown the DMA        */
1234                /* channel in case there is data remaining in         */
1235                /* the DMA buffer                                */
1236                 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1237                 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1238        }
1239 
1240        if ( status & TXSTATUS_EOF_SENT )
1241                info->icount.txok++;
1242        else if ( status & TXSTATUS_UNDERRUN )
1243                info->icount.txunder++;
1244        else if ( status & TXSTATUS_ABORT_SENT )
1245                info->icount.txabort++;
1246        else
1247                info->icount.txunder++;
1248                        
1249        info->tx_active = false;
1250        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1251        del_timer(&info->tx_timer);        
1252        
1253        if ( info->drop_rts_on_tx_done ) {
1254                usc_get_serial_signals( info );
1255                if ( info->serial_signals & SerialSignal_RTS ) {
1256                        info->serial_signals &= ~SerialSignal_RTS;
1257                        usc_set_serial_signals( info );
1258                }
1259                info->drop_rts_on_tx_done = false;
1260        }
1261
1262#if SYNCLINK_GENERIC_HDLC
1263        if (info->netcount)
1264                hdlcdev_tx_done(info);
1265        else 
1266#endif
1267        {
1268                if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1269                        usc_stop_transmitter(info);
1270                        return;
1271                }
1272                info->pending_bh |= BH_TRANSMIT;
1273        }
1274
1275}        /* end of mgsl_isr_transmit_status() */
1276
1277/* mgsl_isr_io_pin()
1278 * 
1279 *         Service an Input/Output pin interrupt. The type of
1280 *         interrupt is indicated by bits in the MISR
1281 *         
1282 * Arguments:                info               pointer to device instance data
1283 * Return Value:        None
1284 */
1285static void mgsl_isr_io_pin( struct mgsl_struct *info )
1286{
1287         struct        mgsl_icount *icount;
1288        u16 status = usc_InReg( info, MISR );
1289
1290        if ( debug_level >= DEBUG_LEVEL_ISR )        
1291                printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1292                        __FILE__,__LINE__,status);
1293                        
1294        usc_ClearIrqPendingBits( info, IO_PIN );
1295        usc_UnlatchIostatusBits( info, status );
1296
1297        if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1298                      MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1299                icount = &info->icount;
1300                /* update input line counters */
1301                if (status & MISCSTATUS_RI_LATCHED) {
1302                        if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1303                                usc_DisablestatusIrqs(info,SICR_RI);
1304                        icount->rng++;
1305                        if ( status & MISCSTATUS_RI )
1306                                info->input_signal_events.ri_up++;        
1307                        else
1308                                info->input_signal_events.ri_down++;        
1309                }
1310                if (status & MISCSTATUS_DSR_LATCHED) {
1311                        if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1312                                usc_DisablestatusIrqs(info,SICR_DSR);
1313                        icount->dsr++;
1314                        if ( status & MISCSTATUS_DSR )
1315                                info->input_signal_events.dsr_up++;
1316                        else
1317                                info->input_signal_events.dsr_down++;
1318                }
1319                if (status & MISCSTATUS_DCD_LATCHED) {
1320                        if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1321                                usc_DisablestatusIrqs(info,SICR_DCD);
1322                        icount->dcd++;
1323                        if (status & MISCSTATUS_DCD) {
1324                                info->input_signal_events.dcd_up++;
1325                        } else
1326                                info->input_signal_events.dcd_down++;
1327#if SYNCLINK_GENERIC_HDLC
1328                        if (info->netcount) {
1329                                if (status & MISCSTATUS_DCD)
1330                                        netif_carrier_on(info->netdev);
1331                                else
1332                                        netif_carrier_off(info->netdev);
1333                        }
1334#endif
1335                }
1336                if (status & MISCSTATUS_CTS_LATCHED)
1337                {
1338                        if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1339                                usc_DisablestatusIrqs(info,SICR_CTS);
1340                        icount->cts++;
1341                        if ( status & MISCSTATUS_CTS )
1342                                info->input_signal_events.cts_up++;
1343                        else
1344                                info->input_signal_events.cts_down++;
1345                }
1346                wake_up_interruptible(&info->status_event_wait_q);
1347                wake_up_interruptible(&info->event_wait_q);
1348
1349                if ( (info->port.flags & ASYNC_CHECK_CD) && 
1350                     (status & MISCSTATUS_DCD_LATCHED) ) {
1351                        if ( debug_level >= DEBUG_LEVEL_ISR )
1352                                printk("%s CD now %s...", info->device_name,
1353                                       (status & MISCSTATUS_DCD) ? "on" : "off");
1354                        if (status & MISCSTATUS_DCD)
1355                                wake_up_interruptible(&info->port.open_wait);
1356                        else {
1357                                if ( debug_level >= DEBUG_LEVEL_ISR )
1358                                        printk("doing serial hangup...");
1359                                if (info->port.tty)
1360                                        tty_hangup(info->port.tty);
1361                        }
1362                }
1363        
1364                if ( (info->port.flags & ASYNC_CTS_FLOW) && 
1365                     (status & MISCSTATUS_CTS_LATCHED) ) {
1366                        if (info->port.tty->hw_stopped) {
1367                                if (status & MISCSTATUS_CTS) {
1368                                        if ( debug_level >= DEBUG_LEVEL_ISR )
1369                                                printk("CTS tx start...");
1370                                        if (info->port.tty)
1371                                                info->port.tty->hw_stopped = 0;
1372                                        usc_start_transmitter(info);
1373                                        info->pending_bh |= BH_TRANSMIT;
1374                                        return;
1375                                }
1376                        } else {
1377                                if (!(status & MISCSTATUS_CTS)) {
1378                                        if ( debug_level >= DEBUG_LEVEL_ISR )
1379                                                printk("CTS tx stop...");
1380                                        if (info->port.tty)
1381                                                info->port.tty->hw_stopped = 1;
1382                                        usc_stop_transmitter(info);
1383                                }
1384                        }
1385                }
1386        }
1387
1388        info->pending_bh |= BH_STATUS;
1389        
1390        /* for diagnostics set IRQ flag */
1391        if ( status & MISCSTATUS_TXC_LATCHED ){
1392                usc_OutReg( info, SICR,
1393                        (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1394                usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1395                info->irq_occurred = true;
1396        }
1397
1398}        /* end of mgsl_isr_io_pin() */
1399
1400/* mgsl_isr_transmit_data()
1401 * 
1402 *         Service a transmit data interrupt (async mode only).
1403 * 
1404 * Arguments:                info        pointer to device instance data
1405 * Return Value:        None
1406 */
1407static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1408{
1409        if ( debug_level >= DEBUG_LEVEL_ISR )        
1410                printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1411                        __FILE__,__LINE__,info->xmit_cnt);
1412                        
1413        usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1414        
1415        if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1416                usc_stop_transmitter(info);
1417                return;
1418        }
1419        
1420        if ( info->xmit_cnt )
1421                usc_load_txfifo( info );
1422        else
1423                info->tx_active = false;
1424                
1425        if (info->xmit_cnt < WAKEUP_CHARS)
1426                info->pending_bh |= BH_TRANSMIT;
1427
1428}        /* end of mgsl_isr_transmit_data() */
1429
1430/* mgsl_isr_receive_data()
1431 * 
1432 *         Service a receive data interrupt. This occurs
1433 *         when operating in asynchronous interrupt transfer mode.
1434 *        The receive data FIFO is flushed to the receive data buffers. 
1435 * 
1436 * Arguments:                info                pointer to device instance data
1437 * Return Value:        None
1438 */
1439static void mgsl_isr_receive_data( struct mgsl_struct *info )
1440{
1441        int Fifocount;
1442        u16 status;
1443        int work = 0;
1444        unsigned char DataByte;
1445         struct tty_struct *tty = info->port.tty;
1446         struct        mgsl_icount *icount = &info->icount;
1447        
1448        if ( debug_level >= DEBUG_LEVEL_ISR )        
1449                printk("%s(%d):mgsl_isr_receive_data\n",
1450                        __FILE__,__LINE__);
1451
1452        usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1453        
1454        /* select FIFO status for RICR readback */
1455        usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1456
1457        /* clear the Wordstatus bit so that status readback */
1458        /* only reflects the status of this byte */
1459        usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1460
1461        /* flush the receive FIFO */
1462
1463        while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1464                int flag;
1465
1466                /* read one byte from RxFIFO */
1467                outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1468                      info->io_base + CCAR );
1469                DataByte = inb( info->io_base + CCAR );
1470
1471                /* get the status of the received byte */
1472                status = usc_InReg(info, RCSR);
1473                if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1474                                RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1475                        usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1476                
1477                icount->rx++;
1478                
1479                flag = 0;
1480                if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1481                                RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1482                        printk("rxerr=%04X\n",status);                                        
1483                        /* update error statistics */
1484                        if ( status & RXSTATUS_BREAK_RECEIVED ) {
1485                                status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1486                                icount->brk++;
1487                        } else if (status & RXSTATUS_PARITY_ERROR) 
1488                                icount->parity++;
1489                        else if (status & RXSTATUS_FRAMING_ERROR)
1490                                icount->frame++;
1491                        else if (status & RXSTATUS_OVERRUN) {
1492                                /* must issue purge fifo cmd before */
1493                                /* 16C32 accepts more receive chars */
1494                                usc_RTCmd(info,RTCmd_PurgeRxFifo);
1495                                icount->overrun++;
1496                        }
1497
1498                        /* discard char if tty control flags say so */                                        
1499                        if (status & info->ignore_status_mask)
1500                                continue;
1501                                
1502                        status &= info->read_status_mask;
1503                
1504                        if (status & RXSTATUS_BREAK_RECEIVED) {
1505                                flag = TTY_BREAK;
1506                                if (info->port.flags & ASYNC_SAK)
1507                                        do_SAK(tty);
1508                        } else if (status & RXSTATUS_PARITY_ERROR)
1509                                flag = TTY_PARITY;
1510                        else if (status & RXSTATUS_FRAMING_ERROR)
1511                                flag = TTY_FRAME;
1512                }        /* end of if (error) */
1513                tty_insert_flip_char(tty, DataByte, flag);
1514                if (status & RXSTATUS_OVERRUN) {
1515                        /* Overrun is special, since it's
1516                         * reported immediately, and doesn't
1517                         * affect the current character
1518                         */
1519                        work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1520                }
1521        }
1522
1523        if ( debug_level >= DEBUG_LEVEL_ISR ) {
1524                printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1525                        __FILE__,__LINE__,icount->rx,icount->brk,
1526                        icount->parity,icount->frame,icount->overrun);
1527        }
1528                        
1529        if(work)
1530                tty_flip_buffer_push(tty);
1531}
1532
1533/* mgsl_isr_misc()
1534 * 
1535 *         Service a miscellaneous interrupt source.
1536 *         
1537 * Arguments:                info                pointer to device extension (instance data)
1538 * Return Value:        None
1539 */
1540static void mgsl_isr_misc( struct mgsl_struct *info )
1541{
1542        u16 status = usc_InReg( info, MISR );
1543
1544        if ( debug_level >= DEBUG_LEVEL_ISR )        
1545                printk("%s(%d):mgsl_isr_misc status=%04X\n",
1546                        __FILE__,__LINE__,status);
1547                        
1548        if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1549            (info->params.mode == MGSL_MODE_HDLC)) {
1550
1551                /* turn off receiver and rx DMA */
1552                usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1553                usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1554                usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1555                usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1556                usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1557
1558                /* schedule BH handler to restart receiver */
1559                info->pending_bh |= BH_RECEIVE;
1560                info->rx_rcc_underrun = true;
1561        }
1562
1563        usc_ClearIrqPendingBits( info, MISC );
1564        usc_UnlatchMiscstatusBits( info, status );
1565
1566}        /* end of mgsl_isr_misc() */
1567
1568/* mgsl_isr_null()
1569 *
1570 *         Services undefined interrupt vectors from the
1571 *         USC. (hence this function SHOULD never be called)
1572 * 
1573 * Arguments:                info                pointer to device extension (instance data)
1574 * Return Value:        None
1575 */
1576static void mgsl_isr_null( struct mgsl_struct *info )
1577{
1578
1579}        /* end of mgsl_isr_null() */
1580
1581/* mgsl_isr_receive_dma()
1582 * 
1583 *         Service a receive DMA channel interrupt.
1584 *         For this driver there are two sources of receive DMA interrupts
1585 *         as identified in the Receive DMA mode Register (RDMR):
1586 * 
1587 *         BIT3        EOA/EOL                End of List, all receive buffers in receive
1588 *                                 buffer list have been filled (no more free buffers
1589 *                                 available). The DMA controller has shut down.
1590 * 
1591 *         BIT2        EOB                End of Buffer. This interrupt occurs when a receive
1592 *                                 DMA buffer is terminated in response to completion
1593 *                                 of a good frame or a frame with errors. The status
1594 *                                 of the frame is stored in the buffer entry in the
1595 *                                 list of receive buffer entries.
1596 * 
1597 * Arguments:                info                pointer to device instance data
1598 * Return Value:        None
1599 */
1600static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1601{
1602        u16 status;
1603        
1604        /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1605        usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1606
1607        /* Read the receive DMA status to identify interrupt type. */
1608        /* This also clears the status bits. */
1609        status = usc_InDmaReg( info, RDMR );
1610
1611        if ( debug_level >= DEBUG_LEVEL_ISR )        
1612                printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1613                        __FILE__,__LINE__,info->device_name,status);
1614                        
1615        info->pending_bh |= BH_RECEIVE;
1616        
1617        if ( status & BIT3 ) {
1618                info->rx_overflow = true;
1619                info->icount.buf_overrun++;
1620        }
1621
1622}        /* end of mgsl_isr_receive_dma() */
1623
1624/* mgsl_isr_transmit_dma()
1625 *
1626 *        This function services a transmit DMA channel interrupt.
1627 *
1628 *        For this driver there is one source of transmit DMA interrupts
1629 *        as identified in the Transmit DMA Mode Register (TDMR):
1630 *
1631 *             BIT2  EOB       End of Buffer. This interrupt occurs when a
1632 *                             transmit DMA buffer has been emptied.
1633 *
1634 *             The driver maintains enough transmit DMA buffers to hold at least
1635 *             one max frame size transmit frame. When operating in a buffered
1636 *             transmit mode, there may be enough transmit DMA buffers to hold at
1637 *             least two or more max frame size frames. On an EOB condition,
1638 *             determine if there are any queued transmit buffers and copy into
1639 *             transmit DMA buffers if we have room.
1640 *
1641 * Arguments:                info                pointer to device instance data
1642 * Return Value:        None
1643 */
1644static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1645{
1646        u16 status;
1647
1648        /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1649        usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1650
1651        /* Read the transmit DMA status to identify interrupt type. */
1652        /* This also clears the status bits. */
1653
1654        status = usc_InDmaReg( info, TDMR );
1655
1656        if ( debug_level >= DEBUG_LEVEL_ISR )
1657                printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1658                        __FILE__,__LINE__,info->device_name,status);
1659
1660        if ( status & BIT2 ) {
1661                --info->tx_dma_buffers_used;
1662
1663                /* if there are transmit frames queued,
1664                 *  try to load the next one
1665                 */
1666                if ( load_next_tx_holding_buffer(info) ) {
1667                        /* if call returns non-zero value, we have
1668                         * at least one free tx holding buffer
1669                         */
1670                        info->pending_bh |= BH_TRANSMIT;
1671                }
1672        }
1673
1674}        /* end of mgsl_isr_transmit_dma() */
1675
1676/* mgsl_interrupt()
1677 * 
1678 *         Interrupt service routine entry point.
1679 *         
1680 * Arguments:
1681 * 
1682 *         irq                interrupt number that caused interrupt
1683 *         dev_id                device ID supplied during interrupt registration
1684 *         
1685 * Return Value: None
1686 */
1687static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1688{
1689        struct mgsl_struct *info = dev_id;
1690        u16 UscVector;
1691        u16 DmaVector;
1692
1693        if ( debug_level >= DEBUG_LEVEL_ISR )        
1694                printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1695                        __FILE__, __LINE__, info->irq_level);
1696
1697        spin_lock(&info->irq_spinlock);
1698
1699        for(;;) {
1700                /* Read the interrupt vectors from hardware. */
1701                UscVector = usc_InReg(info, IVR) >> 9;
1702                DmaVector = usc_InDmaReg(info, DIVR);
1703                
1704                if ( debug_level >= DEBUG_LEVEL_ISR )        
1705                        printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1706                                __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1707                        
1708                if ( !UscVector && !DmaVector )
1709                        break;
1710                        
1711                /* Dispatch interrupt vector */
1712                if ( UscVector )
1713                        (*UscIsrTable[UscVector])(info);
1714                else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1715                        mgsl_isr_transmit_dma(info);
1716                else
1717                        mgsl_isr_receive_dma(info);
1718
1719                if ( info->isr_overflow ) {
1720                        printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1721                                __FILE__, __LINE__, info->device_name, info->irq_level);
1722                        usc_DisableMasterIrqBit(info);
1723                        usc_DisableDmaInterrupts(info,DICR_MASTER);
1724                        break;
1725                }
1726        }
1727        
1728        /* Request bottom half processing if there's something 
1729         * for it to do and the bh is not already running
1730         */
1731
1732        if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1733                if ( debug_level >= DEBUG_LEVEL_ISR )        
1734                        printk("%s(%d):%s queueing bh task.\n",
1735                                __FILE__,__LINE__,info->device_name);
1736                schedule_work(&info->task);
1737                info->bh_requested = true;
1738        }
1739
1740        spin_unlock(&info->irq_spinlock);
1741        
1742        if ( debug_level >= DEBUG_LEVEL_ISR )        
1743                printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1744                        __FILE__, __LINE__, info->irq_level);
1745
1746        return IRQ_HANDLED;
1747}        /* end of mgsl_interrupt() */
1748
1749/* startup()
1750 * 
1751 *         Initialize and start device.
1752 *         
1753 * Arguments:                info        pointer to device instance data
1754 * Return Value:        0 if success, otherwise error code
1755 */
1756static int startup(struct mgsl_struct * info)
1757{
1758        int retval = 0;
1759        
1760        if ( debug_level >= DEBUG_LEVEL_INFO )
1761                printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1762                
1763        if (info->port.flags & ASYNC_INITIALIZED)
1764                return 0;
1765        
1766        if (!info->xmit_buf) {
1767                /* allocate a page of memory for a transmit buffer */
1768                info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1769                if (!info->xmit_buf) {
1770                        printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1771                                __FILE__,__LINE__,info->device_name);
1772                        return -ENOMEM;
1773                }
1774        }
1775
1776        info->pending_bh = 0;
1777        
1778        memset(&info->icount, 0, sizeof(info->icount));
1779
1780        setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1781        
1782        /* Allocate and claim adapter resources */
1783        retval = mgsl_claim_resources(info);
1784        
1785        /* perform existence check and diagnostics */
1786        if ( !retval )
1787                retval = mgsl_adapter_test(info);
1788                
1789        if ( retval ) {
1790                  if (capable(CAP_SYS_ADMIN) && info->port.tty)
1791                        set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1792                mgsl_release_resources(info);
1793                  return retval;
1794          }
1795
1796        /* program hardware for current parameters */
1797        mgsl_change_params(info);
1798        
1799        if (info->port.tty)
1800                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1801
1802        info->port.flags |= ASYNC_INITIALIZED;
1803        
1804        return 0;
1805        
1806}        /* end of startup() */
1807
1808/* shutdown()
1809 *
1810 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1811 *
1812 * Arguments:                info        pointer to device instance data
1813 * Return Value:        None
1814 */
1815static void shutdown(struct mgsl_struct * info)
1816{
1817        unsigned long flags;
1818        
1819        if (!(info->port.flags & ASYNC_INITIALIZED))
1820                return;
1821
1822        if (debug_level >= DEBUG_LEVEL_INFO)
1823                printk("%s(%d):mgsl_shutdown(%s)\n",
1824                         __FILE__,__LINE__, info->device_name );
1825
1826        /* clear status wait queue because status changes */
1827        /* can't happen after shutting down the hardware */
1828        wake_up_interruptible(&info->status_event_wait_q);
1829        wake_up_interruptible(&info->event_wait_q);
1830
1831        del_timer_sync(&info->tx_timer);
1832
1833        if (info->xmit_buf) {
1834                free_page((unsigned long) info->xmit_buf);
1835                info->xmit_buf = NULL;
1836        }
1837
1838        spin_lock_irqsave(&info->irq_spinlock,flags);
1839        usc_DisableMasterIrqBit(info);
1840        usc_stop_receiver(info);
1841        usc_stop_transmitter(info);
1842        usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1843                TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1844        usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1845        
1846        /* Disable DMAEN (Port 7, Bit 14) */
1847        /* This disconnects the DMA request signal from the ISA bus */
1848        /* on the ISA adapter. This has no effect for the PCI adapter */
1849        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1850        
1851        /* Disable INTEN (Port 6, Bit12) */
1852        /* This disconnects the IRQ request signal to the ISA bus */
1853        /* on the ISA adapter. This has no effect for the PCI adapter */
1854        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1855        
1856         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1857                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1858                usc_set_serial_signals(info);
1859        }
1860        
1861        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1862
1863        mgsl_release_resources(info);        
1864        
1865        if (info->port.tty)
1866                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1867
1868        info->port.flags &= ~ASYNC_INITIALIZED;
1869        
1870}        /* end of shutdown() */
1871
1872static void mgsl_program_hw(struct mgsl_struct *info)
1873{
1874        unsigned long flags;
1875
1876        spin_lock_irqsave(&info->irq_spinlock,flags);
1877        
1878        usc_stop_receiver(info);
1879        usc_stop_transmitter(info);
1880        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1881        
1882        if (info->params.mode == MGSL_MODE_HDLC ||
1883            info->params.mode == MGSL_MODE_RAW ||
1884            info->netcount)
1885                usc_set_sync_mode(info);
1886        else
1887                usc_set_async_mode(info);
1888                
1889        usc_set_serial_signals(info);
1890        
1891        info->dcd_chkcount = 0;
1892        info->cts_chkcount = 0;
1893        info->ri_chkcount = 0;
1894        info->dsr_chkcount = 0;
1895
1896        usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);                
1897        usc_EnableInterrupts(info, IO_PIN);
1898        usc_get_serial_signals(info);
1899                
1900        if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1901                usc_start_receiver(info);
1902                
1903        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1904}
1905
1906/* Reconfigure adapter based on new parameters
1907 */
1908static void mgsl_change_params(struct mgsl_struct *info)
1909{
1910        unsigned cflag;
1911        int bits_per_char;
1912
1913        if (!info->port.tty || !info->port.tty->termios)
1914                return;
1915                
1916        if (debug_level >= DEBUG_LEVEL_INFO)
1917                printk("%s(%d):mgsl_change_params(%s)\n",
1918                         __FILE__,__LINE__, info->device_name );
1919                         
1920        cflag = info->port.tty->termios->c_cflag;
1921
1922        /* if B0 rate (hangup) specified then negate DTR and RTS */
1923        /* otherwise assert DTR and RTS */
1924         if (cflag & CBAUD)
1925                info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1926        else
1927                info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1928        
1929        /* byte size and parity */
1930        
1931        switch (cflag & CSIZE) {
1932              case CS5: info->params.data_bits = 5; break;
1933              case CS6: info->params.data_bits = 6; break;
1934              case CS7: info->params.data_bits = 7; break;
1935              case CS8: info->params.data_bits = 8; break;
1936              /* Never happens, but GCC is too dumb to figure it out */
1937              default:  info->params.data_bits = 7; break;
1938              }
1939              
1940        if (cflag & CSTOPB)
1941                info->params.stop_bits = 2;
1942        else
1943                info->params.stop_bits = 1;
1944
1945        info->params.parity = ASYNC_PARITY_NONE;
1946        if (cflag & PARENB) {
1947                if (cflag & PARODD)
1948                        info->params.parity = ASYNC_PARITY_ODD;
1949                else
1950                        info->params.parity = ASYNC_PARITY_EVEN;
1951#ifdef CMSPAR
1952                if (cflag & CMSPAR)
1953                        info->params.parity = ASYNC_PARITY_SPACE;
1954#endif
1955        }
1956
1957        /* calculate number of jiffies to transmit a full
1958         * FIFO (32 bytes) at specified data rate
1959         */
1960        bits_per_char = info->params.data_bits + 
1961                        info->params.stop_bits + 1;
1962
1963        /* if port data rate is set to 460800 or less then
1964         * allow tty settings to override, otherwise keep the
1965         * current data rate.
1966         */
1967        if (info->params.data_rate <= 460800)
1968                info->params.data_rate = tty_get_baud_rate(info->port.tty);
1969        
1970        if ( info->params.data_rate ) {
1971                info->timeout = (32*HZ*bits_per_char) / 
1972                                info->params.data_rate;
1973        }
1974        info->timeout += HZ/50;                /* Add .02 seconds of slop */
1975
1976        if (cflag & CRTSCTS)
1977                info->port.flags |= ASYNC_CTS_FLOW;
1978        else
1979                info->port.flags &= ~ASYNC_CTS_FLOW;
1980                
1981        if (cflag & CLOCAL)
1982                info->port.flags &= ~ASYNC_CHECK_CD;
1983        else
1984                info->port.flags |= ASYNC_CHECK_CD;
1985
1986        /* process tty input control flags */
1987        
1988        info->read_status_mask = RXSTATUS_OVERRUN;
1989        if (I_INPCK(info->port.tty))
1990                info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1991         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1992                 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1993        
1994        if (I_IGNPAR(info->port.tty))
1995                info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1996        if (I_IGNBRK(info->port.tty)) {
1997                info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1998                /* If ignoring parity and break indicators, ignore 
1999                 * overruns too.  (For real raw support).
2000                 */
2001                if (I_IGNPAR(info->port.tty))
2002                        info->ignore_status_mask |= RXSTATUS_OVERRUN;
2003        }
2004
2005        mgsl_program_hw(info);
2006
2007}        /* end of mgsl_change_params() */
2008
2009/* mgsl_put_char()
2010 * 
2011 *         Add a character to the transmit buffer.
2012 *         
2013 * Arguments:                tty        pointer to tty information structure
2014 *                         ch        character to add to transmit buffer
2015 *                 
2016 * Return Value:        None
2017 */
2018static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2019{
2020        struct mgsl_struct *info = tty->driver_data;
2021        unsigned long flags;
2022        int ret = 0;
2023
2024        if (debug_level >= DEBUG_LEVEL_INFO) {
2025                printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2026                        __FILE__, __LINE__, ch, info->device_name);
2027        }                
2028        
2029        if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2030                return 0;
2031
2032        if (!tty || !info->xmit_buf)
2033                return 0;
2034
2035        spin_lock_irqsave(&info->irq_spinlock, flags);
2036        
2037        if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2038                if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2039                        info->xmit_buf[info->xmit_head++] = ch;
2040                        info->xmit_head &= SERIAL_XMIT_SIZE-1;
2041                        info->xmit_cnt++;
2042                        ret = 1;
2043                }
2044        }
2045        spin_unlock_irqrestore(&info->irq_spinlock, flags);
2046        return ret;
2047        
2048}        /* end of mgsl_put_char() */
2049
2050/* mgsl_flush_chars()
2051 * 
2052 *         Enable transmitter so remaining characters in the
2053 *         transmit buffer are sent.
2054 *         
2055 * Arguments:                tty        pointer to tty information structure
2056 * Return Value:        None
2057 */
2058static void mgsl_flush_chars(struct tty_struct *tty)
2059{
2060        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2061        unsigned long flags;
2062                                
2063        if ( debug_level >= DEBUG_LEVEL_INFO )
2064                printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2065                        __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2066        
2067        if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2068                return;
2069
2070        if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2071            !info->xmit_buf)
2072                return;
2073
2074        if ( debug_level >= DEBUG_LEVEL_INFO )
2075                printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2076                        __FILE__,__LINE__,info->device_name );
2077
2078        spin_lock_irqsave(&info->irq_spinlock,flags);
2079        
2080        if (!info->tx_active) {
2081                if ( (info->params.mode == MGSL_MODE_HDLC ||
2082                        info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2083                        /* operating in synchronous (frame oriented) mode */
2084                        /* copy data from circular xmit_buf to */
2085                        /* transmit DMA buffer. */
2086                        mgsl_load_tx_dma_buffer(info,
2087                                 info->xmit_buf,info->xmit_cnt);
2088                }
2089                 usc_start_transmitter(info);
2090        }
2091        
2092        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2093        
2094}        /* end of mgsl_flush_chars() */
2095
2096/* mgsl_write()
2097 * 
2098 *         Send a block of data
2099 *         
2100 * Arguments:
2101 * 
2102 *         tty                pointer to tty information structure
2103 *         buf                pointer to buffer containing send data
2104 *         count                size of send data in bytes
2105 *         
2106 * Return Value:        number of characters written
2107 */
2108static int mgsl_write(struct tty_struct * tty,
2109                    const unsigned char *buf, int count)
2110{
2111        int        c, ret = 0;
2112        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2113        unsigned long flags;
2114        
2115        if ( debug_level >= DEBUG_LEVEL_INFO )
2116                printk( "%s(%d):mgsl_write(%s) count=%d\n",
2117                        __FILE__,__LINE__,info->device_name,count);
2118        
2119        if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2120                goto cleanup;
2121
2122        if (!tty || !info->xmit_buf)
2123                goto cleanup;
2124
2125        if ( info->params.mode == MGSL_MODE_HDLC ||
2126                        info->params.mode == MGSL_MODE_RAW ) {
2127                /* operating in synchronous (frame oriented) mode */
2128                /* operating in synchronous (frame oriented) mode */
2129                if (info->tx_active) {
2130
2131                        if ( info->params.mode == MGSL_MODE_HDLC ) {
2132                                ret = 0;
2133                                goto cleanup;
2134                        }
2135                        /* transmitter is actively sending data -
2136                         * if we have multiple transmit dma and
2137                         * holding buffers, attempt to queue this
2138                         * frame for transmission at a later time.
2139                         */
2140                        if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2141                                /* no tx holding buffers available */
2142                                ret = 0;
2143                                goto cleanup;
2144                        }
2145
2146                        /* queue transmit frame request */
2147                        ret = count;
2148                        save_tx_buffer_request(info,buf,count);
2149
2150                        /* if we have sufficient tx dma buffers,
2151                         * load the next buffered tx request
2152                         */
2153                        spin_lock_irqsave(&info->irq_spinlock,flags);
2154                        load_next_tx_holding_buffer(info);
2155                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2156                        goto cleanup;
2157                }
2158        
2159                /* if operating in HDLC LoopMode and the adapter  */
2160                /* has yet to be inserted into the loop, we can't */
2161                /* transmit                                          */
2162
2163                if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2164                        !usc_loopmode_active(info) )
2165                {
2166                        ret = 0;
2167                        goto cleanup;
2168                }
2169
2170                if ( info->xmit_cnt ) {
2171                        /* Send accumulated from send_char() calls */
2172                        /* as frame and wait before accepting more data. */
2173                        ret = 0;
2174                        
2175                        /* copy data from circular xmit_buf to */
2176                        /* transmit DMA buffer. */
2177                        mgsl_load_tx_dma_buffer(info,
2178                                info->xmit_buf,info->xmit_cnt);
2179                        if ( debug_level >= DEBUG_LEVEL_INFO )
2180                                printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2181                                        __FILE__,__LINE__,info->device_name);
2182                } else {
2183                        if ( debug_level >= DEBUG_LEVEL_INFO )
2184                                printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2185                                        __FILE__,__LINE__,info->device_name);
2186                        ret = count;
2187                        info->xmit_cnt = count;
2188                        mgsl_load_tx_dma_buffer(info,buf,count);
2189                }
2190        } else {
2191                while (1) {
2192                        spin_lock_irqsave(&info->irq_spinlock,flags);
2193                        c = min_t(int, count,
2194                                min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2195                                    SERIAL_XMIT_SIZE - info->xmit_head));
2196                        if (c <= 0) {
2197                                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2198                                break;
2199                        }
2200                        memcpy(info->xmit_buf + info->xmit_head, buf, c);
2201                        info->xmit_head = ((info->xmit_head + c) &
2202                                           (SERIAL_XMIT_SIZE-1));
2203                        info->xmit_cnt += c;
2204                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2205                        buf += c;
2206                        count -= c;
2207                        ret += c;
2208                }
2209        }        
2210        
2211         if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2212                spin_lock_irqsave(&info->irq_spinlock,flags);
2213                if (!info->tx_active)
2214                         usc_start_transmitter(info);
2215                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2216         }
2217cleanup:        
2218        if ( debug_level >= DEBUG_LEVEL_INFO )
2219                printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2220                        __FILE__,__LINE__,info->device_name,ret);
2221                        
2222        return ret;
2223        
2224}        /* end of mgsl_write() */
2225
2226/* mgsl_write_room()
2227 *
2228 *        Return the count of free bytes in transmit buffer
2229 *         
2230 * Arguments:                tty        pointer to tty info structure
2231 * Return Value:        None
2232 */
2233static int mgsl_write_room(struct tty_struct *tty)
2234{
2235        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2236        int        ret;
2237                                
2238        if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2239                return 0;
2240        ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2241        if (ret < 0)
2242                ret = 0;
2243                
2244        if (debug_level >= DEBUG_LEVEL_INFO)
2245                printk("%s(%d):mgsl_write_room(%s)=%d\n",
2246                         __FILE__,__LINE__, info->device_name,ret );
2247                         
2248        if ( info->params.mode == MGSL_MODE_HDLC ||
2249                info->params.mode == MGSL_MODE_RAW ) {
2250                /* operating in synchronous (frame oriented) mode */
2251                if ( info->tx_active )
2252                        return 0;
2253                else
2254                        return HDLC_MAX_FRAME_SIZE;
2255        }
2256        
2257        return ret;
2258        
2259}        /* end of mgsl_write_room() */
2260
2261/* mgsl_chars_in_buffer()
2262 *
2263 *        Return the count of bytes in transmit buffer
2264 *         
2265 * Arguments:                tty        pointer to tty info structure
2266 * Return Value:        None
2267 */
2268static int mgsl_chars_in_buffer(struct tty_struct *tty)
2269{
2270        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2271                         
2272        if (debug_level >= DEBUG_LEVEL_INFO)
2273                printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2274                         __FILE__,__LINE__, info->device_name );
2275                         
2276        if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2277                return 0;
2278                
2279        if (debug_level >= DEBUG_LEVEL_INFO)
2280                printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2281                         __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2282                         
2283        if ( info->params.mode == MGSL_MODE_HDLC ||
2284                info->params.mode == MGSL_MODE_RAW ) {
2285                /* operating in synchronous (frame oriented) mode */
2286                if ( info->tx_active )
2287                        return info->max_frame_size;
2288                else
2289                        return 0;
2290        }
2291                         
2292        return info->xmit_cnt;
2293}        /* end of mgsl_chars_in_buffer() */
2294
2295/* mgsl_flush_buffer()
2296 *
2297 *        Discard all data in the send buffer
2298 *         
2299 * Arguments:                tty        pointer to tty info structure
2300 * Return Value:        None
2301 */
2302static void mgsl_flush_buffer(struct tty_struct *tty)
2303{
2304        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2305        unsigned long flags;
2306        
2307        if (debug_level >= DEBUG_LEVEL_INFO)
2308                printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2309                         __FILE__,__LINE__, info->device_name );
2310        
2311        if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2312                return;
2313                
2314        spin_lock_irqsave(&info->irq_spinlock,flags); 
2315        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2316        del_timer(&info->tx_timer);        
2317        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2318        
2319        tty_wakeup(tty);
2320}
2321
2322/* mgsl_send_xchar()
2323 *
2324 *        Send a high-priority XON/XOFF character
2325 *         
2326 * Arguments:                tty        pointer to tty info structure
2327 *                        ch        character to send
2328 * Return Value:        None
2329 */
2330static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2331{
2332        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2333        unsigned long flags;
2334
2335        if (debug_level >= DEBUG_LEVEL_INFO)
2336                printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2337                         __FILE__,__LINE__, info->device_name, ch );
2338                         
2339        if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2340                return;
2341
2342        info->x_char = ch;
2343        if (ch) {
2344                /* Make sure transmit interrupts are on */
2345                spin_lock_irqsave(&info->irq_spinlock,flags);
2346                if (!info->tx_enabled)
2347                         usc_start_transmitter(info);
2348                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2349        }
2350}        /* end of mgsl_send_xchar() */
2351
2352/* mgsl_throttle()
2353 * 
2354 *         Signal remote device to throttle send data (our receive data)
2355 *         
2356 * Arguments:                tty        pointer to tty info structure
2357 * Return Value:        None
2358 */
2359static void mgsl_throttle(struct tty_struct * tty)
2360{
2361        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2362        unsigned long flags;
2363        
2364        if (debug_level >= DEBUG_LEVEL_INFO)
2365                printk("%s(%d):mgsl_throttle(%s) entry\n",
2366                         __FILE__,__LINE__, info->device_name );
2367
2368        if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2369                return;
2370        
2371        if (I_IXOFF(tty))
2372                mgsl_send_xchar(tty, STOP_CHAR(tty));
2373 
2374         if (tty->termios->c_cflag & CRTSCTS) {
2375                spin_lock_irqsave(&info->irq_spinlock,flags);
2376                info->serial_signals &= ~SerialSignal_RTS;
2377                 usc_set_serial_signals(info);
2378                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2379        }
2380}        /* end of mgsl_throttle() */
2381
2382/* mgsl_unthrottle()
2383 * 
2384 *         Signal remote device to stop throttling send data (our receive data)
2385 *         
2386 * Arguments:                tty        pointer to tty info structure
2387 * Return Value:        None
2388 */
2389static void mgsl_unthrottle(struct tty_struct * tty)
2390{
2391        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2392        unsigned long flags;
2393        
2394        if (debug_level >= DEBUG_LEVEL_INFO)
2395                printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2396                         __FILE__,__LINE__, info->device_name );
2397
2398        if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2399                return;
2400        
2401        if (I_IXOFF(tty)) {
2402                if (info->x_char)
2403                        info->x_char = 0;
2404                else
2405                        mgsl_send_xchar(tty, START_CHAR(tty));
2406        }
2407        
2408         if (tty->termios->c_cflag & CRTSCTS) {
2409                spin_lock_irqsave(&info->irq_spinlock,flags);
2410                info->serial_signals |= SerialSignal_RTS;
2411                 usc_set_serial_signals(info);
2412                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2413        }
2414        
2415}        /* end of mgsl_unthrottle() */
2416
2417/* mgsl_get_stats()
2418 * 
2419 *         get the current serial parameters information
2420 *
2421 * Arguments:        info                pointer to device instance data
2422 *                 user_icount        pointer to buffer to hold returned stats
2423 *         
2424 * Return Value:        0 if success, otherwise error code
2425 */
2426static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2427{
2428        int err;
2429        
2430        if (debug_level >= DEBUG_LEVEL_INFO)
2431                printk("%s(%d):mgsl_get_params(%s)\n",
2432                         __FILE__,__LINE__, info->device_name);
2433                        
2434        if (!user_icount) {
2435                memset(&info->icount, 0, sizeof(info->icount));
2436        } else {
2437                COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2438                if (err)
2439                        return -EFAULT;
2440        }
2441        
2442        return 0;
2443        
2444}        /* end of mgsl_get_stats() */
2445
2446/* mgsl_get_params()
2447 * 
2448 *         get the current serial parameters information
2449 *
2450 * Arguments:        info                pointer to device instance data
2451 *                 user_params        pointer to buffer to hold returned params
2452 *         
2453 * Return Value:        0 if success, otherwise error code
2454 */
2455static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2456{
2457        int err;
2458        if (debug_level >= DEBUG_LEVEL_INFO)
2459                printk("%s(%d):mgsl_get_params(%s)\n",
2460                         __FILE__,__LINE__, info->device_name);
2461                        
2462        COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2463        if (err) {
2464                if ( debug_level >= DEBUG_LEVEL_INFO )
2465                        printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2466                                __FILE__,__LINE__,info->device_name);
2467                return -EFAULT;
2468        }
2469        
2470        return 0;
2471        
2472}        /* end of mgsl_get_params() */
2473
2474/* mgsl_set_params()
2475 * 
2476 *         set the serial parameters
2477 *         
2478 * Arguments:
2479 * 
2480 *         info                pointer to device instance data
2481 *         new_params        user buffer containing new serial params
2482 *
2483 * Return Value:        0 if success, otherwise error code
2484 */
2485static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2486{
2487         unsigned long flags;
2488        MGSL_PARAMS tmp_params;
2489        int err;
2490 
2491        if (debug_level >= DEBUG_LEVEL_INFO)
2492                printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2493                        info->device_name );
2494        COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2495        if (err) {
2496                if ( debug_level >= DEBUG_LEVEL_INFO )
2497                        printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2498                                __FILE__,__LINE__,info->device_name);
2499                return -EFAULT;
2500        }
2501        
2502        spin_lock_irqsave(&info->irq_spinlock,flags);
2503        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2504        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2505        
2506         mgsl_change_params(info);
2507        
2508        return 0;
2509        
2510}        /* end of mgsl_set_params() */
2511
2512/* mgsl_get_txidle()
2513 * 
2514 *         get the current transmit idle mode
2515 *
2516 * Arguments:        info                pointer to device instance data
2517 *                 idle_mode        pointer to buffer to hold returned idle mode
2518 *         
2519 * Return Value:        0 if success, otherwise error code
2520 */
2521static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2522{
2523        int err;
2524        
2525        if (debug_level >= DEBUG_LEVEL_INFO)
2526                printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2527                         __FILE__,__LINE__, info->device_name, info->idle_mode);
2528                        
2529        COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2530        if (err) {
2531                if ( debug_level >= DEBUG_LEVEL_INFO )
2532                        printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2533                                __FILE__,__LINE__,info->device_name);
2534                return -EFAULT;
2535        }
2536        
2537        return 0;
2538        
2539}        /* end of mgsl_get_txidle() */
2540
2541/* mgsl_set_txidle()        service ioctl to set transmit idle mode
2542 *         
2543 * Arguments:                 info                pointer to device instance data
2544 *                         idle_mode        new idle mode
2545 *
2546 * Return Value:        0 if success, otherwise error code
2547 */
2548static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2549{
2550         unsigned long flags;
2551 
2552        if (debug_level >= DEBUG_LEVEL_INFO)
2553                printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2554                        info->device_name, idle_mode );
2555                        
2556        spin_lock_irqsave(&info->irq_spinlock,flags);
2557        info->idle_mode = idle_mode;
2558        usc_set_txidle( info );
2559        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2560        return 0;
2561        
2562}        /* end of mgsl_set_txidle() */
2563
2564/* mgsl_txenable()
2565 * 
2566 *         enable or disable the transmitter
2567 *         
2568 * Arguments:
2569 * 
2570 *         info                pointer to device instance data
2571 *         enable                1 = enable, 0 = disable
2572 *
2573 * Return Value:        0 if success, otherwise error code
2574 */
2575static int mgsl_txenable(struct mgsl_struct * info, int enable)
2576{
2577         unsigned long flags;
2578 
2579        if (debug_level >= DEBUG_LEVEL_INFO)
2580                printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2581                        info->device_name, enable);
2582                        
2583        spin_lock_irqsave(&info->irq_spinlock,flags);
2584        if ( enable ) {
2585                if ( !info->tx_enabled ) {
2586
2587                        usc_start_transmitter(info);
2588                        /*--------------------------------------------------
2589                         * if HDLC/SDLC Loop mode, attempt to insert the
2590                         * station in the 'loop' by setting CMR:13. Upon
2591                         * receipt of the next GoAhead (RxAbort) sequence,
2592                         * the OnLoop indicator (CCSR:7) should go active
2593                         * to indicate that we are on the loop
2594                         *--------------------------------------------------*/
2595                        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2596                                usc_loopmode_insert_request( info );
2597                }
2598        } else {
2599                if ( info->tx_enabled )
2600                        usc_stop_transmitter(info);
2601        }
2602        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2603        return 0;
2604        
2605}        /* end of mgsl_txenable() */
2606
2607/* mgsl_txabort()        abort send HDLC frame
2608 *         
2609 * Arguments:                 info                pointer to device instance data
2610 * Return Value:        0 if success, otherwise error code
2611 */
2612static int mgsl_txabort(struct mgsl_struct * info)
2613{
2614         unsigned long flags;
2615 
2616        if (debug_level >= DEBUG_LEVEL_INFO)
2617                printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2618                        info->device_name);
2619                        
2620        spin_lock_irqsave(&info->irq_spinlock,flags);
2621        if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2622        {
2623                if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2624                        usc_loopmode_cancel_transmit( info );
2625                else
2626                        usc_TCmd(info,TCmd_SendAbort);
2627        }
2628        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2629        return 0;
2630        
2631}        /* end of mgsl_txabort() */
2632
2633/* mgsl_rxenable()         enable or disable the receiver
2634 *         
2635 * Arguments:                 info                pointer to device instance data
2636 *                         enable                1 = enable, 0 = disable
2637 * Return Value:        0 if success, otherwise error code
2638 */
2639static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2640{
2641         unsigned long flags;
2642 
2643        if (debug_level >= DEBUG_LEVEL_INFO)
2644                printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2645                        info->device_name, enable);
2646                        
2647        spin_lock_irqsave(&info->irq_spinlock,flags);
2648        if ( enable ) {
2649                if ( !info->rx_enabled )
2650                        usc_start_receiver(info);
2651        } else {
2652                if ( info->rx_enabled )
2653                        usc_stop_receiver(info);
2654        }
2655        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2656        return 0;
2657        
2658}        /* end of mgsl_rxenable() */
2659
2660/* mgsl_wait_event()         wait for specified event to occur
2661 *         
2662 * Arguments:                 info        pointer to device instance data
2663 *                         mask        pointer to bitmask of events to wait for
2664 * Return Value:        0         if successful and bit mask updated with
2665 *                                of events triggerred,
2666 *                         otherwise error code
2667 */
2668static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2669{
2670         unsigned long flags;
2671        int s;
2672        int rc=0;
2673        struct mgsl_icount cprev, cnow;
2674        int events;
2675        int mask;
2676        struct        _input_signal_events oldsigs, newsigs;
2677        DECLARE_WAITQUEUE(wait, current);
2678
2679        COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2680        if (rc) {
2681                return  -EFAULT;
2682        }
2683                 
2684        if (debug_level >= DEBUG_LEVEL_INFO)
2685                printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2686                        info->device_name, mask);
2687
2688        spin_lock_irqsave(&info->irq_spinlock,flags);
2689
2690        /* return immediately if state matches requested events */
2691        usc_get_serial_signals(info);
2692        s = info->serial_signals;
2693        events = mask &
2694                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2695                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2696                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2697                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2698        if (events) {
2699                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2700                goto exit;
2701        }
2702
2703        /* save current irq counts */
2704        cprev = info->icount;
2705        oldsigs = info->input_signal_events;
2706        
2707        /* enable hunt and idle irqs if needed */
2708        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2709                u16 oldreg = usc_InReg(info,RICR);
2710                u16 newreg = oldreg +
2711                         (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2712                         (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2713                if (oldreg != newreg)
2714                        usc_OutReg(info, RICR, newreg);
2715        }
2716        
2717        set_current_state(TASK_INTERRUPTIBLE);
2718        add_wait_queue(&info->event_wait_q, &wait);
2719        
2720        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2721        
2722
2723        for(;;) {
2724                schedule();
2725                if (signal_pending(current)) {
2726                        rc = -ERESTARTSYS;
2727                        break;
2728                }
2729                        
2730                /* get current irq counts */
2731                spin_lock_irqsave(&info->irq_spinlock,flags);
2732                cnow = info->icount;
2733                newsigs = info->input_signal_events;
2734                set_current_state(TASK_INTERRUPTIBLE);
2735                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2736
2737                /* if no change, wait aborted for some reason */
2738                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2739                    newsigs.dsr_down == oldsigs.dsr_down &&
2740                    newsigs.dcd_up   == oldsigs.dcd_up   &&
2741                    newsigs.dcd_down == oldsigs.dcd_down &&
2742                    newsigs.cts_up   == oldsigs.cts_up   &&
2743                    newsigs.cts_down == oldsigs.cts_down &&
2744                    newsigs.ri_up    == oldsigs.ri_up    &&
2745                    newsigs.ri_down  == oldsigs.ri_down  &&
2746                    cnow.exithunt    == cprev.exithunt   &&
2747                    cnow.rxidle      == cprev.rxidle) {
2748                        rc = -EIO;
2749                        break;
2750                }
2751
2752                events = mask &
2753                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2754                        (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2755                        (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2756                        (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2757                        (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2758                        (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2759                        (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2760                        (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2761                        (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2762                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2763                if (events)
2764                        break;
2765                
2766                cprev = cnow;
2767                oldsigs = newsigs;
2768        }
2769        
2770        remove_wait_queue(&info->event_wait_q, &wait);
2771        set_current_state(TASK_RUNNING);
2772
2773        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2774                spin_lock_irqsave(&info->irq_spinlock,flags);
2775                if (!waitqueue_active(&info->event_wait_q)) {
2776                        /* disable enable exit hunt mode/idle rcvd IRQs */
2777                        usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2778                                ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2779                }
2780                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2781        }
2782exit:
2783        if ( rc == 0 )
2784                PUT_USER(rc, events, mask_ptr);
2785                
2786        return rc;
2787        
2788}        /* end of mgsl_wait_event() */
2789
2790static int modem_input_wait(struct mgsl_struct *info,int arg)
2791{
2792         unsigned long flags;
2793        int rc;
2794        struct mgsl_icount cprev, cnow;
2795        DECLARE_WAITQUEUE(wait, current);
2796
2797        /* save current irq counts */
2798        spin_lock_irqsave(&info->irq_spinlock,flags);
2799        cprev = info->icount;
2800        add_wait_queue(&info->status_event_wait_q, &wait);
2801        set_current_state(TASK_INTERRUPTIBLE);
2802        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2803
2804        for(;;) {
2805                schedule();
2806                if (signal_pending(current)) {
2807                        rc = -ERESTARTSYS;
2808                        break;
2809                }
2810
2811                /* get new irq counts */
2812                spin_lock_irqsave(&info->irq_spinlock,flags);
2813                cnow = info->icount;
2814                set_current_state(TASK_INTERRUPTIBLE);
2815                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2816
2817                /* if no change, wait aborted for some reason */
2818                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2819                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2820                        rc = -EIO;
2821                        break;
2822                }
2823
2824                /* check for change in caller specified modem input */
2825                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2826                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2827                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2828                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2829                        rc = 0;
2830                        break;
2831                }
2832
2833                cprev = cnow;
2834        }
2835        remove_wait_queue(&info->status_event_wait_q, &wait);
2836        set_current_state(TASK_RUNNING);
2837        return rc;
2838}
2839
2840/* return the state of the serial control and status signals
2841 */
2842static int tiocmget(struct tty_struct *tty, struct file *file)
2843{
2844        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2845        unsigned int result;
2846         unsigned long flags;
2847
2848        spin_lock_irqsave(&info->irq_spinlock,flags);
2849         usc_get_serial_signals(info);
2850        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2851
2852        result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2853                ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2854                ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2855                ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2856                ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2857                ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2858
2859        if (debug_level >= DEBUG_LEVEL_INFO)
2860                printk("%s(%d):%s tiocmget() value=%08X\n",
2861                         __FILE__,__LINE__, info->device_name, result );
2862        return result;
2863}
2864
2865/* set modem control signals (DTR/RTS)
2866 */
2867static int tiocmset(struct tty_struct *tty, struct file *file,
2868                    unsigned int set, unsigned int clear)
2869{
2870        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2871         unsigned long flags;
2872
2873        if (debug_level >= DEBUG_LEVEL_INFO)
2874                printk("%s(%d):%s tiocmset(%x,%x)\n",
2875                        __FILE__,__LINE__,info->device_name, set, clear);
2876
2877        if (set & TIOCM_RTS)
2878                info->serial_signals |= SerialSignal_RTS;
2879        if (set & TIOCM_DTR)
2880                info->serial_signals |= SerialSignal_DTR;
2881        if (clear & TIOCM_RTS)
2882                info->serial_signals &= ~SerialSignal_RTS;
2883        if (clear & TIOCM_DTR)
2884                info->serial_signals &= ~SerialSignal_DTR;
2885
2886        spin_lock_irqsave(&info->irq_spinlock,flags);
2887         usc_set_serial_signals(info);
2888        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2889
2890        return 0;
2891}
2892
2893/* mgsl_break()                Set or clear transmit break condition
2894 *
2895 * Arguments:                tty                pointer to tty instance data
2896 *                        break_state        -1=set break condition, 0=clear
2897 * Return Value:        error code
2898 */
2899static int mgsl_break(struct tty_struct *tty, int break_state)
2900{
2901        struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2902        unsigned long flags;
2903        
2904        if (debug_level >= DEBUG_LEVEL_INFO)
2905                printk("%s(%d):mgsl_break(%s,%d)\n",
2906                         __FILE__,__LINE__, info->device_name, break_state);
2907                         
2908        if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2909                return -EINVAL;
2910
2911        spin_lock_irqsave(&info->irq_spinlock,flags);
2912         if (break_state == -1)
2913                usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2914        else 
2915                usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2916        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2917        return 0;
2918        
2919}        /* end of mgsl_break() */
2920
2921/* mgsl_ioctl()        Service an IOCTL request
2922 *         
2923 * Arguments:
2924 * 
2925 *         tty        pointer to tty instance data
2926 *         file        pointer to associated file object for device
2927 *         cmd        IOCTL command code
2928 *         arg        command argument/context
2929 *         
2930 * Return Value:        0 if success, otherwise error code
2931 */
2932static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2933                    unsigned int cmd, unsigned long arg)
2934{
2935        struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2936        int ret;
2937        
2938        if (debug_level >= DEBUG_LEVEL_INFO)
2939                printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2940                        info->device_name, cmd );
2941        
2942        if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2943                return -ENODEV;
2944
2945        if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2946            (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2947                if (tty->flags & (1 << TTY_IO_ERROR))
2948                    return -EIO;
2949        }
2950
2951        lock_kernel();
2952        ret = mgsl_ioctl_common(info, cmd, arg);
2953        unlock_kernel();
2954        return ret;
2955}
2956
2957static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2958{
2959        int error;
2960        struct mgsl_icount cnow;        /* kernel counter temps */
2961        void __user *argp = (void __user *)arg;
2962        struct serial_icounter_struct __user *p_cuser;        /* user space */
2963        unsigned long flags;
2964        
2965        switch (cmd) {
2966                case MGSL_IOCGPARAMS:
2967                        return mgsl_get_params(info, argp);
2968                case MGSL_IOCSPARAMS:
2969                        return mgsl_set_params(info, argp);
2970                case MGSL_IOCGTXIDLE:
2971                        return mgsl_get_txidle(info, argp);
2972                case MGSL_IOCSTXIDLE:
2973                        return mgsl_set_txidle(info,(int)arg);
2974                case MGSL_IOCTXENABLE:
2975                        return mgsl_txenable(info,(int)arg);
2976                case MGSL_IOCRXENABLE:
2977                        return mgsl_rxenable(info,(int)arg);
2978                case MGSL_IOCTXABORT:
2979                        return mgsl_txabort(info);
2980                case MGSL_IOCGSTATS:
2981                        return mgsl_get_stats(info, argp);
2982                case MGSL_IOCWAITEVENT:
2983                        return mgsl_wait_event(info, argp);
2984                case MGSL_IOCLOOPTXDONE:
2985                        return mgsl_loopmode_send_done(info);
2986                /* Wait for modem input (DCD,RI,DSR,CTS) change
2987                 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2988                 */
2989                case TIOCMIWAIT:
2990                        return modem_input_wait(info,(int)arg);
2991
2992                /* 
2993                 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2994                 * Return: write counters to the user passed counter struct
2995                 * NB: both 1->0 and 0->1 transitions are counted except for
2996                 *     RI where only 0->1 is counted.
2997                 */
2998                case TIOCGICOUNT:
2999                        spin_lock_irqsave(&info->irq_spinlock,flags);
3000                        cnow = info->icount;
3001                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3002                        p_cuser = argp;
3003                        PUT_USER(error,cnow.cts, &p_cuser->cts);
3004                        if (error) return error;
3005                        PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3006                        if (error) return error;
3007                        PUT_USER(error,cnow.rng, &p_cuser->rng);
3008                        if (error) return error;
3009                        PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3010                        if (error) return error;
3011                        PUT_USER(error,cnow.rx, &p_cuser->rx);
3012                        if (error) return error;
3013                        PUT_USER(error,cnow.tx, &p_cuser->tx);
3014                        if (error) return error;
3015                        PUT_USER(error,cnow.frame, &p_cuser->frame);
3016                        if (error) return error;
3017                        PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3018                        if (error) return error;
3019                        PUT_USER(error,cnow.parity, &p_cuser->parity);
3020                        if (error) return error;
3021                        PUT_USER(error,cnow.brk, &p_cuser->brk);
3022                        if (error) return error;
3023                        PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3024                        if (error) return error;
3025                        return 0;
3026                default:
3027                        return -ENOIOCTLCMD;
3028        }
3029        return 0;
3030}
3031
3032/* mgsl_set_termios()
3033 * 
3034 *         Set new termios settings
3035 *         
3036 * Arguments:
3037 * 
3038 *         tty                pointer to tty structure
3039 *         termios                pointer to buffer to hold returned old termios
3040 *         
3041 * Return Value:                None
3042 */
3043static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3044{
3045        struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3046        unsigned long flags;
3047        
3048        if (debug_level >= DEBUG_LEVEL_INFO)
3049                printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3050                        tty->driver->name );
3051        
3052        mgsl_change_params(info);
3053
3054        /* Handle transition to B0 status */
3055        if (old_termios->c_cflag & CBAUD &&
3056            !(tty->termios->c_cflag & CBAUD)) {
3057                info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3058                spin_lock_irqsave(&info->irq_spinlock,flags);
3059                 usc_set_serial_signals(info);
3060                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3061        }
3062        
3063        /* Handle transition away from B0 status */
3064        if (!(old_termios->c_cflag & CBAUD) &&
3065            tty->termios->c_cflag & CBAUD) {
3066                info->serial_signals |= SerialSignal_DTR;
3067                 if (!(tty->termios->c_cflag & CRTSCTS) || 
3068                     !test_bit(TTY_THROTTLED, &tty->flags)) {
3069                        info->serial_signals |= SerialSignal_RTS;
3070                 }
3071                spin_lock_irqsave(&info->irq_spinlock,flags);
3072                 usc_set_serial_signals(info);
3073                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3074        }
3075        
3076        /* Handle turning off CRTSCTS */
3077        if (old_termios->c_cflag & CRTSCTS &&
3078            !(tty->termios->c_cflag & CRTSCTS)) {
3079                tty->hw_stopped = 0;
3080                mgsl_start(tty);
3081        }
3082
3083}        /* end of mgsl_set_termios() */
3084
3085/* mgsl_close()
3086 * 
3087 *         Called when port is closed. Wait for remaining data to be
3088 *         sent. Disable port and free resources.
3089 *         
3090 * Arguments:
3091 * 
3092 *         tty        pointer to open tty structure
3093 *         filp        pointer to open file object
3094 *         
3095 * Return Value:        None
3096 */
3097static void mgsl_close(struct tty_struct *tty, struct file * filp)
3098{
3099        struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3100
3101        if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3102                return;
3103        
3104        if (debug_level >= DEBUG_LEVEL_INFO)
3105                printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3106                         __FILE__,__LINE__, info->device_name, info->port.count);
3107                         
3108        if (!info->port.count)
3109                return;
3110
3111        if (tty_hung_up_p(filp))
3112                goto cleanup;
3113                        
3114        if ((tty->count == 1) && (info->port.count != 1)) {
3115                /*
3116                 * tty->count is 1 and the tty structure will be freed.
3117                 * info->port.count should be one in this case.
3118                 * if it's not, correct it so that the port is shutdown.
3119                 */
3120                printk("mgsl_close: bad refcount; tty->count is 1, "
3121                       "info->port.count is %d\n", info->port.count);
3122                info->port.count = 1;
3123        }
3124        
3125        info->port.count--;
3126        
3127        /* if at least one open remaining, leave hardware active */
3128        if (info->port.count)
3129                goto cleanup;
3130        
3131        info->port.flags |= ASYNC_CLOSING;
3132        
3133        /* set tty->closing to notify line discipline to 
3134         * only process XON/XOFF characters. Only the N_TTY
3135         * discipline appears to use this (ppp does not).
3136         */
3137        tty->closing = 1;
3138        
3139        /* wait for transmit data to clear all layers */
3140        
3141        if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3142                if (debug_level >= DEBUG_LEVEL_INFO)
3143                        printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3144                                 __FILE__,__LINE__, info->device_name );
3145                tty_wait_until_sent(tty, info->port.closing_wait);
3146        }
3147                
3148         if (info->port.flags & ASYNC_INITIALIZED)
3149                 mgsl_wait_until_sent(tty, info->timeout);
3150
3151        mgsl_flush_buffer(tty);
3152
3153        tty_ldisc_flush(tty);
3154                
3155        shutdown(info);
3156        
3157        tty->closing = 0;
3158        info->port.tty = NULL;
3159        
3160        if (info->port.blocked_open) {
3161                if (info->port.close_delay) {
3162                        msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
3163                }
3164                wake_up_interruptible(&info->port.open_wait);
3165        }
3166        
3167        info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3168                         
3169        wake_up_interruptible(&info->port.close_wait);
3170        
3171cleanup:                        
3172        if (debug_level >= DEBUG_LEVEL_INFO)
3173                printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3174                        tty->driver->name, info->port.count);
3175                        
3176}        /* end of mgsl_close() */
3177
3178/* mgsl_wait_until_sent()
3179 *
3180 *        Wait until the transmitter is empty.
3181 *
3182 * Arguments:
3183 *
3184 *        tty                pointer to tty info structure
3185 *        timeout                time to wait for send completion
3186 *
3187 * Return Value:        None
3188 */
3189static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3190{
3191        struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3192        unsigned long orig_jiffies, char_time;
3193
3194        if (!info )
3195                return;
3196
3197        if (debug_level >= DEBUG_LEVEL_INFO)
3198                printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3199                         __FILE__,__LINE__, info->device_name );
3200      
3201        if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3202                return;
3203
3204        if (!(info->port.flags & ASYNC_INITIALIZED))
3205                goto exit;
3206         
3207        orig_jiffies = jiffies;
3208      
3209        /* Set check interval to 1/5 of estimated time to
3210         * send a character, and make it at least 1. The check
3211         * interval should also be less than the timeout.
3212         * Note: use tight timings here to satisfy the NIST-PCTS.
3213         */ 
3214
3215        lock_kernel();
3216        if ( info->params.data_rate ) {
3217                       char_time = info->timeout/(32 * 5);
3218                if (!char_time)
3219                        char_time++;
3220        } else
3221                char_time = 1;
3222                
3223        if (timeout)
3224                char_time = min_t(unsigned long, char_time, timeout);
3225                
3226        if ( info->params.mode == MGSL_MODE_HDLC ||
3227                info->params.mode == MGSL_MODE_RAW ) {
3228                while (info->tx_active) {
3229                        msleep_interruptible(jiffies_to_msecs(char_time));
3230                        if (signal_pending(current))
3231                                break;
3232                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
3233                                break;
3234                }
3235        } else {
3236                while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3237                        info->tx_enabled) {
3238                        msleep_interruptible(jiffies_to_msecs(char_time));
3239                        if (signal_pending(current))
3240                                break;
3241                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
3242                                break;
3243                }
3244        }
3245        unlock_kernel();
3246      
3247exit:
3248        if (debug_level >= DEBUG_LEVEL_INFO)
3249                printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3250                         __FILE__,__LINE__, info->device_name );
3251                         
3252}        /* end of mgsl_wait_until_sent() */
3253
3254/* mgsl_hangup()
3255 *
3256 *        Called by tty_hangup() when a hangup is signaled.
3257 *        This is the same as to closing all open files for the port.
3258 *
3259 * Arguments:                tty        pointer to associated tty object
3260 * Return Value:        None
3261 */
3262static void mgsl_hangup(struct tty_struct *tty)
3263{
3264        struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3265        
3266        if (debug_level >= DEBUG_LEVEL_INFO)
3267                printk("%s(%d):mgsl_hangup(%s)\n",
3268                         __FILE__,__LINE__, info->device_name );
3269                         
3270        if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3271                return;
3272
3273        mgsl_flush_buffer(tty);
3274        shutdown(info);
3275        
3276        info->port.count = 0;        
3277        info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3278        info->port.tty = NULL;
3279
3280        wake_up_interruptible(&info->port.open_wait);
3281        
3282}        /* end of mgsl_hangup() */
3283
3284/* block_til_ready()
3285 * 
3286 *         Block the current process until the specified port
3287 *         is ready to be opened.
3288 *         
3289 * Arguments:
3290 * 
3291 *         tty                pointer to tty info structure
3292 *         filp                pointer to open file object
3293 *         info                pointer to device instance data
3294 *         
3295 * Return Value:        0 if success, otherwise error code
3296 */
3297static int block_til_ready(struct tty_struct *tty, struct file * filp,
3298                           struct mgsl_struct *info)
3299{
3300        DECLARE_WAITQUEUE(wait, current);
3301        int                retval;
3302        bool                do_clocal = false;
3303        bool                extra_count = false;
3304        unsigned long        flags;
3305        
3306        if (debug_level >= DEBUG_LEVEL_INFO)
3307                printk("%s(%d):block_til_ready on %s\n",
3308                         __FILE__,__LINE__, tty->driver->name );
3309
3310        if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3311                /* nonblock mode is set or port is not enabled */
3312                info->port.flags |= ASYNC_NORMAL_ACTIVE;
3313                return 0;
3314        }
3315
3316        if (tty->termios->c_cflag & CLOCAL)
3317                do_clocal = true;
3318
3319        /* Wait for carrier detect and the line to become
3320         * free (i.e., not in use by the callout).  While we are in
3321         * this loop, info->port.count is dropped by one, so that
3322         * mgsl_close() knows when to free things.  We restore it upon
3323         * exit, either normal or abnormal.
3324         */
3325         
3326        retval = 0;
3327        add_wait_queue(&info->port.open_wait, &wait);
3328        
3329        if (debug_level >= DEBUG_LEVEL_INFO)
3330                printk("%s(%d):block_til_ready before block on %s count=%d\n",
3331                         __FILE__,__LINE__, tty->driver->name, info->port.count );
3332
3333        spin_lock_irqsave(&info->irq_spinlock, flags);
3334        if (!tty_hung_up_p(filp)) {
3335                extra_count = true;
3336                info->port.count--;
3337        }
3338        spin_unlock_irqrestore(&info->irq_spinlock, flags);
3339        info->port.blocked_open++;
3340        
3341        while (1) {
3342                if (tty->termios->c_cflag & CBAUD) {
3343                        spin_lock_irqsave(&info->irq_spinlock,flags);
3344                        info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3345                         usc_set_serial_signals(info);
3346                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3347                }
3348                
3349                set_current_state(TASK_INTERRUPTIBLE);
3350                
3351                if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3352                        retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3353                                        -EAGAIN : -ERESTARTSYS;
3354                        break;
3355                }
3356                
3357                spin_lock_irqsave(&info->irq_spinlock,flags);
3358                 usc_get_serial_signals(info);
3359                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3360                
3361                 if (!(info->port.flags & ASYNC_CLOSING) &&
3362                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3363                         break;
3364                }
3365                        
3366                if (signal_pending(current)) {
3367                        retval = -ERESTARTSYS;
3368                        break;
3369                }
3370                
3371                if (debug_level >= DEBUG_LEVEL_INFO)
3372                        printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3373                                 __FILE__,__LINE__, tty->driver->name, info->port.count );
3374                                 
3375                schedule();
3376        }
3377        
3378        set_current_state(TASK_RUNNING);
3379        remove_wait_queue(&info->port.open_wait, &wait);
3380        
3381        if (extra_count)
3382                info->port.count++;
3383        info->port.blocked_open--;
3384        
3385        if (debug_level >= DEBUG_LEVEL_INFO)
3386                printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3387                         __FILE__,__LINE__, tty->driver->name, info->port.count );
3388                         
3389        if (!retval)
3390                info->port.flags |= ASYNC_NORMAL_ACTIVE;
3391                
3392        return retval;
3393        
3394}        /* end of block_til_ready() */
3395
3396/* mgsl_open()
3397 *
3398 *        Called when a port is opened.  Init and enable port.
3399 *        Perform serial-specific initialization for the tty structure.
3400 *
3401 * Arguments:                tty        pointer to tty info structure
3402 *                        filp        associated file pointer
3403 *
3404 * Return Value:        0 if success, otherwise error code
3405 */
3406static int mgsl_open(struct tty_struct *tty, struct file * filp)
3407{
3408        struct mgsl_struct        *info;
3409        int                         retval, line;
3410        unsigned long flags;
3411
3412        /* verify range of specified line number */        
3413        line = tty->index;
3414        if ((line < 0) || (line >= mgsl_device_count)) {
3415                printk("%s(%d):mgsl_open with invalid line #%d.\n",
3416                        __FILE__,__LINE__,line);
3417                return -ENODEV;
3418        }
3419
3420        /* find the info structure for the specified line */
3421        info = mgsl_device_list;
3422        while(info && info->line != line)
3423                info = info->next_device;
3424        if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3425                return -ENODEV;
3426        
3427        tty->driver_data = info;
3428        info->port.tty = tty;
3429                
3430        if (debug_level >= DEBUG_LEVEL_INFO)
3431                printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3432                         __FILE__,__LINE__,tty->driver->name, info->port.count);
3433
3434        /* If port is closing, signal caller to try again */
3435        if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3436                if (info->port.flags & ASYNC_CLOSING)
3437                        interruptible_sleep_on(&info->port.close_wait);
3438                retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3439                        -EAGAIN : -ERESTARTSYS);
3440                goto cleanup;
3441        }
3442        
3443        info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3444
3445        spin_lock_irqsave(&info->netlock, flags);
3446        if (info->netcount) {
3447                retval = -EBUSY;
3448                spin_unlock_irqrestore(&info->netlock, flags);
3449                goto cleanup;
3450        }
3451        info->port.count++;
3452        spin_unlock_irqrestore(&info->netlock, flags);
3453
3454        if (info->port.count == 1) {
3455                /* 1st open on this device, init hardware */
3456                retval = startup(info);
3457                if (retval < 0)
3458                        goto cleanup;
3459        }
3460
3461        retval = block_til_ready(tty, filp, info);
3462        if (retval) {
3463                if (debug_level >= DEBUG_LEVEL_INFO)
3464                        printk("%s(%d):block_til_ready(%s) returned %d\n",
3465                                 __FILE__,__LINE__, info->device_name, retval);
3466                goto cleanup;
3467        }
3468
3469        if (debug_level >= DEBUG_LEVEL_INFO)
3470                printk("%s(%d):mgsl_open(%s) success\n",
3471                         __FILE__,__LINE__, info->device_name);
3472        retval = 0;
3473        
3474cleanup:                        
3475        if (retval) {
3476                if (tty->count == 1)
3477                        info->port.tty = NULL; /* tty layer will release tty struct */
3478                if(info->port.count)
3479                        info->port.count--;
3480        }
3481        
3482        return retval;
3483        
3484}        /* end of mgsl_open() */
3485
3486/*
3487 * /proc fs routines....
3488 */
3489
3490static inline int line_info(char *buf, struct mgsl_struct *info)
3491{
3492        char        stat_buf[30];
3493        int        ret;
3494        unsigned long flags;
3495
3496        if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3497                ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3498                        info->device_name, info->io_base, info->irq_level,
3499                        info->phys_memory_base, info->phys_lcr_base);
3500        } else {
3501                ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3502                        info->device_name, info->io_base, 
3503                        info->irq_level, info->dma_level);
3504        }
3505
3506        /* output current serial signal states */
3507        spin_lock_irqsave(&info->irq_spinlock,flags);
3508         usc_get_serial_signals(info);
3509        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3510        
3511        stat_buf[0] = 0;
3512        stat_buf[1] = 0;
3513        if (info->serial_signals & SerialSignal_RTS)
3514                strcat(stat_buf, "|RTS");
3515        if (info->serial_signals & SerialSignal_CTS)
3516                strcat(stat_buf, "|CTS");
3517        if (info->serial_signals & SerialSignal_DTR)
3518                strcat(stat_buf, "|DTR");
3519        if (info->serial_signals & SerialSignal_DSR)
3520                strcat(stat_buf, "|DSR");
3521        if (info->serial_signals & SerialSignal_DCD)
3522                strcat(stat_buf, "|CD");
3523        if (info->serial_signals & SerialSignal_RI)
3524                strcat(stat_buf, "|RI");
3525
3526        if (info->params.mode == MGSL_MODE_HDLC ||
3527            info->params.mode == MGSL_MODE_RAW ) {
3528                ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3529                              info->icount.txok, info->icount.rxok);
3530                if (info->icount.txunder)
3531                        ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3532                if (info->icount.txabort)
3533                        ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3534                if (info->icount.rxshort)
3535                        ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);        
3536                if (info->icount.rxlong)
3537                        ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3538                if (info->icount.rxover)
3539                        ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3540                if (info->icount.rxcrc)
3541                        ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3542        } else {
3543                ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3544                              info->icount.tx, info->icount.rx);
3545                if (info->icount.frame)
3546                        ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3547                if (info->icount.parity)
3548                        ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3549                if (info->icount.brk)
3550                        ret += sprintf(buf+ret, " brk:%d", info->icount.brk);        
3551                if (info->icount.overrun)
3552                        ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3553        }
3554        
3555        /* Append serial signal status to end */
3556        ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3557        
3558        ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3559         info->tx_active,info->bh_requested,info->bh_running,
3560         info->pending_bh);
3561         
3562        spin_lock_irqsave(&info->irq_spinlock,flags);
3563        {        
3564        u16 Tcsr = usc_InReg( info, TCSR );
3565        u16 Tdmr = usc_InDmaReg( info, TDMR );
3566        u16 Ticr = usc_InReg( info, TICR );
3567        u16 Rscr = usc_InReg( info, RCSR );
3568        u16 Rdmr = usc_InDmaReg( info, RDMR );
3569        u16 Ricr = usc_InReg( info, RICR );
3570        u16 Icr = usc_InReg( info, ICR );
3571        u16 Dccr = usc_InReg( info, DCCR );
3572        u16 Tmr = usc_InReg( info, TMR );
3573        u16 Tccr = usc_InReg( info, TCCR );
3574        u16 Ccar = inw( info->io_base + CCAR );
3575        ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3576                        "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3577                         Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3578        }
3579        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3580        
3581        return ret;
3582        
3583}        /* end of line_info() */
3584
3585/* mgsl_read_proc()
3586 * 
3587 * Called to print information about devices
3588 * 
3589 * Arguments:
3590 *         page        page of memory to hold returned info
3591 *         start        
3592 *         off
3593 *         count
3594 *         eof
3595 *         data
3596 *         
3597 * Return Value:
3598 */
3599static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3600                 int *eof, void *data)
3601{
3602        int len = 0, l;
3603        off_t        begin = 0;
3604        struct mgsl_struct *info;
3605        
3606        len += sprintf(page, "synclink driver:%s\n", driver_version);
3607        
3608        info = mgsl_device_list;
3609        while( info ) {
3610                l = line_info(page + len, info);
3611                len += l;
3612                if (len+begin > off+count)
3613                        goto done;
3614                if (len+begin < off) {
3615                        begin += len;
3616                        len = 0;
3617                }
3618                info = info->next_device;
3619        }
3620
3621        *eof = 1;
3622done:
3623        if (off >= len+begin)
3624                return 0;
3625        *start = page + (off-begin);
3626        return ((count < begin+len-off) ? count : begin+len-off);
3627        
3628}        /* end of mgsl_read_proc() */
3629
3630/* mgsl_allocate_dma_buffers()
3631 * 
3632 *         Allocate and format DMA buffers (ISA adapter)
3633 *         or format shared memory buffers (PCI adapter).
3634 * 
3635 * Arguments:                info        pointer to device instance data
3636 * Return Value:        0 if success, otherwise error
3637 */
3638static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3639{
3640        unsigned short BuffersPerFrame;
3641
3642        info->last_mem_alloc = 0;
3643
3644        /* Calculate the number of DMA buffers necessary to hold the */
3645        /* largest allowable frame size. Note: If the max frame size is */
3646        /* not an even multiple of the DMA buffer size then we need to */
3647        /* round the buffer count per frame up one. */
3648
3649        BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3650        if ( info->max_frame_size % DMABUFFERSIZE )
3651                BuffersPerFrame++;
3652
3653        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3654                /*
3655                 * The PCI adapter has 256KBytes of shared memory to use.
3656                 * This is 64 PAGE_SIZE buffers.
3657                 *
3658                 * The first page is used for padding at this time so the
3659                 * buffer list does not begin at offset 0 of the PCI
3660                 * adapter's shared memory.
3661                 *
3662                 * The 2nd page is used for the buffer list. A 4K buffer
3663                 * list can hold 128 DMA_BUFFER structures at 32 bytes
3664                 * each.
3665                 *
3666                 * This leaves 62 4K pages.
3667                 *
3668                 * The next N pages are used for transmit frame(s). We
3669                 * reserve enough 4K page blocks to hold the required
3670                 * number of transmit dma buffers (num_tx_dma_buffers),
3671                 * each of MaxFrameSize size.
3672                 *
3673                 * Of the remaining pages (62-N), determine how many can
3674                 * be used to receive full MaxFrameSize inbound frames
3675                 */
3676                info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3677                info->rx_buffer_count = 62 - info->tx_buffer_count;
3678        } else {
3679                /* Calculate the number of PAGE_SIZE buffers needed for */
3680                /* receive and transmit DMA buffers. */
3681
3682
3683                /* Calculate the number of DMA buffers necessary to */
3684                /* hold 7 max size receive frames and one max size transmit frame. */
3685                /* The receive buffer count is bumped by one so we avoid an */
3686                /* End of List condition if all receive buffers are used when */
3687                /* using linked list DMA buffers. */
3688
3689                info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3690                info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3691                
3692                /* 
3693                 * limit total TxBuffers & RxBuffers to 62 4K total 
3694                 * (ala PCI Allocation) 
3695                 */
3696                
3697                if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3698                        info->rx_buffer_count = 62 - info->tx_buffer_count;
3699
3700        }
3701
3702        if ( debug_level >= DEBUG_LEVEL_INFO )
3703                printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3704                        __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3705        
3706        if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3707                  mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 || 
3708                  mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 || 
3709                  mgsl_alloc_intermediate_rxbuffer_memory(info) < 0  ||
3710                  mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3711                printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3712                return -ENOMEM;
3713        }
3714        
3715        mgsl_reset_rx_dma_buffers( info );
3716          mgsl_reset_tx_dma_buffers( info );
3717
3718        return 0;
3719
3720}        /* end of mgsl_allocate_dma_buffers() */
3721
3722/*
3723 * mgsl_alloc_buffer_list_memory()
3724 * 
3725 * Allocate a common DMA buffer for use as the
3726 * receive and transmit buffer lists.
3727 * 
3728 * A buffer list is a set of buffer entries where each entry contains
3729 * a pointer to an actual buffer and a pointer to the next buffer entry
3730 * (plus some other info about the buffer).
3731 * 
3732 * The buffer entries for a list are built to form a circular list so
3733 * that when the entire list has been traversed you start back at the
3734 * beginning.
3735 * 
3736 * This function allocates memory for just the buffer entries.
3737 * The links (pointer to next entry) are filled in with the physical
3738 * address of the next entry so the adapter can navigate the list
3739 * using bus master DMA. The pointers to the actual buffers are filled
3740 * out later when the actual buffers are allocated.
3741 * 
3742 * Arguments:                info        pointer to device instance data
3743 * Return Value:        0 if success, otherwise error
3744 */
3745static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3746{
3747        unsigned int i;
3748
3749        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3750                /* PCI adapter uses shared memory. */
3751                info->buffer_list = info->memory_base + info->last_mem_alloc;
3752                info->buffer_list_phys = info->last_mem_alloc;
3753                info->last_mem_alloc += BUFFERLISTSIZE;
3754        } else {
3755                /* ISA adapter uses system memory. */
3756                /* The buffer lists are allocated as a common buffer that both */
3757                /* the processor and adapter can access. This allows the driver to */
3758                /* inspect portions of the buffer while other portions are being */
3759                /* updated by the adapter using Bus Master DMA. */
3760
3761                info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3762                if (info->buffer_list == NULL)
3763                        return -ENOMEM;
3764                info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3765        }
3766
3767        /* We got the memory for the buffer entry lists. */
3768        /* Initialize the memory block to all zeros. */
3769        memset( info->buffer_list, 0, BUFFERLISTSIZE );
3770
3771        /* Save virtual address pointers to the receive and */
3772        /* transmit buffer lists. (Receive 1st). These pointers will */
3773        /* be used by the processor to access the lists. */
3774        info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3775        info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3776        info->tx_buffer_list += info->rx_buffer_count;
3777
3778        /*
3779         * Build the links for the buffer entry lists such that
3780         * two circular lists are built. (Transmit and Receive).
3781         *
3782         * Note: the links are physical addresses
3783         * which are read by the adapter to determine the next
3784         * buffer entry to use.
3785         */
3786
3787        for ( i = 0; i < info->rx_buffer_count; i++ ) {
3788                /* calculate and store physical address of this buffer entry */
3789                info->rx_buffer_list[i].phys_entry =
3790                        info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3791
3792                /* calculate and store physical address of */
3793                /* next entry in cirular list of entries */
3794
3795                info->rx_buffer_list[i].link = info->buffer_list_phys;
3796
3797                if ( i < info->rx_buffer_count - 1 )
3798                        info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3799        }
3800
3801        for ( i = 0; i < info->tx_buffer_count; i++ ) {
3802                /* calculate and store physical address of this buffer entry */
3803                info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3804                        ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3805
3806                /* calculate and store physical address of */
3807                /* next entry in cirular list of entries */
3808
3809                info->tx_buffer_list[i].link = info->buffer_list_phys +
3810                        info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3811
3812                if ( i < info->tx_buffer_count - 1 )
3813                        info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3814        }
3815
3816        return 0;
3817
3818}        /* end of mgsl_alloc_buffer_list_memory() */
3819
3820/* Free DMA buffers allocated for use as the
3821 * receive and transmit buffer lists.
3822 * Warning:
3823 * 
3824 *         The data transfer buffers associated with the buffer list
3825 *         MUST be freed before freeing the buffer list itself because
3826 *         the buffer list contains the information necessary to free
3827 *         the individual buffers!
3828 */
3829static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3830{
3831        if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3832                dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3833                
3834        info->buffer_list = NULL;
3835        info->rx_buffer_list = NULL;
3836        info->tx_buffer_list = NULL;
3837
3838}        /* end of mgsl_free_buffer_list_memory() */
3839
3840/*
3841 * mgsl_alloc_frame_memory()
3842 * 
3843 *         Allocate the frame DMA buffers used by the specified buffer list.
3844 *         Each DMA buffer will be one memory page in size. This is necessary
3845 *         because memory can fragment enough that it may be impossible
3846 *         contiguous pages.
3847 * 
3848 * Arguments:
3849 * 
3850 *        info                pointer to device instance data
3851 *         BufferList        pointer to list of buffer entries
3852 *         Buffercount        count of buffer entries in buffer list
3853 * 
3854 * Return Value:        0 if success, otherwise -ENOMEM
3855 */
3856static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3857{
3858        int i;
3859        u32 phys_addr;
3860
3861        /* Allocate page sized buffers for the receive buffer list */
3862
3863        for ( i = 0; i < Buffercount; i++ ) {
3864                if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3865                        /* PCI adapter uses shared memory buffers. */
3866                        BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3867                        phys_addr = info->last_mem_alloc;
3868                        info->last_mem_alloc += DMABUFFERSIZE;
3869                } else {
3870                        /* ISA adapter uses system memory. */
3871                        BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3872                        if (BufferList[i].virt_addr == NULL)
3873                                return -ENOMEM;
3874                        phys_addr = (u32)(BufferList[i].dma_addr);
3875                }
3876                BufferList[i].phys_addr = phys_addr;
3877        }
3878
3879        return 0;
3880
3881}        /* end of mgsl_alloc_frame_memory() */
3882
3883/*
3884 * mgsl_free_frame_memory()
3885 * 
3886 *         Free the buffers associated with
3887 *         each buffer entry of a buffer list.
3888 * 
3889 * Arguments:
3890 * 
3891 *        info                pointer to device instance data
3892 *         BufferList        pointer to list of buffer entries
3893 *         Buffercount        count of buffer entries in buffer list
3894 * 
3895 * Return Value:        None
3896 */
3897static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3898{
3899        int i;
3900
3901        if ( BufferList ) {
3902                for ( i = 0 ; i < Buffercount ; i++ ) {
3903                        if ( BufferList[i].virt_addr ) {
3904                                if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3905                                        dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3906                                BufferList[i].virt_addr = NULL;
3907                        }
3908                }
3909        }
3910
3911}        /* end of mgsl_free_frame_memory() */
3912
3913/* mgsl_free_dma_buffers()
3914 * 
3915 *         Free DMA buffers
3916 *         
3917 * Arguments:                info        pointer to device instance data
3918 * Return Value:        None
3919 */
3920static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3921{
3922        mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3923        mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3924        mgsl_free_buffer_list_memory( info );
3925
3926}        /* end of mgsl_free_dma_buffers() */
3927
3928
3929/*
3930 * mgsl_alloc_intermediate_rxbuffer_memory()
3931 * 
3932 *         Allocate a buffer large enough to hold max_frame_size. This buffer
3933 *        is used to pass an assembled frame to the line discipline.
3934 * 
3935 * Arguments:
3936 * 
3937 *        info                pointer to device instance data
3938 * 
3939 * Return Value:        0 if success, otherwise -ENOMEM
3940 */
3941static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3942{
3943        info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3944        if ( info->intermediate_rxbuffer == NULL )
3945                return -ENOMEM;
3946
3947        return 0;
3948
3949}        /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3950
3951/*
3952 * mgsl_free_intermediate_rxbuffer_memory()
3953 * 
3954 * 
3955 * Arguments:
3956 * 
3957 *        info                pointer to device instance data
3958 * 
3959 * Return Value:        None
3960 */
3961static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3962{
3963        kfree(info->intermediate_rxbuffer);
3964        info->intermediate_rxbuffer = NULL;
3965
3966}        /* end of mgsl_free_intermediate_rxbuffer_memory() */
3967
3968/*
3969 * mgsl_alloc_intermediate_txbuffer_memory()
3970 *
3971 *         Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3972 *         This buffer is used to load transmit frames into the adapter's dma transfer
3973 *         buffers when there is sufficient space.
3974 *
3975 * Arguments:
3976 *
3977 *        info                pointer to device instance data
3978 *
3979 * Return Value:        0 if success, otherwise -ENOMEM
3980 */
3981static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3982{
3983        int i;
3984
3985        if ( debug_level >= DEBUG_LEVEL_INFO )
3986                printk("%s %s(%d)  allocating %d tx holding buffers\n",
3987                                info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3988
3989        memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3990
3991        for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3992                info->tx_holding_buffers[i].buffer =
3993                        kmalloc(info->max_frame_size, GFP_KERNEL);
3994                if (info->tx_holding_buffers[i].buffer == NULL) {
3995                        for (--i; i >= 0; i--) {
3996                                kfree(info->tx_holding_buffers[i].buffer);
3997                                info->tx_holding_buffers[i].buffer = NULL;
3998                        }
3999                        return -ENOMEM;
4000                }
4001        }
4002
4003        return 0;
4004
4005}        /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4006
4007/*
4008 * mgsl_free_intermediate_txbuffer_memory()
4009 *
4010 *
4011 * Arguments:
4012 *
4013 *        info                pointer to device instance data
4014 *
4015 * Return Value:        None
4016 */
4017static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4018{
4019        int i;
4020
4021        for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4022                kfree(info->tx_holding_buffers[i].buffer);
4023                info->tx_holding_buffers[i].buffer = NULL;
4024        }
4025
4026        info->get_tx_holding_index = 0;
4027        info->put_tx_holding_index = 0;
4028        info->tx_holding_count = 0;
4029
4030}        /* end of mgsl_free_intermediate_txbuffer_memory() */
4031
4032
4033/*
4034 * load_next_tx_holding_buffer()
4035 *
4036 * attempts to load the next buffered tx request into the
4037 * tx dma buffers
4038 *
4039 * Arguments:
4040 *
4041 *        info                pointer to device instance data
4042 *
4043 * Return Value:        true if next buffered tx request loaded
4044 *                         into adapter's tx dma buffer,
4045 *                         false otherwise
4046 */
4047static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4048{
4049        bool ret = false;
4050
4051        if ( info->tx_holding_count ) {
4052                /* determine if we have enough tx dma buffers
4053                 * to accommodate the next tx frame
4054                 */
4055                struct tx_holding_buffer *ptx =
4056                        &info->tx_holding_buffers[info->get_tx_holding_index];
4057                int num_free = num_free_tx_dma_buffers(info);
4058                int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4059                if ( ptx->buffer_size % DMABUFFERSIZE )
4060                        ++num_needed;
4061
4062                if (num_needed <= num_free) {
4063                        info->xmit_cnt = ptx->buffer_size;
4064                        mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4065
4066                        --info->tx_holding_count;
4067                        if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4068                                info->get_tx_holding_index=0;
4069
4070                        /* restart transmit timer */
4071                        mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4072
4073                        ret = true;
4074                }
4075        }
4076
4077        return ret;
4078}
4079
4080/*
4081 * save_tx_buffer_request()
4082 *
4083 * attempt to store transmit frame request for later transmission
4084 *
4085 * Arguments:
4086 *
4087 *        info                pointer to device instance data
4088 *         Buffer                pointer to buffer containing frame to load
4089 *         BufferSize        size in bytes of frame in Buffer
4090 *
4091 * Return Value:        1 if able to store, 0 otherwise
4092 */
4093static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4094{
4095        struct tx_holding_buffer *ptx;
4096
4097        if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4098                return 0;                /* all buffers in use */
4099        }
4100
4101        ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4102        ptx->buffer_size = BufferSize;
4103        memcpy( ptx->buffer, Buffer, BufferSize);
4104
4105        ++info->tx_holding_count;
4106        if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4107                info->put_tx_holding_index=0;
4108
4109        return 1;
4110}
4111
4112static int mgsl_claim_resources(struct mgsl_struct *info)
4113{
4114        if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4115                printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4116                        __FILE__,__LINE__,info->device_name, info->io_base);
4117                return -ENODEV;
4118        }
4119        info->io_addr_requested = true;
4120        
4121        if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4122                info->device_name, info ) < 0 ) {
4123                printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4124                        __FILE__,__LINE__,info->device_name, info->irq_level );
4125                goto errout;
4126        }
4127        info->irq_requested = true;
4128        
4129        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4130                if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4131                        printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4132                                __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4133                        goto errout;
4134                }
4135                info->shared_mem_requested = true;
4136                if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4137                        printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4138                                __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4139                        goto errout;
4140                }
4141                info->lcr_mem_requested = true;
4142
4143                info->memory_base = ioremap_nocache(info->phys_memory_base,
4144                                                                0x40000);
4145                if (!info->memory_base) {
4146                        printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4147                                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4148                        goto errout;
4149                }
4150                
4151                if ( !mgsl_memory_test(info) ) {
4152                        printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4153                                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4154                        goto errout;
4155                }
4156                
4157                info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4158                                                                PAGE_SIZE);
4159                if (!info->lcr_base) {
4160                        printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4161                                __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4162                        goto errout;
4163                }
4164                info->lcr_base += info->lcr_offset;
4165                
4166        } else {
4167                /* claim DMA channel */
4168                
4169                if (request_dma(info->dma_level,info->device_name) < 0){
4170                        printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4171                                __FILE__,__LINE__,info->device_name, info->dma_level );
4172                        mgsl_release_resources( info );
4173                        return -ENODEV;
4174                }
4175                info->dma_requested = true;
4176
4177                /* ISA adapter uses bus master DMA */                
4178                set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4179                enable_dma(info->dma_level);
4180        }
4181        
4182        if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4183                printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4184                        __FILE__,__LINE__,info->device_name, info->dma_level );
4185                goto errout;
4186        }        
4187        
4188        return 0;
4189errout:
4190        mgsl_release_resources(info);
4191        return -ENODEV;
4192
4193}        /* end of mgsl_claim_resources() */
4194
4195static void mgsl_release_resources(struct mgsl_struct *info)
4196{
4197        if ( debug_level >= DEBUG_LEVEL_INFO )
4198                printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4199                        __FILE__,__LINE__,info->device_name );
4200                        
4201        if ( info->irq_requested ) {
4202                free_irq(info->irq_level, info);
4203                info->irq_requested = false;
4204        }
4205        if ( info->dma_requested ) {
4206                disable_dma(info->dma_level);
4207                free_dma(info->dma_level);
4208                info->dma_requested = false;
4209        }
4210        mgsl_free_dma_buffers(info);
4211        mgsl_free_intermediate_rxbuffer_memory(info);
4212             mgsl_free_intermediate_txbuffer_memory(info);
4213        
4214        if ( info->io_addr_requested ) {
4215                release_region(info->io_base,info->io_addr_size);
4216                info->io_addr_requested = false;
4217        }
4218        if ( info->shared_mem_requested ) {
4219                release_mem_region(info->phys_memory_base,0x40000);
4220                info->shared_mem_requested = false;
4221        }
4222        if ( info->lcr_mem_requested ) {
4223                release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4224                info->lcr_mem_requested = false;
4225        }
4226        if (info->memory_base){
4227                iounmap(info->memory_base);
4228                info->memory_base = NULL;
4229        }
4230        if (info->lcr_base){
4231                iounmap(info->lcr_base - info->lcr_offset);
4232                info->lcr_base = NULL;
4233        }
4234        
4235        if ( debug_level >= DEBUG_LEVEL_INFO )
4236                printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4237                        __FILE__,__LINE__,info->device_name );
4238                        
4239}        /* end of mgsl_release_resources() */
4240
4241/* mgsl_add_device()
4242 * 
4243 *         Add the specified device instance data structure to the
4244 *         global linked list of devices and increment the device count.
4245 *         
4246 * Arguments:                info        pointer to device instance data
4247 * Return Value:        None
4248 */
4249static void mgsl_add_device( struct mgsl_struct *info )
4250{
4251        info->next_device = NULL;
4252        info->line = mgsl_device_count;
4253        sprintf(info->device_name,"ttySL%d",info->line);
4254        
4255        if (info->line < MAX_TOTAL_DEVICES) {
4256                if (maxframe[info->line])
4257                        info->max_frame_size = maxframe[info->line];
4258
4259                if (txdmabufs[info->line]) {
4260                        info->num_tx_dma_buffers = txdmabufs[info->line];
4261                        if (info->num_tx_dma_buffers < 1)
4262                                info->num_tx_dma_buffers = 1;
4263                }
4264
4265                if (txholdbufs[info->line]) {
4266                        info->num_tx_holding_buffers = txholdbufs[info->line];
4267                        if (info->num_tx_holding_buffers < 1)
4268                                info->num_tx_holding_buffers = 1;
4269                        else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4270                                info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4271                }
4272        }
4273
4274        mgsl_device_count++;
4275        
4276        if ( !mgsl_device_list )
4277                mgsl_device_list = info;
4278        else {        
4279                struct mgsl_struct *current_dev = mgsl_device_list;
4280                while( current_dev->next_device )
4281                        current_dev = current_dev->next_device;
4282                current_dev->next_device = info;
4283        }
4284        
4285        if ( info->max_frame_size < 4096 )
4286                info->max_frame_size = 4096;
4287        else if ( info->max_frame_size > 65535 )
4288                info->max_frame_size = 65535;
4289        
4290        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4291                printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4292                        info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4293                        info->phys_memory_base, info->phys_lcr_base,
4294                             info->max_frame_size );
4295        } else {
4296                printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4297                        info->device_name, info->io_base, info->irq_level, info->dma_level,
4298                             info->max_frame_size );
4299        }
4300
4301#if SYNCLINK_GENERIC_HDLC
4302        hdlcdev_init(info);
4303#endif
4304
4305}        /* end of mgsl_add_device() */
4306
4307/* mgsl_allocate_device()
4308 * 
4309 *         Allocate and initialize a device instance structure
4310 *         
4311 * Arguments:                none
4312 * Return Value:        pointer to mgsl_struct if success, otherwise NULL
4313 */
4314static struct mgsl_struct* mgsl_allocate_device(void)
4315{
4316        struct mgsl_struct *info;
4317        
4318        info = kzalloc(sizeof(struct mgsl_struct),
4319                 GFP_KERNEL);
4320                 
4321        if (!info) {
4322                printk("Error can't allocate device instance data\n");
4323        } else {
4324                tty_port_init(&info->port);
4325                info->magic = MGSL_MAGIC;
4326                INIT_WORK(&info->task, mgsl_bh_handler);
4327                info->max_frame_size = 4096;
4328                info->port.close_delay = 5*HZ/10;
4329                info->port.closing_wait = 30*HZ;
4330                init_waitqueue_head(&info->status_event_wait_q);
4331                init_waitqueue_head(&info->event_wait_q);
4332                spin_lock_init(&info->irq_spinlock);
4333                spin_lock_init(&info->netlock);
4334                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4335                info->idle_mode = HDLC_TXIDLE_FLAGS;                
4336                info->num_tx_dma_buffers = 1;
4337                info->num_tx_holding_buffers = 0;
4338        }
4339        
4340        return info;
4341
4342}        /* end of mgsl_allocate_device()*/
4343
4344static const struct tty_operations mgsl_ops = {
4345        .open = mgsl_open,
4346        .close = mgsl_close,
4347        .write = mgsl_write,
4348        .put_char = mgsl_put_char,
4349        .flush_chars = mgsl_flush_chars,
4350        .write_room = mgsl_write_room,
4351        .chars_in_buffer = mgsl_chars_in_buffer,
4352        .flush_buffer = mgsl_flush_buffer,
4353        .ioctl = mgsl_ioctl,
4354        .throttle = mgsl_throttle,
4355        .unthrottle = mgsl_unthrottle,
4356        .send_xchar = mgsl_send_xchar,
4357        .break_ctl = mgsl_break,
4358        .wait_until_sent = mgsl_wait_until_sent,
4359         .read_proc = mgsl_read_proc,
4360        .set_termios = mgsl_set_termios,
4361        .stop = mgsl_stop,
4362        .start = mgsl_start,
4363        .hangup = mgsl_hangup,
4364        .tiocmget = tiocmget,
4365        .tiocmset = tiocmset,
4366};
4367
4368/*
4369 * perform tty device initialization
4370 */
4371static int mgsl_init_tty(void)
4372{
4373        int rc;
4374
4375        serial_driver = alloc_tty_driver(128);
4376        if (!serial_driver)
4377                return -ENOMEM;
4378        
4379        serial_driver->owner = THIS_MODULE;
4380        serial_driver->driver_name = "synclink";
4381        serial_driver->name = "ttySL";
4382        serial_driver->major = ttymajor;
4383        serial_driver->minor_start = 64;
4384        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4385        serial_driver->subtype = SERIAL_TYPE_NORMAL;
4386        serial_driver->init_termios = tty_std_termios;
4387        serial_driver->init_termios.c_cflag =
4388                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4389        serial_driver->init_termios.c_ispeed = 9600;
4390        serial_driver->init_termios.c_ospeed = 9600;
4391        serial_driver->flags = TTY_DRIVER_REAL_RAW;
4392        tty_set_operations(serial_driver, &mgsl_ops);
4393        if ((rc = tty_register_driver(serial_driver)) < 0) {
4394                printk("%s(%d):Couldn't register serial driver\n",
4395                        __FILE__,__LINE__);
4396                put_tty_driver(serial_driver);
4397                serial_driver = NULL;
4398                return rc;
4399        }
4400                        
4401         printk("%s %s, tty major#%d\n",
4402                driver_name, driver_version,
4403                serial_driver->major);
4404        return 0;
4405}
4406
4407/* enumerate user specified ISA adapters
4408 */
4409static void mgsl_enum_isa_devices(void)
4410{
4411        struct mgsl_struct *info;
4412        int i;
4413                
4414        /* Check for user specified ISA devices */
4415        
4416        for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4417                if ( debug_level >= DEBUG_LEVEL_INFO )
4418                        printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4419                                io[i], irq[i], dma[i] );
4420                
4421                info = mgsl_allocate_device();
4422                if ( !info ) {
4423                        /* error allocating device instance data */
4424                        if ( debug_level >= DEBUG_LEVEL_ERROR )
4425                                printk( "can't allocate device instance data.\n");
4426                        continue;
4427                }
4428                
4429                /* Copy user configuration info to device instance data */
4430                info->io_base = (unsigned int)io[i];
4431                info->irq_level = (unsigned int)irq[i];
4432                info->irq_level = irq_canonicalize(info->irq_level);
4433                info->dma_level = (unsigned int)dma[i];
4434                info->bus_type = MGSL_BUS_TYPE_ISA;
4435                info->io_addr_size = 16;
4436                info->irq_flags = 0;
4437                
4438                mgsl_add_device( info );
4439        }
4440}
4441
4442static void synclink_cleanup(void)
4443{
4444        int rc;
4445        struct mgsl_struct *info;
4446        struct mgsl_struct *tmp;
4447
4448        printk("Unloading %s: %s\n", driver_name, driver_version);
4449
4450        if (serial_driver) {
4451                if ((rc = tty_unregister_driver(serial_driver)))
4452                        printk("%s(%d) failed to unregister tty driver err=%d\n",
4453                               __FILE__,__LINE__,rc);
4454                put_tty_driver(serial_driver);
4455        }
4456
4457        info = mgsl_device_list;
4458        while(info) {
4459#if SYNCLINK_GENERIC_HDLC
4460                hdlcdev_exit(info);
4461#endif
4462                mgsl_release_resources(info);
4463                tmp = info;
4464                info = info->next_device;
4465                kfree(tmp);
4466        }
4467        
4468        if (pci_registered)
4469                pci_unregister_driver(&synclink_pci_driver);
4470}
4471
4472static int __init synclink_init(void)
4473{
4474        int rc;
4475
4476        if (break_on_load) {
4477                 mgsl_get_text_ptr();
4478                  BREAKPOINT();
4479        }
4480
4481         printk("%s %s\n", driver_name, driver_version);
4482
4483        mgsl_enum_isa_devices();
4484        if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4485                printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4486        else
4487                pci_registered = true;
4488
4489        if ((rc = mgsl_init_tty()) < 0)
4490                goto error;
4491
4492        return 0;
4493
4494error:
4495        synclink_cleanup();
4496        return rc;
4497}
4498
4499static void __exit synclink_exit(void)
4500{
4501        synclink_cleanup();
4502}
4503
4504module_init(synclink_init);
4505module_exit(synclink_exit);
4506
4507/*
4508 * usc_RTCmd()
4509 *
4510 * Issue a USC Receive/Transmit command to the
4511 * Channel Command/Address Register (CCAR).
4512 *
4513 * Notes:
4514 *
4515 *    The command is encoded in the most significant 5 bits <15..11>
4516 *    of the CCAR value. Bits <10..7> of the CCAR must be preserved
4517 *    and Bits <6..0> must be written as zeros.
4518 *
4519 * Arguments:
4520 *
4521 *    info   pointer to device information structure
4522 *    Cmd    command mask (use symbolic macros)
4523 *
4524 * Return Value:
4525 *
4526 *    None
4527 */
4528static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4529{
4530        /* output command to CCAR in bits <15..11> */
4531        /* preserve bits <10..7>, bits <6..0> must be zero */
4532
4533        outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4534
4535        /* Read to flush write to CCAR */
4536        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4537                inw( info->io_base + CCAR );
4538
4539}        /* end of usc_RTCmd() */
4540
4541/*
4542 * usc_DmaCmd()
4543 *
4544 *    Issue a DMA command to the DMA Command/Address Register (DCAR).
4545 *
4546 * Arguments:
4547 *
4548 *    info   pointer to device information structure
4549 *    Cmd    DMA command mask (usc_DmaCmd_XX Macros)
4550 *
4551 * Return Value:
4552 *
4553 *       None
4554 */
4555static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4556{
4557        /* write command mask to DCAR */
4558        outw( Cmd + info->mbre_bit, info->io_base );
4559
4560        /* Read to flush write to DCAR */
4561        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4562                inw( info->io_base );
4563
4564}        /* end of usc_DmaCmd() */
4565
4566/*
4567 * usc_OutDmaReg()
4568 *
4569 *    Write a 16-bit value to a USC DMA register
4570 *
4571 * Arguments:
4572 *
4573 *    info      pointer to device info structure
4574 *    RegAddr   register address (number) for write
4575 *    RegValue  16-bit value to write to register
4576 *
4577 * Return Value:
4578 *
4579 *    None
4580 *
4581 */
4582static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4583{
4584        /* Note: The DCAR is located at the adapter base address */
4585        /* Note: must preserve state of BIT8 in DCAR */
4586
4587        outw( RegAddr + info->mbre_bit, info->io_base );
4588        outw( RegValue, info->io_base );
4589
4590        /* Read to flush write to DCAR */
4591        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4592                inw( info->io_base );
4593
4594}        /* end of usc_OutDmaReg() */
4595 
4596/*
4597 * usc_InDmaReg()
4598 *
4599 *    Read a 16-bit value from a DMA register
4600 *
4601 * Arguments:
4602 *
4603 *    info     pointer to device info structure
4604 *    RegAddr  register address (number) to read from
4605 *
4606 * Return Value:
4607 *
4608 *    The 16-bit value read from register
4609 *
4610 */
4611static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4612{
4613        /* Note: The DCAR is located at the adapter base address */
4614        /* Note: must preserve state of BIT8 in DCAR */
4615
4616        outw( RegAddr + info->mbre_bit, info->io_base );
4617        return inw( info->io_base );
4618
4619}        /* end of usc_InDmaReg() */
4620
4621/*
4622 *
4623 * usc_OutReg()
4624 *
4625 *    Write a 16-bit value to a USC serial channel register 
4626 *
4627 * Arguments:
4628 *
4629 *    info      pointer to device info structure
4630 *    RegAddr   register address (number) to write to
4631 *    RegValue  16-bit value to write to register
4632 *
4633 * Return Value:
4634 *
4635 *    None
4636 *
4637 */
4638static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4639{
4640        outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4641        outw( RegValue, info->io_base + CCAR );
4642
4643        /* Read to flush write to CCAR */
4644        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4645                inw( info->io_base + CCAR );
4646
4647}        /* end of usc_OutReg() */
4648
4649/*
4650 * usc_InReg()
4651 *
4652 *    Reads a 16-bit value from a USC serial channel register
4653 *
4654 * Arguments:
4655 *
4656 *    info       pointer to device extension
4657 *    RegAddr    register address (number) to read from
4658 *
4659 * Return Value:
4660 *
4661 *    16-bit value read from register
4662 */
4663static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4664{
4665        outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4666        return inw( info->io_base + CCAR );
4667
4668}        /* end of usc_InReg() */
4669
4670/* usc_set_sdlc_mode()
4671 *
4672 *    Set up the adapter for SDLC DMA communications.
4673 *
4674 * Arguments:                info    pointer to device instance data
4675 * Return Value:         NONE
4676 */
4677static void usc_set_sdlc_mode( struct mgsl_struct *info )
4678{
4679        u16 RegValue;
4680        bool PreSL1660;
4681        
4682        /*
4683         * determine if the IUSC on the adapter is pre-SL1660. If
4684         * not, take advantage of the UnderWait feature of more
4685         * modern chips. If an underrun occurs and this bit is set,
4686         * the transmitter will idle the programmed idle pattern
4687         * until the driver has time to service the underrun. Otherwise,
4688         * the dma controller may get the cycles previously requested
4689         * and begin transmitting queued tx data.
4690         */
4691        usc_OutReg(info,TMCR,0x1f);
4692        RegValue=usc_InReg(info,TMDR);
4693        PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4694
4695         if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4696         {
4697            /*
4698            ** Channel Mode Register (CMR)
4699            **
4700            ** <15..14>    10    Tx Sub Modes, Send Flag on Underrun
4701            ** <13>        0     0 = Transmit Disabled (initially)
4702            ** <12>        0     1 = Consecutive Idles share common 0
4703            ** <11..8>     1110  Transmitter Mode = HDLC/SDLC Loop
4704            ** <7..4>      0000  Rx Sub Modes, addr/ctrl field handling
4705            ** <3..0>      0110  Receiver Mode = HDLC/SDLC
4706            **
4707            ** 1000 1110 0000 0110 = 0x8e06
4708            */
4709            RegValue = 0x8e06;
4710 
4711            /*--------------------------------------------------
4712             * ignore user options for UnderRun Actions and
4713             * preambles
4714             *--------------------------------------------------*/
4715         }
4716         else
4717         {        
4718                /* Channel mode Register (CMR)
4719                 *
4720                 * <15..14>  00    Tx Sub modes, Underrun Action
4721                 * <13>      0     1 = Send Preamble before opening flag
4722                 * <12>      0     1 = Consecutive Idles share common 0
4723                 * <11..8>   0110  Transmitter mode = HDLC/SDLC
4724                 * <7..4>    0000  Rx Sub modes, addr/ctrl field handling
4725                 * <3..0>    0110  Receiver mode = HDLC/SDLC
4726                 *
4727                 * 0000 0110 0000 0110 = 0x0606
4728                 */
4729                if (info->params.mode == MGSL_MODE_RAW) {
4730                        RegValue = 0x0001;                /* Set Receive mode = external sync */
4731
4732                        usc_OutReg( info, IOCR,                /* Set IOCR DCD is RxSync Detect Input */
4733                                (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4734
4735                        /*
4736                         * TxSubMode:
4737                         *         CMR <15>                0        Don't send CRC on Tx Underrun
4738                         *         CMR <14>                x        undefined
4739                         *         CMR <13>                0        Send preamble before openning sync
4740                         *         CMR <12>                0        Send 8-bit syncs, 1=send Syncs per TxLength
4741                         *
4742                         * TxMode:
4743                         *         CMR <11-8)        0100        MonoSync
4744                         *
4745                         *         0x00 0100 xxxx xxxx  04xx
4746                         */
4747                        RegValue |= 0x0400;
4748                }
4749                else {
4750
4751                RegValue = 0x0606;
4752
4753                if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4754                        RegValue |= BIT14;
4755                else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4756                        RegValue |= BIT15;
4757                else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4758                        RegValue |= BIT15 + BIT14;
4759                }
4760
4761                if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4762                        RegValue |= BIT13;
4763        }
4764
4765        if ( info->params.mode == MGSL_MODE_HDLC &&
4766                (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4767                RegValue |= BIT12;
4768
4769        if ( info->params.addr_filter != 0xff )
4770        {
4771                /* set up receive address filtering */
4772                usc_OutReg( info, RSR, info->params.addr_filter );
4773                RegValue |= BIT4;
4774        }
4775
4776        usc_OutReg( info, CMR, RegValue );
4777        info->cmr_value = RegValue;
4778
4779        /* Receiver mode Register (RMR)
4780         *
4781         * <15..13>  000    encoding
4782         * <12..11>  00     FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4783         * <10>      1      1 = Set CRC to all 1s (use for SDLC/HDLC)
4784         * <9>       0      1 = Include Receive chars in CRC
4785         * <8>       1      1 = Use Abort/PE bit as abort indicator
4786         * <7..6>    00     Even parity
4787         * <5>       0      parity disabled
4788         * <4..2>    000    Receive Char Length = 8 bits
4789         * <1..0>    00     Disable Receiver
4790         *
4791         * 0000 0101 0000 0000 = 0x0500
4792         */
4793
4794        RegValue = 0x0500;
4795
4796        switch ( info->params.encoding ) {
4797        case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;
4798        case HDLC_ENCODING_NRZI_MARK:          RegValue |= BIT14; break;
4799        case HDLC_ENCODING_NRZI_SPACE:               RegValue |= BIT14 + BIT13; break;
4800        case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
4801        case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 + BIT13; break;
4802        case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 + BIT14; break;
4803        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4804        }
4805
4806        if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4807                RegValue |= BIT9;
4808        else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4809                RegValue |= ( BIT12 | BIT10 | BIT9 );
4810
4811        usc_OutReg( info, RMR, RegValue );
4812
4813        /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4814        /* When an opening flag of an SDLC frame is recognized the */
4815        /* Receive Character count (RCC) is loaded with the value in */
4816        /* RCLR. The RCC is decremented for each received byte.  The */
4817        /* value of RCC is stored after the closing flag of the frame */
4818        /* allowing the frame size to be computed. */
4819
4820        usc_OutReg( info, RCLR, RCLRVALUE );
4821
4822        usc_RCmd( info, RCmd_SelectRicrdma_level );
4823
4824        /* Receive Interrupt Control Register (RICR)
4825         *
4826         * <15..8>        ?        RxFIFO DMA Request Level
4827         * <7>                0        Exited Hunt IA (Interrupt Arm)
4828         * <6>                0        Idle Received IA
4829         * <5>                0        Break/Abort IA
4830         * <4>                0        Rx Bound IA
4831         * <3>                1        Queued status reflects oldest 2 bytes in FIFO
4832         * <2>                0        Abort/PE IA
4833         * <1>                1        Rx Overrun IA
4834         * <0>                0        Select TC0 value for readback
4835         *
4836         *        0000 0000 0000 1000 = 0x000a
4837         */
4838
4839        /* Carry over the Exit Hunt and Idle Received bits */
4840        /* in case they have been armed by usc_ArmEvents.   */
4841
4842        RegValue = usc_InReg( info, RICR ) & 0xc0;
4843
4844        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4845                usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4846        else
4847                usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4848
4849        /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4850
4851        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4852        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4853
4854        /* Transmit mode Register (TMR)
4855         *        
4856         * <15..13>        000        encoding
4857         * <12..11>        00        FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4858         * <10>                1        1 = Start CRC as all 1s (use for SDLC/HDLC)
4859         * <9>                0        1 = Tx CRC Enabled
4860         * <8>                0        1 = Append CRC to end of transmit frame
4861         * <7..6>        00        Transmit parity Even
4862         * <5>                0        Transmit parity Disabled
4863         * <4..2>        000        Tx Char Length = 8 bits
4864         * <1..0>        00        Disable Transmitter
4865         *
4866         *         0000 0100 0000 0000 = 0x0400
4867         */
4868
4869        RegValue = 0x0400;
4870
4871        switch ( info->params.encoding ) {
4872        case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;
4873        case HDLC_ENCODING_NRZI_MARK:          RegValue |= BIT14; break;
4874        case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 + BIT13; break;
4875        case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
4876        case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 + BIT13; break;
4877        case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 + BIT14; break;
4878        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4879        }
4880
4881        if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4882                RegValue |= BIT9 + BIT8;
4883        else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4884                RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4885
4886        usc_OutReg( info, TMR, RegValue );
4887
4888        usc_set_txidle( info );
4889
4890
4891        usc_TCmd( info, TCmd_SelectTicrdma_level );
4892
4893        /* Transmit Interrupt Control Register (TICR)
4894         *
4895         * <15..8>        ?        Transmit FIFO DMA Level
4896         * <7>                0        Present IA (Interrupt Arm)
4897         * <6>                0        Idle Sent IA
4898         * <5>                1        Abort Sent IA
4899         * <4>                1        EOF/EOM Sent IA
4900         * <3>                0        CRC Sent IA
4901         * <2>                1        1 = Wait for SW Trigger to Start Frame
4902         * <1>                1        Tx Underrun IA
4903         * <0>                0        TC0 constant on read back
4904         *
4905         *        0000 0000 0011 0110 = 0x0036
4906         */
4907
4908        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4909                usc_OutReg( info, TICR, 0x0736 );
4910        else                                                                
4911                usc_OutReg( info, TICR, 0x1436 );
4912
4913        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4914        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4915
4916        /*
4917        ** Transmit Command/Status Register (TCSR)
4918        **
4919        ** <15..12>        0000        TCmd
4920        ** <11>         0/1        UnderWait
4921        ** <10..08>        000        TxIdle
4922        ** <7>                x        PreSent
4923        ** <6>                 x        IdleSent
4924        ** <5>                 x        AbortSent
4925        ** <4>                 x        EOF/EOM Sent
4926        ** <3>                 x        CRC Sent
4927        ** <2>                 x        All Sent
4928        ** <1>                 x        TxUnder
4929        ** <0>                 x        TxEmpty
4930        ** 
4931        ** 0000 0000 0000 0000 = 0x0000
4932        */
4933        info->tcsr_value = 0;
4934
4935        if ( !PreSL1660 )
4936                info->tcsr_value |= TCSR_UNDERWAIT;
4937                
4938        usc_OutReg( info, TCSR, info->tcsr_value );
4939
4940        /* Clock mode Control Register (CMCR)
4941         *
4942         * <15..14>        00        counter 1 Source = Disabled
4943         * <13..12>         00        counter 0 Source = Disabled
4944         * <11..10>         11        BRG1 Input is TxC Pin
4945         * <9..8>        11        BRG0 Input is TxC Pin
4946         * <7..6>        01        DPLL Input is BRG1 Output
4947         * <5..3>        XXX        TxCLK comes from Port 0
4948         * <2..0>           XXX        RxCLK comes from Port 1
4949         *
4950         *        0000 1111 0111 0111 = 0x0f77
4951         */
4952
4953        RegValue = 0x0f40;
4954
4955        if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4956                RegValue |= 0x0003;        /* RxCLK from DPLL */
4957        else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4958                RegValue |= 0x0004;        /* RxCLK from BRG0 */
4959         else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4960                 RegValue |= 0x0006;        /* RxCLK from TXC Input */
4961        else
4962                RegValue |= 0x0007;        /* RxCLK from Port1 */
4963
4964        if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4965                RegValue |= 0x0018;        /* TxCLK from DPLL */
4966        else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4967                RegValue |= 0x0020;        /* TxCLK from BRG0 */
4968         else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4969                 RegValue |= 0x0038;        /* RxCLK from TXC Input */
4970        else
4971                RegValue |= 0x0030;        /* TxCLK from Port0 */
4972
4973        usc_OutReg( info, CMCR, RegValue );
4974
4975
4976        /* Hardware Configuration Register (HCR)
4977         *
4978         * <15..14>        00        CTR0 Divisor:00=32,01=16,10=8,11=4
4979         * <13>                0        CTR1DSel:0=CTR0Div determines CTR0Div
4980         * <12>                0        CVOK:0=report code violation in biphase
4981         * <11..10>        00        DPLL Divisor:00=32,01=16,10=8,11=4
4982         * <9..8>        XX        DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4983         * <7..6>        00        reserved
4984         * <5>                0        BRG1 mode:0=continuous,1=single cycle
4985         * <4>                X        BRG1 Enable
4986         * <3..2>        00        reserved
4987         * <1>                0        BRG0 mode:0=continuous,1=single cycle
4988         * <0>                0        BRG0 Enable
4989         */
4990
4991        RegValue = 0x0000;
4992
4993        if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4994                u32 XtalSpeed;
4995                u32 DpllDivisor;
4996                u16 Tc;
4997
4998                /*  DPLL is enabled. Use BRG1 to provide continuous reference clock  */
4999                /*  for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5000
5001                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5002                        XtalSpeed = 11059200;
5003                else
5004                        XtalSpeed = 14745600;
5005
5006                if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5007                        DpllDivisor = 16;
5008                        RegValue |= BIT10;
5009                }
5010                else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5011                        DpllDivisor = 8;
5012                        RegValue |= BIT11;
5013                }
5014                else
5015                        DpllDivisor = 32;
5016
5017                /*  Tc = (Xtal/Speed) - 1 */
5018                /*  If twice the remainder of (Xtal/Speed) is greater than Speed */
5019                /*  then rounding up gives a more precise time constant. Instead */
5020                /*  of rounding up and then subtracting 1 we just don't subtract */
5021                /*  the one in this case. */
5022
5023                 /*--------------------------------------------------
5024                  * ejz: for DPLL mode, application should use the
5025                  * same clock speed as the partner system, even 
5026                  * though clocking is derived from the input RxData.
5027                  * In case the user uses a 0 for the clock speed,
5028                  * default to 0xffffffff and don't try to divide by
5029                  * zero
5030                  *--------------------------------------------------*/
5031                 if ( info->params.clock_speed )
5032                 {
5033                        Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5034                        if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5035                               / info->params.clock_speed) )
5036                                Tc--;
5037                 }
5038                 else
5039                         Tc = -1;
5040                                   
5041
5042                /* Write 16-bit Time Constant for BRG1 */
5043                usc_OutReg( info, TC1R, Tc );
5044
5045                RegValue |= BIT4;                /* enable BRG1 */
5046
5047                switch ( info->params.encoding ) {
5048                case HDLC_ENCODING_NRZ:
5049                case HDLC_ENCODING_NRZB:
5050                case HDLC_ENCODING_NRZI_MARK:
5051                case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5052                case HDLC_ENCODING_BIPHASE_MARK:
5053                case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5054                case HDLC_ENCODING_BIPHASE_LEVEL:
5055                case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5056                }
5057        }
5058
5059        usc_OutReg( info, HCR, RegValue );
5060
5061
5062        /* Channel Control/status Register (CCSR)
5063         *
5064         * <15>                X        RCC FIFO Overflow status (RO)
5065         * <14>                X        RCC FIFO Not Empty status (RO)
5066         * <13>                0        1 = Clear RCC FIFO (WO)
5067         * <12>                X        DPLL Sync (RW)
5068         * <11>                X        DPLL 2 Missed Clocks status (RO)
5069         * <10>                X        DPLL 1 Missed Clock status (RO)
5070         * <9..8>        00        DPLL Resync on rising and falling edges (RW)
5071         * <7>                X        SDLC Loop On status (RO)
5072         * <6>                X        SDLC Loop Send status (RO)
5073         * <5>                1        Bypass counters for TxClk and RxClk (RW)
5074         * <4..2>           000        Last Char of SDLC frame has 8 bits (RW)
5075         * <1..0>           00        reserved
5076         *
5077         *        0000 0000 0010 0000 = 0x0020
5078         */
5079
5080        usc_OutReg( info, CCSR, 0x1020 );
5081
5082
5083        if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5084                usc_OutReg( info, SICR,
5085                            (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5086        }
5087        
5088
5089        /* enable Master Interrupt Enable bit (MIE) */
5090        usc_EnableMasterIrqBit( info );
5091
5092        usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5093                                TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5094
5095        /* arm RCC underflow interrupt */
5096        usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5097        usc_EnableInterrupts(info, MISC);
5098
5099        info->mbre_bit = 0;
5100        outw( 0, info->io_base );                         /* clear Master Bus Enable (DCAR) */
5101        usc_DmaCmd( info, DmaCmd_ResetAllChannels );        /* disable both DMA channels */
5102        info->mbre_bit = BIT8;
5103        outw( BIT8, info->io_base );                        /* set Master Bus Enable (DCAR) */
5104
5105        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5106                /* Enable DMAEN (Port 7, Bit 14) */
5107                /* This connects the DMA request signal to the ISA bus */
5108                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5109        }
5110
5111        /* DMA Control Register (DCR)
5112         *
5113         * <15..14>        10        Priority mode = Alternating Tx/Rx
5114         *                01        Rx has priority
5115         *                00        Tx has priority
5116         *
5117         * <13>                1        Enable Priority Preempt per DCR<15..14>
5118         *                        (WARNING DCR<11..10> must be 00 when this is 1)
5119         *                0        Choose activate channel per DCR<11..10>
5120         *
5121         * <12>                0        Little Endian for Array/List
5122         * <11..10>        00        Both Channels can use each bus grant
5123         * <9..6>        0000        reserved
5124         * <5>                0        7 CLK - Minimum Bus Re-request Interval
5125         * <4>                0        1 = drive D/C and S/D pins
5126         * <3>                1        1 = Add one wait state to all DMA cycles.
5127         * <2>                0        1 = Strobe /UAS on every transfer.
5128         * <1..0>        11        Addr incrementing only affects LS24 bits
5129         *
5130         *        0110 0000 0000 1011 = 0x600b
5131         */
5132
5133        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5134                /* PCI adapter does not need DMA wait state */
5135                usc_OutDmaReg( info, DCR, 0xa00b );
5136        }
5137        else
5138                usc_OutDmaReg( info, DCR, 0x800b );
5139
5140
5141        /* Receive DMA mode Register (RDMR)
5142         *
5143         * <15..14>        11        DMA mode = Linked List Buffer mode
5144         * <13>                1        RSBinA/L = store Rx status Block in Arrary/List entry
5145         * <12>                1        Clear count of List Entry after fetching
5146         * <11..10>        00        Address mode = Increment
5147         * <9>                1        Terminate Buffer on RxBound
5148         * <8>                0        Bus Width = 16bits
5149         * <7..0>        ?        status Bits (write as 0s)
5150         *
5151         * 1111 0010 0000 0000 = 0xf200
5152         */
5153
5154        usc_OutDmaReg( info, RDMR, 0xf200 );
5155
5156
5157        /* Transmit DMA mode Register (TDMR)
5158         *
5159         * <15..14>        11        DMA mode = Linked List Buffer mode
5160         * <13>                1        TCBinA/L = fetch Tx Control Block from List entry
5161         * <12>                1        Clear count of List Entry after fetching
5162         * <11..10>        00        Address mode = Increment
5163         * <9>                1        Terminate Buffer on end of frame
5164         * <8>                0        Bus Width = 16bits
5165         * <7..0>        ?        status Bits (Read Only so write as 0)
5166         *
5167         *        1111 0010 0000 0000 = 0xf200
5168         */
5169
5170        usc_OutDmaReg( info, TDMR, 0xf200 );
5171
5172
5173        /* DMA Interrupt Control Register (DICR)
5174         *
5175         * <15>                1        DMA Interrupt Enable
5176         * <14>                0        1 = Disable IEO from USC
5177         * <13>                0        1 = Don't provide vector during IntAck
5178         * <12>                1        1 = Include status in Vector
5179         * <10..2>        0        reserved, Must be 0s
5180         * <1>                0        1 = Rx DMA Interrupt Enabled
5181         * <0>                0        1 = Tx DMA Interrupt Enabled
5182         *
5183         *        1001 0000 0000 0000 = 0x9000
5184         */
5185
5186        usc_OutDmaReg( info, DICR, 0x9000 );
5187
5188        usc_InDmaReg( info, RDMR );                /* clear pending receive DMA IRQ bits */
5189        usc_InDmaReg( info, TDMR );                /* clear pending transmit DMA IRQ bits */
5190        usc_OutDmaReg( info, CDIR, 0x0303 );        /* clear IUS and Pending for Tx and Rx */
5191
5192        /* Channel Control Register (CCR)
5193         *
5194         * <15..14>        10        Use 32-bit Tx Control Blocks (TCBs)
5195         * <13>                0        Trigger Tx on SW Command Disabled
5196         * <12>                0        Flag Preamble Disabled
5197         * <11..10>        00        Preamble Length
5198         * <9..8>        00        Preamble Pattern
5199         * <7..6>        10        Use 32-bit Rx status Blocks (RSBs)
5200         * <5>                0        Trigger Rx on SW Command Disabled
5201         * <4..0>        0        reserved
5202         *
5203         *        1000 0000 1000 0000 = 0x8080
5204         */
5205
5206        RegValue = 0x8080;
5207
5208        switch ( info->params.preamble_length ) {
5209        case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5210        case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5211        case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5212        }
5213
5214        switch ( info->params.preamble ) {
5215        case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5216        case HDLC_PREAMBLE_PATTERN_ONES:  RegValue |= BIT8; break;
5217        case HDLC_PREAMBLE_PATTERN_10:    RegValue |= BIT9; break;
5218        case HDLC_PREAMBLE_PATTERN_01:    RegValue |= BIT9 + BIT8; break;
5219        }
5220
5221        usc_OutReg( info, CCR, RegValue );
5222
5223
5224        /*
5225         * Burst/Dwell Control Register
5226         *
5227         * <15..8>        0x20        Maximum number of transfers per bus grant
5228         * <7..0>        0x00        Maximum number of clock cycles per bus grant
5229         */
5230
5231        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5232                /* don't limit bus occupancy on PCI adapter */
5233                usc_OutDmaReg( info, BDCR, 0x0000 );
5234        }
5235        else
5236                usc_OutDmaReg( info, BDCR, 0x2000 );
5237
5238        usc_stop_transmitter(info);
5239        usc_stop_receiver(info);
5240        
5241}        /* end of usc_set_sdlc_mode() */
5242
5243/* usc_enable_loopback()
5244 *
5245 * Set the 16C32 for internal loopback mode.
5246 * The TxCLK and RxCLK signals are generated from the BRG0 and
5247 * the TxD is looped back to the RxD internally.
5248 *
5249 * Arguments:                info        pointer to device instance data
5250 *                        enable        1 = enable loopback, 0 = disable
5251 * Return Value:        None
5252 */
5253static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5254{
5255        if (enable) {
5256                /* blank external TXD output */
5257                usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5258        
5259                /* Clock mode Control Register (CMCR)
5260                 *
5261                 * <15..14>        00        counter 1 Disabled
5262                 * <13..12>         00        counter 0 Disabled
5263                 * <11..10>         11        BRG1 Input is TxC Pin
5264                 * <9..8>        11        BRG0 Input is TxC Pin
5265                 * <7..6>        01        DPLL Input is BRG1 Output
5266                 * <5..3>        100        TxCLK comes from BRG0
5267                 * <2..0>           100        RxCLK comes from BRG0
5268                 *
5269                 * 0000 1111 0110 0100 = 0x0f64
5270                 */
5271
5272                usc_OutReg( info, CMCR, 0x0f64 );
5273
5274                /* Write 16-bit Time Constant for BRG0 */
5275                /* use clock speed if available, otherwise use 8 for diagnostics */
5276                if (info->params.clock_speed) {
5277                        if (info->bus_type == MGSL_BUS_TYPE_PCI)
5278                                usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5279                        else
5280                                usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5281                } else
5282                        usc_OutReg(info, TC0R, (u16)8);
5283
5284                /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5285                   mode = Continuous Set Bit 0 to enable BRG0.  */
5286                usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5287
5288                /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5289                usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5290
5291                /* set Internal Data loopback mode */
5292                info->loopback_bits = 0x300;
5293                outw( 0x0300, info->io_base + CCAR );
5294        } else {
5295                /* enable external TXD output */
5296                usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5297        
5298                /* clear Internal Data loopback mode */
5299                info->loopback_bits = 0;
5300                outw( 0,info->io_base + CCAR );
5301        }
5302        
5303}        /* end of usc_enable_loopback() */
5304
5305/* usc_enable_aux_clock()
5306 *
5307 * Enabled the AUX clock output at the specified frequency.
5308 *
5309 * Arguments:
5310 *
5311 *        info                pointer to device extension
5312 *        data_rate        data rate of clock in bits per second
5313 *                        A data rate of 0 disables the AUX clock.
5314 *
5315 * Return Value:        None
5316 */
5317static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5318{
5319        u32 XtalSpeed;
5320        u16 Tc;
5321
5322        if ( data_rate ) {
5323                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5324                        XtalSpeed = 11059200;
5325                else
5326                        XtalSpeed = 14745600;
5327
5328
5329                /* Tc = (Xtal/Speed) - 1 */
5330                /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5331                /* then rounding up gives a more precise time constant. Instead */
5332                /* of rounding up and then subtracting 1 we just don't subtract */
5333                /* the one in this case. */
5334
5335
5336                Tc = (u16)(XtalSpeed/data_rate);
5337                if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5338                        Tc--;
5339
5340                /* Write 16-bit Time Constant for BRG0 */
5341                usc_OutReg( info, TC0R, Tc );
5342
5343                /*
5344                 * Hardware Configuration Register (HCR)
5345                 * Clear Bit 1, BRG0 mode = Continuous
5346                 * Set Bit 0 to enable BRG0.
5347                 */
5348
5349                usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5350
5351                /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5352                usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5353        } else {
5354                /* data rate == 0 so turn off BRG0 */
5355                usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5356        }
5357
5358}        /* end of usc_enable_aux_clock() */
5359
5360/*
5361 *
5362 * usc_process_rxoverrun_sync()
5363 *
5364 *                This function processes a receive overrun by resetting the
5365 *                receive DMA buffers and issuing a Purge Rx FIFO command
5366 *                to allow the receiver to continue receiving.
5367 *
5368 * Arguments:
5369 *
5370 *        info                pointer to device extension
5371 *
5372 * Return Value: None
5373 */
5374static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5375{
5376        int start_index;
5377        int end_index;
5378        int frame_start_index;
5379        bool start_of_frame_found = false;
5380        bool end_of_frame_found = false;
5381        bool reprogram_dma = false;
5382
5383        DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5384        u32 phys_addr;
5385
5386        usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5387        usc_RCmd( info, RCmd_EnterHuntmode );
5388        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5389
5390        /* CurrentRxBuffer points to the 1st buffer of the next */
5391        /* possibly available receive frame. */
5392        
5393        frame_start_index = start_index = end_index = info->current_rx_buffer;
5394
5395        /* Search for an unfinished string of buffers. This means */
5396        /* that a receive frame started (at least one buffer with */
5397        /* count set to zero) but there is no terminiting buffer */
5398        /* (status set to non-zero). */
5399
5400        while( !buffer_list[end_index].count )
5401        {
5402                /* Count field has been reset to zero by 16C32. */
5403                /* This buffer is currently in use. */
5404
5405                if ( !start_of_frame_found )
5406                {
5407                        start_of_frame_found = true;
5408                        frame_start_index = end_index;
5409                        end_of_frame_found = false;
5410                }
5411
5412                if ( buffer_list[end_index].status )
5413                {
5414                        /* Status field has been set by 16C32. */
5415                        /* This is the last buffer of a received frame. */
5416
5417                        /* We want to leave the buffers for this frame intact. */
5418                        /* Move on to next possible frame. */
5419
5420                        start_of_frame_found = false;
5421                        end_of_frame_found = true;
5422                }
5423
5424                  /* advance to next buffer entry in linked list */
5425                  end_index++;
5426                  if ( end_index == info->rx_buffer_count )
5427                          end_index = 0;
5428
5429                if ( start_index == end_index )
5430                {
5431                        /* The entire list has been searched with all Counts == 0 and */
5432                        /* all Status == 0. The receive buffers are */
5433                        /* completely screwed, reset all receive buffers! */
5434                        mgsl_reset_rx_dma_buffers( info );
5435                        frame_start_index = 0;
5436                        start_of_frame_found = false;
5437                        reprogram_dma = true;
5438                        break;
5439                }
5440        }
5441
5442        if ( start_of_frame_found && !end_of_frame_found )
5443        {
5444                /* There is an unfinished string of receive DMA buffers */
5445                /* as a result of the receiver overrun. */
5446
5447                /* Reset the buffers for the unfinished frame */
5448                /* and reprogram the receive DMA controller to start */
5449                /* at the 1st buffer of unfinished frame. */
5450
5451                start_index = frame_start_index;
5452
5453                do
5454                {
5455                        *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5456
5457                          /* Adjust index for wrap around. */
5458                          if ( start_index == info->rx_buffer_count )
5459                                  start_index = 0;
5460
5461                } while( start_index != end_index );
5462
5463                reprogram_dma = true;
5464        }
5465
5466        if ( reprogram_dma )
5467        {
5468                usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5469                usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5470                usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5471                
5472                usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5473                
5474                /* This empties the receive FIFO and loads the RCC with RCLR */
5475                usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5476
5477                /* program 16C32 with physical address of 1st DMA buffer entry */
5478                phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5479                usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5480                usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5481
5482                usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5483                usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5484                usc_EnableInterrupts( info, RECEIVE_STATUS );
5485
5486                /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5487                /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5488
5489                usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5490                usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5491                usc_DmaCmd( info, DmaCmd_InitRxChannel );
5492                if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5493                        usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5494                else
5495                        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5496        }
5497        else
5498        {
5499                /* This empties the receive FIFO and loads the RCC with RCLR */
5500                usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5501                usc_RTCmd( info, RTCmd_PurgeRxFifo );
5502        }
5503
5504}        /* end of usc_process_rxoverrun_sync() */
5505
5506/* usc_stop_receiver()
5507 *
5508 *        Disable USC receiver
5509 *
5510 * Arguments:                info        pointer to device instance data
5511 * Return Value:        None
5512 */
5513static void usc_stop_receiver( struct mgsl_struct *info )
5514{
5515        if (debug_level >= DEBUG_LEVEL_ISR)
5516                printk("%s(%d):usc_stop_receiver(%s)\n",
5517                         __FILE__,__LINE__, info->device_name );
5518                         
5519        /* Disable receive DMA channel. */
5520        /* This also disables receive DMA channel interrupts */
5521        usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5522
5523        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5524        usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5525        usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5526
5527        usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5528
5529        /* This empties the receive FIFO and loads the RCC with RCLR */
5530        usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5531        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5532
5533        info->rx_enabled = false;
5534        info->rx_overflow = false;
5535        info->rx_rcc_underrun = false;
5536        
5537}        /* end of stop_receiver() */
5538
5539/* usc_start_receiver()
5540 *
5541 *        Enable the USC receiver 
5542 *
5543 * Arguments:                info        pointer to device instance data
5544 * Return Value:        None
5545 */
5546static void usc_start_receiver( struct mgsl_struct *info )
5547{
5548        u32 phys_addr;
5549        
5550        if (debug_level >= DEBUG_LEVEL_ISR)
5551                printk("%s(%d):usc_start_receiver(%s)\n",
5552                         __FILE__,__LINE__, info->device_name );
5553
5554        mgsl_reset_rx_dma_buffers( info );
5555        usc_stop_receiver( info );
5556
5557        usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5558        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5559
5560        if ( info->params.mode == MGSL_MODE_HDLC ||
5561                info->params.mode == MGSL_MODE_RAW ) {
5562                /* DMA mode Transfers */
5563                /* Program the DMA controller. */
5564                /* Enable the DMA controller end of buffer interrupt. */
5565
5566                /* program 16C32 with physical address of 1st DMA buffer entry */
5567                phys_addr = info->rx_buffer_list[0].phys_entry;
5568                usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5569                usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5570
5571                usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5572                usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5573                usc_EnableInterrupts( info, RECEIVE_STATUS );
5574
5575                /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5576                /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5577
5578                usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5579                usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5580                usc_DmaCmd( info, DmaCmd_InitRxChannel );
5581                if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5582                        usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5583                else
5584                        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5585        } else {
5586                usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5587                usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5588                usc_EnableInterrupts(info, RECEIVE_DATA);
5589
5590                usc_RTCmd( info, RTCmd_PurgeRxFifo );
5591                usc_RCmd( info, RCmd_EnterHuntmode );
5592
5593                usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5594        }
5595
5596        usc_OutReg( info, CCSR, 0x1020 );
5597
5598        info->rx_enabled = true;
5599
5600}        /* end of usc_start_receiver() */
5601
5602/* usc_start_transmitter()
5603 *
5604 *        Enable the USC transmitter and send a transmit frame if
5605 *        one is loaded in the DMA buffers.
5606 *
5607 * Arguments:                info        pointer to device instance data
5608 * Return Value:        None
5609 */
5610static void usc_start_transmitter( struct mgsl_struct *info )
5611{
5612        u32 phys_addr;
5613        unsigned int FrameSize;
5614
5615        if (debug_level >= DEBUG_LEVEL_ISR)
5616                printk("%s(%d):usc_start_transmitter(%s)\n",
5617                         __FILE__,__LINE__, info->device_name );
5618                         
5619        if ( info->xmit_cnt ) {
5620
5621                /* If auto RTS enabled and RTS is inactive, then assert */
5622                /* RTS and set a flag indicating that the driver should */
5623                /* negate RTS when the transmission completes. */
5624
5625                info->drop_rts_on_tx_done = false;
5626
5627                if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5628                        usc_get_serial_signals( info );
5629                        if ( !(info->serial_signals & SerialSignal_RTS) ) {
5630                                info->serial_signals |= SerialSignal_RTS;
5631                                usc_set_serial_signals( info );
5632                                info->drop_rts_on_tx_done = true;
5633                        }
5634                }
5635
5636
5637                if ( info->params.mode == MGSL_MODE_ASYNC ) {
5638                        if ( !info->tx_active ) {
5639                                usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5640                                usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5641                                usc_EnableInterrupts(info, TRANSMIT_DATA);
5642                                usc_load_txfifo(info);
5643                        }
5644                } else {
5645                        /* Disable transmit DMA controller while programming. */
5646                        usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5647                        
5648                        /* Transmit DMA buffer is loaded, so program USC */
5649                        /* to send the frame contained in the buffers.         */
5650
5651                        FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5652
5653                        /* if operating in Raw sync mode, reset the rcc component
5654                         * of the tx dma buffer entry, otherwise, the serial controller
5655                         * will send a closing sync char after this count.
5656                         */
5657                            if ( info->params.mode == MGSL_MODE_RAW )
5658                                info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5659
5660                        /* Program the Transmit Character Length Register (TCLR) */
5661                        /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5662                        usc_OutReg( info, TCLR, (u16)FrameSize );
5663
5664                        usc_RTCmd( info, RTCmd_PurgeTxFifo );
5665
5666                        /* Program the address of the 1st DMA Buffer Entry in linked list */
5667                        phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5668                        usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5669                        usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5670
5671                        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5672                        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5673                        usc_EnableInterrupts( info, TRANSMIT_STATUS );
5674
5675                        if ( info->params.mode == MGSL_MODE_RAW &&
5676                                        info->num_tx_dma_buffers > 1 ) {
5677                           /* When running external sync mode, attempt to 'stream' transmit  */
5678                           /* by filling tx dma buffers as they become available. To do this */
5679                           /* we need to enable Tx DMA EOB Status interrupts :               */
5680                           /*                                                                */
5681                           /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5682                           /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5683
5684                           usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5685                           usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5686                        }
5687
5688                        /* Initialize Transmit DMA Channel */
5689                        usc_DmaCmd( info, DmaCmd_InitTxChannel );
5690                        
5691                        usc_TCmd( info, TCmd_SendFrame );
5692                        
5693                        mod_timer(&info->tx_timer, jiffies +
5694                                        msecs_to_jiffies(5000));
5695                }
5696                info->tx_active = true;
5697        }
5698
5699        if ( !info->tx_enabled ) {
5700                info->tx_enabled = true;
5701                if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5702                        usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5703                else
5704                        usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5705        }
5706
5707}        /* end of usc_start_transmitter() */
5708
5709/* usc_stop_transmitter()
5710 *
5711 *        Stops the transmitter and DMA
5712 *
5713 * Arguments:                info        pointer to device isntance data
5714 * Return Value:        None
5715 */
5716static void usc_stop_transmitter( struct mgsl_struct *info )
5717{
5718        if (debug_level >= DEBUG_LEVEL_ISR)
5719                printk("%s(%d):usc_stop_transmitter(%s)\n",
5720                         __FILE__,__LINE__, info->device_name );
5721                         
5722        del_timer(&info->tx_timer);        
5723                         
5724        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5725        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5726        usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5727
5728        usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5729        usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5730        usc_RTCmd( info, RTCmd_PurgeTxFifo );
5731
5732        info->tx_enabled = false;
5733        info->tx_active = false;
5734
5735}        /* end of usc_stop_transmitter() */
5736
5737/* usc_load_txfifo()
5738 *
5739 *        Fill the transmit FIFO until the FIFO is full or
5740 *        there is no more data to load.
5741 *
5742 * Arguments:                info        pointer to device extension (instance data)
5743 * Return Value:        None
5744 */
5745static void usc_load_txfifo( struct mgsl_struct *info )
5746{
5747        int Fifocount;
5748        u8 TwoBytes[2];
5749        
5750        if ( !info->xmit_cnt && !info->x_char )
5751                return; 
5752                
5753        /* Select transmit FIFO status readback in TICR */
5754        usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5755
5756        /* load the Transmit FIFO until FIFOs full or all data sent */
5757
5758        while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5759                /* there is more space in the transmit FIFO and */
5760                /* there is more data in transmit buffer */
5761
5762                if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5763                         /* write a 16-bit word from transmit buffer to 16C32 */
5764                                
5765                        TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5766                        info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5767                        TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5768                        info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5769                        
5770                        outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5771                                
5772                        info->xmit_cnt -= 2;
5773                        info->icount.tx += 2;
5774                } else {
5775                        /* only 1 byte left to transmit or 1 FIFO slot left */
5776                        
5777                        outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5778                                info->io_base + CCAR );
5779                        
5780                        if (info->x_char) {
5781                                /* transmit pending high priority char */
5782                                outw( info->x_char,info->io_base + CCAR );
5783                                info->x_char = 0;
5784                        } else {
5785                                outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5786                                info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5787                                info->xmit_cnt--;
5788                        }
5789                        info->icount.tx++;
5790                }
5791        }
5792
5793}        /* end of usc_load_txfifo() */
5794
5795/* usc_reset()
5796 *
5797 *        Reset the adapter to a known state and prepare it for further use.
5798 *
5799 * Arguments:                info        pointer to device instance data
5800 * Return Value:        None
5801 */
5802static void usc_reset( struct mgsl_struct *info )
5803{
5804        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5805                int i;
5806                u32 readval;
5807
5808                /* Set BIT30 of Misc Control Register */
5809                /* (Local Control Register 0x50) to force reset of USC. */
5810
5811                volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5812                u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5813
5814                info->misc_ctrl_value |= BIT30;
5815                *MiscCtrl = info->misc_ctrl_value;
5816
5817                /*
5818                 * Force at least 170ns delay before clearing 
5819                 * reset bit. Each read from LCR takes at least 
5820                 * 30ns so 10 times for 300ns to be safe.
5821                 */
5822                for(i=0;i<10;i++)
5823                        readval = *MiscCtrl;
5824
5825                info->misc_ctrl_value &= ~BIT30;
5826                *MiscCtrl = info->misc_ctrl_value;
5827
5828                *LCR0BRDR = BUS_DESCRIPTOR(
5829                        1,                // Write Strobe Hold (0-3)
5830                        2,                // Write Strobe Delay (0-3)
5831                        2,                // Read Strobe Delay  (0-3)
5832                        0,                // NWDD (Write data-data) (0-3)
5833                        4,                // NWAD (Write Addr-data) (0-31)
5834                        0,                // NXDA (Read/Write Data-Addr) (0-3)
5835                        0,                // NRDD (Read Data-Data) (0-3)
5836                        5                // NRAD (Read Addr-Data) (0-31)
5837                        );
5838        } else {
5839                /* do HW reset */
5840                outb( 0,info->io_base + 8 );
5841        }
5842
5843        info->mbre_bit = 0;
5844        info->loopback_bits = 0;
5845        info->usc_idle_mode = 0;
5846
5847        /*
5848         * Program the Bus Configuration Register (BCR)
5849         *
5850         * <15>                0        Don't use separate address
5851         * <14..6>        0        reserved
5852         * <5..4>        00        IAckmode = Default, don't care
5853         * <3>                1        Bus Request Totem Pole output
5854         * <2>                1        Use 16 Bit data bus
5855         * <1>                0        IRQ Totem Pole output
5856         * <0>                0        Don't Shift Right Addr
5857         *
5858         * 0000 0000 0000 1100 = 0x000c
5859         *
5860         * By writing to io_base + SDPIN the Wait/Ack pin is
5861         * programmed to work as a Wait pin.
5862         */
5863        
5864        outw( 0x000c,info->io_base + SDPIN );
5865
5866
5867        outw( 0,info->io_base );
5868        outw( 0,info->io_base + CCAR );
5869
5870        /* select little endian byte ordering */
5871        usc_RTCmd( info, RTCmd_SelectLittleEndian );
5872
5873
5874        /* Port Control Register (PCR)
5875         *
5876         * <15..14>        11        Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5877         * <13..12>        11        Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5878         * <11..10>         00        Port 5 is Input (No Connect, Don't Care)
5879         * <9..8>         00        Port 4 is Input (No Connect, Don't Care)
5880         * <7..6>        11        Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5881         * <5..4>        11        Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5882         * <3..2>        01        Port 1 is Input (Dedicated RxC)
5883         * <1..0>        01        Port 0 is Input (Dedicated TxC)
5884         *
5885         *        1111 0000 1111 0101 = 0xf0f5
5886         */
5887
5888        usc_OutReg( info, PCR, 0xf0f5 );
5889
5890
5891        /*
5892         * Input/Output Control Register
5893         *
5894         * <15..14>        00        CTS is active low input
5895         * <13..12>        00        DCD is active low input
5896         * <11..10>        00        TxREQ pin is input (DSR)
5897         * <9..8>        00        RxREQ pin is input (RI)
5898         * <7..6>        00        TxD is output (Transmit Data)
5899         * <5..3>        000        TxC Pin in Input (14.7456MHz Clock)
5900         * <2..0>        100        RxC is Output (drive with BRG0)
5901         *
5902         *        0000 0000 0000 0100 = 0x0004
5903         */
5904
5905        usc_OutReg( info, IOCR, 0x0004 );
5906
5907}        /* end of usc_reset() */
5908
5909/* usc_set_async_mode()
5910 *
5911 *        Program adapter for asynchronous communications.
5912 *
5913 * Arguments:                info                pointer to device instance data
5914 * Return Value:        None
5915 */
5916static void usc_set_async_mode( struct mgsl_struct *info )
5917{
5918        u16 RegValue;
5919
5920        /* disable interrupts while programming USC */
5921        usc_DisableMasterIrqBit( info );
5922
5923        outw( 0, info->io_base );                         /* clear Master Bus Enable (DCAR) */
5924        usc_DmaCmd( info, DmaCmd_ResetAllChannels );        /* disable both DMA channels */
5925
5926        usc_loopback_frame( info );
5927
5928        /* Channel mode Register (CMR)
5929         *
5930         * <15..14>        00        Tx Sub modes, 00 = 1 Stop Bit
5931         * <13..12>        00                      00 = 16X Clock
5932         * <11..8>        0000        Transmitter mode = Asynchronous
5933         * <7..6>        00        reserved?
5934         * <5..4>        00        Rx Sub modes, 00 = 16X Clock
5935         * <3..0>        0000        Receiver mode = Asynchronous
5936         *
5937         * 0000 0000 0000 0000 = 0x0
5938         */
5939
5940        RegValue = 0;
5941        if ( info->params.stop_bits != 1 )
5942                RegValue |= BIT14;
5943        usc_OutReg( info, CMR, RegValue );
5944
5945        
5946        /* Receiver mode Register (RMR)
5947         *
5948         * <15..13>        000        encoding = None
5949         * <12..08>        00000        reserved (Sync Only)
5950         * <7..6>           00        Even parity
5951         * <5>                0        parity disabled
5952         * <4..2>        000        Receive Char Length = 8 bits
5953         * <1..0>        00        Disable Receiver
5954         *
5955         * 0000 0000 0000 0000 = 0x0
5956         */
5957
5958        RegValue = 0;
5959
5960        if ( info->params.data_bits != 8 )
5961                RegValue |= BIT4+BIT3+BIT2;
5962
5963        if ( info->params.parity != ASYNC_PARITY_NONE ) {
5964                RegValue |= BIT5;
5965                if ( info->params.parity != ASYNC_PARITY_ODD )
5966                        RegValue |= BIT6;
5967        }
5968
5969        usc_OutReg( info, RMR, RegValue );
5970
5971
5972        /* Set IRQ trigger level */
5973
5974        usc_RCmd( info, RCmd_SelectRicrIntLevel );
5975
5976        
5977        /* Receive Interrupt Control Register (RICR)
5978         *
5979         * <15..8>        ?                RxFIFO IRQ Request Level
5980         *
5981         * Note: For async mode the receive FIFO level must be set
5982         * to 0 to avoid the situation where the FIFO contains fewer bytes
5983         * than the trigger level and no more data is expected.
5984         *
5985         * <7>                0                Exited Hunt IA (Interrupt Arm)
5986         * <6>                0                Idle Received IA
5987         * <5>                0                Break/Abort IA
5988         * <4>                0                Rx Bound IA
5989         * <3>                0                Queued status reflects oldest byte in FIFO
5990         * <2>                0                Abort/PE IA
5991         * <1>                0                Rx Overrun IA
5992         * <0>                0                Select TC0 value for readback
5993         *
5994         * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5995         */
5996        
5997        usc_OutReg( info, RICR, 0x0000 );
5998
5999        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6000        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6001
6002        
6003        /* Transmit mode Register (TMR)
6004         *
6005         * <15..13>        000        encoding = None
6006         * <12..08>        00000        reserved (Sync Only)
6007         * <7..6>        00        Transmit parity Even
6008         * <5>                0        Transmit parity Disabled
6009         * <4..2>        000        Tx Char Length = 8 bits
6010         * <1..0>        00        Disable Transmitter
6011         *
6012         * 0000 0000 0000 0000 = 0x0
6013         */
6014
6015        RegValue = 0;
6016
6017        if ( info->params.data_bits != 8 )
6018                RegValue |= BIT4+BIT3+BIT2;
6019
6020        if ( info->params.parity != ASYNC_PARITY_NONE ) {
6021                RegValue |= BIT5;
6022                if ( info->params.parity != ASYNC_PARITY_ODD )
6023                        RegValue |= BIT6;
6024        }
6025
6026        usc_OutReg( info, TMR, RegValue );
6027
6028        usc_set_txidle( info );
6029
6030
6031        /* Set IRQ trigger level */
6032
6033        usc_TCmd( info, TCmd_SelectTicrIntLevel );
6034
6035        
6036        /* Transmit Interrupt Control Register (TICR)
6037         *
6038         * <15..8>        ?        Transmit FIFO IRQ Level
6039         * <7>                0        Present IA (Interrupt Arm)
6040         * <6>                1        Idle Sent IA
6041         * <5>                0        Abort Sent IA
6042         * <4>                0        EOF/EOM Sent IA
6043         * <3>                0        CRC Sent IA
6044         * <2>                0        1 = Wait for SW Trigger to Start Frame
6045         * <1>                0        Tx Underrun IA
6046         * <0>                0        TC0 constant on read back
6047         *
6048         *        0000 0000 0100 0000 = 0x0040
6049         */
6050
6051        usc_OutReg( info, TICR, 0x1f40 );
6052
6053        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6054        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6055
6056        usc_enable_async_clock( info, info->params.data_rate );
6057
6058        
6059        /* Channel Control/status Register (CCSR)
6060         *
6061         * <15>                X        RCC FIFO Overflow status (RO)
6062         * <14>                X        RCC FIFO Not Empty status (RO)
6063         * <13>                0        1 = Clear RCC FIFO (WO)
6064         * <12>                X        DPLL in Sync status (RO)
6065         * <11>                X        DPLL 2 Missed Clocks status (RO)
6066         * <10>                X        DPLL 1 Missed Clock status (RO)
6067         * <9..8>        00        DPLL Resync on rising and falling edges (RW)
6068         * <7>                X        SDLC Loop On status (RO)
6069         * <6>                X        SDLC Loop Send status (RO)
6070         * <5>                1        Bypass counters for TxClk and RxClk (RW)
6071         * <4..2>           000        Last Char of SDLC frame has 8 bits (RW)
6072         * <1..0>           00        reserved
6073         *
6074         *        0000 0000 0010 0000 = 0x0020
6075         */
6076        
6077        usc_OutReg( info, CCSR, 0x0020 );
6078
6079        usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6080                              RECEIVE_DATA + RECEIVE_STATUS );
6081
6082        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6083                                RECEIVE_DATA + RECEIVE_STATUS );
6084
6085        usc_EnableMasterIrqBit( info );
6086
6087        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6088                /* Enable INTEN (Port 6, Bit12) */
6089                /* This connects the IRQ request signal to the ISA bus */
6090                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6091        }
6092
6093        if (info->params.loopback) {
6094                info->loopback_bits = 0x300;
6095                outw(0x0300, info->io_base + CCAR);
6096        }
6097
6098}        /* end of usc_set_async_mode() */
6099
6100/* usc_loopback_frame()
6101 *
6102 *        Loop back a small (2 byte) dummy SDLC frame.
6103 *        Interrupts and DMA are NOT used. The purpose of this is to
6104 *        clear any 'stale' status info left over from running in        async mode.
6105 *
6106 *        The 16C32 shows the strange behaviour of marking the 1st
6107 *        received SDLC frame with a CRC error even when there is no
6108 *        CRC error. To get around this a small dummy from of 2 bytes
6109 *        is looped back when switching from async to sync mode.
6110 *
6111 * Arguments:                info                pointer to device instance data
6112 * Return Value:        None
6113 */
6114static void usc_loopback_frame( struct mgsl_struct *info )
6115{
6116        int i;
6117        unsigned long oldmode = info->params.mode;
6118
6119        info->params.mode = MGSL_MODE_HDLC;
6120        
6121        usc_DisableMasterIrqBit( info );
6122
6123        usc_set_sdlc_mode( info );
6124        usc_enable_loopback( info, 1 );
6125
6126        /* Write 16-bit Time Constant for BRG0 */
6127        usc_OutReg( info, TC0R, 0 );
6128        
6129        /* Channel Control Register (CCR)
6130         *
6131         * <15..14>        00        Don't use 32-bit Tx Control Blocks (TCBs)
6132         * <13>                0        Trigger Tx on SW Command Disabled
6133         * <12>                0        Flag Preamble Disabled
6134         * <11..10>        00        Preamble Length = 8-Bits
6135         * <9..8>        01        Preamble Pattern = flags
6136         * <7..6>        10        Don't use 32-bit Rx status Blocks (RSBs)
6137         * <5>                0        Trigger Rx on SW Command Disabled
6138         * <4..0>        0        reserved
6139         *
6140         *        0000 0001 0000 0000 = 0x0100
6141         */
6142
6143        usc_OutReg( info, CCR, 0x0100 );
6144
6145        /* SETUP RECEIVER */
6146        usc_RTCmd( info, RTCmd_PurgeRxFifo );
6147        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6148
6149        /* SETUP TRANSMITTER */
6150        /* Program the Transmit Character Length Register (TCLR) */
6151        /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6152        usc_OutReg( info, TCLR, 2 );
6153        usc_RTCmd( info, RTCmd_PurgeTxFifo );
6154
6155        /* unlatch Tx status bits, and start transmit channel. */
6156        usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6157        outw(0,info->io_base + DATAREG);
6158
6159        /* ENABLE TRANSMITTER */
6160        usc_TCmd( info, TCmd_SendFrame );
6161        usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6162                                                        
6163        /* WAIT FOR RECEIVE COMPLETE */
6164        for (i=0 ; i<1000 ; i++)
6165                if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6166                        break;
6167
6168        /* clear Internal Data loopback mode */
6169        usc_enable_loopback(info, 0);
6170
6171        usc_EnableMasterIrqBit(info);
6172
6173        info->params.mode = oldmode;
6174
6175}        /* end of usc_loopback_frame() */
6176
6177/* usc_set_sync_mode()        Programs the USC for SDLC communications.
6178 *
6179 * Arguments:                info        pointer to adapter info structure
6180 * Return Value:        None
6181 */
6182static void usc_set_sync_mode( struct mgsl_struct *info )
6183{
6184        usc_loopback_frame( info );
6185        usc_set_sdlc_mode( info );
6186
6187        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6188                /* Enable INTEN (Port 6, Bit12) */
6189                /* This connects the IRQ request signal to the ISA bus */
6190                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6191        }
6192
6193        usc_enable_aux_clock(info, info->params.clock_speed);
6194
6195        if (info->params.loopback)
6196                usc_enable_loopback(info,1);
6197
6198}        /* end of mgsl_set_sync_mode() */
6199
6200/* usc_set_txidle()        Set the HDLC idle mode for the transmitter.
6201 *
6202 * Arguments:                info        pointer to device instance data
6203 * Return Value:        None
6204 */
6205static void usc_set_txidle( struct mgsl_struct *info )
6206{
6207        u16 usc_idle_mode = IDLEMODE_FLAGS;
6208
6209        /* Map API idle mode to USC register bits */
6210
6211        switch( info->idle_mode ){
6212        case HDLC_TXIDLE_FLAGS:                        usc_idle_mode = IDLEMODE_FLAGS; break;
6213        case HDLC_TXIDLE_ALT_ZEROS_ONES:        usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6214        case HDLC_TXIDLE_ZEROS:                        usc_idle_mode = IDLEMODE_ZERO; break;
6215        case HDLC_TXIDLE_ONES:                        usc_idle_mode = IDLEMODE_ONE; break;
6216        case HDLC_TXIDLE_ALT_MARK_SPACE:        usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6217        case HDLC_TXIDLE_SPACE:                        usc_idle_mode = IDLEMODE_SPACE; break;
6218        case HDLC_TXIDLE_MARK:                        usc_idle_mode = IDLEMODE_MARK; break;
6219        }
6220
6221        info->usc_idle_mode = usc_idle_mode;
6222        //usc_OutReg(info, TCSR, usc_idle_mode);
6223        info->tcsr_value &= ~IDLEMODE_MASK;        /* clear idle mode bits */
6224        info->tcsr_value += usc_idle_mode;
6225        usc_OutReg(info, TCSR, info->tcsr_value);
6226
6227        /*
6228         * if SyncLink WAN adapter is running in external sync mode, the
6229         * transmitter has been set to Monosync in order to try to mimic
6230         * a true raw outbound bit stream. Monosync still sends an open/close
6231         * sync char at the start/end of a frame. Try to match those sync
6232         * patterns to the idle mode set here
6233         */
6234        if ( info->params.mode == MGSL_MODE_RAW ) {
6235                unsigned char syncpat = 0;
6236                switch( info->idle_mode ) {
6237                case HDLC_TXIDLE_FLAGS:
6238                        syncpat = 0x7e;
6239                        break;
6240                case HDLC_TXIDLE_ALT_ZEROS_ONES:
6241                        syncpat = 0x55;
6242                        break;
6243                case HDLC_TXIDLE_ZEROS:
6244                case HDLC_TXIDLE_SPACE:
6245                        syncpat = 0x00;
6246                        break;
6247                case HDLC_TXIDLE_ONES:
6248                case HDLC_TXIDLE_MARK:
6249                        syncpat = 0xff;
6250                        break;
6251                case HDLC_TXIDLE_ALT_MARK_SPACE:
6252                        syncpat = 0xaa;
6253                        break;
6254                }
6255
6256                usc_SetTransmitSyncChars(info,syncpat,syncpat);
6257        }
6258
6259}        /* end of usc_set_txidle() */
6260
6261/* usc_get_serial_signals()
6262 *
6263 *        Query the adapter for the state of the V24 status (input) signals.
6264 *
6265 * Arguments:                info        pointer to device instance data
6266 * Return Value:        None
6267 */
6268static void usc_get_serial_signals( struct mgsl_struct *info )
6269{
6270        u16 status;
6271
6272        /* clear all serial signals except DTR and RTS */
6273        info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6274
6275        /* Read the Misc Interrupt status Register (MISR) to get */
6276        /* the V24 status signals. */
6277
6278        status = usc_InReg( info, MISR );
6279
6280        /* set serial signal bits to reflect MISR */
6281
6282        if ( status & MISCSTATUS_CTS )
6283                info->serial_signals |= SerialSignal_CTS;
6284
6285        if ( status & MISCSTATUS_DCD )
6286                info->serial_signals |= SerialSignal_DCD;
6287
6288        if ( status & MISCSTATUS_RI )
6289                info->serial_signals |= SerialSignal_RI;
6290
6291        if ( status & MISCSTATUS_DSR )
6292                info->serial_signals |= SerialSignal_DSR;
6293
6294}        /* end of usc_get_serial_signals() */
6295
6296/* usc_set_serial_signals()
6297 *
6298 *        Set the state of DTR and RTS based on contents of
6299 *        serial_signals member of device extension.
6300 *        
6301 * Arguments:                info        pointer to device instance data
6302 * Return Value:        None
6303 */
6304static void usc_set_serial_signals( struct mgsl_struct *info )
6305{
6306        u16 Control;
6307        unsigned char V24Out = info->serial_signals;
6308
6309        /* get the current value of the Port Control Register (PCR) */
6310
6311        Control = usc_InReg( info, PCR );
6312
6313        if ( V24Out & SerialSignal_RTS )
6314                Control &= ~(BIT6);
6315        else
6316                Control |= BIT6;
6317
6318        if ( V24Out & SerialSignal_DTR )
6319                Control &= ~(BIT4);
6320        else
6321                Control |= BIT4;
6322
6323        usc_OutReg( info, PCR, Control );
6324
6325}        /* end of usc_set_serial_signals() */
6326
6327/* usc_enable_async_clock()
6328 *
6329 *        Enable the async clock at the specified frequency.
6330 *
6331 * Arguments:                info                pointer to device instance data
6332 *                        data_rate        data rate of clock in bps
6333 *                                        0 disables the AUX clock.
6334 * Return Value:        None
6335 */
6336static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6337{
6338        if ( data_rate )        {
6339                /*
6340                 * Clock mode Control Register (CMCR)
6341                 * 
6342                 * <15..14>     00      counter 1 Disabled
6343                 * <13..12>     00      counter 0 Disabled
6344                 * <11..10>     11      BRG1 Input is TxC Pin
6345                 * <9..8>       11      BRG0 Input is TxC Pin
6346                 * <7..6>       01      DPLL Input is BRG1 Output
6347                 * <5..3>       100     TxCLK comes from BRG0
6348                 * <2..0>       100     RxCLK comes from BRG0
6349                 *
6350                 * 0000 1111 0110 0100 = 0x0f64
6351                 */
6352                
6353                usc_OutReg( info, CMCR, 0x0f64 );
6354
6355
6356                /*
6357                 * Write 16-bit Time Constant for BRG0
6358                 * Time Constant = (ClkSpeed / data_rate) - 1
6359                 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6360                 */
6361
6362                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6363                        usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6364                else
6365                        usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6366
6367                
6368                /*
6369                 * Hardware Configuration Register (HCR)
6370                 * Clear Bit 1, BRG0 mode = Continuous
6371                 * Set Bit 0 to enable BRG0.
6372                 */
6373
6374                usc_OutReg( info, HCR,
6375                            (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6376
6377
6378                /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6379
6380                usc_OutReg( info, IOCR,
6381                            (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6382        } else {
6383                /* data rate == 0 so turn off BRG0 */
6384                usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6385        }
6386
6387}        /* end of usc_enable_async_clock() */
6388
6389/*
6390 * Buffer Structures:
6391 *
6392 * Normal memory access uses virtual addresses that can make discontiguous
6393 * physical memory pages appear to be contiguous in the virtual address
6394 * space (the processors memory mapping handles the conversions).
6395 *
6396 * DMA transfers require physically contiguous memory. This is because
6397 * the DMA system controller and DMA bus masters deal with memory using
6398 * only physical addresses.
6399 *
6400 * This causes a problem under Windows NT when large DMA buffers are
6401 * needed. Fragmentation of the nonpaged pool prevents allocations of
6402 * physically contiguous buffers larger than the PAGE_SIZE.
6403 *
6404 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6405 * allows DMA transfers to physically discontiguous buffers. Information
6406 * about each data transfer buffer is contained in a memory structure
6407 * called a 'buffer entry'. A list of buffer entries is maintained
6408 * to track and control the use of the data transfer buffers.
6409 *
6410 * To support this strategy we will allocate sufficient PAGE_SIZE
6411 * contiguous memory buffers to allow for the total required buffer
6412 * space.
6413 *
6414 * The 16C32 accesses the list of buffer entries using Bus Master
6415 * DMA. Control information is read from the buffer entries by the
6416 * 16C32 to control data transfers. status information is written to
6417 * the buffer entries by the 16C32 to indicate the status of completed
6418 * transfers.
6419 *
6420 * The CPU writes control information to the buffer entries to control
6421 * the 16C32 and reads status information from the buffer entries to
6422 * determine information about received and transmitted frames.
6423 *
6424 * Because the CPU and 16C32 (adapter) both need simultaneous access
6425 * to the buffer entries, the buffer entry memory is allocated with
6426 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6427 * entry list to PAGE_SIZE.
6428 *
6429 * The actual data buffers on the other hand will only be accessed
6430 * by the CPU or the adapter but not by both simultaneously. This allows
6431 * Scatter/Gather packet based DMA procedures for using physically
6432 * discontiguous pages.
6433 */
6434
6435/*
6436 * mgsl_reset_tx_dma_buffers()
6437 *
6438 *         Set the count for all transmit buffers to 0 to indicate the
6439 *         buffer is available for use and set the current buffer to the
6440 *         first buffer. This effectively makes all buffers free and
6441 *         discards any data in buffers.
6442 *
6443 * Arguments:                info        pointer to device instance data
6444 * Return Value:        None
6445 */
6446static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6447{
6448        unsigned int i;
6449
6450        for ( i = 0; i < info->tx_buffer_count; i++ ) {
6451                *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6452        }
6453
6454        info->current_tx_buffer = 0;
6455        info->start_tx_dma_buffer = 0;
6456        info->tx_dma_buffers_used = 0;
6457
6458        info->get_tx_holding_index = 0;
6459        info->put_tx_holding_index = 0;
6460        info->tx_holding_count = 0;
6461
6462}        /* end of mgsl_reset_tx_dma_buffers() */
6463
6464/*
6465 * num_free_tx_dma_buffers()
6466 *
6467 *         returns the number of free tx dma buffers available
6468 *
6469 * Arguments:                info        pointer to device instance data
6470 * Return Value:        number of free tx dma buffers
6471 */
6472static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6473{
6474        return info->tx_buffer_count - info->tx_dma_buffers_used;
6475}
6476
6477/*
6478 * mgsl_reset_rx_dma_buffers()
6479 * 
6480 *         Set the count for all receive buffers to DMABUFFERSIZE
6481 *         and set the current buffer to the first buffer. This effectively
6482 *         makes all buffers free and discards any data in buffers.
6483 * 
6484 * Arguments:                info        pointer to device instance data
6485 * Return Value:        None
6486 */
6487static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6488{
6489        unsigned int i;
6490
6491        for ( i = 0; i < info->rx_buffer_count; i++ ) {
6492                *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6493//                info->rx_buffer_list[i].count = DMABUFFERSIZE;
6494//                info->rx_buffer_list[i].status = 0;
6495        }
6496
6497        info->current_rx_buffer = 0;
6498
6499}        /* end of mgsl_reset_rx_dma_buffers() */
6500
6501/*
6502 * mgsl_free_rx_frame_buffers()
6503 * 
6504 *         Free the receive buffers used by a received SDLC
6505 *         frame such that the buffers can be reused.
6506 * 
6507 * Arguments:
6508 * 
6509 *         info                        pointer to device instance data
6510 *         StartIndex                index of 1st receive buffer of frame
6511 *         EndIndex                index of last receive buffer of frame
6512 * 
6513 * Return Value:        None
6514 */
6515static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6516{
6517        bool Done = false;
6518        DMABUFFERENTRY *pBufEntry;
6519        unsigned int Index;
6520
6521        /* Starting with 1st buffer entry of the frame clear the status */
6522        /* field and set the count field to DMA Buffer Size. */
6523
6524        Index = StartIndex;
6525
6526        while( !Done ) {
6527                pBufEntry = &(info->rx_buffer_list[Index]);
6528
6529                if ( Index == EndIndex ) {
6530                        /* This is the last buffer of the frame! */
6531                        Done = true;
6532                }
6533
6534                /* reset current buffer for reuse */
6535//                pBufEntry->status = 0;
6536//                pBufEntry->count = DMABUFFERSIZE;
6537                *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6538
6539                /* advance to next buffer entry in linked list */
6540                Index++;
6541                if ( Index == info->rx_buffer_count )
6542                        Index = 0;
6543        }
6544
6545        /* set current buffer to next buffer after last buffer of frame */
6546        info->current_rx_buffer = Index;
6547
6548}        /* end of free_rx_frame_buffers() */
6549
6550/* mgsl_get_rx_frame()
6551 * 
6552 *         This function attempts to return a received SDLC frame from the
6553 *         receive DMA buffers. Only frames received without errors are returned.
6554 *
6555 * Arguments:                 info        pointer to device extension
6556 * Return Value:        true if frame returned, otherwise false
6557 */
6558static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6559{
6560        unsigned int StartIndex, EndIndex;        /* index of 1st and last buffers of Rx frame */
6561        unsigned short status;
6562        DMABUFFERENTRY *pBufEntry;
6563        unsigned int framesize = 0;
6564        bool ReturnCode = false;
6565        unsigned long flags;
6566        struct tty_struct *tty = info->port.tty;
6567        bool return_frame = false;
6568        
6569        /*
6570         * current_rx_buffer points to the 1st buffer of the next available
6571         * receive frame. To find the last buffer of the frame look for
6572         * a non-zero status field in the buffer entries. (The status
6573         * field is set by the 16C32 after completing a receive frame.
6574         */
6575
6576        StartIndex = EndIndex = info->current_rx_buffer;
6577
6578        while( !info->rx_buffer_list[EndIndex].status ) {
6579                /*
6580                 * If the count field of the buffer entry is non-zero then
6581                 * this buffer has not been used. (The 16C32 clears the count
6582                 * field when it starts using the buffer.) If an unused buffer
6583                 * is encountered then there are no frames available.
6584                 */
6585
6586                if ( info->rx_buffer_list[EndIndex].count )
6587                        goto Cleanup;
6588
6589                /* advance to next buffer entry in linked list */
6590                EndIndex++;
6591                if ( EndIndex == info->rx_buffer_count )
6592                        EndIndex = 0;
6593
6594                /* if entire list searched then no frame available */
6595                if ( EndIndex == StartIndex ) {
6596                        /* If this occurs then something bad happened,
6597                         * all buffers have been 'used' but none mark
6598                         * the end of a frame. Reset buffers and receiver.
6599                         */
6600
6601                        if ( info->rx_enabled ){
6602                                spin_lock_irqsave(&info->irq_spinlock,flags);
6603                                usc_start_receiver(info);
6604                                spin_unlock_irqrestore(&info->irq_spinlock,flags);
6605                        }
6606                        goto Cleanup;
6607                }
6608        }
6609
6610
6611        /* check status of receive frame */
6612        
6613        status = info->rx_buffer_list[EndIndex].status;
6614
6615        if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6616                        RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6617                if ( status & RXSTATUS_SHORT_FRAME )
6618                        info->icount.rxshort++;
6619                else if ( status & RXSTATUS_ABORT )
6620                        info->icount.rxabort++;
6621                else if ( status & RXSTATUS_OVERRUN )
6622                        info->icount.rxover++;
6623                else {
6624                        info->icount.rxcrc++;
6625                        if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6626                                return_frame = true;
6627                }
6628                framesize = 0;
6629#if SYNCLINK_GENERIC_HDLC
6630                {
6631                        info->netdev->stats.rx_errors++;
6632                        info->netdev->stats.rx_frame_errors++;
6633                }
6634#endif
6635        } else
6636                return_frame = true;
6637
6638        if ( return_frame ) {
6639                /* receive frame has no errors, get frame size.
6640                 * The frame size is the starting value of the RCC (which was
6641                 * set to 0xffff) minus the ending value of the RCC (decremented
6642                 * once for each receive character) minus 2 for the 16-bit CRC.
6643                 */
6644
6645                framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6646
6647                /* adjust frame size for CRC if any */
6648                if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6649                        framesize -= 2;
6650                else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6651                        framesize -= 4;                
6652        }
6653
6654        if ( debug_level >= DEBUG_LEVEL_BH )
6655                printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6656                        __FILE__,__LINE__,info->device_name,status,framesize);
6657                        
6658        if ( debug_level >= DEBUG_LEVEL_DATA )
6659                mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6660                        min_t(int, framesize, DMABUFFERSIZE),0);
6661                
6662        if (framesize) {
6663                if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6664                                ((framesize+1) > info->max_frame_size) ) ||
6665                        (framesize > info->max_frame_size) )
6666                        info->icount.rxlong++;
6667                else {
6668                        /* copy dma buffer(s) to contiguous intermediate buffer */
6669                        int copy_count = framesize;
6670                        int index = StartIndex;
6671                        unsigned char *ptmp = info->intermediate_rxbuffer;
6672
6673                        if ( !(status & RXSTATUS_CRC_ERROR))
6674                        info->icount.rxok++;
6675                        
6676                        while(copy_count) {
6677                                int partial_count;
6678                                if ( copy_count > DMABUFFERSIZE )
6679                                        partial_count = DMABUFFERSIZE;
6680                                else
6681                                        partial_count = copy_count;
6682                        
6683                                pBufEntry = &(info->rx_buffer_list[index]);
6684                                memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6685                                ptmp += partial_count;
6686                                copy_count -= partial_count;
6687                                
6688                                if ( ++index == info->rx_buffer_count )
6689                                        index = 0;
6690                        }
6691
6692                        if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6693                                ++framesize;
6694                                *ptmp = (status & RXSTATUS_CRC_ERROR ?
6695                                                RX_CRC_ERROR :
6696                                                RX_OK);
6697
6698                                if ( debug_level >= DEBUG_LEVEL_DATA )
6699                                        printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6700                                                __FILE__,__LINE__,info->device_name,
6701                                                *ptmp);
6702                        }
6703
6704#if SYNCLINK_GENERIC_HDLC
6705                        if (info->netcount)
6706                                hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6707                        else
6708#endif
6709                                ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6710                }
6711        }
6712        /* Free the buffers used by this frame. */
6713        mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6714
6715        ReturnCode = true;
6716
6717Cleanup:
6718
6719        if ( info->rx_enabled && info->rx_overflow ) {
6720                /* The receiver needs to restarted because of 
6721                 * a receive overflow (buffer or FIFO). If the 
6722                 * receive buffers are now empty, then restart receiver.
6723                 */
6724
6725                if ( !info->rx_buffer_list[EndIndex].status &&
6726                        info->rx_buffer_list[EndIndex].count ) {
6727                        spin_lock_irqsave(&info->irq_spinlock,flags);
6728                        usc_start_receiver(info);
6729                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
6730                }
6731        }
6732
6733        return ReturnCode;
6734
6735}        /* end of mgsl_get_rx_frame() */
6736
6737/* mgsl_get_raw_rx_frame()
6738 *
6739 *             This function attempts to return a received frame from the
6740 *        receive DMA buffers when running in external loop mode. In this mode,
6741 *        we will return at most one DMABUFFERSIZE frame to the application.
6742 *        The USC receiver is triggering off of DCD going active to start a new
6743 *        frame, and DCD going inactive to terminate the frame (similar to
6744 *        processing a closing flag character).
6745 *
6746 *        In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6747 *        If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6748 *         status field and the RCC field will indicate the length of the
6749 *        entire received frame. We take this RCC field and get the modulus
6750 *        of RCC and DMABUFFERSIZE to determine if number of bytes in the
6751 *        last Rx DMA buffer and return that last portion of the frame.
6752 *
6753 * Arguments:                 info        pointer to device extension
6754 * Return Value:        true if frame returned, otherwise false
6755 */
6756static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6757{
6758        unsigned int CurrentIndex, NextIndex;
6759        unsigned short status;
6760        DMABUFFERENTRY *pBufEntry;
6761        unsigned int framesize = 0;
6762        bool ReturnCode = false;
6763        unsigned long flags;
6764        struct tty_struct *tty = info->port.tty;
6765
6766        /*
6767          * current_rx_buffer points to the 1st buffer of the next available
6768         * receive frame. The status field is set by the 16C32 after
6769         * completing a receive frame. If the status field of this buffer
6770         * is zero, either the USC is still filling this buffer or this
6771         * is one of a series of buffers making up a received frame.
6772         *
6773         * If the count field of this buffer is zero, the USC is either
6774         * using this buffer or has used this buffer. Look at the count
6775         * field of the next buffer. If that next buffer's count is
6776         * non-zero, the USC is still actively using the current buffer.
6777         * Otherwise, if the next buffer's count field is zero, the
6778         * current buffer is complete and the USC is using the next
6779         * buffer.
6780         */
6781        CurrentIndex = NextIndex = info->current_rx_buffer;
6782        ++NextIndex;
6783        if ( NextIndex == info->rx_buffer_count )
6784                NextIndex = 0;
6785
6786        if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6787                (info->rx_buffer_list[CurrentIndex].count == 0 &&
6788                        info->rx_buffer_list[NextIndex].count == 0)) {
6789                /*
6790                  * Either the status field of this dma buffer is non-zero
6791                 * (indicating the last buffer of a receive frame) or the next
6792                  * buffer is marked as in use -- implying this buffer is complete
6793                 * and an intermediate buffer for this received frame.
6794                  */
6795
6796                status = info->rx_buffer_list[CurrentIndex].status;
6797
6798                if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6799                                RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6800                        if ( status & RXSTATUS_SHORT_FRAME )
6801                                info->icount.rxshort++;
6802                        else if ( status & RXSTATUS_ABORT )
6803                                info->icount.rxabort++;
6804                        else if ( status & RXSTATUS_OVERRUN )
6805                                info->icount.rxover++;
6806                        else
6807                                info->icount.rxcrc++;
6808                        framesize = 0;
6809                } else {
6810                        /*
6811                         * A receive frame is available, get frame size and status.
6812                         *
6813                         * The frame size is the starting value of the RCC (which was
6814                         * set to 0xffff) minus the ending value of the RCC (decremented
6815                         * once for each receive character) minus 2 or 4 for the 16-bit
6816                         * or 32-bit CRC.
6817                         *
6818                         * If the status field is zero, this is an intermediate buffer.
6819                         * It's size is 4K.
6820                         *
6821                         * If the DMA Buffer Entry's Status field is non-zero, the
6822                         * receive operation completed normally (ie: DCD dropped). The
6823                         * RCC field is valid and holds the received frame size.
6824                         * It is possible that the RCC field will be zero on a DMA buffer
6825                         * entry with a non-zero status. This can occur if the total
6826                         * frame size (number of bytes between the time DCD goes active
6827                         * to the time DCD goes inactive) exceeds 65535 bytes. In this
6828                         * case the 16C32 has underrun on the RCC count and appears to
6829                         * stop updating this counter to let us know the actual received
6830                         * frame size. If this happens (non-zero status and zero RCC),
6831                         * simply return the entire RxDMA Buffer
6832                         */
6833                        if ( status ) {
6834                                /*
6835                                 * In the event that the final RxDMA Buffer is
6836                                 * terminated with a non-zero status and the RCC
6837                                 * field is zero, we interpret this as the RCC
6838                                 * having underflowed (received frame > 65535 bytes).
6839                                 *
6840                                 * Signal the event to the user by passing back
6841                                 * a status of RxStatus_CrcError returning the full
6842                                 * buffer and let the app figure out what data is
6843                                 * actually valid
6844                                 */
6845                                if ( info->rx_buffer_list[CurrentIndex].rcc )
6846                                        framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6847                                else
6848                                        framesize = DMABUFFERSIZE;
6849                        }
6850                        else
6851                                framesize = DMABUFFERSIZE;
6852                }
6853
6854                if ( framesize > DMABUFFERSIZE ) {
6855                        /*
6856                         * if running in raw sync mode, ISR handler for
6857                         * End Of Buffer events terminates all buffers at 4K.
6858                         * If this frame size is said to be >4K, get the
6859                         * actual number of bytes of the frame in this buffer.
6860                         */
6861                        framesize = framesize % DMABUFFERSIZE;
6862                }
6863
6864
6865                if ( debug_level >= DEBUG_LEVEL_BH )
6866                        printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6867                                __FILE__,__LINE__,info->device_name,status,framesize);
6868
6869                if ( debug_level >= DEBUG_LEVEL_DATA )
6870                        mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6871                                min_t(int, framesize, DMABUFFERSIZE),0);
6872
6873                if (framesize) {
6874                        /* copy dma buffer(s) to contiguous intermediate buffer */
6875                        /* NOTE: we never copy more than DMABUFFERSIZE bytes        */
6876
6877                        pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6878                        memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6879                        info->icount.rxok++;
6880
6881                        ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6882                }
6883
6884                /* Free the buffers used by this frame. */
6885                mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6886
6887                ReturnCode = true;
6888        }
6889
6890
6891        if ( info->rx_enabled && info->rx_overflow ) {
6892                /* The receiver needs to restarted because of
6893                 * a receive overflow (buffer or FIFO). If the
6894                 * receive buffers are now empty, then restart receiver.
6895                 */
6896
6897                if ( !info->rx_buffer_list[CurrentIndex].status &&
6898                        info->rx_buffer_list[CurrentIndex].count ) {
6899                        spin_lock_irqsave(&info->irq_spinlock,flags);
6900                        usc_start_receiver(info);
6901                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
6902                }
6903        }
6904
6905        return ReturnCode;
6906
6907}        /* end of mgsl_get_raw_rx_frame() */
6908
6909/* mgsl_load_tx_dma_buffer()
6910 * 
6911 *         Load the transmit DMA buffer with the specified data.
6912 * 
6913 * Arguments:
6914 * 
6915 *         info                pointer to device extension
6916 *         Buffer                pointer to buffer containing frame to load
6917 *         BufferSize        size in bytes of frame in Buffer
6918 * 
6919 * Return Value:         None
6920 */
6921static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6922                const char *Buffer, unsigned int BufferSize)
6923{
6924        unsigned short Copycount;
6925        unsigned int i = 0;
6926        DMABUFFERENTRY *pBufEntry;
6927        
6928        if ( debug_level >= DEBUG_LEVEL_DATA )
6929                mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6930
6931        if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6932                /* set CMR:13 to start transmit when
6933                 * next GoAhead (abort) is received
6934                 */
6935                 info->cmr_value |= BIT13;                          
6936        }
6937                
6938        /* begin loading the frame in the next available tx dma
6939         * buffer, remember it's starting location for setting
6940         * up tx dma operation
6941         */
6942        i = info->current_tx_buffer;
6943        info->start_tx_dma_buffer = i;
6944
6945        /* Setup the status and RCC (Frame Size) fields of the 1st */
6946        /* buffer entry in the transmit DMA buffer list. */
6947
6948        info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6949        info->tx_buffer_list[i].rcc    = BufferSize;
6950        info->tx_buffer_list[i].count  = BufferSize;
6951
6952        /* Copy frame data from 1st source buffer to the DMA buffers. */
6953        /* The frame data may span multiple DMA buffers. */
6954
6955        while( BufferSize ){
6956                /* Get a pointer to next DMA buffer entry. */
6957                pBufEntry = &info->tx_buffer_list[i++];
6958                        
6959                if ( i == info->tx_buffer_count )
6960                        i=0;
6961
6962                /* Calculate the number of bytes that can be copied from */
6963                /* the source buffer to this DMA buffer. */
6964                if ( BufferSize > DMABUFFERSIZE )
6965                        Copycount = DMABUFFERSIZE;
6966                else
6967                        Copycount = BufferSize;
6968
6969                /* Actually copy data from source buffer to DMA buffer. */
6970                /* Also set the data count for this individual DMA buffer. */
6971                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6972                        mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6973                else
6974                        memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6975
6976                pBufEntry->count = Copycount;
6977
6978                /* Advance source pointer and reduce remaining data count. */
6979                Buffer += Copycount;
6980                BufferSize -= Copycount;
6981
6982                ++info->tx_dma_buffers_used;
6983        }
6984
6985        /* remember next available tx dma buffer */
6986        info->current_tx_buffer = i;
6987
6988}        /* end of mgsl_load_tx_dma_buffer() */
6989
6990/*
6991 * mgsl_register_test()
6992 * 
6993 *         Performs a register test of the 16C32.
6994 *         
6995 * Arguments:                info        pointer to device instance data
6996 * Return Value:                true if test passed, otherwise false
6997 */
6998static bool mgsl_register_test( struct mgsl_struct *info )
6999{
7000        static unsigned short BitPatterns[] =
7001                { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7002        static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
7003        unsigned int i;
7004        bool rc = true;
7005        unsigned long flags;
7006
7007        spin_lock_irqsave(&info->irq_spinlock,flags);
7008        usc_reset(info);
7009
7010        /* Verify the reset state of some registers. */
7011
7012        if ( (usc_InReg( info, SICR ) != 0) ||
7013                  (usc_InReg( info, IVR  ) != 0) ||
7014                  (usc_InDmaReg( info, DIVR ) != 0) ){
7015                rc = false;
7016        }
7017
7018        if ( rc ){
7019                /* Write bit patterns to various registers but do it out of */
7020                /* sync, then read back and verify values. */
7021
7022                for ( i = 0 ; i < Patterncount ; i++ ) {
7023                        usc_OutReg( info, TC0R, BitPatterns[i] );
7024                        usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7025                        usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7026                        usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7027                        usc_OutReg( info, RSR,  BitPatterns[(i+4)%Patterncount] );
7028                        usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7029
7030                        if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7031                                  (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7032                                  (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7033                                  (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7034                                  (usc_InReg( info, RSR )  != BitPatterns[(i+4)%Patterncount]) ||
7035                                  (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7036                                rc = false;
7037                                break;
7038                        }
7039                }
7040        }
7041
7042        usc_reset(info);
7043        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7044
7045        return rc;
7046
7047}        /* end of mgsl_register_test() */
7048
7049/* mgsl_irq_test()         Perform interrupt test of the 16C32.
7050 * 
7051 * Arguments:                info        pointer to device instance data
7052 * Return Value:        true if test passed, otherwise false
7053 */
7054static bool mgsl_irq_test( struct mgsl_struct *info )
7055{
7056        unsigned long EndTime;
7057        unsigned long flags;
7058
7059        spin_lock_irqsave(&info->irq_spinlock,flags);
7060        usc_reset(info);
7061
7062        /*
7063         * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition. 
7064         * The ISR sets irq_occurred to true.
7065         */
7066
7067        info->irq_occurred = false;
7068
7069        /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7070        /* Enable INTEN (Port 6, Bit12) */
7071        /* This connects the IRQ request signal to the ISA bus */
7072        /* on the ISA adapter. This has no effect for the PCI adapter */
7073        usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7074
7075        usc_EnableMasterIrqBit(info);
7076        usc_EnableInterrupts(info, IO_PIN);
7077        usc_ClearIrqPendingBits(info, IO_PIN);
7078        
7079        usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7080        usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7081
7082        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7083
7084        EndTime=100;
7085        while( EndTime-- && !info->irq_occurred ) {
7086                msleep_interruptible(10);
7087        }
7088        
7089        spin_lock_irqsave(&info->irq_spinlock,flags);
7090        usc_reset(info);
7091        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7092        
7093        return info->irq_occurred;
7094
7095}        /* end of mgsl_irq_test() */
7096
7097/* mgsl_dma_test()
7098 * 
7099 *         Perform a DMA test of the 16C32. A small frame is
7100 *         transmitted via DMA from a transmit buffer to a receive buffer
7101 *         using single buffer DMA mode.
7102 *         
7103 * Arguments:                info        pointer to device instance data
7104 * Return Value:        true if test passed, otherwise false
7105 */
7106static bool mgsl_dma_test( struct mgsl_struct *info )
7107{
7108        unsigned short FifoLevel;
7109        unsigned long phys_addr;
7110        unsigned int FrameSize;
7111        unsigned int i;
7112        char *TmpPtr;
7113        bool rc = true;
7114        unsigned short status=0;
7115        unsigned long EndTime;
7116        unsigned long flags;
7117        MGSL_PARAMS tmp_params;
7118
7119        /* save current port options */
7120        memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7121        /* load default port options */
7122        memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7123        
7124#define TESTFRAMESIZE 40
7125
7126        spin_lock_irqsave(&info->irq_spinlock,flags);
7127        
7128        /* setup 16C32 for SDLC DMA transfer mode */
7129
7130        usc_reset(info);
7131        usc_set_sdlc_mode(info);
7132        usc_enable_loopback(info,1);
7133        
7134        /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7135         * field of the buffer entry after fetching buffer address. This
7136         * way we can detect a DMA failure for a DMA read (which should be
7137         * non-destructive to system memory) before we try and write to
7138         * memory (where a failure could corrupt system memory).
7139         */
7140
7141        /* Receive DMA mode Register (RDMR)
7142         * 
7143         * <15..14>        11        DMA mode = Linked List Buffer mode
7144         * <13>                1        RSBinA/L = store Rx status Block in List entry
7145         * <12>                0        1 = Clear count of List Entry after fetching
7146         * <11..10>        00        Address mode = Increment
7147         * <9>                1        Terminate Buffer on RxBound
7148         * <8>                0        Bus Width = 16bits
7149         * <7..0>                ?        status Bits (write as 0s)
7150         * 
7151         * 1110 0010 0000 0000 = 0xe200
7152         */
7153
7154        usc_OutDmaReg( info, RDMR, 0xe200 );
7155        
7156        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7157
7158
7159        /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7160
7161        FrameSize = TESTFRAMESIZE;
7162
7163        /* setup 1st transmit buffer entry: */
7164        /* with frame size and transmit control word */
7165
7166        info->tx_buffer_list[0].count  = FrameSize;
7167        info->tx_buffer_list[0].rcc    = FrameSize;
7168        info->tx_buffer_list[0].status = 0x4000;
7169
7170        /* build a transmit frame in 1st transmit DMA buffer */
7171
7172        TmpPtr = info->tx_buffer_list[0].virt_addr;
7173        for (i = 0; i < FrameSize; i++ )
7174                *TmpPtr++ = i;
7175
7176        /* setup 1st receive buffer entry: */
7177        /* clear status, set max receive buffer size */
7178
7179        info->rx_buffer_list[0].status = 0;
7180        info->rx_buffer_list[0].count = FrameSize + 4;
7181
7182        /* zero out the 1st receive buffer */
7183
7184        memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7185
7186        /* Set count field of next buffer entries to prevent */
7187        /* 16C32 from using buffers after the 1st one. */
7188
7189        info->tx_buffer_list[1].count = 0;
7190        info->rx_buffer_list[1].count = 0;
7191        
7192
7193        /***************************/
7194        /* Program 16C32 receiver. */
7195        /***************************/
7196        
7197        spin_lock_irqsave(&info->irq_spinlock,flags);
7198
7199        /* setup DMA transfers */
7200        usc_RTCmd( info, RTCmd_PurgeRxFifo );
7201
7202        /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7203        phys_addr = info->rx_buffer_list[0].phys_entry;
7204        usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7205        usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7206
7207        /* Clear the Rx DMA status bits (read RDMR) and start channel */
7208        usc_InDmaReg( info, RDMR );
7209        usc_DmaCmd( info, DmaCmd_InitRxChannel );
7210
7211        /* Enable Receiver (RMR <1..0> = 10) */
7212        usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7213        
7214        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7215
7216
7217        /*************************************************************/
7218        /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7219        /*************************************************************/
7220
7221        /* Wait 100ms for interrupt. */
7222        EndTime = jiffies + msecs_to_jiffies(100);
7223
7224        for(;;) {
7225                if (time_after(jiffies, EndTime)) {
7226                        rc = false;
7227                        break;
7228                }
7229
7230                spin_lock_irqsave(&info->irq_spinlock,flags);
7231                status = usc_InDmaReg( info, RDMR );
7232                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7233
7234                if ( !(status & BIT4) && (status & BIT5) ) {
7235                        /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7236                        /* BUSY  (BIT 5) is active (channel still active). */
7237                        /* This means the buffer entry read has completed. */
7238                        break;
7239                }
7240        }
7241
7242
7243        /******************************/
7244        /* Program 16C32 transmitter. */
7245        /******************************/
7246        
7247        spin_lock_irqsave(&info->irq_spinlock,flags);
7248
7249        /* Program the Transmit Character Length Register (TCLR) */
7250        /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7251
7252        usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7253        usc_RTCmd( info, RTCmd_PurgeTxFifo );
7254
7255        /* Program the address of the 1st DMA Buffer Entry in linked list */
7256
7257        phys_addr = info->tx_buffer_list[0].phys_entry;
7258        usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7259        usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7260
7261        /* unlatch Tx status bits, and start transmit channel. */
7262
7263        usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7264        usc_DmaCmd( info, DmaCmd_InitTxChannel );
7265
7266        /* wait for DMA controller to fill transmit FIFO */
7267
7268        usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7269        
7270        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7271
7272
7273        /**********************************/
7274        /* WAIT FOR TRANSMIT FIFO TO FILL */
7275        /**********************************/
7276        
7277        /* Wait 100ms */
7278        EndTime = jiffies + msecs_to_jiffies(100);
7279
7280        for(;;) {
7281                if (time_after(jiffies, EndTime)) {
7282                        rc = false;
7283                        break;
7284                }
7285
7286                spin_lock_irqsave(&info->irq_spinlock,flags);
7287                FifoLevel = usc_InReg(info, TICR) >> 8;
7288                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7289                        
7290                if ( FifoLevel < 16 )
7291                        break;
7292                else
7293                        if ( FrameSize < 32 ) {
7294                                /* This frame is smaller than the entire transmit FIFO */
7295                                /* so wait for the entire frame to be loaded. */
7296                                if ( FifoLevel <= (32 - FrameSize) )
7297                                        break;
7298                        }
7299        }
7300
7301
7302        if ( rc )
7303        {
7304                /* Enable 16C32 transmitter. */
7305
7306                spin_lock_irqsave(&info->irq_spinlock,flags);
7307                
7308                /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7309                usc_TCmd( info, TCmd_SendFrame );
7310                usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7311                
7312                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7313
7314                                                
7315                /******************************/
7316                /* WAIT FOR TRANSMIT COMPLETE */
7317                /******************************/
7318
7319                /* Wait 100ms */
7320                EndTime = jiffies + msecs_to_jiffies(100);
7321
7322                /* While timer not expired wait for transmit complete */
7323
7324                spin_lock_irqsave(&info->irq_spinlock,flags);
7325                status = usc_InReg( info, TCSR );
7326                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7327
7328                while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7329                        if (time_after(jiffies, EndTime)) {
7330                                rc = false;
7331                                break;
7332                        }
7333
7334                        spin_lock_irqsave(&info->irq_spinlock,flags);
7335                        status = usc_InReg( info, TCSR );
7336                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7337                }
7338        }
7339
7340
7341        if ( rc ){
7342                /* CHECK FOR TRANSMIT ERRORS */
7343                if ( status & (BIT5 + BIT1) ) 
7344                        rc = false;
7345        }
7346
7347        if ( rc ) {
7348                /* WAIT FOR RECEIVE COMPLETE */
7349
7350                /* Wait 100ms */
7351                EndTime = jiffies + msecs_to_jiffies(100);
7352
7353                /* Wait for 16C32 to write receive status to buffer entry. */
7354                status=info->rx_buffer_list[0].status;
7355                while ( status == 0 ) {
7356                        if (time_after(jiffies, EndTime)) {
7357                                rc = false;
7358                                break;
7359                        }
7360                        status=info->rx_buffer_list[0].status;
7361                }
7362        }
7363
7364
7365        if ( rc ) {
7366                /* CHECK FOR RECEIVE ERRORS */
7367                status = info->rx_buffer_list[0].status;
7368
7369                if ( status & (BIT8 + BIT3 + BIT1) ) {
7370                        /* receive error has occurred */
7371                        rc = false;
7372                } else {
7373                        if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7374                                info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7375                                rc = false;
7376                        }
7377                }
7378        }
7379
7380        spin_lock_irqsave(&info->irq_spinlock,flags);
7381        usc_reset( info );
7382        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7383
7384        /* restore current port options */
7385        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7386        
7387        return rc;
7388
7389}        /* end of mgsl_dma_test() */
7390
7391/* mgsl_adapter_test()
7392 * 
7393 *         Perform the register, IRQ, and DMA tests for the 16C32.
7394 *         
7395 * Arguments:                info        pointer to device instance data
7396 * Return Value:        0 if success, otherwise -ENODEV
7397 */
7398static int mgsl_adapter_test( struct mgsl_struct *info )
7399{
7400        if ( debug_level >= DEBUG_LEVEL_INFO )
7401                printk( "%s(%d):Testing device %s\n",
7402                        __FILE__,__LINE__,info->device_name );
7403                        
7404        if ( !mgsl_register_test( info ) ) {
7405                info->init_error = DiagStatus_AddressFailure;
7406                printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7407                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7408                return -ENODEV;
7409        }
7410
7411        if ( !mgsl_irq_test( info ) ) {
7412                info->init_error = DiagStatus_IrqFailure;
7413                printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7414                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7415                return -ENODEV;
7416        }
7417
7418        if ( !mgsl_dma_test( info ) ) {
7419                info->init_error = DiagStatus_DmaFailure;
7420                printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7421                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7422                return -ENODEV;
7423        }
7424
7425        if ( debug_level >= DEBUG_LEVEL_INFO )
7426                printk( "%s(%d):device %s passed diagnostics\n",
7427                        __FILE__,__LINE__,info->device_name );
7428                        
7429        return 0;
7430
7431}        /* end of mgsl_adapter_test() */
7432
7433/* mgsl_memory_test()
7434 * 
7435 *         Test the shared memory on a PCI adapter.
7436 * 
7437 * Arguments:                info        pointer to device instance data
7438 * Return Value:        true if test passed, otherwise false
7439 */
7440static bool mgsl_memory_test( struct mgsl_struct *info )
7441{
7442        static unsigned long BitPatterns[] =
7443                { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7444        unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7445        unsigned long i;
7446        unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7447        unsigned long * TestAddr;
7448
7449        if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7450                return true;
7451
7452        TestAddr = (unsigned long *)info->memory_base;
7453
7454        /* Test data lines with test pattern at one location. */
7455
7456        for ( i = 0 ; i < Patterncount ; i++ ) {