Showing error 1649

User: Jiri Slaby
Error type: Invalid Pointer Dereference
Error type description: A pointer which is invalid is being dereferenced
File location: drivers/serial/8250_pci.c
Line in file: 676
Project: Linux Kernel
Project version: 2.6.28
Tools: Smatch (1.59)
Entered: 2013-09-10 07:54:05 UTC

Source: 

   1/*
   2 *  linux/drivers/char/8250_pci.c
   3 *
   4 *  Probe module for 8250/16550-type PCI serial ports.
   5 *
   6 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7 *
   8 *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License.
  13 */
  14#include <linux/module.h>
  15#include <linux/init.h>
  16#include <linux/pci.h>
  17#include <linux/string.h>
  18#include <linux/kernel.h>
  19#include <linux/slab.h>
  20#include <linux/delay.h>
  21#include <linux/tty.h>
  22#include <linux/serial_core.h>
  23#include <linux/8250_pci.h>
  24#include <linux/bitops.h>
  25
  26#include <asm/byteorder.h>
  27#include <asm/io.h>
  28
  29#include "8250.h"
  30
  31#undef SERIAL_DEBUG_PCI
  32
  33/*
  34 * init function returns:
  35 *  > 0 - number of ports
  36 *  = 0 - use board->num_ports
  37 *  < 0 - error
  38 */
  39struct pci_serial_quirk {
  40        u32        vendor;
  41        u32        device;
  42        u32        subvendor;
  43        u32        subdevice;
  44        int        (*init)(struct pci_dev *dev);
  45        int        (*setup)(struct serial_private *, struct pciserial_board *,
  46                         struct uart_port *, int);
  47        void        (*exit)(struct pci_dev *dev);
  48};
  49
  50#define PCI_NUM_BAR_RESOURCES        6
  51
  52struct serial_private {
  53        struct pci_dev                *dev;
  54        unsigned int                nr;
  55        void __iomem                *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56        struct pci_serial_quirk        *quirk;
  57        int                        line[0];
  58};
  59
  60static void moan_device(const char *str, struct pci_dev *dev)
  61{
  62        printk(KERN_WARNING "%s: %s\n"
  63               KERN_WARNING "Please send the output of lspci -vv, this\n"
  64               KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  65               KERN_WARNING "manufacturer and name of serial board or\n"
  66               KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  67               pci_name(dev), str, dev->vendor, dev->device,
  68               dev->subsystem_vendor, dev->subsystem_device);
  69}
  70
  71static int
  72setup_port(struct serial_private *priv, struct uart_port *port,
  73           int bar, int offset, int regshift)
  74{
  75        struct pci_dev *dev = priv->dev;
  76        unsigned long base, len;
  77
  78        if (bar >= PCI_NUM_BAR_RESOURCES)
  79                return -EINVAL;
  80
  81        base = pci_resource_start(dev, bar);
  82
  83        if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  84                len =  pci_resource_len(dev, bar);
  85
  86                if (!priv->remapped_bar[bar])
  87                        priv->remapped_bar[bar] = ioremap_nocache(base, len);
  88                if (!priv->remapped_bar[bar])
  89                        return -ENOMEM;
  90
  91                port->iotype = UPIO_MEM;
  92                port->iobase = 0;
  93                port->mapbase = base + offset;
  94                port->membase = priv->remapped_bar[bar] + offset;
  95                port->regshift = regshift;
  96        } else {
  97                port->iotype = UPIO_PORT;
  98                port->iobase = base + offset;
  99                port->mapbase = 0;
 100                port->membase = NULL;
 101                port->regshift = 0;
 102        }
 103        return 0;
 104}
 105
 106/*
 107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
 108 */
 109static int addidata_apci7800_setup(struct serial_private *priv,
 110                                struct pciserial_board *board,
 111                                struct uart_port *port, int idx)
 112{
 113        unsigned int bar = 0, offset = board->first_offset;
 114        bar = FL_GET_BASE(board->flags);
 115
 116        if (idx < 2) {
 117                offset += idx * board->uart_offset;
 118        } else if ((idx >= 2) && (idx < 4)) {
 119                bar += 1;
 120                offset += ((idx - 2) * board->uart_offset);
 121        } else if ((idx >= 4) && (idx < 6)) {
 122                bar += 2;
 123                offset += ((idx - 4) * board->uart_offset);
 124        } else if (idx >= 6) {
 125                bar += 3;
 126                offset += ((idx - 6) * board->uart_offset);
 127        }
 128
 129        return setup_port(priv, port, bar, offset, board->reg_shift);
 130}
 131
 132/*
 133 * AFAVLAB uses a different mixture of BARs and offsets
 134 * Not that ugly ;) -- HW
 135 */
 136static int
 137afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 138              struct uart_port *port, int idx)
 139{
 140        unsigned int bar, offset = board->first_offset;
 141
 142        bar = FL_GET_BASE(board->flags);
 143        if (idx < 4)
 144                bar += idx;
 145        else {
 146                bar = 4;
 147                offset += (idx - 4) * board->uart_offset;
 148        }
 149
 150        return setup_port(priv, port, bar, offset, board->reg_shift);
 151}
 152
 153/*
 154 * HP's Remote Management Console.  The Diva chip came in several
 155 * different versions.  N-class, L2000 and A500 have two Diva chips, each
 156 * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 157 * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 158 * one Diva chip, but it has been expanded to 5 UARTs.
 159 */
 160static int pci_hp_diva_init(struct pci_dev *dev)
 161{
 162        int rc = 0;
 163
 164        switch (dev->subsystem_device) {
 165        case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 166        case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 167        case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 168        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 169                rc = 3;
 170                break;
 171        case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 172                rc = 2;
 173                break;
 174        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 175                rc = 4;
 176                break;
 177        case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 178        case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 179                rc = 1;
 180                break;
 181        }
 182
 183        return rc;
 184}
 185
 186/*
 187 * HP's Diva chip puts the 4th/5th serial port further out, and
 188 * some serial ports are supposed to be hidden on certain models.
 189 */
 190static int
 191pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 192              struct uart_port *port, int idx)
 193{
 194        unsigned int offset = board->first_offset;
 195        unsigned int bar = FL_GET_BASE(board->flags);
 196
 197        switch (priv->dev->subsystem_device) {
 198        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 199                if (idx == 3)
 200                        idx++;
 201                break;
 202        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 203                if (idx > 0)
 204                        idx++;
 205                if (idx > 2)
 206                        idx++;
 207                break;
 208        }
 209        if (idx > 2)
 210                offset = 0x18;
 211
 212        offset += idx * board->uart_offset;
 213
 214        return setup_port(priv, port, bar, offset, board->reg_shift);
 215}
 216
 217/*
 218 * Added for EKF Intel i960 serial boards
 219 */
 220static int pci_inteli960ni_init(struct pci_dev *dev)
 221{
 222        unsigned long oldval;
 223
 224        if (!(dev->subsystem_device & 0x1000))
 225                return -ENODEV;
 226
 227        /* is firmware started? */
 228        pci_read_config_dword(dev, 0x44, (void *)&oldval);
 229        if (oldval == 0x00001000L) { /* RESET value */
 230                printk(KERN_DEBUG "Local i960 firmware missing");
 231                return -ENODEV;
 232        }
 233        return 0;
 234}
 235
 236/*
 237 * Some PCI serial cards using the PLX 9050 PCI interface chip require
 238 * that the card interrupt be explicitly enabled or disabled.  This
 239 * seems to be mainly needed on card using the PLX which also use I/O
 240 * mapped memory.
 241 */
 242static int pci_plx9050_init(struct pci_dev *dev)
 243{
 244        u8 irq_config;
 245        void __iomem *p;
 246
 247        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 248                moan_device("no memory in bar 0", dev);
 249                return 0;
 250        }
 251
 252        irq_config = 0x41;
 253        if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 254            dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 255                irq_config = 0x43;
 256
 257        if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 258            (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 259                /*
 260                 * As the megawolf cards have the int pins active
 261                 * high, and have 2 UART chips, both ints must be
 262                 * enabled on the 9050. Also, the UARTS are set in
 263                 * 16450 mode by default, so we have to enable the
 264                 * 16C950 'enhanced' mode so that we can use the
 265                 * deep FIFOs
 266                 */
 267                irq_config = 0x5b;
 268        /*
 269         * enable/disable interrupts
 270         */
 271        p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 272        if (p == NULL)
 273                return -ENOMEM;
 274        writel(irq_config, p + 0x4c);
 275
 276        /*
 277         * Read the register back to ensure that it took effect.
 278         */
 279        readl(p + 0x4c);
 280        iounmap(p);
 281
 282        return 0;
 283}
 284
 285static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 286{
 287        u8 __iomem *p;
 288
 289        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 290                return;
 291
 292        /*
 293         * disable interrupts
 294         */
 295        p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 296        if (p != NULL) {
 297                writel(0, p + 0x4c);
 298
 299                /*
 300                 * Read the register back to ensure that it took effect.
 301                 */
 302                readl(p + 0x4c);
 303                iounmap(p);
 304        }
 305}
 306
 307/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 308static int
 309sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 310                struct uart_port *port, int idx)
 311{
 312        unsigned int bar, offset = board->first_offset;
 313
 314        bar = 0;
 315
 316        if (idx < 4) {
 317                /* first four channels map to 0, 0x100, 0x200, 0x300 */
 318                offset += idx * board->uart_offset;
 319        } else if (idx < 8) {
 320                /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 321                offset += idx * board->uart_offset + 0xC00;
 322        } else /* we have only 8 ports on PMC-OCTALPRO */
 323                return 1;
 324
 325        return setup_port(priv, port, bar, offset, board->reg_shift);
 326}
 327
 328/*
 329* This does initialization for PMC OCTALPRO cards:
 330* maps the device memory, resets the UARTs (needed, bc
 331* if the module is removed and inserted again, the card
 332* is in the sleep mode) and enables global interrupt.
 333*/
 334
 335/* global control register offset for SBS PMC-OctalPro */
 336#define OCT_REG_CR_OFF                0x500
 337
 338static int sbs_init(struct pci_dev *dev)
 339{
 340        u8 __iomem *p;
 341
 342        p = ioremap_nocache(pci_resource_start(dev, 0),
 343                                                pci_resource_len(dev, 0));
 344
 345        if (p == NULL)
 346                return -ENOMEM;
 347        /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 348        writeb(0x10, p + OCT_REG_CR_OFF);
 349        udelay(50);
 350        writeb(0x0, p + OCT_REG_CR_OFF);
 351
 352        /* Set bit-2 (INTENABLE) of Control Register */
 353        writeb(0x4, p + OCT_REG_CR_OFF);
 354        iounmap(p);
 355
 356        return 0;
 357}
 358
 359/*
 360 * Disables the global interrupt of PMC-OctalPro
 361 */
 362
 363static void __devexit sbs_exit(struct pci_dev *dev)
 364{
 365        u8 __iomem *p;
 366
 367        p = ioremap_nocache(pci_resource_start(dev, 0),
 368                                        pci_resource_len(dev, 0));
 369        /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 370        if (p != NULL)
 371                writeb(0, p + OCT_REG_CR_OFF);
 372        iounmap(p);
 373}
 374
 375/*
 376 * SIIG serial cards have an PCI interface chip which also controls
 377 * the UART clocking frequency. Each UART can be clocked independently
 378 * (except cards equiped with 4 UARTs) and initial clocking settings
 379 * are stored in the EEPROM chip. It can cause problems because this
 380 * version of serial driver doesn't support differently clocked UART's
 381 * on single PCI card. To prevent this, initialization functions set
 382 * high frequency clocking for all UART's on given card. It is safe (I
 383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
 384 * with other OSes (like M$ DOS).
 385 *
 386 *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 387 *
 388 * There is two family of SIIG serial cards with different PCI
 389 * interface chip and different configuration methods:
 390 *     - 10x cards have control registers in IO and/or memory space;
 391 *     - 20x cards have control registers in standard PCI configuration space.
 392 *
 393 * Note: all 10x cards have PCI device ids 0x10..
 394 *       all 20x cards have PCI device ids 0x20..
 395 *
 396 * There are also Quartet Serial cards which use Oxford Semiconductor
 397 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 398 *
 399 * Note: some SIIG cards are probed by the parport_serial object.
 400 */
 401
 402#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 403#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 404
 405static int pci_siig10x_init(struct pci_dev *dev)
 406{
 407        u16 data;
 408        void __iomem *p;
 409
 410        switch (dev->device & 0xfff8) {
 411        case PCI_DEVICE_ID_SIIG_1S_10x:        /* 1S */
 412                data = 0xffdf;
 413                break;
 414        case PCI_DEVICE_ID_SIIG_2S_10x:        /* 2S, 2S1P */
 415                data = 0xf7ff;
 416                break;
 417        default:                        /* 1S1P, 4S */
 418                data = 0xfffb;
 419                break;
 420        }
 421
 422        p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 423        if (p == NULL)
 424                return -ENOMEM;
 425
 426        writew(readw(p + 0x28) & data, p + 0x28);
 427        readw(p + 0x28);
 428        iounmap(p);
 429        return 0;
 430}
 431
 432#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 433#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 434
 435static int pci_siig20x_init(struct pci_dev *dev)
 436{
 437        u8 data;
 438
 439        /* Change clock frequency for the first UART. */
 440        pci_read_config_byte(dev, 0x6f, &data);
 441        pci_write_config_byte(dev, 0x6f, data & 0xef);
 442
 443        /* If this card has 2 UART, we have to do the same with second UART. */
 444        if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 445            ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 446                pci_read_config_byte(dev, 0x73, &data);
 447                pci_write_config_byte(dev, 0x73, data & 0xef);
 448        }
 449        return 0;
 450}
 451
 452static int pci_siig_init(struct pci_dev *dev)
 453{
 454        unsigned int type = dev->device & 0xff00;
 455
 456        if (type == 0x1000)
 457                return pci_siig10x_init(dev);
 458        else if (type == 0x2000)
 459                return pci_siig20x_init(dev);
 460
 461        moan_device("Unknown SIIG card", dev);
 462        return -ENODEV;
 463}
 464
 465static int pci_siig_setup(struct serial_private *priv,
 466                          struct pciserial_board *board,
 467                          struct uart_port *port, int idx)
 468{
 469        unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 470
 471        if (idx > 3) {
 472                bar = 4;
 473                offset = (idx - 4) * 8;
 474        }
 475
 476        return setup_port(priv, port, bar, offset, 0);
 477}
 478
 479/*
 480 * Timedia has an explosion of boards, and to avoid the PCI table from
 481 * growing *huge*, we use this function to collapse some 70 entries
 482 * in the PCI table into one, for sanity's and compactness's sake.
 483 */
 484static const unsigned short timedia_single_port[] = {
 485        0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 486};
 487
 488static const unsigned short timedia_dual_port[] = {
 489        0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 490        0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 491        0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 492        0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 493        0xD079, 0
 494};
 495
 496static const unsigned short timedia_quad_port[] = {
 497        0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 498        0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 499        0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 500        0xB157, 0
 501};
 502
 503static const unsigned short timedia_eight_port[] = {
 504        0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 505        0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 506};
 507
 508static const struct timedia_struct {
 509        int num;
 510        const unsigned short *ids;
 511} timedia_data[] = {
 512        { 1, timedia_single_port },
 513        { 2, timedia_dual_port },
 514        { 4, timedia_quad_port },
 515        { 8, timedia_eight_port }
 516};
 517
 518static int pci_timedia_init(struct pci_dev *dev)
 519{
 520        const unsigned short *ids;
 521        int i, j;
 522
 523        for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 524                ids = timedia_data[i].ids;
 525                for (j = 0; ids[j]; j++)
 526                        if (dev->subsystem_device == ids[j])
 527                                return timedia_data[i].num;
 528        }
 529        return 0;
 530}
 531
 532/*
 533 * Timedia/SUNIX uses a mixture of BARs and offsets
 534 * Ugh, this is ugly as all hell --- TYT
 535 */
 536static int
 537pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 538                  struct uart_port *port, int idx)
 539{
 540        unsigned int bar = 0, offset = board->first_offset;
 541
 542        switch (idx) {
 543        case 0:
 544                bar = 0;
 545                break;
 546        case 1:
 547                offset = board->uart_offset;
 548                bar = 0;
 549                break;
 550        case 2:
 551                bar = 1;
 552                break;
 553        case 3:
 554                offset = board->uart_offset;
 555                /* FALLTHROUGH */
 556        case 4: /* BAR 2 */
 557        case 5: /* BAR 3 */
 558        case 6: /* BAR 4 */
 559        case 7: /* BAR 5 */
 560                bar = idx - 2;
 561        }
 562
 563        return setup_port(priv, port, bar, offset, board->reg_shift);
 564}
 565
 566/*
 567 * Some Titan cards are also a little weird
 568 */
 569static int
 570titan_400l_800l_setup(struct serial_private *priv,
 571                      struct pciserial_board *board,
 572                      struct uart_port *port, int idx)
 573{
 574        unsigned int bar, offset = board->first_offset;
 575
 576        switch (idx) {
 577        case 0:
 578                bar = 1;
 579                break;
 580        case 1:
 581                bar = 2;
 582                break;
 583        default:
 584                bar = 4;
 585                offset = (idx - 2) * board->uart_offset;
 586        }
 587
 588        return setup_port(priv, port, bar, offset, board->reg_shift);
 589}
 590
 591static int pci_xircom_init(struct pci_dev *dev)
 592{
 593        msleep(100);
 594        return 0;
 595}
 596
 597static int pci_netmos_init(struct pci_dev *dev)
 598{
 599        /* subdevice 0x00PS means <P> parallel, <S> serial */
 600        unsigned int num_serial = dev->subsystem_device & 0xf;
 601
 602        if (num_serial == 0)
 603                return -ENODEV;
 604        return num_serial;
 605}
 606
 607/*
 608 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
 609 *
 610 * These chips are available with optionally one parallel port and up to
 611 * two serial ports. Unfortunately they all have the same product id.
 612 *
 613 * Basic configuration is done over a region of 32 I/O ports. The base
 614 * ioport is called INTA or INTC, depending on docs/other drivers.
 615 *
 616 * The region of the 32 I/O ports is configured in POSIO0R...
 617 */
 618
 619/* registers */
 620#define ITE_887x_MISCR                0x9c
 621#define ITE_887x_INTCBAR        0x78
 622#define ITE_887x_UARTBAR        0x7c
 623#define ITE_887x_PS0BAR                0x10
 624#define ITE_887x_POSIO0                0x60
 625
 626/* I/O space size */
 627#define ITE_887x_IOSIZE                32
 628/* I/O space size (bits 26-24; 8 bytes = 011b) */
 629#define ITE_887x_POSIO_IOSIZE_8                (3 << 24)
 630/* I/O space size (bits 26-24; 32 bytes = 101b) */
 631#define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 632/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 633#define ITE_887x_POSIO_SPEED                (3 << 29)
 634/* enable IO_Space bit */
 635#define ITE_887x_POSIO_ENABLE                (1 << 31)
 636
 637static int pci_ite887x_init(struct pci_dev *dev)
 638{
 639        /* inta_addr are the configuration addresses of the ITE */
 640        static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 641                                                        0x200, 0x280, 0 };
 642        int ret, i, type;
 643        struct resource *iobase = NULL;
 644        u32 miscr, uartbar, ioport;
 645
 646        /* search for the base-ioport */
 647        i = 0;
 648        while (inta_addr[i] && iobase == NULL) {
 649                iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 650                                                                "ite887x");
 651                if (iobase != NULL) {
 652                        /* write POSIO0R - speed | size | ioport */
 653                        pci_write_config_dword(dev, ITE_887x_POSIO0,
 654                                ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 655                                ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 656                        /* write INTCBAR - ioport */
 657                        pci_write_config_dword(dev, ITE_887x_INTCBAR,
 658                                                                inta_addr[i]);
 659                        ret = inb(inta_addr[i]);
 660                        if (ret != 0xff) {
 661                                /* ioport connected */
 662                                break;
 663                        }
 664                        release_region(iobase->start, ITE_887x_IOSIZE);
 665                        iobase = NULL;
 666                }
 667                i++;
 668        }
 669
 670        if (!inta_addr[i]) {
 671                printk(KERN_ERR "ite887x: could not find iobase\n");
 672                return -ENODEV;
 673        }
 674
 675        /* start of undocumented type checking (see parport_pc.c) */
 676        type = inb(iobase->start + 0x18) & 0x0f;
 677
 678        switch (type) {
 679        case 0x2:        /* ITE8871 (1P) */
 680        case 0xa:        /* ITE8875 (1P) */
 681                ret = 0;
 682                break;
 683        case 0xe:        /* ITE8872 (2S1P) */
 684                ret = 2;
 685                break;
 686        case 0x6:        /* ITE8873 (1S) */
 687                ret = 1;
 688                break;
 689        case 0x8:        /* ITE8874 (2S) */
 690                ret = 2;
 691                break;
 692        default:
 693                moan_device("Unknown ITE887x", dev);
 694                ret = -ENODEV;
 695        }
 696
 697        /* configure all serial ports */
 698        for (i = 0; i < ret; i++) {
 699                /* read the I/O port from the device */
 700                pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 701                                                                &ioport);
 702                ioport &= 0x0000FF00;        /* the actual base address */
 703                pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 704                        ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 705                        ITE_887x_POSIO_IOSIZE_8 | ioport);
 706
 707                /* write the ioport to the UARTBAR */
 708                pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 709                uartbar &= ~(0xffff << (16 * i));        /* clear half the reg */
 710                uartbar |= (ioport << (16 * i));        /* set the ioport */
 711                pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 712
 713                /* get current config */
 714                pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 715                /* disable interrupts (UARTx_Routing[3:0]) */
 716                miscr &= ~(0xf << (12 - 4 * i));
 717                /* activate the UART (UARTx_En) */
 718                miscr |= 1 << (23 - i);
 719                /* write new config with activated UART */
 720                pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 721        }
 722
 723        if (ret <= 0) {
 724                /* the device has no UARTs if we get here */
 725                release_region(iobase->start, ITE_887x_IOSIZE);
 726        }
 727
 728        return ret;
 729}
 730
 731static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 732{
 733        u32 ioport;
 734        /* the ioport is bit 0-15 in POSIO0R */
 735        pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 736        ioport &= 0xffff;
 737        release_region(ioport, ITE_887x_IOSIZE);
 738}
 739
 740static int
 741pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 742                  struct uart_port *port, int idx)
 743{
 744        unsigned int bar, offset = board->first_offset, maxnr;
 745
 746        bar = FL_GET_BASE(board->flags);
 747        if (board->flags & FL_BASE_BARS)
 748                bar += idx;
 749        else
 750                offset += idx * board->uart_offset;
 751
 752        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 753                (board->reg_shift + 3);
 754
 755        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 756                return 1;
 757
 758        return setup_port(priv, port, bar, offset, board->reg_shift);
 759}
 760
 761/* This should be in linux/pci_ids.h */
 762#define PCI_VENDOR_ID_SBSMODULARIO        0x124B
 763#define PCI_SUBVENDOR_ID_SBSMODULARIO        0x124B
 764#define PCI_DEVICE_ID_OCTPRO                0x0001
 765#define PCI_SUBDEVICE_ID_OCTPRO232        0x0108
 766#define PCI_SUBDEVICE_ID_OCTPRO422        0x0208
 767#define PCI_SUBDEVICE_ID_POCTAL232        0x0308
 768#define PCI_SUBDEVICE_ID_POCTAL422        0x0408
 769
 770/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
 771#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584        0x1584
 772
 773/*
 774 * Master list of serial port init/setup/exit quirks.
 775 * This does not describe the general nature of the port.
 776 * (ie, baud base, number and location of ports, etc)
 777 *
 778 * This list is ordered alphabetically by vendor then device.
 779 * Specific entries must come before more generic entries.
 780 */
 781static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 782        /*
 783        * ADDI-DATA GmbH communication cards <info@addi-data.com>
 784        */
 785        {
 786                .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
 787                .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
 788                .subvendor      = PCI_ANY_ID,
 789                .subdevice      = PCI_ANY_ID,
 790                .setup          = addidata_apci7800_setup,
 791        },
 792        /*
 793         * AFAVLAB cards - these may be called via parport_serial
 794         *  It is not clear whether this applies to all products.
 795         */
 796        {
 797                .vendor                = PCI_VENDOR_ID_AFAVLAB,
 798                .device                = PCI_ANY_ID,
 799                .subvendor        = PCI_ANY_ID,
 800                .subdevice        = PCI_ANY_ID,
 801                .setup                = afavlab_setup,
 802        },
 803        /*
 804         * HP Diva
 805         */
 806        {
 807                .vendor                = PCI_VENDOR_ID_HP,
 808                .device                = PCI_DEVICE_ID_HP_DIVA,
 809                .subvendor        = PCI_ANY_ID,
 810                .subdevice        = PCI_ANY_ID,
 811                .init                = pci_hp_diva_init,
 812                .setup                = pci_hp_diva_setup,
 813        },
 814        /*
 815         * Intel
 816         */
 817        {
 818                .vendor                = PCI_VENDOR_ID_INTEL,
 819                .device                = PCI_DEVICE_ID_INTEL_80960_RP,
 820                .subvendor        = 0xe4bf,
 821                .subdevice        = PCI_ANY_ID,
 822                .init                = pci_inteli960ni_init,
 823                .setup                = pci_default_setup,
 824        },
 825        /*
 826         * ITE
 827         */
 828        {
 829                .vendor                = PCI_VENDOR_ID_ITE,
 830                .device                = PCI_DEVICE_ID_ITE_8872,
 831                .subvendor        = PCI_ANY_ID,
 832                .subdevice        = PCI_ANY_ID,
 833                .init                = pci_ite887x_init,
 834                .setup                = pci_default_setup,
 835                .exit                = __devexit_p(pci_ite887x_exit),
 836        },
 837        /*
 838         * Panacom
 839         */
 840        {
 841                .vendor                = PCI_VENDOR_ID_PANACOM,
 842                .device                = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 843                .subvendor        = PCI_ANY_ID,
 844                .subdevice        = PCI_ANY_ID,
 845                .init                = pci_plx9050_init,
 846                .setup                = pci_default_setup,
 847                .exit                = __devexit_p(pci_plx9050_exit),
 848        },
 849        {
 850                .vendor                = PCI_VENDOR_ID_PANACOM,
 851                .device                = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 852                .subvendor        = PCI_ANY_ID,
 853                .subdevice        = PCI_ANY_ID,
 854                .init                = pci_plx9050_init,
 855                .setup                = pci_default_setup,
 856                .exit                = __devexit_p(pci_plx9050_exit),
 857        },
 858        /*
 859         * PLX
 860         */
 861        {
 862                .vendor                = PCI_VENDOR_ID_PLX,
 863                .device                = PCI_DEVICE_ID_PLX_9030,
 864                .subvendor        = PCI_SUBVENDOR_ID_PERLE,
 865                .subdevice        = PCI_ANY_ID,
 866                .setup                = pci_default_setup,
 867        },
 868        {
 869                .vendor                = PCI_VENDOR_ID_PLX,
 870                .device                = PCI_DEVICE_ID_PLX_9050,
 871                .subvendor        = PCI_SUBVENDOR_ID_EXSYS,
 872                .subdevice        = PCI_SUBDEVICE_ID_EXSYS_4055,
 873                .init                = pci_plx9050_init,
 874                .setup                = pci_default_setup,
 875                .exit                = __devexit_p(pci_plx9050_exit),
 876        },
 877        {
 878                .vendor                = PCI_VENDOR_ID_PLX,
 879                .device                = PCI_DEVICE_ID_PLX_9050,
 880                .subvendor        = PCI_SUBVENDOR_ID_KEYSPAN,
 881                .subdevice        = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 882                .init                = pci_plx9050_init,
 883                .setup                = pci_default_setup,
 884                .exit                = __devexit_p(pci_plx9050_exit),
 885        },
 886        {
 887                .vendor                = PCI_VENDOR_ID_PLX,
 888                .device                = PCI_DEVICE_ID_PLX_9050,
 889                .subvendor        = PCI_VENDOR_ID_PLX,
 890                .subdevice        = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
 891                .init                = pci_plx9050_init,
 892                .setup                = pci_default_setup,
 893                .exit                = __devexit_p(pci_plx9050_exit),
 894        },
 895        {
 896                .vendor                = PCI_VENDOR_ID_PLX,
 897                .device                = PCI_DEVICE_ID_PLX_ROMULUS,
 898                .subvendor        = PCI_VENDOR_ID_PLX,
 899                .subdevice        = PCI_DEVICE_ID_PLX_ROMULUS,
 900                .init                = pci_plx9050_init,
 901                .setup                = pci_default_setup,
 902                .exit                = __devexit_p(pci_plx9050_exit),
 903        },
 904        /*
 905         * SBS Technologies, Inc., PMC-OCTALPRO 232
 906         */
 907        {
 908                .vendor                = PCI_VENDOR_ID_SBSMODULARIO,
 909                .device                = PCI_DEVICE_ID_OCTPRO,
 910                .subvendor        = PCI_SUBVENDOR_ID_SBSMODULARIO,
 911                .subdevice        = PCI_SUBDEVICE_ID_OCTPRO232,
 912                .init                = sbs_init,
 913                .setup                = sbs_setup,
 914                .exit                = __devexit_p(sbs_exit),
 915        },
 916        /*
 917         * SBS Technologies, Inc., PMC-OCTALPRO 422
 918         */
 919        {
 920                .vendor                = PCI_VENDOR_ID_SBSMODULARIO,
 921                .device                = PCI_DEVICE_ID_OCTPRO,
 922                .subvendor        = PCI_SUBVENDOR_ID_SBSMODULARIO,
 923                .subdevice        = PCI_SUBDEVICE_ID_OCTPRO422,
 924                .init                = sbs_init,
 925                .setup                = sbs_setup,
 926                .exit                = __devexit_p(sbs_exit),
 927        },
 928        /*
 929         * SBS Technologies, Inc., P-Octal 232
 930         */
 931        {
 932                .vendor                = PCI_VENDOR_ID_SBSMODULARIO,
 933                .device                = PCI_DEVICE_ID_OCTPRO,
 934                .subvendor        = PCI_SUBVENDOR_ID_SBSMODULARIO,
 935                .subdevice        = PCI_SUBDEVICE_ID_POCTAL232,
 936                .init                = sbs_init,
 937                .setup                = sbs_setup,
 938                .exit                = __devexit_p(sbs_exit),
 939        },
 940        /*
 941         * SBS Technologies, Inc., P-Octal 422
 942         */
 943        {
 944                .vendor                = PCI_VENDOR_ID_SBSMODULARIO,
 945                .device                = PCI_DEVICE_ID_OCTPRO,
 946                .subvendor        = PCI_SUBVENDOR_ID_SBSMODULARIO,
 947                .subdevice        = PCI_SUBDEVICE_ID_POCTAL422,
 948                .init                = sbs_init,
 949                .setup                = sbs_setup,
 950                .exit                = __devexit_p(sbs_exit),
 951        },
 952        /*
 953         * SIIG cards - these may be called via parport_serial
 954         */
 955        {
 956                .vendor                = PCI_VENDOR_ID_SIIG,
 957                .device                = PCI_ANY_ID,
 958                .subvendor        = PCI_ANY_ID,
 959                .subdevice        = PCI_ANY_ID,
 960                .init                = pci_siig_init,
 961                .setup                = pci_siig_setup,
 962        },
 963        /*
 964         * Titan cards
 965         */
 966        {
 967                .vendor                = PCI_VENDOR_ID_TITAN,
 968                .device                = PCI_DEVICE_ID_TITAN_400L,
 969                .subvendor        = PCI_ANY_ID,
 970                .subdevice        = PCI_ANY_ID,
 971                .setup                = titan_400l_800l_setup,
 972        },
 973        {
 974                .vendor                = PCI_VENDOR_ID_TITAN,
 975                .device                = PCI_DEVICE_ID_TITAN_800L,
 976                .subvendor        = PCI_ANY_ID,
 977                .subdevice        = PCI_ANY_ID,
 978                .setup                = titan_400l_800l_setup,
 979        },
 980        /*
 981         * Timedia cards
 982         */
 983        {
 984                .vendor                = PCI_VENDOR_ID_TIMEDIA,
 985                .device                = PCI_DEVICE_ID_TIMEDIA_1889,
 986                .subvendor        = PCI_VENDOR_ID_TIMEDIA,
 987                .subdevice        = PCI_ANY_ID,
 988                .init                = pci_timedia_init,
 989                .setup                = pci_timedia_setup,
 990        },
 991        {
 992                .vendor                = PCI_VENDOR_ID_TIMEDIA,
 993                .device                = PCI_ANY_ID,
 994                .subvendor        = PCI_ANY_ID,
 995                .subdevice        = PCI_ANY_ID,
 996                .setup                = pci_timedia_setup,
 997        },
 998        /*
 999         * Xircom cards
1000         */
1001        {
1002                .vendor                = PCI_VENDOR_ID_XIRCOM,
1003                .device                = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1004                .subvendor        = PCI_ANY_ID,
1005                .subdevice        = PCI_ANY_ID,
1006                .init                = pci_xircom_init,
1007                .setup                = pci_default_setup,
1008        },
1009        /*
1010         * Netmos cards - these may be called via parport_serial
1011         */
1012        {
1013                .vendor                = PCI_VENDOR_ID_NETMOS,
1014                .device                = PCI_ANY_ID,
1015                .subvendor        = PCI_ANY_ID,
1016                .subdevice        = PCI_ANY_ID,
1017                .init                = pci_netmos_init,
1018                .setup                = pci_default_setup,
1019        },
1020        /*
1021         * Default "match everything" terminator entry
1022         */
1023        {
1024                .vendor                = PCI_ANY_ID,
1025                .device                = PCI_ANY_ID,
1026                .subvendor        = PCI_ANY_ID,
1027                .subdevice        = PCI_ANY_ID,
1028                .setup                = pci_default_setup,
1029        }
1030};
1031
1032static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1033{
1034        return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1035}
1036
1037static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1038{
1039        struct pci_serial_quirk *quirk;
1040
1041        for (quirk = pci_serial_quirks; ; quirk++)
1042                if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1043                    quirk_id_matches(quirk->device, dev->device) &&
1044                    quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1045                    quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1046                        break;
1047        return quirk;
1048}
1049
1050static inline int get_pci_irq(struct pci_dev *dev,
1051                                struct pciserial_board *board)
1052{
1053        if (board->flags & FL_NOIRQ)
1054                return 0;
1055        else
1056                return dev->irq;
1057}
1058
1059/*
1060 * This is the configuration table for all of the PCI serial boards
1061 * which we support.  It is directly indexed by the pci_board_num_t enum
1062 * value, which is encoded in the pci_device_id PCI probe table's
1063 * driver_data member.
1064 *
1065 * The makeup of these names are:
1066 *  pbn_bn{_bt}_n_baud{_offsetinhex}
1067 *
1068 *  bn                = PCI BAR number
1069 *  bt                = Index using PCI BARs
1070 *  n                = number of serial ports
1071 *  baud        = baud rate
1072 *  offsetinhex        = offset for each sequential port (in hex)
1073 *
1074 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1075 *
1076 * Please note: in theory if n = 1, _bt infix should make no difference.
1077 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1078 */
1079enum pci_board_num_t {
1080        pbn_default = 0,
1081
1082        pbn_b0_1_115200,
1083        pbn_b0_2_115200,
1084        pbn_b0_4_115200,
1085        pbn_b0_5_115200,
1086        pbn_b0_8_115200,
1087
1088        pbn_b0_1_921600,
1089        pbn_b0_2_921600,
1090        pbn_b0_4_921600,
1091
1092        pbn_b0_2_1130000,
1093
1094        pbn_b0_4_1152000,
1095
1096        pbn_b0_2_1843200,
1097        pbn_b0_4_1843200,
1098
1099        pbn_b0_2_1843200_200,
1100        pbn_b0_4_1843200_200,
1101        pbn_b0_8_1843200_200,
1102
1103        pbn_b0_1_4000000,
1104
1105        pbn_b0_bt_1_115200,
1106        pbn_b0_bt_2_115200,
1107        pbn_b0_bt_8_115200,
1108
1109        pbn_b0_bt_1_460800,
1110        pbn_b0_bt_2_460800,
1111        pbn_b0_bt_4_460800,
1112
1113        pbn_b0_bt_1_921600,
1114        pbn_b0_bt_2_921600,
1115        pbn_b0_bt_4_921600,
1116        pbn_b0_bt_8_921600,
1117
1118        pbn_b1_1_115200,
1119        pbn_b1_2_115200,
1120        pbn_b1_4_115200,
1121        pbn_b1_8_115200,
1122
1123        pbn_b1_1_921600,
1124        pbn_b1_2_921600,
1125        pbn_b1_4_921600,
1126        pbn_b1_8_921600,
1127
1128        pbn_b1_2_1250000,
1129
1130        pbn_b1_bt_1_115200,
1131        pbn_b1_bt_2_921600,
1132
1133        pbn_b1_1_1382400,
1134        pbn_b1_2_1382400,
1135        pbn_b1_4_1382400,
1136        pbn_b1_8_1382400,
1137
1138        pbn_b2_1_115200,
1139        pbn_b2_2_115200,
1140        pbn_b2_4_115200,
1141        pbn_b2_8_115200,
1142
1143        pbn_b2_1_460800,
1144        pbn_b2_4_460800,
1145        pbn_b2_8_460800,
1146        pbn_b2_16_460800,
1147
1148        pbn_b2_1_921600,
1149        pbn_b2_4_921600,
1150        pbn_b2_8_921600,
1151
1152        pbn_b2_bt_1_115200,
1153        pbn_b2_bt_2_115200,
1154        pbn_b2_bt_4_115200,
1155
1156        pbn_b2_bt_2_921600,
1157        pbn_b2_bt_4_921600,
1158
1159        pbn_b3_2_115200,
1160        pbn_b3_4_115200,
1161        pbn_b3_8_115200,
1162
1163        /*
1164         * Board-specific versions.
1165         */
1166        pbn_panacom,
1167        pbn_panacom2,
1168        pbn_panacom4,
1169        pbn_exsys_4055,
1170        pbn_plx_romulus,
1171        pbn_oxsemi,
1172        pbn_oxsemi_1_4000000,
1173        pbn_oxsemi_2_4000000,
1174        pbn_oxsemi_4_4000000,
1175        pbn_oxsemi_8_4000000,
1176        pbn_intel_i960,
1177        pbn_sgi_ioc3,
1178        pbn_computone_4,
1179        pbn_computone_6,
1180        pbn_computone_8,
1181        pbn_sbsxrsio,
1182        pbn_exar_XR17C152,
1183        pbn_exar_XR17C154,
1184        pbn_exar_XR17C158,
1185        pbn_pasemi_1682M,
1186};
1187
1188/*
1189 * uart_offset - the space between channels
1190 * reg_shift   - describes how the UART registers are mapped
1191 *               to PCI memory by the card.
1192 * For example IER register on SBS, Inc. PMC-OctPro is located at
1193 * offset 0x10 from the UART base, while UART_IER is defined as 1
1194 * in include/linux/serial_reg.h,
1195 * see first lines of serial_in() and serial_out() in 8250.c
1196*/
1197
1198static struct pciserial_board pci_boards[] __devinitdata = {
1199        [pbn_default] = {
1200                .flags                = FL_BASE0,
1201                .num_ports        = 1,
1202                .base_baud        = 115200,
1203                .uart_offset        = 8,
1204        },
1205        [pbn_b0_1_115200] = {
1206                .flags                = FL_BASE0,
1207                .num_ports        = 1,
1208                .base_baud        = 115200,
1209                .uart_offset        = 8,
1210        },
1211        [pbn_b0_2_115200] = {
1212                .flags                = FL_BASE0,
1213                .num_ports        = 2,
1214                .base_baud        = 115200,
1215                .uart_offset        = 8,
1216        },
1217        [pbn_b0_4_115200] = {
1218                .flags                = FL_BASE0,
1219                .num_ports        = 4,
1220                .base_baud        = 115200,
1221                .uart_offset        = 8,
1222        },
1223        [pbn_b0_5_115200] = {
1224                .flags                = FL_BASE0,
1225                .num_ports        = 5,
1226                .base_baud        = 115200,
1227                .uart_offset        = 8,
1228        },
1229        [pbn_b0_8_115200] = {
1230                .flags                = FL_BASE0,
1231                .num_ports        = 8,
1232                .base_baud        = 115200,
1233                .uart_offset        = 8,
1234        },
1235        [pbn_b0_1_921600] = {
1236                .flags                = FL_BASE0,
1237                .num_ports        = 1,
1238                .base_baud        = 921600,
1239                .uart_offset        = 8,
1240        },
1241        [pbn_b0_2_921600] = {
1242                .flags                = FL_BASE0,
1243                .num_ports        = 2,
1244                .base_baud        = 921600,
1245                .uart_offset        = 8,
1246        },
1247        [pbn_b0_4_921600] = {
1248                .flags                = FL_BASE0,
1249                .num_ports        = 4,
1250                .base_baud        = 921600,
1251                .uart_offset        = 8,
1252        },
1253
1254        [pbn_b0_2_1130000] = {
1255                .flags          = FL_BASE0,
1256                .num_ports      = 2,
1257                .base_baud      = 1130000,
1258                .uart_offset    = 8,
1259        },
1260
1261        [pbn_b0_4_1152000] = {
1262                .flags                = FL_BASE0,
1263                .num_ports        = 4,
1264                .base_baud        = 1152000,
1265                .uart_offset        = 8,
1266        },
1267
1268        [pbn_b0_2_1843200] = {
1269                .flags                = FL_BASE0,
1270                .num_ports        = 2,
1271                .base_baud        = 1843200,
1272                .uart_offset        = 8,
1273        },
1274        [pbn_b0_4_1843200] = {
1275                .flags                = FL_BASE0,
1276                .num_ports        = 4,
1277                .base_baud        = 1843200,
1278                .uart_offset        = 8,
1279        },
1280
1281        [pbn_b0_2_1843200_200] = {
1282                .flags                = FL_BASE0,
1283                .num_ports        = 2,
1284                .base_baud        = 1843200,
1285                .uart_offset        = 0x200,
1286        },
1287        [pbn_b0_4_1843200_200] = {
1288                .flags                = FL_BASE0,
1289                .num_ports        = 4,
1290                .base_baud        = 1843200,
1291                .uart_offset        = 0x200,
1292        },
1293        [pbn_b0_8_1843200_200] = {
1294                .flags                = FL_BASE0,
1295                .num_ports        = 8,
1296                .base_baud        = 1843200,
1297                .uart_offset        = 0x200,
1298        },
1299        [pbn_b0_1_4000000] = {
1300                .flags                = FL_BASE0,
1301                .num_ports        = 1,
1302                .base_baud        = 4000000,
1303                .uart_offset        = 8,
1304        },
1305
1306        [pbn_b0_bt_1_115200] = {
1307                .flags                = FL_BASE0|FL_BASE_BARS,
1308                .num_ports        = 1,
1309                .base_baud        = 115200,
1310                .uart_offset        = 8,
1311        },
1312        [pbn_b0_bt_2_115200] = {
1313                .flags                = FL_BASE0|FL_BASE_BARS,
1314                .num_ports        = 2,
1315                .base_baud        = 115200,
1316                .uart_offset        = 8,
1317        },
1318        [pbn_b0_bt_8_115200] = {
1319                .flags                = FL_BASE0|FL_BASE_BARS,
1320                .num_ports        = 8,
1321                .base_baud        = 115200,
1322                .uart_offset        = 8,
1323        },
1324
1325        [pbn_b0_bt_1_460800] = {
1326                .flags                = FL_BASE0|FL_BASE_BARS,
1327                .num_ports        = 1,
1328                .base_baud        = 460800,
1329                .uart_offset        = 8,
1330        },
1331        [pbn_b0_bt_2_460800] = {
1332                .flags                = FL_BASE0|FL_BASE_BARS,
1333                .num_ports        = 2,
1334                .base_baud        = 460800,
1335                .uart_offset        = 8,
1336        },
1337        [pbn_b0_bt_4_460800] = {
1338                .flags                = FL_BASE0|FL_BASE_BARS,
1339                .num_ports        = 4,
1340                .base_baud        = 460800,
1341                .uart_offset        = 8,
1342        },
1343
1344        [pbn_b0_bt_1_921600] = {
1345                .flags                = FL_BASE0|FL_BASE_BARS,
1346                .num_ports        = 1,
1347                .base_baud        = 921600,
1348                .uart_offset        = 8,
1349        },
1350        [pbn_b0_bt_2_921600] = {
1351                .flags                = FL_BASE0|FL_BASE_BARS,
1352                .num_ports        = 2,
1353                .base_baud        = 921600,
1354                .uart_offset        = 8,
1355        },
1356        [pbn_b0_bt_4_921600] = {
1357                .flags                = FL_BASE0|FL_BASE_BARS,
1358                .num_ports        = 4,
1359                .base_baud        = 921600,
1360                .uart_offset        = 8,
1361        },
1362        [pbn_b0_bt_8_921600] = {
1363                .flags                = FL_BASE0|FL_BASE_BARS,
1364                .num_ports        = 8,
1365                .base_baud        = 921600,
1366                .uart_offset        = 8,
1367        },
1368
1369        [pbn_b1_1_115200] = {
1370                .flags                = FL_BASE1,
1371                .num_ports        = 1,
1372                .base_baud        = 115200,
1373                .uart_offset        = 8,
1374        },
1375        [pbn_b1_2_115200] = {
1376                .flags                = FL_BASE1,
1377                .num_ports        = 2,
1378                .base_baud        = 115200,
1379                .uart_offset        = 8,
1380        },
1381        [pbn_b1_4_115200] = {
1382                .flags                = FL_BASE1,
1383                .num_ports        = 4,
1384                .base_baud        = 115200,
1385                .uart_offset        = 8,
1386        },
1387        [pbn_b1_8_115200] = {
1388                .flags                = FL_BASE1,
1389                .num_ports        = 8,
1390                .base_baud        = 115200,
1391                .uart_offset        = 8,
1392        },
1393
1394        [pbn_b1_1_921600] = {
1395                .flags                = FL_BASE1,
1396                .num_ports        = 1,
1397                .base_baud        = 921600,
1398                .uart_offset        = 8,
1399        },
1400        [pbn_b1_2_921600] = {
1401                .flags                = FL_BASE1,
1402                .num_ports        = 2,
1403                .base_baud        = 921600,
1404                .uart_offset        = 8,
1405        },
1406        [pbn_b1_4_921600] = {
1407                .flags                = FL_BASE1,
1408                .num_ports        = 4,
1409                .base_baud        = 921600,
1410                .uart_offset        = 8,
1411        },
1412        [pbn_b1_8_921600] = {
1413                .flags                = FL_BASE1,
1414                .num_ports        = 8,
1415                .base_baud        = 921600,
1416                .uart_offset        = 8,
1417        },
1418        [pbn_b1_2_1250000] = {
1419                .flags                = FL_BASE1,
1420                .num_ports        = 2,
1421                .base_baud        = 1250000,
1422                .uart_offset        = 8,
1423        },
1424
1425        [pbn_b1_bt_1_115200] = {
1426                .flags                = FL_BASE1|FL_BASE_BARS,
1427                .num_ports        = 1,
1428                .base_baud        = 115200,
1429                .uart_offset        = 8,
1430        },
1431
1432        [pbn_b1_bt_2_921600] = {
1433                .flags                = FL_BASE1|FL_BASE_BARS,
1434                .num_ports        = 2,
1435                .base_baud        = 921600,
1436                .uart_offset        = 8,
1437        },
1438
1439        [pbn_b1_1_1382400] = {
1440                .flags                = FL_BASE1,
1441                .num_ports        = 1,
1442                .base_baud        = 1382400,
1443                .uart_offset        = 8,
1444        },
1445        [pbn_b1_2_1382400] = {
1446                .flags                = FL_BASE1,
1447                .num_ports        = 2,
1448                .base_baud        = 1382400,
1449                .uart_offset        = 8,
1450        },
1451        [pbn_b1_4_1382400] = {
1452                .flags                = FL_BASE1,
1453                .num_ports        = 4,
1454                .base_baud        = 1382400,
1455                .uart_offset        = 8,
1456        },
1457        [pbn_b1_8_1382400] = {
1458                .flags                = FL_BASE1,
1459                .num_ports        = 8,
1460                .base_baud        = 1382400,
1461                .uart_offset        = 8,
1462        },
1463
1464        [pbn_b2_1_115200] = {
1465                .flags                = FL_BASE2,
1466                .num_ports        = 1,
1467                .base_baud        = 115200,
1468                .uart_offset        = 8,
1469        },
1470        [pbn_b2_2_115200] = {
1471                .flags                = FL_BASE2,
1472                .num_ports        = 2,
1473                .base_baud        = 115200,
1474                .uart_offset        = 8,
1475        },
1476        [pbn_b2_4_115200] = {
1477                .flags          = FL_BASE2,
1478                .num_ports      = 4,
1479                .base_baud      = 115200,
1480                .uart_offset    = 8,
1481        },
1482        [pbn_b2_8_115200] = {
1483                .flags                = FL_BASE2,
1484                .num_ports        = 8,
1485                .base_baud        = 115200,
1486                .uart_offset        = 8,
1487        },
1488
1489        [pbn_b2_1_460800] = {
1490                .flags                = FL_BASE2,
1491                .num_ports        = 1,
1492                .base_baud        = 460800,
1493                .uart_offset        = 8,
1494        },
1495        [pbn_b2_4_460800] = {
1496                .flags                = FL_BASE2,
1497                .num_ports        = 4,
1498                .base_baud        = 460800,
1499                .uart_offset        = 8,
1500        },
1501        [pbn_b2_8_460800] = {
1502                .flags                = FL_BASE2,
1503                .num_ports        = 8,
1504                .base_baud        = 460800,
1505                .uart_offset        = 8,
1506        },
1507        [pbn_b2_16_460800] = {
1508                .flags                = FL_BASE2,
1509                .num_ports        = 16,
1510                .base_baud        = 460800,
1511                .uart_offset        = 8,
1512         },
1513
1514        [pbn_b2_1_921600] = {
1515                .flags                = FL_BASE2,
1516                .num_ports        = 1,
1517                .base_baud        = 921600,
1518                .uart_offset        = 8,
1519        },
1520        [pbn_b2_4_921600] = {
1521                .flags                = FL_BASE2,
1522                .num_ports        = 4,
1523                .base_baud        = 921600,
1524                .uart_offset        = 8,
1525        },
1526        [pbn_b2_8_921600] = {
1527                .flags                = FL_BASE2,
1528                .num_ports        = 8,
1529                .base_baud        = 921600,
1530                .uart_offset        = 8,
1531        },
1532
1533        [pbn_b2_bt_1_115200] = {
1534                .flags                = FL_BASE2|FL_BASE_BARS,
1535                .num_ports        = 1,
1536                .base_baud        = 115200,
1537                .uart_offset        = 8,
1538        },
1539        [pbn_b2_bt_2_115200] = {
1540                .flags                = FL_BASE2|FL_BASE_BARS,
1541                .num_ports        = 2,
1542                .base_baud        = 115200,
1543                .uart_offset        = 8,
1544        },
1545        [pbn_b2_bt_4_115200] = {
1546                .flags                = FL_BASE2|FL_BASE_BARS,
1547                .num_ports        = 4,
1548                .base_baud        = 115200,
1549                .uart_offset        = 8,
1550        },
1551
1552        [pbn_b2_bt_2_921600] = {
1553                .flags                = FL_BASE2|FL_BASE_BARS,
1554                .num_ports        = 2,
1555                .base_baud        = 921600,
1556                .uart_offset        = 8,
1557        },
1558        [pbn_b2_bt_4_921600] = {
1559                .flags                = FL_BASE2|FL_BASE_BARS,
1560                .num_ports        = 4,
1561                .base_baud        = 921600,
1562                .uart_offset        = 8,
1563        },
1564
1565        [pbn_b3_2_115200] = {
1566                .flags                = FL_BASE3,
1567                .num_ports        = 2,
1568                .base_baud        = 115200,
1569                .uart_offset        = 8,
1570        },
1571        [pbn_b3_4_115200] = {
1572                .flags                = FL_BASE3,
1573                .num_ports        = 4,
1574                .base_baud        = 115200,
1575                .uart_offset        = 8,
1576        },
1577        [pbn_b3_8_115200] = {
1578                .flags                = FL_BASE3,
1579                .num_ports        = 8,
1580                .base_baud        = 115200,
1581                .uart_offset        = 8,
1582        },
1583
1584        /*
1585         * Entries following this are board-specific.
1586         */
1587
1588        /*
1589         * Panacom - IOMEM
1590         */
1591        [pbn_panacom] = {
1592                .flags                = FL_BASE2,
1593                .num_ports        = 2,
1594                .base_baud        = 921600,
1595                .uart_offset        = 0x400,
1596                .reg_shift        = 7,
1597        },
1598        [pbn_panacom2] = {
1599                .flags                = FL_BASE2|FL_BASE_BARS,
1600                .num_ports        = 2,
1601                .base_baud        = 921600,
1602                .uart_offset        = 0x400,
1603                .reg_shift        = 7,
1604        },
1605        [pbn_panacom4] = {
1606                .flags                = FL_BASE2|FL_BASE_BARS,
1607                .num_ports        = 4,
1608                .base_baud        = 921600,
1609                .uart_offset        = 0x400,
1610                .reg_shift        = 7,
1611        },
1612
1613        [pbn_exsys_4055] = {
1614                .flags                = FL_BASE2,
1615                .num_ports        = 4,
1616                .base_baud        = 115200,
1617                .uart_offset        = 8,
1618        },
1619
1620        /* I think this entry is broken - the first_offset looks wrong --rmk */
1621        [pbn_plx_romulus] = {
1622                .flags                = FL_BASE2,
1623                .num_ports        = 4,
1624                .base_baud        = 921600,
1625                .uart_offset        = 8 << 2,
1626                .reg_shift        = 2,
1627                .first_offset        = 0x03,
1628        },
1629
1630        /*
1631         * This board uses the size of PCI Base region 0 to
1632         * signal now many ports are available
1633         */
1634        [pbn_oxsemi] = {
1635                .flags                = FL_BASE0|FL_REGION_SZ_CAP,
1636                .num_ports        = 32,
1637                .base_baud        = 115200,
1638                .uart_offset        = 8,
1639        },
1640        [pbn_oxsemi_1_4000000] = {
1641                .flags                = FL_BASE0,
1642                .num_ports        = 1,
1643                .base_baud        = 4000000,
1644                .uart_offset        = 0x200,
1645                .first_offset        = 0x1000,
1646        },
1647        [pbn_oxsemi_2_4000000] = {
1648                .flags                = FL_BASE0,
1649                .num_ports        = 2,
1650                .base_baud        = 4000000,
1651                .uart_offset        = 0x200,
1652                .first_offset        = 0x1000,
1653        },
1654        [pbn_oxsemi_4_4000000] = {
1655                .flags                = FL_BASE0,
1656                .num_ports        = 4,
1657                .base_baud        = 4000000,
1658                .uart_offset        = 0x200,
1659                .first_offset        = 0x1000,
1660        },
1661        [pbn_oxsemi_8_4000000] = {
1662                .flags                = FL_BASE0,
1663                .num_ports        = 8,
1664                .base_baud        = 4000000,
1665                .uart_offset        = 0x200,
1666                .first_offset        = 0x1000,
1667        },
1668
1669
1670        /*
1671         * EKF addition for i960 Boards form EKF with serial port.
1672         * Max 256 ports.
1673         */
1674        [pbn_intel_i960] = {
1675                .flags                = FL_BASE0,
1676                .num_ports        = 32,
1677                .base_baud        = 921600,
1678                .uart_offset        = 8 << 2,
1679                .reg_shift        = 2,
1680                .first_offset        = 0x10000,
1681        },
1682        [pbn_sgi_ioc3] = {
1683                .flags                = FL_BASE0|FL_NOIRQ,
1684                .num_ports        = 1,
1685                .base_baud        = 458333,
1686                .uart_offset        = 8,
1687                .reg_shift        = 0,
1688                .first_offset        = 0x20178,
1689        },
1690
1691        /*
1692         * Computone - uses IOMEM.
1693         */
1694        [pbn_computone_4] = {
1695                .flags                = FL_BASE0,
1696                .num_ports        = 4,
1697                .base_baud        = 921600,
1698                .uart_offset        = 0x40,
1699                .reg_shift        = 2,
1700                .first_offset        = 0x200,
1701        },
1702        [pbn_computone_6] = {
1703                .flags                = FL_BASE0,
1704                .num_ports        = 6,
1705                .base_baud        = 921600,
1706                .uart_offset        = 0x40,
1707                .reg_shift        = 2,
1708                .first_offset        = 0x200,
1709        },
1710        [pbn_computone_8] = {
1711                .flags                = FL_BASE0,
1712                .num_ports        = 8,
1713                .base_baud        = 921600,
1714                .uart_offset        = 0x40,
1715                .reg_shift        = 2,
1716                .first_offset        = 0x200,
1717        },
1718        [pbn_sbsxrsio] = {
1719                .flags                = FL_BASE0,
1720                .num_ports        = 8,
1721                .base_baud        = 460800,
1722                .uart_offset        = 256,
1723                .reg_shift        = 4,
1724        },
1725        /*
1726         * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1727         *  Only basic 16550A support.
1728         *  XR17C15[24] are not tested, but they should work.
1729         */
1730        [pbn_exar_XR17C152] = {
1731                .flags                = FL_BASE0,
1732                .num_ports        = 2,
1733                .base_baud        = 921600,
1734                .uart_offset        = 0x200,
1735        },
1736        [pbn_exar_XR17C154] = {
1737                .flags                = FL_BASE0,
1738                .num_ports        = 4,
1739                .base_baud        = 921600,
1740                .uart_offset        = 0x200,
1741        },
1742        [pbn_exar_XR17C158] = {
1743                .flags                = FL_BASE0,
1744                .num_ports        = 8,
1745                .base_baud        = 921600,
1746                .uart_offset        = 0x200,
1747        },
1748        /*
1749         * PA Semi PWRficient PA6T-1682M on-chip UART
1750         */
1751        [pbn_pasemi_1682M] = {
1752                .flags                = FL_BASE0,
1753                .num_ports        = 1,
1754                .base_baud        = 8333333,
1755        },
1756};
1757
1758static const struct pci_device_id softmodem_blacklist[] = {
1759        { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1760};
1761
1762/*
1763 * Given a complete unknown PCI device, try to use some heuristics to
1764 * guess what the configuration might be, based on the pitiful PCI
1765 * serial specs.  Returns 0 on success, 1 on failure.
1766 */
1767static int __devinit
1768serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1769{
1770        const struct pci_device_id *blacklist;
1771        int num_iomem, num_port, first_port = -1, i;
1772
1773        /*
1774         * If it is not a communications device or the programming
1775         * interface is greater than 6, give up.
1776         *
1777         * (Should we try to make guesses for multiport serial devices
1778         * later?)
1779         */
1780        if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1781             ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1782            (dev->class & 0xff) > 6)
1783                return -ENODEV;
1784
1785        /*
1786         * Do not access blacklisted devices that are known not to
1787         * feature serial ports.
1788         */
1789        for (blacklist = softmodem_blacklist;
1790             blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1791             blacklist++) {
1792                if (dev->vendor == blacklist->vendor &&
1793                    dev->device == blacklist->device)
1794                        return -ENODEV;
1795        }
1796
1797        num_iomem = num_port = 0;
1798        for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1799                if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1800                        num_port++;
1801                        if (first_port == -1)
1802                                first_port = i;
1803                }
1804                if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1805                        num_iomem++;
1806        }
1807
1808        /*
1809         * If there is 1 or 0 iomem regions, and exactly one port,
1810         * use it.  We guess the number of ports based on the IO
1811         * region size.
1812         */
1813        if (num_iomem <= 1 && num_port == 1) {
1814                board->flags = first_port;
1815                board->num_ports = pci_resource_len(dev, first_port) / 8;
1816                return 0;
1817        }
1818
1819        /*
1820         * Now guess if we've got a board which indexes by BARs.
1821         * Each IO BAR should be 8 bytes, and they should follow
1822         * consecutively.
1823         */
1824        first_port = -1;
1825        num_port = 0;
1826        for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1827                if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1828                    pci_resource_len(dev, i) == 8 &&
1829                    (first_port == -1 || (first_port + num_port) == i)) {
1830                        num_port++;
1831                        if (first_port == -1)
1832                                first_port = i;
1833                }
1834        }
1835
1836        if (num_port > 1) {
1837                board->flags = first_port | FL_BASE_BARS;
1838                board->num_ports = num_port;
1839                return 0;
1840        }
1841
1842        return -ENODEV;
1843}
1844
1845static inline int
1846serial_pci_matches(struct pciserial_board *board,
1847                   struct pciserial_board *guessed)
1848{
1849        return
1850            board->num_ports == guessed->num_ports &&
1851            board->base_baud == guessed->base_baud &&
1852            board->uart_offset == guessed->uart_offset &&
1853            board->reg_shift == guessed->reg_shift &&
1854            board->first_offset == guessed->first_offset;
1855}
1856
1857/*
1858 * Oxford Semiconductor Inc.
1859 * Check that device is part of the Tornado range of devices, then determine
1860 * the number of ports available on the device.
1861 */
1862static int pci_oxsemi_tornado_init(struct pci_dev *dev, struct pciserial_board *board)
1863{
1864        u8 __iomem *p;
1865        unsigned long deviceID;
1866        unsigned int  number_uarts;
1867
1868        /* OxSemi Tornado devices are all 0xCxxx */
1869        if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1870            (dev->device & 0xF000) != 0xC000)
1871                return 0;
1872
1873        p = pci_iomap(dev, 0, 5);
1874        if (p == NULL)
1875                return -ENOMEM;
1876
1877        deviceID = ioread32(p);
1878        /* Tornado device */
1879        if (deviceID == 0x07000200) {
1880                number_uarts = ioread8(p + 4);
1881                board->num_ports = number_uarts;
1882                printk(KERN_DEBUG
1883                        "%d ports detected on Oxford PCI Express device\n",
1884                                                                number_uarts);
1885        }
1886        pci_iounmap(dev, p);
1887        return 0;
1888}
1889
1890struct serial_private *
1891pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1892{
1893        struct uart_port serial_port;
1894        struct serial_private *priv;
1895        struct pci_serial_quirk *quirk;
1896        int rc, nr_ports, i;
1897
1898        /*
1899         * Find number of ports on board
1900         */
1901        if (dev->vendor == PCI_VENDOR_ID_OXSEMI ||
1902            dev->vendor == PCI_VENDOR_ID_MAINPINE)
1903                pci_oxsemi_tornado_init(dev, board);
1904
1905        nr_ports = board->num_ports;
1906
1907        /*
1908         * Find an init and setup quirks.
1909         */
1910        quirk = find_quirk(dev);
1911
1912        /*
1913         * Run the new-style initialization function.
1914         * The initialization function returns:
1915         *  <0  - error
1916         *   0  - use board->num_ports
1917         *  >0  - number of ports
1918         */
1919        if (quirk->init) {
1920                rc = quirk->init(dev);
1921                if (rc < 0) {
1922                        priv = ERR_PTR(rc);
1923                        goto err_out;
1924                }
1925                if (rc)
1926                        nr_ports = rc;
1927        }
1928
1929        priv = kzalloc(sizeof(struct serial_private) +
1930                       sizeof(unsigned int) * nr_ports,
1931                       GFP_KERNEL);
1932        if (!priv) {
1933                priv = ERR_PTR(-ENOMEM);
1934                goto err_deinit;
1935        }
1936
1937        priv->dev = dev;
1938        priv->quirk = quirk;
1939
1940        memset(&serial_port, 0, sizeof(struct uart_port));
1941        serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1942        serial_port.uartclk = board->base_baud * 16;
1943        serial_port.irq = get_pci_irq(dev, board);
1944        serial_port.dev = &dev->dev;
1945
1946        for (i = 0; i < nr_ports; i++) {
1947                if (quirk->setup(priv, board, &serial_port, i))
1948                        break;
1949
1950#ifdef SERIAL_DEBUG_PCI
1951                printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1952                       serial_port.iobase, serial_port.irq, serial_port.iotype);
1953#endif
1954
1955                priv->line[i] = serial8250_register_port(&serial_port);
1956                if (priv->line[i] < 0) {
1957                        printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1958                        break;
1959                }
1960        }
1961        priv->nr = i;
1962        return priv;
1963
1964err_deinit:
1965        if (quirk->exit)
1966                quirk->exit(dev);
1967err_out:
1968        return priv;
1969}
1970EXPORT_SYMBOL_GPL(pciserial_init_ports);
1971
1972void pciserial_remove_ports(struct serial_private *priv)
1973{
1974        struct pci_serial_quirk *quirk;
1975        int i;
1976
1977        for (i = 0; i < priv->nr; i++)
1978                serial8250_unregister_port(priv->line[i]);
1979
1980        for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1981                if (priv->remapped_bar[i])
1982                        iounmap(priv->remapped_bar[i]);
1983                priv->remapped_bar[i] = NULL;
1984        }
1985
1986        /*
1987         * Find the exit quirks.
1988         */
1989        quirk = find_quirk(priv->dev);
1990        if (quirk->exit)
1991                quirk->exit(priv->dev);
1992
1993        kfree(priv);
1994}
1995EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1996
1997void pciserial_suspend_ports(struct serial_private *priv)
1998{
1999        int i;
2000
2001        for (i = 0; i < priv->nr; i++)
2002                if (priv->line[i] >= 0)
2003                        serial8250_suspend_port(priv->line[i]);
2004}
2005EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2006
2007void pciserial_resume_ports(struct serial_private *priv)
2008{
2009        int i;
2010
2011        /*
2012         * Ensure that the board is correctly configured.
2013         */
2014        if (priv->quirk->init)
2015                priv->quirk->init(priv->dev);
2016
2017        for (i = 0; i < priv->nr; i++)
2018                if (priv->line[i] >= 0)
2019                        serial8250_resume_port(priv->line[i]);
2020}
2021EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2022
2023/*
2024 * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2025 * to the arrangement of serial ports on a PCI card.
2026 */
2027static int __devinit
2028pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2029{
2030        struct serial_private *priv;
2031        struct pciserial_board *board, tmp;
2032        int rc;
2033
2034        if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2035                printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2036                        ent->driver_data);
2037                return -EINVAL;
2038        }
2039
2040        board = &pci_boards[ent->driver_data];
2041
2042        rc = pci_enable_device(dev);
2043        if (rc)
2044                return rc;
2045
2046        if (ent->driver_data == pbn_default) {
2047                /*
2048                 * Use a copy of the pci_board entry for this;
2049                 * avoid changing entries in the table.
2050                 */
2051                memcpy(&tmp, board, sizeof(struct pciserial_board));
2052                board = &tmp;
2053
2054                /*
2055                 * We matched one of our class entries.  Try to
2056                 * determine the parameters of this board.
2057                 */
2058                rc = serial_pci_guess_board(dev, board);
2059                if (rc)
2060                        goto disable;
2061        } else {
2062                /*
2063                 * We matched an explicit entry.  If we are able to
2064                 * detect this boards settings with our heuristic,
2065                 * then we no longer need this entry.
2066                 */
2067                memcpy(&tmp, &pci_boards[pbn_default],
2068                       sizeof(struct pciserial_board));
2069                rc = serial_pci_guess_board(dev, &tmp);
2070                if (rc == 0 && serial_pci_matches(board, &tmp))
2071                        moan_device("Redundant entry in serial pci_table.",
2072                                    dev);
2073        }
2074
2075        priv = pciserial_init_ports(dev, board);
2076        if (!IS_ERR(priv)) {
2077                pci_set_drvdata(dev, priv);
2078                return 0;
2079        }
2080
2081        rc = PTR_ERR(priv);
2082
2083 disable:
2084        pci_disable_device(dev);
2085        return rc;
2086}
2087
2088static void __devexit pciserial_remove_one(struct pci_dev *dev)
2089{
2090        struct serial_private *priv = pci_get_drvdata(dev);
2091
2092        pci_set_drvdata(dev, NULL);
2093
2094        pciserial_remove_ports(priv);
2095
2096        pci_disable_device(dev);
2097}
2098
2099#ifdef CONFIG_PM
2100static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2101{
2102        struct serial_private *priv = pci_get_drvdata(dev);
2103
2104        if (priv)
2105                pciserial_suspend_ports(priv);
2106
2107        pci_save_state(dev);
2108        pci_set_power_state(dev, pci_choose_state(dev, state));
2109        return 0;
2110}
2111
2112static int pciserial_resume_one(struct pci_dev *dev)
2113{
2114        int err;
2115        struct serial_private *priv = pci_get_drvdata(dev);
2116
2117        pci_set_power_state(dev, PCI_D0);
2118        pci_restore_state(dev);
2119
2120        if (priv) {
2121                /*
2122                 * The device may have been disabled.  Re-enable it.
2123                 */
2124                err = pci_enable_device(dev);
2125                /* FIXME: We cannot simply error out here */
2126                if (err)
2127                        printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2128                pciserial_resume_ports(priv);
2129        }
2130        return 0;
2131}
2132#endif
2133
2134static struct pci_device_id serial_pci_tbl[] = {
2135        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2136                PCI_SUBVENDOR_ID_CONNECT_TECH,
2137                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2138                pbn_b1_8_1382400 },
2139        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2140                PCI_SUBVENDOR_ID_CONNECT_TECH,
2141                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2142                pbn_b1_4_1382400 },
2143        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2144                PCI_SUBVENDOR_ID_CONNECT_TECH,
2145                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2146                pbn_b1_2_1382400 },
2147        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2148                PCI_SUBVENDOR_ID_CONNECT_TECH,
2149                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2150                pbn_b1_8_1382400 },
2151        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2152                PCI_SUBVENDOR_ID_CONNECT_TECH,
2153                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2154                pbn_b1_4_1382400 },
2155        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2156                PCI_SUBVENDOR_ID_CONNECT_TECH,
2157                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2158                pbn_b1_2_1382400 },
2159        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2160                PCI_SUBVENDOR_ID_CONNECT_TECH,
2161                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2162                pbn_b1_8_921600 },
2163        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2164                PCI_SUBVENDOR_ID_CONNECT_TECH,
2165                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2166                pbn_b1_8_921600 },
2167        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2168                PCI_SUBVENDOR_ID_CONNECT_TECH,
2169                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2170                pbn_b1_4_921600 },
2171        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2172                PCI_SUBVENDOR_ID_CONNECT_TECH,
2173                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2174                pbn_b1_4_921600 },
2175        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2176                PCI_SUBVENDOR_ID_CONNECT_TECH,
2177                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2178                pbn_b1_2_921600 },
2179        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2180                PCI_SUBVENDOR_ID_CONNECT_TECH,
2181                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2182                pbn_b1_8_921600 },
2183        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2184                PCI_SUBVENDOR_ID_CONNECT_TECH,
2185                PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2186                pbn_b1_8_921600 },
2187        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2188                PCI_SUBVENDOR_ID_CONNECT_TECH,
2189                PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2190                pbn_b1_4_921600 },
2191        {        PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2192                PCI_SUBVENDOR_ID_CONNECT_TECH,
2193                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2194                pbn_b1_2_1250000 },
2195        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2196                PCI_SUBVENDOR_ID_CONNECT_TECH,
2197                PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2198                pbn_b0_2_1843200 },
2199        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2200                PCI_SUBVENDOR_ID_CONNECT_TECH,
2201                PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2202                pbn_b0_4_1843200 },
2203        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2204                PCI_VENDOR_ID_AFAVLAB,
2205                PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2206                pbn_b0_4_1152000 },
2207        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2208                PCI_SUBVENDOR_ID_CONNECT_TECH,
2209                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2210                pbn_b0_2_1843200_200 },
2211        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2212                PCI_SUBVENDOR_ID_CONNECT_TECH,
2213                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2214                pbn_b0_4_1843200_200 },
2215        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2216                PCI_SUBVENDOR_ID_CONNECT_TECH,
2217                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2218                pbn_b0_8_1843200_200 },
2219        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2220                PCI_SUBVENDOR_ID_CONNECT_TECH,
2221                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2222                pbn_b0_2_1843200_200 },
2223        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2224                PCI_SUBVENDOR_ID_CONNECT_TECH,
2225                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2226                pbn_b0_4_1843200_200 },
2227        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2228                PCI_SUBVENDOR_ID_CONNECT_TECH,
2229                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2230                pbn_b0_8_1843200_200 },
2231        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2232                PCI_SUBVENDOR_ID_CONNECT_TECH,
2233                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2234                pbn_b0_2_1843200_200 },
2235        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2236                PCI_SUBVENDOR_ID_CONNECT_TECH,
2237                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2238                pbn_b0_4_1843200_200 },
2239        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2240                PCI_SUBVENDOR_ID_CONNECT_TECH,
2241                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2242                pbn_b0_8_1843200_200 },
2243        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2244                PCI_SUBVENDOR_ID_CONNECT_TECH,
2245                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2246                pbn_b0_2_1843200_200 },
2247        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2248                PCI_SUBVENDOR_ID_CONNECT_TECH,
2249                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2250                pbn_b0_4_1843200_200 },
2251        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2252                PCI_SUBVENDOR_ID_CONNECT_TECH,
2253                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2254                pbn_b0_8_1843200_200 },
2255
2256        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2257                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2258                pbn_b2_bt_1_115200 },
2259        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2260                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2261                pbn_b2_bt_2_115200 },
2262        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2263                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2264                pbn_b2_bt_4_115200 },
2265        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2266                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2267                pbn_b2_bt_2_115200 },
2268        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2269                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2270                pbn_b2_bt_4_115200 },
2271        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2272                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2273                pbn_b2_8_115200 },
2274        {        PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2275                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2276                pbn_b2_8_115200 },
2277
2278        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2279                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2280                pbn_b2_bt_2_115200 },
2281        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2282                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2283                pbn_b2_bt_2_921600 },
2284        /*
2285         * VScom SPCOM800, from sl@s.pl
2286         */
2287        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2288                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2289                pbn_b2_8_921600 },
2290        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2291                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2292                pbn_b2_4_921600 },
2293        /* Unknown card - subdevice 0x1584 */
2294        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2295                PCI_VENDOR_ID_PLX,
2296                PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2297                pbn_b0_4_115200 },
2298        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2299                PCI_SUBVENDOR_ID_KEYSPAN,
2300                PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2301                pbn_panacom },
2302        {        PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2303                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2304                pbn_panacom4 },
2305        {        PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2306                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2307                pbn_panacom2 },
2308        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2309                PCI_VENDOR_ID_ESDGMBH,
2310                PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2311                pbn_b2_4_115200 },
2312        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2313                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2314                PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2315                pbn_b2_4_460800 },
2316        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2317                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2318                PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2319                pbn_b2_8_460800 },
2320        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2321                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2322                PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2323                pbn_b2_16_460800 },
2324        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2325                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2326                PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2327                pbn_b2_16_460800 },
2328        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2329                PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2330                PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2331                pbn_b2_4_460800 },
2332        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2333                PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2334                PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2335                pbn_b2_8_460800 },
2336        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2337                PCI_SUBVENDOR_ID_EXSYS,
2338                PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2339                pbn_exsys_4055 },
2340        /*
2341         * Megawolf Romulus PCI Serial Card, from Mike Hudson
2342         * (Exoray@isys.ca)
2343         */
2344        {        PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2345                0x10b5, 0x106a, 0, 0,
2346                pbn_plx_romulus },
2347        {        PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2348                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2349                pbn_b1_4_115200 },
2350        {        PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2351                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2352                pbn_b1_2_115200 },
2353        {        PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2354                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2355                pbn_b1_8_115200 },
2356        {        PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2357                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2358                pbn_b1_8_115200 },
2359        {        PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2360                PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2361                0, 0,
2362                pbn_b0_4_921600 },
2363        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2364                PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2365                0, 0,
2366                pbn_b0_4_1152000 },
2367
2368                /*
2369                 * The below card is a little controversial since it is the
2370                 * subject of a PCI vendor/device ID clash.  (See
2371                 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2372                 * For now just used the hex ID 0x950a.
2373                 */
2374        {        PCI_VENDOR_ID_OXSEMI, 0x950a,
2375                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2376                pbn_b0_2_1130000 },
2377        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2378                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2379                pbn_b0_4_115200 },
2380        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2381                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2382                pbn_b0_bt_2_921600 },
2383
2384        /*
2385         * Oxford Semiconductor Inc. Tornado PCI express device range.
2386         */
2387        {        PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
2388                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2389                pbn_b0_1_4000000 },
2390        {        PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
2391                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2392                pbn_b0_1_4000000 },
2393        {        PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
2394                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2395                pbn_oxsemi_1_4000000 },
2396        {        PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
2397                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2398                pbn_oxsemi_1_4000000 },
2399        {        PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
2400                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2401                pbn_b0_1_4000000 },
2402        {        PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
2403                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2404                pbn_b0_1_4000000 },
2405        {        PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
2406                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2407                pbn_oxsemi_1_4000000 },
2408        {        PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
2409                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2410                pbn_oxsemi_1_4000000 },
2411        {        PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
2412                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2413                pbn_b0_1_4000000 },
2414        {        PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
2415                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2416                pbn_b0_1_4000000 },
2417        {        PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
2418                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2419                pbn_b0_1_4000000 },
2420        {        PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
2421                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2422                pbn_b0_1_4000000 },
2423        {        PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
2424                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2425                pbn_oxsemi_2_4000000 },
2426        {        PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
2427                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2428                pbn_oxsemi_2_4000000 },
2429        {        PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
2430                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2431                pbn_oxsemi_4_4000000 },
2432        {        PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
2433                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2434                pbn_oxsemi_4_4000000 },
2435        {        PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
2436                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2437                pbn_oxsemi_8_4000000 },
2438        {        PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
2439                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2440                pbn_oxsemi_8_4000000 },
2441        {        PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
2442                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2443                pbn_oxsemi_1_4000000 },
2444        {        PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
2445                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2446                pbn_oxsemi_1_4000000 },
2447        {        PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
2448                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2449                pbn_oxsemi_1_4000000 },
2450        {        PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
2451                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2452                pbn_oxsemi_1_4000000 },
2453        {        PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
2454                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2455                pbn_oxsemi_1_4000000 },
2456        {        PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
2457                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2458                pbn_oxsemi_1_4000000 },
2459        {        PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
2460                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2461                pbn_oxsemi_1_4000000 },
2462        {        PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
2463                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2464                pbn_oxsemi_1_4000000 },
2465        {        PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
2466                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2467                pbn_oxsemi_1_4000000 },
2468        {        PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
2469                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2470                pbn_oxsemi_1_4000000 },
2471        {        PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
2472                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2473                pbn_oxsemi_1_4000000 },
2474        {        PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
2475                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2476                pbn_oxsemi_1_4000000 },
2477        {        PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
2478                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2479                pbn_oxsemi_1_4000000 },
2480        {        PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
2481                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2482                pbn_oxsemi_1_4000000 },
2483        {        PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
2484                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2485                pbn_oxsemi_1_4000000 },
2486        {        PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
2487                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2488                pbn_oxsemi_1_4000000 },
2489        {        PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
2490                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2491                pbn_oxsemi_1_4000000 },
2492        {        PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
2493                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2494                pbn_oxsemi_1_4000000 },
2495        {        PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
2496                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2497                pbn_oxsemi_1_4000000 },
2498        {        PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
2499                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2500                pbn_oxsemi_1_4000000 },
2501        {        PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
2502                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2503                pbn_oxsemi_1_4000000 },
2504        {        PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
2505                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2506                pbn_oxsemi_1_4000000 },
2507        {        PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
2508                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2509                pbn_oxsemi_1_4000000 },
2510        {        PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
2511                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2512                pbn_oxsemi_1_4000000 },
2513        {        PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
2514                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2515                pbn_oxsemi_1_4000000 },
2516        {        PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
2517                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2518                pbn_oxsemi_1_4000000 },
2519        /*
2520         * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2521         */
2522        {        PCI_VENDOR_ID_MAINPINE, 0x4000,        /* IQ Express 1 Port V.34 Super-G3 Fax */
2523                PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2524                pbn_oxsemi_1_4000000 },
2525        {        PCI_VENDOR_ID_MAINPINE, 0x4000,        /* IQ Express 2 Port V.34 Super-G3 Fax */
2526                PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2527                pbn_oxsemi_2_4000000 },
2528        {        PCI_VENDOR_ID_MAINPINE, 0x4000,        /* IQ Express 4 Port V.34 Super-G3 Fax */
2529                PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2530                pbn_oxsemi_4_4000000 },
2531        {        PCI_VENDOR_ID_MAINPINE, 0x4000,        /* IQ Express 8 Port V.34 Super-G3 Fax */
2532                PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2533                pbn_oxsemi_8_4000000 },
2534        /*
2535         * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2536         * from skokodyn@yahoo.com
2537         */
2538        {        PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2539                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2540                pbn_sbsxrsio },
2541        {        PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2542                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2543                pbn_sbsxrsio },
2544        {        PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2545                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2546                pbn_sbsxrsio },
2547        {        PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2548                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2549                pbn_sbsxrsio },
2550
2551        /*
2552         * Digitan DS560-558, from jimd@esoft.com
2553         */
2554        {        PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2555                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2556                pbn_b1_1_115200 },
2557
2558        /*
2559         * Titan Electronic cards
2560         *  The 400L and 800L have a custom setup quirk.
2561         */
2562        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2563                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2564                pbn_b0_1_921600 },
2565        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2566                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2567                pbn_b0_2_921600 },
2568        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2569                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2570                pbn_b0_4_921600 },
2571        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2572                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2573                pbn_b0_4_921600 },
2574        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2575                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2576                pbn_b1_1_921600 },
2577        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2578                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2579                pbn_b1_bt_2_921600 },
2580        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2581                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2582                pbn_b0_bt_4_921600 },
2583        {        PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2584                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2585                pbn_b0_bt_8_921600 },
2586
2587        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2588                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2589                pbn_b2_1_460800 },
2590        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2591                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2592                pbn_b2_1_460800 },
2593        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2594                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2595                pbn_b2_1_460800 },
2596        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2597                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2598                pbn_b2_bt_2_921600 },
2599        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2600                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2601                pbn_b2_bt_2_921600 },
2602        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2603                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2604                pbn_b2_bt_2_921600 },
2605        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2606                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2607                pbn_b2_bt_4_921600 },
2608        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2609                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2610                pbn_b2_bt_4_921600 },
2611        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2612                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2613                pbn_b2_bt_4_921600 },
2614        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2615                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2616                pbn_b0_1_921600 },
2617        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2618                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2619                pbn_b0_1_921600 },
2620        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2621                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2622                pbn_b0_1_921600 },
2623        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2624                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2625                pbn_b0_bt_2_921600 },
2626        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2627                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2628                pbn_b0_bt_2_921600 },
2629        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2630                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2631                pbn_b0_bt_2_921600 },
2632        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2633                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2634                pbn_b0_bt_4_921600 },
2635        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2636                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2637                pbn_b0_bt_4_921600 },
2638        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2639                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2640                pbn_b0_bt_4_921600 },
2641        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2642                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2643                pbn_b0_bt_8_921600 },
2644        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2645                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2646                pbn_b0_bt_8_921600 },
2647        {        PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2648                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2649                pbn_b0_bt_8_921600 },
2650
2651        /*
2652         * Computone devices submitted by Doug McNash dmcnash@computone.com
2653         */
2654        {        PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2655                PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2656                0, 0, pbn_computone_4 },
2657        {        PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2658                PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2659                0, 0, pbn_computone_8 },
2660        {        PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2661                PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2662                0, 0, pbn_computone_6 },
2663
2664        {        PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2665                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2666                pbn_oxsemi },
2667        {        PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2668                PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2669                pbn_b0_bt_1_921600 },
2670
2671        /*
2672         * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2673         */
2674        {        PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2675                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2676                pbn_b0_bt_8_115200 },
2677        {        PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2678                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2679                pbn_b0_bt_8_115200 },
2680
2681        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2682                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2683                pbn_b0_bt_2_115200 },
2684        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2685                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2686                pbn_b0_bt_2_115200 },
2687        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2688                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2689                pbn_b0_bt_2_115200 },
2690        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2691                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2692                pbn_b0_bt_4_460800 },
2693        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2694                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2695                pbn_b0_bt_4_460800 },
2696        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2697                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2698                pbn_b0_bt_2_460800 },
2699        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2700                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2701                pbn_b0_bt_2_460800 },
2702        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2703                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2704                pbn_b0_bt_2_460800 },
2705        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2706                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2707                pbn_b0_bt_1_115200 },
2708        {        PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2709                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2710                pbn_b0_bt_1_460800 },
2711
2712        /*
2713         * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2714         * Cards are identified by their subsystem vendor IDs, which
2715         * (in hex) match the model number.
2716         *
2717         * Note that JC140x are RS422/485 cards which require ox950
2718         * ACR = 0x10, and as such are not currently fully supported.
2719         */
2720        {        PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2721                0x1204, 0x0004, 0, 0,
2722                pbn_b0_4_921600 },
2723        {        PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2724                0x1208, 0x0004, 0, 0,
2725                pbn_b0_4_921600 },
2726/*        {        PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2727                0x1402, 0x0002, 0, 0,
2728                pbn_b0_2_921600 }, */
2729/*        {        PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2730                0x1404, 0x0004, 0, 0,
2731                pbn_b0_4_921600 }, */
2732        {        PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2733                0x1208, 0x0004, 0, 0,
2734                pbn_b0_4_921600 },
2735
2736        /*
2737         * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2738         */
2739        {        PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2740                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2741                pbn_b1_1_1382400 },
2742
2743        /*
2744         * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2745         */
2746        {        PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2747                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2748                pbn_b1_1_1382400 },
2749
2750        /*
2751         * RAStel 2 port modem, gerg@moreton.com.au
2752         */
2753        {        PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2754                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2755                pbn_b2_bt_2_115200 },
2756
2757        /*
2758         * EKF addition for i960 Boards form EKF with serial port
2759         */
2760        {        PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2761                0xE4BF, PCI_ANY_ID, 0, 0,
2762                pbn_intel_i960 },
2763
2764        /*
2765         * Xircom Cardbus/Ethernet combos
2766         */
2767        {        PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2768                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2769                pbn_b0_1_115200 },
2770        /*
2771         * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2772         */
2773        {        PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2774                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2775                pbn_b0_1_115200 },
2776
2777        /*
2778         * Untested PCI modems, sent in from various folks...
2779         */
2780
2781        /*
2782         * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2783         */
2784        {        PCI_VENDOR_ID_ROCKWELL, 0x1004,
2785                0x1048, 0x1500, 0, 0,
2786                pbn_b1_1_115200 },
2787
2788        {        PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2789                0xFF00, 0, 0, 0,
2790                pbn_sgi_ioc3 },
2791
2792        /*
2793         * HP Diva card
2794         */
2795        {        PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2796                PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2797                pbn_b1_1_115200 },
2798        {        PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2799                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2800                pbn_b0_5_115200 },
2801        {        PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2802                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803                pbn_b2_1_115200 },
2804
2805        {        PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2806                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2807                pbn_b3_2_115200 },
2808        {        PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2809                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2810                pbn_b3_4_115200 },
2811        {        PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2812                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2813                pbn_b3_8_115200 },
2814
2815        /*
2816         * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2817         */
2818        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2819                PCI_ANY_ID, PCI_ANY_ID,
2820                0,
2821                0, pbn_exar_XR17C152 },
2822        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2823                PCI_ANY_ID, PCI_ANY_ID,
2824                0,
2825                0, pbn_exar_XR17C154 },
2826        {        PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2827                PCI_ANY_ID, PCI_ANY_ID,
2828                0,
2829                0, pbn_exar_XR17C158 },
2830
2831        /*
2832         * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2833         */
2834        {        PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2835                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2836                pbn_b0_1_115200 },
2837        /*
2838         * ITE
2839         */
2840        {        PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2841                PCI_ANY_ID, PCI_ANY_ID,
2842                0, 0,
2843                pbn_b1_bt_1_115200 },
2844
2845        /*
2846         * IntaShield IS-200
2847         */
2848        {        PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2849                PCI_ANY_ID, PCI_ANY_ID, 0, 0,        /* 135a.0811 */
2850                pbn_b2_2_115200 },
2851        /*
2852         * IntaShield IS-400
2853         */
2854        {        PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2855                PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
2856                pbn_b2_4_115200 },
2857        /*
2858         * Perle PCI-RAS cards
2859         */
2860        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2861                PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2862                0, 0, pbn_b2_4_921600 },
2863        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2864                PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2865                0, 0, pbn_b2_8_921600 },
2866
2867        /*
2868         * Mainpine series cards: Fairly standard layout but fools
2869         * parts of the autodetect in some cases and uses otherwise
2870         * unmatched communications subclasses in the PCI Express case
2871         */
2872
2873        {        /* RockForceDUO */
2874                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2875                PCI_VENDOR_ID_MAINPINE, 0x0200,
2876                0, 0, pbn_b0_2_115200 },
2877        {        /* RockForceQUATRO */
2878                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2879                PCI_VENDOR_ID_MAINPINE, 0x0300,
2880                0, 0, pbn_b0_4_115200 },
2881        {        /* RockForceDUO+ */
2882                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2883                PCI_VENDOR_ID_MAINPINE, 0x0400,
2884                0, 0, pbn_b0_2_115200 },
2885        {        /* RockForceQUATRO+ */
2886                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2887                PCI_VENDOR_ID_MAINPINE, 0x0500,
2888                0, 0, pbn_b0_4_115200 },
2889        {        /* RockForce+ */
2890                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2891                PCI_VENDOR_ID_MAINPINE, 0x0600,
2892                0, 0, pbn_b0_2_115200 },
2893        {        /* RockForce+ */
2894                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2895                PCI_VENDOR_ID_MAINPINE, 0x0700,
2896                0, 0, pbn_b0_4_115200 },
2897        {        /* RockForceOCTO+ */
2898                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2899                PCI_VENDOR_ID_MAINPINE, 0x0800,
2900                0, 0, pbn_b0_8_115200 },
2901        {        /* RockForceDUO+ */
2902                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2903                PCI_VENDOR_ID_MAINPINE, 0x0C00,
2904                0, 0, pbn_b0_2_115200 },
2905        {        /* RockForceQUARTRO+ */
2906                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2907                PCI_VENDOR_ID_MAINPINE, 0x0D00,
2908                0, 0, pbn_b0_4_115200 },
2909        {        /* RockForceOCTO+ */
2910                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2911                PCI_VENDOR_ID_MAINPINE, 0x1D00,
2912                0, 0, pbn_b0_8_115200 },
2913        {        /* RockForceD1 */
2914                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2915                PCI_VENDOR_ID_MAINPINE, 0x2000,
2916                0, 0, pbn_b0_1_115200 },
2917        {        /* RockForceF1 */
2918                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2919                PCI_VENDOR_ID_MAINPINE, 0x2100,
2920                0, 0, pbn_b0_1_115200 },
2921        {        /* RockForceD2 */
2922                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2923                PCI_VENDOR_ID_MAINPINE, 0x2200,
2924                0, 0, pbn_b0_2_115200 },
2925        {        /* RockForceF2 */
2926                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2927                PCI_VENDOR_ID_MAINPINE, 0x2300,
2928                0, 0, pbn_b0_2_115200 },
2929        {        /* RockForceD4 */
2930                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2931                PCI_VENDOR_ID_MAINPINE, 0x2400,
2932                0, 0, pbn_b0_4_115200 },
2933        {        /* RockForceF4 */
2934                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2935                PCI_VENDOR_ID_MAINPINE, 0x2500,
2936                0, 0, pbn_b0_4_115200 },
2937        {        /* RockForceD8 */
2938                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2939                PCI_VENDOR_ID_MAINPINE, 0x2600,
2940                0, 0, pbn_b0_8_115200 },
2941        {        /* RockForceF8 */
2942                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2943                PCI_VENDOR_ID_MAINPINE, 0x2700,
2944                0, 0, pbn_b0_8_115200 },
2945        {        /* IQ Express D1 */
2946                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2947                PCI_VENDOR_ID_MAINPINE, 0x3000,
2948                0, 0, pbn_b0_1_115200 },
2949        {        /* IQ Express F1 */
2950                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2951                PCI_VENDOR_ID_MAINPINE, 0x3100,
2952                0, 0, pbn_b0_1_115200 },
2953        {        /* IQ Express D2 */
2954                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2955                PCI_VENDOR_ID_MAINPINE, 0x3200,
2956                0, 0, pbn_b0_2_115200 },
2957        {        /* IQ Express F2 */
2958                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2959                PCI_VENDOR_ID_MAINPINE, 0x3300,
2960                0, 0, pbn_b0_2_115200 },
2961        {        /* IQ Express D4 */
2962                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2963                PCI_VENDOR_ID_MAINPINE, 0x3400,
2964                0, 0, pbn_b0_4_115200 },
2965        {        /* IQ Express F4 */
2966                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2967                PCI_VENDOR_ID_MAINPINE, 0x3500,
2968                0, 0, pbn_b0_4_115200 },
2969        {        /* IQ Express D8 */
2970                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2971                PCI_VENDOR_ID_MAINPINE, 0x3C00,
2972                0, 0, pbn_b0_8_115200 },
2973        {        /* IQ Express F8 */
2974                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2975                PCI_VENDOR_ID_MAINPINE, 0x3D00,
2976                0, 0, pbn_b0_8_115200 },
2977
2978
2979        /*
2980         * PA Semi PA6T-1682M on-chip UART
2981         */
2982        {        PCI_VENDOR_ID_PASEMI, 0xa004,
2983                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2984                pbn_pasemi_1682M },
2985
2986        /*
2987        * ADDI-DATA GmbH communication cards <info@addi-data.com>
2988        */
2989        {        PCI_VENDOR_ID_ADDIDATA,
2990                PCI_DEVICE_ID_ADDIDATA_APCI7500,
2991                PCI_ANY_ID,
2992                PCI_ANY_ID,
2993                0,
2994                0,
2995                pbn_b0_4_115200 },
2996
2997        {        PCI_VENDOR_ID_ADDIDATA,
2998                PCI_DEVICE_ID_ADDIDATA_APCI7420,
2999                PCI_ANY_ID,
3000                PCI_ANY_ID,
3001                0,
3002                0,
3003                pbn_b0_2_115200 },
3004
3005        {        PCI_VENDOR_ID_ADDIDATA,
3006                PCI_DEVICE_ID_ADDIDATA_APCI7300,
3007                PCI_ANY_ID,
3008                PCI_ANY_ID,
3009                0,
3010                0,
3011                pbn_b0_1_115200 },
3012
3013        {        PCI_VENDOR_ID_ADDIDATA_OLD,
3014                PCI_DEVICE_ID_ADDIDATA_APCI7800,
3015                PCI_ANY_ID,
3016                PCI_ANY_ID,
3017                0,
3018                0,
3019                pbn_b1_8_115200 },
3020
3021        {        PCI_VENDOR_ID_ADDIDATA,
3022                PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3023                PCI_ANY_ID,
3024                PCI_ANY_ID,
3025                0,
3026                0,
3027                pbn_b0_4_115200 },
3028
3029        {        PCI_VENDOR_ID_ADDIDATA,
3030                PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3031                PCI_ANY_ID,
3032                PCI_ANY_ID,
3033                0,
3034                0,
3035                pbn_b0_2_115200 },
3036
3037        {        PCI_VENDOR_ID_ADDIDATA,
3038                PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3039                PCI_ANY_ID,
3040                PCI_ANY_ID,
3041                0,
3042                0,
3043                pbn_b0_1_115200 },
3044
3045        {        PCI_VENDOR_ID_ADDIDATA,
3046                PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3047                PCI_ANY_ID,
3048                PCI_ANY_ID,
3049                0,
3050                0,
3051                pbn_b0_4_115200 },
3052
3053        {        PCI_VENDOR_ID_ADDIDATA,
3054                PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3055                PCI_ANY_ID,
3056                PCI_ANY_ID,
3057                0,
3058                0,
3059                pbn_b0_2_115200 },
3060
3061        {        PCI_VENDOR_ID_ADDIDATA,
3062                PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3063                PCI_ANY_ID,
3064                PCI_ANY_ID,
3065                0,
3066                0,
3067                pbn_b0_1_115200 },
3068
3069        {        PCI_VENDOR_ID_ADDIDATA,
3070                PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3071                PCI_ANY_ID,
3072                PCI_ANY_ID,
3073                0,
3074                0,
3075                pbn_b0_8_115200 },
3076
3077        /*
3078         * These entries match devices with class COMMUNICATION_SERIAL,
3079         * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3080         */
3081        {        PCI_ANY_ID, PCI_ANY_ID,
3082                PCI_ANY_ID, PCI_ANY_ID,
3083                PCI_CLASS_COMMUNICATION_SERIAL << 8,
3084                0xffff00, pbn_default },
3085        {        PCI_ANY_ID, PCI_ANY_ID,
3086                PCI_ANY_ID, PCI_ANY_ID,
3087                PCI_CLASS_COMMUNICATION_MODEM << 8,
3088                0xffff00, pbn_default },
3089        {        PCI_ANY_ID, PCI_ANY_ID,
3090                PCI_ANY_ID, PCI_ANY_ID,
3091                PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3092                0xffff00, pbn_default },
3093        { 0, }
3094};
3095
3096static struct pci_driver serial_pci_driver = {
3097        .name                = "serial",
3098        .probe                = pciserial_init_one,
3099        .remove                = __devexit_p(pciserial_remove_one),
3100#ifdef CONFIG_PM
3101        .suspend        = pciserial_suspend_one,
3102        .resume                = pciserial_resume_one,
3103#endif
3104        .id_table        = serial_pci_tbl,
3105};
3106
3107static int __init serial8250_pci_init(void)
3108{
3109        return pci_register_driver(&serial_pci_driver);
3110}
3111
3112static void __exit serial8250_pci_exit(void)
3113{
3114        pci_unregister_driver(&serial_pci_driver);
3115}
3116
3117module_init(serial8250_pci_init);
3118module_exit(serial8250_pci_exit);
3119
3120MODULE_LICENSE("GPL");
3121MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3122MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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