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51#include <linux/netdevice.h>
52#include <linux/ethtool.h>
53#include <linux/delay.h>
54#include <linux/pci.h>
55
56#include "e1000.h"
57
58#define ICH_FLASH_GFPREG 0x0000
59#define ICH_FLASH_HSFSTS 0x0004
60#define ICH_FLASH_HSFCTL 0x0006
61#define ICH_FLASH_FADDR 0x0008
62#define ICH_FLASH_FDATA0 0x0010
63#define ICH_FLASH_PR0 0x0074
64
65#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
66#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
67#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
68#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
69#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
70
71#define ICH_CYCLE_READ 0
72#define ICH_CYCLE_WRITE 2
73#define ICH_CYCLE_ERASE 3
74
75#define FLASH_GFPREG_BASE_MASK 0x1FFF
76#define FLASH_SECTOR_ADDR_SHIFT 12
77
78#define ICH_FLASH_SEG_SIZE_256 256
79#define ICH_FLASH_SEG_SIZE_4K 4096
80#define ICH_FLASH_SEG_SIZE_8K 8192
81#define ICH_FLASH_SEG_SIZE_64K 65536
82
83
84#define E1000_ICH_FWSM_RSPCIPHY 0x00000040
85
86#define E1000_ICH_MNG_IAMT_MODE 0x2
87
88#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
89 (ID_LED_DEF1_OFF2 << 8) | \
90 (ID_LED_DEF1_ON2 << 4) | \
91 (ID_LED_DEF1_DEF2))
92
93#define E1000_ICH_NVM_SIG_WORD 0x13
94#define E1000_ICH_NVM_SIG_MASK 0xC000
95
96#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
97
98#define E1000_FEXTNVM_SW_CONFIG 1
99#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27)
100
101#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
102
103#define E1000_ICH_RAR_ENTRIES 7
104
105#define PHY_PAGE_SHIFT 5
106#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
107 ((reg) & MAX_PHY_REG_ADDRESS))
108#define IGP3_KMRN_DIAG PHY_REG(770, 19)
109#define IGP3_VR_CTRL PHY_REG(776, 18)
110
111#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
112#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
113#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
114
115
116
117union ich8_hws_flash_status {
118 struct ich8_hsfsts {
119 u16 flcdone :1;
120 u16 flcerr :1;
121 u16 dael :1;
122 u16 berasesz :2;
123 u16 flcinprog :1;
124 u16 reserved1 :2;
125 u16 reserved2 :6;
126 u16 fldesvalid :1;
127 u16 flockdn :1;
128 } hsf_status;
129 u16 regval;
130};
131
132
133
134union ich8_hws_flash_ctrl {
135 struct ich8_hsflctl {
136 u16 flcgo :1;
137 u16 flcycle :2;
138 u16 reserved :5;
139 u16 fldbcount :2;
140 u16 flockdn :6;
141 } hsf_ctrl;
142 u16 regval;
143};
144
145
146union ich8_hws_flash_regacc {
147 struct ich8_flracc {
148 u32 grra :8;
149 u32 grwa :8;
150 u32 gmrag :8;
151 u32 gmwag :8;
152 } hsf_flregacc;
153 u16 regval;
154};
155
156
157union ich8_flash_protected_range {
158 struct ich8_pr {
159 u32 base:13;
160 u32 reserved1:2;
161 u32 rpe:1;
162 u32 limit:13;
163 u32 reserved2:2;
164 u32 wpe:1;
165 } range;
166 u32 regval;
167};
168
169static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
170static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
171static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
172static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
173static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
174static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
175 u32 offset, u8 byte);
176static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
177 u8 *data);
178static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
179 u16 *data);
180static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
181 u8 size, u16 *data);
182static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
183static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
184static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
185
186static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
187{
188 return readw(hw->flash_address + reg);
189}
190
191static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
192{
193 return readl(hw->flash_address + reg);
194}
195
196static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
197{
198 writew(val, hw->flash_address + reg);
199}
200
201static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
202{
203 writel(val, hw->flash_address + reg);
204}
205
206#define er16flash(reg) __er16flash(hw, (reg))
207#define er32flash(reg) __er32flash(hw, (reg))
208#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
209#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
210
211
212
213
214
215
216
217static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
218{
219 struct e1000_phy_info *phy = &hw->phy;
220 s32 ret_val;
221 u16 i = 0;
222
223 phy->addr = 1;
224 phy->reset_delay_us = 100;
225
226
227
228
229
230 ret_val = e1000e_determine_phy_address(hw);
231 if (ret_val) {
232 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
233 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
234 ret_val = e1000e_determine_phy_address(hw);
235 if (ret_val)
236 return ret_val;
237 }
238
239 phy->id = 0;
240 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
241 (i++ < 100)) {
242 msleep(1);
243 ret_val = e1000e_get_phy_id(hw);
244 if (ret_val)
245 return ret_val;
246 }
247
248
249 switch (phy->id) {
250 case IGP03E1000_E_PHY_ID:
251 phy->type = e1000_phy_igp_3;
252 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
253 break;
254 case IFE_E_PHY_ID:
255 case IFE_PLUS_E_PHY_ID:
256 case IFE_C_E_PHY_ID:
257 phy->type = e1000_phy_ife;
258 phy->autoneg_mask = E1000_ALL_NOT_GIG;
259 break;
260 case BME1000_E_PHY_ID:
261 phy->type = e1000_phy_bm;
262 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
263 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
264 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
265 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
266 break;
267 default:
268 return -E1000_ERR_PHY;
269 break;
270 }
271
272 return 0;
273}
274
275
276
277
278
279
280
281
282static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
283{
284 struct e1000_nvm_info *nvm = &hw->nvm;
285 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
286 u32 gfpreg;
287 u32 sector_base_addr;
288 u32 sector_end_addr;
289 u16 i;
290
291
292 if (!hw->flash_address) {
293 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
294 return -E1000_ERR_CONFIG;
295 }
296
297 nvm->type = e1000_nvm_flash_sw;
298
299 gfpreg = er32flash(ICH_FLASH_GFPREG);
300
301
302
303
304
305
306 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
307 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
308
309
310 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
311
312
313
314
315
316 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
317 << FLASH_SECTOR_ADDR_SHIFT;
318 nvm->flash_bank_size /= 2;
319
320 nvm->flash_bank_size /= sizeof(u16);
321
322 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
323
324
325 for (i = 0; i < nvm->word_size; i++) {
326 dev_spec->shadow_ram[i].modified = 0;
327 dev_spec->shadow_ram[i].value = 0xFFFF;
328 }
329
330 return 0;
331}
332
333
334
335
336
337
338
339
340static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
341{
342 struct e1000_hw *hw = &adapter->hw;
343 struct e1000_mac_info *mac = &hw->mac;
344
345
346 hw->phy.media_type = e1000_media_type_copper;
347
348
349 mac->mta_reg_count = 32;
350
351 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
352 if (mac->type == e1000_ich8lan)
353 mac->rar_entry_count--;
354
355 mac->arc_subsystem_valid = 1;
356
357
358 if (mac->type == e1000_ich8lan)
359 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
360
361 return 0;
362}
363
364static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
365{
366 struct e1000_hw *hw = &adapter->hw;
367 s32 rc;
368
369 rc = e1000_init_mac_params_ich8lan(adapter);
370 if (rc)
371 return rc;
372
373 rc = e1000_init_nvm_params_ich8lan(hw);
374 if (rc)
375 return rc;
376
377 rc = e1000_init_phy_params_ich8lan(hw);
378 if (rc)
379 return rc;
380
381 if ((adapter->hw.mac.type == e1000_ich8lan) &&
382 (adapter->hw.phy.type == e1000_phy_igp_3))
383 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
384
385 return 0;
386}
387
388static DEFINE_MUTEX(nvm_mutex);
389static pid_t nvm_owner = -1;
390
391
392
393
394
395
396
397
398
399static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
400{
401 u32 extcnf_ctrl;
402 u32 timeout = PHY_CFG_TIMEOUT;
403
404 might_sleep();
405
406 if (!mutex_trylock(&nvm_mutex)) {
407 WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n",
408 nvm_owner);
409 mutex_lock(&nvm_mutex);
410 }
411 nvm_owner = current->pid;
412
413 while (timeout) {
414 extcnf_ctrl = er32(EXTCNF_CTRL);
415 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
416 ew32(EXTCNF_CTRL, extcnf_ctrl);
417
418 extcnf_ctrl = er32(EXTCNF_CTRL);
419 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
420 break;
421 mdelay(1);
422 timeout--;
423 }
424
425 if (!timeout) {
426 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
427 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
428 ew32(EXTCNF_CTRL, extcnf_ctrl);
429 nvm_owner = -1;
430 mutex_unlock(&nvm_mutex);
431 return -E1000_ERR_CONFIG;
432 }
433
434 return 0;
435}
436
437
438
439
440
441
442
443
444
445static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
446{
447 u32 extcnf_ctrl;
448
449 extcnf_ctrl = er32(EXTCNF_CTRL);
450 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
451 ew32(EXTCNF_CTRL, extcnf_ctrl);
452
453 nvm_owner = -1;
454 mutex_unlock(&nvm_mutex);
455}
456
457
458
459
460
461
462
463
464
465static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
466{
467 u32 fwsm = er32(FWSM);
468
469 return (fwsm & E1000_FWSM_MODE_MASK) ==
470 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
471}
472
473
474
475
476
477
478
479
480
481static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
482{
483 u32 fwsm;
484
485 fwsm = er32(FWSM);
486
487 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
488}
489
490
491
492
493
494
495
496
497
498static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
499{
500 struct e1000_phy_info *phy = &hw->phy;
501 s32 ret_val;
502 u16 data;
503 bool link;
504
505 if (phy->type != e1000_phy_ife) {
506 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
507 return ret_val;
508 }
509
510 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
511 if (ret_val)
512 return ret_val;
513
514 e1000e_phy_force_speed_duplex_setup(hw, &data);
515
516 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
517 if (ret_val)
518 return ret_val;
519
520
521 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
522 if (ret_val)
523 return ret_val;
524
525 data &= ~IFE_PMC_AUTO_MDIX;
526 data &= ~IFE_PMC_FORCE_MDIX;
527
528 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
529 if (ret_val)
530 return ret_val;
531
532 hw_dbg(hw, "IFE PMC: %X\n", data);
533
534 udelay(1);
535
536 if (phy->autoneg_wait_to_complete) {
537 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
538
539 ret_val = e1000e_phy_has_link_generic(hw,
540 PHY_FORCE_LIMIT,
541 100000,
542 &link);
543 if (ret_val)
544 return ret_val;
545
546 if (!link)
547 hw_dbg(hw, "Link taking longer than expected.\n");
548
549
550 ret_val = e1000e_phy_has_link_generic(hw,
551 PHY_FORCE_LIMIT,
552 100000,
553 &link);
554 if (ret_val)
555 return ret_val;
556 }
557
558 return 0;
559}
560
561
562
563
564
565
566
567
568
569static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
570{
571 struct e1000_phy_info *phy = &hw->phy;
572 u32 i;
573 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
574 s32 ret_val;
575 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
576 u16 word_addr, reg_data, reg_addr, phy_page = 0;
577
578 ret_val = e1000e_phy_hw_reset_generic(hw);
579 if (ret_val)
580 return ret_val;
581
582
583
584
585
586
587
588
589 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
590 struct e1000_adapter *adapter = hw->adapter;
591
592
593 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
594 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
595 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
596 else
597 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
598
599 data = er32(FEXTNVM);
600 if (!(data & sw_cfg_mask))
601 return 0;
602
603
604 do {
605 data = er32(STATUS);
606 data &= E1000_STATUS_LAN_INIT_DONE;
607 udelay(100);
608 } while ((!data) && --loop);
609
610
611
612
613
614
615 if (loop == 0) {
616 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
617 }
618
619
620 data = er32(STATUS);
621 data &= ~E1000_STATUS_LAN_INIT_DONE;
622 ew32(STATUS, data);
623
624
625
626
627
628 data = er32(EXTCNF_CTRL);
629 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
630 return 0;
631
632 cnf_size = er32(EXTCNF_SIZE);
633 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
634 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
635 if (!cnf_size)
636 return 0;
637
638 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
639 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
640
641
642
643
644 word_addr = (u16)(cnf_base_addr << 1);
645
646 for (i = 0; i < cnf_size; i++) {
647 ret_val = e1000_read_nvm(hw,
648 (word_addr + i * 2),
649 1,
650 ®_data);
651 if (ret_val)
652 return ret_val;
653
654 ret_val = e1000_read_nvm(hw,
655 (word_addr + i * 2 + 1),
656 1,
657 ®_addr);
658 if (ret_val)
659 return ret_val;
660
661
662 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
663 phy_page = reg_data;
664 continue;
665 }
666
667 reg_addr |= phy_page;
668
669 ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
670 if (ret_val)
671 return ret_val;
672 }
673 }
674
675 return 0;
676}
677
678
679
680
681
682
683
684
685
686static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
687{
688 struct e1000_phy_info *phy = &hw->phy;
689 s32 ret_val;
690 u16 data;
691 bool link;
692
693 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
694 if (ret_val)
695 return ret_val;
696
697 if (!link) {
698 hw_dbg(hw, "Phy info is only valid if link is up\n");
699 return -E1000_ERR_CONFIG;
700 }
701
702 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
703 if (ret_val)
704 return ret_val;
705 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
706
707 if (phy->polarity_correction) {
708 ret_val = e1000_check_polarity_ife_ich8lan(hw);
709 if (ret_val)
710 return ret_val;
711 } else {
712
713 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
714 ? e1000_rev_polarity_reversed
715 : e1000_rev_polarity_normal;
716 }
717
718 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
719 if (ret_val)
720 return ret_val;
721
722 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
723
724
725 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
726 phy->local_rx = e1000_1000t_rx_status_undefined;
727 phy->remote_rx = e1000_1000t_rx_status_undefined;
728
729 return 0;
730}
731
732
733
734
735
736
737
738
739
740static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
741{
742 switch (hw->phy.type) {
743 case e1000_phy_ife:
744 return e1000_get_phy_info_ife_ich8lan(hw);
745 break;
746 case e1000_phy_igp_3:
747 case e1000_phy_bm:
748 return e1000e_get_phy_info_igp(hw);
749 break;
750 default:
751 break;
752 }
753
754 return -E1000_ERR_PHY_TYPE;
755}
756
757
758
759
760
761
762
763
764
765static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
766{
767 struct e1000_phy_info *phy = &hw->phy;
768 s32 ret_val;
769 u16 phy_data, offset, mask;
770
771
772
773
774 if (phy->polarity_correction) {
775 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
776 mask = IFE_PESC_POLARITY_REVERSED;
777 } else {
778 offset = IFE_PHY_SPECIAL_CONTROL;
779 mask = IFE_PSC_FORCE_POLARITY;
780 }
781
782 ret_val = e1e_rphy(hw, offset, &phy_data);
783
784 if (!ret_val)
785 phy->cable_polarity = (phy_data & mask)
786 ? e1000_rev_polarity_reversed
787 : e1000_rev_polarity_normal;
788
789 return ret_val;
790}
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
806{
807 struct e1000_phy_info *phy = &hw->phy;
808 u32 phy_ctrl;
809 s32 ret_val = 0;
810 u16 data;
811
812 if (phy->type == e1000_phy_ife)
813 return ret_val;
814
815 phy_ctrl = er32(PHY_CTRL);
816
817 if (active) {
818 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
819 ew32(PHY_CTRL, phy_ctrl);
820
821
822
823
824
825 if ((hw->mac.type == e1000_ich8lan) &&
826 (hw->phy.type == e1000_phy_igp_3))
827 e1000e_gig_downshift_workaround_ich8lan(hw);
828
829
830 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
831 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
832 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
833 if (ret_val)
834 return ret_val;
835 } else {
836 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
837 ew32(PHY_CTRL, phy_ctrl);
838
839
840
841
842
843
844
845 if (phy->smart_speed == e1000_smart_speed_on) {
846 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
847 &data);
848 if (ret_val)
849 return ret_val;
850
851 data |= IGP01E1000_PSCFR_SMART_SPEED;
852 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
853 data);
854 if (ret_val)
855 return ret_val;
856 } else if (phy->smart_speed == e1000_smart_speed_off) {
857 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
858 &data);
859 if (ret_val)
860 return ret_val;
861
862 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
863 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
864 data);
865 if (ret_val)
866 return ret_val;
867 }
868 }
869
870 return 0;
871}
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
887{
888 struct e1000_phy_info *phy = &hw->phy;
889 u32 phy_ctrl;
890 s32 ret_val;
891 u16 data;
892
893 phy_ctrl = er32(PHY_CTRL);
894
895 if (!active) {
896 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
897 ew32(PHY_CTRL, phy_ctrl);
898
899
900
901
902
903
904 if (phy->smart_speed == e1000_smart_speed_on) {
905 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
906 &data);
907 if (ret_val)
908 return ret_val;
909
910 data |= IGP01E1000_PSCFR_SMART_SPEED;
911 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
912 data);
913 if (ret_val)
914 return ret_val;
915 } else if (phy->smart_speed == e1000_smart_speed_off) {
916 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
917 &data);
918 if (ret_val)
919 return ret_val;
920
921 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
922 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
923 data);
924 if (ret_val)
925 return ret_val;
926 }
927 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
928 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
929 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
930 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
931 ew32(PHY_CTRL, phy_ctrl);
932
933
934
935
936
937 if ((hw->mac.type == e1000_ich8lan) &&
938 (hw->phy.type == e1000_phy_igp_3))
939 e1000e_gig_downshift_workaround_ich8lan(hw);
940
941
942 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
943 if (ret_val)
944 return ret_val;
945
946 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
947 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
948 }
949
950 return 0;
951}
952
953
954
955
956
957
958
959
960static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
961{
962 struct e1000_nvm_info *nvm = &hw->nvm;
963
964 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
965 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
966 u8 bank_high_byte = 0;
967
968 if (hw->mac.type != e1000_ich10lan) {
969 if (er32(EECD) & E1000_EECD_SEC1VAL)
970 *bank = 1;
971 else
972 *bank = 0;
973 } else {
974
975
976
977
978 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
979 if ((bank_high_byte & 0xC0) == 0x80) {
980 *bank = 0;
981 } else {
982
983
984
985
986 e1000_read_flash_byte_ich8lan(hw,
987 act_offset + bank1_offset,
988 &bank_high_byte);
989
990
991 if ((bank_high_byte & 0xC0) == 0x80) {
992 *bank = 1;
993 } else {
994 hw_dbg(hw, "ERROR: EEPROM not present\n");
995 return -E1000_ERR_NVM;
996 }
997 }
998 }
999
1000 return 0;
1001}
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1013 u16 *data)
1014{
1015 struct e1000_nvm_info *nvm = &hw->nvm;
1016 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1017 u32 act_offset;
1018 s32 ret_val;
1019 u32 bank = 0;
1020 u16 i, word;
1021
1022 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1023 (words == 0)) {
1024 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1025 return -E1000_ERR_NVM;
1026 }
1027
1028 ret_val = e1000_acquire_swflag_ich8lan(hw);
1029 if (ret_val)
1030 return ret_val;
1031
1032 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1033 if (ret_val)
1034 return ret_val;
1035
1036 act_offset = (bank) ? nvm->flash_bank_size : 0;
1037 act_offset += offset;
1038
1039 for (i = 0; i < words; i++) {
1040 if ((dev_spec->shadow_ram) &&
1041 (dev_spec->shadow_ram[offset+i].modified)) {
1042 data[i] = dev_spec->shadow_ram[offset+i].value;
1043 } else {
1044 ret_val = e1000_read_flash_word_ich8lan(hw,
1045 act_offset + i,
1046 &word);
1047 if (ret_val)
1048 break;
1049 data[i] = word;
1050 }
1051 }
1052
1053 e1000_release_swflag_ich8lan(hw);
1054
1055 return ret_val;
1056}
1057
1058
1059
1060
1061
1062
1063
1064
1065static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1066{
1067 union ich8_hws_flash_status hsfsts;
1068 s32 ret_val = -E1000_ERR_NVM;
1069 s32 i = 0;
1070
1071 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1072
1073
1074 if (hsfsts.hsf_status.fldesvalid == 0) {
1075 hw_dbg(hw, "Flash descriptor invalid. "
1076 "SW Sequencing must be used.");
1077 return -E1000_ERR_NVM;
1078 }
1079
1080
1081 hsfsts.hsf_status.flcerr = 1;
1082 hsfsts.hsf_status.dael = 1;
1083
1084 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095 if (hsfsts.hsf_status.flcinprog == 0) {
1096
1097
1098
1099
1100
1101 hsfsts.hsf_status.flcdone = 1;
1102 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1103 ret_val = 0;
1104 } else {
1105
1106
1107
1108
1109 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1110 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1111 if (hsfsts.hsf_status.flcinprog == 0) {
1112 ret_val = 0;
1113 break;
1114 }
1115 udelay(1);
1116 }
1117 if (ret_val == 0) {
1118
1119
1120
1121
1122 hsfsts.hsf_status.flcdone = 1;
1123 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1124 } else {
1125 hw_dbg(hw, "Flash controller busy, cannot get access");
1126 }
1127 }
1128
1129 return ret_val;
1130}
1131
1132
1133
1134
1135
1136
1137
1138
1139static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1140{
1141 union ich8_hws_flash_ctrl hsflctl;
1142 union ich8_hws_flash_status hsfsts;
1143 s32 ret_val = -E1000_ERR_NVM;
1144 u32 i = 0;
1145
1146
1147 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1148 hsflctl.hsf_ctrl.flcgo = 1;
1149 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1150
1151
1152 do {
1153 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1154 if (hsfsts.hsf_status.flcdone == 1)
1155 break;
1156 udelay(1);
1157 } while (i++ < timeout);
1158
1159 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1160 return 0;
1161
1162 return ret_val;
1163}
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1175 u16 *data)
1176{
1177
1178 offset <<= 1;
1179
1180 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1181}
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1192 u8 *data)
1193{
1194 s32 ret_val;
1195 u16 word = 0;
1196
1197 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1198 if (ret_val)
1199 return ret_val;
1200
1201 *data = (u8)word;
1202
1203 return 0;
1204}
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1216 u8 size, u16 *data)
1217{
1218 union ich8_hws_flash_status hsfsts;
1219 union ich8_hws_flash_ctrl hsflctl;
1220 u32 flash_linear_addr;
1221 u32 flash_data = 0;
1222 s32 ret_val = -E1000_ERR_NVM;
1223 u8 count = 0;
1224
1225 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1226 return -E1000_ERR_NVM;
1227
1228 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1229 hw->nvm.flash_base_addr;
1230
1231 do {
1232 udelay(1);
1233
1234 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1235 if (ret_val != 0)
1236 break;
1237
1238 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1239
1240 hsflctl.hsf_ctrl.fldbcount = size - 1;
1241 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1242 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1243
1244 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1245
1246 ret_val = e1000_flash_cycle_ich8lan(hw,
1247 ICH_FLASH_READ_COMMAND_TIMEOUT);
1248
1249
1250
1251
1252
1253
1254
1255 if (ret_val == 0) {
1256 flash_data = er32flash(ICH_FLASH_FDATA0);
1257 if (size == 1) {
1258 *data = (u8)(flash_data & 0x000000FF);
1259 } else if (size == 2) {
1260 *data = (u16)(flash_data & 0x0000FFFF);
1261 }
1262 break;
1263 } else {
1264
1265
1266
1267
1268
1269
1270 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1271 if (hsfsts.hsf_status.flcerr == 1) {
1272
1273 continue;
1274 } else if (hsfsts.hsf_status.flcdone == 0) {
1275 hw_dbg(hw, "Timeout error - flash cycle "
1276 "did not complete.");
1277 break;
1278 }
1279 }
1280 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1281
1282 return ret_val;
1283}
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1295 u16 *data)
1296{
1297 struct e1000_nvm_info *nvm = &hw->nvm;
1298 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1299 s32 ret_val;
1300 u16 i;
1301
1302 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1303 (words == 0)) {
1304 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1305 return -E1000_ERR_NVM;
1306 }
1307
1308 ret_val = e1000_acquire_swflag_ich8lan(hw);
1309 if (ret_val)
1310 return ret_val;
1311
1312 for (i = 0; i < words; i++) {
1313 dev_spec->shadow_ram[offset+i].modified = 1;
1314 dev_spec->shadow_ram[offset+i].value = data[i];
1315 }
1316
1317 e1000_release_swflag_ich8lan(hw);
1318
1319 return 0;
1320}
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1334{
1335 struct e1000_nvm_info *nvm = &hw->nvm;
1336 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1337 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1338 s32 ret_val;
1339 u16 data;
1340
1341 ret_val = e1000e_update_nvm_checksum_generic(hw);
1342 if (ret_val)
1343 return ret_val;
1344
1345 if (nvm->type != e1000_nvm_flash_sw)
1346 return ret_val;
1347
1348 ret_val = e1000_acquire_swflag_ich8lan(hw);
1349 if (ret_val)
1350 return ret_val;
1351
1352
1353
1354
1355
1356
1357 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1358 if (ret_val)
1359 return ret_val;
1360
1361 if (bank == 0) {
1362 new_bank_offset = nvm->flash_bank_size;
1363 old_bank_offset = 0;
1364 e1000_erase_flash_bank_ich8lan(hw, 1);
1365 } else {
1366 old_bank_offset = nvm->flash_bank_size;
1367 new_bank_offset = 0;
1368 e1000_erase_flash_bank_ich8lan(hw, 0);
1369 }
1370
1371 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1372
1373
1374
1375
1376
1377 if (dev_spec->shadow_ram[i].modified) {
1378 data = dev_spec->shadow_ram[i].value;
1379 } else {
1380 e1000_read_flash_word_ich8lan(hw,
1381 i + old_bank_offset,
1382 &data);
1383 }
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393 if (i == E1000_ICH_NVM_SIG_WORD)
1394 data |= E1000_ICH_NVM_SIG_MASK;
1395
1396
1397 act_offset = (i + new_bank_offset) << 1;
1398
1399 udelay(100);
1400
1401 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1402 act_offset,
1403 (u8)data);
1404 if (ret_val)
1405 break;
1406
1407 udelay(100);
1408 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1409 act_offset + 1,
1410 (u8)(data >> 8));
1411 if (ret_val)
1412 break;
1413 }
1414
1415
1416
1417
1418
1419 if (ret_val) {
1420
1421 hw_dbg(hw, "Flash commit failed.\n");
1422 e1000_release_swflag_ich8lan(hw);
1423 return ret_val;
1424 }
1425
1426
1427
1428
1429
1430
1431
1432 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1433 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1434 data &= 0xBFFF;
1435 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1436 act_offset * 2 + 1,
1437 (u8)(data >> 8));
1438 if (ret_val) {
1439 e1000_release_swflag_ich8lan(hw);
1440 return ret_val;
1441 }
1442
1443
1444
1445
1446
1447
1448
1449 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1450 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1451 if (ret_val) {
1452 e1000_release_swflag_ich8lan(hw);
1453 return ret_val;
1454 }
1455
1456
1457 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1458 dev_spec->shadow_ram[i].modified = 0;
1459 dev_spec->shadow_ram[i].value = 0xFFFF;
1460 }
1461
1462 e1000_release_swflag_ich8lan(hw);
1463
1464
1465
1466
1467
1468 e1000e_reload_nvm(hw);
1469 msleep(10);
1470
1471 return ret_val;
1472}
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1483{
1484 s32 ret_val;
1485 u16 data;
1486
1487
1488
1489
1490
1491
1492
1493 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1494 if (ret_val)
1495 return ret_val;
1496
1497 if ((data & 0x40) == 0) {
1498 data |= 0x40;
1499 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1500 if (ret_val)
1501 return ret_val;
1502 ret_val = e1000e_update_nvm_checksum(hw);
1503 if (ret_val)
1504 return ret_val;
1505 }
1506
1507 return e1000e_validate_nvm_checksum_generic(hw);
1508}
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1521{
1522 union ich8_flash_protected_range pr0;
1523 union ich8_hws_flash_status hsfsts;
1524 u32 gfpreg;
1525 s32 ret_val;
1526
1527 ret_val = e1000_acquire_swflag_ich8lan(hw);
1528 if (ret_val)
1529 return;
1530
1531 gfpreg = er32flash(ICH_FLASH_GFPREG);
1532
1533
1534 pr0.regval = er32flash(ICH_FLASH_PR0);
1535 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1536 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1537 pr0.range.wpe = true;
1538 ew32flash(ICH_FLASH_PR0, pr0.regval);
1539
1540
1541
1542
1543
1544
1545
1546 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1547 hsfsts.hsf_status.flockdn = true;
1548 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1549
1550 e1000_release_swflag_ich8lan(hw);
1551}
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1563 u8 size, u16 data)
1564{
1565 union ich8_hws_flash_status hsfsts;
1566 union ich8_hws_flash_ctrl hsflctl;
1567 u32 flash_linear_addr;
1568 u32 flash_data = 0;
1569 s32 ret_val;
1570 u8 count = 0;
1571
1572 if (size < 1 || size > 2 || data > size * 0xff ||
1573 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1574 return -E1000_ERR_NVM;
1575
1576 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1577 hw->nvm.flash_base_addr;
1578
1579 do {
1580 udelay(1);
1581
1582 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1583 if (ret_val)
1584 break;
1585
1586 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1587
1588 hsflctl.hsf_ctrl.fldbcount = size -1;
1589 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1590 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1591
1592 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1593
1594 if (size == 1)
1595 flash_data = (u32)data & 0x00FF;
1596 else
1597 flash_data = (u32)data;
1598
1599 ew32flash(ICH_FLASH_FDATA0, flash_data);
1600
1601
1602
1603
1604
1605 ret_val = e1000_flash_cycle_ich8lan(hw,
1606 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1607 if (!ret_val)
1608 break;
1609
1610
1611
1612
1613
1614
1615
1616 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1617 if (hsfsts.hsf_status.flcerr == 1)
1618
1619 continue;
1620 if (hsfsts.hsf_status.flcdone == 0) {
1621 hw_dbg(hw, "Timeout error - flash cycle "
1622 "did not complete.");
1623 break;
1624 }
1625 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1626
1627 return ret_val;
1628}
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1639 u8 data)
1640{
1641 u16 word = (u16)data;
1642
1643 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1644}
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1656 u32 offset, u8 byte)
1657{
1658 s32 ret_val;
1659 u16 program_retries;
1660
1661 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1662 if (!ret_val)
1663 return ret_val;
1664
1665 for (program_retries = 0; program_retries < 100; program_retries++) {
1666 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1667 udelay(100);
1668 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1669 if (!ret_val)
1670 break;
1671 }
1672 if (program_retries == 100)
1673 return -E1000_ERR_NVM;
1674
1675 return 0;
1676}
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1687{
1688 struct e1000_nvm_info *nvm = &hw->nvm;
1689 union ich8_hws_flash_status hsfsts;
1690 union ich8_hws_flash_ctrl hsflctl;
1691 u32 flash_linear_addr;
1692
1693 u32 flash_bank_size = nvm->flash_bank_size * 2;
1694 s32 ret_val;
1695 s32 count = 0;
1696 s32 iteration;
1697 s32 sector_size;
1698 s32 j;
1699
1700 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715 switch (hsfsts.hsf_status.berasesz) {
1716 case 0:
1717
1718 sector_size = ICH_FLASH_SEG_SIZE_256;
1719 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1720 break;
1721 case 1:
1722 sector_size = ICH_FLASH_SEG_SIZE_4K;
1723 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1724 break;
1725 case 2:
1726 if (hw->mac.type == e1000_ich9lan) {
1727 sector_size = ICH_FLASH_SEG_SIZE_8K;
1728 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1729 } else {
1730 return -E1000_ERR_NVM;
1731 }
1732 break;
1733 case 3:
1734 sector_size = ICH_FLASH_SEG_SIZE_64K;
1735 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1736 break;
1737 default:
1738 return -E1000_ERR_NVM;
1739 }
1740
1741
1742 flash_linear_addr = hw->nvm.flash_base_addr;
1743 flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1744
1745 for (j = 0; j < iteration ; j++) {
1746 do {
1747
1748 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1749 if (ret_val)
1750 return ret_val;
1751
1752
1753
1754
1755
1756 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1757 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1758 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1759
1760
1761
1762
1763
1764
1765 flash_linear_addr += (j * sector_size);
1766 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1767
1768 ret_val = e1000_flash_cycle_ich8lan(hw,
1769 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1770 if (ret_val == 0)
1771 break;
1772
1773
1774
1775
1776
1777
1778 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1779 if (hsfsts.hsf_status.flcerr == 1)
1780
1781 continue;
1782 else if (hsfsts.hsf_status.flcdone == 0)
1783 return ret_val;
1784 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1785 }
1786
1787 return 0;
1788}
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1800{
1801 s32 ret_val;
1802
1803 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1804 if (ret_val) {
1805 hw_dbg(hw, "NVM Read Error\n");
1806 return ret_val;
1807 }
1808
1809 if (*data == ID_LED_RESERVED_0000 ||
1810 *data == ID_LED_RESERVED_FFFF)
1811 *data = ID_LED_DEFAULT_ICH8LAN;
1812
1813 return 0;
1814}
1815
1816
1817
1818
1819
1820
1821
1822
1823static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1824{
1825 struct e1000_bus_info *bus = &hw->bus;
1826 s32 ret_val;
1827
1828 ret_val = e1000e_get_bus_info_pcie(hw);
1829
1830
1831
1832
1833
1834
1835
1836 if (bus->width == e1000_bus_width_unknown)
1837 bus->width = e1000_bus_width_pcie_x1;
1838
1839 return ret_val;
1840}
1841
1842
1843
1844
1845
1846
1847
1848
1849static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1850{
1851 u32 ctrl, icr, kab;
1852 s32 ret_val;
1853
1854
1855
1856
1857
1858 ret_val = e1000e_disable_pcie_master(hw);
1859 if (ret_val) {
1860 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1861 }
1862
1863 hw_dbg(hw, "Masking off all interrupts\n");
1864 ew32(IMC, 0xffffffff);
1865
1866
1867
1868
1869
1870
1871 ew32(RCTL, 0);
1872 ew32(TCTL, E1000_TCTL_PSP);
1873 e1e_flush();
1874
1875 msleep(10);
1876
1877
1878 if (hw->mac.type == e1000_ich8lan) {
1879
1880 ew32(PBA, E1000_PBA_8K);
1881
1882 ew32(PBS, E1000_PBS_16K);
1883 }
1884
1885 ctrl = er32(CTRL);
1886
1887 if (!e1000_check_reset_block(hw)) {
1888
1889
1890
1891
1892
1893 ctrl |= E1000_CTRL_PHY_RST;
1894 }
1895 ret_val = e1000_acquire_swflag_ich8lan(hw);
1896
1897 hw_dbg(hw, "Issuing a global reset to ich8lan");
1898 ew32(CTRL, (ctrl | E1000_CTRL_RST));
1899 msleep(20);
1900
1901 if (!ret_val) {
1902
1903
1904
1905 e1000_release_swflag_ich8lan(hw);
1906 }
1907
1908 ret_val = e1000e_get_auto_rd_done(hw);
1909 if (ret_val) {
1910
1911
1912
1913
1914
1915 hw_dbg(hw, "Auto Read Done did not complete\n");
1916 }
1917
1918 ew32(IMC, 0xffffffff);
1919 icr = er32(ICR);
1920
1921 kab = er32(KABGTXD);
1922 kab |= E1000_KABGTXD_BGSQLBIAS;
1923 ew32(KABGTXD, kab);
1924
1925 return ret_val;
1926}
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1941{
1942 struct e1000_mac_info *mac = &hw->mac;
1943 u32 ctrl_ext, txdctl, snoop;
1944 s32 ret_val;
1945 u16 i;
1946
1947 e1000_initialize_hw_bits_ich8lan(hw);
1948
1949
1950 ret_val = e1000e_id_led_init(hw);
1951 if (ret_val) {
1952 hw_dbg(hw, "Error initializing identification LED\n");
1953 return ret_val;
1954 }
1955
1956
1957 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1958
1959
1960 hw_dbg(hw, "Zeroing the MTA\n");
1961 for (i = 0; i < mac->mta_reg_count; i++)
1962 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1963
1964
1965 ret_val = e1000_setup_link_ich8lan(hw);
1966
1967
1968 txdctl = er32(TXDCTL(0));
1969 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1970 E1000_TXDCTL_FULL_TX_DESC_WB;
1971 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1972 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1973 ew32(TXDCTL(0), txdctl);
1974 txdctl = er32(TXDCTL(1));
1975 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1976 E1000_TXDCTL_FULL_TX_DESC_WB;
1977 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1978 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1979 ew32(TXDCTL(1), txdctl);
1980
1981
1982
1983
1984
1985 if (mac->type == e1000_ich8lan)
1986 snoop = PCIE_ICH8_SNOOP_ALL;
1987 else
1988 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1989 e1000e_set_pcie_no_snoop(hw, snoop);
1990
1991 ctrl_ext = er32(CTRL_EXT);
1992 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1993 ew32(CTRL_EXT, ctrl_ext);
1994
1995
1996
1997
1998
1999
2000
2001 e1000_clear_hw_cntrs_ich8lan(hw);
2002
2003 return 0;
2004}
2005
2006
2007
2008
2009
2010
2011
2012static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2013{
2014 u32 reg;
2015
2016
2017 reg = er32(CTRL_EXT);
2018 reg |= (1 << 22);
2019 ew32(CTRL_EXT, reg);
2020
2021
2022 reg = er32(TXDCTL(0));
2023 reg |= (1 << 22);
2024 ew32(TXDCTL(0), reg);
2025
2026
2027 reg = er32(TXDCTL(1));
2028 reg |= (1 << 22);
2029 ew32(TXDCTL(1), reg);
2030
2031
2032 reg = er32(TARC(0));
2033 if (hw->mac.type == e1000_ich8lan)
2034 reg |= (1 << 28) | (1 << 29);
2035 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2036 ew32(TARC(0), reg);
2037
2038
2039 reg = er32(TARC(1));
2040 if (er32(TCTL) & E1000_TCTL_MULR)
2041 reg &= ~(1 << 28);
2042 else
2043 reg |= (1 << 28);
2044 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2045 ew32(TARC(1), reg);
2046
2047
2048 if (hw->mac.type == e1000_ich8lan) {
2049 reg = er32(STATUS);
2050 reg &= ~(1 << 31);
2051 ew32(STATUS, reg);
2052 }
2053}
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2066{
2067 s32 ret_val;
2068
2069 if (e1000_check_reset_block(hw))
2070 return 0;
2071
2072
2073
2074
2075
2076
2077 if (hw->fc.type == e1000_fc_default)
2078 hw->fc.type = e1000_fc_full;
2079
2080 hw->fc.original_type = hw->fc.type;
2081
2082 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
2083
2084
2085 ret_val = e1000_setup_copper_link_ich8lan(hw);
2086 if (ret_val)
2087 return ret_val;
2088
2089 ew32(FCTTV, hw->fc.pause_time);
2090
2091 return e1000e_set_fc_watermarks(hw);
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2103{
2104 u32 ctrl;
2105 s32 ret_val;
2106 u16 reg_data;
2107
2108 ctrl = er32(CTRL);
2109 ctrl |= E1000_CTRL_SLU;
2110 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2111 ew32(CTRL, ctrl);
2112
2113
2114
2115
2116
2117
2118 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2119 if (ret_val)
2120 return ret_val;
2121 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
2122 if (ret_val)
2123 return ret_val;
2124 reg_data |= 0x3F;
2125 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2126 if (ret_val)
2127 return ret_val;
2128
2129 if (hw->phy.type == e1000_phy_igp_3) {
2130 ret_val = e1000e_copper_link_setup_igp(hw);
2131 if (ret_val)
2132 return ret_val;
2133 } else if (hw->phy.type == e1000_phy_bm) {
2134 ret_val = e1000e_copper_link_setup_m88(hw);
2135 if (ret_val)
2136 return ret_val;
2137 }
2138
2139 if (hw->phy.type == e1000_phy_ife) {
2140 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
2141 if (ret_val)
2142 return ret_val;
2143
2144 reg_data &= ~IFE_PMC_AUTO_MDIX;
2145
2146 switch (hw->phy.mdix) {
2147 case 1:
2148 reg_data &= ~IFE_PMC_FORCE_MDIX;
2149 break;
2150 case 2:
2151 reg_data |= IFE_PMC_FORCE_MDIX;
2152 break;
2153 case 0:
2154 default:
2155 reg_data |= IFE_PMC_AUTO_MDIX;
2156 break;
2157 }
2158 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2159 if (ret_val)
2160 return ret_val;
2161 }
2162 return e1000e_setup_copper_link(hw);
2163}
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2176 u16 *duplex)
2177{
2178 s32 ret_val;
2179
2180 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2181 if (ret_val)
2182 return ret_val;
2183
2184 if ((hw->mac.type == e1000_ich8lan) &&
2185 (hw->phy.type == e1000_phy_igp_3) &&
2186 (*speed == SPEED_1000)) {
2187 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2188 }
2189
2190 return ret_val;
2191}
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2209{
2210 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2211 u32 phy_ctrl;
2212 s32 ret_val;
2213 u16 i, data;
2214 bool link;
2215
2216 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2217 return 0;
2218
2219
2220
2221
2222
2223
2224 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2225 if (!link)
2226 return 0;
2227
2228 for (i = 0; i < 10; i++) {
2229
2230 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2231 if (ret_val)
2232 return ret_val;
2233
2234 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2235 if (ret_val)
2236 return ret_val;
2237
2238
2239 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2240 return 0;
2241
2242
2243 e1000_phy_hw_reset(hw);
2244 mdelay(5);
2245 }
2246
2247 phy_ctrl = er32(PHY_CTRL);
2248 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2249 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2250 ew32(PHY_CTRL, phy_ctrl);
2251
2252
2253
2254
2255
2256 e1000e_gig_downshift_workaround_ich8lan(hw);
2257
2258
2259 return -E1000_ERR_PHY;
2260}
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2271 bool state)
2272{
2273 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2274
2275 if (hw->mac.type != e1000_ich8lan) {
2276 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2277 return;
2278 }
2279
2280 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2281}
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2294{
2295 u32 reg;
2296 u16 data;
2297 u8 retry = 0;
2298
2299 if (hw->phy.type != e1000_phy_igp_3)
2300 return;
2301
2302
2303 do {
2304
2305 reg = er32(PHY_CTRL);
2306 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2307 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2308 ew32(PHY_CTRL, reg);
2309
2310
2311
2312
2313
2314 if (hw->mac.type == e1000_ich8lan)
2315 e1000e_gig_downshift_workaround_ich8lan(hw);
2316
2317
2318 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2319 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2320 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2321
2322
2323 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2324 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2325 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2326 break;
2327
2328
2329 reg = er32(CTRL);
2330 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2331 retry++;
2332 } while (retry);
2333}
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2346{
2347 s32 ret_val;
2348 u16 reg_data;
2349
2350 if ((hw->mac.type != e1000_ich8lan) ||
2351 (hw->phy.type != e1000_phy_igp_3))
2352 return;
2353
2354 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2355 ®_data);
2356 if (ret_val)
2357 return;
2358 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2359 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2360 reg_data);
2361 if (ret_val)
2362 return;
2363 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2364 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2365 reg_data);
2366}
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2380{
2381 u32 phy_ctrl;
2382
2383 if ((hw->mac.type == e1000_ich10lan) ||
2384 (hw->mac.type == e1000_ich9lan)) {
2385 phy_ctrl = er32(PHY_CTRL);
2386 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2387 E1000_PHY_CTRL_GBE_DISABLE;
2388 ew32(PHY_CTRL, phy_ctrl);
2389 }
2390
2391 return;
2392}
2393
2394
2395
2396
2397
2398
2399
2400static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2401{
2402 if (hw->phy.type == e1000_phy_ife)
2403 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2404
2405 ew32(LEDCTL, hw->mac.ledctl_default);
2406 return 0;
2407}
2408
2409
2410
2411
2412
2413
2414
2415static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2416{
2417 if (hw->phy.type == e1000_phy_ife)
2418 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2419 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2420
2421 ew32(LEDCTL, hw->mac.ledctl_mode2);
2422 return 0;
2423}
2424
2425
2426
2427
2428
2429
2430
2431static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2432{
2433 if (hw->phy.type == e1000_phy_ife)
2434 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2435 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2436
2437 ew32(LEDCTL, hw->mac.ledctl_mode1);
2438 return 0;
2439}
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2452{
2453 u32 bank = 0;
2454
2455 e1000e_get_cfg_done(hw);
2456
2457
2458 if (hw->mac.type != e1000_ich10lan) {
2459 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2460 (hw->phy.type == e1000_phy_igp_3)) {
2461 e1000e_phy_init_script_igp3(hw);
2462 }
2463 } else {
2464 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2465
2466 hw_dbg(hw, "EEPROM not present\n");
2467 return -E1000_ERR_CONFIG;
2468 }
2469 }
2470
2471 return 0;
2472}
2473
2474
2475
2476
2477
2478
2479
2480
2481static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2482{
2483 u32 temp;
2484
2485 e1000e_clear_hw_cntrs_base(hw);
2486
2487 temp = er32(ALGNERRC);
2488 temp = er32(RXERRC);
2489 temp = er32(TNCRS);
2490 temp = er32(CEXTERR);
2491 temp = er32(TSCTC);
2492 temp = er32(TSCTFC);
2493
2494 temp = er32(MGTPRC);
2495 temp = er32(MGTPDC);
2496 temp = er32(MGTPTC);
2497
2498 temp = er32(IAC);
2499 temp = er32(ICRXOC);
2500
2501}
2502
2503static struct e1000_mac_operations ich8_mac_ops = {
2504 .check_mng_mode = e1000_check_mng_mode_ich8lan,
2505 .check_for_link = e1000e_check_for_copper_link,
2506 .cleanup_led = e1000_cleanup_led_ich8lan,
2507 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
2508 .get_bus_info = e1000_get_bus_info_ich8lan,
2509 .get_link_up_info = e1000_get_link_up_info_ich8lan,
2510 .led_on = e1000_led_on_ich8lan,
2511 .led_off = e1000_led_off_ich8lan,
2512 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
2513 .reset_hw = e1000_reset_hw_ich8lan,
2514 .init_hw = e1000_init_hw_ich8lan,
2515 .setup_link = e1000_setup_link_ich8lan,
2516 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2517};
2518
2519static struct e1000_phy_operations ich8_phy_ops = {
2520 .acquire_phy = e1000_acquire_swflag_ich8lan,
2521 .check_reset_block = e1000_check_reset_block_ich8lan,
2522 .commit_phy = NULL,
2523 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
2524 .get_cfg_done = e1000_get_cfg_done_ich8lan,
2525 .get_cable_length = e1000e_get_cable_length_igp_2,
2526 .get_phy_info = e1000_get_phy_info_ich8lan,
2527 .read_phy_reg = e1000e_read_phy_reg_igp,
2528 .release_phy = e1000_release_swflag_ich8lan,
2529 .reset_phy = e1000_phy_hw_reset_ich8lan,
2530 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
2531 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
2532 .write_phy_reg = e1000e_write_phy_reg_igp,
2533};
2534
2535static struct e1000_nvm_operations ich8_nvm_ops = {
2536 .acquire_nvm = e1000_acquire_swflag_ich8lan,
2537 .read_nvm = e1000_read_nvm_ich8lan,
2538 .release_nvm = e1000_release_swflag_ich8lan,
2539 .update_nvm = e1000_update_nvm_checksum_ich8lan,
2540 .valid_led_default = e1000_valid_led_default_ich8lan,
2541 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
2542 .write_nvm = e1000_write_nvm_ich8lan,
2543};
2544
2545struct e1000_info e1000_ich8_info = {
2546 .mac = e1000_ich8lan,
2547 .flags = FLAG_HAS_WOL
2548 | FLAG_IS_ICH
2549 | FLAG_RX_CSUM_ENABLED
2550 | FLAG_HAS_CTRLEXT_ON_LOAD
2551 | FLAG_HAS_AMT
2552 | FLAG_HAS_FLASH
2553 | FLAG_APME_IN_WUC,
2554 .pba = 8,
2555 .get_variants = e1000_get_variants_ich8lan,
2556 .mac_ops = &ich8_mac_ops,
2557 .phy_ops = &ich8_phy_ops,
2558 .nvm_ops = &ich8_nvm_ops,
2559};
2560
2561struct e1000_info e1000_ich9_info = {
2562 .mac = e1000_ich9lan,
2563 .flags = FLAG_HAS_JUMBO_FRAMES
2564 | FLAG_IS_ICH
2565 | FLAG_HAS_WOL
2566 | FLAG_RX_CSUM_ENABLED
2567 | FLAG_HAS_CTRLEXT_ON_LOAD
2568 | FLAG_HAS_AMT
2569 | FLAG_HAS_ERT
2570 | FLAG_HAS_FLASH
2571 | FLAG_APME_IN_WUC,
2572 .pba = 10,
2573 .get_variants = e1000_get_variants_ich8lan,
2574 .mac_ops = &ich8_mac_ops,
2575 .phy_ops = &ich8_phy_ops,
2576 .nvm_ops = &ich8_nvm_ops,
2577};
2578
2579struct e1000_info e1000_ich10_info = {
2580 .mac = e1000_ich10lan,
2581 .flags = FLAG_HAS_JUMBO_FRAMES
2582 | FLAG_IS_ICH
2583 | FLAG_HAS_WOL
2584 | FLAG_RX_CSUM_ENABLED
2585 | FLAG_HAS_CTRLEXT_ON_LOAD
2586 | FLAG_HAS_AMT
2587 | FLAG_HAS_ERT
2588 | FLAG_HAS_FLASH
2589 | FLAG_APME_IN_WUC,
2590 .pba = 10,
2591 .get_variants = e1000_get_variants_ich8lan,
2592 .mac_ops = &ich8_mac_ops,
2593 .phy_ops = &ich8_phy_ops,
2594 .nvm_ops = &ich8_nvm_ops,
2595};