Showing error 1213

User: Jiri Slaby
Error type: Double Unlock
Error type description: Some lock is unlocked twice unintentionally in a sequence
File location: drivers/net/e1000/e1000_hw.c
Line in file: 4914
Project: Linux Kernel
Project version: 2.6.28
Tools: Stanse (1.2)
Entered: 2012-04-30 10:52:00 UTC


Source:

   1/*******************************************************************************
   2
   3  Intel PRO/1000 Linux driver
   4  Copyright(c) 1999 - 2006 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  Linux NICS <linux.nics@intel.com>
  24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27*******************************************************************************/
  28
  29/* e1000_hw.c
  30 * Shared functions for accessing and configuring the MAC
  31 */
  32
  33
  34#include "e1000_hw.h"
  35
  36static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
  37static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
  38static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
  39static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
  40static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
  41static void e1000_release_software_semaphore(struct e1000_hw *hw);
  42
  43static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
  44static s32 e1000_check_downshift(struct e1000_hw *hw);
  45static s32 e1000_check_polarity(struct e1000_hw *hw,
  46                                e1000_rev_polarity *polarity);
  47static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
  48static void e1000_clear_vfta(struct e1000_hw *hw);
  49static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
  50static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
  51                                              bool link_up);
  52static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
  53static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
  54static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
  55static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
  56static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
  57                                  u16 *max_length);
  58static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  59static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
  60static s32 e1000_get_software_flag(struct e1000_hw *hw);
  61static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
  62static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
  63static s32 e1000_id_led_init(struct e1000_hw *hw);
  64static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
  65                                                 u32 cnf_base_addr,
  66                                                 u32 cnf_size);
  67static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
  68static void e1000_init_rx_addrs(struct e1000_hw *hw);
  69static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
  70static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
  71static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
  72static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
  73static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
  74                                   u16 offset, u8 *sum);
  75static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
  76                                      struct e1000_host_mng_command_header
  77                                      *hdr);
  78static s32 e1000_mng_write_commit(struct e1000_hw *hw);
  79static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
  80                                  struct e1000_phy_info *phy_info);
  81static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
  82                                  struct e1000_phy_info *phy_info);
  83static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
  84                                  u16 *data);
  85static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
  86                                   u16 *data);
  87static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
  88static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
  89                                  struct e1000_phy_info *phy_info);
  90static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  91static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
  92static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
  93                                        u8 byte);
  94static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
  95static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
  96static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
  97                                u16 *data);
  98static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
  99                                 u16 data);
 100static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
 101                                  u16 *data);
 102static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
 103                                   u16 *data);
 104static void e1000_release_software_flag(struct e1000_hw *hw);
 105static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
 106static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
 107static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
 108static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
 109static s32 e1000_wait_autoneg(struct e1000_hw *hw);
 110static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
 111static s32 e1000_set_phy_type(struct e1000_hw *hw);
 112static void e1000_phy_init_script(struct e1000_hw *hw);
 113static s32 e1000_setup_copper_link(struct e1000_hw *hw);
 114static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
 115static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
 116static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
 117static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
 118static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
 119static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
 120static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
 121                                     u16 count);
 122static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
 123static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
 124static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
 125                                      u16 words, u16 *data);
 126static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
 127                                        u16 words, u16 *data);
 128static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
 129static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
 130static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
 131static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
 132static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
 133                                  u16 phy_data);
 134static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
 135                                 u16 *phy_data);
 136static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
 137static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
 138static void e1000_release_eeprom(struct e1000_hw *hw);
 139static void e1000_standby_eeprom(struct e1000_hw *hw);
 140static s32 e1000_set_vco_speed(struct e1000_hw *hw);
 141static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
 142static s32 e1000_set_phy_mode(struct e1000_hw *hw);
 143static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
 144static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
 145static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
 146static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
 147static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 148static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 149
 150/* IGP cable length table */
 151static const
 152u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
 153    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
 154      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
 155      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
 156      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
 157      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
 158      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
 159      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
 160      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
 161
 162static const
 163u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
 164    { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
 165      0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
 166      6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
 167      21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
 168      40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
 169      60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
 170      83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
 171      104, 109, 114, 118, 121, 124};
 172
 173static DEFINE_SPINLOCK(e1000_eeprom_lock);
 174
 175/******************************************************************************
 176 * Set the phy type member in the hw struct.
 177 *
 178 * hw - Struct containing variables accessed by shared code
 179 *****************************************************************************/
 180static s32 e1000_set_phy_type(struct e1000_hw *hw)
 181{
 182    DEBUGFUNC("e1000_set_phy_type");
 183
 184    if (hw->mac_type == e1000_undefined)
 185        return -E1000_ERR_PHY_TYPE;
 186
 187    switch (hw->phy_id) {
 188    case M88E1000_E_PHY_ID:
 189    case M88E1000_I_PHY_ID:
 190    case M88E1011_I_PHY_ID:
 191    case M88E1111_I_PHY_ID:
 192        hw->phy_type = e1000_phy_m88;
 193        break;
 194    case IGP01E1000_I_PHY_ID:
 195        if (hw->mac_type == e1000_82541 ||
 196            hw->mac_type == e1000_82541_rev_2 ||
 197            hw->mac_type == e1000_82547 ||
 198            hw->mac_type == e1000_82547_rev_2) {
 199            hw->phy_type = e1000_phy_igp;
 200            break;
 201        }
 202    case IGP03E1000_E_PHY_ID:
 203        hw->phy_type = e1000_phy_igp_3;
 204        break;
 205    case IFE_E_PHY_ID:
 206    case IFE_PLUS_E_PHY_ID:
 207    case IFE_C_E_PHY_ID:
 208        hw->phy_type = e1000_phy_ife;
 209        break;
 210    case GG82563_E_PHY_ID:
 211        if (hw->mac_type == e1000_80003es2lan) {
 212            hw->phy_type = e1000_phy_gg82563;
 213            break;
 214        }
 215        /* Fall Through */
 216    default:
 217        /* Should never have loaded on this device */
 218        hw->phy_type = e1000_phy_undefined;
 219        return -E1000_ERR_PHY_TYPE;
 220    }
 221
 222    return E1000_SUCCESS;
 223}
 224
 225/******************************************************************************
 226 * IGP phy init script - initializes the GbE PHY
 227 *
 228 * hw - Struct containing variables accessed by shared code
 229 *****************************************************************************/
 230static void e1000_phy_init_script(struct e1000_hw *hw)
 231{
 232    u32 ret_val;
 233    u16 phy_saved_data;
 234
 235    DEBUGFUNC("e1000_phy_init_script");
 236
 237    if (hw->phy_init_script) {
 238        msleep(20);
 239
 240        /* Save off the current value of register 0x2F5B to be restored at
 241         * the end of this routine. */
 242        ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
 243
 244        /* Disabled the PHY transmitter */
 245        e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
 246
 247        msleep(20);
 248
 249        e1000_write_phy_reg(hw,0x0000,0x0140);
 250
 251        msleep(5);
 252
 253        switch (hw->mac_type) {
 254        case e1000_82541:
 255        case e1000_82547:
 256            e1000_write_phy_reg(hw, 0x1F95, 0x0001);
 257
 258            e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
 259
 260            e1000_write_phy_reg(hw, 0x1F79, 0x0018);
 261
 262            e1000_write_phy_reg(hw, 0x1F30, 0x1600);
 263
 264            e1000_write_phy_reg(hw, 0x1F31, 0x0014);
 265
 266            e1000_write_phy_reg(hw, 0x1F32, 0x161C);
 267
 268            e1000_write_phy_reg(hw, 0x1F94, 0x0003);
 269
 270            e1000_write_phy_reg(hw, 0x1F96, 0x003F);
 271
 272            e1000_write_phy_reg(hw, 0x2010, 0x0008);
 273            break;
 274
 275        case e1000_82541_rev_2:
 276        case e1000_82547_rev_2:
 277            e1000_write_phy_reg(hw, 0x1F73, 0x0099);
 278            break;
 279        default:
 280            break;
 281        }
 282
 283        e1000_write_phy_reg(hw, 0x0000, 0x3300);
 284
 285        msleep(20);
 286
 287        /* Now enable the transmitter */
 288        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
 289
 290        if (hw->mac_type == e1000_82547) {
 291            u16 fused, fine, coarse;
 292
 293            /* Move to analog registers page */
 294            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
 295
 296            if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
 297                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
 298
 299                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
 300                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
 301
 302                if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
 303                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
 304                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
 305                } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
 306                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
 307
 308                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
 309                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
 310                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
 311
 312                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
 313                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
 314                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
 315            }
 316        }
 317    }
 318}
 319
 320/******************************************************************************
 321 * Set the mac type member in the hw struct.
 322 *
 323 * hw - Struct containing variables accessed by shared code
 324 *****************************************************************************/
 325s32 e1000_set_mac_type(struct e1000_hw *hw)
 326{
 327        DEBUGFUNC("e1000_set_mac_type");
 328
 329        switch (hw->device_id) {
 330        case E1000_DEV_ID_82542:
 331                switch (hw->revision_id) {
 332                case E1000_82542_2_0_REV_ID:
 333                        hw->mac_type = e1000_82542_rev2_0;
 334                        break;
 335                case E1000_82542_2_1_REV_ID:
 336                        hw->mac_type = e1000_82542_rev2_1;
 337                        break;
 338                default:
 339                        /* Invalid 82542 revision ID */
 340                        return -E1000_ERR_MAC_TYPE;
 341                }
 342                break;
 343        case E1000_DEV_ID_82543GC_FIBER:
 344        case E1000_DEV_ID_82543GC_COPPER:
 345                hw->mac_type = e1000_82543;
 346                break;
 347        case E1000_DEV_ID_82544EI_COPPER:
 348        case E1000_DEV_ID_82544EI_FIBER:
 349        case E1000_DEV_ID_82544GC_COPPER:
 350        case E1000_DEV_ID_82544GC_LOM:
 351                hw->mac_type = e1000_82544;
 352                break;
 353        case E1000_DEV_ID_82540EM:
 354        case E1000_DEV_ID_82540EM_LOM:
 355        case E1000_DEV_ID_82540EP:
 356        case E1000_DEV_ID_82540EP_LOM:
 357        case E1000_DEV_ID_82540EP_LP:
 358                hw->mac_type = e1000_82540;
 359                break;
 360        case E1000_DEV_ID_82545EM_COPPER:
 361        case E1000_DEV_ID_82545EM_FIBER:
 362                hw->mac_type = e1000_82545;
 363                break;
 364        case E1000_DEV_ID_82545GM_COPPER:
 365        case E1000_DEV_ID_82545GM_FIBER:
 366        case E1000_DEV_ID_82545GM_SERDES:
 367                hw->mac_type = e1000_82545_rev_3;
 368                break;
 369        case E1000_DEV_ID_82546EB_COPPER:
 370        case E1000_DEV_ID_82546EB_FIBER:
 371        case E1000_DEV_ID_82546EB_QUAD_COPPER:
 372                hw->mac_type = e1000_82546;
 373                break;
 374        case E1000_DEV_ID_82546GB_COPPER:
 375        case E1000_DEV_ID_82546GB_FIBER:
 376        case E1000_DEV_ID_82546GB_SERDES:
 377        case E1000_DEV_ID_82546GB_PCIE:
 378        case E1000_DEV_ID_82546GB_QUAD_COPPER:
 379        case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
 380                hw->mac_type = e1000_82546_rev_3;
 381                break;
 382        case E1000_DEV_ID_82541EI:
 383        case E1000_DEV_ID_82541EI_MOBILE:
 384        case E1000_DEV_ID_82541ER_LOM:
 385                hw->mac_type = e1000_82541;
 386                break;
 387        case E1000_DEV_ID_82541ER:
 388        case E1000_DEV_ID_82541GI:
 389        case E1000_DEV_ID_82541GI_LF:
 390        case E1000_DEV_ID_82541GI_MOBILE:
 391                hw->mac_type = e1000_82541_rev_2;
 392                break;
 393        case E1000_DEV_ID_82547EI:
 394        case E1000_DEV_ID_82547EI_MOBILE:
 395                hw->mac_type = e1000_82547;
 396                break;
 397        case E1000_DEV_ID_82547GI:
 398                hw->mac_type = e1000_82547_rev_2;
 399                break;
 400        case E1000_DEV_ID_82571EB_COPPER:
 401        case E1000_DEV_ID_82571EB_FIBER:
 402        case E1000_DEV_ID_82571EB_SERDES:
 403        case E1000_DEV_ID_82571EB_SERDES_DUAL:
 404        case E1000_DEV_ID_82571EB_SERDES_QUAD:
 405        case E1000_DEV_ID_82571EB_QUAD_COPPER:
 406        case E1000_DEV_ID_82571PT_QUAD_COPPER:
 407        case E1000_DEV_ID_82571EB_QUAD_FIBER:
 408        case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
 409                hw->mac_type = e1000_82571;
 410                break;
 411        case E1000_DEV_ID_82572EI_COPPER:
 412        case E1000_DEV_ID_82572EI_FIBER:
 413        case E1000_DEV_ID_82572EI_SERDES:
 414        case E1000_DEV_ID_82572EI:
 415                hw->mac_type = e1000_82572;
 416                break;
 417        case E1000_DEV_ID_82573E:
 418        case E1000_DEV_ID_82573E_IAMT:
 419        case E1000_DEV_ID_82573L:
 420                hw->mac_type = e1000_82573;
 421                break;
 422        case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
 423        case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
 424        case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
 425        case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 426                hw->mac_type = e1000_80003es2lan;
 427                break;
 428        case E1000_DEV_ID_ICH8_IGP_M_AMT:
 429        case E1000_DEV_ID_ICH8_IGP_AMT:
 430        case E1000_DEV_ID_ICH8_IGP_C:
 431        case E1000_DEV_ID_ICH8_IFE:
 432        case E1000_DEV_ID_ICH8_IFE_GT:
 433        case E1000_DEV_ID_ICH8_IFE_G:
 434        case E1000_DEV_ID_ICH8_IGP_M:
 435                hw->mac_type = e1000_ich8lan;
 436                break;
 437        default:
 438                /* Should never have loaded on this device */
 439                return -E1000_ERR_MAC_TYPE;
 440        }
 441
 442        switch (hw->mac_type) {
 443        case e1000_ich8lan:
 444                hw->swfwhw_semaphore_present = true;
 445                hw->asf_firmware_present = true;
 446                break;
 447        case e1000_80003es2lan:
 448                hw->swfw_sync_present = true;
 449                /* fall through */
 450        case e1000_82571:
 451        case e1000_82572:
 452        case e1000_82573:
 453                hw->eeprom_semaphore_present = true;
 454                /* fall through */
 455        case e1000_82541:
 456        case e1000_82547:
 457        case e1000_82541_rev_2:
 458        case e1000_82547_rev_2:
 459                hw->asf_firmware_present = true;
 460                break;
 461        default:
 462                break;
 463        }
 464
 465        /* The 82543 chip does not count tx_carrier_errors properly in
 466         * FD mode
 467         */
 468        if (hw->mac_type == e1000_82543)
 469                hw->bad_tx_carr_stats_fd = true;
 470
 471        /* capable of receiving management packets to the host */
 472        if (hw->mac_type >= e1000_82571)
 473                hw->has_manc2h = true;
 474
 475        /* In rare occasions, ESB2 systems would end up started without
 476         * the RX unit being turned on.
 477         */
 478        if (hw->mac_type == e1000_80003es2lan)
 479                hw->rx_needs_kicking = true;
 480
 481        if (hw->mac_type > e1000_82544)
 482                hw->has_smbus = true;
 483
 484        return E1000_SUCCESS;
 485}
 486
 487/*****************************************************************************
 488 * Set media type and TBI compatibility.
 489 *
 490 * hw - Struct containing variables accessed by shared code
 491 * **************************************************************************/
 492void e1000_set_media_type(struct e1000_hw *hw)
 493{
 494    u32 status;
 495
 496    DEBUGFUNC("e1000_set_media_type");
 497
 498    if (hw->mac_type != e1000_82543) {
 499        /* tbi_compatibility is only valid on 82543 */
 500        hw->tbi_compatibility_en = false;
 501    }
 502
 503    switch (hw->device_id) {
 504    case E1000_DEV_ID_82545GM_SERDES:
 505    case E1000_DEV_ID_82546GB_SERDES:
 506    case E1000_DEV_ID_82571EB_SERDES:
 507    case E1000_DEV_ID_82571EB_SERDES_DUAL:
 508    case E1000_DEV_ID_82571EB_SERDES_QUAD:
 509    case E1000_DEV_ID_82572EI_SERDES:
 510    case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 511        hw->media_type = e1000_media_type_internal_serdes;
 512        break;
 513    default:
 514        switch (hw->mac_type) {
 515        case e1000_82542_rev2_0:
 516        case e1000_82542_rev2_1:
 517            hw->media_type = e1000_media_type_fiber;
 518            break;
 519        case e1000_ich8lan:
 520        case e1000_82573:
 521            /* The STATUS_TBIMODE bit is reserved or reused for the this
 522             * device.
 523             */
 524            hw->media_type = e1000_media_type_copper;
 525            break;
 526        default:
 527            status = er32(STATUS);
 528            if (status & E1000_STATUS_TBIMODE) {
 529                hw->media_type = e1000_media_type_fiber;
 530                /* tbi_compatibility not valid on fiber */
 531                hw->tbi_compatibility_en = false;
 532            } else {
 533                hw->media_type = e1000_media_type_copper;
 534            }
 535            break;
 536        }
 537    }
 538}
 539
 540/******************************************************************************
 541 * Reset the transmit and receive units; mask and clear all interrupts.
 542 *
 543 * hw - Struct containing variables accessed by shared code
 544 *****************************************************************************/
 545s32 e1000_reset_hw(struct e1000_hw *hw)
 546{
 547    u32 ctrl;
 548    u32 ctrl_ext;
 549    u32 icr;
 550    u32 manc;
 551    u32 led_ctrl;
 552    u32 timeout;
 553    u32 extcnf_ctrl;
 554    s32 ret_val;
 555
 556    DEBUGFUNC("e1000_reset_hw");
 557
 558    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
 559    if (hw->mac_type == e1000_82542_rev2_0) {
 560        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 561        e1000_pci_clear_mwi(hw);
 562    }
 563
 564    if (hw->bus_type == e1000_bus_type_pci_express) {
 565        /* Prevent the PCI-E bus from sticking if there is no TLP connection
 566         * on the last TLP read/write transaction when MAC is reset.
 567         */
 568        if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
 569            DEBUGOUT("PCI-E Master disable polling has failed.\n");
 570        }
 571    }
 572
 573    /* Clear interrupt mask to stop board from generating interrupts */
 574    DEBUGOUT("Masking off all interrupts\n");
 575    ew32(IMC, 0xffffffff);
 576
 577    /* Disable the Transmit and Receive units.  Then delay to allow
 578     * any pending transactions to complete before we hit the MAC with
 579     * the global reset.
 580     */
 581    ew32(RCTL, 0);
 582    ew32(TCTL, E1000_TCTL_PSP);
 583    E1000_WRITE_FLUSH();
 584
 585    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
 586    hw->tbi_compatibility_on = false;
 587
 588    /* Delay to allow any outstanding PCI transactions to complete before
 589     * resetting the device
 590     */
 591    msleep(10);
 592
 593    ctrl = er32(CTRL);
 594
 595    /* Must reset the PHY before resetting the MAC */
 596    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
 597        ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
 598        msleep(5);
 599    }
 600
 601    /* Must acquire the MDIO ownership before MAC reset.
 602     * Ownership defaults to firmware after a reset. */
 603    if (hw->mac_type == e1000_82573) {
 604        timeout = 10;
 605
 606        extcnf_ctrl = er32(EXTCNF_CTRL);
 607        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 608
 609        do {
 610            ew32(EXTCNF_CTRL, extcnf_ctrl);
 611            extcnf_ctrl = er32(EXTCNF_CTRL);
 612
 613            if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 614                break;
 615            else
 616                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 617
 618            msleep(2);
 619            timeout--;
 620        } while (timeout);
 621    }
 622
 623    /* Workaround for ICH8 bit corruption issue in FIFO memory */
 624    if (hw->mac_type == e1000_ich8lan) {
 625        /* Set Tx and Rx buffer allocation to 8k apiece. */
 626        ew32(PBA, E1000_PBA_8K);
 627        /* Set Packet Buffer Size to 16k. */
 628        ew32(PBS, E1000_PBS_16K);
 629    }
 630
 631    /* Issue a global reset to the MAC.  This will reset the chip's
 632     * transmit, receive, DMA, and link units.  It will not effect
 633     * the current PCI configuration.  The global reset bit is self-
 634     * clearing, and should clear within a microsecond.
 635     */
 636    DEBUGOUT("Issuing a global reset to MAC\n");
 637
 638    switch (hw->mac_type) {
 639        case e1000_82544:
 640        case e1000_82540:
 641        case e1000_82545:
 642        case e1000_82546:
 643        case e1000_82541:
 644        case e1000_82541_rev_2:
 645            /* These controllers can't ack the 64-bit write when issuing the
 646             * reset, so use IO-mapping as a workaround to issue the reset */
 647            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
 648            break;
 649        case e1000_82545_rev_3:
 650        case e1000_82546_rev_3:
 651            /* Reset is performed on a shadow of the control register */
 652            ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
 653            break;
 654        case e1000_ich8lan:
 655            if (!hw->phy_reset_disable &&
 656                e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
 657                /* e1000_ich8lan PHY HW reset requires MAC CORE reset
 658                 * at the same time to make sure the interface between
 659                 * MAC and the external PHY is reset.
 660                 */
 661                ctrl |= E1000_CTRL_PHY_RST;
 662            }
 663
 664            e1000_get_software_flag(hw);
 665            ew32(CTRL, (ctrl | E1000_CTRL_RST));
 666            msleep(5);
 667            break;
 668        default:
 669            ew32(CTRL, (ctrl | E1000_CTRL_RST));
 670            break;
 671    }
 672
 673    /* After MAC reset, force reload of EEPROM to restore power-on settings to
 674     * device.  Later controllers reload the EEPROM automatically, so just wait
 675     * for reload to complete.
 676     */
 677    switch (hw->mac_type) {
 678        case e1000_82542_rev2_0:
 679        case e1000_82542_rev2_1:
 680        case e1000_82543:
 681        case e1000_82544:
 682            /* Wait for reset to complete */
 683            udelay(10);
 684            ctrl_ext = er32(CTRL_EXT);
 685            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 686            ew32(CTRL_EXT, ctrl_ext);
 687            E1000_WRITE_FLUSH();
 688            /* Wait for EEPROM reload */
 689            msleep(2);
 690            break;
 691        case e1000_82541:
 692        case e1000_82541_rev_2:
 693        case e1000_82547:
 694        case e1000_82547_rev_2:
 695            /* Wait for EEPROM reload */
 696            msleep(20);
 697            break;
 698        case e1000_82573:
 699            if (!e1000_is_onboard_nvm_eeprom(hw)) {
 700                udelay(10);
 701                ctrl_ext = er32(CTRL_EXT);
 702                ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 703                ew32(CTRL_EXT, ctrl_ext);
 704                E1000_WRITE_FLUSH();
 705            }
 706            /* fall through */
 707        default:
 708            /* Auto read done will delay 5ms or poll based on mac type */
 709            ret_val = e1000_get_auto_rd_done(hw);
 710            if (ret_val)
 711                return ret_val;
 712            break;
 713    }
 714
 715    /* Disable HW ARPs on ASF enabled adapters */
 716    if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
 717        manc = er32(MANC);
 718        manc &= ~(E1000_MANC_ARP_EN);
 719        ew32(MANC, manc);
 720    }
 721
 722    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
 723        e1000_phy_init_script(hw);
 724
 725        /* Configure activity LED after PHY reset */
 726        led_ctrl = er32(LEDCTL);
 727        led_ctrl &= IGP_ACTIVITY_LED_MASK;
 728        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 729        ew32(LEDCTL, led_ctrl);
 730    }
 731
 732    /* Clear interrupt mask to stop board from generating interrupts */
 733    DEBUGOUT("Masking off all interrupts\n");
 734    ew32(IMC, 0xffffffff);
 735
 736    /* Clear any pending interrupt events. */
 737    icr = er32(ICR);
 738
 739    /* If MWI was previously enabled, reenable it. */
 740    if (hw->mac_type == e1000_82542_rev2_0) {
 741        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
 742            e1000_pci_set_mwi(hw);
 743    }
 744
 745    if (hw->mac_type == e1000_ich8lan) {
 746        u32 kab = er32(KABGTXD);
 747        kab |= E1000_KABGTXD_BGSQLBIAS;
 748        ew32(KABGTXD, kab);
 749    }
 750
 751    return E1000_SUCCESS;
 752}
 753
 754/******************************************************************************
 755 *
 756 * Initialize a number of hardware-dependent bits
 757 *
 758 * hw: Struct containing variables accessed by shared code
 759 *
 760 * This function contains hardware limitation workarounds for PCI-E adapters
 761 *
 762 *****************************************************************************/
 763static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
 764{
 765    if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
 766        /* Settings common to all PCI-express silicon */
 767        u32 reg_ctrl, reg_ctrl_ext;
 768        u32 reg_tarc0, reg_tarc1;
 769        u32 reg_tctl;
 770        u32 reg_txdctl, reg_txdctl1;
 771
 772        /* link autonegotiation/sync workarounds */
 773        reg_tarc0 = er32(TARC0);
 774        reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
 775
 776        /* Enable not-done TX descriptor counting */
 777        reg_txdctl = er32(TXDCTL);
 778        reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
 779        ew32(TXDCTL, reg_txdctl);
 780        reg_txdctl1 = er32(TXDCTL1);
 781        reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
 782        ew32(TXDCTL1, reg_txdctl1);
 783
 784        switch (hw->mac_type) {
 785            case e1000_82571:
 786            case e1000_82572:
 787                /* Clear PHY TX compatible mode bits */
 788                reg_tarc1 = er32(TARC1);
 789                reg_tarc1 &= ~((1 << 30)|(1 << 29));
 790
 791                /* link autonegotiation/sync workarounds */
 792                reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
 793
 794                /* TX ring control fixes */
 795                reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
 796
 797                /* Multiple read bit is reversed polarity */
 798                reg_tctl = er32(TCTL);
 799                if (reg_tctl & E1000_TCTL_MULR)
 800                    reg_tarc1 &= ~(1 << 28);
 801                else
 802                    reg_tarc1 |= (1 << 28);
 803
 804                ew32(TARC1, reg_tarc1);
 805                break;
 806            case e1000_82573:
 807                reg_ctrl_ext = er32(CTRL_EXT);
 808                reg_ctrl_ext &= ~(1 << 23);
 809                reg_ctrl_ext |= (1 << 22);
 810
 811                /* TX byte count fix */
 812                reg_ctrl = er32(CTRL);
 813                reg_ctrl &= ~(1 << 29);
 814
 815                ew32(CTRL_EXT, reg_ctrl_ext);
 816                ew32(CTRL, reg_ctrl);
 817                break;
 818            case e1000_80003es2lan:
 819                /* improve small packet performace for fiber/serdes */
 820                if ((hw->media_type == e1000_media_type_fiber) ||
 821                    (hw->media_type == e1000_media_type_internal_serdes)) {
 822                    reg_tarc0 &= ~(1 << 20);
 823                }
 824
 825                /* Multiple read bit is reversed polarity */
 826                reg_tctl = er32(TCTL);
 827                reg_tarc1 = er32(TARC1);
 828                if (reg_tctl & E1000_TCTL_MULR)
 829                    reg_tarc1 &= ~(1 << 28);
 830                else
 831                    reg_tarc1 |= (1 << 28);
 832
 833                ew32(TARC1, reg_tarc1);
 834                break;
 835            case e1000_ich8lan:
 836                /* Reduce concurrent DMA requests to 3 from 4 */
 837                if ((hw->revision_id < 3) ||
 838                    ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
 839                     (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
 840                    reg_tarc0 |= ((1 << 29)|(1 << 28));
 841
 842                reg_ctrl_ext = er32(CTRL_EXT);
 843                reg_ctrl_ext |= (1 << 22);
 844                ew32(CTRL_EXT, reg_ctrl_ext);
 845
 846                /* workaround TX hang with TSO=on */
 847                reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
 848
 849                /* Multiple read bit is reversed polarity */
 850                reg_tctl = er32(TCTL);
 851                reg_tarc1 = er32(TARC1);
 852                if (reg_tctl & E1000_TCTL_MULR)
 853                    reg_tarc1 &= ~(1 << 28);
 854                else
 855                    reg_tarc1 |= (1 << 28);
 856
 857                /* workaround TX hang with TSO=on */
 858                reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
 859
 860                ew32(TARC1, reg_tarc1);
 861                break;
 862            default:
 863                break;
 864        }
 865
 866        ew32(TARC0, reg_tarc0);
 867    }
 868}
 869
 870/******************************************************************************
 871 * Performs basic configuration of the adapter.
 872 *
 873 * hw - Struct containing variables accessed by shared code
 874 *
 875 * Assumes that the controller has previously been reset and is in a
 876 * post-reset uninitialized state. Initializes the receive address registers,
 877 * multicast table, and VLAN filter table. Calls routines to setup link
 878 * configuration and flow control settings. Clears all on-chip counters. Leaves
 879 * the transmit and receive units disabled and uninitialized.
 880 *****************************************************************************/
 881s32 e1000_init_hw(struct e1000_hw *hw)
 882{
 883    u32 ctrl;
 884    u32 i;
 885    s32 ret_val;
 886    u32 mta_size;
 887    u32 reg_data;
 888    u32 ctrl_ext;
 889
 890    DEBUGFUNC("e1000_init_hw");
 891
 892    /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
 893    if ((hw->mac_type == e1000_ich8lan) &&
 894        ((hw->revision_id < 3) ||
 895         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
 896          (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
 897            reg_data = er32(STATUS);
 898            reg_data &= ~0x80000000;
 899            ew32(STATUS, reg_data);
 900    }
 901
 902    /* Initialize Identification LED */
 903    ret_val = e1000_id_led_init(hw);
 904    if (ret_val) {
 905        DEBUGOUT("Error Initializing Identification LED\n");
 906        return ret_val;
 907    }
 908
 909    /* Set the media type and TBI compatibility */
 910    e1000_set_media_type(hw);
 911
 912    /* Must be called after e1000_set_media_type because media_type is used */
 913    e1000_initialize_hardware_bits(hw);
 914
 915    /* Disabling VLAN filtering. */
 916    DEBUGOUT("Initializing the IEEE VLAN\n");
 917    /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
 918    if (hw->mac_type != e1000_ich8lan) {
 919        if (hw->mac_type < e1000_82545_rev_3)
 920            ew32(VET, 0);
 921        e1000_clear_vfta(hw);
 922    }
 923
 924    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
 925    if (hw->mac_type == e1000_82542_rev2_0) {
 926        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 927        e1000_pci_clear_mwi(hw);
 928        ew32(RCTL, E1000_RCTL_RST);
 929        E1000_WRITE_FLUSH();
 930        msleep(5);
 931    }
 932
 933    /* Setup the receive address. This involves initializing all of the Receive
 934     * Address Registers (RARs 0 - 15).
 935     */
 936    e1000_init_rx_addrs(hw);
 937
 938    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
 939    if (hw->mac_type == e1000_82542_rev2_0) {
 940        ew32(RCTL, 0);
 941        E1000_WRITE_FLUSH();
 942        msleep(1);
 943        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
 944            e1000_pci_set_mwi(hw);
 945    }
 946
 947    /* Zero out the Multicast HASH table */
 948    DEBUGOUT("Zeroing the MTA\n");
 949    mta_size = E1000_MC_TBL_SIZE;
 950    if (hw->mac_type == e1000_ich8lan)
 951        mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
 952    for (i = 0; i < mta_size; i++) {
 953        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
 954        /* use write flush to prevent Memory Write Block (MWB) from
 955         * occuring when accessing our register space */
 956        E1000_WRITE_FLUSH();
 957    }
 958
 959    /* Set the PCI priority bit correctly in the CTRL register.  This
 960     * determines if the adapter gives priority to receives, or if it
 961     * gives equal priority to transmits and receives.  Valid only on
 962     * 82542 and 82543 silicon.
 963     */
 964    if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
 965        ctrl = er32(CTRL);
 966        ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
 967    }
 968
 969    switch (hw->mac_type) {
 970    case e1000_82545_rev_3:
 971    case e1000_82546_rev_3:
 972        break;
 973    default:
 974        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
 975        if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
 976                e1000_pcix_set_mmrbc(hw, 2048);
 977        break;
 978    }
 979
 980    /* More time needed for PHY to initialize */
 981    if (hw->mac_type == e1000_ich8lan)
 982        msleep(15);
 983
 984    /* Call a subroutine to configure the link and setup flow control. */
 985    ret_val = e1000_setup_link(hw);
 986
 987    /* Set the transmit descriptor write-back policy */
 988    if (hw->mac_type > e1000_82544) {
 989        ctrl = er32(TXDCTL);
 990        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
 991        ew32(TXDCTL, ctrl);
 992    }
 993
 994    if (hw->mac_type == e1000_82573) {
 995        e1000_enable_tx_pkt_filtering(hw);
 996    }
 997
 998    switch (hw->mac_type) {
 999    default:
1000        break;
1001    case e1000_80003es2lan:
1002        /* Enable retransmit on late collisions */
1003        reg_data = er32(TCTL);
1004        reg_data |= E1000_TCTL_RTLC;
1005        ew32(TCTL, reg_data);
1006
1007        /* Configure Gigabit Carry Extend Padding */
1008        reg_data = er32(TCTL_EXT);
1009        reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1010        reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1011        ew32(TCTL_EXT, reg_data);
1012
1013        /* Configure Transmit Inter-Packet Gap */
1014        reg_data = er32(TIPG);
1015        reg_data &= ~E1000_TIPG_IPGT_MASK;
1016        reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1017        ew32(TIPG, reg_data);
1018
1019        reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1020        reg_data &= ~0x00100000;
1021        E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1022        /* Fall through */
1023    case e1000_82571:
1024    case e1000_82572:
1025    case e1000_ich8lan:
1026        ctrl = er32(TXDCTL1);
1027        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1028        ew32(TXDCTL1, ctrl);
1029        break;
1030    }
1031
1032
1033    if (hw->mac_type == e1000_82573) {
1034        u32 gcr = er32(GCR);
1035        gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1036        ew32(GCR, gcr);
1037    }
1038
1039    /* Clear all of the statistics registers (clear on read).  It is
1040     * important that we do this after we have tried to establish link
1041     * because the symbol error count will increment wildly if there
1042     * is no link.
1043     */
1044    e1000_clear_hw_cntrs(hw);
1045
1046    /* ICH8 No-snoop bits are opposite polarity.
1047     * Set to snoop by default after reset. */
1048    if (hw->mac_type == e1000_ich8lan)
1049        e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1050
1051    if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1052        hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1053        ctrl_ext = er32(CTRL_EXT);
1054        /* Relaxed ordering must be disabled to avoid a parity
1055         * error crash in a PCI slot. */
1056        ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1057        ew32(CTRL_EXT, ctrl_ext);
1058    }
1059
1060    return ret_val;
1061}
1062
1063/******************************************************************************
1064 * Adjust SERDES output amplitude based on EEPROM setting.
1065 *
1066 * hw - Struct containing variables accessed by shared code.
1067 *****************************************************************************/
1068static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1069{
1070    u16 eeprom_data;
1071    s32  ret_val;
1072
1073    DEBUGFUNC("e1000_adjust_serdes_amplitude");
1074
1075    if (hw->media_type != e1000_media_type_internal_serdes)
1076        return E1000_SUCCESS;
1077
1078    switch (hw->mac_type) {
1079    case e1000_82545_rev_3:
1080    case e1000_82546_rev_3:
1081        break;
1082    default:
1083        return E1000_SUCCESS;
1084    }
1085
1086    ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1087    if (ret_val) {
1088        return ret_val;
1089    }
1090
1091    if (eeprom_data != EEPROM_RESERVED_WORD) {
1092        /* Adjust SERDES output amplitude only. */
1093        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1094        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1095        if (ret_val)
1096            return ret_val;
1097    }
1098
1099    return E1000_SUCCESS;
1100}
1101
1102/******************************************************************************
1103 * Configures flow control and link settings.
1104 *
1105 * hw - Struct containing variables accessed by shared code
1106 *
1107 * Determines which flow control settings to use. Calls the apropriate media-
1108 * specific link configuration function. Configures the flow control settings.
1109 * Assuming the adapter has a valid link partner, a valid link should be
1110 * established. Assumes the hardware has previously been reset and the
1111 * transmitter and receiver are not enabled.
1112 *****************************************************************************/
1113s32 e1000_setup_link(struct e1000_hw *hw)
1114{
1115    u32 ctrl_ext;
1116    s32 ret_val;
1117    u16 eeprom_data;
1118
1119    DEBUGFUNC("e1000_setup_link");
1120
1121    /* In the case of the phy reset being blocked, we already have a link.
1122     * We do not have to set it up again. */
1123    if (e1000_check_phy_reset_block(hw))
1124        return E1000_SUCCESS;
1125
1126    /* Read and store word 0x0F of the EEPROM. This word contains bits
1127     * that determine the hardware's default PAUSE (flow control) mode,
1128     * a bit that determines whether the HW defaults to enabling or
1129     * disabling auto-negotiation, and the direction of the
1130     * SW defined pins. If there is no SW over-ride of the flow
1131     * control setting, then the variable hw->fc will
1132     * be initialized based on a value in the EEPROM.
1133     */
1134    if (hw->fc == E1000_FC_DEFAULT) {
1135        switch (hw->mac_type) {
1136        case e1000_ich8lan:
1137        case e1000_82573:
1138            hw->fc = E1000_FC_FULL;
1139            break;
1140        default:
1141            ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1142                                        1, &eeprom_data);
1143            if (ret_val) {
1144                DEBUGOUT("EEPROM Read Error\n");
1145                return -E1000_ERR_EEPROM;
1146            }
1147            if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1148                hw->fc = E1000_FC_NONE;
1149            else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1150                    EEPROM_WORD0F_ASM_DIR)
1151                hw->fc = E1000_FC_TX_PAUSE;
1152            else
1153                hw->fc = E1000_FC_FULL;
1154            break;
1155        }
1156    }
1157
1158    /* We want to save off the original Flow Control configuration just
1159     * in case we get disconnected and then reconnected into a different
1160     * hub or switch with different Flow Control capabilities.
1161     */
1162    if (hw->mac_type == e1000_82542_rev2_0)
1163        hw->fc &= (~E1000_FC_TX_PAUSE);
1164
1165    if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1166        hw->fc &= (~E1000_FC_RX_PAUSE);
1167
1168    hw->original_fc = hw->fc;
1169
1170    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1171
1172    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1173     * polarity value for the SW controlled pins, and setup the
1174     * Extended Device Control reg with that info.
1175     * This is needed because one of the SW controlled pins is used for
1176     * signal detection.  So this should be done before e1000_setup_pcs_link()
1177     * or e1000_phy_setup() is called.
1178     */
1179    if (hw->mac_type == e1000_82543) {
1180        ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1181                                    1, &eeprom_data);
1182        if (ret_val) {
1183            DEBUGOUT("EEPROM Read Error\n");
1184            return -E1000_ERR_EEPROM;
1185        }
1186        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1187                    SWDPIO__EXT_SHIFT);
1188        ew32(CTRL_EXT, ctrl_ext);
1189    }
1190
1191    /* Call the necessary subroutine to configure the link. */
1192    ret_val = (hw->media_type == e1000_media_type_copper) ?
1193              e1000_setup_copper_link(hw) :
1194              e1000_setup_fiber_serdes_link(hw);
1195
1196    /* Initialize the flow control address, type, and PAUSE timer
1197     * registers to their default values.  This is done even if flow
1198     * control is disabled, because it does not hurt anything to
1199     * initialize these registers.
1200     */
1201    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1202
1203    /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1204    if (hw->mac_type != e1000_ich8lan) {
1205        ew32(FCT, FLOW_CONTROL_TYPE);
1206        ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1207        ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1208    }
1209
1210    ew32(FCTTV, hw->fc_pause_time);
1211
1212    /* Set the flow control receive threshold registers.  Normally,
1213     * these registers will be set to a default threshold that may be
1214     * adjusted later by the driver's runtime code.  However, if the
1215     * ability to transmit pause frames in not enabled, then these
1216     * registers will be set to 0.
1217     */
1218    if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1219        ew32(FCRTL, 0);
1220        ew32(FCRTH, 0);
1221    } else {
1222        /* We need to set up the Receive Threshold high and low water marks
1223         * as well as (optionally) enabling the transmission of XON frames.
1224         */
1225        if (hw->fc_send_xon) {
1226            ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1227            ew32(FCRTH, hw->fc_high_water);
1228        } else {
1229            ew32(FCRTL, hw->fc_low_water);
1230            ew32(FCRTH, hw->fc_high_water);
1231        }
1232    }
1233    return ret_val;
1234}
1235
1236/******************************************************************************
1237 * Sets up link for a fiber based or serdes based adapter
1238 *
1239 * hw - Struct containing variables accessed by shared code
1240 *
1241 * Manipulates Physical Coding Sublayer functions in order to configure
1242 * link. Assumes the hardware has been previously reset and the transmitter
1243 * and receiver are not enabled.
1244 *****************************************************************************/
1245static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1246{
1247    u32 ctrl;
1248    u32 status;
1249    u32 txcw = 0;
1250    u32 i;
1251    u32 signal = 0;
1252    s32 ret_val;
1253
1254    DEBUGFUNC("e1000_setup_fiber_serdes_link");
1255
1256    /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1257     * until explicitly turned off or a power cycle is performed.  A read to
1258     * the register does not indicate its status.  Therefore, we ensure
1259     * loopback mode is disabled during initialization.
1260     */
1261    if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1262        ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1263
1264    /* On adapters with a MAC newer than 82544, SWDP 1 will be
1265     * set when the optics detect a signal. On older adapters, it will be
1266     * cleared when there is a signal.  This applies to fiber media only.
1267     * If we're on serdes media, adjust the output amplitude to value
1268     * set in the EEPROM.
1269     */
1270    ctrl = er32(CTRL);
1271    if (hw->media_type == e1000_media_type_fiber)
1272        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1273
1274    ret_val = e1000_adjust_serdes_amplitude(hw);
1275    if (ret_val)
1276        return ret_val;
1277
1278    /* Take the link out of reset */
1279    ctrl &= ~(E1000_CTRL_LRST);
1280
1281    /* Adjust VCO speed to improve BER performance */
1282    ret_val = e1000_set_vco_speed(hw);
1283    if (ret_val)
1284        return ret_val;
1285
1286    e1000_config_collision_dist(hw);
1287
1288    /* Check for a software override of the flow control settings, and setup
1289     * the device accordingly.  If auto-negotiation is enabled, then software
1290     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1291     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1292     * auto-negotiation is disabled, then software will have to manually
1293     * configure the two flow control enable bits in the CTRL register.
1294     *
1295     * The possible values of the "fc" parameter are:
1296     *      0:  Flow control is completely disabled
1297     *      1:  Rx flow control is enabled (we can receive pause frames, but
1298     *          not send pause frames).
1299     *      2:  Tx flow control is enabled (we can send pause frames but we do
1300     *          not support receiving pause frames).
1301     *      3:  Both Rx and TX flow control (symmetric) are enabled.
1302     */
1303    switch (hw->fc) {
1304    case E1000_FC_NONE:
1305        /* Flow control is completely disabled by a software over-ride. */
1306        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1307        break;
1308    case E1000_FC_RX_PAUSE:
1309        /* RX Flow control is enabled and TX Flow control is disabled by a
1310         * software over-ride. Since there really isn't a way to advertise
1311         * that we are capable of RX Pause ONLY, we will advertise that we
1312         * support both symmetric and asymmetric RX PAUSE. Later, we will
1313         *  disable the adapter's ability to send PAUSE frames.
1314         */
1315        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1316        break;
1317    case E1000_FC_TX_PAUSE:
1318        /* TX Flow control is enabled, and RX Flow control is disabled, by a
1319         * software over-ride.
1320         */
1321        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1322        break;
1323    case E1000_FC_FULL:
1324        /* Flow control (both RX and TX) is enabled by a software over-ride. */
1325        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1326        break;
1327    default:
1328        DEBUGOUT("Flow control param set incorrectly\n");
1329        return -E1000_ERR_CONFIG;
1330        break;
1331    }
1332
1333    /* Since auto-negotiation is enabled, take the link out of reset (the link
1334     * will be in reset, because we previously reset the chip). This will
1335     * restart auto-negotiation.  If auto-neogtiation is successful then the
1336     * link-up status bit will be set and the flow control enable bits (RFCE
1337     * and TFCE) will be set according to their negotiated value.
1338     */
1339    DEBUGOUT("Auto-negotiation enabled\n");
1340
1341    ew32(TXCW, txcw);
1342    ew32(CTRL, ctrl);
1343    E1000_WRITE_FLUSH();
1344
1345    hw->txcw = txcw;
1346    msleep(1);
1347
1348    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1349     * indication in the Device Status Register.  Time-out if a link isn't
1350     * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1351     * less than 500 milliseconds even if the other end is doing it in SW).
1352     * For internal serdes, we just assume a signal is present, then poll.
1353     */
1354    if (hw->media_type == e1000_media_type_internal_serdes ||
1355       (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1356        DEBUGOUT("Looking for Link\n");
1357        for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1358            msleep(10);
1359            status = er32(STATUS);
1360            if (status & E1000_STATUS_LU) break;
1361        }
1362        if (i == (LINK_UP_TIMEOUT / 10)) {
1363            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1364            hw->autoneg_failed = 1;
1365            /* AutoNeg failed to achieve a link, so we'll call
1366             * e1000_check_for_link. This routine will force the link up if
1367             * we detect a signal. This will allow us to communicate with
1368             * non-autonegotiating link partners.
1369             */
1370            ret_val = e1000_check_for_link(hw);
1371            if (ret_val) {
1372                DEBUGOUT("Error while checking for link\n");
1373                return ret_val;
1374            }
1375            hw->autoneg_failed = 0;
1376        } else {
1377            hw->autoneg_failed = 0;
1378            DEBUGOUT("Valid Link Found\n");
1379        }
1380    } else {
1381        DEBUGOUT("No Signal Detected\n");
1382    }
1383    return E1000_SUCCESS;
1384}
1385
1386/******************************************************************************
1387* Make sure we have a valid PHY and change PHY mode before link setup.
1388*
1389* hw - Struct containing variables accessed by shared code
1390******************************************************************************/
1391static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1392{
1393    u32 ctrl;
1394    s32 ret_val;
1395    u16 phy_data;
1396
1397    DEBUGFUNC("e1000_copper_link_preconfig");
1398
1399    ctrl = er32(CTRL);
1400    /* With 82543, we need to force speed and duplex on the MAC equal to what
1401     * the PHY speed and duplex configuration is. In addition, we need to
1402     * perform a hardware reset on the PHY to take it out of reset.
1403     */
1404    if (hw->mac_type > e1000_82543) {
1405        ctrl |= E1000_CTRL_SLU;
1406        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1407        ew32(CTRL, ctrl);
1408    } else {
1409        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1410        ew32(CTRL, ctrl);
1411        ret_val = e1000_phy_hw_reset(hw);
1412        if (ret_val)
1413            return ret_val;
1414    }
1415
1416    /* Make sure we have a valid PHY */
1417    ret_val = e1000_detect_gig_phy(hw);
1418    if (ret_val) {
1419        DEBUGOUT("Error, did not detect valid phy.\n");
1420        return ret_val;
1421    }
1422    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1423
1424    /* Set PHY to class A mode (if necessary) */
1425    ret_val = e1000_set_phy_mode(hw);
1426    if (ret_val)
1427        return ret_val;
1428
1429    if ((hw->mac_type == e1000_82545_rev_3) ||
1430       (hw->mac_type == e1000_82546_rev_3)) {
1431        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1432        phy_data |= 0x00000008;
1433        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1434    }
1435
1436    if (hw->mac_type <= e1000_82543 ||
1437        hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1438        hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1439        hw->phy_reset_disable = false;
1440
1441   return E1000_SUCCESS;
1442}
1443
1444
1445/********************************************************************
1446* Copper link setup for e1000_phy_igp series.
1447*
1448* hw - Struct containing variables accessed by shared code
1449*********************************************************************/
1450static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1451{
1452    u32 led_ctrl;
1453    s32 ret_val;
1454    u16 phy_data;
1455
1456    DEBUGFUNC("e1000_copper_link_igp_setup");
1457
1458    if (hw->phy_reset_disable)
1459        return E1000_SUCCESS;
1460
1461    ret_val = e1000_phy_reset(hw);
1462    if (ret_val) {
1463        DEBUGOUT("Error Resetting the PHY\n");
1464        return ret_val;
1465    }
1466
1467    /* Wait 15ms for MAC to configure PHY from eeprom settings */
1468    msleep(15);
1469    if (hw->mac_type != e1000_ich8lan) {
1470    /* Configure activity LED after PHY reset */
1471    led_ctrl = er32(LEDCTL);
1472    led_ctrl &= IGP_ACTIVITY_LED_MASK;
1473    led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1474    ew32(LEDCTL, led_ctrl);
1475    }
1476
1477    /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1478    if (hw->phy_type == e1000_phy_igp) {
1479        /* disable lplu d3 during driver init */
1480        ret_val = e1000_set_d3_lplu_state(hw, false);
1481        if (ret_val) {
1482            DEBUGOUT("Error Disabling LPLU D3\n");
1483            return ret_val;
1484        }
1485    }
1486
1487    /* disable lplu d0 during driver init */
1488    ret_val = e1000_set_d0_lplu_state(hw, false);
1489    if (ret_val) {
1490        DEBUGOUT("Error Disabling LPLU D0\n");
1491        return ret_val;
1492    }
1493    /* Configure mdi-mdix settings */
1494    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1495    if (ret_val)
1496        return ret_val;
1497
1498    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1499        hw->dsp_config_state = e1000_dsp_config_disabled;
1500        /* Force MDI for earlier revs of the IGP PHY */
1501        phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1502        hw->mdix = 1;
1503
1504    } else {
1505        hw->dsp_config_state = e1000_dsp_config_enabled;
1506        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1507
1508        switch (hw->mdix) {
1509        case 1:
1510            phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1511            break;
1512        case 2:
1513            phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1514            break;
1515        case 0:
1516        default:
1517            phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1518            break;
1519        }
1520    }
1521    ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1522    if (ret_val)
1523        return ret_val;
1524
1525    /* set auto-master slave resolution settings */
1526    if (hw->autoneg) {
1527        e1000_ms_type phy_ms_setting = hw->master_slave;
1528
1529        if (hw->ffe_config_state == e1000_ffe_config_active)
1530            hw->ffe_config_state = e1000_ffe_config_enabled;
1531
1532        if (hw->dsp_config_state == e1000_dsp_config_activated)
1533            hw->dsp_config_state = e1000_dsp_config_enabled;
1534
1535        /* when autonegotiation advertisment is only 1000Mbps then we
1536          * should disable SmartSpeed and enable Auto MasterSlave
1537          * resolution as hardware default. */
1538        if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1539            /* Disable SmartSpeed */
1540            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1541                                         &phy_data);
1542            if (ret_val)
1543                return ret_val;
1544            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1545            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1546                                          phy_data);
1547            if (ret_val)
1548                return ret_val;
1549            /* Set auto Master/Slave resolution process */
1550            ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1551            if (ret_val)
1552                return ret_val;
1553            phy_data &= ~CR_1000T_MS_ENABLE;
1554            ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1555            if (ret_val)
1556                return ret_val;
1557        }
1558
1559        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1560        if (ret_val)
1561            return ret_val;
1562
1563        /* load defaults for future use */
1564        hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1565                                        ((phy_data & CR_1000T_MS_VALUE) ?
1566                                         e1000_ms_force_master :
1567                                         e1000_ms_force_slave) :
1568                                         e1000_ms_auto;
1569
1570        switch (phy_ms_setting) {
1571        case e1000_ms_force_master:
1572            phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1573            break;
1574        case e1000_ms_force_slave:
1575            phy_data |= CR_1000T_MS_ENABLE;
1576            phy_data &= ~(CR_1000T_MS_VALUE);
1577            break;
1578        case e1000_ms_auto:
1579            phy_data &= ~CR_1000T_MS_ENABLE;
1580            default:
1581            break;
1582        }
1583        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1584        if (ret_val)
1585            return ret_val;
1586    }
1587
1588    return E1000_SUCCESS;
1589}
1590
1591/********************************************************************
1592* Copper link setup for e1000_phy_gg82563 series.
1593*
1594* hw - Struct containing variables accessed by shared code
1595*********************************************************************/
1596static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1597{
1598    s32 ret_val;
1599    u16 phy_data;
1600    u32 reg_data;
1601
1602    DEBUGFUNC("e1000_copper_link_ggp_setup");
1603
1604    if (!hw->phy_reset_disable) {
1605
1606        /* Enable CRS on TX for half-duplex operation. */
1607        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1608                                     &phy_data);
1609        if (ret_val)
1610            return ret_val;
1611
1612        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1613        /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1614        phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1615
1616        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1617                                      phy_data);
1618        if (ret_val)
1619            return ret_val;
1620
1621        /* Options:
1622         *   MDI/MDI-X = 0 (default)
1623         *   0 - Auto for all speeds
1624         *   1 - MDI mode
1625         *   2 - MDI-X mode
1626         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1627         */
1628        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1629        if (ret_val)
1630            return ret_val;
1631
1632        phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1633
1634        switch (hw->mdix) {
1635        case 1:
1636            phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1637            break;
1638        case 2:
1639            phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1640            break;
1641        case 0:
1642        default:
1643            phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1644            break;
1645        }
1646
1647        /* Options:
1648         *   disable_polarity_correction = 0 (default)
1649         *       Automatic Correction for Reversed Cable Polarity
1650         *   0 - Disabled
1651         *   1 - Enabled
1652         */
1653        phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1654        if (hw->disable_polarity_correction == 1)
1655            phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1656        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1657
1658        if (ret_val)
1659            return ret_val;
1660
1661        /* SW Reset the PHY so all changes take effect */
1662        ret_val = e1000_phy_reset(hw);
1663        if (ret_val) {
1664            DEBUGOUT("Error Resetting the PHY\n");
1665            return ret_val;
1666        }
1667    } /* phy_reset_disable */
1668
1669    if (hw->mac_type == e1000_80003es2lan) {
1670        /* Bypass RX and TX FIFO's */
1671        ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1672                                       E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1673                                       E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1674        if (ret_val)
1675            return ret_val;
1676
1677        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1678        if (ret_val)
1679            return ret_val;
1680
1681        phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1682        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1683
1684        if (ret_val)
1685            return ret_val;
1686
1687        reg_data = er32(CTRL_EXT);
1688        reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1689        ew32(CTRL_EXT, reg_data);
1690
1691        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1692                                          &phy_data);
1693        if (ret_val)
1694            return ret_val;
1695
1696        /* Do not init these registers when the HW is in IAMT mode, since the
1697         * firmware will have already initialized them.  We only initialize
1698         * them if the HW is not in IAMT mode.
1699         */
1700        if (!e1000_check_mng_mode(hw)) {
1701            /* Enable Electrical Idle on the PHY */
1702            phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1703            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1704                                          phy_data);
1705            if (ret_val)
1706                return ret_val;
1707
1708            ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1709                                         &phy_data);
1710            if (ret_val)
1711                return ret_val;
1712
1713            phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1714            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1715                                          phy_data);
1716
1717            if (ret_val)
1718                return ret_val;
1719        }
1720
1721        /* Workaround: Disable padding in Kumeran interface in the MAC
1722         * and in the PHY to avoid CRC errors.
1723         */
1724        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1725                                     &phy_data);
1726        if (ret_val)
1727            return ret_val;
1728        phy_data |= GG82563_ICR_DIS_PADDING;
1729        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1730                                      phy_data);
1731        if (ret_val)
1732            return ret_val;
1733    }
1734
1735    return E1000_SUCCESS;
1736}
1737
1738/********************************************************************
1739* Copper link setup for e1000_phy_m88 series.
1740*
1741* hw - Struct containing variables accessed by shared code
1742*********************************************************************/
1743static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1744{
1745    s32 ret_val;
1746    u16 phy_data;
1747
1748    DEBUGFUNC("e1000_copper_link_mgp_setup");
1749
1750    if (hw->phy_reset_disable)
1751        return E1000_SUCCESS;
1752
1753    /* Enable CRS on TX. This must be set for half-duplex operation. */
1754    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1755    if (ret_val)
1756        return ret_val;
1757
1758    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1759
1760    /* Options:
1761     *   MDI/MDI-X = 0 (default)
1762     *   0 - Auto for all speeds
1763     *   1 - MDI mode
1764     *   2 - MDI-X mode
1765     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1766     */
1767    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1768
1769    switch (hw->mdix) {
1770    case 1:
1771        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1772        break;
1773    case 2:
1774        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1775        break;
1776    case 3:
1777        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1778        break;
1779    case 0:
1780    default:
1781        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1782        break;
1783    }
1784
1785    /* Options:
1786     *   disable_polarity_correction = 0 (default)
1787     *       Automatic Correction for Reversed Cable Polarity
1788     *   0 - Disabled
1789     *   1 - Enabled
1790     */
1791    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1792    if (hw->disable_polarity_correction == 1)
1793        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1794    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1795    if (ret_val)
1796        return ret_val;
1797
1798    if (hw->phy_revision < M88E1011_I_REV_4) {
1799        /* Force TX_CLK in the Extended PHY Specific Control Register
1800         * to 25MHz clock.
1801         */
1802        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1803        if (ret_val)
1804            return ret_val;
1805
1806        phy_data |= M88E1000_EPSCR_TX_CLK_25;
1807
1808        if ((hw->phy_revision == E1000_REVISION_2) &&
1809            (hw->phy_id == M88E1111_I_PHY_ID)) {
1810            /* Vidalia Phy, set the downshift counter to 5x */
1811            phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1812            phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1813            ret_val = e1000_write_phy_reg(hw,
1814                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1815            if (ret_val)
1816                return ret_val;
1817        } else {
1818            /* Configure Master and Slave downshift values */
1819            phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1820                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1821            phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1822                             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1823            ret_val = e1000_write_phy_reg(hw,
1824                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1825            if (ret_val)
1826               return ret_val;
1827        }
1828    }
1829
1830    /* SW Reset the PHY so all changes take effect */
1831    ret_val = e1000_phy_reset(hw);
1832    if (ret_val) {
1833        DEBUGOUT("Error Resetting the PHY\n");
1834        return ret_val;
1835    }
1836
1837   return E1000_SUCCESS;
1838}
1839
1840/********************************************************************
1841* Setup auto-negotiation and flow control advertisements,
1842* and then perform auto-negotiation.
1843*
1844* hw - Struct containing variables accessed by shared code
1845*********************************************************************/
1846static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1847{
1848    s32 ret_val;
1849    u16 phy_data;
1850
1851    DEBUGFUNC("e1000_copper_link_autoneg");
1852
1853    /* Perform some bounds checking on the hw->autoneg_advertised
1854     * parameter.  If this variable is zero, then set it to the default.
1855     */
1856    hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1857
1858    /* If autoneg_advertised is zero, we assume it was not defaulted
1859     * by the calling code so we set to advertise full capability.
1860     */
1861    if (hw->autoneg_advertised == 0)
1862        hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1863
1864    /* IFE phy only supports 10/100 */
1865    if (hw->phy_type == e1000_phy_ife)
1866        hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1867
1868    DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1869    ret_val = e1000_phy_setup_autoneg(hw);
1870    if (ret_val) {
1871        DEBUGOUT("Error Setting up Auto-Negotiation\n");
1872        return ret_val;
1873    }
1874    DEBUGOUT("Restarting Auto-Neg\n");
1875
1876    /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1877     * the Auto Neg Restart bit in the PHY control register.
1878     */
1879    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1880    if (ret_val)
1881        return ret_val;
1882
1883    phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1884    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1885    if (ret_val)
1886        return ret_val;
1887
1888    /* Does the user want to wait for Auto-Neg to complete here, or
1889     * check at a later time (for example, callback routine).
1890     */
1891    if (hw->wait_autoneg_complete) {
1892        ret_val = e1000_wait_autoneg(hw);
1893        if (ret_val) {
1894            DEBUGOUT("Error while waiting for autoneg to complete\n");
1895            return ret_val;
1896        }
1897    }
1898
1899    hw->get_link_status = true;
1900
1901    return E1000_SUCCESS;
1902}
1903
1904/******************************************************************************
1905* Config the MAC and the PHY after link is up.
1906*   1) Set up the MAC to the current PHY speed/duplex
1907*      if we are on 82543.  If we
1908*      are on newer silicon, we only need to configure
1909*      collision distance in the Transmit Control Register.
1910*   2) Set up flow control on the MAC to that established with
1911*      the link partner.
1912*   3) Config DSP to improve Gigabit link quality for some PHY revisions.
1913*
1914* hw - Struct containing variables accessed by shared code
1915******************************************************************************/
1916static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1917{
1918    s32 ret_val;
1919    DEBUGFUNC("e1000_copper_link_postconfig");
1920
1921    if (hw->mac_type >= e1000_82544) {
1922        e1000_config_collision_dist(hw);
1923    } else {
1924        ret_val = e1000_config_mac_to_phy(hw);
1925        if (ret_val) {
1926            DEBUGOUT("Error configuring MAC to PHY settings\n");
1927            return ret_val;
1928        }
1929    }
1930    ret_val = e1000_config_fc_after_link_up(hw);
1931    if (ret_val) {
1932        DEBUGOUT("Error Configuring Flow Control\n");
1933        return ret_val;
1934    }
1935
1936    /* Config DSP to improve Giga link quality */
1937    if (hw->phy_type == e1000_phy_igp) {
1938        ret_val = e1000_config_dsp_after_link_change(hw, true);
1939        if (ret_val) {
1940            DEBUGOUT("Error Configuring DSP after link up\n");
1941            return ret_val;
1942        }
1943    }
1944
1945    return E1000_SUCCESS;
1946}
1947
1948/******************************************************************************
1949* Detects which PHY is present and setup the speed and duplex
1950*
1951* hw - Struct containing variables accessed by shared code
1952******************************************************************************/
1953static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1954{
1955    s32 ret_val;
1956    u16 i;
1957    u16 phy_data;
1958    u16 reg_data;
1959
1960    DEBUGFUNC("e1000_setup_copper_link");
1961
1962    switch (hw->mac_type) {
1963    case e1000_80003es2lan:
1964    case e1000_ich8lan:
1965        /* Set the mac to wait the maximum time between each
1966         * iteration and increase the max iterations when
1967         * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1968        ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1969        if (ret_val)
1970            return ret_val;
1971        ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1972        if (ret_val)
1973            return ret_val;
1974        reg_data |= 0x3F;
1975        ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1976        if (ret_val)
1977            return ret_val;
1978    default:
1979        break;
1980    }
1981
1982    /* Check if it is a valid PHY and set PHY mode if necessary. */
1983    ret_val = e1000_copper_link_preconfig(hw);
1984    if (ret_val)
1985        return ret_val;
1986
1987    switch (hw->mac_type) {
1988    case e1000_80003es2lan:
1989        /* Kumeran registers are written-only */
1990        reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1991        reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1992        ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1993                                       reg_data);
1994        if (ret_val)
1995            return ret_val;
1996        break;
1997    default:
1998        break;
1999    }
2000
2001    if (hw->phy_type == e1000_phy_igp ||
2002        hw->phy_type == e1000_phy_igp_3 ||
2003        hw->phy_type == e1000_phy_igp_2) {
2004        ret_val = e1000_copper_link_igp_setup(hw);
2005        if (ret_val)
2006            return ret_val;
2007    } else if (hw->phy_type == e1000_phy_m88) {
2008        ret_val = e1000_copper_link_mgp_setup(hw);
2009        if (ret_val)
2010            return ret_val;
2011    } else if (hw->phy_type == e1000_phy_gg82563) {
2012        ret_val = e1000_copper_link_ggp_setup(hw);
2013        if (ret_val)
2014            return ret_val;
2015    }
2016
2017    if (hw->autoneg) {
2018        /* Setup autoneg and flow control advertisement
2019          * and perform autonegotiation */
2020        ret_val = e1000_copper_link_autoneg(hw);
2021        if (ret_val)
2022            return ret_val;
2023    } else {
2024        /* PHY will be set to 10H, 10F, 100H,or 100F
2025          * depending on value from forced_speed_duplex. */
2026        DEBUGOUT("Forcing speed and duplex\n");
2027        ret_val = e1000_phy_force_speed_duplex(hw);
2028        if (ret_val) {
2029            DEBUGOUT("Error Forcing Speed and Duplex\n");
2030            return ret_val;
2031        }
2032    }
2033
2034    /* Check link status. Wait up to 100 microseconds for link to become
2035     * valid.
2036     */
2037    for (i = 0; i < 10; i++) {
2038        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2039        if (ret_val)
2040            return ret_val;
2041        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2042        if (ret_val)
2043            return ret_val;
2044
2045        if (phy_data & MII_SR_LINK_STATUS) {
2046            /* Config the MAC and PHY after link is up */
2047            ret_val = e1000_copper_link_postconfig(hw);
2048            if (ret_val)
2049                return ret_val;
2050
2051            DEBUGOUT("Valid link established!!!\n");
2052            return E1000_SUCCESS;
2053        }
2054        udelay(10);
2055    }
2056
2057    DEBUGOUT("Unable to establish link!!!\n");
2058    return E1000_SUCCESS;
2059}
2060
2061/******************************************************************************
2062* Configure the MAC-to-PHY interface for 10/100Mbps
2063*
2064* hw - Struct containing variables accessed by shared code
2065******************************************************************************/
2066static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2067{
2068    s32 ret_val = E1000_SUCCESS;
2069    u32 tipg;
2070    u16 reg_data;
2071
2072    DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2073
2074    reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2075    ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2076                                   reg_data);
2077    if (ret_val)
2078        return ret_val;
2079
2080    /* Configure Transmit Inter-Packet Gap */
2081    tipg = er32(TIPG);
2082    tipg &= ~E1000_TIPG_IPGT_MASK;
2083    tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2084    ew32(TIPG, tipg);
2085
2086    ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2087
2088    if (ret_val)
2089        return ret_val;
2090
2091    if (duplex == HALF_DUPLEX)
2092        reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2093    else
2094        reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2095
2096    ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2097
2098    return ret_val;
2099}
2100
2101static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2102{
2103    s32 ret_val = E1000_SUCCESS;
2104    u16 reg_data;
2105    u32 tipg;
2106
2107    DEBUGFUNC("e1000_configure_kmrn_for_1000");
2108
2109    reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2110    ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2111                                   reg_data);
2112    if (ret_val)
2113        return ret_val;
2114
2115    /* Configure Transmit Inter-Packet Gap */
2116    tipg = er32(TIPG);
2117    tipg &= ~E1000_TIPG_IPGT_MASK;
2118    tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2119    ew32(TIPG, tipg);
2120
2121    ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2122
2123    if (ret_val)
2124        return ret_val;
2125
2126    reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2127    ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2128
2129    return ret_val;
2130}
2131
2132/******************************************************************************
2133* Configures PHY autoneg and flow control advertisement settings
2134*
2135* hw - Struct containing variables accessed by shared code
2136******************************************************************************/
2137s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2138{
2139    s32 ret_val;
2140    u16 mii_autoneg_adv_reg;
2141    u16 mii_1000t_ctrl_reg;
2142
2143    DEBUGFUNC("e1000_phy_setup_autoneg");
2144
2145    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2146    ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2147    if (ret_val)
2148        return ret_val;
2149
2150    if (hw->phy_type != e1000_phy_ife) {
2151        /* Read the MII 1000Base-T Control Register (Address 9). */
2152        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2153        if (ret_val)
2154            return ret_val;
2155    } else
2156        mii_1000t_ctrl_reg=0;
2157
2158    /* Need to parse both autoneg_advertised and fc and set up
2159     * the appropriate PHY registers.  First we will parse for
2160     * autoneg_advertised software override.  Since we can advertise
2161     * a plethora of combinations, we need to check each bit
2162     * individually.
2163     */
2164
2165    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2166     * Advertisement Register (Address 4) and the 1000 mb speed bits in
2167     * the  1000Base-T Control Register (Address 9).
2168     */
2169    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2170    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2171
2172    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2173
2174    /* Do we want to advertise 10 Mb Half Duplex? */
2175    if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2176        DEBUGOUT("Advertise 10mb Half duplex\n");
2177        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2178    }
2179
2180    /* Do we want to advertise 10 Mb Full Duplex? */
2181    if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2182        DEBUGOUT("Advertise 10mb Full duplex\n");
2183        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2184    }
2185
2186    /* Do we want to advertise 100 Mb Half Duplex? */
2187    if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2188        DEBUGOUT("Advertise 100mb Half duplex\n");
2189        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2190    }
2191
2192    /* Do we want to advertise 100 Mb Full Duplex? */
2193    if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2194        DEBUGOUT("Advertise 100mb Full duplex\n");
2195        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2196    }
2197
2198    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2199    if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2200        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2201    }
2202
2203    /* Do we want to advertise 1000 Mb Full Duplex? */
2204    if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2205        DEBUGOUT("Advertise 1000mb Full duplex\n");
2206        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2207        if (hw->phy_type == e1000_phy_ife) {
2208            DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2209        }
2210    }
2211
2212    /* Check for a software override of the flow control settings, and
2213     * setup the PHY advertisement registers accordingly.  If
2214     * auto-negotiation is enabled, then software will have to set the
2215     * "PAUSE" bits to the correct value in the Auto-Negotiation
2216     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2217     *
2218     * The possible values of the "fc" parameter are:
2219     *      0:  Flow control is completely disabled
2220     *      1:  Rx flow control is enabled (we can receive pause frames
2221     *          but not send pause frames).
2222     *      2:  Tx flow control is enabled (we can send pause frames
2223     *          but we do not support receiving pause frames).
2224     *      3:  Both Rx and TX flow control (symmetric) are enabled.
2225     *  other:  No software override.  The flow control configuration
2226     *          in the EEPROM is used.
2227     */
2228    switch (hw->fc) {
2229    case E1000_FC_NONE: /* 0 */
2230        /* Flow control (RX & TX) is completely disabled by a
2231         * software over-ride.
2232         */
2233        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2234        break;
2235    case E1000_FC_RX_PAUSE: /* 1 */
2236        /* RX Flow control is enabled, and TX Flow control is
2237         * disabled, by a software over-ride.
2238         */
2239        /* Since there really isn't a way to advertise that we are
2240         * capable of RX Pause ONLY, we will advertise that we
2241         * support both symmetric and asymmetric RX PAUSE.  Later
2242         * (in e1000_config_fc_after_link_up) we will disable the
2243         *hw's ability to send PAUSE frames.
2244         */
2245        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2246        break;
2247    case E1000_FC_TX_PAUSE: /* 2 */
2248        /* TX Flow control is enabled, and RX Flow control is
2249         * disabled, by a software over-ride.
2250         */
2251        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2252        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2253        break;
2254    case E1000_FC_FULL: /* 3 */
2255        /* Flow control (both RX and TX) is enabled by a software
2256         * over-ride.
2257         */
2258        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2259        break;
2260    default:
2261        DEBUGOUT("Flow control param set incorrectly\n");
2262        return -E1000_ERR_CONFIG;
2263    }
2264
2265    ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2266    if (ret_val)
2267        return ret_val;
2268
2269    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2270
2271    if (hw->phy_type != e1000_phy_ife) {
2272        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2273        if (ret_val)
2274            return ret_val;
2275    }
2276
2277    return E1000_SUCCESS;
2278}
2279
2280/******************************************************************************
2281* Force PHY speed and duplex settings to hw->forced_speed_duplex
2282*
2283* hw - Struct containing variables accessed by shared code
2284******************************************************************************/
2285static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2286{
2287    u32 ctrl;
2288    s32 ret_val;
2289    u16 mii_ctrl_reg;
2290    u16 mii_status_reg;
2291    u16 phy_data;
2292    u16 i;
2293
2294    DEBUGFUNC("e1000_phy_force_speed_duplex");
2295
2296    /* Turn off Flow control if we are forcing speed and duplex. */
2297    hw->fc = E1000_FC_NONE;
2298
2299    DEBUGOUT1("hw->fc = %d\n", hw->fc);
2300
2301    /* Read the Device Control Register. */
2302    ctrl = er32(CTRL);
2303
2304    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2305    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2306    ctrl &= ~(DEVICE_SPEED_MASK);
2307
2308    /* Clear the Auto Speed Detect Enable bit. */
2309    ctrl &= ~E1000_CTRL_ASDE;
2310
2311    /* Read the MII Control Register. */
2312    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2313    if (ret_val)
2314        return ret_val;
2315
2316    /* We need to disable autoneg in order to force link and duplex. */
2317
2318    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2319
2320    /* Are we forcing Full or Half Duplex? */
2321    if (hw->forced_speed_duplex == e1000_100_full ||
2322        hw->forced_speed_duplex == e1000_10_full) {
2323        /* We want to force full duplex so we SET the full duplex bits in the
2324         * Device and MII Control Registers.
2325         */
2326        ctrl |= E1000_CTRL_FD;
2327        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2328        DEBUGOUT("Full Duplex\n");
2329    } else {
2330        /* We want to force half duplex so we CLEAR the full duplex bits in
2331         * the Device and MII Control Registers.
2332         */
2333        ctrl &= ~E1000_CTRL_FD;
2334        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2335        DEBUGOUT("Half Duplex\n");
2336    }
2337
2338    /* Are we forcing 100Mbps??? */
2339    if (hw->forced_speed_duplex == e1000_100_full ||
2340       hw->forced_speed_duplex == e1000_100_half) {
2341        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2342        ctrl |= E1000_CTRL_SPD_100;
2343        mii_ctrl_reg |= MII_CR_SPEED_100;
2344        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2345        DEBUGOUT("Forcing 100mb ");
2346    } else {
2347        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2348        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2349        mii_ctrl_reg |= MII_CR_SPEED_10;
2350        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2351        DEBUGOUT("Forcing 10mb ");
2352    }
2353
2354    e1000_config_collision_dist(hw);
2355
2356    /* Write the configured values back to the Device Control Reg. */
2357    ew32(CTRL, ctrl);
2358
2359    if ((hw->phy_type == e1000_phy_m88) ||
2360        (hw->phy_type == e1000_phy_gg82563)) {
2361        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2362        if (ret_val)
2363            return ret_val;
2364
2365        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2366         * forced whenever speed are duplex are forced.
2367         */
2368        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2369        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2370        if (ret_val)
2371            return ret_val;
2372
2373        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2374
2375        /* Need to reset the PHY or these changes will be ignored */
2376        mii_ctrl_reg |= MII_CR_RESET;
2377
2378    /* Disable MDI-X support for 10/100 */
2379    } else if (hw->phy_type == e1000_phy_ife) {
2380        ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2381        if (ret_val)
2382            return ret_val;
2383
2384        phy_data &= ~IFE_PMC_AUTO_MDIX;
2385        phy_data &= ~IFE_PMC_FORCE_MDIX;
2386
2387        ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2388        if (ret_val)
2389            return ret_val;
2390
2391    } else {
2392        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
2393         * forced whenever speed or duplex are forced.
2394         */
2395        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2396        if (ret_val)
2397            return ret_val;
2398
2399        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2400        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2401
2402        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2403        if (ret_val)
2404            return ret_val;
2405    }
2406
2407    /* Write back the modified PHY MII control register. */
2408    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2409    if (ret_val)
2410        return ret_val;
2411
2412    udelay(1);
2413
2414    /* The wait_autoneg_complete flag may be a little misleading here.
2415     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2416     * But we do want to delay for a period while forcing only so we
2417     * don't generate false No Link messages.  So we will wait here
2418     * only if the user has set wait_autoneg_complete to 1, which is
2419     * the default.
2420     */
2421    if (hw->wait_autoneg_complete) {
2422        /* We will wait for autoneg to complete. */
2423        DEBUGOUT("Waiting for forced speed/duplex link.\n");
2424        mii_status_reg = 0;
2425
2426        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2427        for (i = PHY_FORCE_TIME; i > 0; i--) {
2428            /* Read the MII Status Register and wait for Auto-Neg Complete bit
2429             * to be set.
2430             */
2431            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2432            if (ret_val)
2433                return ret_val;
2434
2435            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2436            if (ret_val)
2437                return ret_val;
2438
2439            if (mii_status_reg & MII_SR_LINK_STATUS) break;
2440            msleep(100);
2441        }
2442        if ((i == 0) &&
2443           ((hw->phy_type == e1000_phy_m88) ||
2444            (hw->phy_type == e1000_phy_gg82563))) {
2445            /* We didn't get link.  Reset the DSP and wait again for link. */
2446            ret_val = e1000_phy_reset_dsp(hw);
2447            if (ret_val) {
2448                DEBUGOUT("Error Resetting PHY DSP\n");
2449                return ret_val;
2450            }
2451        }
2452        /* This loop will early-out if the link condition has been met.  */
2453        for (i = PHY_FORCE_TIME; i > 0; i--) {
2454            if (mii_status_reg & MII_SR_LINK_STATUS) break;
2455            msleep(100);
2456            /* Read the MII Status Register and wait for Auto-Neg Complete bit
2457             * to be set.
2458             */
2459            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2460            if (ret_val)
2461                return ret_val;
2462
2463            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2464            if (ret_val)
2465                return ret_val;
2466        }
2467    }
2468
2469    if (hw->phy_type == e1000_phy_m88) {
2470        /* Because we reset the PHY above, we need to re-force TX_CLK in the
2471         * Extended PHY Specific Control Register to 25MHz clock.  This value
2472         * defaults back to a 2.5MHz clock when the PHY is reset.
2473         */
2474        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2475        if (ret_val)
2476            return ret_val;
2477
2478        phy_data |= M88E1000_EPSCR_TX_CLK_25;
2479        ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2480        if (ret_val)
2481            return ret_val;
2482
2483        /* In addition, because of the s/w reset above, we need to enable CRS on
2484         * TX.  This must be set for both full and half duplex operation.
2485         */
2486        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2487        if (ret_val)
2488            return ret_val;
2489
2490        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2491        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2492        if (ret_val)
2493            return ret_val;
2494
2495        if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2496            (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2497             hw->forced_speed_duplex == e1000_10_half)) {
2498            ret_val = e1000_polarity_reversal_workaround(hw);
2499            if (ret_val)
2500                return ret_val;
2501        }
2502    } else if (hw->phy_type == e1000_phy_gg82563) {
2503        /* The TX_CLK of the Extended PHY Specific Control Register defaults
2504         * to 2.5MHz on a reset.  We need to re-force it back to 25MHz, if
2505         * we're not in a forced 10/duplex configuration. */
2506        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2507        if (ret_val)
2508            return ret_val;
2509
2510        phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2511        if ((hw->forced_speed_duplex == e1000_10_full) ||
2512            (hw->forced_speed_duplex == e1000_10_half))
2513            phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2514        else
2515            phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2516
2517        /* Also due to the reset, we need to enable CRS on Tx. */
2518        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2519
2520        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2521        if (ret_val)
2522            return ret_val;
2523    }
2524    return E1000_SUCCESS;
2525}
2526
2527/******************************************************************************
2528* Sets the collision distance in the Transmit Control register
2529*
2530* hw - Struct containing variables accessed by shared code
2531*
2532* Link should have been established previously. Reads the speed and duplex
2533* information from the Device Status register.
2534******************************************************************************/
2535void e1000_config_collision_dist(struct e1000_hw *hw)
2536{
2537    u32 tctl, coll_dist;
2538
2539    DEBUGFUNC("e1000_config_collision_dist");
2540
2541    if (hw->mac_type < e1000_82543)
2542        coll_dist = E1000_COLLISION_DISTANCE_82542;
2543    else
2544        coll_dist = E1000_COLLISION_DISTANCE;
2545
2546    tctl = er32(TCTL);
2547
2548    tctl &= ~E1000_TCTL_COLD;
2549    tctl |= coll_dist << E1000_COLD_SHIFT;
2550
2551    ew32(TCTL, tctl);
2552    E1000_WRITE_FLUSH();
2553}
2554
2555/******************************************************************************
2556* Sets MAC speed and duplex settings to reflect the those in the PHY
2557*
2558* hw - Struct containing variables accessed by shared code
2559* mii_reg - data to write to the MII control register
2560*
2561* The contents of the PHY register containing the needed information need to
2562* be passed in.
2563******************************************************************************/
2564static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
2565{
2566    u32 ctrl;
2567    s32 ret_val;
2568    u16 phy_data;
2569
2570    DEBUGFUNC("e1000_config_mac_to_phy");
2571
2572    /* 82544 or newer MAC, Auto Speed Detection takes care of
2573    * MAC speed/duplex configuration.*/
2574    if (hw->mac_type >= e1000_82544)
2575        return E1000_SUCCESS;
2576
2577    /* Read the Device Control Register and set the bits to Force Speed
2578     * and Duplex.
2579     */
2580    ctrl = er32(CTRL);
2581    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2582    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2583
2584    /* Set up duplex in the Device Control and Transmit Control
2585     * registers depending on negotiated values.
2586     */
2587    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2588    if (ret_val)
2589        return ret_val;
2590
2591    if (phy_data & M88E1000_PSSR_DPLX)
2592        ctrl |= E1000_CTRL_FD;
2593    else
2594        ctrl &= ~E1000_CTRL_FD;
2595
2596    e1000_config_collision_dist(hw);
2597
2598    /* Set up speed in the Device Control register depending on
2599     * negotiated values.
2600     */
2601    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2602        ctrl |= E1000_CTRL_SPD_1000;
2603    else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2604        ctrl |= E1000_CTRL_SPD_100;
2605
2606    /* Write the configured values back to the Device Control Reg. */
2607    ew32(CTRL, ctrl);
2608    return E1000_SUCCESS;
2609}
2610
2611/******************************************************************************
2612 * Forces the MAC's flow control settings.
2613 *
2614 * hw - Struct containing variables accessed by shared code
2615 *
2616 * Sets the TFCE and RFCE bits in the device control register to reflect
2617 * the adapter settings. TFCE and RFCE need to be explicitly set by
2618 * software when a Copper PHY is used because autonegotiation is managed
2619 * by the PHY rather than the MAC. Software must also configure these
2620 * bits when link is forced on a fiber connection.
2621 *****************************************************************************/
2622s32 e1000_force_mac_fc(struct e1000_hw *hw)
2623{
2624    u32 ctrl;
2625
2626    DEBUGFUNC("e1000_force_mac_fc");
2627
2628    /* Get the current configuration of the Device Control Register */
2629    ctrl = er32(CTRL);
2630
2631    /* Because we didn't get link via the internal auto-negotiation
2632     * mechanism (we either forced link or we got link via PHY
2633     * auto-neg), we have to manually enable/disable transmit an
2634     * receive flow control.
2635     *
2636     * The "Case" statement below enables/disable flow control
2637     * according to the "hw->fc" parameter.
2638     *
2639     * The possible values of the "fc" parameter are:
2640     *      0:  Flow control is completely disabled
2641     *      1:  Rx flow control is enabled (we can receive pause
2642     *          frames but not send pause frames).
2643     *      2:  Tx flow control is enabled (we can send pause frames
2644     *          frames but we do not receive pause frames).
2645     *      3:  Both Rx and TX flow control (symmetric) is enabled.
2646     *  other:  No other values should be possible at this point.
2647     */
2648
2649    switch (hw->fc) {
2650    case E1000_FC_NONE:
2651        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2652        break;
2653    case E1000_FC_RX_PAUSE:
2654        ctrl &= (~E1000_CTRL_TFCE);
2655        ctrl |= E1000_CTRL_RFCE;
2656        break;
2657    case E1000_FC_TX_PAUSE:
2658        ctrl &= (~E1000_CTRL_RFCE);
2659        ctrl |= E1000_CTRL_TFCE;
2660        break;
2661    case E1000_FC_FULL:
2662        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2663        break;
2664    default:
2665        DEBUGOUT("Flow control param set incorrectly\n");
2666        return -E1000_ERR_CONFIG;
2667    }
2668
2669    /* Disable TX Flow Control for 82542 (rev 2.0) */
2670    if (hw->mac_type == e1000_82542_rev2_0)
2671        ctrl &= (~E1000_CTRL_TFCE);
2672
2673    ew32(CTRL, ctrl);
2674    return E1000_SUCCESS;
2675}
2676
2677/******************************************************************************
2678 * Configures flow control settings after link is established
2679 *
2680 * hw - Struct containing variables accessed by shared code
2681 *
2682 * Should be called immediately after a valid link has been established.
2683 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2684 * and autonegotiation is enabled, the MAC flow control settings will be set
2685 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2686 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2687 *****************************************************************************/
2688static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2689{
2690    s32 ret_val;
2691    u16 mii_status_reg;
2692    u16 mii_nway_adv_reg;
2693    u16 mii_nway_lp_ability_reg;
2694    u16 speed;
2695    u16 duplex;
2696
2697    DEBUGFUNC("e1000_config_fc_after_link_up");
2698
2699    /* Check for the case where we have fiber media and auto-neg failed
2700     * so we had to force link.  In this case, we need to force the
2701     * configuration of the MAC to match the "fc" parameter.
2702     */
2703    if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2704        ((hw->media_type == e1000_media_type_internal_serdes) &&
2705         (hw->autoneg_failed)) ||
2706        ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2707        ret_val = e1000_force_mac_fc(hw);
2708        if (ret_val) {
2709            DEBUGOUT("Error forcing flow control settings\n");
2710            return ret_val;
2711        }
2712    }
2713
2714    /* Check for the case where we have copper media and auto-neg is
2715     * enabled.  In this case, we need to check and see if Auto-Neg
2716     * has completed, and if so, how the PHY and link partner has
2717     * flow control configured.
2718     */
2719    if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2720        /* Read the MII Status Register and check to see if AutoNeg
2721         * has completed.  We read this twice because this reg has
2722         * some "sticky" (latched) bits.
2723         */
2724        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2725        if (ret_val)
2726            return ret_val;
2727        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2728        if (ret_val)
2729            return ret_val;
2730
2731        if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2732            /* The AutoNeg process has completed, so we now need to
2733             * read both the Auto Negotiation Advertisement Register
2734             * (Address 4) and the Auto_Negotiation Base Page Ability
2735             * Register (Address 5) to determine how flow control was
2736             * negotiated.
2737             */
2738            ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2739                                         &mii_nway_adv_reg);
2740            if (ret_val)
2741                return ret_val;
2742            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2743                                         &mii_nway_lp_ability_reg);
2744            if (ret_val)
2745                return ret_val;
2746
2747            /* Two bits in the Auto Negotiation Advertisement Register
2748             * (Address 4) and two bits in the Auto Negotiation Base
2749             * Page Ability Register (Address 5) determine flow control
2750             * for both the PHY and the link partner.  The following
2751             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2752             * 1999, describes these PAUSE resolution bits and how flow
2753             * control is determined based upon these settings.
2754             * NOTE:  DC = Don't Care
2755             *
2756             *   LOCAL DEVICE  |   LINK PARTNER
2757             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2758             *-------|---------|-------|---------|--------------------
2759             *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
2760             *   0   |    1    |   0   |   DC    | E1000_FC_NONE
2761             *   0   |    1    |   1   |    0    | E1000_FC_NONE
2762             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
2763             *   1   |    0    |   0   |   DC    | E1000_FC_NONE
2764             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
2765             *   1   |    1    |   0   |    0    | E1000_FC_NONE
2766             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
2767             *
2768             */
2769            /* Are both PAUSE bits set to 1?  If so, this implies
2770             * Symmetric Flow Control is enabled at both ends.  The
2771             * ASM_DIR bits are irrelevant per the spec.
2772             *
2773             * For Symmetric Flow Control:
2774             *
2775             *   LOCAL DEVICE  |   LINK PARTNER
2776             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2777             *-------|---------|-------|---------|--------------------
2778             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
2779             *
2780             */
2781            if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2782                (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2783                /* Now we need to check if the user selected RX ONLY
2784                 * of pause frames.  In this case, we had to advertise
2785                 * FULL flow control because we could not advertise RX
2786                 * ONLY. Hence, we must now check to see if we need to
2787                 * turn OFF  the TRANSMISSION of PAUSE frames.
2788                 */
2789                if (hw->original_fc == E1000_FC_FULL) {
2790                    hw->fc = E1000_FC_FULL;
2791                    DEBUGOUT("Flow Control = FULL.\n");
2792                } else {
2793                    hw->fc = E1000_FC_RX_PAUSE;
2794                    DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2795                }
2796            }
2797            /* For receiving PAUSE frames ONLY.
2798             *
2799             *   LOCAL DEVICE  |   LINK PARTNER
2800             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2801             *-------|---------|-------|---------|--------------------
2802             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
2803             *
2804             */
2805            else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2806                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2807                     (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2808                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2809                hw->fc = E1000_FC_TX_PAUSE;
2810                DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2811            }
2812            /* For transmitting PAUSE frames ONLY.
2813             *
2814             *   LOCAL DEVICE  |   LINK PARTNER
2815             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2816             *-------|---------|-------|---------|--------------------
2817             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
2818             *
2819             */
2820            else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2821                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2822                     !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2823                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2824                hw->fc = E1000_FC_RX_PAUSE;
2825                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2826            }
2827            /* Per the IEEE spec, at this point flow control should be
2828             * disabled.  However, we want to consider that we could
2829             * be connected to a legacy switch that doesn't advertise
2830             * desired flow control, but can be forced on the link
2831             * partner.  So if we advertised no flow control, that is
2832             * what we will resolve to.  If we advertised some kind of
2833             * receive capability (Rx Pause Only or Full Flow Control)
2834             * and the link partner advertised none, we will configure
2835             * ourselves to enable Rx Flow Control only.  We can do
2836             * this safely for two reasons:  If the link partner really
2837             * didn't want flow control enabled, and we enable Rx, no
2838             * harm done since we won't be receiving any PAUSE frames
2839             * anyway.  If the intent on the link partner was to have
2840             * flow control enabled, then by us enabling RX only, we
2841             * can at least receive pause frames and process them.
2842             * This is a good idea because in most cases, since we are
2843             * predominantly a server NIC, more times than not we will
2844             * be asked to delay transmission of packets than asking
2845             * our link partner to pause transmission of frames.
2846             */
2847            else if ((hw->original_fc == E1000_FC_NONE ||
2848                      hw->original_fc == E1000_FC_TX_PAUSE) ||
2849                      hw->fc_strict_ieee) {
2850                hw->fc = E1000_FC_NONE;
2851                DEBUGOUT("Flow Control = NONE.\n");
2852            } else {
2853                hw->fc = E1000_FC_RX_PAUSE;
2854                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2855            }
2856
2857            /* Now we need to do one last check...  If we auto-
2858             * negotiated to HALF DUPLEX, flow control should not be
2859             * enabled per IEEE 802.3 spec.
2860             */
2861            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2862            if (ret_val) {
2863                DEBUGOUT("Error getting link speed and duplex\n");
2864                return ret_val;
2865            }
2866
2867            if (duplex == HALF_DUPLEX)
2868                hw->fc = E1000_FC_NONE;
2869
2870            /* Now we call a subroutine to actually force the MAC
2871             * controller to use the correct flow control settings.
2872             */
2873            ret_val = e1000_force_mac_fc(hw);
2874            if (ret_val) {
2875                DEBUGOUT("Error forcing flow control settings\n");
2876                return ret_val;
2877            }
2878        } else {
2879            DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2880        }
2881    }
2882    return E1000_SUCCESS;
2883}
2884
2885/******************************************************************************
2886 * Checks to see if the link status of the hardware has changed.
2887 *
2888 * hw - Struct containing variables accessed by shared code
2889 *
2890 * Called by any function that needs to check the link status of the adapter.
2891 *****************************************************************************/
2892s32 e1000_check_for_link(struct e1000_hw *hw)
2893{
2894    u32 rxcw = 0;
2895    u32 ctrl;
2896    u32 status;
2897    u32 rctl;
2898    u32 icr;
2899    u32 signal = 0;
2900    s32 ret_val;
2901    u16 phy_data;
2902
2903    DEBUGFUNC("e1000_check_for_link");
2904
2905    ctrl = er32(CTRL);
2906    status = er32(STATUS);
2907
2908    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2909     * set when the optics detect a signal. On older adapters, it will be
2910     * cleared when there is a signal.  This applies to fiber media only.
2911     */
2912    if ((hw->media_type == e1000_media_type_fiber) ||
2913        (hw->media_type == e1000_media_type_internal_serdes)) {
2914        rxcw = er32(RXCW);
2915
2916        if (hw->media_type == e1000_media_type_fiber) {
2917            signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2918            if (status & E1000_STATUS_LU)
2919                hw->get_link_status = false;
2920        }
2921    }
2922
2923    /* If we have a copper PHY then we only want to go out to the PHY
2924     * registers to see if Auto-Neg has completed and/or if our link
2925     * status has changed.  The get_link_status flag will be set if we
2926     * receive a Link Status Change interrupt or we have Rx Sequence
2927     * Errors.
2928     */
2929    if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2930        /* First we want to see if the MII Status Register reports
2931         * link.  If so, then we want to get the current speed/duplex
2932         * of the PHY.
2933         * Read the register twice since the link bit is sticky.
2934         */
2935        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2936        if (ret_val)
2937            return ret_val;
2938        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2939        if (ret_val)
2940            return ret_val;
2941
2942        if (phy_data & MII_SR_LINK_STATUS) {
2943            hw->get_link_status = false;
2944            /* Check if there was DownShift, must be checked immediately after
2945             * link-up */
2946            e1000_check_downshift(hw);
2947
2948            /* If we are on 82544 or 82543 silicon and speed/duplex
2949             * are forced to 10H or 10F, then we will implement the polarity
2950             * reversal workaround.  We disable interrupts first, and upon
2951             * returning, place the devices interrupt state to its previous
2952             * value except for the link status change interrupt which will
2953             * happen due to the execution of this workaround.
2954             */
2955
2956            if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2957                (!hw->autoneg) &&
2958                (hw->forced_speed_duplex == e1000_10_full ||
2959                 hw->forced_speed_duplex == e1000_10_half)) {
2960                ew32(IMC, 0xffffffff);
2961                ret_val = e1000_polarity_reversal_workaround(hw);
2962                icr = er32(ICR);
2963                ew32(ICS, (icr & ~E1000_ICS_LSC));
2964                ew32(IMS, IMS_ENABLE_MASK);
2965            }
2966
2967        } else {
2968            /* No link detected */
2969            e1000_config_dsp_after_link_change(hw, false);
2970            return 0;
2971        }
2972
2973        /* If we are forcing speed/duplex, then we simply return since
2974         * we have already determined whether we have link or not.
2975         */
2976        if (!hw->autoneg) return -E1000_ERR_CONFIG;
2977
2978        /* optimize the dsp settings for the igp phy */
2979        e1000_config_dsp_after_link_change(hw, true);
2980
2981        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
2982         * have Si on board that is 82544 or newer, Auto
2983         * Speed Detection takes care of MAC speed/duplex
2984         * configuration.  So we only need to configure Collision
2985         * Distance in the MAC.  Otherwise, we need to force
2986         * speed/duplex on the MAC to the current PHY speed/duplex
2987         * settings.
2988         */
2989        if (hw->mac_type >= e1000_82544)
2990            e1000_config_collision_dist(hw);
2991        else {
2992            ret_val = e1000_config_mac_to_phy(hw);
2993            if (ret_val) {
2994                DEBUGOUT("Error configuring MAC to PHY settings\n");
2995                return ret_val;
2996            }
2997        }
2998
2999        /* Configure Flow Control now that Auto-Neg has completed. First, we
3000         * need to restore the desired flow control settings because we may
3001         * have had to re-autoneg with a different link partner.
3002         */
3003        ret_val = e1000_config_fc_after_link_up(hw);
3004        if (ret_val) {
3005            DEBUGOUT("Error configuring flow control\n");
3006            return ret_val;
3007        }
3008
3009        /* At this point we know that we are on copper and we have
3010         * auto-negotiated link.  These are conditions for checking the link
3011         * partner capability register.  We use the link speed to determine if
3012         * TBI compatibility needs to be turned on or off.  If the link is not
3013         * at gigabit speed, then TBI compatibility is not needed.  If we are
3014         * at gigabit speed, we turn on TBI compatibility.
3015         */
3016        if (hw->tbi_compatibility_en) {
3017            u16 speed, duplex;
3018            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3019            if (ret_val) {
3020                DEBUGOUT("Error getting link speed and duplex\n");
3021                return ret_val;
3022            }
3023            if (speed != SPEED_1000) {
3024                /* If link speed is not set to gigabit speed, we do not need
3025                 * to enable TBI compatibility.
3026                 */
3027                if (hw->tbi_compatibility_on) {
3028                    /* If we previously were in the mode, turn it off. */
3029                    rctl = er32(RCTL);
3030                    rctl &= ~E1000_RCTL_SBP;
3031                    ew32(RCTL, rctl);
3032                    hw->tbi_compatibility_on = false;
3033                }
3034            } else {
3035                /* If TBI compatibility is was previously off, turn it on. For
3036                 * compatibility with a TBI link partner, we will store bad
3037                 * packets. Some frames have an additional byte on the end and
3038                 * will look like CRC errors to to the hardware.
3039                 */
3040                if (!hw->tbi_compatibility_on) {
3041                    hw->tbi_compatibility_on = true;
3042                    rctl = er32(RCTL);
3043                    rctl |= E1000_RCTL_SBP;
3044                    ew32(RCTL, rctl);
3045                }
3046            }
3047        }
3048    }
3049    /* If we don't have link (auto-negotiation failed or link partner cannot
3050     * auto-negotiate), the cable is plugged in (we have signal), and our
3051     * link partner is not trying to auto-negotiate with us (we are receiving
3052     * idles or data), we need to force link up. We also need to give
3053     * auto-negotiation time to complete, in case the cable was just plugged
3054     * in. The autoneg_failed flag does this.
3055     */
3056    else if ((((hw->media_type == e1000_media_type_fiber) &&
3057              ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3058              (hw->media_type == e1000_media_type_internal_serdes)) &&
3059              (!(status & E1000_STATUS_LU)) &&
3060              (!(rxcw & E1000_RXCW_C))) {
3061        if (hw->autoneg_failed == 0) {
3062            hw->autoneg_failed = 1;
3063            return 0;
3064        }
3065        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3066
3067        /* Disable auto-negotiation in the TXCW register */
3068        ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3069
3070        /* Force link-up and also force full-duplex. */
3071        ctrl = er32(CTRL);
3072        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3073        ew32(CTRL, ctrl);
3074
3075        /* Configure Flow Control after forcing link up. */
3076        ret_val = e1000_config_fc_after_link_up(hw);
3077        if (ret_val) {
3078            DEBUGOUT("Error configuring flow control\n");
3079            return ret_val;
3080        }
3081    }
3082    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3083     * auto-negotiation in the TXCW register and disable forced link in the
3084     * Device Control register in an attempt to auto-negotiate with our link
3085     * partner.
3086     */
3087    else if (((hw->media_type == e1000_media_type_fiber) ||
3088              (hw->media_type == e1000_media_type_internal_serdes)) &&
3089              (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3090        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3091        ew32(TXCW, hw->txcw);
3092        ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
3093
3094        hw->serdes_link_down = false;
3095    }
3096    /* If we force link for non-auto-negotiation switch, check link status
3097     * based on MAC synchronization for internal serdes media type.
3098     */
3099    else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3100             !(E1000_TXCW_ANE & er32(TXCW))) {
3101        /* SYNCH bit and IV bit are sticky. */
3102        udelay(10);
3103        if (E1000_RXCW_SYNCH & er32(RXCW)) {
3104            if (!(rxcw & E1000_RXCW_IV)) {
3105                hw->serdes_link_down = false;
3106                DEBUGOUT("SERDES: Link is up.\n");
3107            }
3108        } else {
3109            hw->serdes_link_down = true;
3110            DEBUGOUT("SERDES: Link is down.\n");
3111        }
3112    }
3113    if ((hw->media_type == e1000_media_type_internal_serdes) &&
3114        (E1000_TXCW_ANE & er32(TXCW))) {
3115        hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
3116    }
3117    return E1000_SUCCESS;
3118}
3119
3120/******************************************************************************
3121 * Detects the current speed and duplex settings of the hardware.
3122 *
3123 * hw - Struct containing variables accessed by shared code
3124 * speed - Speed of the connection
3125 * duplex - Duplex setting of the connection
3126 *****************************************************************************/
3127s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3128{
3129    u32 status;
3130    s32 ret_val;
3131    u16 phy_data;
3132
3133    DEBUGFUNC("e1000_get_speed_and_duplex");
3134
3135    if (hw->mac_type >= e1000_82543) {
3136        status = er32(STATUS);
3137        if (status & E1000_STATUS_SPEED_1000) {
3138            *speed = SPEED_1000;
3139            DEBUGOUT("1000 Mbs, ");
3140        } else if (status & E1000_STATUS_SPEED_100) {
3141            *speed = SPEED_100;
3142            DEBUGOUT("100 Mbs, ");
3143        } else {
3144            *speed = SPEED_10;
3145            DEBUGOUT("10 Mbs, ");
3146        }
3147
3148        if (status & E1000_STATUS_FD) {
3149            *duplex = FULL_DUPLEX;
3150            DEBUGOUT("Full Duplex\n");
3151        } else {
3152            *duplex = HALF_DUPLEX;
3153            DEBUGOUT(" Half Duplex\n");
3154        }
3155    } else {
3156        DEBUGOUT("1000 Mbs, Full Duplex\n");
3157        *speed = SPEED_1000;
3158        *duplex = FULL_DUPLEX;
3159    }
3160
3161    /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3162     * if it is operating at half duplex.  Here we set the duplex settings to
3163     * match the duplex in the link partner's capabilities.
3164     */
3165    if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3166        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3167        if (ret_val)
3168            return ret_val;
3169
3170        if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3171            *duplex = HALF_DUPLEX;
3172        else {
3173            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3174            if (ret_val)
3175                return ret_val;
3176            if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3177               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3178                *duplex = HALF_DUPLEX;
3179        }
3180    }
3181
3182    if ((hw->mac_type == e1000_80003es2lan) &&
3183        (hw->media_type == e1000_media_type_copper)) {
3184        if (*speed == SPEED_1000)
3185            ret_val = e1000_configure_kmrn_for_1000(hw);
3186        else
3187            ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3188        if (ret_val)
3189            return ret_val;
3190    }
3191
3192    if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3193        ret_val = e1000_kumeran_lock_loss_workaround(hw);
3194        if (ret_val)
3195            return ret_val;
3196    }
3197
3198    return E1000_SUCCESS;
3199}
3200
3201/******************************************************************************
3202* Blocks until autoneg completes or times out (~4.5 seconds)
3203*
3204* hw - Struct containing variables accessed by shared code
3205******************************************************************************/
3206static s32 e1000_wait_autoneg(struct e1000_hw *hw)
3207{
3208    s32 ret_val;
3209    u16 i;
3210    u16 phy_data;
3211
3212    DEBUGFUNC("e1000_wait_autoneg");
3213    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3214
3215    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3216    for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3217        /* Read the MII Status Register and wait for Auto-Neg
3218         * Complete bit to be set.
3219         */
3220        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3221        if (ret_val)
3222            return ret_val;
3223        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3224        if (ret_val)
3225            return ret_val;
3226        if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3227            return E1000_SUCCESS;
3228        }
3229        msleep(100);
3230    }
3231    return E1000_SUCCESS;
3232}
3233
3234/******************************************************************************
3235* Raises the Management Data Clock
3236*
3237* hw - Struct containing variables accessed by shared code
3238* ctrl - Device control register's current value
3239******************************************************************************/
3240static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3241{
3242    /* Raise the clock input to the Management Data Clock (by setting the MDC
3243     * bit), and then delay 10 microseconds.
3244     */
3245    ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
3246    E1000_WRITE_FLUSH();
3247    udelay(10);
3248}
3249
3250/******************************************************************************
3251* Lowers the Management Data Clock
3252*
3253* hw - Struct containing variables accessed by shared code
3254* ctrl - Device control register's current value
3255******************************************************************************/
3256static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3257{
3258    /* Lower the clock input to the Management Data Clock (by clearing the MDC
3259     * bit), and then delay 10 microseconds.
3260     */
3261    ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
3262    E1000_WRITE_FLUSH();
3263    udelay(10);
3264}
3265
3266/******************************************************************************
3267* Shifts data bits out to the PHY
3268*
3269* hw - Struct containing variables accessed by shared code
3270* data - Data to send out to the PHY
3271* count - Number of bits to shift out
3272*
3273* Bits are shifted out in MSB to LSB order.
3274******************************************************************************/
3275static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
3276{
3277    u32 ctrl;
3278    u32 mask;
3279
3280    /* We need to shift "count" number of bits out to the PHY. So, the value
3281     * in the "data" parameter will be shifted out to the PHY one bit at a
3282     * time. In order to do this, "data" must be broken down into bits.
3283     */
3284    mask = 0x01;
3285    mask <<= (count - 1);
3286
3287    ctrl = er32(CTRL);
3288
3289    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3290    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3291
3292    while (mask) {
3293        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3294         * then raising and lowering the Management Data Clock. A "0" is
3295         * shifted out to the PHY by setting the MDIO bit to "0" and then
3296         * raising and lowering the clock.
3297         */
3298        if (data & mask)
3299            ctrl |= E1000_CTRL_MDIO;
3300        else
3301            ctrl &= ~E1000_CTRL_MDIO;
3302
3303        ew32(CTRL, ctrl);
3304        E1000_WRITE_FLUSH();
3305
3306        udelay(10);
3307
3308        e1000_raise_mdi_clk(hw, &ctrl);
3309        e1000_lower_mdi_clk(hw, &ctrl);
3310
3311        mask = mask >> 1;
3312    }
3313}
3314
3315/******************************************************************************
3316* Shifts data bits in from the PHY
3317*
3318* hw - Struct containing variables accessed by shared code
3319*
3320* Bits are shifted in in MSB to LSB order.
3321******************************************************************************/
3322static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3323{
3324    u32 ctrl;
3325    u16 data = 0;
3326    u8 i;
3327
3328    /* In order to read a register from the PHY, we need to shift in a total
3329     * of 18 bits from the PHY. The first two bit (turnaround) times are used
3330     * to avoid contention on the MDIO pin when a read operation is performed.
3331     * These two bits are ignored by us and thrown away. Bits are "shifted in"
3332     * by raising the input to the Management Data Clock (setting the MDC bit),
3333     * and then reading the value of the MDIO bit.
3334     */
3335    ctrl = er32(CTRL);
3336
3337    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3338    ctrl &= ~E1000_CTRL_MDIO_DIR;
3339    ctrl &= ~E1000_CTRL_MDIO;
3340
3341    ew32(CTRL, ctrl);
3342    E1000_WRITE_FLUSH();
3343
3344    /* Raise and Lower the clock before reading in the data. This accounts for
3345     * the turnaround bits. The first clock occurred when we clocked out the
3346     * last bit of the Register Address.
3347     */
3348    e1000_raise_mdi_clk(hw, &ctrl);
3349    e1000_lower_mdi_clk(hw, &ctrl);
3350
3351    for (data = 0, i = 0; i < 16; i++) {
3352        data = data << 1;
3353        e1000_raise_mdi_clk(hw, &ctrl);
3354        ctrl = er32(CTRL);
3355        /* Check to see if we shifted in a "1". */
3356        if (ctrl & E1000_CTRL_MDIO)
3357            data |= 1;
3358        e1000_lower_mdi_clk(hw, &ctrl);
3359    }
3360
3361    e1000_raise_mdi_clk(hw, &ctrl);
3362    e1000_lower_mdi_clk(hw, &ctrl);
3363
3364    return data;
3365}
3366
3367static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3368{
3369    u32 swfw_sync = 0;
3370    u32 swmask = mask;
3371    u32 fwmask = mask << 16;
3372    s32 timeout = 200;
3373
3374    DEBUGFUNC("e1000_swfw_sync_acquire");
3375
3376    if (hw->swfwhw_semaphore_present)
3377        return e1000_get_software_flag(hw);
3378
3379    if (!hw->swfw_sync_present)
3380        return e1000_get_hw_eeprom_semaphore(hw);
3381
3382    while (timeout) {
3383            if (e1000_get_hw_eeprom_semaphore(hw))
3384                return -E1000_ERR_SWFW_SYNC;
3385
3386            swfw_sync = er32(SW_FW_SYNC);
3387            if (!(swfw_sync & (fwmask | swmask))) {
3388                break;
3389            }
3390
3391            /* firmware currently using resource (fwmask) */
3392            /* or other software thread currently using resource (swmask) */
3393            e1000_put_hw_eeprom_semaphore(hw);
3394            mdelay(5);
3395            timeout--;
3396    }
3397
3398    if (!timeout) {
3399        DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3400        return -E1000_ERR_SWFW_SYNC;
3401    }
3402
3403    swfw_sync |= swmask;
3404    ew32(SW_FW_SYNC, swfw_sync);
3405
3406    e1000_put_hw_eeprom_semaphore(hw);
3407    return E1000_SUCCESS;
3408}
3409
3410static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3411{
3412    u32 swfw_sync;
3413    u32 swmask = mask;
3414
3415    DEBUGFUNC("e1000_swfw_sync_release");
3416
3417    if (hw->swfwhw_semaphore_present) {
3418        e1000_release_software_flag(hw);
3419        return;
3420    }
3421
3422    if (!hw->swfw_sync_present) {
3423        e1000_put_hw_eeprom_semaphore(hw);
3424        return;
3425    }
3426
3427    /* if (e1000_get_hw_eeprom_semaphore(hw))
3428     *    return -E1000_ERR_SWFW_SYNC; */
3429    while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3430        /* empty */
3431
3432    swfw_sync = er32(SW_FW_SYNC);
3433    swfw_sync &= ~swmask;
3434    ew32(SW_FW_SYNC, swfw_sync);
3435
3436    e1000_put_hw_eeprom_semaphore(hw);
3437}
3438
3439/*****************************************************************************
3440* Reads the value from a PHY register, if the value is on a specific non zero
3441* page, sets the page first.
3442* hw - Struct containing variables accessed by shared code
3443* reg_addr - address of the PHY register to read
3444******************************************************************************/
3445s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
3446{
3447    u32 ret_val;
3448    u16 swfw;
3449
3450    DEBUGFUNC("e1000_read_phy_reg");
3451
3452    if ((hw->mac_type == e1000_80003es2lan) &&
3453        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3454        swfw = E1000_SWFW_PHY1_SM;
3455    } else {
3456        swfw = E1000_SWFW_PHY0_SM;
3457    }
3458    if (e1000_swfw_sync_acquire(hw, swfw))
3459        return -E1000_ERR_SWFW_SYNC;
3460
3461    if ((hw->phy_type == e1000_phy_igp ||
3462        hw->phy_type == e1000_phy_igp_3 ||
3463        hw->phy_type == e1000_phy_igp_2) &&
3464       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3465        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3466                                         (u16)reg_addr);
3467        if (ret_val) {
3468            e1000_swfw_sync_release(hw, swfw);
3469            return ret_val;
3470        }
3471    } else if (hw->phy_type == e1000_phy_gg82563) {
3472        if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3473            (hw->mac_type == e1000_80003es2lan)) {
3474            /* Select Configuration Page */
3475            if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3476                ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3477                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3478            } else {
3479                /* Use Alternative Page Select register to access
3480                 * registers 30 and 31
3481                 */
3482                ret_val = e1000_write_phy_reg_ex(hw,
3483                                                 GG82563_PHY_PAGE_SELECT_ALT,
3484                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3485            }
3486
3487            if (ret_val) {
3488                e1000_swfw_sync_release(hw, swfw);
3489                return ret_val;
3490            }
3491        }
3492    }
3493
3494    ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3495                                    phy_data);
3496
3497    e1000_swfw_sync_release(hw, swfw);
3498    return ret_val;
3499}
3500
3501static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3502                                 u16 *phy_data)
3503{
3504    u32 i;
3505    u32 mdic = 0;
3506    const u32 phy_addr = 1;
3507
3508    DEBUGFUNC("e1000_read_phy_reg_ex");
3509
3510    if (reg_addr > MAX_PHY_REG_ADDRESS) {
3511        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3512        return -E1000_ERR_PARAM;
3513    }
3514
3515    if (hw->mac_type > e1000_82543) {
3516        /* Set up Op-code, Phy Address, and register address in the MDI
3517         * Control register.  The MAC will take care of interfacing with the
3518         * PHY to retrieve the desired data.
3519         */
3520        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3521                (phy_addr << E1000_MDIC_PHY_SHIFT) |
3522                (E1000_MDIC_OP_READ));
3523
3524        ew32(MDIC, mdic);
3525
3526        /* Poll the ready bit to see if the MDI read completed */
3527        for (i = 0; i < 64; i++) {
3528            udelay(50);
3529            mdic = er32(MDIC);
3530            if (mdic & E1000_MDIC_READY) break;
3531        }
3532        if (!(mdic & E1000_MDIC_READY)) {
3533            DEBUGOUT("MDI Read did not complete\n");
3534            return -E1000_ERR_PHY;
3535        }
3536        if (mdic & E1000_MDIC_ERROR) {
3537            DEBUGOUT("MDI Error\n");
3538            return -E1000_ERR_PHY;
3539        }
3540        *phy_data = (u16)mdic;
3541    } else {
3542        /* We must first send a preamble through the MDIO pin to signal the
3543         * beginning of an MII instruction.  This is done by sending 32
3544         * consecutive "1" bits.
3545         */
3546        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3547
3548        /* Now combine the next few fields that are required for a read
3549         * operation.  We use this method instead of calling the
3550         * e1000_shift_out_mdi_bits routine five different times. The format of
3551         * a MII read instruction consists of a shift out of 14 bits and is
3552         * defined as follows:
3553         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3554         * followed by a shift in of 18 bits.  This first two bits shifted in
3555         * are TurnAround bits used to avoid contention on the MDIO pin when a
3556         * READ operation is performed.  These two bits are thrown away
3557         * followed by a shift in of 16 bits which contains the desired data.
3558         */
3559        mdic = ((reg_addr) | (phy_addr << 5) |
3560                (PHY_OP_READ << 10) | (PHY_SOF << 12));
3561
3562        e1000_shift_out_mdi_bits(hw, mdic, 14);
3563
3564        /* Now that we've shifted out the read command to the MII, we need to
3565         * "shift in" the 16-bit value (18 total bits) of the requested PHY
3566         * register address.
3567         */
3568        *phy_data = e1000_shift_in_mdi_bits(hw);
3569    }
3570    return E1000_SUCCESS;
3571}
3572
3573/******************************************************************************
3574* Writes a value to a PHY register
3575*
3576* hw - Struct containing variables accessed by shared code
3577* reg_addr - address of the PHY register to write
3578* data - data to write to the PHY
3579******************************************************************************/
3580s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
3581{
3582    u32 ret_val;
3583    u16 swfw;
3584
3585    DEBUGFUNC("e1000_write_phy_reg");
3586
3587    if ((hw->mac_type == e1000_80003es2lan) &&
3588        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3589        swfw = E1000_SWFW_PHY1_SM;
3590    } else {
3591        swfw = E1000_SWFW_PHY0_SM;
3592    }
3593    if (e1000_swfw_sync_acquire(hw, swfw))
3594        return -E1000_ERR_SWFW_SYNC;
3595
3596    if ((hw->phy_type == e1000_phy_igp ||
3597        hw->phy_type == e1000_phy_igp_3 ||
3598        hw->phy_type == e1000_phy_igp_2) &&
3599       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3600        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3601                                         (u16)reg_addr);
3602        if (ret_val) {
3603            e1000_swfw_sync_release(hw, swfw);
3604            return ret_val;
3605        }
3606    } else if (hw->phy_type == e1000_phy_gg82563) {
3607        if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3608            (hw->mac_type == e1000_80003es2lan)) {
3609            /* Select Configuration Page */
3610            if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3611                ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3612                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3613            } else {
3614                /* Use Alternative Page Select register to access
3615                 * registers 30 and 31
3616                 */
3617                ret_val = e1000_write_phy_reg_ex(hw,
3618                                                 GG82563_PHY_PAGE_SELECT_ALT,
3619                          (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
3620            }
3621
3622            if (ret_val) {
3623                e1000_swfw_sync_release(hw, swfw);
3624                return ret_val;
3625            }
3626        }
3627    }
3628
3629    ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3630                                     phy_data);
3631
3632    e1000_swfw_sync_release(hw, swfw);
3633    return ret_val;
3634}
3635
3636static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3637                                  u16 phy_data)
3638{
3639    u32 i;
3640    u32 mdic = 0;
3641    const u32 phy_addr = 1;
3642
3643    DEBUGFUNC("e1000_write_phy_reg_ex");
3644
3645    if (reg_addr > MAX_PHY_REG_ADDRESS) {
3646        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3647        return -E1000_ERR_PARAM;
3648    }
3649
3650    if (hw->mac_type > e1000_82543) {
3651        /* Set up Op-code, Phy Address, register address, and data intended
3652         * for the PHY register in the MDI Control register.  The MAC will take
3653         * care of interfacing with the PHY to send the desired data.
3654         */
3655        mdic = (((u32)phy_data) |
3656                (reg_addr << E1000_MDIC_REG_SHIFT) |
3657                (phy_addr << E1000_MDIC_PHY_SHIFT) |
3658                (E1000_MDIC_OP_WRITE));
3659
3660        ew32(MDIC, mdic);
3661
3662        /* Poll the ready bit to see if the MDI read completed */
3663        for (i = 0; i < 641; i++) {
3664            udelay(5);
3665            mdic = er32(MDIC);
3666            if (mdic & E1000_MDIC_READY) break;
3667        }
3668        if (!(mdic & E1000_MDIC_READY)) {
3669            DEBUGOUT("MDI Write did not complete\n");
3670            return -E1000_ERR_PHY;
3671        }
3672    } else {
3673        /* We'll need to use the SW defined pins to shift the write command
3674         * out to the PHY. We first send a preamble to the PHY to signal the
3675         * beginning of the MII instruction.  This is done by sending 32
3676         * consecutive "1" bits.
3677         */
3678        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3679
3680        /* Now combine the remaining required fields that will indicate a
3681         * write operation. We use this method instead of calling the
3682         * e1000_shift_out_mdi_bits routine for each field in the command. The
3683         * format of a MII write instruction is as follows:
3684         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3685         */
3686        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3687                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3688        mdic <<= 16;
3689        mdic |= (u32)phy_data;
3690
3691        e1000_shift_out_mdi_bits(hw, mdic, 32);
3692    }
3693
3694    return E1000_SUCCESS;
3695}
3696
3697static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
3698{
3699    u32 reg_val;
3700    u16 swfw;
3701    DEBUGFUNC("e1000_read_kmrn_reg");
3702
3703    if ((hw->mac_type == e1000_80003es2lan) &&
3704        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3705        swfw = E1000_SWFW_PHY1_SM;
3706    } else {
3707        swfw = E1000_SWFW_PHY0_SM;
3708    }
3709    if (e1000_swfw_sync_acquire(hw, swfw))
3710        return -E1000_ERR_SWFW_SYNC;
3711
3712    /* Write register address */
3713    reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3714              E1000_KUMCTRLSTA_OFFSET) |
3715              E1000_KUMCTRLSTA_REN;
3716    ew32(KUMCTRLSTA, reg_val);
3717    udelay(2);
3718
3719    /* Read the data returned */
3720    reg_val = er32(KUMCTRLSTA);
3721    *data = (u16)reg_val;
3722
3723    e1000_swfw_sync_release(hw, swfw);
3724    return E1000_SUCCESS;
3725}
3726
3727static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
3728{
3729    u32 reg_val;
3730    u16 swfw;
3731    DEBUGFUNC("e1000_write_kmrn_reg");
3732
3733    if ((hw->mac_type == e1000_80003es2lan) &&
3734        (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3735        swfw = E1000_SWFW_PHY1_SM;
3736    } else {
3737        swfw = E1000_SWFW_PHY0_SM;
3738    }
3739    if (e1000_swfw_sync_acquire(hw, swfw))
3740        return -E1000_ERR_SWFW_SYNC;
3741
3742    reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3743              E1000_KUMCTRLSTA_OFFSET) | data;
3744    ew32(KUMCTRLSTA, reg_val);
3745    udelay(2);
3746
3747    e1000_swfw_sync_release(hw, swfw);
3748    return E1000_SUCCESS;
3749}
3750
3751/******************************************************************************
3752* Returns the PHY to the power-on reset state
3753*
3754* hw - Struct containing variables accessed by shared code
3755******************************************************************************/
3756s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3757{
3758    u32 ctrl, ctrl_ext;
3759    u32 led_ctrl;
3760    s32 ret_val;
3761    u16 swfw;
3762
3763    DEBUGFUNC("e1000_phy_hw_reset");
3764
3765    /* In the case of the phy reset being blocked, it's not an error, we
3766     * simply return success without performing the reset. */
3767    ret_val = e1000_check_phy_reset_block(hw);
3768    if (ret_val)
3769        return E1000_SUCCESS;
3770
3771    DEBUGOUT("Resetting Phy...\n");
3772
3773    if (hw->mac_type > e1000_82543) {
3774        if ((hw->mac_type == e1000_80003es2lan) &&
3775            (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3776            swfw = E1000_SWFW_PHY1_SM;
3777        } else {
3778            swfw = E1000_SWFW_PHY0_SM;
3779        }
3780        if (e1000_swfw_sync_acquire(hw, swfw)) {
3781            DEBUGOUT("Unable to acquire swfw sync\n");
3782            return -E1000_ERR_SWFW_SYNC;
3783        }
3784        /* Read the device control register and assert the E1000_CTRL_PHY_RST
3785         * bit. Then, take it out of reset.
3786         * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3787         * and deassert.  For e1000_82571 hardware and later, we instead delay
3788         * for 50us between and 10ms after the deassertion.
3789         */
3790        ctrl = er32(CTRL);
3791        ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3792        E1000_WRITE_FLUSH();
3793
3794        if (hw->mac_type < e1000_82571)
3795            msleep(10);
3796        else
3797            udelay(100);
3798
3799        ew32(CTRL, ctrl);
3800        E1000_WRITE_FLUSH();
3801
3802        if (hw->mac_type >= e1000_82571)
3803            mdelay(10);
3804
3805        e1000_swfw_sync_release(hw, swfw);
3806    } else {
3807        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3808         * bit to put the PHY into reset. Then, take it out of reset.
3809         */
3810        ctrl_ext = er32(CTRL_EXT);
3811        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3812        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3813        ew32(CTRL_EXT, ctrl_ext);
3814        E1000_WRITE_FLUSH();
3815        msleep(10);
3816        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3817        ew32(CTRL_EXT, ctrl_ext);
3818        E1000_WRITE_FLUSH();
3819    }
3820    udelay(150);
3821
3822    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3823        /* Configure activity LED after PHY reset */
3824        led_ctrl = er32(LEDCTL);
3825        led_ctrl &= IGP_ACTIVITY_LED_MASK;
3826        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3827        ew32(LEDCTL, led_ctrl);
3828    }
3829
3830    /* Wait for FW to finish PHY configuration. */
3831    ret_val = e1000_get_phy_cfg_done(hw);
3832    if (ret_val != E1000_SUCCESS)
3833        return ret_val;
3834    e1000_release_software_semaphore(hw);
3835
3836    if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3837        ret_val = e1000_init_lcd_from_nvm(hw);
3838
3839    return ret_val;
3840}
3841
3842/******************************************************************************
3843* Resets the PHY
3844*
3845* hw - Struct containing variables accessed by shared code
3846*
3847* Sets bit 15 of the MII Control register
3848******************************************************************************/
3849s32 e1000_phy_reset(struct e1000_hw *hw)
3850{
3851    s32 ret_val;
3852    u16 phy_data;
3853
3854    DEBUGFUNC("e1000_phy_reset");
3855
3856    /* In the case of the phy reset being blocked, it's not an error, we
3857     * simply return success without performing the reset. */
3858    ret_val = e1000_check_phy_reset_block(hw);
3859    if (ret_val)
3860        return E1000_SUCCESS;
3861
3862    switch (hw->phy_type) {
3863    case e1000_phy_igp:
3864    case e1000_phy_igp_2:
3865    case e1000_phy_igp_3:
3866    case e1000_phy_ife:
3867        ret_val = e1000_phy_hw_reset(hw);
3868        if (ret_val)
3869            return ret_val;
3870        break;
3871    default:
3872        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3873        if (ret_val)
3874            return ret_val;
3875
3876        phy_data |= MII_CR_RESET;
3877        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3878        if (ret_val)
3879            return ret_val;
3880
3881        udelay(1);
3882        break;
3883    }
3884
3885    if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3886        e1000_phy_init_script(hw);
3887
3888    return E1000_SUCCESS;
3889}
3890
3891/******************************************************************************
3892* Work-around for 82566 power-down: on D3 entry-
3893* 1) disable gigabit link
3894* 2) write VR power-down enable
3895* 3) read it back
3896* if successful continue, else issue LCD reset and repeat
3897*
3898* hw - struct containing variables accessed by shared code
3899******************************************************************************/
3900void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3901{
3902    s32 reg;
3903    u16 phy_data;
3904    s32 retry = 0;
3905
3906    DEBUGFUNC("e1000_phy_powerdown_workaround");
3907
3908    if (hw->phy_type != e1000_phy_igp_3)
3909        return;
3910
3911    do {
3912        /* Disable link */
3913        reg = er32(PHY_CTRL);
3914        ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3915                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3916
3917        /* Write VR power-down enable - bits 9:8 should be 10b */
3918        e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3919        phy_data |= (1 << 9);
3920        phy_data &= ~(1 << 8);
3921        e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3922
3923        /* Read it back and test */
3924        e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3925        if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3926            break;
3927
3928        /* Issue PHY reset and repeat at most one more time */
3929        reg = er32(CTRL);
3930        ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3931        retry++;
3932    } while (retry);
3933
3934    return;
3935
3936}
3937
3938/******************************************************************************
3939* Work-around for 82566 Kumeran PCS lock loss:
3940* On link status change (i.e. PCI reset, speed change) and link is up and
3941* speed is gigabit-
3942* 0) if workaround is optionally disabled do nothing
3943* 1) wait 1ms for Kumeran link to come up
3944* 2) check Kumeran Diagnostic register PCS lock loss bit
3945* 3) if not set the link is locked (all is good), otherwise...
3946* 4) reset the PHY
3947* 5) repeat up to 10 times
3948* Note: this is only called for IGP3 copper when speed is 1gb.
3949*
3950* hw - struct containing variables accessed by shared code
3951******************************************************************************/
3952static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3953{
3954    s32 ret_val;
3955    s32 reg;
3956    s32 cnt;
3957    u16 phy_data;
3958
3959    if (hw->kmrn_lock_loss_workaround_disabled)
3960        return E1000_SUCCESS;
3961
3962    /* Make sure link is up before proceeding.  If not just return.
3963     * Attempting this while link is negotiating fouled up link
3964     * stability */
3965    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3966    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3967
3968    if (phy_data & MII_SR_LINK_STATUS) {
3969        for (cnt = 0; cnt < 10; cnt++) {
3970            /* read once to clear */
3971            ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3972            if (ret_val)
3973                return ret_val;
3974            /* and again to get new status */
3975            ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3976            if (ret_val)
3977                return ret_val;
3978
3979            /* check for PCS lock */
3980            if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3981                return E1000_SUCCESS;
3982
3983            /* Issue PHY reset */
3984            e1000_phy_hw_reset(hw);
3985            mdelay(5);
3986        }
3987        /* Disable GigE link negotiation */
3988        reg = er32(PHY_CTRL);
3989        ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3990                        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3991
3992        /* unable to acquire PCS lock */
3993        return E1000_ERR_PHY;
3994    }
3995
3996    return E1000_SUCCESS;
3997}
3998
3999/******************************************************************************
4000* Probes the expected PHY address for known PHY IDs
4001*
4002* hw - Struct containing variables accessed by shared code
4003******************************************************************************/
4004static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
4005{
4006    s32 phy_init_status, ret_val;
4007    u16 phy_id_high, phy_id_low;
4008    bool match = false;
4009
4010    DEBUGFUNC("e1000_detect_gig_phy");
4011
4012    if (hw->phy_id != 0)
4013        return E1000_SUCCESS;
4014
4015    /* The 82571 firmware may still be configuring the PHY.  In this
4016     * case, we cannot access the PHY until the configuration is done.  So
4017     * we explicitly set the PHY values. */
4018    if (hw->mac_type == e1000_82571 ||
4019        hw->mac_type == e1000_82572) {
4020        hw->phy_id = IGP01E1000_I_PHY_ID;
4021        hw->phy_type = e1000_phy_igp_2;
4022        return E1000_SUCCESS;
4023    }
4024
4025    /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4026     * around that forces PHY page 0 to be set or the reads fail.  The rest of
4027     * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4028     * So for ESB-2 we need to have this set so our reads won't fail.  If the
4029     * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4030     * this out as well. */
4031    if (hw->mac_type == e1000_80003es2lan)
4032        hw->phy_type = e1000_phy_gg82563;
4033
4034    /* Read the PHY ID Registers to identify which PHY is onboard. */
4035    ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4036    if (ret_val)
4037        return ret_val;
4038
4039    hw->phy_id = (u32)(phy_id_high << 16);
4040    udelay(20);
4041    ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4042    if (ret_val)
4043        return ret_val;
4044
4045    hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
4046    hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
4047
4048    switch (hw->mac_type) {
4049    case e1000_82543:
4050        if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
4051        break;
4052    case e1000_82544:
4053        if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
4054        break;
4055    case e1000_82540:
4056    case e1000_82545:
4057    case e1000_82545_rev_3:
4058    case e1000_82546:
4059    case e1000_82546_rev_3:
4060        if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
4061        break;
4062    case e1000_82541:
4063    case e1000_82541_rev_2:
4064    case e1000_82547:
4065    case e1000_82547_rev_2:
4066        if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
4067        break;
4068    case e1000_82573:
4069        if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
4070        break;
4071    case e1000_80003es2lan:
4072        if (hw->phy_id == GG82563_E_PHY_ID) match = true;
4073        break;
4074    case e1000_ich8lan:
4075        if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
4076        if (hw->phy_id == IFE_E_PHY_ID) match = true;
4077        if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
4078        if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
4079        break;
4080    default:
4081        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4082        return -E1000_ERR_CONFIG;
4083    }
4084    phy_init_status = e1000_set_phy_type(hw);
4085
4086    if ((match) && (phy_init_status == E1000_SUCCESS)) {
4087        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4088        return E1000_SUCCESS;
4089    }
4090    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4091    return -E1000_ERR_PHY;
4092}
4093
4094/******************************************************************************
4095* Resets the PHY's DSP
4096*
4097* hw - Struct containing variables accessed by shared code
4098******************************************************************************/
4099static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
4100{
4101    s32 ret_val;
4102    DEBUGFUNC("e1000_phy_reset_dsp");
4103
4104    do {
4105        if (hw->phy_type != e1000_phy_gg82563) {
4106            ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4107            if (ret_val) break;
4108        }
4109        ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4110        if (ret_val) break;
4111        ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4112        if (ret_val) break;
4113        ret_val = E1000_SUCCESS;
4114    } while (0);
4115
4116    return ret_val;
4117}
4118
4119/******************************************************************************
4120* Get PHY information from various PHY registers for igp PHY only.
4121*
4122* hw - Struct containing variables accessed by shared code
4123* phy_info - PHY information structure
4124******************************************************************************/
4125static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
4126                                  struct e1000_phy_info *phy_info)
4127{
4128    s32 ret_val;
4129    u16 phy_data, min_length, max_length, average;
4130    e1000_rev_polarity polarity;
4131
4132    DEBUGFUNC("e1000_phy_igp_get_info");
4133
4134    /* The downshift status is checked only once, after link is established,
4135     * and it stored in the hw->speed_downgraded parameter. */
4136    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4137
4138    /* IGP01E1000 does not need to support it. */
4139    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4140
4141    /* IGP01E1000 always correct polarity reversal */
4142    phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4143
4144    /* Check polarity status */
4145    ret_val = e1000_check_polarity(hw, &polarity);
4146    if (ret_val)
4147        return ret_val;
4148
4149    phy_info->cable_polarity = polarity;
4150
4151    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4152    if (ret_val)
4153        return ret_val;
4154
4155    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4156                          IGP01E1000_PSSR_MDIX_SHIFT);
4157
4158    if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4159       IGP01E1000_PSSR_SPEED_1000MBPS) {
4160        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4161        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4162        if (ret_val)
4163            return ret_val;
4164
4165        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4166                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4167                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4168        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4169                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4170                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4171
4172        /* Get cable length */
4173        ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4174        if (ret_val)
4175            return ret_val;
4176
4177        /* Translate to old method */
4178        average = (max_length + min_length) / 2;
4179
4180        if (average <= e1000_igp_cable_length_50)
4181            phy_info->cable_length = e1000_cable_length_50;
4182        else if (average <= e1000_igp_cable_length_80)
4183            phy_info->cable_length = e1000_cable_length_50_80;
4184        else if (average <= e1000_igp_cable_length_110)
4185            phy_info->cable_length = e1000_cable_length_80_110;
4186        else if (average <= e1000_igp_cable_length_140)
4187            phy_info->cable_length = e1000_cable_length_110_140;
4188        else
4189            phy_info->cable_length = e1000_cable_length_140;
4190    }
4191
4192    return E1000_SUCCESS;
4193}
4194
4195/******************************************************************************
4196* Get PHY information from various PHY registers for ife PHY only.
4197*
4198* hw - Struct containing variables accessed by shared code
4199* phy_info - PHY information structure
4200******************************************************************************/
4201static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
4202                                  struct e1000_phy_info *phy_info)
4203{
4204    s32 ret_val;
4205    u16 phy_data;
4206    e1000_rev_polarity polarity;
4207
4208    DEBUGFUNC("e1000_phy_ife_get_info");
4209
4210    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4211    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4212
4213    ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4214    if (ret_val)
4215        return ret_val;
4216    phy_info->polarity_correction =
4217                        ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4218                        IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4219                        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4220
4221    if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4222        ret_val = e1000_check_polarity(hw, &polarity);
4223        if (ret_val)
4224            return ret_val;
4225    } else {
4226        /* Polarity is forced. */
4227        polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4228                     IFE_PSC_FORCE_POLARITY_SHIFT) ?
4229                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4230    }
4231    phy_info->cable_polarity = polarity;
4232
4233    ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4234    if (ret_val)
4235        return ret_val;
4236
4237    phy_info->mdix_mode = (e1000_auto_x_mode)
4238                     ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4239                     IFE_PMC_MDIX_MODE_SHIFT);
4240
4241    return E1000_SUCCESS;
4242}
4243
4244/******************************************************************************
4245* Get PHY information from various PHY registers fot m88 PHY only.
4246*
4247* hw - Struct containing variables accessed by shared code
4248* phy_info - PHY information structure
4249******************************************************************************/
4250static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
4251                                  struct e1000_phy_info *phy_info)
4252{
4253    s32 ret_val;
4254    u16 phy_data;
4255    e1000_rev_polarity polarity;
4256
4257    DEBUGFUNC("e1000_phy_m88_get_info");
4258
4259    /* The downshift status is checked only once, after link is established,
4260     * and it stored in the hw->speed_downgraded parameter. */
4261    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4262
4263    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4264    if (ret_val)
4265        return ret_val;
4266
4267    phy_info->extended_10bt_distance =
4268        ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4269        M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4270        e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4271
4272    phy_info->polarity_correction =
4273        ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4274        M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4275        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4276
4277    /* Check polarity status */
4278    ret_val = e1000_check_polarity(hw, &polarity);
4279    if (ret_val)
4280        return ret_val;
4281    phy_info->cable_polarity = polarity;
4282
4283    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4284    if (ret_val)
4285        return ret_val;
4286
4287    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4288                          M88E1000_PSSR_MDIX_SHIFT);
4289
4290    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4291        /* Cable Length Estimation and Local/Remote Receiver Information
4292         * are only valid at 1000 Mbps.
4293         */
4294        if (hw->phy_type != e1000_phy_gg82563) {
4295            phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4296                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4297        } else {
4298            ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4299                                         &phy_data);
4300            if (ret_val)
4301                return ret_val;
4302
4303            phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4304        }
4305
4306        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4307        if (ret_val)
4308            return ret_val;
4309
4310        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4311                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4312                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4313        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4314                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4315                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4316
4317    }
4318
4319    return E1000_SUCCESS;
4320}
4321
4322/******************************************************************************
4323* Get PHY information from various PHY registers
4324*
4325* hw - Struct containing variables accessed by shared code
4326* phy_info - PHY information structure
4327******************************************************************************/
4328s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
4329{
4330    s32 ret_val;
4331    u16 phy_data;
4332
4333    DEBUGFUNC("e1000_phy_get_info");
4334
4335    phy_info->cable_length = e1000_cable_length_undefined;
4336    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4337    phy_info->cable_polarity = e1000_rev_polarity_undefined;
4338    phy_info->downshift = e1000_downshift_undefined;
4339    phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4340    phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4341    phy_info->local_rx = e1000_1000t_rx_status_undefined;
4342    phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4343
4344    if (hw->media_type != e1000_media_type_copper) {
4345        DEBUGOUT("PHY info is only valid for copper media\n");
4346        return -E1000_ERR_CONFIG;
4347    }
4348
4349    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4350    if (ret_val)
4351        return ret_val;
4352
4353    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4354    if (ret_val)
4355        return ret_val;
4356
4357    if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4358        DEBUGOUT("PHY info is only valid if link is up\n");
4359        return -E1000_ERR_CONFIG;
4360    }
4361
4362    if (hw->phy_type == e1000_phy_igp ||
4363        hw->phy_type == e1000_phy_igp_3 ||
4364        hw->phy_type == e1000_phy_igp_2)
4365        return e1000_phy_igp_get_info(hw, phy_info);
4366    else if (hw->phy_type == e1000_phy_ife)
4367        return e1000_phy_ife_get_info(hw, phy_info);
4368    else
4369        return e1000_phy_m88_get_info(hw, phy_info);
4370}
4371
4372s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
4373{
4374    DEBUGFUNC("e1000_validate_mdi_settings");
4375
4376    if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4377        DEBUGOUT("Invalid MDI setting detected\n");
4378        hw->mdix = 1;
4379        return -E1000_ERR_CONFIG;
4380    }
4381    return E1000_SUCCESS;
4382}
4383
4384
4385/******************************************************************************
4386 * Sets up eeprom variables in the hw struct.  Must be called after mac_type
4387 * is configured.  Additionally, if this is ICH8, the flash controller GbE
4388 * registers must be mapped, or this will crash.
4389 *
4390 * hw - Struct containing variables accessed by shared code
4391 *****************************************************************************/
4392s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4393{
4394    struct e1000_eeprom_info *eeprom = &hw->eeprom;
4395    u32 eecd = er32(EECD);
4396    s32 ret_val = E1000_SUCCESS;
4397    u16 eeprom_size;
4398
4399    DEBUGFUNC("e1000_init_eeprom_params");
4400
4401    switch (hw->mac_type) {
4402    case e1000_82542_rev2_0:
4403    case e1000_82542_rev2_1:
4404    case e1000_82543:
4405    case e1000_82544:
4406        eeprom->type = e1000_eeprom_microwire;
4407        eeprom->word_size = 64;
4408        eeprom->opcode_bits = 3;
4409        eeprom->address_bits = 6;
4410        eeprom->delay_usec = 50;
4411        eeprom->use_eerd = false;
4412        eeprom->use_eewr = false;
4413        break;
4414    case e1000_82540:
4415    case e1000_82545:
4416    case e1000_82545_rev_3:
4417    case e1000_82546:
4418    case e1000_82546_rev_3:
4419        eeprom->type = e1000_eeprom_microwire;
4420        eeprom->opcode_bits = 3;
4421        eeprom->delay_usec = 50;
4422        if (eecd & E1000_EECD_SIZE) {
4423            eeprom->word_size = 256;
4424            eeprom->address_bits = 8;
4425        } else {
4426            eeprom->word_size = 64;
4427            eeprom->address_bits = 6;
4428        }
4429        eeprom->use_eerd = false;
4430        eeprom->use_eewr = false;
4431        break;
4432    case e1000_82541:
4433    case e1000_82541_rev_2:
4434    case e1000_82547:
4435    case e1000_82547_rev_2:
4436        if (eecd & E1000_EECD_TYPE) {
4437            eeprom->type = e1000_eeprom_spi;
4438            eeprom->opcode_bits = 8;
4439            eeprom->delay_usec = 1;
4440            if (eecd & E1000_EECD_ADDR_BITS) {
4441                eeprom->page_size = 32;
4442                eeprom->address_bits = 16;
4443            } else {
4444                eeprom->page_size = 8;
4445                eeprom->address_bits = 8;
4446            }
4447        } else {
4448            eeprom->type = e1000_eeprom_microwire;
4449            eeprom->opcode_bits = 3;
4450            eeprom->delay_usec = 50;
4451            if (eecd & E1000_EECD_ADDR_BITS) {
4452                eeprom->word_size = 256;
4453                eeprom->address_bits = 8;
4454            } else {
4455                eeprom->word_size = 64;
4456                eeprom->address_bits = 6;
4457            }
4458        }
4459        eeprom->use_eerd = false;
4460        eeprom->use_eewr = false;
4461        break;
4462    case e1000_82571:
4463    case e1000_82572:
4464        eeprom->type = e1000_eeprom_spi;
4465        eeprom->opcode_bits = 8;
4466        eeprom->delay_usec = 1;
4467        if (eecd & E1000_EECD_ADDR_BITS) {
4468            eeprom->page_size = 32;
4469            eeprom->address_bits = 16;
4470        } else {
4471            eeprom->page_size = 8;
4472            eeprom->address_bits = 8;
4473        }
4474        eeprom->use_eerd = false;
4475        eeprom->use_eewr = false;
4476        break;
4477    case e1000_82573:
4478        eeprom->type = e1000_eeprom_spi;
4479        eeprom->opcode_bits = 8;
4480        eeprom->delay_usec = 1;
4481        if (eecd & E1000_EECD_ADDR_BITS) {
4482            eeprom->page_size = 32;
4483            eeprom->address_bits = 16;
4484        } else {
4485            eeprom->page_size = 8;
4486            eeprom->address_bits = 8;
4487        }
4488        eeprom->use_eerd = true;
4489        eeprom->use_eewr = true;
4490        if (!e1000_is_onboard_nvm_eeprom(hw)) {
4491            eeprom->type = e1000_eeprom_flash;
4492            eeprom->word_size = 2048;
4493
4494            /* Ensure that the Autonomous FLASH update bit is cleared due to
4495             * Flash update issue on parts which use a FLASH for NVM. */
4496            eecd &= ~E1000_EECD_AUPDEN;
4497            ew32(EECD, eecd);
4498        }
4499        break;
4500    case e1000_80003es2lan:
4501        eeprom->type = e1000_eeprom_spi;
4502        eeprom->opcode_bits = 8;
4503        eeprom->delay_usec = 1;
4504        if (eecd & E1000_EECD_ADDR_BITS) {
4505            eeprom->page_size = 32;
4506            eeprom->address_bits = 16;
4507        } else {
4508            eeprom->page_size = 8;
4509            eeprom->address_bits = 8;
4510        }
4511        eeprom->use_eerd = true;
4512        eeprom->use_eewr = false;
4513        break;
4514    case e1000_ich8lan:
4515        {
4516        s32  i = 0;
4517        u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4518
4519        eeprom->type = e1000_eeprom_ich8;
4520        eeprom->use_eerd = false;
4521        eeprom->use_eewr = false;
4522        eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4523
4524        /* Zero the shadow RAM structure. But don't load it from NVM
4525         * so as to save time for driver init */
4526        if (hw->eeprom_shadow_ram != NULL) {
4527            for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4528                hw->eeprom_shadow_ram[i].modified = false;
4529                hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4530            }
4531        }
4532
4533        hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4534                              ICH_FLASH_SECTOR_SIZE;
4535
4536        hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4537        hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4538
4539        hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4540
4541        hw->flash_bank_size /= 2 * sizeof(u16);
4542
4543        break;
4544        }
4545    default:
4546        break;
4547    }
4548
4549    if (eeprom->type == e1000_eeprom_spi) {
4550        /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4551         * 32KB (incremented by powers of 2).
4552         */
4553        if (hw->mac_type <= e1000_82547_rev_2) {
4554            /* Set to default value for initial eeprom read. */
4555            eeprom->word_size = 64;
4556            ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4557            if (ret_val)
4558                return ret_val;
4559            eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4560            /* 256B eeprom size was not supported in earlier hardware, so we
4561             * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4562             * is never the result used in the shifting logic below. */
4563            if (eeprom_size)
4564                eeprom_size++;
4565        } else {
4566            eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4567                          E1000_EECD_SIZE_EX_SHIFT);
4568        }
4569
4570        eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4571    }
4572    return ret_val;
4573}
4574
4575/******************************************************************************
4576 * Raises the EEPROM's clock input.
4577 *
4578 * hw - Struct containing variables accessed by shared code
4579 * eecd - EECD's current value
4580 *****************************************************************************/
4581static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
4582{
4583    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4584     * wait <delay> microseconds.
4585     */
4586    *eecd = *eecd | E1000_EECD_SK;
4587    ew32(EECD, *eecd);
4588    E1000_WRITE_FLUSH();
4589    udelay(hw->eeprom.delay_usec);
4590}
4591
4592/******************************************************************************
4593 * Lowers the EEPROM's clock input.
4594 *
4595 * hw - Struct containing variables accessed by shared code
4596 * eecd - EECD's current value
4597 *****************************************************************************/
4598static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
4599{
4600    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4601     * wait 50 microseconds.
4602     */
4603    *eecd = *eecd & ~E1000_EECD_SK;
4604    ew32(EECD, *eecd);
4605    E1000_WRITE_FLUSH();
4606    udelay(hw->eeprom.delay_usec);
4607}
4608
4609/******************************************************************************
4610 * Shift data bits out to the EEPROM.
4611 *
4612 * hw - Struct containing variables accessed by shared code
4613 * data - data to send to the EEPROM
4614 * count - number of bits to shift out
4615 *****************************************************************************/
4616static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4617{
4618    struct e1000_eeprom_info *eeprom = &hw->eeprom;
4619    u32 eecd;
4620    u32 mask;
4621
4622    /* We need to shift "count" bits out to the EEPROM. So, value in the
4623     * "data" parameter will be shifted out to the EEPROM one bit at a time.
4624     * In order to do this, "data" must be broken down into bits.
4625     */
4626    mask = 0x01 << (count - 1);
4627    eecd = er32(EECD);
4628    if (eeprom->type == e1000_eeprom_microwire) {
4629        eecd &= ~E1000_EECD_DO;
4630    } else if (eeprom->type == e1000_eeprom_spi) {
4631        eecd |= E1000_EECD_DO;
4632    }
4633    do {
4634        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4635         * and then raising and then lowering the clock (the SK bit controls
4636         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
4637         * by setting "DI" to "0" and then raising and then lowering the clock.
4638         */
4639        eecd &= ~E1000_EECD_DI;
4640
4641        if (data & mask)
4642            eecd |= E1000_EECD_DI;
4643
4644        ew32(EECD, eecd);
4645        E1000_WRITE_FLUSH();
4646
4647        udelay(eeprom->delay_usec);
4648
4649        e1000_raise_ee_clk(hw, &eecd);
4650        e1000_lower_ee_clk(hw, &eecd);
4651
4652        mask = mask >> 1;
4653
4654    } while (mask);
4655
4656    /* We leave the "DI" bit set to "0" when we leave this routine. */
4657    eecd &= ~E1000_EECD_DI;
4658    ew32(EECD, eecd);
4659}
4660
4661/******************************************************************************
4662 * Shift data bits in from the EEPROM
4663 *
4664 * hw - Struct containing variables accessed by shared code
4665 *****************************************************************************/
4666static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
4667{
4668    u32 eecd;
4669    u32 i;
4670    u16 data;
4671
4672    /* In order to read a register from the EEPROM, we need to shift 'count'
4673     * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4674     * input to the EEPROM (setting the SK bit), and then reading the value of
4675     * the "DO" bit.  During this "shifting in" process the "DI" bit should
4676     * always be clear.
4677     */
4678
4679    eecd = er32(EECD);
4680
4681    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4682    data = 0;
4683
4684    for (i = 0; i < count; i++) {
4685        data = data << 1;
4686        e1000_raise_ee_clk(hw, &eecd);
4687
4688        eecd = er32(EECD);
4689
4690        eecd &= ~(E1000_EECD_DI);
4691        if (eecd & E1000_EECD_DO)
4692            data |= 1;
4693
4694        e1000_lower_ee_clk(hw, &eecd);
4695    }
4696
4697    return data;
4698}
4699
4700/******************************************************************************
4701 * Prepares EEPROM for access
4702 *
4703 * hw - Struct containing variables accessed by shared code
4704 *
4705 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4706 * function should be called before issuing a command to the EEPROM.
4707 *****************************************************************************/
4708static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4709{
4710    struct e1000_eeprom_info *eeprom = &hw->eeprom;
4711    u32 eecd, i=0;
4712
4713    DEBUGFUNC("e1000_acquire_eeprom");
4714
4715    if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4716        return -E1000_ERR_SWFW_SYNC;
4717    eecd = er32(EECD);
4718
4719    if (hw->mac_type != e1000_82573) {
4720        /* Request EEPROM Access */
4721        if (hw->mac_type > e1000_82544) {
4722            eecd |= E1000_EECD_REQ;
4723            ew32(EECD, eecd);
4724            eecd = er32(EECD);
4725            while ((!(eecd & E1000_EECD_GNT)) &&
4726                  (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4727                i++;
4728                udelay(5);
4729                eecd = er32(EECD);
4730            }
4731            if (!(eecd & E1000_EECD_GNT)) {
4732                eecd &= ~E1000_EECD_REQ;
4733                ew32(EECD, eecd);
4734                DEBUGOUT("Could not acquire EEPROM grant\n");
4735                e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4736                return -E1000_ERR_EEPROM;
4737            }
4738        }
4739    }
4740
4741    /* Setup EEPROM for Read/Write */
4742
4743    if (eeprom->type == e1000_eeprom_microwire) {
4744        /* Clear SK and DI */
4745        eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4746        ew32(EECD, eecd);
4747
4748        /* Set CS */
4749        eecd |= E1000_EECD_CS;
4750        ew32(EECD, eecd);
4751    } else if (eeprom->type == e1000_eeprom_spi) {
4752        /* Clear SK and CS */
4753        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4754        ew32(EECD, eecd);
4755        udelay(1);
4756    }
4757
4758    return E1000_SUCCESS;
4759}
4760
4761/******************************************************************************
4762 * Returns EEPROM to a "standby" state
4763 *
4764 * hw - Struct containing variables accessed by shared code
4765 *****************************************************************************/
4766static void e1000_standby_eeprom(struct e1000_hw *hw)
4767{
4768    struct e1000_eeprom_info *eeprom = &hw->eeprom;
4769    u32 eecd;
4770
4771    eecd = er32(EECD);
4772
4773    if (eeprom->type == e1000_eeprom_microwire) {
4774        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4775        ew32(EECD, eecd);
4776        E1000_WRITE_FLUSH();
4777        udelay(eeprom->delay_usec);
4778
4779        /* Clock high */
4780        eecd |= E1000_EECD_SK;
4781        ew32(EECD, eecd);
4782        E1000_WRITE_FLUSH();
4783        udelay(eeprom->delay_usec);
4784
4785        /* Select EEPROM */
4786        eecd |= E1000_EECD_CS;
4787        ew32(EECD, eecd);
4788        E1000_WRITE_FLUSH();
4789        udelay(eeprom->delay_usec);
4790
4791        /* Clock low */
4792        eecd &= ~E1000_EECD_SK;
4793        ew32(EECD, eecd);
4794        E1000_WRITE_FLUSH();
4795        udelay(eeprom->delay_usec);
4796    } else if (eeprom->type == e1000_eeprom_spi) {
4797        /* Toggle CS to flush commands */
4798        eecd |= E1000_EECD_CS;
4799        ew32(EECD, eecd);
4800        E1000_WRITE_FLUSH();
4801        udelay(eeprom->delay_usec);
4802        eecd &= ~E1000_EECD_CS;
4803        ew32(EECD, eecd);
4804        E1000_WRITE_FLUSH();
4805        udelay(eeprom->delay_usec);
4806    }
4807}
4808
4809/******************************************************************************
4810 * Terminates a command by inverting the EEPROM's chip select pin
4811 *
4812 * hw - Struct containing variables accessed by shared code
4813 *****************************************************************************/
4814static void e1000_release_eeprom(struct e1000_hw *hw)
4815{
4816    u32 eecd;
4817
4818    DEBUGFUNC("e1000_release_eeprom");
4819
4820    eecd = er32(EECD);
4821
4822    if (hw->eeprom.type == e1000_eeprom_spi) {
4823        eecd |= E1000_EECD_CS;  /* Pull CS high */
4824        eecd &= ~E1000_EECD_SK; /* Lower SCK */
4825
4826        ew32(EECD, eecd);
4827
4828        udelay(hw->eeprom.delay_usec);
4829    } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4830        /* cleanup eeprom */
4831
4832        /* CS on Microwire is active-high */
4833        eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4834
4835        ew32(EECD, eecd);
4836
4837        /* Rising edge of clock */
4838        eecd |= E1000_EECD_SK;
4839        ew32(EECD, eecd);
4840        E1000_WRITE_FLUSH();
4841        udelay(hw->eeprom.delay_usec);
4842
4843        /* Falling edge of clock */
4844        eecd &= ~E1000_EECD_SK;
4845        ew32(EECD, eecd);
4846        E1000_WRITE_FLUSH();
4847        udelay(hw->eeprom.delay_usec);
4848    }
4849
4850    /* Stop requesting EEPROM access */
4851    if (hw->mac_type > e1000_82544) {
4852        eecd &= ~E1000_EECD_REQ;
4853        ew32(EECD, eecd);
4854    }
4855
4856    e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4857}
4858
4859/******************************************************************************
4860 * Reads a 16 bit word from the EEPROM.
4861 *
4862 * hw - Struct containing variables accessed by shared code
4863 *****************************************************************************/
4864static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4865{
4866    u16 retry_count = 0;
4867    u8 spi_stat_reg;
4868
4869    DEBUGFUNC("e1000_spi_eeprom_ready");
4870
4871    /* Read "Status Register" repeatedly until the LSB is cleared.  The
4872     * EEPROM will signal that the command has been completed by clearing
4873     * bit 0 of the internal status register.  If it's not cleared within
4874     * 5 milliseconds, then error out.
4875     */
4876    retry_count = 0;
4877    do {
4878        e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4879                                hw->eeprom.opcode_bits);
4880        spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
4881        if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4882            break;
4883
4884        udelay(5);
4885        retry_count += 5;
4886
4887        e1000_standby_eeprom(hw);
4888    } while (retry_count < EEPROM_MAX_RETRY_SPI);
4889
4890    /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4891     * only 0-5mSec on 5V devices)
4892     */
4893    if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4894        DEBUGOUT("SPI EEPROM Status error\n");
4895        return -E1000_ERR_EEPROM;
4896    }
4897
4898    return E1000_SUCCESS;
4899}
4900
4901/******************************************************************************
4902 * Reads a 16 bit word from the EEPROM.
4903 *
4904 * hw - Struct containing variables accessed by shared code
4905 * offset - offset of  word in the EEPROM to read
4906 * data - word read from the EEPROM
4907 * words - number of words to read
4908 *****************************************************************************/
4909s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4910{
4911    s32 ret;
4912    spin_lock(&e1000_eeprom_lock);
4913    ret = e1000_do_read_eeprom(hw, offset, words, data);
4914    spin_unlock(&e1000_eeprom_lock);
4915    return ret;
4916}
4917
4918static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4919{
4920    struct e1000_eeprom_info *eeprom = &hw->eeprom;
4921    u32 i = 0;
4922
4923    DEBUGFUNC("e1000_read_eeprom");
4924
4925    /* If eeprom is not yet detected, do so now */
4926    if (eeprom->word_size == 0)
4927        e1000_init_eeprom_params(hw);
4928
4929    /* A check for invalid values:  offset too large, too many words, and not
4930     * enough words.
4931     */
4932    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4933       (words == 0)) {
4934        DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4935        return -E1000_ERR_EEPROM;
4936    }
4937
4938    /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4939     * directly. In this case, we need to acquire the EEPROM so that
4940     * FW or other port software does not interrupt.
4941     */
4942    if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
4943        /* Prepare the EEPROM for bit-bang reading */
4944        if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4945            return -E1000_ERR_EEPROM;
4946    }
4947
4948    /* Eerd register EEPROM access requires no eeprom aquire/release */
4949    if (eeprom->use_eerd)
4950        return e1000_read_eeprom_eerd(hw, offset, words, data);
4951
4952    /* ICH EEPROM access is done via the ICH flash controller */
4953    if (eeprom->type == e1000_eeprom_ich8)
4954        return e1000_read_eeprom_ich8(hw, offset, words, data);
4955
4956    /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
4957     * acquired the EEPROM at this point, so any returns should relase it */
4958    if (eeprom->type == e1000_eeprom_spi) {
4959        u16 word_in;
4960        u8 read_opcode = EEPROM_READ_OPCODE_SPI;
4961
4962        if (e1000_spi_eeprom_ready(hw)) {
4963            e1000_release_eeprom(hw);
4964            return -E1000_ERR_EEPROM;
4965        }
4966
4967        e1000_standby_eeprom(hw);
4968
4969        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4970        if ((eeprom->address_bits == 8) && (offset >= 128))
4971            read_opcode |= EEPROM_A8_OPCODE_SPI;
4972
4973        /* Send the READ command (opcode + addr)  */
4974        e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4975        e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
4976
4977        /* Read the data.  The address of the eeprom internally increments with
4978         * each byte (spi) being read, saving on the overhead of eeprom setup
4979         * and tear-down.  The address counter will roll over if reading beyond
4980         * the size of the eeprom, thus allowing the entire memory to be read
4981         * starting from any offset. */
4982        for (i = 0; i < words; i++) {
4983            word_in = e1000_shift_in_ee_bits(hw, 16);
4984            data[i] = (word_in >> 8) | (word_in << 8);
4985        }
4986    } else if (eeprom->type == e1000_eeprom_microwire) {
4987        for (i = 0; i < words; i++) {
4988            /* Send the READ command (opcode + addr)  */
4989            e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4990                                    eeprom->opcode_bits);
4991            e1000_shift_out_ee_bits(hw, (u16)(offset + i),
4992                                    eeprom->address_bits);
4993
4994            /* Read the data.  For microwire, each word requires the overhead
4995             * of eeprom setup and tear-down. */
4996            data[i] = e1000_shift_in_ee_bits(hw, 16);
4997            e1000_standby_eeprom(hw);
4998        }
4999    }
5000
5001    /* End this read operation */
5002    e1000_release_eeprom(hw);
5003
5004    return E1000_SUCCESS;
5005}
5006
5007/******************************************************************************
5008 * Reads a 16 bit word from the EEPROM using the EERD register.
5009 *
5010 * hw - Struct containing variables accessed by shared code
5011 * offset - offset of  word in the EEPROM to read
5012 * data - word read from the EEPROM
5013 * words - number of words to read
5014 *****************************************************************************/
5015static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
5016                                  u16 *data)
5017{
5018    u32 i, eerd = 0;
5019    s32 error = 0;
5020
5021    for (i = 0; i < words; i++) {
5022        eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5023                         E1000_EEPROM_RW_REG_START;
5024
5025        ew32(EERD, eerd);
5026        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5027
5028        if (error) {
5029            break;
5030        }
5031        data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
5032
5033    }
5034
5035    return error;
5036}
5037
5038/******************************************************************************
5039 * Writes a 16 bit word from the EEPROM using the EEWR register.
5040 *
5041 * hw - Struct containing variables accessed by shared code
5042 * offset - offset of  word in the EEPROM to read
5043 * data - word read from the EEPROM
5044 * words - number of words to read
5045 *****************************************************************************/
5046static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
5047                                   u16 *data)
5048{
5049    u32    register_value = 0;
5050    u32    i              = 0;
5051    s32     error          = 0;
5052
5053    if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5054        return -E1000_ERR_SWFW_SYNC;
5055
5056    for (i = 0; i < words; i++) {
5057        register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5058                         ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5059                         E1000_EEPROM_RW_REG_START;
5060
5061        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5062        if (error) {
5063            break;
5064        }
5065
5066        ew32(EEWR, register_value);
5067
5068        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5069
5070        if (error) {
5071            break;
5072        }
5073    }
5074
5075    e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5076    return error;
5077}
5078
5079/******************************************************************************
5080 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5081 *
5082 * hw - Struct containing variables accessed by shared code
5083 *****************************************************************************/
5084static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5085{
5086    u32 attempts = 100000;
5087    u32 i, reg = 0;
5088    s32 done = E1000_ERR_EEPROM;
5089
5090    for (i = 0; i < attempts; i++) {
5091        if (eerd == E1000_EEPROM_POLL_READ)
5092            reg = er32(EERD);
5093        else
5094            reg = er32(EEWR);
5095
5096        if (reg & E1000_EEPROM_RW_REG_DONE) {
5097            done = E1000_SUCCESS;
5098            break;
5099        }
5100        udelay(5);
5101    }
5102
5103    return done;
5104}
5105
5106/***************************************************************************
5107* Description:     Determines if the onboard NVM is FLASH or EEPROM.
5108*
5109* hw - Struct containing variables accessed by shared code
5110****************************************************************************/
5111static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5112{
5113    u32 eecd = 0;
5114
5115    DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5116
5117    if (hw->mac_type == e1000_ich8lan)
5118        return false;
5119
5120    if (hw->mac_type == e1000_82573) {
5121        eecd = er32(EECD);
5122
5123        /* Isolate bits 15 & 16 */
5124        eecd = ((eecd >> 15) & 0x03);
5125
5126        /* If both bits are set, device is Flash type */
5127        if (eecd == 0x03) {
5128            return false;
5129        }
5130    }
5131    return true;
5132}
5133
5134/******************************************************************************
5135 * Verifies that the EEPROM has a valid checksum
5136 *
5137 * hw - Struct containing variables accessed by shared code
5138 *
5139 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5140 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5141 * valid.
5142 *****************************************************************************/
5143s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5144{
5145    u16 checksum = 0;
5146    u16 i, eeprom_data;
5147
5148    DEBUGFUNC("e1000_validate_eeprom_checksum");
5149
5150    if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
5151        /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
5152         * 10h-12h.  Checksum may need to be fixed. */
5153        e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5154        if ((eeprom_data & 0x10) == 0) {
5155            /* Read 0x23 and check bit 15.  This bit is a 1 when the checksum
5156             * has already been fixed.  If the checksum is still wrong and this
5157             * bit is a 1, we need to return bad checksum.  Otherwise, we need
5158             * to set this bit to a 1 and update the checksum. */
5159            e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5160            if ((eeprom_data & 0x8000) == 0) {
5161                eeprom_data |= 0x8000;
5162                e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5163                e1000_update_eeprom_checksum(hw);
5164            }
5165        }
5166    }
5167
5168    if (hw->mac_type == e1000_ich8lan) {
5169        /* Drivers must allocate the shadow ram structure for the
5170         * EEPROM checksum to be updated.  Otherwise, this bit as well
5171         * as the checksum must both be set correctly for this
5172         * validation to pass.
5173         */
5174        e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5175        if ((eeprom_data & 0x40) == 0) {
5176            eeprom_data |= 0x40;
5177            e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5178            e1000_update_eeprom_checksum(hw);
5179        }
5180    }
5181
5182    for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5183        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5184            DEBUGOUT("EEPROM Read Error\n");
5185            return -E1000_ERR_EEPROM;
5186        }
5187        checksum += eeprom_data;
5188    }
5189
5190    if (checksum == (u16)EEPROM_SUM)
5191        return E1000_SUCCESS;
5192    else {
5193        DEBUGOUT("EEPROM Checksum Invalid\n");
5194        return -E1000_ERR_EEPROM;
5195    }
5196}
5197
5198/******************************************************************************
5199 * Calculates the EEPROM checksum and writes it to the EEPROM
5200 *
5201 * hw - Struct containing variables accessed by shared code
5202 *
5203 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5204 * Writes the difference to word offset 63 of the EEPROM.
5205 *****************************************************************************/
5206s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5207{
5208    u32 ctrl_ext;
5209    u16 checksum = 0;
5210    u16 i, eeprom_data;
5211
5212    DEBUGFUNC("e1000_update_eeprom_checksum");
5213
5214    for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5215        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5216            DEBUGOUT("EEPROM Read Error\n");
5217            return -E1000_ERR_EEPROM;
5218        }
5219        checksum += eeprom_data;
5220    }
5221    checksum = (u16)EEPROM_SUM - checksum;
5222    if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5223        DEBUGOUT("EEPROM Write Error\n");
5224        return -E1000_ERR_EEPROM;
5225    } else if (hw->eeprom.type == e1000_eeprom_flash) {
5226        e1000_commit_shadow_ram(hw);
5227    } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5228        e1000_commit_shadow_ram(hw);
5229        /* Reload the EEPROM, or else modifications will not appear
5230         * until after next adapter reset. */
5231        ctrl_ext = er32(CTRL_EXT);
5232        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5233        ew32(CTRL_EXT, ctrl_ext);
5234        msleep(10);
5235    }
5236    return E1000_SUCCESS;
5237}
5238
5239/******************************************************************************
5240 * Parent function for writing words to the different EEPROM types.
5241 *
5242 * hw - Struct containing variables accessed by shared code
5243 * offset - offset within the EEPROM to be written to
5244 * words - number of words to write
5245 * data - 16 bit word to be written to the EEPROM
5246 *
5247 * If e1000_update_eeprom_checksum is not called after this function, the
5248 * EEPROM will most likely contain an invalid checksum.
5249 *****************************************************************************/
5250s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5251{
5252    s32 ret;
5253    spin_lock(&e1000_eeprom_lock);
5254    ret = e1000_do_write_eeprom(hw, offset, words, data);
5255    spin_unlock(&e1000_eeprom_lock);
5256    return ret;
5257}
5258
5259
5260static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
5261{
5262    struct e1000_eeprom_info *eeprom = &hw->eeprom;
5263    s32 status = 0;
5264
5265    DEBUGFUNC("e1000_write_eeprom");
5266
5267    /* If eeprom is not yet detected, do so now */
5268    if (eeprom->word_size == 0)
5269        e1000_init_eeprom_params(hw);
5270
5271    /* A check for invalid values:  offset too large, too many words, and not
5272     * enough words.
5273     */
5274    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5275       (words == 0)) {
5276        DEBUGOUT("\"words\" parameter out of bounds\n");
5277        return -E1000_ERR_EEPROM;
5278    }
5279
5280    /* 82573 writes only through eewr */
5281    if (eeprom->use_eewr)
5282        return e1000_write_eeprom_eewr(hw, offset, words, data);
5283
5284    if (eeprom->type == e1000_eeprom_ich8)
5285        return e1000_write_eeprom_ich8(hw, offset, words, data);
5286
5287    /* Prepare the EEPROM for writing  */
5288    if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5289        return -E1000_ERR_EEPROM;
5290
5291    if (eeprom->type == e1000_eeprom_microwire) {
5292        status = e1000_write_eeprom_microwire(hw, offset, words, data);
5293    } else {
5294        status = e1000_write_eeprom_spi(hw, offset, words, data);
5295        msleep(10);
5296    }
5297
5298    /* Done with writing */
5299    e1000_release_eeprom(hw);
5300
5301    return status;
5302}
5303
5304/******************************************************************************
5305 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5306 *
5307 * hw - Struct containing variables accessed by shared code
5308 * offset - offset within the EEPROM to be written to
5309 * words - number of words to write
5310 * data - pointer to array of 8 bit words to be written to the EEPROM
5311 *
5312 *****************************************************************************/
5313static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
5314                                  u16 *data)
5315{
5316    struct e1000_eeprom_info *eeprom = &hw->eeprom;
5317    u16 widx = 0;
5318
5319    DEBUGFUNC("e1000_write_eeprom_spi");
5320
5321    while (widx < words) {
5322        u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
5323
5324        if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5325
5326        e1000_standby_eeprom(hw);
5327
5328        /*  Send the WRITE ENABLE command (8 bit opcode )  */
5329        e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5330                                    eeprom->opcode_bits);
5331
5332        e1000_standby_eeprom(hw);
5333
5334        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5335        if ((eeprom->address_bits == 8) && (offset >= 128))
5336            write_opcode |= EEPROM_A8_OPCODE_SPI;
5337
5338        /* Send the Write command (8-bit opcode + addr) */
5339        e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5340
5341        e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
5342                                eeprom->address_bits);
5343
5344        /* Send the data */
5345
5346        /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5347        while (widx < words) {
5348            u16 word_out = data[widx];
5349            word_out = (word_out >> 8) | (word_out << 8);
5350            e1000_shift_out_ee_bits(hw, word_out, 16);
5351            widx++;
5352
5353            /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5354             * operation, while the smaller eeproms are capable of an 8-byte
5355             * PAGE WRITE operation.  Break the inner loop to pass new address
5356             */
5357            if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5358                e1000_standby_eeprom(hw);
5359                break;
5360            }
5361        }
5362    }
5363
5364    return E1000_SUCCESS;
5365}
5366
5367/******************************************************************************
5368 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5369 *
5370 * hw - Struct containing variables accessed by shared code
5371 * offset - offset within the EEPROM to be written to
5372 * words - number of words to write
5373 * data - pointer to array of 16 bit words to be written to the EEPROM
5374 *
5375 *****************************************************************************/
5376static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
5377                                        u16 words, u16 *data)
5378{
5379    struct e1000_eeprom_info *eeprom = &hw->eeprom;
5380    u32 eecd;
5381    u16 words_written = 0;
5382    u16 i = 0;
5383
5384    DEBUGFUNC("e1000_write_eeprom_microwire");
5385
5386    /* Send the write enable command to the EEPROM (3-bit opcode plus
5387     * 6/8-bit dummy address beginning with 11).  It's less work to include
5388     * the 11 of the dummy address as part of the opcode than it is to shift
5389     * it over the correct number of bits for the address.  This puts the
5390     * EEPROM into write/erase mode.
5391     */
5392    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5393                            (u16)(eeprom->opcode_bits + 2));
5394
5395    e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5396
5397    /* Prepare the EEPROM */
5398    e1000_standby_eeprom(hw);
5399
5400    while (words_written < words) {
5401        /* Send the Write command (3-bit opcode + addr) */
5402        e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5403                                eeprom->opcode_bits);
5404
5405        e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
5406                                eeprom->address_bits);
5407
5408        /* Send the data */
5409        e1000_shift_out_ee_bits(hw, data[words_written], 16);
5410
5411        /* Toggle the CS line.  This in effect tells the EEPROM to execute
5412         * the previous command.
5413         */
5414        e1000_standby_eeprom(hw);
5415
5416        /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
5417         * signal that the command has been completed by raising the DO signal.
5418         * If DO does not go high in 10 milliseconds, then error out.
5419         */
5420        for (i = 0; i < 200; i++) {
5421            eecd = er32(EECD);
5422            if (eecd & E1000_EECD_DO) break;
5423            udelay(50);
5424        }
5425        if (i == 200) {
5426            DEBUGOUT("EEPROM Write did not complete\n");
5427            return -E1000_ERR_EEPROM;
5428        }
5429
5430        /* Recover from write */
5431        e1000_standby_eeprom(hw);
5432
5433        words_written++;
5434    }
5435
5436    /* Send the write disable command to the EEPROM (3-bit opcode plus
5437     * 6/8-bit dummy address beginning with 10).  It's less work to include
5438     * the 10 of the dummy address as part of the opcode than it is to shift
5439     * it over the correct number of bits for the address.  This takes the
5440     * EEPROM out of write/erase mode.
5441     */
5442    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5443                            (u16)(eeprom->opcode_bits + 2));
5444
5445    e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
5446
5447    return E1000_SUCCESS;
5448}
5449
5450/******************************************************************************
5451 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5452 * in the eeprom cache and the non modified values in the currently active bank
5453 * to the new bank.
5454 *
5455 * hw - Struct containing variables accessed by shared code
5456 * offset - offset of  word in the EEPROM to read
5457 * data - word read from the EEPROM
5458 * words - number of words to read
5459 *****************************************************************************/
5460static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5461{
5462    u32 attempts = 100000;
5463    u32 eecd = 0;
5464    u32 flop = 0;
5465    u32 i = 0;
5466    s32 error = E1000_SUCCESS;
5467    u32 old_bank_offset = 0;
5468    u32 new_bank_offset = 0;
5469    u8 low_byte = 0;
5470    u8 high_byte = 0;
5471    bool sector_write_failed = false;
5472
5473    if (hw->mac_type == e1000_82573) {
5474        /* The flop register will be used to determine if flash type is STM */
5475        flop = er32(FLOP);
5476        for (i=0; i < attempts; i++) {
5477            eecd = er32(EECD);
5478            if ((eecd & E1000_EECD_FLUPD) == 0) {
5479                break;
5480            }
5481            udelay(5);
5482        }
5483
5484        if (i == attempts) {
5485            return -E1000_ERR_EEPROM;
5486        }
5487
5488        /* If STM opcode located in bits 15:8 of flop, reset firmware */
5489        if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5490            ew32(HICR, E1000_HICR_FW_RESET);
5491        }
5492
5493        /* Perform the flash update */
5494        ew32(EECD, eecd | E1000_EECD_FLUPD);
5495
5496        for (i=0; i < attempts; i++) {
5497            eecd = er32(EECD);
5498            if ((eecd & E1000_EECD_FLUPD) == 0) {
5499                break;
5500            }
5501            udelay(5);
5502        }
5503
5504        if (i == attempts) {
5505            return -E1000_ERR_EEPROM;
5506        }
5507    }
5508
5509    if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5510        /* We're writing to the opposite bank so if we're on bank 1,
5511         * write to bank 0 etc.  We also need to erase the segment that
5512         * is going to be written */
5513        if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
5514            new_bank_offset = hw->flash_bank_size * 2;
5515            old_bank_offset = 0;
5516            e1000_erase_ich8_4k_segment(hw, 1);
5517        } else {
5518            old_bank_offset = hw->flash_bank_size * 2;
5519            new_bank_offset = 0;
5520            e1000_erase_ich8_4k_segment(hw, 0);
5521        }
5522
5523        sector_write_failed = false;
5524        /* Loop for every byte in the shadow RAM,
5525         * which is in units of words. */
5526        for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5527            /* Determine whether to write the value stored
5528             * in the other NVM bank or a modified value stored
5529             * in the shadow RAM */
5530            if (hw->eeprom_shadow_ram[i].modified) {
5531                low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
5532                udelay(100);
5533                error = e1000_verify_write_ich8_byte(hw,
5534                            (i << 1) + new_bank_offset, low_byte);
5535
5536                if (error != E1000_SUCCESS)
5537                    sector_write_failed = true;
5538                else {
5539                    high_byte =
5540                        (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5541                    udelay(100);
5542                }
5543            } else {
5544                e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5545                                     &low_byte);
5546                udelay(100);
5547                error = e1000_verify_write_ich8_byte(hw,
5548                            (i << 1) + new_bank_offset, low_byte);
5549
5550                if (error != E1000_SUCCESS)
5551                    sector_write_failed = true;
5552                else {
5553                    e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5554                                         &high_byte);
5555                    udelay(100);
5556                }
5557            }
5558
5559            /* If the write of the low byte was successful, go ahead and
5560             * write the high byte while checking to make sure that if it
5561             * is the signature byte, then it is handled properly */
5562            if (!sector_write_failed) {
5563                /* If the word is 0x13, then make sure the signature bits
5564                 * (15:14) are 11b until the commit has completed.
5565                 * This will allow us to write 10b which indicates the
5566                 * signature is valid.  We want to do this after the write
5567                 * has completed so that we don't mark the segment valid
5568                 * while the write is still in progress */
5569                if (i == E1000_ICH_NVM_SIG_WORD)
5570                    high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5571
5572                error = e1000_verify_write_ich8_byte(hw,
5573                            (i << 1) + new_bank_offset + 1, high_byte);
5574                if (error != E1000_SUCCESS)
5575                    sector_write_failed = true;
5576
5577            } else {
5578                /* If the write failed then break from the loop and
5579                 * return an error */
5580                break;
5581            }
5582        }
5583
5584        /* Don't bother writing the segment valid bits if sector
5585         * programming failed. */
5586        if (!sector_write_failed) {
5587            /* Finally validate the new segment by setting bit 15:14
5588             * to 10b in word 0x13 , this can be done without an
5589             * erase as well since these bits are 11 to start with
5590             * and we need to change bit 14 to 0b */
5591            e1000_read_ich8_byte(hw,
5592                                 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5593                                 &high_byte);
5594            high_byte &= 0xBF;
5595            error = e1000_verify_write_ich8_byte(hw,
5596                        E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5597            /* And invalidate the previously valid segment by setting
5598             * its signature word (0x13) high_byte to 0b. This can be
5599             * done without an erase because flash erase sets all bits
5600             * to 1's. We can write 1's to 0's without an erase */
5601            if (error == E1000_SUCCESS) {
5602                error = e1000_verify_write_ich8_byte(hw,
5603                            E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5604            }
5605
5606            /* Clear the now not used entry in the cache */
5607            for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5608                hw->eeprom_shadow_ram[i].modified = false;
5609                hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5610            }
5611        }
5612    }
5613
5614    return error;
5615}
5616
5617/******************************************************************************
5618 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5619 * second function of dual function devices
5620 *
5621 * hw - Struct containing variables accessed by shared code
5622 *****************************************************************************/
5623s32 e1000_read_mac_addr(struct e1000_hw *hw)
5624{
5625    u16 offset;
5626    u16 eeprom_data, i;
5627
5628    DEBUGFUNC("e1000_read_mac_addr");
5629
5630    for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5631        offset = i >> 1;
5632        if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5633            DEBUGOUT("EEPROM Read Error\n");
5634            return -E1000_ERR_EEPROM;
5635        }
5636        hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
5637        hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
5638    }
5639
5640    switch (hw->mac_type) {
5641    default:
5642        break;
5643    case e1000_82546:
5644    case e1000_82546_rev_3:
5645    case e1000_82571:
5646    case e1000_80003es2lan:
5647        if (er32(STATUS) & E1000_STATUS_FUNC_1)
5648            hw->perm_mac_addr[5] ^= 0x01;
5649        break;
5650    }
5651
5652    for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5653        hw->mac_addr[i] = hw->perm_mac_addr[i];
5654    return E1000_SUCCESS;
5655}
5656
5657/******************************************************************************
5658 * Initializes receive address filters.
5659 *
5660 * hw - Struct containing variables accessed by shared code
5661 *
5662 * Places the MAC address in receive address register 0 and clears the rest
5663 * of the receive addresss registers. Clears the multicast table. Assumes
5664 * the receiver is in reset when the routine is called.
5665 *****************************************************************************/
5666static void e1000_init_rx_addrs(struct e1000_hw *hw)
5667{
5668    u32 i;
5669    u32 rar_num;
5670
5671    DEBUGFUNC("e1000_init_rx_addrs");
5672
5673    /* Setup the receive address. */
5674    DEBUGOUT("Programming MAC Address into RAR[0]\n");
5675
5676    e1000_rar_set(hw, hw->mac_addr, 0);
5677
5678    rar_num = E1000_RAR_ENTRIES;
5679
5680    /* Reserve a spot for the Locally Administered Address to work around
5681     * an 82571 issue in which a reset on one port will reload the MAC on
5682     * the other port. */
5683    if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
5684        rar_num -= 1;
5685    if (hw->mac_type == e1000_ich8lan)
5686        rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5687
5688    /* Zero out the other 15 receive addresses. */
5689    DEBUGOUT("Clearing RAR[1-15]\n");
5690    for (i = 1; i < rar_num; i++) {
5691        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5692        E1000_WRITE_FLUSH();
5693        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5694        E1000_WRITE_FLUSH();
5695    }
5696}
5697
5698/******************************************************************************
5699 * Hashes an address to determine its location in the multicast table
5700 *
5701 * hw - Struct containing variables accessed by shared code
5702 * mc_addr - the multicast address to hash
5703 *****************************************************************************/
5704u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
5705{
5706    u32 hash_value = 0;
5707
5708    /* The portion of the address that is used for the hash table is
5709     * determined by the mc_filter_type setting.
5710     */
5711    switch (hw->mc_filter_type) {
5712    /* [0] [1] [2] [3] [4] [5]
5713     * 01  AA  00  12  34  56
5714     * LSB                 MSB
5715     */
5716    case 0:
5717        if (hw->mac_type == e1000_ich8lan) {
5718            /* [47:38] i.e. 0x158 for above example address */
5719            hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2));
5720        } else {
5721            /* [47:36] i.e. 0x563 for above example address */
5722            hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5723        }
5724        break;
5725    case 1:
5726        if (hw->mac_type == e1000_ich8lan) {
5727            /* [46:37] i.e. 0x2B1 for above example address */
5728            hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3));
5729        } else {
5730            /* [46:35] i.e. 0xAC6 for above example address */
5731            hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
5732        }
5733        break;
5734    case 2:
5735        if (hw->mac_type == e1000_ich8lan) {
5736            /*[45:36] i.e. 0x163 for above example address */
5737            hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
5738        } else {
5739            /* [45:34] i.e. 0x5D8 for above example address */
5740            hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5741        }
5742        break;
5743    case 3:
5744        if (hw->mac_type == e1000_ich8lan) {
5745            /* [43:34] i.e. 0x18D for above example address */
5746            hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
5747        } else {
5748            /* [43:32] i.e. 0x634 for above example address */
5749            hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
5750        }
5751        break;
5752    }
5753
5754    hash_value &= 0xFFF;
5755    if (hw->mac_type == e1000_ich8lan)
5756        hash_value &= 0x3FF;
5757
5758    return hash_value;
5759}
5760
5761/******************************************************************************
5762 * Sets the bit in the multicast table corresponding to the hash value.
5763 *
5764 * hw - Struct containing variables accessed by shared code
5765 * hash_value - Multicast address hash value
5766 *****************************************************************************/
5767void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
5768{
5769    u32 hash_bit, hash_reg;
5770    u32 mta;
5771    u32 temp;
5772
5773    /* The MTA is a register array of 128 32-bit registers.
5774     * It is treated like an array of 4096 bits.  We want to set
5775     * bit BitArray[hash_value]. So we figure out what register
5776     * the bit is in, read it, OR in the new bit, then write
5777     * back the new value.  The register is determined by the
5778     * upper 7 bits of the hash value and the bit within that
5779     * register are determined by the lower 5 bits of the value.
5780     */
5781    hash_reg = (hash_value >> 5) & 0x7F;
5782    if (hw->mac_type == e1000_ich8lan)
5783        hash_reg &= 0x1F;
5784
5785    hash_bit = hash_value & 0x1F;
5786
5787    mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5788
5789    mta |= (1 << hash_bit);
5790
5791    /* If we are on an 82544 and we are trying to write an odd offset
5792     * in the MTA, save off the previous entry before writing and
5793     * restore the old value after writing.
5794     */
5795    if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5796        temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5797        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5798        E1000_WRITE_FLUSH();
5799        E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5800        E1000_WRITE_FLUSH();
5801    } else {
5802        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5803        E1000_WRITE_FLUSH();
5804    }
5805}
5806
5807/******************************************************************************
5808 * Puts an ethernet address into a receive address register.
5809 *
5810 * hw - Struct containing variables accessed by shared code
5811 * addr - Address to put into receive address register
5812 * index - Receive address register to write
5813 *****************************************************************************/
5814void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
5815{
5816    u32 rar_low, rar_high;
5817
5818    /* HW expects these in little endian so we reverse the byte order
5819     * from network order (big endian) to little endian
5820     */
5821    rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
5822               ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
5823    rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
5824
5825    /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5826     * unit hang.
5827     *
5828     * Description:
5829     * If there are any Rx frames queued up or otherwise present in the HW
5830     * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5831     * hang.  To work around this issue, we have to disable receives and
5832     * flush out all Rx frames before we enable RSS. To do so, we modify we
5833     * redirect all Rx traffic to manageability and then reset the HW.
5834     * This flushes away Rx frames, and (since the redirections to
5835     * manageability persists across resets) keeps new ones from coming in
5836     * while we work.  Then, we clear the Address Valid AV bit for all MAC
5837     * addresses and undo the re-direction to manageability.
5838     * Now, frames are coming in again, but the MAC won't accept them, so
5839     * far so good.  We now proceed to initialize RSS (if necessary) and
5840     * configure the Rx unit.  Last, we re-enable the AV bits and continue
5841     * on our merry way.
5842     */
5843    switch (hw->mac_type) {
5844    case e1000_82571:
5845    case e1000_82572:
5846    case e1000_80003es2lan:
5847        if (hw->leave_av_bit_off)
5848            break;
5849    default:
5850        /* Indicate to hardware the Address is Valid. */
5851        rar_high |= E1000_RAH_AV;
5852        break;
5853    }
5854
5855    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5856    E1000_WRITE_FLUSH();
5857    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5858    E1000_WRITE_FLUSH();
5859}
5860
5861/******************************************************************************
5862 * Writes a value to the specified offset in the VLAN filter table.
5863 *
5864 * hw - Struct containing variables accessed by shared code
5865 * offset - Offset in VLAN filer table to write
5866 * value - Value to write into VLAN filter table
5867 *****************************************************************************/
5868void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5869{
5870    u32 temp;
5871
5872    if (hw->mac_type == e1000_ich8lan)
5873        return;
5874
5875    if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5876        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5877        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5878        E1000_WRITE_FLUSH();
5879        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5880        E1000_WRITE_FLUSH();
5881    } else {
5882        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5883        E1000_WRITE_FLUSH();
5884    }
5885}
5886
5887/******************************************************************************
5888 * Clears the VLAN filer table
5889 *
5890 * hw - Struct containing variables accessed by shared code
5891 *****************************************************************************/
5892static void e1000_clear_vfta(struct e1000_hw *hw)
5893{
5894    u32 offset;
5895    u32 vfta_value = 0;
5896    u32 vfta_offset = 0;
5897    u32 vfta_bit_in_reg = 0;
5898
5899    if (hw->mac_type == e1000_ich8lan)
5900        return;
5901
5902    if (hw->mac_type == e1000_82573) {
5903        if (hw->mng_cookie.vlan_id != 0) {
5904            /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5905             * ID.  The following operations determine which 32b entry
5906             * (i.e. offset) into the array we want to set the VLAN ID
5907             * (i.e. bit) of the manageability unit. */
5908            vfta_offset = (hw->mng_cookie.vlan_id >>
5909                           E1000_VFTA_ENTRY_SHIFT) &
5910                          E1000_VFTA_ENTRY_MASK;
5911            vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5912                                    E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5913        }
5914    }
5915    for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5916        /* If the offset we want to clear is the same offset of the
5917         * manageability VLAN ID, then clear all bits except that of the
5918         * manageability unit */
5919        vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5920        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5921        E1000_WRITE_FLUSH();
5922    }
5923}
5924
5925static s32 e1000_id_led_init(struct e1000_hw *hw)
5926{
5927    u32 ledctl;
5928    const u32 ledctl_mask = 0x000000FF;
5929    const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5930    const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5931    u16 eeprom_data, i, temp;
5932    const u16 led_mask = 0x0F;
5933
5934    DEBUGFUNC("e1000_id_led_init");
5935
5936    if (hw->mac_type < e1000_82540) {
5937        /* Nothing to do */
5938        return E1000_SUCCESS;
5939    }
5940
5941    ledctl = er32(LEDCTL);
5942    hw->ledctl_default = ledctl;
5943    hw->ledctl_mode1 = hw->ledctl_default;
5944    hw->ledctl_mode2 = hw->ledctl_default;
5945
5946    if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5947        DEBUGOUT("EEPROM Read Error\n");
5948        return -E1000_ERR_EEPROM;
5949    }
5950
5951    if ((hw->mac_type == e1000_82573) &&
5952        (eeprom_data == ID_LED_RESERVED_82573))
5953        eeprom_data = ID_LED_DEFAULT_82573;
5954    else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5955            (eeprom_data == ID_LED_RESERVED_FFFF)) {
5956        if (hw->mac_type == e1000_ich8lan)
5957            eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5958        else
5959            eeprom_data = ID_LED_DEFAULT;
5960    }
5961
5962    for (i = 0; i < 4; i++) {
5963        temp = (eeprom_data >> (i << 2)) & led_mask;
5964        switch (temp) {
5965        case ID_LED_ON1_DEF2:
5966        case ID_LED_ON1_ON2:
5967        case ID_LED_ON1_OFF2:
5968            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5969            hw->ledctl_mode1 |= ledctl_on << (i << 3);
5970            break;
5971        case ID_LED_OFF1_DEF2:
5972        case ID_LED_OFF1_ON2:
5973        case ID_LED_OFF1_OFF2:
5974            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5975            hw->ledctl_mode1 |= ledctl_off << (i << 3);
5976            break;
5977        default:
5978            /* Do nothing */
5979            break;
5980        }
5981        switch (temp) {
5982        case ID_LED_DEF1_ON2:
5983        case ID_LED_ON1_ON2:
5984        case ID_LED_OFF1_ON2:
5985            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5986            hw->ledctl_mode2 |= ledctl_on << (i << 3);
5987            break;
5988        case ID_LED_DEF1_OFF2:
5989        case ID_LED_ON1_OFF2:
5990        case ID_LED_OFF1_OFF2:
5991            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5992            hw->ledctl_mode2 |= ledctl_off << (i << 3);
5993            break;
5994        default:
5995            /* Do nothing */
5996            break;
5997        }
5998    }
5999    return E1000_SUCCESS;
6000}
6001
6002/******************************************************************************
6003 * Prepares SW controlable LED for use and saves the current state of the LED.
6004 *
6005 * hw - Struct containing variables accessed by shared code
6006 *****************************************************************************/
6007s32 e1000_setup_led(struct e1000_hw *hw)
6008{
6009    u32 ledctl;
6010    s32 ret_val = E1000_SUCCESS;
6011
6012    DEBUGFUNC("e1000_setup_led");
6013
6014    switch (hw->mac_type) {
6015    case e1000_82542_rev2_0:
6016    case e1000_82542_rev2_1:
6017    case e1000_82543:
6018    case e1000_82544:
6019        /* No setup necessary */
6020        break;
6021    case e1000_82541:
6022    case e1000_82547:
6023    case e1000_82541_rev_2:
6024    case e1000_82547_rev_2:
6025        /* Turn off PHY Smart Power Down (if enabled) */
6026        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6027                                     &hw->phy_spd_default);
6028        if (ret_val)
6029            return ret_val;
6030        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6031                                      (u16)(hw->phy_spd_default &
6032                                      ~IGP01E1000_GMII_SPD));
6033        if (ret_val)
6034            return ret_val;
6035        /* Fall Through */
6036    default:
6037        if (hw->media_type == e1000_media_type_fiber) {
6038            ledctl = er32(LEDCTL);
6039            /* Save current LEDCTL settings */
6040            hw->ledctl_default = ledctl;
6041            /* Turn off LED0 */
6042            ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6043                        E1000_LEDCTL_LED0_BLINK |
6044                        E1000_LEDCTL_LED0_MODE_MASK);
6045            ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6046                       E1000_LEDCTL_LED0_MODE_SHIFT);
6047            ew32(LEDCTL, ledctl);
6048        } else if (hw->media_type == e1000_media_type_copper)
6049            ew32(LEDCTL, hw->ledctl_mode1);
6050        break;
6051    }
6052
6053    return E1000_SUCCESS;
6054}
6055
6056
6057/******************************************************************************
6058 * Used on 82571 and later Si that has LED blink bits.
6059 * Callers must use their own timer and should have already called
6060 * e1000_id_led_init()
6061 * Call e1000_cleanup led() to stop blinking
6062 *
6063 * hw - Struct containing variables accessed by shared code
6064 *****************************************************************************/
6065s32 e1000_blink_led_start(struct e1000_hw *hw)
6066{
6067    s16  i;
6068    u32 ledctl_blink = 0;
6069
6070    DEBUGFUNC("e1000_id_led_blink_on");
6071
6072    if (hw->mac_type < e1000_82571) {
6073        /* Nothing to do */
6074        return E1000_SUCCESS;
6075    }
6076    if (hw->media_type == e1000_media_type_fiber) {
6077        /* always blink LED0 for PCI-E fiber */
6078        ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6079                     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6080    } else {
6081        /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6082        ledctl_blink = hw->ledctl_mode2;
6083        for (i=0; i < 4; i++)
6084            if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6085                E1000_LEDCTL_MODE_LED_ON)
6086                ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6087    }
6088
6089    ew32(LEDCTL, ledctl_blink);
6090
6091    return E1000_SUCCESS;
6092}
6093
6094/******************************************************************************
6095 * Restores the saved state of the SW controlable LED.
6096 *
6097 * hw - Struct containing variables accessed by shared code
6098 *****************************************************************************/
6099s32 e1000_cleanup_led(struct e1000_hw *hw)
6100{
6101    s32 ret_val = E1000_SUCCESS;
6102
6103    DEBUGFUNC("e1000_cleanup_led");
6104
6105    switch (hw->mac_type) {
6106    case e1000_82542_rev2_0:
6107    case e1000_82542_rev2_1:
6108    case e1000_82543:
6109    case e1000_82544:
6110        /* No cleanup necessary */
6111        break;
6112    case e1000_82541:
6113    case e1000_82547:
6114    case e1000_82541_rev_2:
6115    case e1000_82547_rev_2:
6116        /* Turn on PHY Smart Power Down (if previously enabled) */
6117        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6118                                      hw->phy_spd_default);
6119        if (ret_val)
6120            return ret_val;
6121        /* Fall Through */
6122    default:
6123        if (hw->phy_type == e1000_phy_ife) {
6124            e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6125            break;
6126        }
6127        /* Restore LEDCTL settings */
6128        ew32(LEDCTL, hw->ledctl_default);
6129        break;
6130    }
6131
6132    return E1000_SUCCESS;
6133}
6134
6135/******************************************************************************
6136 * Turns on the software controllable LED
6137 *
6138 * hw - Struct containing variables accessed by shared code
6139 *****************************************************************************/
6140s32 e1000_led_on(struct e1000_hw *hw)
6141{
6142    u32 ctrl = er32(CTRL);
6143
6144    DEBUGFUNC("e1000_led_on");
6145
6146    switch (hw->mac_type) {
6147    case e1000_82542_rev2_0:
6148    case e1000_82542_rev2_1:
6149    case e1000_82543:
6150        /* Set SW Defineable Pin 0 to turn on the LED */
6151        ctrl |= E1000_CTRL_SWDPIN0;
6152        ctrl |= E1000_CTRL_SWDPIO0;
6153        break;
6154    case e1000_82544:
6155        if (hw->media_type == e1000_media_type_fiber) {
6156            /* Set SW Defineable Pin 0 to turn on the LED */
6157            ctrl |= E1000_CTRL_SWDPIN0;
6158            ctrl |= E1000_CTRL_SWDPIO0;
6159        } else {
6160            /* Clear SW Defineable Pin 0 to turn on the LED */
6161            ctrl &= ~E1000_CTRL_SWDPIN0;
6162            ctrl |= E1000_CTRL_SWDPIO0;
6163        }
6164        break;
6165    default:
6166        if (hw->media_type == e1000_media_type_fiber) {
6167            /* Clear SW Defineable Pin 0 to turn on the LED */
6168            ctrl &= ~E1000_CTRL_SWDPIN0;
6169            ctrl |= E1000_CTRL_SWDPIO0;
6170        } else if (hw->phy_type == e1000_phy_ife) {
6171            e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6172                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6173        } else if (hw->media_type == e1000_media_type_copper) {
6174            ew32(LEDCTL, hw->ledctl_mode2);
6175            return E1000_SUCCESS;
6176        }
6177        break;
6178    }
6179
6180    ew32(CTRL, ctrl);
6181
6182    return E1000_SUCCESS;
6183}
6184
6185/******************************************************************************
6186 * Turns off the software controllable LED
6187 *
6188 * hw - Struct containing variables accessed by shared code
6189 *****************************************************************************/
6190s32 e1000_led_off(struct e1000_hw *hw)
6191{
6192    u32 ctrl = er32(CTRL);
6193
6194    DEBUGFUNC("e1000_led_off");
6195
6196    switch (hw->mac_type) {
6197    case e1000_82542_rev2_0:
6198    case e1000_82542_rev2_1:
6199    case e1000_82543:
6200        /* Clear SW Defineable Pin 0 to turn off the LED */
6201        ctrl &= ~E1000_CTRL_SWDPIN0;
6202        ctrl |= E1000_CTRL_SWDPIO0;
6203        break;
6204    case e1000_82544:
6205        if (hw->media_type == e1000_media_type_fiber) {
6206            /* Clear SW Defineable Pin 0 to turn off the LED */
6207            ctrl &= ~E1000_CTRL_SWDPIN0;
6208            ctrl |= E1000_CTRL_SWDPIO0;
6209        } else {
6210            /* Set SW Defineable Pin 0 to turn off the LED */
6211            ctrl |= E1000_CTRL_SWDPIN0;
6212            ctrl |= E1000_CTRL_SWDPIO0;
6213        }
6214        break;
6215    default:
6216        if (hw->media_type == e1000_media_type_fiber) {
6217            /* Set SW Defineable Pin 0 to turn off the LED */
6218            ctrl |= E1000_CTRL_SWDPIN0;
6219            ctrl |= E1000_CTRL_SWDPIO0;
6220        } else if (hw->phy_type == e1000_phy_ife) {
6221            e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6222                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6223        } else if (hw->media_type == e1000_media_type_copper) {
6224            ew32(LEDCTL, hw->ledctl_mode1);
6225            return E1000_SUCCESS;
6226        }
6227        break;
6228    }
6229
6230    ew32(CTRL, ctrl);
6231
6232    return E1000_SUCCESS;
6233}
6234
6235/******************************************************************************
6236 * Clears all hardware statistics counters.
6237 *
6238 * hw - Struct containing variables accessed by shared code
6239 *****************************************************************************/
6240static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6241{
6242    volatile u32 temp;
6243
6244    temp = er32(CRCERRS);
6245    temp = er32(SYMERRS);
6246    temp = er32(MPC);
6247    temp = er32(SCC);
6248    temp = er32(ECOL);
6249    temp = er32(MCC);
6250    temp = er32(LATECOL);
6251    temp = er32(COLC);
6252    temp = er32(DC);
6253    temp = er32(SEC);
6254    temp = er32(RLEC);
6255    temp = er32(XONRXC);
6256    temp = er32(XONTXC);
6257    temp = er32(XOFFRXC);
6258    temp = er32(XOFFTXC);
6259    temp = er32(FCRUC);
6260
6261    if (hw->mac_type != e1000_ich8lan) {
6262    temp = er32(PRC64);
6263    temp = er32(PRC127);
6264    temp = er32(PRC255);
6265    temp = er32(PRC511);
6266    temp = er32(PRC1023);
6267    temp = er32(PRC1522);
6268    }
6269
6270    temp = er32(GPRC);
6271    temp = er32(BPRC);
6272    temp = er32(MPRC);
6273    temp = er32(GPTC);
6274    temp = er32(GORCL);
6275    temp = er32(GORCH);
6276    temp = er32(GOTCL);
6277    temp = er32(GOTCH);
6278    temp = er32(RNBC);
6279    temp = er32(RUC);
6280    temp = er32(RFC);
6281    temp = er32(ROC);
6282    temp = er32(RJC);
6283    temp = er32(TORL);
6284    temp = er32(TORH);
6285    temp = er32(TOTL);
6286    temp = er32(TOTH);
6287    temp = er32(TPR);
6288    temp = er32(TPT);
6289
6290    if (hw->mac_type != e1000_ich8lan) {
6291    temp = er32(PTC64);
6292    temp = er32(PTC127);
6293    temp = er32(PTC255);
6294    temp = er32(PTC511);
6295    temp = er32(PTC1023);
6296    temp = er32(PTC1522);
6297    }
6298
6299    temp = er32(MPTC);
6300    temp = er32(BPTC);
6301
6302    if (hw->mac_type < e1000_82543) return;
6303
6304    temp = er32(ALGNERRC);
6305    temp = er32(RXERRC);
6306    temp = er32(TNCRS);
6307    temp = er32(CEXTERR);
6308    temp = er32(TSCTC);
6309    temp = er32(TSCTFC);
6310
6311    if (hw->mac_type <= e1000_82544) return;
6312
6313    temp = er32(MGTPRC);
6314    temp = er32(MGTPDC);
6315    temp = er32(MGTPTC);
6316
6317    if (hw->mac_type <= e1000_82547_rev_2) return;
6318
6319    temp = er32(IAC);
6320    temp = er32(ICRXOC);
6321
6322    if (hw->mac_type == e1000_ich8lan) return;
6323
6324    temp = er32(ICRXPTC);
6325    temp = er32(ICRXATC);
6326    temp = er32(ICTXPTC);
6327    temp = er32(ICTXATC);
6328    temp = er32(ICTXQEC);
6329    temp = er32(ICTXQMTC);
6330    temp = er32(ICRXDMTC);
6331}
6332
6333/******************************************************************************
6334 * Resets Adaptive IFS to its default state.
6335 *
6336 * hw - Struct containing variables accessed by shared code
6337 *
6338 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6339 * hw->ifs_params_forced to true. However, you must initialize hw->
6340 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6341 * before calling this function.
6342 *****************************************************************************/
6343void e1000_reset_adaptive(struct e1000_hw *hw)
6344{
6345    DEBUGFUNC("e1000_reset_adaptive");
6346
6347    if (hw->adaptive_ifs) {
6348        if (!hw->ifs_params_forced) {
6349            hw->current_ifs_val = 0;
6350            hw->ifs_min_val = IFS_MIN;
6351            hw->ifs_max_val = IFS_MAX;
6352            hw->ifs_step_size = IFS_STEP;
6353            hw->ifs_ratio = IFS_RATIO;
6354        }
6355        hw->in_ifs_mode = false;
6356        ew32(AIT, 0);
6357    } else {
6358        DEBUGOUT("Not in Adaptive IFS mode!\n");
6359    }
6360}
6361
6362/******************************************************************************
6363 * Called during the callback/watchdog routine to update IFS value based on
6364 * the ratio of transmits to collisions.
6365 *
6366 * hw - Struct containing variables accessed by shared code
6367 * tx_packets - Number of transmits since last callback
6368 * total_collisions - Number of collisions since last callback
6369 *****************************************************************************/
6370void e1000_update_adaptive(struct e1000_hw *hw)
6371{
6372    DEBUGFUNC("e1000_update_adaptive");
6373
6374    if (hw->adaptive_ifs) {
6375        if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6376            if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6377                hw->in_ifs_mode = true;
6378                if (hw->current_ifs_val < hw->ifs_max_val) {
6379                    if (hw->current_ifs_val == 0)
6380                        hw->current_ifs_val = hw->ifs_min_val;
6381                    else
6382                        hw->current_ifs_val += hw->ifs_step_size;
6383                    ew32(AIT, hw->current_ifs_val);
6384                }
6385            }
6386        } else {
6387            if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6388                hw->current_ifs_val = 0;
6389                hw->in_ifs_mode = false;
6390                ew32(AIT, 0);
6391            }
6392        }
6393    } else {
6394        DEBUGOUT("Not in Adaptive IFS mode!\n");
6395    }
6396}
6397
6398/******************************************************************************
6399 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6400 *
6401 * hw - Struct containing variables accessed by shared code
6402 * frame_len - The length of the frame in question
6403 * mac_addr - The Ethernet destination address of the frame in question
6404 *****************************************************************************/
6405void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
6406                            u32 frame_len, u8 *mac_addr)
6407{
6408    u64 carry_bit;
6409
6410    /* First adjust the frame length. */
6411    frame_len--;
6412    /* We need to adjust the statistics counters, since the hardware
6413     * counters overcount this packet as a CRC error and undercount
6414     * the packet as a good packet
6415     */
6416    /* This packet should not be counted as a CRC error.    */
6417    stats->crcerrs--;
6418    /* This packet does count as a Good Packet Received.    */
6419    stats->gprc++;
6420
6421    /* Adjust the Good Octets received counters             */
6422    carry_bit = 0x80000000 & stats->gorcl;
6423    stats->gorcl += frame_len;
6424    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6425     * Received Count) was one before the addition,
6426     * AND it is zero after, then we lost the carry out,
6427     * need to add one to Gorch (Good Octets Received Count High).
6428     * This could be simplified if all environments supported
6429     * 64-bit integers.
6430     */
6431    if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6432        stats->gorch++;
6433    /* Is this a broadcast or multicast?  Check broadcast first,
6434     * since the test for a multicast frame will test positive on
6435     * a broadcast frame.
6436     */
6437    if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
6438        /* Broadcast packet */
6439        stats->bprc++;
6440    else if (*mac_addr & 0x01)
6441        /* Multicast packet */
6442        stats->mprc++;
6443
6444    if (frame_len == hw->max_frame_size) {
6445        /* In this case, the hardware has overcounted the number of
6446         * oversize frames.
6447         */
6448        if (stats->roc > 0)
6449            stats->roc--;
6450    }
6451
6452    /* Adjust the bin counters when the extra byte put the frame in the
6453     * wrong bin. Remember that the frame_len was adjusted above.
6454     */
6455    if (frame_len == 64) {
6456        stats->prc64++;
6457        stats->prc127--;
6458    } else if (frame_len == 127) {
6459        stats->prc127++;
6460        stats->prc255--;
6461    } else if (frame_len == 255) {
6462        stats->prc255++;
6463        stats->prc511--;
6464    } else if (frame_len == 511) {
6465        stats->prc511++;
6466        stats->prc1023--;
6467    } else if (frame_len == 1023) {
6468        stats->prc1023++;
6469        stats->prc1522--;
6470    } else if (frame_len == 1522) {
6471        stats->prc1522++;
6472    }
6473}
6474
6475/******************************************************************************
6476 * Gets the current PCI bus type, speed, and width of the hardware
6477 *
6478 * hw - Struct containing variables accessed by shared code
6479 *****************************************************************************/
6480void e1000_get_bus_info(struct e1000_hw *hw)
6481{
6482    s32 ret_val;
6483    u16 pci_ex_link_status;
6484    u32 status;
6485
6486    switch (hw->mac_type) {
6487    case e1000_82542_rev2_0:
6488    case e1000_82542_rev2_1:
6489        hw->bus_type = e1000_bus_type_pci;
6490        hw->bus_speed = e1000_bus_speed_unknown;
6491        hw->bus_width = e1000_bus_width_unknown;
6492        break;
6493    case e1000_82571:
6494    case e1000_82572:
6495    case e1000_82573:
6496    case e1000_80003es2lan:
6497        hw->bus_type = e1000_bus_type_pci_express;
6498        hw->bus_speed = e1000_bus_speed_2500;
6499        ret_val = e1000_read_pcie_cap_reg(hw,
6500                                      PCI_EX_LINK_STATUS,
6501                                      &pci_ex_link_status);
6502        if (ret_val)
6503            hw->bus_width = e1000_bus_width_unknown;
6504        else
6505            hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6506                          PCI_EX_LINK_WIDTH_SHIFT;
6507        break;
6508    case e1000_ich8lan:
6509        hw->bus_type = e1000_bus_type_pci_express;
6510        hw->bus_speed = e1000_bus_speed_2500;
6511        hw->bus_width = e1000_bus_width_pciex_1;
6512        break;
6513    default:
6514        status = er32(STATUS);
6515        hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6516                       e1000_bus_type_pcix : e1000_bus_type_pci;
6517
6518        if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6519            hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6520                            e1000_bus_speed_66 : e1000_bus_speed_120;
6521        } else if (hw->bus_type == e1000_bus_type_pci) {
6522            hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6523                            e1000_bus_speed_66 : e1000_bus_speed_33;
6524        } else {
6525            switch (status & E1000_STATUS_PCIX_SPEED) {
6526            case E1000_STATUS_PCIX_SPEED_66:
6527                hw->bus_speed = e1000_bus_speed_66;
6528                break;
6529            case E1000_STATUS_PCIX_SPEED_100:
6530                hw->bus_speed = e1000_bus_speed_100;
6531                break;
6532            case E1000_STATUS_PCIX_SPEED_133:
6533                hw->bus_speed = e1000_bus_speed_133;
6534                break;
6535            default:
6536                hw->bus_speed = e1000_bus_speed_reserved;
6537                break;
6538            }
6539        }
6540        hw->bus_width = (status & E1000_STATUS_BUS64) ?
6541                        e1000_bus_width_64 : e1000_bus_width_32;
6542        break;
6543    }
6544}
6545
6546/******************************************************************************
6547 * Writes a value to one of the devices registers using port I/O (as opposed to
6548 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6549 *
6550 * hw - Struct containing variables accessed by shared code
6551 * offset - offset to write to
6552 * value - value to write
6553 *****************************************************************************/
6554static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
6555{
6556    unsigned long io_addr = hw->io_base;
6557    unsigned long io_data = hw->io_base + 4;
6558
6559    e1000_io_write(hw, io_addr, offset);
6560    e1000_io_write(hw, io_data, value);
6561}
6562
6563/******************************************************************************
6564 * Estimates the cable length.
6565 *
6566 * hw - Struct containing variables accessed by shared code
6567 * min_length - The estimated minimum length
6568 * max_length - The estimated maximum length
6569 *
6570 * returns: - E1000_ERR_XXX
6571 *            E1000_SUCCESS
6572 *
6573 * This function always returns a ranged length (minimum & maximum).
6574 * So for M88 phy's, this function interprets the one value returned from the
6575 * register to the minimum and maximum range.
6576 * For IGP phy's, the function calculates the range by the AGC registers.
6577 *****************************************************************************/
6578static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
6579                                  u16 *max_length)
6580{
6581    s32 ret_val;
6582    u16 agc_value = 0;
6583    u16 i, phy_data;
6584    u16 cable_length;
6585
6586    DEBUGFUNC("e1000_get_cable_length");
6587
6588    *min_length = *max_length = 0;
6589
6590    /* Use old method for Phy older than IGP */
6591    if (hw->phy_type == e1000_phy_m88) {
6592
6593        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6594                                     &phy_data);
6595        if (ret_val)
6596            return ret_val;
6597        cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6598                       M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6599
6600        /* Convert the enum value to ranged values */
6601        switch (cable_length) {
6602        case e1000_cable_length_50:
6603            *min_length = 0;
6604            *max_length = e1000_igp_cable_length_50;
6605            break;
6606        case e1000_cable_length_50_80:
6607            *min_length = e1000_igp_cable_length_50;
6608            *max_length = e1000_igp_cable_length_80;
6609            break;
6610        case e1000_cable_length_80_110:
6611            *min_length = e1000_igp_cable_length_80;
6612            *max_length = e1000_igp_cable_length_110;
6613            break;
6614        case e1000_cable_length_110_140:
6615            *min_length = e1000_igp_cable_length_110;
6616            *max_length = e1000_igp_cable_length_140;
6617            break;
6618        case e1000_cable_length_140:
6619            *min_length = e1000_igp_cable_length_140;
6620            *max_length = e1000_igp_cable_length_170;
6621            break;
6622        default:
6623            return -E1000_ERR_PHY;
6624            break;
6625        }
6626    } else if (hw->phy_type == e1000_phy_gg82563) {
6627        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6628                                     &phy_data);
6629        if (ret_val)
6630            return ret_val;
6631        cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6632
6633        switch (cable_length) {
6634        case e1000_gg_cable_length_60:
6635            *min_length = 0;
6636            *max_length = e1000_igp_cable_length_60;
6637            break;
6638        case e1000_gg_cable_length_60_115:
6639            *min_length = e1000_igp_cable_length_60;
6640            *max_length = e1000_igp_cable_length_115;
6641            break;
6642        case e1000_gg_cable_length_115_150:
6643            *min_length = e1000_igp_cable_length_115;
6644            *max_length = e1000_igp_cable_length_150;
6645            break;
6646        case e1000_gg_cable_length_150:
6647            *min_length = e1000_igp_cable_length_150;
6648            *max_length = e1000_igp_cable_length_180;
6649            break;
6650        default:
6651            return -E1000_ERR_PHY;
6652            break;
6653        }
6654    } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6655        u16 cur_agc_value;
6656        u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6657        u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6658                                                         {IGP01E1000_PHY_AGC_A,
6659                                                          IGP01E1000_PHY_AGC_B,
6660                                                          IGP01E1000_PHY_AGC_C,
6661                                                          IGP01E1000_PHY_AGC_D};
6662        /* Read the AGC registers for all channels */
6663        for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6664
6665            ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6666            if (ret_val)
6667                return ret_val;
6668
6669            cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6670
6671            /* Value bound check. */
6672            if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6673                (cur_agc_value == 0))
6674                return -E1000_ERR_PHY;
6675
6676            agc_value += cur_agc_value;
6677
6678            /* Update minimal AGC value. */
6679            if (min_agc_value > cur_agc_value)
6680                min_agc_value = cur_agc_value;
6681        }
6682
6683        /* Remove the minimal AGC result for length < 50m */
6684        if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6685            agc_value -= min_agc_value;
6686
6687            /* Get the average length of the remaining 3 channels */
6688            agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6689        } else {
6690            /* Get the average length of all the 4 channels. */
6691            agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6692        }
6693
6694        /* Set the range of the calculated length. */
6695        *min_length = ((e1000_igp_cable_length_table[agc_value] -
6696                       IGP01E1000_AGC_RANGE) > 0) ?
6697                       (e1000_igp_cable_length_table[agc_value] -
6698                       IGP01E1000_AGC_RANGE) : 0;
6699        *max_length = e1000_igp_cable_length_table[agc_value] +
6700                      IGP01E1000_AGC_RANGE;
6701    } else if (hw->phy_type == e1000_phy_igp_2 ||
6702               hw->phy_type == e1000_phy_igp_3) {
6703        u16 cur_agc_index, max_agc_index = 0;
6704        u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6705        u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6706                                                         {IGP02E1000_PHY_AGC_A,
6707                                                          IGP02E1000_PHY_AGC_B,
6708                                                          IGP02E1000_PHY_AGC_C,
6709                                                          IGP02E1000_PHY_AGC_D};
6710        /* Read the AGC registers for all channels */
6711        for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6712            ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6713            if (ret_val)
6714                return ret_val;
6715
6716            /* Getting bits 15:9, which represent the combination of course and
6717             * fine gain values.  The result is a number that can be put into
6718             * the lookup table to obtain the approximate cable length. */
6719            cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6720                            IGP02E1000_AGC_LENGTH_MASK;
6721
6722            /* Array index bound check. */
6723            if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6724                (cur_agc_index == 0))
6725                return -E1000_ERR_PHY;
6726
6727            /* Remove min & max AGC values from calculation. */
6728            if (e1000_igp_2_cable_length_table[min_agc_index] >
6729                e1000_igp_2_cable_length_table[cur_agc_index])
6730                min_agc_index = cur_agc_index;
6731            if (e1000_igp_2_cable_length_table[max_agc_index] <
6732                e1000_igp_2_cable_length_table[cur_agc_index])
6733                max_agc_index = cur_agc_index;
6734
6735            agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6736        }
6737
6738        agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6739                      e1000_igp_2_cable_length_table[max_agc_index]);
6740        agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6741
6742        /* Calculate cable length with the error range of +/- 10 meters. */
6743        *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6744                       (agc_value - IGP02E1000_AGC_RANGE) : 0;
6745        *max_length = agc_value + IGP02E1000_AGC_RANGE;
6746    }
6747
6748    return E1000_SUCCESS;
6749}
6750
6751/******************************************************************************
6752 * Check the cable polarity
6753 *
6754 * hw - Struct containing variables accessed by shared code
6755 * polarity - output parameter : 0 - Polarity is not reversed
6756 *                               1 - Polarity is reversed.
6757 *
6758 * returns: - E1000_ERR_XXX
6759 *            E1000_SUCCESS
6760 *
6761 * For phy's older then IGP, this function simply reads the polarity bit in the
6762 * Phy Status register.  For IGP phy's, this bit is valid only if link speed is
6763 * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
6764 * return 0.  If the link speed is 1000 Mbps the polarity status is in the
6765 * IGP01E1000_PHY_PCS_INIT_REG.
6766 *****************************************************************************/
6767static s32 e1000_check_polarity(struct e1000_hw *hw,
6768                                e1000_rev_polarity *polarity)
6769{
6770    s32 ret_val;
6771    u16 phy_data;
6772
6773    DEBUGFUNC("e1000_check_polarity");
6774
6775    if ((hw->phy_type == e1000_phy_m88) ||
6776        (hw->phy_type == e1000_phy_gg82563)) {
6777        /* return the Polarity bit in the Status register. */
6778        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6779                                     &phy_data);
6780        if (ret_val)
6781            return ret_val;
6782        *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6783                     M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6784                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6785
6786    } else if (hw->phy_type == e1000_phy_igp ||
6787              hw->phy_type == e1000_phy_igp_3 ||
6788              hw->phy_type == e1000_phy_igp_2) {
6789        /* Read the Status register to check the speed */
6790        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6791                                     &phy_data);
6792        if (ret_val)
6793            return ret_val;
6794
6795        /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6796         * find the polarity status */
6797        if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6798           IGP01E1000_PSSR_SPEED_1000MBPS) {
6799
6800            /* Read the GIG initialization PCS register (0x00B4) */
6801            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6802                                         &phy_data);
6803            if (ret_val)
6804                return ret_val;
6805
6806            /* Check the polarity bits */
6807            *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6808                         e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6809        } else {
6810            /* For 10 Mbps, read the polarity bit in the status register. (for
6811             * 100 Mbps this bit is always 0) */
6812            *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6813                         e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6814        }
6815    } else if (hw->phy_type == e1000_phy_ife) {
6816        ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6817                                     &phy_data);
6818        if (ret_val)
6819            return ret_val;
6820        *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6821                     IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6822                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6823    }
6824    return E1000_SUCCESS;
6825}
6826
6827/******************************************************************************
6828 * Check if Downshift occured
6829 *
6830 * hw - Struct containing variables accessed by shared code
6831 * downshift - output parameter : 0 - No Downshift ocured.
6832 *                                1 - Downshift ocured.
6833 *
6834 * returns: - E1000_ERR_XXX
6835 *            E1000_SUCCESS
6836 *
6837 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6838 * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
6839 * Link Health register.  In IGP this bit is latched high, so the driver must
6840 * read it immediately after link is established.
6841 *****************************************************************************/
6842static s32 e1000_check_downshift(struct e1000_hw *hw)
6843{
6844    s32 ret_val;
6845    u16 phy_data;
6846
6847    DEBUGFUNC("e1000_check_downshift");
6848
6849    if (hw->phy_type == e1000_phy_igp ||
6850        hw->phy_type == e1000_phy_igp_3 ||
6851        hw->phy_type == e1000_phy_igp_2) {
6852        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6853                                     &phy_data);
6854        if (ret_val)
6855            return ret_val;
6856
6857        hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6858    } else if ((hw->phy_type == e1000_phy_m88) ||
6859               (hw->phy_type == e1000_phy_gg82563)) {
6860        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6861                                     &phy_data);
6862        if (ret_val)
6863            return ret_val;
6864
6865        hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6866                               M88E1000_PSSR_DOWNSHIFT_SHIFT;
6867    } else if (hw->phy_type == e1000_phy_ife) {
6868        /* e1000_phy_ife supports 10/100 speed only */
6869        hw->speed_downgraded = false;
6870    }
6871
6872    return E1000_SUCCESS;
6873}
6874
6875/*****************************************************************************
6876 *
6877 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6878 * gigabit link is achieved to improve link quality.
6879 *
6880 * hw: Struct containing variables accessed by shared code
6881 *
6882 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6883 *            E1000_SUCCESS at any other case.
6884 *
6885 ****************************************************************************/
6886
6887static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
6888{
6889    s32 ret_val;
6890    u16 phy_data, phy_saved_data, speed, duplex, i;
6891    u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6892                                        {IGP01E1000_PHY_AGC_PARAM_A,
6893                                        IGP01E1000_PHY_AGC_PARAM_B,
6894                                        IGP01E1000_PHY_AGC_PARAM_C,
6895                                        IGP01E1000_PHY_AGC_PARAM_D};
6896    u16 min_length, max_length;
6897
6898    DEBUGFUNC("e1000_config_dsp_after_link_change");
6899
6900    if (hw->phy_type != e1000_phy_igp)
6901        return E1000_SUCCESS;
6902
6903    if (link_up) {
6904        ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6905        if (ret_val) {
6906            DEBUGOUT("Error getting link speed and duplex\n");
6907            return ret_val;
6908        }
6909
6910        if (speed == SPEED_1000) {
6911
6912            ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6913            if (ret_val)
6914                return ret_val;
6915
6916            if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6917                min_length >= e1000_igp_cable_length_50) {
6918
6919                for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6920                    ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6921                                                 &phy_data);
6922                    if (ret_val)
6923                        return ret_val;
6924
6925                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6926
6927                    ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6928                                                  phy_data);
6929                    if (ret_val)
6930                        return ret_val;
6931                }
6932                hw->dsp_config_state = e1000_dsp_config_activated;
6933            }
6934
6935            if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6936               (min_length < e1000_igp_cable_length_50)) {
6937
6938                u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6939                u32 idle_errs = 0;
6940
6941                /* clear previous idle error counts */
6942                ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6943                                             &phy_data);
6944                if (ret_val)
6945                    return ret_val;
6946
6947                for (i = 0; i < ffe_idle_err_timeout; i++) {
6948                    udelay(1000);
6949                    ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6950                                                 &phy_data);
6951                    if (ret_val)
6952                        return ret_val;
6953
6954                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
6955                    if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
6956                        hw->ffe_config_state = e1000_ffe_config_active;
6957
6958                        ret_val = e1000_write_phy_reg(hw,
6959                                    IGP01E1000_PHY_DSP_FFE,
6960                                    IGP01E1000_PHY_DSP_FFE_CM_CP);
6961                        if (ret_val)
6962                            return ret_val;
6963                        break;
6964                    }
6965
6966                    if (idle_errs)
6967                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
6968                }
6969            }
6970        }
6971    } else {
6972        if (hw->dsp_config_state == e1000_dsp_config_activated) {
6973            /* Save off the current value of register 0x2F5B to be restored at
6974             * the end of the routines. */
6975            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6976
6977            if (ret_val)
6978                return ret_val;
6979
6980            /* Disable the PHY transmitter */
6981            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6982
6983            if (ret_val)
6984                return ret_val;
6985
6986            mdelay(20);
6987
6988            ret_val = e1000_write_phy_reg(hw, 0x0000,
6989                                          IGP01E1000_IEEE_FORCE_GIGA);
6990            if (ret_val)
6991                return ret_val;
6992            for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6993                ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
6994                if (ret_val)
6995                    return ret_val;
6996
6997                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6998                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
6999
7000                ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7001                if (ret_val)
7002                    return ret_val;
7003            }
7004
7005            ret_val = e1000_write_phy_reg(hw, 0x0000,
7006                                          IGP01E1000_IEEE_RESTART_AUTONEG);
7007            if (ret_val)
7008                return ret_val;
7009
7010            mdelay(20);
7011
7012            /* Now enable the transmitter */
7013            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7014
7015            if (ret_val)
7016                return ret_val;
7017
7018            hw->dsp_config_state = e1000_dsp_config_enabled;
7019        }
7020
7021        if (hw->ffe_config_state == e1000_ffe_config_active) {
7022            /* Save off the current value of register 0x2F5B to be restored at
7023             * the end of the routines. */
7024            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7025
7026            if (ret_val)
7027                return ret_val;
7028
7029            /* Disable the PHY transmitter */
7030            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7031
7032            if (ret_val)
7033                return ret_val;
7034
7035            mdelay(20);
7036
7037            ret_val = e1000_write_phy_reg(hw, 0x0000,
7038                                          IGP01E1000_IEEE_FORCE_GIGA);
7039            if (ret_val)
7040                return ret_val;
7041            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7042                                          IGP01E1000_PHY_DSP_FFE_DEFAULT);
7043            if (ret_val)
7044                return ret_val;
7045
7046            ret_val = e1000_write_phy_reg(hw, 0x0000,
7047                                          IGP01E1000_IEEE_RESTART_AUTONEG);
7048            if (ret_val)
7049                return ret_val;
7050
7051            mdelay(20);
7052
7053            /* Now enable the transmitter */
7054            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7055
7056            if (ret_val)
7057                return ret_val;
7058
7059            hw->ffe_config_state = e1000_ffe_config_enabled;
7060        }
7061    }
7062    return E1000_SUCCESS;
7063}
7064
7065/*****************************************************************************
7066 * Set PHY to class A mode
7067 * Assumes the following operations will follow to enable the new class mode.
7068 *  1. Do a PHY soft reset
7069 *  2. Restart auto-negotiation or force link.
7070 *
7071 * hw - Struct containing variables accessed by shared code
7072 ****************************************************************************/
7073static s32 e1000_set_phy_mode(struct e1000_hw *hw)
7074{
7075    s32 ret_val;
7076    u16 eeprom_data;
7077
7078    DEBUGFUNC("e1000_set_phy_mode");
7079
7080    if ((hw->mac_type == e1000_82545_rev_3) &&
7081        (hw->media_type == e1000_media_type_copper)) {
7082        ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7083        if (ret_val) {
7084            return ret_val;
7085        }
7086
7087        if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7088            (eeprom_data & EEPROM_PHY_CLASS_A)) {
7089            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7090            if (ret_val)
7091                return ret_val;
7092            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7093            if (ret_val)
7094                return ret_val;
7095
7096            hw->phy_reset_disable = false;
7097        }
7098    }
7099
7100    return E1000_SUCCESS;
7101}
7102
7103/*****************************************************************************
7104 *
7105 * This function sets the lplu state according to the active flag.  When
7106 * activating lplu this function also disables smart speed and vise versa.
7107 * lplu will not be activated unless the device autonegotiation advertisment
7108 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7109 * hw: Struct containing variables accessed by shared code
7110 * active - true to enable lplu false to disable lplu.
7111 *
7112 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7113 *            E1000_SUCCESS at any other case.
7114 *
7115 ****************************************************************************/
7116
7117static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7118{
7119    u32 phy_ctrl = 0;
7120    s32 ret_val;
7121    u16 phy_data;
7122    DEBUGFUNC("e1000_set_d3_lplu_state");
7123
7124    if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7125        && hw->phy_type != e1000_phy_igp_3)
7126        return E1000_SUCCESS;
7127
7128    /* During driver activity LPLU should not be used or it will attain link
7129     * from the lowest speeds starting from 10Mbps. The capability is used for
7130     * Dx transitions and states */
7131    if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7132        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7133        if (ret_val)
7134            return ret_val;
7135    } else if (hw->mac_type == e1000_ich8lan) {
7136        /* MAC writes into PHY register based on the state transition
7137         * and start auto-negotiation. SW driver can overwrite the settings
7138         * in CSR PHY power control E1000_PHY_CTRL register. */
7139        phy_ctrl = er32(PHY_CTRL);
7140    } else {
7141        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7142        if (ret_val)
7143            return ret_val;
7144    }
7145
7146    if (!active) {
7147        if (hw->mac_type == e1000_82541_rev_2 ||
7148            hw->mac_type == e1000_82547_rev_2) {
7149            phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7150            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7151            if (ret_val)
7152                return ret_val;
7153        } else {
7154            if (hw->mac_type == e1000_ich8lan) {
7155                phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7156                ew32(PHY_CTRL, phy_ctrl);
7157            } else {
7158                phy_data &= ~IGP02E1000_PM_D3_LPLU;
7159                ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7160                                              phy_data);
7161                if (ret_val)
7162                    return ret_val;
7163            }
7164        }
7165
7166        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
7167         * Dx states where the power conservation is most important.  During
7168         * driver activity we should enable SmartSpeed, so performance is
7169         * maintained. */
7170        if (hw->smart_speed == e1000_smart_speed_on) {
7171            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7172                                         &phy_data);
7173            if (ret_val)
7174                return ret_val;
7175
7176            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7177            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7178                                          phy_data);
7179            if (ret_val)
7180                return ret_val;
7181        } else if (hw->smart_speed == e1000_smart_speed_off) {
7182            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7183                                         &phy_data);
7184            if (ret_val)
7185                return ret_val;
7186
7187            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7188            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7189                                          phy_data);
7190            if (ret_val)
7191                return ret_val;
7192        }
7193
7194    } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7195               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7196               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7197
7198        if (hw->mac_type == e1000_82541_rev_2 ||
7199            hw->mac_type == e1000_82547_rev_2) {
7200            phy_data |= IGP01E1000_GMII_FLEX_SPD;
7201            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7202            if (ret_val)
7203                return ret_val;
7204        } else {
7205            if (hw->mac_type == e1000_ich8lan) {
7206                phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7207                ew32(PHY_CTRL, phy_ctrl);
7208            } else {
7209                phy_data |= IGP02E1000_PM_D3_LPLU;
7210                ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7211                                              phy_data);
7212                if (ret_val)
7213                    return ret_val;
7214            }
7215        }
7216
7217        /* When LPLU is enabled we should disable SmartSpeed */
7218        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7219        if (ret_val)
7220            return ret_val;
7221
7222        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7223        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7224        if (ret_val)
7225            return ret_val;
7226
7227    }
7228    return E1000_SUCCESS;
7229}
7230
7231/*****************************************************************************
7232 *
7233 * This function sets the lplu d0 state according to the active flag.  When
7234 * activating lplu this function also disables smart speed and vise versa.
7235 * lplu will not be activated unless the device autonegotiation advertisment
7236 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7237 * hw: Struct containing variables accessed by shared code
7238 * active - true to enable lplu false to disable lplu.
7239 *
7240 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7241 *            E1000_SUCCESS at any other case.
7242 *
7243 ****************************************************************************/
7244
7245static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7246{
7247    u32 phy_ctrl = 0;
7248    s32 ret_val;
7249    u16 phy_data;
7250    DEBUGFUNC("e1000_set_d0_lplu_state");
7251
7252    if (hw->mac_type <= e1000_82547_rev_2)
7253        return E1000_SUCCESS;
7254
7255    if (hw->mac_type == e1000_ich8lan) {
7256        phy_ctrl = er32(PHY_CTRL);
7257    } else {
7258        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7259        if (ret_val)
7260            return ret_val;
7261    }
7262
7263    if (!active) {
7264        if (hw->mac_type == e1000_ich8lan) {
7265            phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7266            ew32(PHY_CTRL, phy_ctrl);
7267        } else {
7268            phy_data &= ~IGP02E1000_PM_D0_LPLU;
7269            ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7270            if (ret_val)
7271                return ret_val;
7272        }
7273
7274        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
7275         * Dx states where the power conservation is most important.  During
7276         * driver activity we should enable SmartSpeed, so performance is
7277         * maintained. */
7278        if (hw->smart_speed == e1000_smart_speed_on) {
7279            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7280                                         &phy_data);
7281            if (ret_val)
7282                return ret_val;
7283
7284            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7285            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7286                                          phy_data);
7287            if (ret_val)
7288                return ret_val;
7289        } else if (hw->smart_speed == e1000_smart_speed_off) {
7290            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7291                                         &phy_data);
7292            if (ret_val)
7293                return ret_val;
7294
7295            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7296            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7297                                          phy_data);
7298            if (ret_val)
7299                return ret_val;
7300        }
7301
7302
7303    } else {
7304
7305        if (hw->mac_type == e1000_ich8lan) {
7306            phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7307            ew32(PHY_CTRL, phy_ctrl);
7308        } else {
7309            phy_data |= IGP02E1000_PM_D0_LPLU;
7310            ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7311            if (ret_val)
7312                return ret_val;
7313        }
7314
7315        /* When LPLU is enabled we should disable SmartSpeed */
7316        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7317        if (ret_val)
7318            return ret_val;
7319
7320        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7321        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7322        if (ret_val)
7323            return ret_val;
7324
7325    }
7326    return E1000_SUCCESS;
7327}
7328
7329/******************************************************************************
7330 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7331 *
7332 * hw - Struct containing variables accessed by shared code
7333 *****************************************************************************/
7334static s32 e1000_set_vco_speed(struct e1000_hw *hw)
7335{
7336    s32  ret_val;
7337    u16 default_page = 0;
7338    u16 phy_data;
7339
7340    DEBUGFUNC("e1000_set_vco_speed");
7341
7342    switch (hw->mac_type) {
7343    case e1000_82545_rev_3:
7344    case e1000_82546_rev_3:
7345       break;
7346    default:
7347        return E1000_SUCCESS;
7348    }
7349
7350    /* Set PHY register 30, page 5, bit 8 to 0 */
7351
7352    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7353    if (ret_val)
7354        return ret_val;
7355
7356    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7357    if (ret_val)
7358        return ret_val;
7359
7360    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7361    if (ret_val)
7362        return ret_val;
7363
7364    phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7365    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7366    if (ret_val)
7367        return ret_val;
7368
7369    /* Set PHY register 30, page 4, bit 11 to 1 */
7370
7371    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7372    if (ret_val)
7373        return ret_val;
7374
7375    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7376    if (ret_val)
7377        return ret_val;
7378
7379    phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7380    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7381    if (ret_val)
7382        return ret_val;
7383
7384    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7385    if (ret_val)
7386        return ret_val;
7387
7388    return E1000_SUCCESS;
7389}
7390
7391
7392/*****************************************************************************
7393 * This function reads the cookie from ARC ram.
7394 *
7395 * returns: - E1000_SUCCESS .
7396 ****************************************************************************/
7397static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer)
7398{
7399    u8 i;
7400    u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7401    u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
7402
7403    length = (length >> 2);
7404    offset = (offset >> 2);
7405
7406    for (i = 0; i < length; i++) {
7407        *((u32 *)buffer + i) =
7408            E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7409    }
7410    return E1000_SUCCESS;
7411}
7412
7413
7414/*****************************************************************************
7415 * This function checks whether the HOST IF is enabled for command operaton
7416 * and also checks whether the previous command is completed.
7417 * It busy waits in case of previous command is not completed.
7418 *
7419 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7420 *            timeout
7421 *          - E1000_SUCCESS for success.
7422 ****************************************************************************/
7423static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7424{
7425    u32 hicr;
7426    u8 i;
7427
7428    /* Check that the host interface is enabled. */
7429    hicr = er32(HICR);
7430    if ((hicr & E1000_HICR_EN) == 0) {
7431        DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7432        return -E1000_ERR_HOST_INTERFACE_COMMAND;
7433    }
7434    /* check the previous command is completed */
7435    for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7436        hicr = er32(HICR);
7437        if (!(hicr & E1000_HICR_C))
7438            break;
7439        mdelay(1);
7440    }
7441
7442    if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7443        DEBUGOUT("Previous command timeout failed .\n");
7444        return -E1000_ERR_HOST_INTERFACE_COMMAND;
7445    }
7446    return E1000_SUCCESS;
7447}
7448
7449/*****************************************************************************
7450 * This function writes the buffer content at the offset given on the host if.
7451 * It also does alignment considerations to do the writes in most efficient way.
7452 * Also fills up the sum of the buffer in *buffer parameter.
7453 *
7454 * returns  - E1000_SUCCESS for success.
7455 ****************************************************************************/
7456static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
7457                                   u16 offset, u8 *sum)
7458{
7459    u8 *tmp;
7460    u8 *bufptr = buffer;
7461    u32 data = 0;
7462    u16 remaining, i, j, prev_bytes;
7463
7464    /* sum = only sum of the data and it is not checksum */
7465
7466    if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7467        return -E1000_ERR_PARAM;
7468    }
7469
7470    tmp = (u8 *)&data;
7471    prev_bytes = offset & 0x3;
7472    offset &= 0xFFFC;
7473    offset >>= 2;
7474
7475    if (prev_bytes) {
7476        data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7477        for (j = prev_bytes; j < sizeof(u32); j++) {
7478            *(tmp + j) = *bufptr++;
7479            *sum += *(tmp + j);
7480        }
7481        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7482        length -= j - prev_bytes;
7483        offset++;
7484    }
7485
7486    remaining = length & 0x3;
7487    length -= remaining;
7488
7489    /* Calculate length in DWORDs */
7490    length >>= 2;
7491
7492    /* The device driver writes the relevant command block into the
7493     * ram area. */
7494    for (i = 0; i < length; i++) {
7495        for (j = 0; j < sizeof(u32); j++) {
7496            *(tmp + j) = *bufptr++;
7497            *sum += *(tmp + j);
7498        }
7499
7500        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7501    }
7502    if (remaining) {
7503        for (j = 0; j < sizeof(u32); j++) {
7504            if (j < remaining)
7505                *(tmp + j) = *bufptr++;
7506            else
7507                *(tmp + j) = 0;
7508
7509            *sum += *(tmp + j);
7510        }
7511        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7512    }
7513
7514    return E1000_SUCCESS;
7515}
7516
7517
7518/*****************************************************************************
7519 * This function writes the command header after does the checksum calculation.
7520 *
7521 * returns  - E1000_SUCCESS for success.
7522 ****************************************************************************/
7523static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
7524                                      struct e1000_host_mng_command_header *hdr)
7525{
7526    u16 i;
7527    u8 sum;
7528    u8 *buffer;
7529
7530    /* Write the whole command header structure which includes sum of
7531     * the buffer */
7532
7533    u16 length = sizeof(struct e1000_host_mng_command_header);
7534
7535    sum = hdr->checksum;
7536    hdr->checksum = 0;
7537
7538    buffer = (u8 *)hdr;
7539    i = length;
7540    while (i--)
7541        sum += buffer[i];
7542
7543    hdr->checksum = 0 - sum;
7544
7545    length >>= 2;
7546    /* The device driver writes the relevant command block into the ram area. */
7547    for (i = 0; i < length; i++) {
7548        E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i));
7549        E1000_WRITE_FLUSH();
7550    }
7551
7552    return E1000_SUCCESS;
7553}
7554
7555
7556/*****************************************************************************
7557 * This function indicates to ARC that a new command is pending which completes
7558 * one write operation by the driver.
7559 *
7560 * returns  - E1000_SUCCESS for success.
7561 ****************************************************************************/
7562static s32 e1000_mng_write_commit(struct e1000_hw *hw)
7563{
7564    u32 hicr;
7565
7566    hicr = er32(HICR);
7567    /* Setting this bit tells the ARC that a new command is pending. */
7568    ew32(HICR, hicr | E1000_HICR_C);
7569
7570    return E1000_SUCCESS;
7571}
7572
7573
7574/*****************************************************************************
7575 * This function checks the mode of the firmware.
7576 *
7577 * returns  - true when the mode is IAMT or false.
7578 ****************************************************************************/
7579bool e1000_check_mng_mode(struct e1000_hw *hw)
7580{
7581    u32 fwsm;
7582
7583    fwsm = er32(FWSM);
7584
7585    if (hw->mac_type == e1000_ich8lan) {
7586        if ((fwsm & E1000_FWSM_MODE_MASK) ==
7587            (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7588            return true;
7589    } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7590               (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7591        return true;
7592
7593    return false;
7594}
7595
7596
7597/*****************************************************************************
7598 * This function writes the dhcp info .
7599 ****************************************************************************/
7600s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
7601{
7602    s32 ret_val;
7603    struct e1000_host_mng_command_header hdr;
7604
7605    hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7606    hdr.command_length = length;
7607    hdr.reserved1 = 0;
7608    hdr.reserved2 = 0;
7609    hdr.checksum = 0;
7610
7611    ret_val = e1000_mng_enable_host_if(hw);
7612    if (ret_val == E1000_SUCCESS) {
7613        ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7614                                          &(hdr.checksum));
7615        if (ret_val == E1000_SUCCESS) {
7616            ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7617            if (ret_val == E1000_SUCCESS)
7618                ret_val = e1000_mng_write_commit(hw);
7619        }
7620    }
7621    return ret_val;
7622}
7623
7624
7625/*****************************************************************************
7626 * This function calculates the checksum.
7627 *
7628 * returns  - checksum of buffer contents.
7629 ****************************************************************************/
7630static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
7631{
7632    u8 sum = 0;
7633    u32 i;
7634
7635    if (!buffer)
7636        return 0;
7637
7638    for (i=0; i < length; i++)
7639        sum += buffer[i];
7640
7641    return (u8)(0 - sum);
7642}
7643
7644/*****************************************************************************
7645 * This function checks whether tx pkt filtering needs to be enabled or not.
7646 *
7647 * returns  - true for packet filtering or false.
7648 ****************************************************************************/
7649bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7650{
7651    /* called in init as well as watchdog timer functions */
7652
7653    s32 ret_val, checksum;
7654    bool tx_filter = false;
7655    struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7656    u8 *buffer = (u8 *) &(hw->mng_cookie);
7657
7658    if (e1000_check_mng_mode(hw)) {
7659        ret_val = e1000_mng_enable_host_if(hw);
7660        if (ret_val == E1000_SUCCESS) {
7661            ret_val = e1000_host_if_read_cookie(hw, buffer);
7662            if (ret_val == E1000_SUCCESS) {
7663                checksum = hdr->checksum;
7664                hdr->checksum = 0;
7665                if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7666                    checksum == e1000_calculate_mng_checksum((char *)buffer,
7667                                               E1000_MNG_DHCP_COOKIE_LENGTH)) {
7668                    if (hdr->status &
7669                        E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7670                        tx_filter = true;
7671                } else
7672                    tx_filter = true;
7673            } else
7674                tx_filter = true;
7675        }
7676    }
7677
7678    hw->tx_pkt_filtering = tx_filter;
7679    return tx_filter;
7680}
7681
7682/******************************************************************************
7683 * Verifies the hardware needs to allow ARPs to be processed by the host
7684 *
7685 * hw - Struct containing variables accessed by shared code
7686 *
7687 * returns: - true/false
7688 *
7689 *****************************************************************************/
7690u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7691{
7692    u32 manc;
7693    u32 fwsm, factps;
7694
7695    if (hw->asf_firmware_present) {
7696        manc = er32(MANC);
7697
7698        if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7699            !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7700            return false;
7701        if (e1000_arc_subsystem_valid(hw)) {
7702            fwsm = er32(FWSM);
7703            factps = er32(FACTPS);
7704
7705            if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7706                   e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7707                return true;
7708        } else
7709            if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7710                return true;
7711    }
7712    return false;
7713}
7714
7715static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7716{
7717    s32 ret_val;
7718    u16 mii_status_reg;
7719    u16 i;
7720
7721    /* Polarity reversal workaround for forced 10F/10H links. */
7722
7723    /* Disable the transmitter on the PHY */
7724
7725    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7726    if (ret_val)
7727        return ret_val;
7728    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7729    if (ret_val)
7730        return ret_val;
7731
7732    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7733    if (ret_val)
7734        return ret_val;
7735
7736    /* This loop will early-out if the NO link condition has been met. */
7737    for (i = PHY_FORCE_TIME; i > 0; i--) {
7738        /* Read the MII Status Register and wait for Link Status bit
7739         * to be clear.
7740         */
7741
7742        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7743        if (ret_val)
7744            return ret_val;
7745
7746        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7747        if (ret_val)
7748            return ret_val;
7749
7750        if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7751        mdelay(100);
7752    }
7753
7754    /* Recommended delay time after link has been lost */
7755    mdelay(1000);
7756
7757    /* Now we will re-enable th transmitter on the PHY */
7758
7759    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7760    if (ret_val)
7761        return ret_val;
7762    mdelay(50);
7763    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7764    if (ret_val)
7765        return ret_val;
7766    mdelay(50);
7767    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7768    if (ret_val)
7769        return ret_val;
7770    mdelay(50);
7771    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7772    if (ret_val)
7773        return ret_val;
7774
7775    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7776    if (ret_val)
7777        return ret_val;
7778
7779    /* This loop will early-out if the link condition has been met. */
7780    for (i = PHY_FORCE_TIME; i > 0; i--) {
7781        /* Read the MII Status Register and wait for Link Status bit
7782         * to be set.
7783         */
7784
7785        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7786        if (ret_val)
7787            return ret_val;
7788
7789        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7790        if (ret_val)
7791            return ret_val;
7792
7793        if (mii_status_reg & MII_SR_LINK_STATUS) break;
7794        mdelay(100);
7795    }
7796    return E1000_SUCCESS;
7797}
7798
7799/***************************************************************************
7800 *
7801 * Disables PCI-Express master access.
7802 *
7803 * hw: Struct containing variables accessed by shared code
7804 *
7805 * returns: - none.
7806 *
7807 ***************************************************************************/
7808static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7809{
7810    u32 ctrl;
7811
7812    DEBUGFUNC("e1000_set_pci_express_master_disable");
7813
7814    if (hw->bus_type != e1000_bus_type_pci_express)
7815        return;
7816
7817    ctrl = er32(CTRL);
7818    ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7819    ew32(CTRL, ctrl);
7820}
7821
7822/*******************************************************************************
7823 *
7824 * Disables PCI-Express master access and verifies there are no pending requests
7825 *
7826 * hw: Struct containing variables accessed by shared code
7827 *
7828 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7829 *            caused the master requests to be disabled.
7830 *            E1000_SUCCESS master requests disabled.
7831 *
7832 ******************************************************************************/
7833s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7834{
7835    s32 timeout = MASTER_DISABLE_TIMEOUT;   /* 80ms */
7836
7837    DEBUGFUNC("e1000_disable_pciex_master");
7838
7839    if (hw->bus_type != e1000_bus_type_pci_express)
7840        return E1000_SUCCESS;
7841
7842    e1000_set_pci_express_master_disable(hw);
7843
7844    while (timeout) {
7845        if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7846            break;
7847        else
7848            udelay(100);
7849        timeout--;
7850    }
7851
7852    if (!timeout) {
7853        DEBUGOUT("Master requests are pending.\n");
7854        return -E1000_ERR_MASTER_REQUESTS_PENDING;
7855    }
7856
7857    return E1000_SUCCESS;
7858}
7859
7860/*******************************************************************************
7861 *
7862 * Check for EEPROM Auto Read bit done.
7863 *
7864 * hw: Struct containing variables accessed by shared code
7865 *
7866 * returns: - E1000_ERR_RESET if fail to reset MAC
7867 *            E1000_SUCCESS at any other case.
7868 *
7869 ******************************************************************************/
7870static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7871{
7872    s32 timeout = AUTO_READ_DONE_TIMEOUT;
7873
7874    DEBUGFUNC("e1000_get_auto_rd_done");
7875
7876    switch (hw->mac_type) {
7877    default:
7878        msleep(5);
7879        break;
7880    case e1000_82571:
7881    case e1000_82572:
7882    case e1000_82573:
7883    case e1000_80003es2lan:
7884    case e1000_ich8lan:
7885        while (timeout) {
7886            if (er32(EECD) & E1000_EECD_AUTO_RD)
7887                break;
7888