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21#include "core.h"
22
23#define BITS_PER_BYTE 8
24#define OFDM_PLCP_BITS 22
25#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
27#define L_STF 8
28#define L_LTF 8
29#define L_SIG 4
30#define HT_SIG 8
31#define HT_STF 4
32#define HT_LTF(_ns) (4 * (_ns))
33#define SYMBOL_TIME(_ns) ((_ns) << 2)
34#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
35#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
37
38#define OFDM_SIFS_TIME 16
39
40static u32 bits_per_symbol[][2] = {
41
42 { 26, 54 },
43 { 52, 108 },
44 { 78, 162 },
45 { 104, 216 },
46 { 156, 324 },
47 { 208, 432 },
48 { 234, 486 },
49 { 260, 540 },
50 { 52, 108 },
51 { 104, 216 },
52 { 156, 324 },
53 { 208, 432 },
54 { 312, 648 },
55 { 416, 864 },
56 { 468, 972 },
57 { 520, 1080 },
58};
59
60#define IS_HT_RATE(_rate) ((_rate) & 0x80)
61
62
63
64
65
66
67
68static void ath_tx_txqaddbuf(struct ath_softc *sc,
69 struct ath_txq *txq, struct list_head *head)
70{
71 struct ath_hal *ah = sc->sc_ah;
72 struct ath_buf *bf;
73
74
75
76
77
78 if (list_empty(head))
79 return;
80
81 bf = list_first_entry(head, struct ath_buf, list);
82
83 list_splice_tail_init(head, &txq->axq_q);
84 txq->axq_depth++;
85 txq->axq_totalqueued++;
86 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
87
88 DPRINTF(sc, ATH_DBG_QUEUE,
89 "%s: txq depth = %d\n", __func__, txq->axq_depth);
90
91 if (txq->axq_link == NULL) {
92 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
93 DPRINTF(sc, ATH_DBG_XMIT,
94 "%s: TXDP[%u] = %llx (%p)\n",
95 __func__, txq->axq_qnum,
96 ito64(bf->bf_daddr), bf->bf_desc);
97 } else {
98 *txq->axq_link = bf->bf_daddr;
99 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
100 __func__,
101 txq->axq_qnum, txq->axq_link,
102 ito64(bf->bf_daddr), bf->bf_desc);
103 }
104 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
105 ath9k_hw_txstart(ah, txq->axq_qnum);
106}
107
108
109
110static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
111{
112 int i;
113 int ndx = 0;
114
115 for (i = 0; i < rt->rateCount; i++) {
116 if (rt->info[i].rateKbps == rate) {
117 ndx = i;
118 break;
119 }
120 }
121
122 return ndx;
123}
124
125
126
127static int ath_aggr_query(struct ath_softc *sc,
128 struct ath_node *an, u8 tidno)
129{
130 struct ath_atx_tid *tid;
131 tid = ATH_AN_2_TID(an, tidno);
132
133 if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress)
134 return 1;
135 else
136 return 0;
137}
138
139static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
140{
141 enum ath9k_pkt_type htype;
142 __le16 fc;
143
144 fc = hdr->frame_control;
145
146
147
148 if (ieee80211_is_beacon(fc))
149 htype = ATH9K_PKT_TYPE_BEACON;
150 else if (ieee80211_is_probe_resp(fc))
151 htype = ATH9K_PKT_TYPE_PROBE_RESP;
152 else if (ieee80211_is_atim(fc))
153 htype = ATH9K_PKT_TYPE_ATIM;
154 else if (ieee80211_is_pspoll(fc))
155 htype = ATH9K_PKT_TYPE_PSPOLL;
156 else
157 htype = ATH9K_PKT_TYPE_NORMAL;
158
159 return htype;
160}
161
162static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
163{
164 struct ieee80211_hdr *hdr;
165 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
166 struct ath_tx_info_priv *tx_info_priv;
167 __le16 fc;
168
169 hdr = (struct ieee80211_hdr *)skb->data;
170 fc = hdr->frame_control;
171 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
172
173 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
174 txctl->use_minrate = 1;
175 txctl->min_rate = tx_info_priv->min_rate;
176 } else if (ieee80211_is_data(fc)) {
177 if (ieee80211_is_nullfunc(fc) ||
178
179 (skb->protocol == cpu_to_be16(0x888E))) {
180 txctl->use_minrate = 1;
181 txctl->min_rate = tx_info_priv->min_rate;
182 }
183 if (is_multicast_ether_addr(hdr->addr1))
184 txctl->mcast_rate = tx_info_priv->min_rate;
185 }
186
187}
188
189
190
191static int ath_tx_prepare(struct ath_softc *sc,
192 struct sk_buff *skb,
193 struct ath_tx_control *txctl)
194{
195 struct ieee80211_hw *hw = sc->hw;
196 struct ieee80211_hdr *hdr;
197 struct ath_rc_series *rcs;
198 struct ath_txq *txq = NULL;
199 const struct ath9k_rate_table *rt;
200 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
201 struct ath_tx_info_priv *tx_info_priv;
202 int hdrlen;
203 u8 rix, antenna;
204 __le16 fc;
205 u8 *qc;
206
207 txctl->dev = sc;
208 hdr = (struct ieee80211_hdr *)skb->data;
209 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
210 fc = hdr->frame_control;
211
212 rt = sc->sc_currates;
213 BUG_ON(!rt);
214
215
216
217 spin_lock_bh(&sc->node_lock);
218 txctl->an = ath_node_get(sc, hdr->addr1);
219
220 if (!txctl->an)
221 txctl->an = ath_node_attach(sc, hdr->addr1, 0);
222 spin_unlock_bh(&sc->node_lock);
223
224 if (ieee80211_is_data_qos(fc)) {
225 qc = ieee80211_get_qos_ctl(hdr);
226 txctl->tidno = qc[0] & 0xf;
227 }
228
229 txctl->if_id = 0;
230 txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3);
231 txctl->txpower = MAX_RATE_POWER;
232
233
234
235 txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
236 txctl->keyix = ATH9K_TXKEYIX_INVALID;
237
238 if (tx_info->control.hw_key) {
239 txctl->keyix = tx_info->control.hw_key->hw_key_idx;
240 txctl->frmlen += tx_info->control.hw_key->icv_len;
241
242 if (tx_info->control.hw_key->alg == ALG_WEP)
243 txctl->keytype = ATH9K_KEY_TYPE_WEP;
244 else if (tx_info->control.hw_key->alg == ALG_TKIP)
245 txctl->keytype = ATH9K_KEY_TYPE_TKIP;
246 else if (tx_info->control.hw_key->alg == ALG_CCMP)
247 txctl->keytype = ATH9K_KEY_TYPE_AES;
248 }
249
250
251
252 txctl->atype = get_hal_packet_type(hdr);
253
254
255
256 if (unlikely(txctl->flags & ATH9K_TXDESC_CAB)) {
257 txctl->qnum = 0;
258 txq = sc->sc_cabq;
259 } else {
260 txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
261 txq = &sc->sc_txq[txctl->qnum];
262 }
263 spin_lock_bh(&txq->axq_lock);
264
265
266 if (txq->axq_depth >= (ATH_TXBUF - 20) &&
267 !(txctl->flags & ATH9K_TXDESC_CAB)) {
268 DPRINTF(sc, ATH_DBG_FATAL,
269 "%s: TX queue: %d is full, depth: %d\n",
270 __func__,
271 txctl->qnum,
272 txq->axq_depth);
273 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
274 txq->stopped = 1;
275 spin_unlock_bh(&txq->axq_lock);
276 return -1;
277 }
278
279 spin_unlock_bh(&txq->axq_lock);
280
281
282
283 fill_min_rates(skb, txctl);
284
285
286
287 txctl->flags |= ATH9K_TXDESC_CLRDMASK;
288
289 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
290 txctl->flags |= ATH9K_TXDESC_NOACK;
291 if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
292 txctl->flags |= ATH9K_TXDESC_RTSENA;
293
294
295
296
297 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
298 rcs = tx_info_priv->rcs;
299
300 if (ieee80211_is_data(fc) && !txctl->use_minrate) {
301
302
303 txctl->ht = (hw->conf.ht_conf.ht_supported &&
304 (tx_info->flags & IEEE80211_TX_CTL_AMPDU));
305
306 if (is_multicast_ether_addr(hdr->addr1)) {
307 rcs[0].rix = (u8)
308 ath_tx_findindex(rt, txctl->mcast_rate);
309
310
311
312
313 rcs[0].tries = 1;
314 }
315
316
317
318
319
320
321
322
323
324 if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
325 txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
326 struct ath_atx_tid *tid;
327
328 tid = ATH_AN_2_TID(txctl->an, txctl->tidno);
329
330 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
331 IEEE80211_SEQ_SEQ_SHIFT);
332 txctl->seqno = tid->seq_next;
333 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
334 }
335 } else {
336
337
338 if (txctl->min_rate)
339 rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate);
340 else
341 rcs[0].rix = 0;
342 rcs[0].tries = ATH_MGT_TXMAXTRY;
343 }
344 rix = rcs[0].rix;
345
346 if (ieee80211_has_morefrags(fc) ||
347 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
348
349
350
351
352
353
354 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
355 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
356
357 rcs[0].tries = ATH_TXMAXTRY;
358 }
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375 spin_lock_bh(&txq->axq_lock);
376 if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
377 txctl->flags |= ATH9K_TXDESC_INTREQ;
378 txq->axq_intrcnt = 0;
379 }
380 spin_unlock_bh(&txq->axq_lock);
381
382 if (is_multicast_ether_addr(hdr->addr1)) {
383 antenna = sc->sc_mcastantenna + 1;
384 sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
385 }
386
387 return 0;
388}
389
390
391
392static void ath_tx_complete_buf(struct ath_softc *sc,
393 struct ath_buf *bf,
394 struct list_head *bf_q,
395 int txok, int sendbar)
396{
397 struct sk_buff *skb = bf->bf_mpdu;
398 struct ath_xmit_status tx_status;
399
400
401
402
403
404
405 tx_status.retries = bf->bf_retries;
406 tx_status.flags = 0;
407
408 if (sendbar)
409 tx_status.flags = ATH_TX_BAR;
410
411 if (!txok) {
412 tx_status.flags |= ATH_TX_ERROR;
413
414 if (bf_isxretried(bf))
415 tx_status.flags |= ATH_TX_XRETRY;
416 }
417
418 pci_unmap_single(sc->pdev,
419 bf->bf_dmacontext,
420 skb->len,
421 PCI_DMA_TODEVICE);
422
423 ath_tx_complete(sc, skb, &tx_status, bf->bf_node);
424
425
426
427
428 spin_lock_bh(&sc->sc_txbuflock);
429 list_splice_tail_init(bf_q, &sc->sc_txbuf);
430 spin_unlock_bh(&sc->sc_txbuflock);
431}
432
433
434
435
436
437
438static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
439{
440 struct ath_atx_ac *ac = tid->ac;
441
442
443
444
445 if (tid->paused)
446 return;
447
448
449
450
451 if (tid->sched)
452 return;
453
454 tid->sched = true;
455 list_add_tail(&tid->list, &ac->tid_q);
456
457
458
459
460 if (ac->sched)
461 return;
462
463 ac->sched = true;
464 list_add_tail(&ac->list, &txq->axq_acq);
465}
466
467
468
469static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
470{
471 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
472
473 spin_lock_bh(&txq->axq_lock);
474
475 tid->paused++;
476
477 spin_unlock_bh(&txq->axq_lock);
478}
479
480
481
482void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
483{
484 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
485
486 ASSERT(tid->paused > 0);
487 spin_lock_bh(&txq->axq_lock);
488
489 tid->paused--;
490
491 if (tid->paused > 0)
492 goto unlock;
493
494 if (list_empty(&tid->buf_q))
495 goto unlock;
496
497
498
499
500 ath_tx_queue_tid(txq, tid);
501 ath_txq_schedule(sc, txq);
502unlock:
503 spin_unlock_bh(&txq->axq_lock);
504}
505
506
507
508static int ath_tx_num_badfrms(struct ath_softc *sc,
509 struct ath_buf *bf, int txok)
510{
511 struct ath_node *an = bf->bf_node;
512 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
513 struct ath_buf *bf_last = bf->bf_lastbf;
514 struct ath_desc *ds = bf_last->bf_desc;
515 u16 seq_st = 0;
516 u32 ba[WME_BA_BMP_SIZE >> 5];
517 int ba_index;
518 int nbad = 0;
519 int isaggr = 0;
520
521 if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
522 return 0;
523
524 isaggr = bf_isaggr(bf);
525 if (isaggr) {
526 seq_st = ATH_DS_BA_SEQ(ds);
527 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
528 }
529
530 while (bf) {
531 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
532 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
533 nbad++;
534
535 bf = bf->bf_next;
536 }
537
538 return nbad;
539}
540
541static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
542{
543 struct sk_buff *skb;
544 struct ieee80211_hdr *hdr;
545
546 bf->bf_state.bf_type |= BUF_RETRY;
547 bf->bf_retries++;
548
549 skb = bf->bf_mpdu;
550 hdr = (struct ieee80211_hdr *)skb->data;
551 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
552}
553
554
555
556static void ath_tx_update_baw(struct ath_softc *sc,
557 struct ath_atx_tid *tid, int seqno)
558{
559 int index, cindex;
560
561 index = ATH_BA_INDEX(tid->seq_start, seqno);
562 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
563
564 tid->tx_buf[cindex] = NULL;
565
566 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
567 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
568 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
569 }
570}
571
572
573
574
575
576
577
578
579
580
581static u32 ath_pkt_duration(struct ath_softc *sc,
582 u8 rix,
583 struct ath_buf *bf,
584 int width,
585 int half_gi,
586 bool shortPreamble)
587{
588 const struct ath9k_rate_table *rt = sc->sc_currates;
589 u32 nbits, nsymbits, duration, nsymbols;
590 u8 rc;
591 int streams, pktlen;
592
593 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
594 rc = rt->info[rix].rateCode;
595
596
597
598
599 if (!IS_HT_RATE(rc))
600 return ath9k_hw_computetxtime(sc->sc_ah,
601 rt,
602 pktlen,
603 rix,
604 shortPreamble);
605
606
607
608 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
609 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
610 nsymbols = (nbits + nsymbits - 1) / nsymbits;
611
612 if (!half_gi)
613 duration = SYMBOL_TIME(nsymbols);
614 else
615 duration = SYMBOL_TIME_HALFGI(nsymbols);
616
617
618
619
620 streams = HT_RC_2_STREAMS(rc);
621 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
622 return duration;
623}
624
625
626
627static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
628{
629 struct ath_hal *ah = sc->sc_ah;
630 const struct ath9k_rate_table *rt;
631 struct ath_desc *ds = bf->bf_desc;
632 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
633 struct ath9k_11n_rate_series series[4];
634 int i, flags, rtsctsena = 0, dynamic_mimops = 0;
635 u32 ctsduration = 0;
636 u8 rix = 0, cix, ctsrate = 0;
637 u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit;
638 struct ath_node *an = (struct ath_node *) bf->bf_node;
639
640
641
642
643 rt = sc->sc_currates;
644 for (i = 4; i--;) {
645 if (bf->bf_rcs[i].tries) {
646 rix = bf->bf_rcs[i].rix;
647 break;
648 }
649 }
650 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
651 cix = rt->info[rix].controlRate;
652
653
654
655
656
657
658 if (sc->sc_protmode != PROT_M_NONE &&
659 (rt->info[rix].phy == PHY_OFDM ||
660 rt->info[rix].phy == PHY_HT) &&
661 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
662 if (sc->sc_protmode == PROT_M_RTSCTS)
663 flags = ATH9K_TXDESC_RTSENA;
664 else if (sc->sc_protmode == PROT_M_CTSONLY)
665 flags = ATH9K_TXDESC_CTSENA;
666
667 cix = rt->info[sc->sc_protrix].controlRate;
668 rtsctsena = 1;
669 }
670
671
672
673
674
675
676 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
677 BUG_ON(!an);
678
679
680
681 if (!rtsctsena)
682 flags = ATH9K_TXDESC_RTSENA;
683
684
685
686
687 if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
688 if (!bf_isaggrburst(bf)) {
689 flags = ATH9K_TXDESC_RTSENA;
690 dynamic_mimops = 1;
691 } else {
692 flags = 0;
693 }
694 }
695 }
696
697
698
699
700 if (sc->sc_config.ath_aggr_prot &&
701 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
702 flags = ATH9K_TXDESC_RTSENA;
703 cix = rt->info[sc->sc_protrix].controlRate;
704 rtsctsena = 1;
705 }
706
707
708
709
710 if (bf_isaggr(bf) && (bf->bf_al > aggr_limit_with_rts)) {
711
712
713
714
715
716 flags &= ~(ATH9K_TXDESC_RTSENA);
717 }
718
719
720
721
722
723
724
725 BUG_ON(cix == 0xff);
726 ctsrate = rt->info[cix].rateCode |
727 (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0);
728
729
730
731
732 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
733
734 for (i = 0; i < 4; i++) {
735 if (!bf->bf_rcs[i].tries)
736 continue;
737
738 rix = bf->bf_rcs[i].rix;
739
740 series[i].Rate = rt->info[rix].rateCode |
741 (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0);
742
743 series[i].Tries = bf->bf_rcs[i].tries;
744
745 series[i].RateFlags = (
746 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
747 ATH9K_RATESERIES_RTS_CTS : 0) |
748 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
749 ATH9K_RATESERIES_2040 : 0) |
750 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
751 ATH9K_RATESERIES_HALFGI : 0);
752
753 series[i].PktDuration = ath_pkt_duration(
754 sc, rix, bf,
755 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
756 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
757 bf_isshpreamble(bf));
758
759 if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
760 (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
761
762
763
764
765
766
767
768 series[i].ChSel = sc->sc_tx_chainmask;
769 } else {
770 if (bf_isht(bf))
771 series[i].ChSel =
772 ath_chainmask_sel_logic(sc, an);
773 else
774 series[i].ChSel = sc->sc_tx_chainmask;
775 }
776
777 if (rtsctsena)
778 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
779
780
781
782
783
784 if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
785 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
786 }
787
788
789
790
791
792 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
793
794
795
796
797
798
799
800
801
802 if (flags & ATH9K_TXDESC_RTSENA) {
803 ctsduration += bf_isshpreamble(bf) ?
804 rt->info[cix].spAckDuration :
805 rt->info[cix].lpAckDuration;
806 }
807
808 ctsduration += series[0].PktDuration;
809
810 if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
811 ctsduration += bf_isshpreamble(bf) ?
812 rt->info[rix].spAckDuration :
813 rt->info[rix].lpAckDuration;
814 }
815
816
817
818
819
820 memset(&series[1], 0, sizeof(struct ath9k_11n_rate_series) * 3);
821 }
822
823
824
825
826 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
827 !bf_ispspoll(bf),
828 ctsrate,
829 ctsduration,
830 series, 4, flags);
831 if (sc->sc_config.ath_aggr_prot && flags)
832 ath9k_hw_set11n_burstduration(ah, ds, 8192);
833}
834
835
836
837
838
839
840static int ath_tx_send_normal(struct ath_softc *sc,
841 struct ath_txq *txq,
842 struct ath_atx_tid *tid,
843 struct list_head *bf_head)
844{
845 struct ath_buf *bf;
846 struct sk_buff *skb;
847 struct ieee80211_tx_info *tx_info;
848 struct ath_tx_info_priv *tx_info_priv;
849
850 BUG_ON(list_empty(bf_head));
851
852 bf = list_first_entry(bf_head, struct ath_buf, list);
853 bf->bf_state.bf_type &= ~BUF_AMPDU;
854
855 skb = (struct sk_buff *)bf->bf_mpdu;
856 tx_info = IEEE80211_SKB_CB(skb);
857 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
858 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
859
860
861 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
862
863
864 bf->bf_nframes = 1;
865 bf->bf_lastbf = bf->bf_lastfrm;
866 ath_buf_set_rate(sc, bf);
867 ath_tx_txqaddbuf(sc, txq, bf_head);
868
869 return 0;
870}
871
872
873
874static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
875{
876 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
877 struct ath_buf *bf;
878 struct list_head bf_head;
879 INIT_LIST_HEAD(&bf_head);
880
881 ASSERT(tid->paused > 0);
882 spin_lock_bh(&txq->axq_lock);
883
884 tid->paused--;
885
886 if (tid->paused > 0) {
887 spin_unlock_bh(&txq->axq_lock);
888 return;
889 }
890
891 while (!list_empty(&tid->buf_q)) {
892 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
893 ASSERT(!bf_isretried(bf));
894 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
895 ath_tx_send_normal(sc, txq, tid, &bf_head);
896 }
897
898 spin_unlock_bh(&txq->axq_lock);
899}
900
901
902
903static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
904 struct ath_txq *txq,
905 struct ath_buf *bf,
906 struct list_head *bf_q,
907 int txok)
908{
909 struct ath_node *an = bf->bf_node;
910 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
911 struct ath_buf *bf_last = bf->bf_lastbf;
912 struct ath_desc *ds = bf_last->bf_desc;
913 struct ath_buf *bf_next, *bf_lastq = NULL;
914 struct list_head bf_head, bf_pending;
915 u16 seq_st = 0;
916 u32 ba[WME_BA_BMP_SIZE >> 5];
917 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
918 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
919
920 isaggr = bf_isaggr(bf);
921 if (isaggr) {
922 if (txok) {
923 if (ATH_DS_TX_BA(ds)) {
924
925
926
927
928 seq_st = ATH_DS_BA_SEQ(ds);
929 memcpy(ba,
930 ATH_DS_BA_BITMAP(ds),
931 WME_BA_BMP_SIZE >> 3);
932 } else {
933 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
934
935
936
937
938
939
940
941
942 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
943 needreset = 1;
944 }
945 } else {
946 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
947 }
948 }
949
950 INIT_LIST_HEAD(&bf_pending);
951 INIT_LIST_HEAD(&bf_head);
952
953 while (bf) {
954 txfail = txpending = 0;
955 bf_next = bf->bf_next;
956
957 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
958
959
960 } else if (!isaggr && txok) {
961
962 } else {
963
964 if (!tid->cleanup_inprogress && !isnodegone &&
965 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
966 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
967 ath_tx_set_retry(sc, bf);
968 txpending = 1;
969 } else {
970 bf->bf_state.bf_type |= BUF_XRETRY;
971 txfail = 1;
972 sendbar = 1;
973 }
974 } else {
975
976
977
978
979 txfail = 1;
980 }
981 }
982
983
984
985 if (bf_next == NULL) {
986 ASSERT(bf->bf_lastfrm == bf_last);
987
988
989
990
991
992
993
994
995 if (!list_empty(bf_q)) {
996 bf_lastq = list_entry(bf_q->prev,
997 struct ath_buf, list);
998 list_cut_position(&bf_head,
999 bf_q, &bf_lastq->list);
1000 } else {
1001
1002
1003
1004
1005
1006
1007 INIT_LIST_HEAD(&bf_head);
1008 }
1009 } else {
1010 ASSERT(!list_empty(bf_q));
1011 list_cut_position(&bf_head,
1012 bf_q, &bf->bf_lastfrm->list);
1013 }
1014
1015 if (!txpending) {
1016
1017
1018
1019
1020 spin_lock_bh(&txq->axq_lock);
1021 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1022 spin_unlock_bh(&txq->axq_lock);
1023
1024
1025 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
1026 } else {
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036 if (bf->bf_next == NULL &&
1037 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
1038 struct ath_buf *tbf;
1039
1040
1041 spin_lock_bh(&sc->sc_txbuflock);
1042 ASSERT(!list_empty((&sc->sc_txbuf)));
1043 tbf = list_first_entry(&sc->sc_txbuf,
1044 struct ath_buf, list);
1045 list_del(&tbf->list);
1046 spin_unlock_bh(&sc->sc_txbuflock);
1047
1048 ATH_TXBUF_RESET(tbf);
1049
1050
1051 tbf->bf_mpdu = bf_last->bf_mpdu;
1052 tbf->bf_node = bf_last->bf_node;
1053 tbf->bf_buf_addr = bf_last->bf_buf_addr;
1054 *(tbf->bf_desc) = *(bf_last->bf_desc);
1055
1056
1057 if (bf_lastq) {
1058 bf_lastq->bf_desc->ds_link =
1059 tbf->bf_daddr;
1060 bf->bf_lastfrm = tbf;
1061 ath9k_hw_cleartxdesc(sc->sc_ah,
1062 bf->bf_lastfrm->bf_desc);
1063 } else {
1064 tbf->bf_state = bf_last->bf_state;
1065 tbf->bf_lastfrm = tbf;
1066 ath9k_hw_cleartxdesc(sc->sc_ah,
1067 tbf->bf_lastfrm->bf_desc);
1068
1069
1070 tbf->bf_dmacontext =
1071 bf_last->bf_dmacontext;
1072 }
1073 list_add_tail(&tbf->list, &bf_head);
1074 } else {
1075
1076
1077
1078
1079 ath9k_hw_cleartxdesc(sc->sc_ah,
1080 bf->bf_lastfrm->bf_desc);
1081 }
1082
1083
1084
1085
1086
1087 list_splice_tail_init(&bf_head, &bf_pending);
1088 }
1089
1090 bf = bf_next;
1091 }
1092
1093
1094
1095
1096
1097
1098
1099 if (isnodegone)
1100 return;
1101
1102 if (tid->cleanup_inprogress) {
1103
1104 spin_lock_bh(&txq->axq_lock);
1105
1106 if (tid->baw_head == tid->baw_tail) {
1107 tid->addba_exchangecomplete = 0;
1108 tid->addba_exchangeattempts = 0;
1109 spin_unlock_bh(&txq->axq_lock);
1110
1111 tid->cleanup_inprogress = false;
1112
1113
1114 ath_tx_flush_tid(sc, tid);
1115 } else
1116 spin_unlock_bh(&txq->axq_lock);
1117
1118 return;
1119 }
1120
1121
1122
1123
1124 if (!list_empty(&bf_pending)) {
1125 spin_lock_bh(&txq->axq_lock);
1126
1127
1128 list_splice(&bf_pending, &tid->buf_q);
1129 ath_tx_queue_tid(txq, tid);
1130 spin_unlock_bh(&txq->axq_lock);
1131 }
1132
1133 if (needreset)
1134 ath_reset(sc, false);
1135
1136 return;
1137}
1138
1139
1140
1141static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1142{
1143 struct ath_hal *ah = sc->sc_ah;
1144 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1145 struct list_head bf_head;
1146 struct ath_desc *ds, *tmp_ds;
1147 struct sk_buff *skb;
1148 struct ieee80211_tx_info *tx_info;
1149 struct ath_tx_info_priv *tx_info_priv;
1150 int nacked, txok, nbad = 0, isrifs = 0;
1151 int status;
1152
1153 DPRINTF(sc, ATH_DBG_QUEUE,
1154 "%s: tx queue %d (%x), link %p\n", __func__,
1155 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1156 txq->axq_link);
1157
1158 nacked = 0;
1159 for (;;) {
1160 spin_lock_bh(&txq->axq_lock);
1161 txq->axq_intrcnt = 0;
1162 if (list_empty(&txq->axq_q)) {
1163 txq->axq_link = NULL;
1164 txq->axq_linkbuf = NULL;
1165 spin_unlock_bh(&txq->axq_lock);
1166 break;
1167 }
1168 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178 bf_held = NULL;
1179 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1180 bf_held = bf;
1181 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1182
1183
1184
1185
1186
1187 spin_unlock_bh(&txq->axq_lock);
1188 break;
1189 } else {
1190
1191 bf = list_entry(bf_held->list.next,
1192 struct ath_buf, list);
1193 }
1194 }
1195
1196 lastbf = bf->bf_lastbf;
1197 ds = lastbf->bf_desc;
1198
1199 status = ath9k_hw_txprocdesc(ah, ds);
1200 if (status == -EINPROGRESS) {
1201 spin_unlock_bh(&txq->axq_lock);
1202 break;
1203 }
1204 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1205 txq->axq_lastdsWithCTS = NULL;
1206 if (ds == txq->axq_gatingds)
1207 txq->axq_gatingds = NULL;
1208
1209
1210
1211
1212
1213
1214 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1215 INIT_LIST_HEAD(&bf_head);
1216
1217 if (!list_is_singular(&lastbf->list))
1218 list_cut_position(&bf_head,
1219 &txq->axq_q, lastbf->list.prev);
1220
1221 txq->axq_depth--;
1222
1223 if (bf_isaggr(bf))
1224 txq->axq_aggr_depth--;
1225
1226 txok = (ds->ds_txstat.ts_status == 0);
1227
1228 spin_unlock_bh(&txq->axq_lock);
1229
1230 if (bf_held) {
1231 list_del(&bf_held->list);
1232 spin_lock_bh(&sc->sc_txbuflock);
1233 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1234 spin_unlock_bh(&sc->sc_txbuflock);
1235 }
1236
1237 if (!bf_isampdu(bf)) {
1238
1239
1240
1241
1242 bf->bf_retries = ds->ds_txstat.ts_longretry;
1243 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1244 bf->bf_state.bf_type |= BUF_XRETRY;
1245 nbad = 0;
1246 } else {
1247 nbad = ath_tx_num_badfrms(sc, bf, txok);
1248 }
1249 skb = bf->bf_mpdu;
1250 tx_info = IEEE80211_SKB_CB(skb);
1251 tx_info_priv = (struct ath_tx_info_priv *)
1252 tx_info->driver_data[0];
1253 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1254 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1255 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1256 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1257 if (ds->ds_txstat.ts_status == 0)
1258 nacked++;
1259
1260 if (bf_isdata(bf)) {
1261 if (isrifs)
1262 tmp_ds = bf->bf_rifslast->bf_desc;
1263 else
1264 tmp_ds = ds;
1265 memcpy(&tx_info_priv->tx,
1266 &tmp_ds->ds_txstat,
1267 sizeof(tx_info_priv->tx));
1268 tx_info_priv->n_frames = bf->bf_nframes;
1269 tx_info_priv->n_bad_frames = nbad;
1270 }
1271 }
1272
1273
1274
1275
1276 if (bf_isampdu(bf))
1277 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1278 else
1279 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1280
1281
1282
1283 spin_lock_bh(&txq->axq_lock);
1284 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1285 (ATH_TXBUF - 20)) {
1286 int qnum;
1287 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1288 if (qnum != -1) {
1289 ieee80211_wake_queue(sc->hw, qnum);
1290 txq->stopped = 0;
1291 }
1292
1293 }
1294
1295
1296
1297
1298 if (sc->sc_flags & SC_OP_TXAGGR)
1299 ath_txq_schedule(sc, txq);
1300 spin_unlock_bh(&txq->axq_lock);
1301 }
1302 return nacked;
1303}
1304
1305static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1306{
1307 struct ath_hal *ah = sc->sc_ah;
1308
1309 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1310 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1311 __func__, txq->axq_qnum,
1312 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1313}
1314
1315
1316
1317static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1318{
1319 struct ath_hal *ah = sc->sc_ah;
1320 int i;
1321 int npend = 0;
1322
1323
1324 if (!(sc->sc_flags & SC_OP_INVALID)) {
1325 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1326 if (ATH_TXQ_SETUP(sc, i)) {
1327 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1328
1329
1330
1331 npend += ath9k_hw_numtxpending(ah,
1332 sc->sc_txq[i].axq_qnum);
1333 }
1334 }
1335 }
1336
1337 if (npend) {
1338 int status;
1339
1340
1341 DPRINTF(sc, ATH_DBG_XMIT,
1342 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1343
1344 spin_lock_bh(&sc->sc_resetlock);
1345 if (!ath9k_hw_reset(ah,
1346 sc->sc_ah->ah_curchan,
1347 sc->sc_ht_info.tx_chan_width,
1348 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1349 sc->sc_ht_extprotspacing, true, &status)) {
1350
1351 DPRINTF(sc, ATH_DBG_FATAL,
1352 "%s: unable to reset hardware; hal status %u\n",
1353 __func__,
1354 status);
1355 }
1356 spin_unlock_bh(&sc->sc_resetlock);
1357 }
1358
1359 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1360 if (ATH_TXQ_SETUP(sc, i))
1361 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1362 }
1363}
1364
1365
1366
1367static void ath_tx_addto_baw(struct ath_softc *sc,
1368 struct ath_atx_tid *tid,
1369 struct ath_buf *bf)
1370{
1371 int index, cindex;
1372
1373 if (bf_isretried(bf))
1374 return;
1375
1376 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1377 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1378
1379 ASSERT(tid->tx_buf[cindex] == NULL);
1380 tid->tx_buf[cindex] = bf;
1381
1382 if (index >= ((tid->baw_tail - tid->baw_head) &
1383 (ATH_TID_MAX_BUFS - 1))) {
1384 tid->baw_tail = cindex;
1385 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1386 }
1387}
1388
1389
1390
1391
1392
1393
1394static int ath_tx_send_ampdu(struct ath_softc *sc,
1395 struct ath_txq *txq,
1396 struct ath_atx_tid *tid,
1397 struct list_head *bf_head,
1398 struct ath_tx_control *txctl)
1399{
1400 struct ath_buf *bf;
1401 struct sk_buff *skb;
1402 struct ieee80211_tx_info *tx_info;
1403 struct ath_tx_info_priv *tx_info_priv;
1404
1405 BUG_ON(list_empty(bf_head));
1406
1407 bf = list_first_entry(bf_head, struct ath_buf, list);
1408 bf->bf_state.bf_type |= BUF_AMPDU;
1409 bf->bf_seqno = txctl->seqno;
1410 bf->bf_tidno = txctl->tidno;
1411
1412
1413
1414
1415
1416
1417
1418
1419 if (!list_empty(&tid->buf_q) || tid->paused ||
1420 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1421 txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1422
1423
1424
1425
1426 list_splice_tail_init(bf_head, &tid->buf_q);
1427 ath_tx_queue_tid(txq, tid);
1428 return 0;
1429 }
1430
1431 skb = (struct sk_buff *)bf->bf_mpdu;
1432 tx_info = IEEE80211_SKB_CB(skb);
1433 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1434 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1435
1436
1437 ath_tx_addto_baw(sc, tid, bf);
1438
1439
1440 bf->bf_nframes = 1;
1441 bf->bf_lastbf = bf->bf_lastfrm;
1442 ath_buf_set_rate(sc, bf);
1443 ath_tx_txqaddbuf(sc, txq, bf_head);
1444 return 0;
1445}
1446
1447
1448
1449
1450
1451
1452static u32 ath_lookup_rate(struct ath_softc *sc,
1453 struct ath_buf *bf)
1454{
1455 const struct ath9k_rate_table *rt = sc->sc_currates;
1456 struct sk_buff *skb;
1457 struct ieee80211_tx_info *tx_info;
1458 struct ath_tx_info_priv *tx_info_priv;
1459 u32 max_4ms_framelen, frame_length;
1460 u16 aggr_limit, legacy = 0, maxampdu;
1461 int i;
1462
1463
1464 skb = (struct sk_buff *)bf->bf_mpdu;
1465 tx_info = IEEE80211_SKB_CB(skb);
1466 tx_info_priv = (struct ath_tx_info_priv *)
1467 tx_info->driver_data[0];
1468 memcpy(bf->bf_rcs,
1469 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1470
1471
1472
1473
1474
1475
1476 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1477
1478 for (i = 0; i < 4; i++) {
1479 if (bf->bf_rcs[i].tries) {
1480 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1481
1482 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1483 legacy = 1;
1484 break;
1485 }
1486
1487 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1488 }
1489 }
1490
1491
1492
1493
1494
1495
1496 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1497 return 0;
1498
1499 aggr_limit = min(max_4ms_framelen,
1500 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1501
1502
1503
1504
1505
1506
1507 maxampdu = sc->sc_ht_info.maxampdu;
1508 if (maxampdu)
1509 aggr_limit = min(aggr_limit, maxampdu);
1510
1511 return aggr_limit;
1512}
1513
1514
1515
1516
1517
1518
1519
1520static int ath_compute_num_delims(struct ath_softc *sc,
1521 struct ath_buf *bf,
1522 u16 frmlen)
1523{
1524 const struct ath9k_rate_table *rt = sc->sc_currates;
1525 u32 nsymbits, nsymbols, mpdudensity;
1526 u16 minlen;
1527 u8 rc, flags, rix;
1528 int width, half_gi, ndelim, mindelim;
1529
1530
1531 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1532
1533
1534
1535
1536
1537
1538
1539 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1540 ndelim += ATH_AGGR_ENCRYPTDELIM;
1541
1542
1543
1544
1545
1546
1547
1548 mpdudensity = sc->sc_ht_info.mpdudensity;
1549
1550
1551
1552
1553
1554 if (mpdudensity == 0)
1555 return ndelim;
1556
1557 rix = bf->bf_rcs[0].rix;
1558 flags = bf->bf_rcs[0].flags;
1559 rc = rt->info[rix].rateCode;
1560 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1561 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1562
1563 if (half_gi)
1564 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1565 else
1566 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1567
1568 if (nsymbols == 0)
1569 nsymbols = 1;
1570
1571 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1572 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1573
1574
1575 if (frmlen < minlen) {
1576
1577 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1578 ndelim = max(mindelim, ndelim);
1579 }
1580
1581 return ndelim;
1582}
1583
1584
1585
1586
1587
1588
1589static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1590 struct ath_atx_tid *tid,
1591 struct list_head *bf_q,
1592 struct ath_buf **bf_last,
1593 struct aggr_rifs_param *param,
1594 int *prev_frames)
1595{
1596#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1597 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1598 struct list_head bf_head;
1599 int rl = 0, nframes = 0, ndelim;
1600 u16 aggr_limit = 0, al = 0, bpad = 0,
1601 al_delta, h_baw = tid->baw_size / 2;
1602 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1603 int prev_al = 0, is_ds_rate = 0;
1604 INIT_LIST_HEAD(&bf_head);
1605
1606 BUG_ON(list_empty(&tid->buf_q));
1607
1608 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1609
1610 do {
1611 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1612
1613
1614
1615
1616 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1617 status = ATH_AGGR_BAW_CLOSED;
1618 break;
1619 }
1620
1621 if (!rl) {
1622 aggr_limit = ath_lookup_rate(sc, bf);
1623 rl = 1;
1624
1625
1626
1627 is_ds_rate =
1628 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1629 }
1630
1631
1632
1633
1634 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1635
1636 if (nframes && (aggr_limit <
1637 (al + bpad + al_delta + prev_al))) {
1638 status = ATH_AGGR_LIMITED;
1639 break;
1640 }
1641
1642
1643
1644
1645 if ((nframes + *prev_frames) >=
1646 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1647 status = ATH_AGGR_LIMITED;
1648 break;
1649 }
1650
1651
1652
1653
1654 al += bpad + al_delta;
1655
1656
1657
1658
1659
1660 ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_frmlen);
1661
1662 bpad = PADBYTES(al_delta) + (ndelim << 2);
1663
1664 bf->bf_next = NULL;
1665 bf->bf_lastfrm->bf_desc->ds_link = 0;
1666
1667
1668
1669
1670
1671
1672
1673
1674 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1675 ath_tx_addto_baw(sc, tid, bf);
1676
1677 list_for_each_entry(tbf, &bf_head, list) {
1678 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1679 tbf->bf_desc, ndelim);
1680 }
1681
1682
1683
1684
1685 list_splice_tail_init(&bf_head, bf_q);
1686 nframes++;
1687
1688 if (bf_prev) {
1689 bf_prev->bf_next = bf;
1690 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1691 }
1692 bf_prev = bf;
1693
1694#ifdef AGGR_NOSHORT
1695
1696
1697
1698 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1699 status = ATH_AGGR_SHORTPKT;
1700 break;
1701 }
1702#endif
1703 } while (!list_empty(&tid->buf_q));
1704
1705 bf_first->bf_al = al;
1706 bf_first->bf_nframes = nframes;
1707 *bf_last = bf_prev;
1708 return status;
1709#undef PADBYTES
1710}
1711
1712
1713
1714
1715
1716
1717static void ath_tx_sched_aggr(struct ath_softc *sc,
1718 struct ath_txq *txq, struct ath_atx_tid *tid)
1719{
1720 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1721 enum ATH_AGGR_STATUS status;
1722 struct list_head bf_q;
1723 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1724 int prev_frames = 0;
1725
1726 do {
1727 if (list_empty(&tid->buf_q))
1728 return;
1729
1730 INIT_LIST_HEAD(&bf_q);
1731
1732 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, ¶m,
1733 &prev_frames);
1734
1735
1736
1737
1738
1739 if (list_empty(&bf_q))
1740 break;
1741
1742 bf = list_first_entry(&bf_q, struct ath_buf, list);
1743 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1744 bf->bf_lastbf = bf_last;
1745
1746
1747
1748
1749 if (bf->bf_nframes == 1) {
1750 ASSERT(bf->bf_lastfrm == bf_last);
1751
1752 bf->bf_state.bf_type &= ~BUF_AGGR;
1753
1754
1755
1756
1757 list_for_each_entry(tbf, &bf_q, list) {
1758 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1759 }
1760
1761 ath_buf_set_rate(sc, bf);
1762 ath_tx_txqaddbuf(sc, txq, &bf_q);
1763 continue;
1764 }
1765
1766
1767
1768
1769 bf->bf_state.bf_type |= BUF_AGGR;
1770 ath_buf_set_rate(sc, bf);
1771 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1772
1773
1774
1775
1776 ASSERT(bf_lastaggr);
1777 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1778 tbf = bf_lastaggr;
1779 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1780
1781
1782 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1783 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1784 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1785 }
1786
1787 txq->axq_aggr_depth++;
1788
1789
1790
1791
1792 ath_tx_txqaddbuf(sc, txq, &bf_q);
1793
1794 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1795 status != ATH_AGGR_BAW_CLOSED);
1796}
1797
1798
1799
1800static void ath_tid_drain(struct ath_softc *sc,
1801 struct ath_txq *txq,
1802 struct ath_atx_tid *tid,
1803 bool bh_flag)
1804{
1805 struct ath_buf *bf;
1806 struct list_head bf_head;
1807 INIT_LIST_HEAD(&bf_head);
1808
1809 for (;;) {
1810 if (list_empty(&tid->buf_q))
1811 break;
1812 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1813
1814 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1815
1816
1817 if (bf_isretried(bf))
1818 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1819
1820
1821
1822
1823
1824 if (likely(bh_flag))
1825 spin_unlock_bh(&txq->axq_lock);
1826 else
1827 spin_unlock(&txq->axq_lock);
1828
1829
1830 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1831
1832 if (likely(bh_flag))
1833 spin_lock_bh(&txq->axq_lock);
1834 else
1835 spin_lock(&txq->axq_lock);
1836 }
1837
1838
1839
1840
1841
1842
1843
1844 tid->seq_next = tid->seq_start;
1845 tid->baw_tail = tid->baw_head;
1846}
1847
1848
1849
1850
1851
1852
1853static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1854 struct ath_txq *txq,
1855 bool bh_flag)
1856{
1857 struct ath_atx_ac *ac, *ac_tmp;
1858 struct ath_atx_tid *tid, *tid_tmp;
1859
1860 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1861 list_del(&ac->list);
1862 ac->sched = false;
1863 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1864 list_del(&tid->list);
1865 tid->sched = false;
1866 ath_tid_drain(sc, txq, tid, bh_flag);
1867 }
1868 }
1869}
1870
1871static int ath_tx_start_dma(struct ath_softc *sc,
1872 struct sk_buff *skb,
1873 struct scatterlist *sg,
1874 u32 n_sg,
1875 struct ath_tx_control *txctl)
1876{
1877 struct ath_node *an = txctl->an;
1878 struct ath_buf *bf = NULL;
1879 struct list_head bf_head;
1880 struct ath_desc *ds;
1881 struct ath_hal *ah = sc->sc_ah;
1882 struct ath_txq *txq;
1883 struct ath_tx_info_priv *tx_info_priv;
1884 struct ath_rc_series *rcs;
1885 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1886 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1887 __le16 fc = hdr->frame_control;
1888
1889 if (unlikely(txctl->flags & ATH9K_TXDESC_CAB))
1890 txq = sc->sc_cabq;
1891 else
1892 txq = &sc->sc_txq[txctl->qnum];
1893
1894
1895 INIT_LIST_HEAD(&bf_head);
1896 spin_lock_bh(&sc->sc_txbuflock);
1897 if (unlikely(list_empty(&sc->sc_txbuf))) {
1898 spin_unlock_bh(&sc->sc_txbuflock);
1899 return -ENOMEM;
1900 }
1901
1902 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
1903 list_del(&bf->list);
1904 spin_unlock_bh(&sc->sc_txbuflock);
1905
1906 list_add_tail(&bf->list, &bf_head);
1907
1908
1909 ATH_TXBUF_RESET(bf);
1910 bf->bf_frmlen = txctl->frmlen;
1911
1912 ieee80211_is_data(fc) ?
1913 (bf->bf_state.bf_type |= BUF_DATA) :
1914 (bf->bf_state.bf_type &= ~BUF_DATA);
1915 ieee80211_is_back_req(fc) ?
1916 (bf->bf_state.bf_type |= BUF_BAR) :
1917 (bf->bf_state.bf_type &= ~BUF_BAR);
1918 ieee80211_is_pspoll(fc) ?
1919 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1920 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
1921 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
1922 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1923 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1924
1925 bf->bf_flags = txctl->flags;
1926 bf->bf_keytype = txctl->keytype;
1927 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1928 rcs = tx_info_priv->rcs;
1929 bf->bf_rcs[0] = rcs[0];
1930 bf->bf_rcs[1] = rcs[1];
1931 bf->bf_rcs[2] = rcs[2];
1932 bf->bf_rcs[3] = rcs[3];
1933 bf->bf_node = an;
1934 bf->bf_mpdu = skb;
1935 bf->bf_buf_addr = sg_dma_address(sg);
1936
1937
1938 ds = bf->bf_desc;
1939 ds->ds_link = 0;
1940 ds->ds_data = bf->bf_buf_addr;
1941
1942
1943
1944
1945 bf->bf_dmacontext = txctl->dmacontext;
1946
1947
1948
1949
1950 ath9k_hw_set11n_txdesc(ah,
1951 ds,
1952 bf->bf_frmlen,
1953 txctl->atype,
1954 min(txctl->txpower, (u16)60),
1955 txctl->keyix,
1956 txctl->keytype,
1957 txctl->flags);
1958 ath9k_hw_filltxdesc(ah,
1959 ds,
1960 sg_dma_len(sg),
1961 true,
1962 (n_sg == 1) ? true : false,
1963 ds);
1964
1965 bf->bf_lastfrm = bf;
1966 (txctl->ht) ?
1967 (bf->bf_state.bf_type |= BUF_HT) :
1968 (bf->bf_state.bf_type &= ~BUF_HT);
1969
1970 spin_lock_bh(&txq->axq_lock);
1971
1972 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
1973 struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno);
1974 if (ath_aggr_query(sc, an, txctl->tidno)) {
1975
1976
1977
1978
1979 ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl);
1980 } else {
1981
1982
1983
1984
1985 ath_tx_send_normal(sc, txq, tid, &bf_head);
1986 }
1987 } else {
1988 bf->bf_lastbf = bf;
1989 bf->bf_nframes = 1;
1990 ath_buf_set_rate(sc, bf);
1991
1992 if (ieee80211_is_back_req(fc)) {
1993
1994
1995 bf->bf_tidno = txctl->tidno;
1996 }
1997
1998 ath_tx_txqaddbuf(sc, txq, &bf_head);
1999 }
2000 spin_unlock_bh(&txq->axq_lock);
2001 return 0;
2002}
2003
2004static void xmit_map_sg(struct ath_softc *sc,
2005 struct sk_buff *skb,
2006 struct ath_tx_control *txctl)
2007{
2008 struct ath_xmit_status tx_status;
2009 struct ath_atx_tid *tid;
2010 struct scatterlist sg;
2011
2012 txctl->dmacontext = pci_map_single(sc->pdev, skb->data,
2013 skb->len, PCI_DMA_TODEVICE);
2014
2015
2016 memset(&sg, 0, sizeof(struct scatterlist));
2017 sg_dma_address(&sg) = txctl->dmacontext;
2018 sg_dma_len(&sg) = skb->len;
2019
2020 if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) {
2021
2022
2023
2024 pci_unmap_single(sc->pdev, txctl->dmacontext,
2025 skb->len, PCI_DMA_TODEVICE);
2026
2027 tx_status.retries = 0;
2028 tx_status.flags = ATH_TX_ERROR;
2029
2030 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
2031
2032 tid = ATH_AN_2_TID((struct ath_node *)
2033 txctl->an, txctl->tidno);
2034 DECR(tid->seq_next, IEEE80211_SEQ_MAX);
2035 }
2036 ath_tx_complete(sc, skb, &tx_status, txctl->an);
2037 }
2038}
2039
2040
2041
2042int ath_tx_init(struct ath_softc *sc, int nbufs)
2043{
2044 int error = 0;
2045
2046 do {
2047 spin_lock_init(&sc->sc_txbuflock);
2048
2049
2050 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2051 "tx", nbufs, 1);
2052 if (error != 0) {
2053 DPRINTF(sc, ATH_DBG_FATAL,
2054 "%s: failed to allocate tx descriptors: %d\n",
2055 __func__, error);
2056 break;
2057 }
2058
2059
2060 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2061 "beacon", ATH_BCBUF, 1);
2062 if (error != 0) {
2063 DPRINTF(sc, ATH_DBG_FATAL,
2064 "%s: failed to allocate "
2065 "beacon descripotrs: %d\n",
2066 __func__, error);
2067 break;
2068 }
2069
2070 } while (0);
2071
2072 if (error != 0)
2073 ath_tx_cleanup(sc);
2074
2075 return error;
2076}
2077
2078
2079
2080int ath_tx_cleanup(struct ath_softc *sc)
2081{
2082
2083 if (sc->sc_bdma.dd_desc_len != 0)
2084 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2085
2086
2087 if (sc->sc_txdma.dd_desc_len != 0)
2088 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2089
2090 return 0;
2091}
2092
2093
2094
2095struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2096{
2097 struct ath_hal *ah = sc->sc_ah;
2098 struct ath9k_tx_queue_info qi;
2099 int qnum;
2100
2101 memset(&qi, 0, sizeof(qi));
2102 qi.tqi_subtype = subtype;
2103 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
2104 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
2105 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
2106 qi.tqi_physCompBuf = 0;
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123 if (qtype == ATH9K_TX_QUEUE_UAPSD)
2124 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2125 else
2126 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2127 TXQ_FLAG_TXDESCINT_ENABLE;
2128 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2129 if (qnum == -1) {
2130
2131
2132
2133
2134 return NULL;
2135 }
2136 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2137 DPRINTF(sc, ATH_DBG_FATAL,
2138 "%s: hal qnum %u out of range, max %u!\n",
2139 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2140 ath9k_hw_releasetxqueue(ah, qnum);
2141 return NULL;
2142 }
2143 if (!ATH_TXQ_SETUP(sc, qnum)) {
2144 struct ath_txq *txq = &sc->sc_txq[qnum];
2145
2146 txq->axq_qnum = qnum;
2147 txq->axq_link = NULL;
2148 INIT_LIST_HEAD(&txq->axq_q);
2149 INIT_LIST_HEAD(&txq->axq_acq);
2150 spin_lock_init(&txq->axq_lock);
2151 txq->axq_depth = 0;
2152 txq->axq_aggr_depth = 0;
2153 txq->axq_totalqueued = 0;
2154 txq->axq_intrcnt = 0;
2155 txq->axq_linkbuf = NULL;
2156 sc->sc_txqsetup |= 1<<qnum;
2157 }
2158 return &sc->sc_txq[qnum];
2159}
2160
2161
2162
2163void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2164{
2165 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2166 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2167}
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179int ath_tx_setup(struct ath_softc *sc, int haltype)
2180{
2181 struct ath_txq *txq;
2182
2183 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2184 DPRINTF(sc, ATH_DBG_FATAL,
2185 "%s: HAL AC %u out of range, max %zu!\n",
2186 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2187 return 0;
2188 }
2189 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
2190 if (txq != NULL) {
2191 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2192 return 1;
2193 } else
2194 return 0;
2195}
2196
2197int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2198{
2199 int qnum;
2200
2201 switch (qtype) {
2202 case ATH9K_TX_QUEUE_DATA:
2203 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2204 DPRINTF(sc, ATH_DBG_FATAL,
2205 "%s: HAL AC %u out of range, max %zu!\n",
2206 __func__,
2207 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2208 return -1;
2209 }
2210 qnum = sc->sc_haltype2q[haltype];
2211 break;
2212 case ATH9K_TX_QUEUE_BEACON:
2213 qnum = sc->sc_bhalq;
2214 break;
2215 case ATH9K_TX_QUEUE_CAB:
2216 qnum = sc->sc_cabq->axq_qnum;
2217 break;
2218 default:
2219 qnum = -1;
2220 }
2221 return qnum;
2222}
2223
2224
2225
2226int ath_txq_update(struct ath_softc *sc, int qnum,
2227 struct ath9k_tx_queue_info *qinfo)
2228{
2229 struct ath_hal *ah = sc->sc_ah;
2230 int error = 0;
2231 struct ath9k_tx_queue_info qi;
2232
2233 if (qnum == sc->sc_bhalq) {
2234
2235
2236
2237
2238
2239 sc->sc_beacon_qi = *qinfo;
2240 return 0;
2241 }
2242
2243 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2244
2245 ath9k_hw_get_txq_props(ah, qnum, &qi);
2246 qi.tqi_aifs = qinfo->tqi_aifs;
2247 qi.tqi_cwmin = qinfo->tqi_cwmin;
2248 qi.tqi_cwmax = qinfo->tqi_cwmax;
2249 qi.tqi_burstTime = qinfo->tqi_burstTime;
2250 qi.tqi_readyTime = qinfo->tqi_readyTime;
2251
2252 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2253 DPRINTF(sc, ATH_DBG_FATAL,
2254 "%s: unable to update hardware queue %u!\n",
2255 __func__, qnum);
2256 error = -EIO;
2257 } else {
2258 ath9k_hw_resettxqueue(ah, qnum);
2259 }
2260
2261 return error;
2262}
2263
2264int ath_cabq_update(struct ath_softc *sc)
2265{
2266 struct ath9k_tx_queue_info qi;
2267 int qnum = sc->sc_cabq->axq_qnum;
2268 struct ath_beacon_config conf;
2269
2270 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
2271
2272
2273
2274 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2275 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2276 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2277 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2278
2279 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2280 qi.tqi_readyTime =
2281 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2282 ath_txq_update(sc, qnum, &qi);
2283
2284 return 0;
2285}
2286
2287int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
2288{
2289 struct ath_tx_control txctl;
2290 int error = 0;
2291
2292 memset(&txctl, 0, sizeof(struct ath_tx_control));
2293 error = ath_tx_prepare(sc, skb, &txctl);
2294 if (error == 0)
2295
2296
2297
2298
2299
2300 xmit_map_sg(sc, skb, &txctl);
2301 else
2302 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2303
2304
2305 return error;
2306}
2307
2308
2309
2310void ath_tx_tasklet(struct ath_softc *sc)
2311{
2312 int i;
2313 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2314
2315 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2316
2317
2318
2319
2320 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2321 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2322 ath_tx_processq(sc, &sc->sc_txq[i]);
2323 }
2324}
2325
2326void ath_tx_draintxq(struct ath_softc *sc,
2327 struct ath_txq *txq, bool retry_tx)
2328{
2329 struct ath_buf *bf, *lastbf;
2330 struct list_head bf_head;
2331
2332 INIT_LIST_HEAD(&bf_head);
2333
2334
2335
2336
2337
2338 for (;;) {
2339 spin_lock_bh(&txq->axq_lock);
2340
2341 if (list_empty(&txq->axq_q)) {
2342 txq->axq_link = NULL;
2343 txq->axq_linkbuf = NULL;
2344 spin_unlock_bh(&txq->axq_lock);
2345 break;
2346 }
2347
2348 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2349
2350 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2351 list_del(&bf->list);
2352 spin_unlock_bh(&txq->axq_lock);
2353
2354 spin_lock_bh(&sc->sc_txbuflock);
2355 list_add_tail(&bf->list, &sc->sc_txbuf);
2356 spin_unlock_bh(&sc->sc_txbuflock);
2357 continue;
2358 }
2359
2360 lastbf = bf->bf_lastbf;
2361 if (!retry_tx)
2362 lastbf->bf_desc->ds_txstat.ts_flags =
2363 ATH9K_TX_SW_ABORTED;
2364
2365
2366 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2367 txq->axq_depth--;
2368
2369 spin_unlock_bh(&txq->axq_lock);
2370
2371 if (bf_isampdu(bf))
2372 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2373 else
2374 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2375 }
2376
2377
2378 if (sc->sc_flags & SC_OP_TXAGGR) {
2379 if (!retry_tx) {
2380 spin_lock_bh(&txq->axq_lock);
2381 ath_txq_drain_pending_buffers(sc, txq,
2382 ATH9K_BH_STATUS_CHANGE);
2383 spin_unlock_bh(&txq->axq_lock);
2384 }
2385 }
2386}
2387
2388
2389
2390void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2391{
2392
2393
2394 if (!(sc->sc_flags & SC_OP_INVALID)) {
2395 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2396 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2397 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2398 }
2399
2400 ath_drain_txdataq(sc, retry_tx);
2401}
2402
2403u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2404{
2405 return sc->sc_txq[qnum].axq_depth;
2406}
2407
2408u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2409{
2410 return sc->sc_txq[qnum].axq_aggr_depth;
2411}
2412
2413
2414enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
2415 struct ath_node *an,
2416 u8 tidno)
2417{
2418 struct ath_atx_tid *txtid;
2419 DECLARE_MAC_BUF(mac);
2420
2421 if (!(sc->sc_flags & SC_OP_TXAGGR))
2422 return AGGR_NOT_REQUIRED;
2423
2424
2425 txtid = ATH_AN_2_TID(an, tidno);
2426
2427 if (txtid->addba_exchangecomplete)
2428 return AGGR_EXCHANGE_DONE;
2429
2430 if (txtid->cleanup_inprogress)
2431 return AGGR_CLEANUP_PROGRESS;
2432
2433 if (txtid->addba_exchangeinprogress)
2434 return AGGR_EXCHANGE_PROGRESS;
2435
2436 if (!txtid->addba_exchangecomplete) {
2437 if (!txtid->addba_exchangeinprogress &&
2438 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2439 txtid->addba_exchangeattempts++;
2440 return AGGR_REQUIRED;
2441 }
2442 }
2443
2444 return AGGR_NOT_REQUIRED;
2445}
2446
2447
2448
2449int ath_tx_aggr_start(struct ath_softc *sc,
2450 const u8 *addr,
2451 u16 tid,
2452 u16 *ssn)
2453{
2454 struct ath_atx_tid *txtid;
2455 struct ath_node *an;
2456
2457 spin_lock_bh(&sc->node_lock);
2458 an = ath_node_find(sc, (u8 *) addr);
2459 spin_unlock_bh(&sc->node_lock);
2460
2461 if (!an) {
2462 DPRINTF(sc, ATH_DBG_AGGR,
2463 "%s: Node not found to initialize "
2464 "TX aggregation\n", __func__);
2465 return -1;
2466 }
2467
2468 if (sc->sc_flags & SC_OP_TXAGGR) {
2469 txtid = ATH_AN_2_TID(an, tid);
2470 txtid->addba_exchangeinprogress = 1;
2471 ath_tx_pause_tid(sc, txtid);
2472 }
2473
2474 return 0;
2475}
2476
2477
2478
2479int ath_tx_aggr_stop(struct ath_softc *sc,
2480 const u8 *addr,
2481 u16 tid)
2482{
2483 struct ath_node *an;
2484
2485 spin_lock_bh(&sc->node_lock);
2486 an = ath_node_find(sc, (u8 *) addr);
2487 spin_unlock_bh(&sc->node_lock);
2488
2489 if (!an) {
2490 DPRINTF(sc, ATH_DBG_AGGR,
2491 "%s: TX aggr stop for non-existent node\n", __func__);
2492 return -1;
2493 }
2494
2495 ath_tx_aggr_teardown(sc, an, tid);
2496 return 0;
2497}
2498
2499
2500
2501
2502
2503
2504
2505
2506void ath_tx_aggr_teardown(struct ath_softc *sc,
2507 struct ath_node *an, u8 tid)
2508{
2509 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2510 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2511 struct ath_buf *bf;
2512 struct list_head bf_head;
2513 INIT_LIST_HEAD(&bf_head);
2514
2515 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2516
2517 if (txtid->cleanup_inprogress)
2518 return;
2519
2520 if (!txtid->addba_exchangecomplete) {
2521 txtid->addba_exchangeattempts = 0;
2522 return;
2523 }
2524
2525
2526 ath_tx_pause_tid(sc, txtid);
2527
2528
2529 spin_lock_bh(&txq->axq_lock);
2530 while (!list_empty(&txtid->buf_q)) {
2531 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2532 if (!bf_isretried(bf)) {
2533
2534
2535
2536
2537
2538 break;
2539 }
2540 list_cut_position(&bf_head,
2541 &txtid->buf_q, &bf->bf_lastfrm->list);
2542 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2543
2544
2545 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2546 }
2547
2548 if (txtid->baw_head != txtid->baw_tail) {
2549 spin_unlock_bh(&txq->axq_lock);
2550 txtid->cleanup_inprogress = true;
2551 } else {
2552 txtid->addba_exchangecomplete = 0;
2553 txtid->addba_exchangeattempts = 0;
2554 spin_unlock_bh(&txq->axq_lock);
2555 ath_tx_flush_tid(sc, txtid);
2556 }
2557}
2558
2559
2560
2561
2562
2563
2564void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2565{
2566 struct ath_atx_ac *ac;
2567 struct ath_atx_tid *tid;
2568
2569
2570 if (list_empty(&txq->axq_acq))
2571 return;
2572
2573
2574
2575 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2576 list_del(&ac->list);
2577 ac->sched = false;
2578
2579
2580
2581
2582 do {
2583
2584 if (list_empty(&ac->tid_q))
2585 return;
2586
2587 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2588 list_del(&tid->list);
2589 tid->sched = false;
2590
2591 if (tid->paused)
2592 continue;
2593
2594 if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) ||
2595 ((txq->axq_depth % 2) == 0)) {
2596 ath_tx_sched_aggr(sc, txq, tid);
2597 }
2598
2599
2600
2601
2602
2603 if (!list_empty(&tid->buf_q))
2604 ath_tx_queue_tid(txq, tid);
2605
2606
2607 break;
2608 } while (!list_empty(&ac->tid_q));
2609
2610
2611
2612
2613 if (!list_empty(&ac->tid_q)) {
2614
2615
2616
2617 if (!ac->sched) {
2618 ac->sched = true;
2619 list_add_tail(&ac->list, &txq->axq_acq);
2620 }
2621 }
2622}
2623
2624
2625
2626void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2627{
2628 if (sc->sc_flags & SC_OP_TXAGGR) {
2629 struct ath_atx_tid *tid;
2630 struct ath_atx_ac *ac;
2631 int tidno, acno;
2632
2633 sc->sc_ht_info.maxampdu = ATH_AMPDU_LIMIT_DEFAULT;
2634
2635
2636
2637
2638 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2639 tidno < WME_NUM_TID;
2640 tidno++, tid++) {
2641 tid->an = an;
2642 tid->tidno = tidno;
2643 tid->seq_start = tid->seq_next = 0;
2644 tid->baw_size = WME_MAX_BA;
2645 tid->baw_head = tid->baw_tail = 0;
2646 tid->sched = false;
2647 tid->paused = false;
2648 tid->cleanup_inprogress = false;
2649 INIT_LIST_HEAD(&tid->buf_q);
2650
2651 acno = TID_TO_WME_AC(tidno);
2652 tid->ac = &an->an_aggr.tx.ac[acno];
2653
2654
2655 tid->addba_exchangecomplete = 0;
2656 tid->addba_exchangeinprogress = 0;
2657 tid->addba_exchangeattempts = 0;
2658 }
2659
2660
2661
2662
2663 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2664 acno < WME_NUM_AC; acno++, ac++) {
2665 ac->sched = false;
2666 INIT_LIST_HEAD(&ac->tid_q);
2667
2668 switch (acno) {
2669 case WME_AC_BE:
2670 ac->qnum = ath_tx_get_qnum(sc,
2671 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2672 break;
2673 case WME_AC_BK:
2674 ac->qnum = ath_tx_get_qnum(sc,
2675 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2676 break;
2677 case WME_AC_VI:
2678 ac->qnum = ath_tx_get_qnum(sc,
2679 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2680 break;
2681 case WME_AC_VO:
2682 ac->qnum = ath_tx_get_qnum(sc,
2683 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2684 break;
2685 }
2686 }
2687 }
2688}
2689
2690
2691
2692void ath_tx_node_cleanup(struct ath_softc *sc,
2693 struct ath_node *an, bool bh_flag)
2694{
2695 int i;
2696 struct ath_atx_ac *ac, *ac_tmp;
2697 struct ath_atx_tid *tid, *tid_tmp;
2698 struct ath_txq *txq;
2699 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2700 if (ATH_TXQ_SETUP(sc, i)) {
2701 txq = &sc->sc_txq[i];
2702
2703 if (likely(bh_flag))
2704 spin_lock_bh(&txq->axq_lock);
2705 else
2706 spin_lock(&txq->axq_lock);
2707
2708 list_for_each_entry_safe(ac,
2709 ac_tmp, &txq->axq_acq, list) {
2710 tid = list_first_entry(&ac->tid_q,
2711 struct ath_atx_tid, list);
2712 if (tid && tid->an != an)
2713 continue;
2714 list_del(&ac->list);
2715 ac->sched = false;
2716
2717 list_for_each_entry_safe(tid,
2718 tid_tmp, &ac->tid_q, list) {
2719 list_del(&tid->list);
2720 tid->sched = false;
2721 ath_tid_drain(sc, txq, tid, bh_flag);
2722 tid->addba_exchangecomplete = 0;
2723 tid->addba_exchangeattempts = 0;
2724 tid->cleanup_inprogress = false;
2725 }
2726 }
2727
2728 if (likely(bh_flag))
2729 spin_unlock_bh(&txq->axq_lock);
2730 else
2731 spin_unlock(&txq->axq_lock);
2732 }
2733 }
2734}
2735
2736
2737
2738void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an)
2739{
2740 if (sc->sc_flags & SC_OP_TXAGGR) {
2741 struct ath_atx_tid *tid;
2742 int tidno, i;
2743
2744
2745 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2746 tidno < WME_NUM_TID;
2747 tidno++, tid++) {
2748
2749 for (i = 0; i < ATH_TID_MAX_BUFS; i++)
2750 ASSERT(tid->tx_buf[i] == NULL);
2751 }
2752 }
2753}
2754
2755void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2756{
2757 int hdrlen, padsize;
2758 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2759 struct ath_tx_control txctl;
2760
2761
2762
2763
2764
2765
2766 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2767 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2768 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2769 sc->seq_no += 0x10;
2770 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2771 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2772 }
2773
2774
2775 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2776 if (hdrlen & 3) {
2777 padsize = hdrlen % 4;
2778 if (skb_headroom(skb) < padsize) {
2779 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding "
2780 "failed\n", __func__);
2781 dev_kfree_skb_any(skb);
2782 return;
2783 }
2784 skb_push(skb, padsize);
2785 memmove(skb->data, skb->data + padsize, hdrlen);
2786 }
2787
2788 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
2789 __func__,
2790 skb);
2791
2792 memset(&txctl, 0, sizeof(struct ath_tx_control));
2793 txctl.flags = ATH9K_TXDESC_CAB;
2794 if (ath_tx_prepare(sc, skb, &txctl) == 0) {
2795
2796
2797
2798
2799
2800 xmit_map_sg(sc, skb, &txctl);
2801 } else {
2802 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2803 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ failed\n", __func__);
2804 dev_kfree_skb_any(skb);
2805 }
2806}
2807